[SCSI] Documentation/devicetree: Add DT bindings for UFS host controller
[linux-3.10.git] / drivers / mmc / host / sdhci.c
1 /*
2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3  *
4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5  *  Copyright (C) 2012-2015, NVIDIA CORPORATION.  All rights reserved.
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or (at
10  * your option) any later version.
11  *
12  * Thanks to the following companies for their support:
13  *
14  *     - JMicron (hardware and technical support)
15  */
16
17 #include <linux/delay.h>
18 #include <linux/highmem.h>
19 #include <linux/io.h>
20 #include <linux/module.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/slab.h>
23 #include <linux/scatterlist.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/platform_device.h>
27 #include <linux/sched.h>
28
29 #include <linux/leds.h>
30
31 #include <linux/mmc/mmc.h>
32 #include <linux/mmc/host.h>
33 #include <linux/mmc/card.h>
34 #include <linux/mmc/slot-gpio.h>
35
36 #include <linux/sysedp.h>
37 #ifdef CONFIG_DEBUG_FS
38 #include <linux/debugfs.h>
39 #include <linux/ktime.h>
40 #endif
41
42 #ifdef CONFIG_EMMC_BLKTRACE
43 #include <linux/mmc/emmc-trace.h>
44 #include "../card/queue.h"
45 #endif
46 #include "sdhci.h"
47
48 #define DRIVER_NAME "sdhci"
49
50 #define DBG(f, x...) \
51         pr_debug(DRIVER_NAME " [%s()]: " f, __func__, ## x)
52 #define MMC_CHECK_CMDQ_MODE(host)                       \
53         (host && host->mmc &&                                   \
54         host->mmc->card &&                                              \
55         host->mmc->card->ext_csd.cmdq_mode_en)
56
57 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
58         defined(CONFIG_MMC_SDHCI_MODULE))
59 #define SDHCI_USE_LEDS_CLASS
60 #endif
61
62 #define MAX_TUNING_LOOP 40
63
64 #ifdef CONFIG_CMD_DUMP
65 static volatile unsigned int printk_cpu_test = UINT_MAX;
66 struct timeval cur_tv;
67 struct timeval prev_tv, curr_tv;
68 void mmc_cmd_dump(struct mmc_host *host);
69 void dbg_add_host_log(struct mmc_host *host, int type, int cmd, int arg)
70 {
71         unsigned long long t;
72         unsigned long long nanosec_rem;
73         unsigned long flags;
74         spin_lock_irqsave(&host->cmd_dump_lock, flags);
75
76         if (host->dbg_run_host_log_dat[host->dbg_host_cnt - 1].type == type &&
77                 host->dbg_run_host_log_dat[host->dbg_host_cnt - 1].cmd == cmd &&
78                 host->dbg_run_host_log_dat[host->dbg_host_cnt - 1].arg == arg) {
79                 spin_unlock_irqrestore(&host->cmd_dump_lock, flags);
80                 return;
81         }
82         t = cpu_clock(printk_cpu_test);
83         nanosec_rem = do_div(t, 1000000000)/1000;
84         do_gettimeofday(&cur_tv);
85         host->dbg_run_host_log_dat[host->dbg_host_cnt].time_sec = t;
86         host->dbg_run_host_log_dat[host->dbg_host_cnt].time_usec = nanosec_rem;
87         host->dbg_run_host_log_dat[host->dbg_host_cnt].type = type;
88         host->dbg_run_host_log_dat[host->dbg_host_cnt].cmd = cmd;
89         host->dbg_run_host_log_dat[host->dbg_host_cnt].arg = arg;
90         host->dbg_host_cnt++;
91         if (host->dbg_host_cnt >= dbg_max_cnt)
92                 host->dbg_host_cnt = 0;
93         spin_unlock_irqrestore(&host->cmd_dump_lock, flags);
94 }
95 #endif
96
97 /* MMC_RTPM timeout */
98 #define MMC_RTPM_MSEC_TMOUT 10
99
100 /* SDIO 1msec timeout, but use 10msec timeout for HZ=100 */
101 #define SDIO_CLK_GATING_TICK_TMOUT ((HZ >= 1000) ? (HZ / 1000) : 1)
102 /* 20msec EMMC delayed clock gate timeout */
103 #define EMMC_CLK_GATING_TICK_TMOUT ((HZ >= 50) ? (HZ / 50) : 2)
104
105 #define IS_SDIO_CARD(host) \
106                 (host->mmc->card && \
107                 (host->mmc->card->type == MMC_TYPE_SDIO))
108
109 #define IS_EMMC_CARD(host) \
110                 (host->mmc->card && \
111                 (host->mmc->card->type == MMC_TYPE_MMC))
112
113 #define IS_SDIO_CARD_OR_EMMC(host) \
114                 (host->mmc->card && \
115                 ((host->mmc->card->type == MMC_TYPE_SDIO) || \
116                 (host->mmc->card->type == MMC_TYPE_MMC)))
117
118 #define IS_DELAYED_CLK_GATE(host) \
119                 ((host->quirks2 & SDHCI_QUIRK2_DELAYED_CLK_GATE) && \
120                 (IS_SDIO_CARD_OR_EMMC(host)) && \
121                 (host->mmc->caps2 & MMC_CAP2_CLOCK_GATING))
122
123 #ifdef CONFIG_DEBUG_FS
124
125 #define IS_32_BIT(x)    (x < (1ULL << 32))
126
127 #define IS_DATA_READ(flags)     ((flags & MMC_DATA_READ) ? true : false)
128
129 #define PERF_STAT_COMPARE(stat, blk_size, blk_count, is_read) \
130                 ( \
131                         (stat->is_read == is_read) && \
132                         (stat->stat_blk_size == blk_size) && \
133                         (stat->stat_blks_per_transfer == blk_count) \
134                 )
135
136 #endif
137
138 #define MIN_SDMMC_FREQ 400000
139
140 static unsigned int debug_quirks;
141 static unsigned int debug_quirks2;
142
143 static void sdhci_finish_data(struct sdhci_host *);
144
145 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
146 static void sdhci_finish_command(struct sdhci_host *);
147 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
148 static int sdhci_validate_sd2_0(struct mmc_host *mmc);
149 static void sdhci_tuning_timer(unsigned long data);
150 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
151
152 #ifdef CONFIG_PM_RUNTIME
153 static int sdhci_runtime_pm_get(struct sdhci_host *host);
154 static int sdhci_runtime_pm_put(struct sdhci_host *host);
155 #else
156 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
157 {
158         return 0;
159 }
160 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
161 {
162         return 0;
163 }
164 static inline int sdhci_runtime_resume_host(struct sdhci_host *host)
165 {
166         return 0;
167 }
168 static inline int sdhci_runtime_suspend_host(struct sdhci_host *host)
169 {
170         return 0;
171 }
172 #endif
173
174 static void sdhci_dumpregs(struct sdhci_host *host)
175 {
176         pr_err(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
177                 mmc_hostname(host->mmc));
178
179         pr_err(DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
180                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
181                 sdhci_readw(host, SDHCI_HOST_VERSION));
182         pr_err(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
183                 sdhci_readw(host, SDHCI_BLOCK_SIZE),
184                 sdhci_readw(host, SDHCI_BLOCK_COUNT));
185         pr_err(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
186                 sdhci_readl(host, SDHCI_ARGUMENT),
187                 sdhci_readw(host, SDHCI_TRANSFER_MODE));
188         pr_err(DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
189                 sdhci_readl(host, SDHCI_PRESENT_STATE),
190                 sdhci_readb(host, SDHCI_HOST_CONTROL));
191         pr_err(DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
192                 sdhci_readb(host, SDHCI_POWER_CONTROL),
193                 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
194         pr_err(DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
195                 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
196                 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
197         pr_err(DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
198                 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
199                 sdhci_readl(host, SDHCI_INT_STATUS));
200         pr_err(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
201                 sdhci_readl(host, SDHCI_INT_ENABLE),
202                 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
203         pr_err(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
204                 sdhci_readw(host, SDHCI_ACMD12_ERR),
205                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
206         pr_err(DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
207                 sdhci_readl(host, SDHCI_CAPABILITIES),
208                 sdhci_readl(host, SDHCI_CAPABILITIES_1));
209         pr_err(DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
210                 sdhci_readw(host, SDHCI_COMMAND),
211                 sdhci_readl(host, SDHCI_MAX_CURRENT));
212         pr_err(DRIVER_NAME ": Host ctl2: 0x%08x\n",
213                 sdhci_readw(host, SDHCI_HOST_CONTROL2));
214
215         if (host->flags & SDHCI_USE_ADMA)
216                 pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
217                        readl(host->ioaddr + SDHCI_ADMA_ERROR),
218                        readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
219
220         if (host->ops->dump_host_cust_regs)
221                 host->ops->dump_host_cust_regs(host);
222
223         pr_err(DRIVER_NAME ": ===========================================\n");
224 }
225
226 /*****************************************************************************\
227  *                                                                           *
228  * Low level functions                                                       *
229  *                                                                           *
230 \*****************************************************************************/
231
232 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
233 {
234         host->ier &= ~clear;
235         host->ier |= set;
236         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
237         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
238 }
239
240 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
241 {
242         sdhci_clear_set_irqs(host, 0, irqs);
243 }
244
245 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
246 {
247         sdhci_clear_set_irqs(host, irqs, 0);
248 }
249
250 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
251 {
252         u32 present, irqs;
253
254         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
255             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
256                 return;
257
258         present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
259                               SDHCI_CARD_PRESENT;
260         irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
261
262         if (enable)
263                 sdhci_unmask_irqs(host, irqs);
264         else
265                 sdhci_mask_irqs(host, irqs);
266 }
267
268 static void sdhci_enable_card_detection(struct sdhci_host *host)
269 {
270         sdhci_set_card_detection(host, true);
271 }
272
273 static void sdhci_disable_card_detection(struct sdhci_host *host)
274 {
275         sdhci_set_card_detection(host, false);
276 }
277
278 static void sdhci_reset(struct sdhci_host *host, u8 mask)
279 {
280         u32 ctrl;
281         unsigned long timeout;
282
283         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
284                 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
285                         SDHCI_CARD_PRESENT))
286                         return;
287         }
288
289         if (host->ops->platform_reset_enter)
290                 host->ops->platform_reset_enter(host, mask);
291
292         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
293
294         if (mask & SDHCI_RESET_ALL)
295                 host->clock = 0;
296
297         /* Wait max 100 ms */
298         timeout = 100;
299
300         /* hw clears the bit when it's done */
301         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
302                 if (timeout == 0) {
303                         pr_err("%s: Reset 0x%x never completed.\n",
304                                 mmc_hostname(host->mmc), (int)mask);
305                         sdhci_dumpregs(host);
306                         return;
307                 }
308                 timeout--;
309                 mdelay(1);
310         }
311
312         if (host->ops->platform_reset_exit)
313                 host->ops->platform_reset_exit(host, mask);
314
315         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
316                 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, host->ier);
317
318         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
319                 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
320                         host->ops->enable_dma(host);
321         }
322
323         /*
324          * VERSION_4_EN bit and 64BIT_EN bit are cleared after a full reset
325          * need to re-configure them after each full reset
326          */
327         if ((mask & SDHCI_RESET_ALL) && host->version >= SDHCI_SPEC_400) {
328                 ctrl = sdhci_readl(host, SDHCI_ACMD12_ERR);
329                 ctrl |= SDHCI_HOST_VERSION_4_EN;
330                 if (host->quirks2 & SDHCI_QUIRK2_SUPPORT_64BIT_DMA)
331                         ctrl |= SDHCI_ADDRESSING_64BIT_EN;
332                 sdhci_writel(host, ctrl, SDHCI_ACMD12_ERR);
333         }
334 }
335
336 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
337
338 static void sdhci_init(struct sdhci_host *host, int soft)
339 {
340         if (soft)
341                 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
342         else
343                 sdhci_reset(host, SDHCI_RESET_ALL);
344
345         sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
346                 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
347                 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
348                 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
349                 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
350
351         if (soft) {
352                 /* force clock reconfiguration */
353                 host->clock = 0;
354                 sdhci_set_ios(host->mmc, &host->mmc->ios);
355         }
356 }
357
358 static void sdhci_reinit(struct sdhci_host *host)
359 {
360         sdhci_init(host, 0);
361         /*
362          * Retuning stuffs are affected by different cards inserted and only
363          * applicable to UHS-I cards. So reset these fields to their initial
364          * value when card is removed.
365          */
366         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
367                 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
368
369                 del_timer_sync(&host->tuning_timer);
370                 host->flags &= ~SDHCI_NEEDS_RETUNING;
371                 host->mmc->max_blk_count =
372                         (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
373         }
374         sdhci_enable_card_detection(host);
375 }
376
377 static void sdhci_activate_led(struct sdhci_host *host)
378 {
379         u8 ctrl;
380
381         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
382         ctrl |= SDHCI_CTRL_LED;
383         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
384 }
385
386 static void sdhci_deactivate_led(struct sdhci_host *host)
387 {
388         u8 ctrl;
389
390         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
391         ctrl &= ~SDHCI_CTRL_LED;
392         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
393 }
394
395 #ifdef SDHCI_USE_LEDS_CLASS
396 static void sdhci_led_control(struct led_classdev *led,
397         enum led_brightness brightness)
398 {
399         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
400         unsigned long flags;
401
402         spin_lock_irqsave(&host->lock, flags);
403
404         if (host->runtime_suspended)
405                 goto out;
406
407         if (brightness == LED_OFF)
408                 sdhci_deactivate_led(host);
409         else
410                 sdhci_activate_led(host);
411 out:
412         spin_unlock_irqrestore(&host->lock, flags);
413 }
414 #endif
415
416 /*****************************************************************************\
417  *                                                                           *
418  * Core functions                                                            *
419  *                                                                           *
420 \*****************************************************************************/
421
422 static void sdhci_read_block_pio(struct sdhci_host *host)
423 {
424         unsigned long flags;
425         size_t blksize, len, chunk;
426         u32 uninitialized_var(scratch);
427         u8 *buf;
428
429         DBG("PIO reading\n");
430
431         blksize = host->data->blksz;
432         chunk = 0;
433
434         local_irq_save(flags);
435
436         while (blksize) {
437                 if (!sg_miter_next(&host->sg_miter))
438                         BUG();
439
440                 len = min(host->sg_miter.length, blksize);
441
442                 blksize -= len;
443                 host->sg_miter.consumed = len;
444
445                 buf = host->sg_miter.addr;
446
447                 while (len) {
448                         if (chunk == 0) {
449                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
450                                 chunk = 4;
451                         }
452
453                         *buf = scratch & 0xFF;
454
455                         buf++;
456                         scratch >>= 8;
457                         chunk--;
458                         len--;
459                 }
460         }
461
462         sg_miter_stop(&host->sg_miter);
463
464         local_irq_restore(flags);
465 }
466
467 static void sdhci_write_block_pio(struct sdhci_host *host)
468 {
469         unsigned long flags;
470         size_t blksize, len, chunk;
471         u32 scratch;
472         u8 *buf;
473
474         DBG("PIO writing\n");
475
476         blksize = host->data->blksz;
477         chunk = 0;
478         scratch = 0;
479
480         local_irq_save(flags);
481
482         while (blksize) {
483                 if (!sg_miter_next(&host->sg_miter))
484                         BUG();
485
486                 len = min(host->sg_miter.length, blksize);
487
488                 blksize -= len;
489                 host->sg_miter.consumed = len;
490
491                 buf = host->sg_miter.addr;
492
493                 while (len) {
494                         scratch |= (u32)*buf << (chunk * 8);
495
496                         buf++;
497                         chunk++;
498                         len--;
499
500                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
501                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
502                                 chunk = 0;
503                                 scratch = 0;
504                         }
505                 }
506         }
507
508         sg_miter_stop(&host->sg_miter);
509
510         local_irq_restore(flags);
511 }
512
513 static void sdhci_transfer_pio(struct sdhci_host *host)
514 {
515         u32 mask;
516
517         BUG_ON(!host->data);
518
519         if (host->data->flags & MMC_DATA_READ)
520                 mask = SDHCI_DATA_AVAILABLE;
521         else
522                 mask = SDHCI_SPACE_AVAILABLE;
523
524         /*
525          * Some controllers (JMicron JMB38x) mess up the buffer bits
526          * for transfers < 4 bytes. As long as it is just one block,
527          * we can ignore the bits.
528          */
529         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
530                 (host->data->blocks == 1))
531                 mask = ~0;
532
533         /*
534          * Start the transfer if the present state register indicates
535          * SDHCI_DATA_AVAILABLE or SDHCI_SPACE_AVAILABLE. The driver should
536          * transfer one complete block of data and wait for the buffer ready
537          * interrupt to transfer the next block of data.
538          */
539         if (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
540                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
541                         udelay(100);
542
543                 if (host->data->flags & MMC_DATA_READ)
544                         sdhci_read_block_pio(host);
545                 else
546                         sdhci_write_block_pio(host);
547         }
548
549         DBG("PIO transfer complete.\n");
550 }
551
552 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
553 {
554         local_irq_save(*flags);
555         return kmap_atomic(sg_page(sg)) + sg->offset;
556 }
557
558 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
559 {
560         kunmap_atomic(buffer);
561         local_irq_restore(*flags);
562 }
563
564 static void sdhci_set_adma_desc(struct sdhci_host *host, u8 *desc,
565                                 dma_addr_t addr, int len, unsigned cmd)
566 {
567         __le32 *dataddr = (__le32 __force *)(desc + 4);
568         __le64 *dataddr64 = (__le64 __force *)(desc + 4);
569         __le16 *cmdlen = (__le16 __force *)desc;
570         u32 ctrl;
571
572         /* SDHCI specification says ADMA descriptors should be 4 byte
573          * aligned, so using 16 or 32bit operations should be safe. */
574
575         cmdlen[0] = cpu_to_le16(cmd);
576         cmdlen[1] = cpu_to_le16(len);
577
578         ctrl = sdhci_readl(host, SDHCI_ACMD12_ERR);
579         if (ctrl & SDHCI_ADDRESSING_64BIT_EN)
580                 dataddr64[0] = cpu_to_le64(addr);
581         else
582                 dataddr[0] = cpu_to_le32(addr);
583 }
584
585 static int sdhci_adma_table_pre(struct sdhci_host *host,
586         struct mmc_data *data)
587 {
588         int direction;
589
590         u8 *desc;
591         u8 *align;
592         dma_addr_t addr;
593         dma_addr_t align_addr;
594         int len, offset;
595
596         struct scatterlist *sg;
597         int i;
598         char *buffer;
599         unsigned long flags;
600         int next_desc;
601         u32 ctrl;
602
603         /*
604          * The spec does not specify endianness of descriptor table.
605          * We currently guess that it is LE.
606          */
607
608         if (data->flags & MMC_DATA_READ)
609                 direction = DMA_FROM_DEVICE;
610         else
611                 direction = DMA_TO_DEVICE;
612
613         /*
614          * The ADMA descriptor table is mapped further down as we
615          * need to fill it with data first.
616          */
617
618         if (!host->use_dma_alloc) {
619                 host->align_addr = dma_map_single(mmc_dev(host->mmc),
620                         host->align_buffer, 128 * 8, direction);
621                 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
622                         goto fail;
623                 BUG_ON(host->align_addr & 0x3);
624         }
625
626         host->sg_count = dma_map_sg(mmc_dev(host->mmc),
627                 data->sg, data->sg_len, direction);
628         if (host->sg_count == 0)
629                 goto unmap_align;
630
631         desc = host->adma_desc;
632         align = host->align_buffer;
633
634         align_addr = host->align_addr;
635
636         ctrl = sdhci_readl(host, SDHCI_ACMD12_ERR);
637         if (ctrl & SDHCI_ADDRESSING_64BIT_EN) {
638                 if (ctrl & SDHCI_HOST_VERSION_4_EN)
639                         next_desc = 16;
640                 else
641                         next_desc = 12;
642         } else {
643                 /* 32 bit DMA mode supported */
644                 next_desc = 8;
645         }
646
647         for_each_sg(data->sg, sg, host->sg_count, i) {
648                 addr = sg_dma_address(sg);
649                 len = sg_dma_len(sg);
650
651                 /*
652                  * The SDHCI specification states that ADMA
653                  * addresses must be 32-bit aligned. If they
654                  * aren't, then we use a bounce buffer for
655                  * the (up to three) bytes that screw up the
656                  * alignment.
657                  */
658                 offset = (4 - (addr & 0x3)) & 0x3;
659                 if (offset) {
660                         if (data->flags & MMC_DATA_WRITE) {
661                                 buffer = sdhci_kmap_atomic(sg, &flags);
662                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
663                                 memcpy(align, buffer, offset);
664                                 sdhci_kunmap_atomic(buffer, &flags);
665                         }
666
667                         /* tran, valid */
668                         sdhci_set_adma_desc(host, desc, align_addr, offset,
669                                                 0x21);
670
671                         BUG_ON(offset > 65536);
672
673                         align += 4;
674                         align_addr += 4;
675
676                         desc += next_desc;
677
678                         addr += offset;
679                         len -= offset;
680                 }
681
682                 BUG_ON(len > 65536);
683
684                 /* tran, valid */
685                 if (len > 0) {
686                         sdhci_set_adma_desc(host, desc, addr, len, 0x21);
687                         desc += next_desc;
688                 }
689
690                 /*
691                  * If this triggers then we have a calculation bug
692                  * somewhere. :/
693                  */
694                 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 8);
695         }
696
697         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
698                 /*
699                 * Mark the last descriptor as the terminating descriptor
700                 */
701                 if (desc != host->adma_desc) {
702                         desc -= next_desc;
703                         desc[0] |= 0x3; /* end and valid*/
704                 }
705         } else {
706                 /*
707                 * Add a terminating entry.
708                 */
709
710                 /* nop, end, valid */
711                 sdhci_set_adma_desc(host, desc, 0, 0, 0x3);
712         }
713
714         /*
715          * Resync align buffer as we might have changed it.
716          */
717         if (data->flags & MMC_DATA_WRITE) {
718                 dma_sync_single_for_device(mmc_dev(host->mmc),
719                         host->align_addr, 128 * 8, direction);
720         }
721
722         if (!host->use_dma_alloc) {
723                 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
724                         host->adma_desc, (128 * 2 + 1) * 8, DMA_TO_DEVICE);
725                 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
726                         goto unmap_entries;
727                 BUG_ON(host->adma_addr & 0x3);
728         }
729
730         return 0;
731
732 unmap_entries:
733         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
734                 data->sg_len, direction);
735 unmap_align:
736         if (!host->use_dma_alloc)
737                 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
738                                 128 * 8, direction);
739 fail:
740         return -EINVAL;
741 }
742
743 static void sdhci_adma_table_post(struct sdhci_host *host,
744         struct mmc_data *data)
745 {
746         int direction;
747
748         struct scatterlist *sg;
749         int i, size;
750         u8 *align;
751         char *buffer;
752         unsigned long flags;
753
754         if (data->flags & MMC_DATA_READ)
755                 direction = DMA_FROM_DEVICE;
756         else
757                 direction = DMA_TO_DEVICE;
758
759         if (!host->use_dma_alloc) {
760                 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
761                         (128 * 2 + 1) * 8, DMA_TO_DEVICE);
762
763                 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
764                         128 * 8, direction);
765         }
766
767         if (data->flags & MMC_DATA_READ) {
768                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
769                         data->sg_len, direction);
770
771                 align = host->align_buffer;
772
773                 for_each_sg(data->sg, sg, host->sg_count, i) {
774                         if (sg_dma_address(sg) & 0x3) {
775                                 size = 4 - (sg_dma_address(sg) & 0x3);
776
777                                 buffer = sdhci_kmap_atomic(sg, &flags);
778                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
779                                 memcpy(buffer, align, size);
780                                 sdhci_kunmap_atomic(buffer, &flags);
781
782                                 align += 4;
783                         }
784                 }
785         }
786
787         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
788                 data->sg_len, direction);
789 }
790
791 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
792 {
793         u8 count;
794         struct mmc_data *data = cmd->data;
795         unsigned target_timeout, current_timeout;
796
797         /*
798          * If the host controller provides us with an incorrect timeout
799          * value, just skip the check and use 0xE.  The hardware may take
800          * longer to time out, but that's much better than having a too-short
801          * timeout value.
802          */
803         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
804                 return 0xE;
805
806         /* Unspecified timeout, assume max */
807         if (!data && !cmd->cmd_timeout_ms)
808                 return 0xE;
809
810         /* timeout in us */
811         if (!data)
812                 target_timeout = cmd->cmd_timeout_ms * 1000;
813         else {
814                 target_timeout = data->timeout_ns / 1000;
815                 if (host->clock)
816                         target_timeout += data->timeout_clks / host->clock;
817         }
818
819         /*
820          * Figure out needed cycles.
821          * We do this in steps in order to fit inside a 32 bit int.
822          * The first step is the minimum timeout, which will have a
823          * minimum resolution of 6 bits:
824          * (1) 2^13*1000 > 2^22,
825          * (2) host->timeout_clk < 2^16
826          *     =>
827          *     (1) / (2) > 2^6
828          */
829         count = 0;
830         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
831         while (current_timeout < target_timeout) {
832                 count++;
833                 current_timeout <<= 1;
834                 if (count >= 0xF)
835                         break;
836         }
837
838         if (count >= 0xF) {
839                 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
840                     mmc_hostname(host->mmc), count, cmd->opcode);
841                 count = 0xE;
842         }
843
844         return count;
845 }
846
847 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
848 {
849         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
850         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
851
852         if (host->flags & SDHCI_REQ_USE_DMA)
853                 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
854         else
855                 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
856 }
857
858 static void sdhci_determine_transfer_mode(struct sdhci_host *host,
859         unsigned int req_size, unsigned int req_blocks)
860 {
861         /* Nothing to do if DMA modes are not supported. */
862         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
863                 host->flags &= ~SDHCI_REQ_USE_DMA;
864         } else if (!host->max_pio_size || (req_size > host->max_pio_size)) {
865                 host->flags |= SDHCI_REQ_USE_DMA;
866         } else if (req_size < host->max_pio_size) {
867                 host->flags &= ~SDHCI_REQ_USE_DMA;
868                 if (host->max_pio_blocks &&
869                         (req_blocks > host->max_pio_blocks))
870                         host->flags |= SDHCI_REQ_USE_DMA;
871         }
872 }
873
874 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
875 {
876         u8 count;
877         u8 ctrl;
878         struct mmc_data *data = cmd->data;
879         int ret;
880
881         if (!MMC_CHECK_CMDQ_MODE(host))
882                 WARN_ON(host->data);
883
884         if (data || (cmd->flags & MMC_RSP_BUSY)) {
885                 count = sdhci_calc_timeout(host, cmd);
886                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
887         }
888
889         if (!data)
890                 return;
891
892         /* Sanity checks */
893         BUG_ON(data->blksz * data->blocks > 524288);
894         BUG_ON(data->blksz > host->mmc->max_blk_size);
895         BUG_ON(data->blocks > 65535);
896
897         host->data = data;
898         host->data_early = 0;
899         host->data->bytes_xfered = 0;
900
901         /* Select dma or PIO mode for transfer */
902         sdhci_determine_transfer_mode(host, data->blksz * data->blocks,
903                 data->blocks);
904
905         /*
906          * FIXME: This doesn't account for merging when mapping the
907          * scatterlist.
908          */
909         if (host->flags & SDHCI_REQ_USE_DMA) {
910                 int broken, i;
911                 struct scatterlist *sg;
912
913                 broken = 0;
914                 if (host->flags & SDHCI_USE_ADMA) {
915                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
916                                 broken = 1;
917                 } else {
918                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
919                                 broken = 1;
920                 }
921
922                 if (unlikely(broken)) {
923                         for_each_sg(data->sg, sg, data->sg_len, i) {
924                                 if (sg->length & 0x3) {
925                                         DBG("Reverting to PIO because of "
926                                                 "transfer size (%d)\n",
927                                                 sg->length);
928                                         host->flags &= ~SDHCI_REQ_USE_DMA;
929                                         break;
930                                 }
931                         }
932                 }
933         }
934
935         /*
936          * The assumption here being that alignment is the same after
937          * translation to device address space.
938          */
939         if (host->flags & SDHCI_REQ_USE_DMA) {
940                 int broken, i;
941                 struct scatterlist *sg;
942
943                 broken = 0;
944                 if (host->flags & SDHCI_USE_ADMA) {
945                         /*
946                          * As we use 3 byte chunks to work around
947                          * alignment problems, we need to check this
948                          * quirk.
949                          */
950                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
951                                 broken = 1;
952                 } else {
953                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
954                                 broken = 1;
955                 }
956
957                 if (unlikely(broken)) {
958                         for_each_sg(data->sg, sg, data->sg_len, i) {
959                                 if (sg->offset & 0x3) {
960                                         DBG("Reverting to PIO because of "
961                                                 "bad alignment\n");
962                                         host->flags &= ~SDHCI_REQ_USE_DMA;
963                                         break;
964                                 }
965                         }
966                 }
967         }
968
969         if (host->flags & SDHCI_REQ_USE_DMA) {
970                 if (host->flags & SDHCI_USE_ADMA) {
971                         ret = sdhci_adma_table_pre(host, data);
972                         if (ret) {
973                                 /*
974                                  * This only happens when someone fed
975                                  * us an invalid request.
976                                  */
977                                 WARN_ON(1);
978                                 host->flags &= ~SDHCI_REQ_USE_DMA;
979                         } else {
980                                 sdhci_writel(host,
981                                         (host->adma_addr & 0xFFFFFFFF),
982                                         SDHCI_ADMA_ADDRESS);
983
984                                 if ((host->version >= SDHCI_SPEC_400) &&
985                                     (host->quirks2 &
986                                      SDHCI_QUIRK2_SUPPORT_64BIT_DMA)) {
987                                         if (host->quirks2 &
988                                             SDHCI_QUIRK2_USE_64BIT_ADDR) {
989
990                                                 sdhci_writel(host,
991                                                 (host->adma_addr >> 32)
992                                                         & 0xFFFFFFFF,
993                                                 SDHCI_UPPER_ADMA_ADDRESS);
994                                         } else {
995                                                 sdhci_writel(host, 0,
996                                                 SDHCI_UPPER_ADMA_ADDRESS);
997                                         }
998                                 }
999                         }
1000                 } else {
1001                         int sg_cnt;
1002
1003                         sg_cnt = dma_map_sg(mmc_dev(host->mmc),
1004                                         data->sg, data->sg_len,
1005                                         (data->flags & MMC_DATA_READ) ?
1006                                                 DMA_FROM_DEVICE :
1007                                                 DMA_TO_DEVICE);
1008                         if (sg_cnt == 0) {
1009                                 /*
1010                                  * This only happens when someone fed
1011                                  * us an invalid request.
1012                                  */
1013                                 WARN_ON(1);
1014                                 host->flags &= ~SDHCI_REQ_USE_DMA;
1015                         } else {
1016                                 WARN_ON(sg_cnt != 1);
1017                                 sdhci_writel(host, sg_dma_address(data->sg),
1018                                         SDHCI_DMA_ADDRESS);
1019                         }
1020                 }
1021         }
1022
1023         /*
1024          * Always adjust the DMA selection as some controllers
1025          * (e.g. JMicron) can't do PIO properly when the selection
1026          * is ADMA.
1027          */
1028         if (host->version >= SDHCI_SPEC_200) {
1029                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1030                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
1031                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
1032                         (host->flags & SDHCI_USE_ADMA))
1033                         ctrl |= SDHCI_CTRL_ADMA2;
1034                 else
1035                         ctrl |= SDHCI_CTRL_SDMA;
1036                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1037         }
1038
1039         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
1040                 int flags;
1041
1042                 flags = SG_MITER_ATOMIC;
1043                 if (host->data->flags & MMC_DATA_READ)
1044                         flags |= SG_MITER_TO_SG;
1045                 else
1046                         flags |= SG_MITER_FROM_SG;
1047                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1048                 host->blocks = data->blocks;
1049         }
1050
1051         sdhci_set_transfer_irqs(host);
1052
1053         /* Set the DMA boundary value and block size */
1054         sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
1055                 data->blksz), SDHCI_BLOCK_SIZE);
1056         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
1057 }
1058
1059 static void sdhci_set_transfer_mode(struct sdhci_host *host,
1060         struct mmc_command *cmd)
1061 {
1062         u16 mode;
1063         struct mmc_data *data = cmd->data;
1064
1065         if (data == NULL)
1066                 return;
1067
1068         WARN_ON(!host->data);
1069
1070         mode = SDHCI_TRNS_BLK_CNT_EN;
1071         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
1072                 mode |= SDHCI_TRNS_MULTI;
1073                 /*
1074                  * If we are sending CMD23, CMD12 never gets sent
1075                  * on successful completion (so no Auto-CMD12).
1076                  */
1077                 if (!MMC_CHECK_CMDQ_MODE(host)) {
1078                         if (!host->mrq_cmd->sbc &&
1079                                 (host->flags & SDHCI_AUTO_CMD12) &&
1080                                 mmc_op_multi(cmd->opcode))
1081                                         mode |= SDHCI_TRNS_AUTO_CMD12;
1082                         else if (host->mrq_cmd->sbc &&
1083                                 (host->flags & SDHCI_AUTO_CMD23)) {
1084                                         mode |= SDHCI_TRNS_AUTO_CMD23;
1085                                         sdhci_writel(host,
1086                                                 host->mrq_cmd->sbc->arg,
1087                                                 SDHCI_ARGUMENT2);
1088                         }
1089                 }
1090         }
1091
1092         if (data->flags & MMC_DATA_READ)
1093                 mode |= SDHCI_TRNS_READ;
1094         if (host->flags & SDHCI_REQ_USE_DMA)
1095                 mode |= SDHCI_TRNS_DMA;
1096
1097         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1098 }
1099
1100 #ifdef CONFIG_DEBUG_FS
1101 static void get_kbps_from_size_n_usec_32bit(
1102                 u32 size_in_bits_x1000, u32 time_usecs,
1103                 u32 *speed_in_kbps)
1104 {
1105         *speed_in_kbps = DIV_ROUND_CLOSEST(size_in_bits_x1000, time_usecs);
1106 }
1107
1108 static void get_kbps_from_size_n_usec_64bit(
1109                 u64 size_in_bits_x1000, u64 time_usecs,
1110                 u32 *speed_in_kbps)
1111 {
1112         int i;
1113
1114         /* convert 64 bit into 32 bits */
1115         i = 0;
1116         while (!(IS_32_BIT(size_in_bits_x1000) && IS_32_BIT(time_usecs))) {
1117                 /* shift right both the operands bytes and time */
1118                 size_in_bits_x1000 >>= 1;
1119                 time_usecs >>= 1;
1120                 i++;
1121         }
1122         if (i)
1123                 pr_debug("%s right shifted operands by %d, size=%lld, time=%lld usec\n",
1124                         __func__, i, size_in_bits_x1000, time_usecs);
1125         /* check for 32 bit operations first */
1126         get_kbps_from_size_n_usec_32bit(
1127                 (u32)size_in_bits_x1000, (u32)time_usecs,
1128                 speed_in_kbps);
1129         return;
1130 }
1131
1132 static void free_stats_nodes(struct sdhci_host *host)
1133 {
1134         struct data_stat_entry *ptr, *ptr2;
1135
1136         ptr = host->sdhci_data_stat.head;
1137         while (ptr) {
1138                 ptr2 = ptr->next;
1139                 host->sdhci_data_stat.stat_size--;
1140                 devm_kfree(host->mmc->parent, ptr);
1141                 ptr = ptr2;
1142         }
1143         if (host->sdhci_data_stat.stat_size)
1144                 pr_err("stat_size=%d after free %s\n",
1145                         host->sdhci_data_stat.stat_size,
1146                         __func__);
1147         host->sdhci_data_stat.head = NULL;
1148 }
1149
1150 static struct data_stat_entry *add_entry_sorted(struct sdhci_host *host,
1151         unsigned int blk_size, unsigned int blk_count,
1152         unsigned int data_flags)
1153 {
1154         struct data_stat_entry *node, *ptr;
1155         bool is_read;
1156
1157         if (!blk_count) {
1158                 pr_err("%s %s: call blk_size=%d, blk_count=%d, data_flags=0x%x\n",
1159                         mmc_hostname(host->mmc), __func__,
1160                         blk_size, blk_count, data_flags);
1161                 goto end;
1162         }
1163
1164         node = devm_kzalloc(host->mmc->parent, sizeof(struct data_stat_entry),
1165                 GFP_KERNEL);
1166         if (!node) {
1167                 pr_err("%s, %s, line=%d %s: unable to allocate data_stat_entry\n",
1168                         __FILE__, __func__, __LINE__, mmc_hostname(host->mmc));
1169                 goto end;
1170         }
1171         node->stat_blk_size = blk_size;
1172         node->stat_blks_per_transfer = blk_count;
1173         is_read = IS_DATA_READ(data_flags);
1174         node->is_read = is_read;
1175         host->sdhci_data_stat.stat_size++;
1176         /* assume existing list is sorted and try to insert this new node
1177          * into the increasing order sorted array
1178          */
1179         ptr = host->sdhci_data_stat.head;
1180         if (!ptr) {
1181                 /* first element */
1182                 host->sdhci_data_stat.head = node;
1183                 return node;
1184         }
1185         if (ptr && ((ptr->stat_blk_size > blk_size) ||
1186                 ((ptr->stat_blk_size == blk_size) &&
1187                 (ptr->stat_blks_per_transfer > blk_count)))) {
1188                 host->sdhci_data_stat.head = node;
1189                 /* update new head */
1190                 node->next = ptr;
1191                 return node;
1192         }
1193         while (ptr->next) {
1194                 if ((ptr->next->stat_blk_size < blk_size) ||
1195                         ((ptr->next->stat_blk_size == blk_size) &&
1196                         (ptr->next->stat_blks_per_transfer < blk_count)))
1197                         ptr = ptr->next;
1198                 else
1199                         break;
1200         }
1201         /* We are here if -
1202          * 1. ptr->next is null or
1203          * 2. blk_size of ptr->next is greater than new blk size, so we should
1204          *    place the new node between ptr and ptr->next
1205          */
1206         if (!ptr->next) {
1207                 ptr->next = node;
1208                 return node;
1209         }
1210         if ((ptr->next->stat_blk_size > blk_size) ||
1211                 ((ptr->next->stat_blk_size == blk_size) &&
1212                 (ptr->next->stat_blks_per_transfer > blk_count)) ||
1213                 ((ptr->next->stat_blk_size == blk_size) &&
1214                 (ptr->next->stat_blks_per_transfer == blk_count) &&
1215                 (ptr->next->is_read != is_read))) {
1216                 node->next = ptr->next;
1217                 ptr->next = node;
1218                 return node;
1219         }
1220         pr_err("%s %s: line=%d should be unreachable ptr-next->blk_size=%d, blks_per_xfer=%d, is_read=%d, new blk_size=%d, blks_per_xfer=%d, data_flags=0x%x\n",
1221                 mmc_hostname(host->mmc), __func__, __LINE__,
1222                 ptr->next->stat_blk_size, ptr->next->stat_blks_per_transfer,
1223                 ptr->next->is_read, blk_size, blk_count, data_flags);
1224 end:
1225         return NULL;
1226 }
1227
1228 static void free_data_entry(struct sdhci_host *host,
1229                                 unsigned int blk_size, unsigned int blk_count,
1230                                 unsigned int data_flags)
1231 {
1232         struct data_stat_entry *ptr, *ptr2;
1233         bool is_read;
1234
1235         ptr = host->sdhci_data_stat.head;
1236         if (!ptr)
1237                 return;
1238         is_read = IS_DATA_READ(data_flags);
1239         if (PERF_STAT_COMPARE(ptr, blk_size, blk_count, is_read)) {
1240                 host->sdhci_data_stat.head = ptr->next;
1241                 devm_kfree(host->mmc->parent, ptr);
1242                 host->sdhci_data_stat.stat_size--;
1243                 return;
1244         }
1245         while (ptr->next) {
1246                 if (PERF_STAT_COMPARE(ptr->next, blk_size, blk_count,
1247                         is_read)) {
1248                         ptr2 = ptr->next->next;
1249                         devm_kfree(host->mmc->parent, ptr->next);
1250                         host->sdhci_data_stat.stat_size--;
1251                         ptr->next = ptr2;
1252                         return;
1253                 }
1254                 ptr = ptr->next;
1255         }
1256         pr_err("Error %s %s: given blk_size=%d not found\n",
1257                 mmc_hostname(host->mmc), __func__, blk_size);
1258         return;
1259 }
1260
1261 static void update_stat(struct sdhci_host *host, u32 blk_size, u32 blk_count,
1262                         bool is_start_stat, bool is_data_error,
1263                         unsigned int data_flags)
1264 {
1265         u32 new_kbps;
1266         struct data_stat_entry *stat;
1267         ktime_t t;
1268         bool is_read;
1269
1270         if (!host->enable_sdhci_perf_stats)
1271                 goto end;
1272
1273         if (!blk_count) {
1274                 pr_err("%s %s error stats case: blk_size=%d, blk_count=0, is_start_stat=%d, is_data_error=%d, data_flags=0x%x\n",
1275                         mmc_hostname(host->mmc), __func__, blk_size,
1276                         (int)is_start_stat, (int)is_data_error, data_flags);
1277                 goto end;
1278         }
1279         stat = host->sdhci_data_stat.head;
1280         is_read = IS_DATA_READ(data_flags);
1281         while (stat) {
1282                 if (PERF_STAT_COMPARE(stat, blk_size, blk_count, is_read))
1283                         break;
1284                 stat = stat->next;
1285         }
1286         /* allocation skipped in finish call */
1287         if (!stat) {
1288                 if (!is_start_stat)
1289                         goto end;
1290                 /* allocate an entry */
1291                 stat = add_entry_sorted(host, blk_size, blk_count, data_flags);
1292                 if (!stat) {
1293                         pr_err("%s %s line=%d: stat entry not found\n",
1294                                 mmc_hostname(host->mmc), __func__, __LINE__);
1295                         goto end;
1296                 }
1297         }
1298
1299         if (is_start_stat) {
1300                 stat->start_ktime = ktime_get();
1301         } else {
1302                 if (is_data_error) {
1303                         pr_err("%s %s error stats case: blk_size=%d, blk_count=0, is_start_stat=%d, data Error case ... data_flags=0x%x\n",
1304                                 mmc_hostname(host->mmc), __func__, blk_size,
1305                                 (int)is_start_stat, data_flags);
1306                         memset(&stat->start_ktime, 0, sizeof(ktime_t));
1307                         if (!stat->total_bytes)
1308                                 free_data_entry(host, blk_size, blk_count,
1309                                         data_flags);
1310                         goto end;
1311                 }
1312                 t = ktime_get();
1313                 stat->duration_usecs = ktime_us_delta(t, stat->start_ktime);
1314                 stat->current_transferred_bytes = (blk_size * blk_count);
1315                 get_kbps_from_size_n_usec_32bit(
1316                         (((u32)stat->current_transferred_bytes << 3) * 1000),
1317                         stat->duration_usecs,
1318                         &new_kbps);
1319                 if (stat->max_kbps == 0) {
1320                         stat->max_kbps = new_kbps;
1321                         stat->min_kbps = new_kbps;
1322                 } else {
1323                         if (new_kbps > stat->max_kbps)
1324                                 stat->max_kbps = new_kbps;
1325                         if (new_kbps < stat->min_kbps)
1326                                 stat->min_kbps = new_kbps;
1327                 }
1328                 /* update the total bytes figure for this entry */
1329                 stat->total_usecs += stat->duration_usecs;
1330                 stat->total_bytes += stat->current_transferred_bytes;
1331                 stat->total_transfers++;
1332         }
1333 end:
1334         return;
1335 }
1336 #endif
1337
1338 static void sdhci_finish_data(struct sdhci_host *host)
1339 {
1340         struct mmc_data *data;
1341
1342         BUG_ON(!host->data);
1343 #ifdef CONFIG_CMD_DUMP
1344         if (IS_EMMC_CARD(host))
1345                 dbg_add_host_log(host->mmc, 9, 9, (int)host->mrq_dat);
1346 #endif
1347
1348         data = host->data;
1349         host->data = NULL;
1350
1351         if (host->flags & SDHCI_REQ_USE_DMA) {
1352                 if (host->flags & SDHCI_USE_ADMA)
1353                         sdhci_adma_table_post(host, data);
1354                 else {
1355                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
1356                                 data->sg_len, (data->flags & MMC_DATA_READ) ?
1357                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
1358                 }
1359         }
1360
1361         /*
1362          * The specification states that the block count register must
1363          * be updated, but it does not specify at what point in the
1364          * data flow. That makes the register entirely useless to read
1365          * back so we have to assume that nothing made it to the card
1366          * in the event of an error.
1367          */
1368         if (data->error)
1369                 data->bytes_xfered = 0;
1370         else
1371                 data->bytes_xfered = data->blksz * data->blocks;
1372
1373         /*
1374          * Need to send CMD12 if -
1375          * a) open-ended multiblock transfer (no CMD23)
1376          * b) error in multiblock transfer
1377          */
1378         if (data->stop &&
1379             (data->error ||
1380              (!MMC_CHECK_CMDQ_MODE(host) && !host->mrq_dat->sbc))) {
1381
1382                 /*
1383                  * The controller needs a reset of internal state machines
1384                  * upon error conditions.
1385                  */
1386                 if (data->error) {
1387                         if (!MMC_CHECK_CMDQ_MODE(host))
1388                                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1389                         else
1390                                 sdhci_reset(host, SDHCI_RESET_DATA);
1391                 }
1392                 sdhci_send_command(host, data->stop);
1393         } else {
1394                 if (MMC_CHECK_CMDQ_MODE(host))
1395                         tasklet_schedule(&host->finish_dat_tasklet);
1396                 else
1397                         tasklet_schedule(&host->finish_tasklet);
1398         }
1399 #ifdef CONFIG_DEBUG_FS
1400         if (data->bytes_xfered) {
1401                 update_stat(host, data->blksz, data->blocks, false, false,
1402                         data->flags);
1403         } else {
1404                 host->no_data_transfer_count++;
1405                 /* performance stats does not include cases of data error */
1406                 update_stat(host, data->blksz, data->blocks, false, true,
1407                         data->flags);
1408         }
1409 #endif
1410 }
1411
1412 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1413 {
1414         int flags;
1415         u32 mask;
1416         unsigned long timeout;
1417
1418         WARN_ON(host->cmd);
1419
1420         /* Wait max 10 ms */
1421         timeout = 10;
1422
1423         if (!host->mrq_cmd && host->mrq_dat)
1424                 host->mrq_cmd = host->mrq_dat;
1425
1426         mask = SDHCI_CMD_INHIBIT;
1427         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
1428                 mask |= SDHCI_DATA_INHIBIT;
1429
1430         /* We shouldn't wait for data inihibit for stop commands, even
1431            though they might use busy signaling */
1432         if (host->mrq_cmd->data && (cmd == host->mrq_cmd->data->stop))
1433                 mask &= ~SDHCI_DATA_INHIBIT;
1434
1435         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1436                 if (timeout == 0) {
1437                         pr_err("%s: Controller never released "
1438                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
1439                         sdhci_dumpregs(host);
1440                         cmd->error = -EIO;
1441                         if (MMC_CHECK_CMDQ_MODE(host))
1442                                 tasklet_schedule(&host->finish_cmd_tasklet);
1443                         else
1444                                 tasklet_schedule(&host->finish_tasklet);
1445                         return;
1446                 }
1447                 timeout--;
1448                 mdelay(1);
1449         }
1450
1451         if ((cmd->opcode == MMC_SWITCH) &&
1452                 (((cmd->arg >> 16) & EXT_CSD_SANITIZE_START)
1453                 == EXT_CSD_SANITIZE_START))
1454                 timeout = 100;
1455         else
1456                 timeout = 10;
1457
1458         mod_timer(&host->timer, jiffies + timeout * HZ);
1459
1460         host->cmd = cmd;
1461
1462         sdhci_prepare_data(host, cmd);
1463
1464         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1465
1466         sdhci_set_transfer_mode(host, cmd);
1467
1468         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1469                 pr_err("%s: Unsupported response type!\n",
1470                         mmc_hostname(host->mmc));
1471                 cmd->error = -EINVAL;
1472                 if (MMC_CHECK_CMDQ_MODE(host))
1473                         tasklet_schedule(&host->finish_cmd_tasklet);
1474                 else
1475                         tasklet_schedule(&host->finish_tasklet);
1476                 return;
1477         }
1478
1479         if (!(cmd->flags & MMC_RSP_PRESENT))
1480                 flags = SDHCI_CMD_RESP_NONE;
1481         else if (cmd->flags & MMC_RSP_136)
1482                 flags = SDHCI_CMD_RESP_LONG;
1483         else if (cmd->flags & MMC_RSP_BUSY)
1484                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1485         else
1486                 flags = SDHCI_CMD_RESP_SHORT;
1487
1488         if (cmd->flags & MMC_RSP_CRC)
1489                 flags |= SDHCI_CMD_CRC;
1490         if (cmd->flags & MMC_RSP_OPCODE)
1491                 flags |= SDHCI_CMD_INDEX;
1492
1493         /* CMD19, CMD21 is special in that the Data Present Select should be set */
1494         if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1495             cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1496                 flags |= SDHCI_CMD_DATA;
1497
1498 #ifdef CONFIG_CMD_DUMP
1499         if (MMC_CHECK_CMDQ_MODE(host))
1500                 dbg_add_host_log(host->mmc, 0, cmd->opcode, cmd->arg);
1501 #endif
1502 #ifdef CONFIG_EMMC_BLKTRACE
1503         if (!MMC_CHECK_CMDQ_MODE(host)) {
1504                 if (cmd->opcode == MMC_SET_BLOCK_COUNT)
1505                         emmc_trace(MMC_ISSUE, host->mmc->mqrq_cur, host->mmc);
1506                 else if (cmd->opcode == MMC_READ_MULTIPLE_BLOCK ||
1507                                 cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK)
1508                         emmc_trace(MMC_ISSUE_DONE,
1509                                 host->mmc->mqrq_cur, host->mmc);
1510         } else {
1511                 if (cmd->opcode == MMC_QUEUED_TASK_ADDRESS)
1512                         emmc_trace(MMC_ISSUE,
1513                                 &host->mmc->mq->mqrq[cmd->mrq->areq->mrq->cmd->arg >> 16],
1514                                 host->mmc);
1515                 else if (cmd->opcode == MMC_EXECUTE_READ_TASK ||
1516                                 cmd->opcode == MMC_EXECUTE_WRITE_TASK)
1517                         emmc_trace(MMC_ISSUE_DONE,
1518                                 &host->mmc->mq->mqrq[cmd->arg >> 16],
1519                                 host->mmc);
1520         }
1521 #endif
1522         host->command = SDHCI_MAKE_CMD(cmd->opcode, flags);
1523         sdhci_writew(host, host->command, SDHCI_COMMAND);
1524 }
1525
1526 static void sdhci_finish_command(struct sdhci_host *host)
1527 {
1528         int i;
1529
1530         BUG_ON(host->cmd == NULL);
1531 #ifdef CONFIG_CMD_DUMP
1532         if (IS_EMMC_CARD(host))
1533                 dbg_add_host_log(host->mmc, 8, 8, (int)host->mrq_cmd);
1534 #endif
1535
1536         if (host->cmd->flags & MMC_RSP_PRESENT) {
1537                 if (host->cmd->flags & MMC_RSP_136) {
1538                         /* CRC is stripped so we need to do some shifting. */
1539                         for (i = 0; i < 4; i++) {
1540                                 host->cmd->resp[i] = sdhci_readl(host,
1541                                         SDHCI_RESPONSE + (3-i)*4) << 8;
1542                                 if (i != 3)
1543                                         host->cmd->resp[i] |=
1544                                                 sdhci_readb(host,
1545                                                 SDHCI_RESPONSE + (3-i)*4-1);
1546                         }
1547                 } else {
1548                         host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1549                 }
1550         }
1551
1552         host->cmd->error = 0;
1553
1554 #ifdef CONFIG_CMD_DUMP
1555         if (MMC_CHECK_CMDQ_MODE(host))
1556                 dbg_add_host_log(host->mmc, 0,
1557                         host->cmd->opcode, host->cmd->resp[0]);
1558 #endif
1559         /* Finished CMD23, now send actual command. */
1560         if (host->cmd == host->mrq_cmd->sbc) {
1561                 host->cmd = NULL;
1562                 sdhci_send_command(host, host->mrq_cmd->cmd);
1563         } else {
1564
1565                 /* Processed actual command. */
1566                 if (host->cmd->data && host->data_early) {
1567                         host->cmd = NULL;
1568                         host->mrq_dat = host->mrq_cmd;
1569                         host->mrq_cmd = NULL;
1570                         sdhci_finish_data(host);
1571                 }
1572
1573                 if (!MMC_CHECK_CMDQ_MODE(host)) {
1574                         if (!host->cmd->data)
1575
1576                                 tasklet_schedule(&host->finish_tasklet);
1577                         else {
1578                                 host->mrq_dat = host->mrq_cmd;
1579                                 host->mrq_cmd = NULL;
1580                         }
1581
1582                         host->cmd = NULL;
1583                 } else if (!host->data_early) {
1584                         if (!host->mrq_cmd->cmd->error &&
1585                         !host->cmd->error && host->cmd->data) {
1586                                 host->cmd = NULL;
1587                                 host->mrq_dat = host->mrq_cmd;
1588                                 host->mrq_cmd = NULL;
1589                         }
1590                         tasklet_schedule(&host->finish_cmd_tasklet);
1591                 }
1592         }
1593 }
1594
1595 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1596 {
1597         u16 ctrl, preset = 0;
1598
1599         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1600
1601         switch (ctrl & SDHCI_CTRL_UHS_MASK) {
1602         case SDHCI_CTRL_UHS_SDR12:
1603                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1604                 break;
1605         case SDHCI_CTRL_UHS_SDR25:
1606                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1607                 break;
1608         case SDHCI_CTRL_UHS_SDR50:
1609                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1610                 break;
1611         case SDHCI_CTRL_UHS_SDR104:
1612                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1613                 break;
1614         case SDHCI_CTRL_UHS_DDR50:
1615                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1616                 break;
1617         default:
1618                 pr_warn("%s: Invalid UHS-I mode selected\n",
1619                         mmc_hostname(host->mmc));
1620                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1621                 break;
1622         }
1623         return preset;
1624 }
1625
1626 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1627 {
1628         int div = 0; /* Initialized for compiler warning */
1629         int real_div = div, clk_mul = 1;
1630         u16 clk = 0;
1631         unsigned long timeout;
1632         u32 caps;
1633
1634         if (clock && clock == host->clock)
1635                 return;
1636
1637         host->mmc->actual_clock = 0;
1638
1639         if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1640                 return;
1641
1642         /*
1643          * If the entire clock control register is updated with zero, some
1644          * controllers might first update clock divisor fields and then update
1645          * the INT_CLK_EN and CARD_CLK_EN fields. Disable card clock first
1646          * to ensure there is no abnormal clock behavior.
1647          */
1648         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1649         clk &= ~SDHCI_CLOCK_CARD_EN;
1650         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1651         clk = 0;
1652         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1653
1654         if (clock == 0)
1655                 goto out;
1656
1657         if (host->version >= SDHCI_SPEC_300) {
1658                 if (sdhci_readw(host, SDHCI_HOST_CONTROL2) &
1659                         SDHCI_CTRL_PRESET_VAL_ENABLE) {
1660                         u16 pre_val;
1661
1662                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1663                         pre_val = sdhci_get_preset_value(host);
1664                         div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1665                                 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1666                         if (host->clk_mul &&
1667                                 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1668                                 clk = SDHCI_PROG_CLOCK_MODE;
1669                                 real_div = div + 1;
1670                                 clk_mul = host->clk_mul;
1671                         } else {
1672                                 real_div = max_t(int, 1, div << 1);
1673                         }
1674                         goto clock_set;
1675                 }
1676
1677                 /*
1678                  * Check if the Host Controller supports Programmable Clock
1679                  * Mode.
1680                  */
1681                 if (host->clk_mul) {
1682                         for (div = 1; div <= 1024; div++) {
1683                                 if ((host->max_clk * host->clk_mul / div)
1684                                         <= clock)
1685                                         break;
1686                         }
1687                         /*
1688                          * Set Programmable Clock Mode in the Clock
1689                          * Control register.
1690                          */
1691                         clk = SDHCI_PROG_CLOCK_MODE;
1692                         real_div = div;
1693                         clk_mul = host->clk_mul;
1694                         div--;
1695                 } else {
1696                         /* Version 3.00 divisors must be a multiple of 2. */
1697                         if (host->max_clk <= clock) {
1698                                 if (host->mmc->ios.timing ==
1699                                         MMC_TIMING_UHS_DDR50)
1700                                         div = 2;
1701                                 else
1702                                         div = 1;
1703                         } else {
1704                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1705                                      div += 2) {
1706                                         if ((host->max_clk / div) <= clock)
1707                                                 break;
1708                                 }
1709                         }
1710                         real_div = div;
1711                         div >>= 1;
1712                 }
1713         } else {
1714                 /* Version 2.00 divisors must be a power of 2. */
1715                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1716                         if ((host->max_clk / div) <= clock)
1717                                 break;
1718                 }
1719                 real_div = div;
1720                 div >>= 1;
1721         }
1722
1723 clock_set:
1724         if (real_div)
1725                 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1726
1727         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1728         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1729                 << SDHCI_DIVIDER_HI_SHIFT;
1730         clk |= SDHCI_CLOCK_INT_EN;
1731         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1732
1733         /*
1734          * For Tegra3 sdmmc controller, internal clock will not be stable bit
1735          * will get set only after some other register write is done. To
1736          * handle, do a dummy reg write to the caps reg if
1737          * SDHCI_QUIRK2_INT_CLK_STABLE_REQ_DUMMY_REG_WRITE is set.
1738          */
1739         if (host->quirks2 & SDHCI_QUIRK2_INT_CLK_STABLE_REQ_DUMMY_REG_WRITE) {
1740                 udelay(5);
1741
1742                 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
1743                 caps |= 1;
1744                 sdhci_writel(host, caps, SDHCI_CAPABILITIES);
1745         }
1746
1747         /* Wait max 20 ms */
1748         timeout = 20;
1749         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1750                 & SDHCI_CLOCK_INT_STABLE)) {
1751                 if (timeout == 0) {
1752                         pr_err("%s: Internal clock never "
1753                                 "stabilised.\n", mmc_hostname(host->mmc));
1754                         sdhci_dumpregs(host);
1755                         return;
1756                 }
1757                 timeout--;
1758                 mdelay(1);
1759         }
1760
1761         clk |= SDHCI_CLOCK_CARD_EN;
1762         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1763
1764 out:
1765         host->clock = clock;
1766 }
1767
1768 static inline void sdhci_update_clock(struct sdhci_host *host)
1769 {
1770         unsigned int clock;
1771
1772         clock = host->clock;
1773         host->clock = 0;
1774         if (host->ops->set_clock)
1775                 host->ops->set_clock(host, clock);
1776         sdhci_set_clock(host, clock);
1777 }
1778
1779 static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
1780 {
1781         u8 pwr = 0;
1782
1783         if (power != (unsigned short)-1) {
1784                 switch (1 << power) {
1785                 case MMC_VDD_165_195:
1786                         pwr = SDHCI_POWER_180;
1787                         break;
1788                 case MMC_VDD_29_30:
1789                 case MMC_VDD_30_31:
1790                         pwr = SDHCI_POWER_300;
1791                         break;
1792                 case MMC_VDD_32_33:
1793                 case MMC_VDD_33_34:
1794                         pwr = SDHCI_POWER_330;
1795                         break;
1796                 default:
1797                         BUG();
1798                 }
1799         }
1800
1801         if (host->pwr == pwr)
1802                 return -1;
1803
1804         host->pwr = pwr;
1805
1806         if (pwr == 0) {
1807                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1808                 return 0;
1809         }
1810
1811         /*
1812          * Spec says that we should clear the power reg before setting
1813          * a new value. Some controllers don't seem to like this though.
1814          */
1815         if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1816                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1817
1818         /*
1819          * At least the Marvell CaFe chip gets confused if we set the voltage
1820          * and set turn on power at the same time, so set the voltage first.
1821          */
1822         if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1823                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1824
1825         pwr |= SDHCI_POWER_ON;
1826
1827         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1828
1829         /*
1830          * Some controllers need an extra 10ms delay of 10ms before they
1831          * can apply clock after applying power
1832          */
1833         if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1834                 mdelay(10);
1835
1836         return power;
1837 }
1838
1839 static void sdhci_en_strobe(struct mmc_host *mmc)
1840 {
1841         struct sdhci_host *host;
1842
1843         host = mmc_priv(mmc);
1844
1845         sdhci_runtime_pm_get(host);
1846         if (host->ops->en_strobe)
1847                 host->ops->en_strobe(host);
1848         sdhci_runtime_pm_put(host);
1849 }
1850 /* Execute DLL calibration once for MMC device if it is
1851  * enumerated in HS400 mode at 200MHz clock freq before
1852  * starting any data transfer.
1853  */
1854 static void sdhci_post_init(struct mmc_host *mmc)
1855 {
1856         struct sdhci_host *host;
1857
1858         host = mmc_priv(mmc);
1859
1860         sdhci_runtime_pm_get(host);
1861         if (host->ops->post_init)
1862                 host->ops->post_init(host);
1863         sdhci_runtime_pm_put(host);
1864 }
1865 /*****************************************************************************\
1866  *                                                                           *
1867  * MMC callbacks                                                             *
1868  *                                                                           *
1869 \*****************************************************************************/
1870
1871 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1872 {
1873         struct sdhci_host *host;
1874         int present;
1875         unsigned long flags;
1876         u32 tuning_opcode;
1877
1878         host = mmc_priv(mmc);
1879
1880 #ifdef CONFIG_DEBUG_FS
1881         if (mrq->data && mrq->data->blocks)
1882                 update_stat(host, mrq->data->blksz, mrq->data->blocks,
1883                         true, false, mrq->data->flags);
1884 #endif
1885
1886         sdhci_runtime_pm_get(host);
1887
1888         spin_lock_irqsave(&host->lock, flags);
1889
1890         WARN_ON(host->mrq_cmd != NULL);
1891
1892 #ifndef SDHCI_USE_LEDS_CLASS
1893         sdhci_activate_led(host);
1894 #endif
1895
1896         /*
1897          * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1898          * requests if Auto-CMD12 is enabled.
1899          */
1900         if (!MMC_CHECK_CMDQ_MODE(host) && !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1901                 if (mrq->stop) {
1902                         mrq->data->stop = NULL;
1903                         mrq->stop = NULL;
1904                 }
1905         }
1906
1907         host->mrq_cmd = mrq;
1908         host->mrq_cmd->data_early = 0;
1909
1910         /*
1911          * Firstly check card presence from cd-gpio.  The return could
1912          * be one of the following possibilities:
1913          *     negative: cd-gpio is not available
1914          *     zero: cd-gpio is used, and card is removed
1915          *     one: cd-gpio is used, and card is present
1916          */
1917         present = mmc_gpio_get_cd(host->mmc);
1918         if (present < 0) {
1919                 /* If polling, assume that the card is always present. */
1920                 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1921                         if (host->ops->get_cd)
1922                                 present = host->ops->get_cd(host);
1923                         else
1924                                 present = 1;
1925                 else
1926                         present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1927                                         SDHCI_CARD_PRESENT;
1928         }
1929
1930         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1931                 host->mrq_cmd->cmd->error = -ENOMEDIUM;
1932                 if (MMC_CHECK_CMDQ_MODE(host))
1933                         tasklet_schedule(&host->finish_cmd_tasklet);
1934                 else
1935                         tasklet_schedule(&host->finish_tasklet);
1936         } else {
1937                 u32 present_state;
1938
1939                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1940                 /*
1941                  * Check if the re-tuning timer has already expired and there
1942                  * is no on-going data transfer. If so, we need to execute
1943                  * tuning procedure before sending command.
1944                  */
1945                 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1946                     !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1947                         if (!mmc->need_tuning || !mmc->ready_tuning) {
1948                                 if (!mmc->need_tuning)
1949                                         mmc->need_tuning = 1;
1950                                 goto end_tuning;
1951                         }
1952
1953                         if (mmc->card) {
1954                                 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1955                                 tuning_opcode =
1956                                         mmc->card->type == MMC_TYPE_MMC ?
1957                                         MMC_SEND_TUNING_BLOCK_HS200 :
1958                                         MMC_SEND_TUNING_BLOCK;
1959                                 host->mrq_cmd = NULL;
1960                                 spin_unlock_irqrestore(&host->lock, flags);
1961                                 sdhci_execute_tuning(mmc, tuning_opcode);
1962                                 mmc->need_tuning = 0;
1963                                 mmc->ready_tuning = 0;
1964                                 spin_lock_irqsave(&host->lock, flags);
1965
1966 end_tuning:
1967                                 /* Restore original mmc_request structure */
1968                                 host->mrq_cmd = mrq;
1969                         }
1970                 }
1971
1972                 /* For a data cmd, check for plat specific preparation */
1973                 spin_unlock_irqrestore(&host->lock, flags);
1974                 if (mrq->data)
1975                         host->ops->platform_get_bus(host);
1976                 spin_lock_irqsave(&host->lock, flags);
1977
1978                 if (!MMC_CHECK_CMDQ_MODE(host) &&
1979                         (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)))
1980                                 sdhci_send_command(host, mrq->sbc);
1981                 else if (MMC_CHECK_CMDQ_MODE(host) && mrq->sbc)
1982                         sdhci_send_command(host, mrq->sbc);
1983                 else {
1984                         sdhci_send_command(host, mrq->cmd);
1985                 }
1986         }
1987
1988         mmiowb();
1989         spin_unlock_irqrestore(&host->lock, flags);
1990 }
1991
1992 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1993 {
1994         unsigned long flags;
1995         int vdd_bit = -1;
1996         u8 ctrl;
1997
1998         /* cancel delayed clk gate work */
1999         if (host->quirks2 & SDHCI_QUIRK2_DELAYED_CLK_GATE)
2000                 cancel_delayed_work_sync(&host->delayed_clk_gate_wrk);
2001
2002         /* Do any required preparations prior to setting ios */
2003         if (host->ops->platform_ios_config_enter)
2004                 host->ops->platform_ios_config_enter(host, ios);
2005
2006         spin_lock_irqsave(&host->lock, flags);
2007
2008         if (host->flags & SDHCI_DEVICE_DEAD) {
2009                 spin_unlock_irqrestore(&host->lock, flags);
2010                 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
2011                         mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
2012                 return;
2013         }
2014
2015         /*
2016          * Reset the chip on each power off.
2017          * Should clear out any weird states.
2018          */
2019         if (ios->power_mode == MMC_POWER_OFF) {
2020                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2021                 sdhci_reinit(host);
2022         }
2023
2024         if (host->version >= SDHCI_SPEC_300 &&
2025                 (ios->power_mode == MMC_POWER_UP))
2026                 sdhci_enable_preset_value(host, false);
2027
2028         if (ios->power_mode == MMC_POWER_OFF)
2029                 vdd_bit = sdhci_set_power(host, -1);
2030         else
2031                 vdd_bit = sdhci_set_power(host, ios->vdd);
2032
2033         if (host->vmmc && vdd_bit != -1) {
2034                 spin_unlock_irqrestore(&host->lock, flags);
2035                 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
2036                 spin_lock_irqsave(&host->lock, flags);
2037         }
2038
2039         sdhci_set_clock(host, ios->clock);
2040
2041         if (host->ops->platform_send_init_74_clocks)
2042                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
2043
2044         /*
2045          * If your platform has 8-bit width support but is not a v3 controller,
2046          * or if it requires special setup code, you should implement that in
2047          * platform_bus_width().
2048          */
2049         if (host->ops->platform_bus_width) {
2050                 host->ops->platform_bus_width(host, ios->bus_width);
2051         } else {
2052                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2053                 if (ios->bus_width == MMC_BUS_WIDTH_8) {
2054                         ctrl &= ~SDHCI_CTRL_4BITBUS;
2055                         if (host->version >= SDHCI_SPEC_300)
2056                                 ctrl |= SDHCI_CTRL_8BITBUS;
2057                 } else {
2058                         if (host->version >= SDHCI_SPEC_300)
2059                                 ctrl &= ~SDHCI_CTRL_8BITBUS;
2060                         if (ios->bus_width == MMC_BUS_WIDTH_4)
2061                                 ctrl |= SDHCI_CTRL_4BITBUS;
2062                         else
2063                                 ctrl &= ~SDHCI_CTRL_4BITBUS;
2064                 }
2065                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2066         }
2067
2068         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2069
2070         if ((ios->timing == MMC_TIMING_SD_HS ||
2071              ios->timing == MMC_TIMING_MMC_HS)
2072             && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
2073                 ctrl |= SDHCI_CTRL_HISPD;
2074         else
2075                 ctrl &= ~SDHCI_CTRL_HISPD;
2076
2077         if (host->version >= SDHCI_SPEC_300) {
2078                 u16 clk, ctrl_2;
2079
2080                 /* In case of UHS-I modes, set High Speed Enable */
2081                 if (((ios->timing == MMC_TIMING_MMC_HS200) ||
2082                     (ios->timing == MMC_TIMING_UHS_SDR50) ||
2083                     (ios->timing == MMC_TIMING_UHS_SDR104) ||
2084                     (ios->timing == MMC_TIMING_UHS_DDR50) ||
2085                     (ios->timing == MMC_TIMING_UHS_SDR25))
2086                     && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
2087                         ctrl |= SDHCI_CTRL_HISPD;
2088
2089                 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2090                 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2091                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2092                         /*
2093                          * We only need to set Driver Strength if the
2094                          * preset value enable is not set.
2095                          */
2096                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
2097                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
2098                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
2099                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
2100                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
2101
2102                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
2103                 } else {
2104                         /*
2105                          * According to SDHC Spec v3.00, if the Preset Value
2106                          * Enable in the Host Control 2 register is set, we
2107                          * need to reset SD Clock Enable before changing High
2108                          * Speed Enable to avoid generating clock gliches.
2109                          */
2110
2111                         /* Reset SD Clock Enable */
2112                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2113                         clk &= ~SDHCI_CLOCK_CARD_EN;
2114                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2115
2116                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2117
2118                         /* Re-enable SD Clock */
2119                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2120                         clk |= SDHCI_CLOCK_CARD_EN;
2121                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2122                 }
2123
2124
2125                 /* Reset SD Clock Enable */
2126                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2127                 clk &= ~SDHCI_CLOCK_CARD_EN;
2128                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2129
2130                 if (host->ops->set_uhs_signaling)
2131                         host->ops->set_uhs_signaling(host, ios->timing);
2132                 else {
2133                         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2134                         /* Select Bus Speed Mode for host */
2135                         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
2136                         if (ios->timing == MMC_TIMING_MMC_HS200)
2137                                 ctrl_2 |= SDHCI_CTRL_HS_SDR200;
2138                         else if (ios->timing == MMC_TIMING_UHS_SDR12)
2139                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
2140                         else if (ios->timing == MMC_TIMING_UHS_SDR25)
2141                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
2142                         else if (ios->timing == MMC_TIMING_UHS_SDR50)
2143                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
2144                         else if (ios->timing == MMC_TIMING_UHS_SDR104)
2145                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
2146                         else if (ios->timing == MMC_TIMING_UHS_DDR50)
2147                                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
2148                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
2149                 }
2150
2151                 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
2152                                 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
2153                                  (ios->timing == MMC_TIMING_UHS_SDR25) ||
2154                                  (ios->timing == MMC_TIMING_UHS_SDR50) ||
2155                                  (ios->timing == MMC_TIMING_UHS_SDR104) ||
2156                                  (ios->timing == MMC_TIMING_UHS_DDR50))) {
2157                         u16 preset;
2158
2159                         sdhci_enable_preset_value(host, true);
2160                         preset = sdhci_get_preset_value(host);
2161                         ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
2162                                 >> SDHCI_PRESET_DRV_SHIFT;
2163                 }
2164
2165                 /* Re-enable SD Clock */
2166                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2167                 clk |= SDHCI_CLOCK_CARD_EN;
2168                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2169         } else
2170                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2171
2172         /*
2173          * Some (ENE) controllers go apeshit on some ios operation,
2174          * signalling timeout and CRC errors even on CMD0. Resetting
2175          * it on each ios seems to solve the problem.
2176          */
2177         if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
2178                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
2179
2180         mmiowb();
2181         spin_unlock_irqrestore(&host->lock, flags);
2182
2183         /* Platform specific handling post ios setting */
2184         if (host->ops->platform_ios_config_exit)
2185                 host->ops->platform_ios_config_exit(host, ios);
2186
2187 }
2188
2189 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
2190 {
2191         struct sdhci_host *host = mmc_priv(mmc);
2192
2193         sdhci_runtime_pm_get(host);
2194         sdhci_do_set_ios(host, ios);
2195         sdhci_runtime_pm_put(host);
2196 }
2197
2198 static int sdhci_do_get_cd(struct sdhci_host *host)
2199 {
2200         int gpio_cd = mmc_gpio_get_cd(host->mmc);
2201
2202         if (host->flags & SDHCI_DEVICE_DEAD)
2203                 return 0;
2204
2205         /* If polling/nonremovable, assume that the card is always present. */
2206         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
2207             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
2208                 return 1;
2209
2210         /* Try slot gpio detect */
2211         if (!IS_ERR_VALUE(gpio_cd))
2212                 return !!gpio_cd;
2213
2214         /* Host native card detect */
2215         return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
2216 }
2217
2218 static int sdhci_get_cd(struct mmc_host *mmc)
2219 {
2220         struct sdhci_host *host = mmc_priv(mmc);
2221         int ret;
2222
2223         sdhci_runtime_pm_get(host);
2224         ret = sdhci_do_get_cd(host);
2225         sdhci_runtime_pm_put(host);
2226         return ret;
2227 }
2228
2229 static int sdhci_check_ro(struct sdhci_host *host)
2230 {
2231         unsigned long flags;
2232         int is_readonly;
2233
2234         spin_lock_irqsave(&host->lock, flags);
2235
2236         if (host->flags & SDHCI_DEVICE_DEAD)
2237                 is_readonly = 0;
2238         else if (host->ops->get_ro)
2239                 is_readonly = host->ops->get_ro(host);
2240         else
2241                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
2242                                 & SDHCI_WRITE_PROTECT);
2243
2244         spin_unlock_irqrestore(&host->lock, flags);
2245
2246         /* This quirk needs to be replaced by a callback-function later */
2247         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
2248                 !is_readonly : is_readonly;
2249 }
2250
2251 #define SAMPLE_COUNT    5
2252
2253 static int sdhci_do_get_ro(struct sdhci_host *host)
2254 {
2255         int i, ro_count;
2256
2257         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
2258                 return sdhci_check_ro(host);
2259
2260         ro_count = 0;
2261         for (i = 0; i < SAMPLE_COUNT; i++) {
2262                 if (sdhci_check_ro(host)) {
2263                         if (++ro_count > SAMPLE_COUNT / 2)
2264                                 return 1;
2265                 }
2266                 msleep(30);
2267         }
2268         return 0;
2269 }
2270
2271 static void sdhci_hw_reset(struct mmc_host *mmc)
2272 {
2273         struct sdhci_host *host = mmc_priv(mmc);
2274
2275         if (host->ops && host->ops->hw_reset)
2276                 host->ops->hw_reset(host);
2277 }
2278
2279 static int sdhci_get_ro(struct mmc_host *mmc)
2280 {
2281         struct sdhci_host *host = mmc_priv(mmc);
2282         int ret;
2283
2284         sdhci_runtime_pm_get(host);
2285         ret = sdhci_do_get_ro(host);
2286         sdhci_runtime_pm_put(host);
2287         return ret;
2288 }
2289
2290 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
2291 {
2292         if (host->flags & SDHCI_DEVICE_DEAD)
2293                 goto out;
2294
2295         if (enable)
2296                 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
2297         else
2298                 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
2299
2300         /* SDIO IRQ will be enabled as appropriate in runtime resume */
2301         if (host->runtime_suspended)
2302                 goto out;
2303
2304         if (enable)
2305                 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
2306         else
2307                 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
2308 out:
2309         mmiowb();
2310 }
2311
2312 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
2313 {
2314         struct sdhci_host *host = mmc_priv(mmc);
2315         unsigned long flags;
2316
2317         spin_lock_irqsave(&host->lock, flags);
2318         sdhci_enable_sdio_irq_nolock(host, enable);
2319         spin_unlock_irqrestore(&host->lock, flags);
2320 }
2321
2322 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
2323                                                 struct mmc_ios *ios)
2324 {
2325         u16 ctrl;
2326         int ret;
2327
2328         /*
2329          * Signal Voltage Switching is only applicable for Host Controllers
2330          * v3.00 and above.
2331          */
2332         if (host->version < SDHCI_SPEC_300)
2333                 return 0;
2334
2335         if (host->quirks2 & SDHCI_QUIRK2_NON_STD_VOLTAGE_SWITCHING) {
2336                 if (host->ops->switch_signal_voltage)
2337                         return host->ops->switch_signal_voltage(
2338                                 host, ios->signal_voltage);
2339         }
2340
2341         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2342
2343         switch (ios->signal_voltage) {
2344         case MMC_SIGNAL_VOLTAGE_330:
2345                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
2346                 ctrl &= ~SDHCI_CTRL_VDD_180;
2347                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2348
2349                 if (host->vqmmc) {
2350                         ret = regulator_set_voltage(host->vqmmc, 2700000, 3600000);
2351                         if (ret) {
2352                                 pr_warning("%s: Switching to 3.3V signalling voltage "
2353                                                 " failed\n", mmc_hostname(host->mmc));
2354                                 return -EIO;
2355                         }
2356                 }
2357                 /* Wait for 5ms */
2358                 usleep_range(5000, 5500);
2359
2360                 /* 3.3V regulator output should be stable within 5 ms */
2361                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2362                 if (!(ctrl & SDHCI_CTRL_VDD_180))
2363                         return 0;
2364
2365                 pr_warning("%s: 3.3V regulator output did not became stable\n",
2366                                 mmc_hostname(host->mmc));
2367
2368                 return -EAGAIN;
2369         case MMC_SIGNAL_VOLTAGE_180:
2370                 if (host->vqmmc) {
2371                         ret = regulator_set_voltage(host->vqmmc,
2372                                         1700000, 1950000);
2373                         if (ret) {
2374                                 pr_warning("%s: Switching to 1.8V signalling voltage "
2375                                                 " failed\n", mmc_hostname(host->mmc));
2376                                 return -EIO;
2377                         }
2378                 }
2379
2380                 /*
2381                  * Enable 1.8V Signal Enable in the Host Control2
2382                  * register
2383                  */
2384                 ctrl |= SDHCI_CTRL_VDD_180;
2385                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2386
2387                 /* Wait for 5ms */
2388                 usleep_range(5000, 5500);
2389
2390                 /* 1.8V regulator output should be stable within 5 ms */
2391                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2392                 if (ctrl & SDHCI_CTRL_VDD_180)
2393                         return 0;
2394
2395                 pr_warning("%s: 1.8V regulator output did not became stable\n",
2396                                 mmc_hostname(host->mmc));
2397
2398                 return -EAGAIN;
2399         case MMC_SIGNAL_VOLTAGE_120:
2400                 if (host->vqmmc) {
2401                         ret = regulator_set_voltage(host->vqmmc, 1100000, 1300000);
2402                         if (ret) {
2403                                 pr_warning("%s: Switching to 1.2V signalling voltage "
2404                                                 " failed\n", mmc_hostname(host->mmc));
2405                                 return -EIO;
2406                         }
2407                 }
2408                 return 0;
2409         default:
2410                 /* No signal voltage switch required */
2411                 return 0;
2412         }
2413 }
2414
2415 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
2416         struct mmc_ios *ios)
2417 {
2418         struct sdhci_host *host = mmc_priv(mmc);
2419         int err;
2420
2421         if (host->version < SDHCI_SPEC_300)
2422                 return 0;
2423         sdhci_runtime_pm_get(host);
2424         err = sdhci_do_start_signal_voltage_switch(host, ios);
2425         /* Do any post voltage switch platform specific configuration */
2426         if  (host->ops->switch_signal_voltage_exit)
2427                 host->ops->switch_signal_voltage_exit(host,
2428                         ios->signal_voltage);
2429         sdhci_runtime_pm_put(host);
2430         return err;
2431 }
2432
2433 static int sdhci_card_busy(struct mmc_host *mmc)
2434 {
2435         struct sdhci_host *host = mmc_priv(mmc);
2436         u32 present_state;
2437
2438         sdhci_runtime_pm_get(host);
2439         /* Check whether DAT[3:0] is 0000 */
2440         present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
2441         sdhci_runtime_pm_put(host);
2442
2443         return !(present_state & SDHCI_DATA_LVL_MASK);
2444 }
2445
2446 static void sdhci_config_tap(struct mmc_host *mmc, u8 option)
2447 {
2448         struct sdhci_host *host = mmc_priv(mmc);
2449
2450         if (host->ops->config_tap_delay)
2451                 host->ops->config_tap_delay(host, option);
2452 }
2453
2454 static int sdhci_validate_sd2_0(struct mmc_host *mmc)
2455 {
2456         struct sdhci_host *host;
2457         int err = 0;
2458
2459         host = mmc_priv(mmc);
2460
2461         if (host->ops->validate_sd2_0)
2462                 err = host->ops->validate_sd2_0(host);
2463         return err;
2464 }
2465
2466 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
2467 {
2468         struct sdhci_host *host;
2469         u16 ctrl;
2470         u32 ier;
2471         int tuning_loop_counter = MAX_TUNING_LOOP;
2472         unsigned long timeout;
2473         int err = 0;
2474         bool requires_tuning_nonuhs = false;
2475         u16 clk = 0;
2476
2477         host = mmc_priv(mmc);
2478
2479         sdhci_runtime_pm_get(host);
2480         disable_irq(host->irq);
2481
2482         if ((host->quirks2 & SDHCI_QUIRK2_NON_STANDARD_TUNING) &&
2483                 host->ops->execute_freq_tuning) {
2484                 err = host->ops->execute_freq_tuning(host, opcode);
2485                 enable_irq(host->irq);
2486                 sdhci_runtime_pm_put(host);
2487                 return err;
2488         }
2489
2490         if ((host->quirks2 & SDHCI_QUIRK2_NON_STD_TUNING_LOOP_CNTR) &&
2491                 (host->ops->get_max_tuning_loop_counter))
2492                 tuning_loop_counter =
2493                         host->ops->get_max_tuning_loop_counter(host);
2494
2495         spin_lock(&host->lock);
2496         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2497
2498         /*
2499          * The Host Controller needs tuning only in case of SDR104 mode
2500          * and for SDR50 mode when Use Tuning for SDR50 is set in the
2501          * Capabilities register.
2502          * If the Host Controller supports the HS200 mode then the
2503          * tuning function has to be executed.
2504          */
2505         if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
2506             (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
2507              host->flags & SDHCI_HS200_NEEDS_TUNING))
2508                 requires_tuning_nonuhs = true;
2509
2510         if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
2511             requires_tuning_nonuhs)
2512                 ctrl |= SDHCI_CTRL_EXEC_TUNING;
2513         else {
2514                 spin_unlock(&host->lock);
2515                 enable_irq(host->irq);
2516                 sdhci_runtime_pm_put(host);
2517                 return 0;
2518         }
2519
2520         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2521
2522         /*
2523          * As per the Host Controller spec v3.00, tuning command
2524          * generates Buffer Read Ready interrupt, so enable that.
2525          *
2526          * Note: The spec clearly says that when tuning sequence
2527          * is being performed, the controller does not generate
2528          * interrupts other than Buffer Read Ready interrupt. But
2529          * to make sure we don't hit a controller bug, we _only_
2530          * enable Buffer Read Ready interrupt here.
2531          */
2532         ier = host->ier;
2533         sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
2534
2535         /*
2536          * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
2537          * of loops reaches 40 times or a timeout of 150ms occurs.
2538          */
2539         timeout = 150;
2540         do {
2541                 struct mmc_command cmd = {0};
2542                 struct mmc_request mrq = {NULL};
2543
2544                 if (!tuning_loop_counter && !timeout)
2545                         break;
2546
2547                 cmd.opcode = opcode;
2548                 cmd.arg = 0;
2549                 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2550                 cmd.retries = 0;
2551                 cmd.data = NULL;
2552                 cmd.error = 0;
2553
2554                 mrq.cmd = &cmd;
2555                 host->mrq_cmd = &mrq;
2556
2557                 if (host->quirks2 & SDHCI_QUIRK2_NON_STD_TUN_CARD_CLOCK) {
2558                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2559                         clk &= ~SDHCI_CLOCK_CARD_EN;
2560                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2561                 }
2562
2563                 /*
2564                  * In response to CMD19, the card sends 64 bytes of tuning
2565                  * block to the Host Controller. So we set the block size
2566                  * to 64 here.
2567                  * In response to CMD21, the card sends 128 bytes of tuning
2568                  * block for MMC_BUS_WIDTH_8 and 64 bytes for MMC_BUS_WIDTH_4
2569                  * to the Host Controller. So we set the block size to 64 here.
2570                  */
2571                 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
2572                         if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2573                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
2574                                              SDHCI_BLOCK_SIZE);
2575                         else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
2576                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2577                                              SDHCI_BLOCK_SIZE);
2578                 } else {
2579                         sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2580                                      SDHCI_BLOCK_SIZE);
2581                 }
2582
2583                 /*
2584                  * The tuning block is sent by the card to the host controller.
2585                  * So we set the TRNS_READ bit in the Transfer Mode register.
2586                  * This also takes care of setting DMA Enable and Multi Block
2587                  * Select in the same register to 0.
2588                  */
2589                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2590
2591                 sdhci_send_command(host, &cmd);
2592
2593                 host->cmd = NULL;
2594                 host->mrq_cmd = NULL;
2595
2596                 spin_unlock(&host->lock);
2597                 enable_irq(host->irq);
2598
2599                 if (host->quirks2 & SDHCI_QUIRK2_NON_STD_TUN_CARD_CLOCK) {
2600                         udelay(1);
2601                         sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
2602                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2603                         clk |= SDHCI_CLOCK_CARD_EN;
2604                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2605                 }
2606
2607                 /* Wait for Buffer Read Ready interrupt */
2608                 wait_event_interruptible_timeout(host->buf_ready_int,
2609                                         (host->tuning_done == 1),
2610                                         msecs_to_jiffies(50));
2611                 disable_irq(host->irq);
2612                 spin_lock(&host->lock);
2613
2614                 if (!host->tuning_done) {
2615                         pr_info(DRIVER_NAME ": Timeout waiting for "
2616                                 "Buffer Read Ready interrupt during tuning "
2617                                 "procedure, falling back to fixed sampling "
2618                                 "clock\n");
2619                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2620                         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2621                         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2622                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2623
2624                         err = -EIO;
2625                         goto out;
2626                 }
2627
2628                 host->tuning_done = 0;
2629
2630                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2631                 tuning_loop_counter--;
2632                 timeout--;
2633                 mdelay(1);
2634         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2635
2636         /*
2637          * The Host Driver has exhausted the maximum number of loops allowed,
2638          * so use fixed sampling frequency.
2639          */
2640         if (!tuning_loop_counter || !timeout) {
2641                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2642                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2643         } else {
2644                 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2645                         pr_info(DRIVER_NAME ": Tuning procedure"
2646                                 " failed, falling back to fixed sampling"
2647                                 " clock\n");
2648                         err = -EIO;
2649                 } else {
2650                         sdhci_config_tap(mmc, SAVE_TUNED_TAP);
2651                         pr_info("%s: tap value and tuning window after hw tuning completion ...\n",
2652                                 mmc_hostname(mmc));
2653                         /* log tap, trim and tuning windows */
2654                         if (host->ops->dump_host_cust_regs)
2655                                 host->ops->dump_host_cust_regs(host);
2656                 }
2657         }
2658
2659 out:
2660         /*
2661          * If this is the very first time we are here, we start the retuning
2662          * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
2663          * flag won't be set, we check this condition before actually starting
2664          * the timer.
2665          */
2666         if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
2667             (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
2668                 host->flags |= SDHCI_USING_RETUNING_TIMER;
2669                 mod_timer(&host->tuning_timer, jiffies +
2670                         host->tuning_count * HZ);
2671                 /* Tuning mode 1 limits the maximum data length to 4MB */
2672                 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
2673         } else {
2674                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2675                 /* Reload the new initial value for timer */
2676                 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2677                         mod_timer(&host->tuning_timer, jiffies +
2678                                 host->tuning_count * HZ);
2679         }
2680
2681         /*
2682          * In case tuning fails, host controllers which support re-tuning can
2683          * try tuning again at a later time, when the re-tuning timer expires.
2684          * So for these controllers, we return 0. Since there might be other
2685          * controllers who do not have this capability, we return error for
2686          * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2687          * a retuning timer to do the retuning for the card.
2688          */
2689         if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
2690                 err = 0;
2691
2692         sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
2693         spin_unlock(&host->lock);
2694         enable_irq(host->irq);
2695         sdhci_runtime_pm_put(host);
2696
2697         return err;
2698 }
2699
2700
2701 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2702 {
2703         u16 ctrl;
2704
2705         /* Host Controller v3.00 defines preset value registers */
2706         if (host->version < SDHCI_SPEC_300)
2707                 return;
2708
2709         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2710
2711         /*
2712          * We only enable or disable Preset Value if they are not already
2713          * enabled or disabled respectively. Otherwise, we bail out.
2714          */
2715         if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2716                 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2717                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2718                 host->flags |= SDHCI_PV_ENABLED;
2719         } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2720                 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2721                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2722                 host->flags &= ~SDHCI_PV_ENABLED;
2723         }
2724 }
2725
2726 static void sdhci_card_event(struct mmc_host *mmc)
2727 {
2728         struct sdhci_host *host = mmc_priv(mmc);
2729         unsigned long flags;
2730
2731         sdhci_runtime_pm_get(host);
2732         spin_lock_irqsave(&host->lock, flags);
2733
2734         /* Check host->mrq_cmd first in case we are runtime suspended */
2735         if ((host->mrq_cmd || host->mrq_dat) &&
2736             !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
2737                 pr_err("%s: Card removed during transfer!\n",
2738                         mmc_hostname(host->mmc));
2739                 pr_err("%s: Resetting controller.\n",
2740                         mmc_hostname(host->mmc));
2741
2742                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
2743
2744                 if (host->mrq_cmd) {
2745                         host->mrq_cmd->cmd->error = -ENOMEDIUM;
2746                         if (MMC_CHECK_CMDQ_MODE(host))
2747                                 tasklet_schedule(&host->finish_cmd_tasklet);
2748                         else
2749                                 tasklet_schedule(&host->finish_tasklet);
2750                 }
2751                 if (host->mrq_dat) {
2752                         host->mrq_dat->cmd->error = -ENOMEDIUM;
2753                         if (MMC_CHECK_CMDQ_MODE(host))
2754                                 tasklet_schedule(&host->finish_dat_tasklet);
2755                         else
2756                                 tasklet_schedule(&host->finish_tasklet);
2757                 }
2758         }
2759
2760         spin_unlock_irqrestore(&host->lock, flags);
2761         sdhci_runtime_pm_put(host);
2762 }
2763
2764 int sdhci_enable(struct mmc_host *mmc)
2765 {
2766         struct sdhci_host *host = mmc_priv(mmc);
2767
2768         if (!mmc->card || !(mmc->caps2 & MMC_CAP2_CLOCK_GATING))
2769                 return 0;
2770
2771         /* cancel delayed clk gate work */
2772         if (host->quirks2 & SDHCI_QUIRK2_DELAYED_CLK_GATE)
2773                 cancel_delayed_work_sync(&host->delayed_clk_gate_wrk);
2774
2775         sysedp_set_state(host->sysedpc, 1);
2776
2777         if (mmc->ios.clock) {
2778                 if (host->ops->set_clock)
2779                         host->ops->set_clock(host, mmc->ios.clock);
2780                 sdhci_set_clock(host, mmc->ios.clock);
2781         }
2782
2783         return 0;
2784 }
2785
2786 static void mmc_host_clk_gate(struct sdhci_host *host)
2787 {
2788         sdhci_set_clock(host, 0);
2789         if (host->ops->set_clock)
2790                 host->ops->set_clock(host, 0);
2791
2792         sysedp_set_state(host->sysedpc, 0);
2793
2794         return;
2795 }
2796
2797 void delayed_clk_gate_cb(struct work_struct *work)
2798 {
2799         struct sdhci_host *host = container_of(work, struct sdhci_host,
2800                                               delayed_clk_gate_wrk.work);
2801
2802         /* power off check */
2803         if (host->mmc->ios.power_mode == MMC_POWER_OFF)
2804                 goto end;
2805
2806         mmc_host_clk_gate(host);
2807 end:
2808         return;
2809 }
2810 EXPORT_SYMBOL_GPL(delayed_clk_gate_cb);
2811
2812 int sdhci_disable(struct mmc_host *mmc)
2813 {
2814         struct sdhci_host *host = mmc_priv(mmc);
2815
2816         if (!mmc->card || !(mmc->caps2 & MMC_CAP2_CLOCK_GATING))
2817                 return 0;
2818
2819         if (IS_DELAYED_CLK_GATE(host)) {
2820                 if (host->is_clk_on) {
2821                         if (IS_SDIO_CARD(host))
2822                                 host->clk_gate_tmout_ticks =
2823                                         SDIO_CLK_GATING_TICK_TMOUT;
2824                         else if (IS_EMMC_CARD(host))
2825                                 host->clk_gate_tmout_ticks =
2826                                         EMMC_CLK_GATING_TICK_TMOUT;
2827                         if (host->clk_gate_tmout_ticks > 0)
2828                                 schedule_delayed_work(
2829                                         &host->delayed_clk_gate_wrk,
2830                                         host->clk_gate_tmout_ticks);
2831                 }
2832                 return 0;
2833         }
2834
2835         mmc_host_clk_gate(host);
2836
2837         return 0;
2838 }
2839
2840 #ifdef CONFIG_MMC_FREQ_SCALING
2841 /*
2842  * Wrapper functions to call any platform specific implementation for
2843  * supporting dynamic frequency scaling for SD/MMC devices.
2844  */
2845 static int sdhci_gov_get_target(struct mmc_host *mmc, unsigned long *freq)
2846 {
2847         struct sdhci_host *host = mmc_priv(mmc);
2848
2849         if (host->ops->dfs_gov_get_target_freq)
2850                 *freq = host->ops->dfs_gov_get_target_freq(host,
2851                         mmc->devfreq_stats);
2852
2853         return 0;
2854 }
2855
2856 static int sdhci_gov_init(struct mmc_host *mmc)
2857 {
2858         struct sdhci_host *host = mmc_priv(mmc);
2859
2860         if (host->ops->dfs_gov_init)
2861                 return host->ops->dfs_gov_init(host);
2862
2863         return 0;
2864 }
2865
2866 static void sdhci_gov_exit(struct mmc_host *mmc)
2867 {
2868         struct sdhci_host *host = mmc_priv(mmc);
2869
2870         if (host->ops->dfs_gov_exit)
2871                 host->ops->dfs_gov_exit(host);
2872 }
2873 #endif
2874
2875 static int sdhci_select_drive_strength(struct mmc_host *mmc,
2876                                        unsigned int max_dtr,
2877                                        int host_drv,
2878                                        int card_drv)
2879 {
2880         struct sdhci_host *host = mmc_priv(mmc);
2881         unsigned char   drv_type;
2882
2883         /* return default strength if no handler in driver */
2884         if (!host->ops->get_drive_strength)
2885                 return MMC_SET_DRIVER_TYPE_B;
2886
2887         drv_type = host->ops->get_drive_strength(host, max_dtr,
2888                         host_drv, card_drv);
2889
2890         if (drv_type > MMC_SET_DRIVER_TYPE_D) {
2891                 pr_err("%s: Error on getting drive strength. Got drv_type %d\n"
2892                         , mmc_hostname(host->mmc), drv_type);
2893                 return MMC_SET_DRIVER_TYPE_B;
2894         }
2895
2896         return drv_type;
2897 }
2898 static void sdhci_init_card(struct mmc_host *mmc, struct mmc_card *card)
2899 {
2900         struct sdhci_host *host = mmc_priv(mmc);
2901
2902         /*
2903          * Get the max pio transfer limits if defined. This would be used to
2904          * dynamically choose between dma and pio modes depending on the
2905          * transfer parameters.
2906          */
2907         if (host->ops->get_max_pio_transfer_limits)
2908                 host->ops->get_max_pio_transfer_limits(host);
2909 }
2910 static const struct mmc_host_ops sdhci_ops = {
2911         .request        = sdhci_request,
2912         .set_ios        = sdhci_set_ios,
2913         .get_cd         = sdhci_get_cd,
2914         .get_ro         = sdhci_get_ro,
2915         .hw_reset       = sdhci_hw_reset,
2916         .enable         = sdhci_enable,
2917         .disable        = sdhci_disable,
2918         .enable_sdio_irq = sdhci_enable_sdio_irq,
2919         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
2920         .execute_tuning                 = sdhci_execute_tuning,
2921         .validate_sd2_0                 = sdhci_validate_sd2_0,
2922         .card_event                     = sdhci_card_event,
2923         .card_busy      = sdhci_card_busy,
2924 #ifdef CONFIG_MMC_FREQ_SCALING
2925         .dfs_governor_init              = sdhci_gov_init,
2926         .dfs_governor_exit              = sdhci_gov_exit,
2927         .dfs_governor_get_target        = sdhci_gov_get_target,
2928 #endif
2929         .select_drive_strength          = sdhci_select_drive_strength,
2930         .post_init      = sdhci_post_init,
2931         .en_strobe      = sdhci_en_strobe,
2932         .init_card      = sdhci_init_card,
2933 };
2934
2935 /*****************************************************************************\
2936  *                                                                           *
2937  * Tasklets                                                                  *
2938  *                                                                           *
2939 \*****************************************************************************/
2940
2941 static void sdhci_tasklet_card(unsigned long param)
2942 {
2943         struct sdhci_host *host = (struct sdhci_host *)param;
2944
2945         sdhci_card_event(host->mmc);
2946
2947         mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2948 }
2949
2950 static void sdhci_tasklet_finish(unsigned long param)
2951 {
2952         struct sdhci_host *host;
2953         unsigned long flags;
2954         struct mmc_request *mrq = NULL;
2955
2956         host = (struct sdhci_host *)param;
2957
2958         spin_lock_irqsave(&host->lock, flags);
2959
2960         /*
2961          * If this tasklet gets rescheduled while running, it will
2962          * be run again afterwards but without any active request.
2963          */
2964         if (!host->mrq_cmd && !host->mrq_dat) {
2965                 spin_unlock_irqrestore(&host->lock, flags);
2966                 return;
2967         }
2968
2969         del_timer(&host->timer);
2970
2971         if (host->mrq_cmd)
2972                 mrq = host->mrq_cmd;
2973         else if (host->mrq_dat)
2974                 mrq = host->mrq_dat;
2975
2976         /*
2977          * The controller needs a reset of internal state machines
2978          * upon error conditions.
2979          */
2980         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2981             ((mrq->cmd && mrq->cmd->error) ||
2982                  (mrq->data && (mrq->data->error ||
2983                   (mrq->data->stop && mrq->data->stop->error))) ||
2984                    (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2985
2986                 /* Some controllers need this kick or reset won't work here */
2987                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2988                         /* This is to force an update */
2989                         sdhci_update_clock(host);
2990
2991                 /* Spec says we should do both at the same time */
2992                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
2993         }
2994
2995         host->mrq_cmd = NULL;
2996         host->mrq_dat = NULL;
2997         host->cmd = NULL;
2998         host->data = NULL;
2999
3000 #ifndef SDHCI_USE_LEDS_CLASS
3001         sdhci_deactivate_led(host);
3002 #endif
3003
3004         mmiowb();
3005         spin_unlock_irqrestore(&host->lock, flags);
3006
3007         mmc_request_done(host->mmc, mrq);
3008         sdhci_runtime_pm_put(host);
3009 }
3010
3011 /*
3012  * This tasklet gets scheduled to handle CMD only requests in CQ.
3013  */
3014 static void sdhci_tasklet_cmd_finish(unsigned long param)
3015 {
3016         struct sdhci_host *host;
3017         unsigned long flags;
3018         struct mmc_request *mrq;
3019
3020         host = (struct sdhci_host *)param;
3021
3022         if (!host->mrq_cmd && host->mrq_dat) {
3023                 mmc_handle_queued_request(host->mmc, MMC_HANDLE_CLR_CMD);
3024                 return;
3025         }
3026
3027         spin_lock_irqsave(&host->lock, flags);
3028
3029         /*
3030          * If this tasklet gets rescheduled while running, it will
3031          * be run again afterwards but without any active request.
3032          */
3033         if (!host->mrq_cmd) {
3034                 spin_unlock_irqrestore(&host->lock, flags);
3035                 return;
3036         }
3037
3038         del_timer(&host->timer);
3039
3040         mrq = host->mrq_cmd;
3041
3042         /*
3043          * The controller needs a reset of internal state machines
3044          * upon error conditions.
3045          */
3046         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
3047             ((mrq->cmd && mrq->cmd->error) ||
3048                  (mrq->data && (mrq->data->error ||
3049                   (mrq->data->stop && mrq->data->stop->error))) ||
3050                    (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
3051
3052                 /* Some controllers need this kick or reset won't work here */
3053                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
3054                         /* This is to force an update */
3055                         sdhci_update_clock(host);
3056
3057                 sdhci_reset(host, SDHCI_RESET_CMD);
3058         }
3059
3060         host->mrq_cmd = NULL;
3061         host->cmd = NULL;
3062
3063 #ifndef SDHCI_USE_LEDS_CLASS
3064         sdhci_deactivate_led(host);
3065 #endif
3066
3067         mmiowb();
3068         spin_unlock_irqrestore(&host->lock, flags);
3069
3070         mmc_request_done(host->mmc, mrq);
3071         sdhci_runtime_pm_put(host);
3072 }
3073
3074 /*
3075  * This tasklet gets scheduled to handle CMD with DATA requests in CQ.
3076  */
3077 static void sdhci_tasklet_dat_finish(unsigned long param)
3078 {
3079         struct sdhci_host *host;
3080         unsigned long flags;
3081         struct mmc_request *mrq;
3082
3083         host = (struct sdhci_host *)param;
3084
3085         spin_lock_irqsave(&host->lock, flags);
3086
3087         /*
3088          * If this tasklet gets rescheduled while running, it will
3089          * be run again afterwards but without any active request.
3090          */
3091         if (!host->mrq_dat) {
3092                 spin_unlock_irqrestore(&host->lock, flags);
3093                 return;
3094         }
3095
3096         del_timer(&host->timer);
3097
3098         mrq = host->mrq_dat;
3099
3100         if (host->data_early)
3101                 mrq->data_early = 1;
3102
3103         /*
3104          * The controller needs a reset of internal state machines
3105          * upon error conditions.
3106          */
3107         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
3108             ((mrq->cmd && mrq->cmd->error) ||
3109                  (mrq->data && (mrq->data->error ||
3110                   (mrq->data->stop && mrq->data->stop->error))) ||
3111                    (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
3112
3113                 /* Some controllers need this kick or reset won't work here */
3114                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
3115                         /* This is to force an update */
3116                         sdhci_update_clock(host);
3117
3118                 sdhci_reset(host, SDHCI_RESET_DATA);
3119         }
3120
3121         host->mrq_dat = NULL;
3122         host->data = NULL;
3123
3124 #ifndef SDHCI_USE_LEDS_CLASS
3125         sdhci_deactivate_led(host);
3126 #endif
3127
3128         mmiowb();
3129         spin_unlock_irqrestore(&host->lock, flags);
3130
3131         mmc_request_done(host->mmc, mrq);
3132         sdhci_runtime_pm_put(host);
3133 }
3134
3135 static void sdhci_timeout_timer(unsigned long data)
3136 {
3137         struct sdhci_host *host;
3138         unsigned long flags;
3139
3140         host = (struct sdhci_host *)data;
3141
3142         spin_lock_irqsave(&host->lock, flags);
3143
3144         if (host->mrq_cmd || host->mrq_dat) {
3145                 pr_err("%s: Timeout waiting for hardware "
3146                         "interrupt.\n", mmc_hostname(host->mmc));
3147                 sdhci_dumpregs(host);
3148
3149                 if (host->data) {
3150                         host->data->error = -ETIMEDOUT;
3151                         sdhci_finish_data(host);
3152                 } else {
3153                         if (host->cmd)
3154                                 host->cmd->error = -ETIMEDOUT;
3155                         else if (host->mrq_dat)
3156                                 host->mrq_dat->cmd->error = -ETIMEDOUT;
3157
3158                         if (MMC_CHECK_CMDQ_MODE(host))
3159                                 tasklet_schedule(&host->finish_cmd_tasklet);
3160                         else
3161                                 tasklet_schedule(&host->finish_tasklet);
3162                 }
3163         }
3164
3165         mmiowb();
3166         spin_unlock_irqrestore(&host->lock, flags);
3167 }
3168
3169 static void sdhci_tuning_timer(unsigned long data)
3170 {
3171         struct sdhci_host *host;
3172         unsigned long flags;
3173
3174         host = (struct sdhci_host *)data;
3175
3176         spin_lock_irqsave(&host->lock, flags);
3177
3178         host->flags |= SDHCI_NEEDS_RETUNING;
3179
3180         spin_unlock_irqrestore(&host->lock, flags);
3181 }
3182
3183 /*****************************************************************************\
3184  *                                                                           *
3185  * Interrupt handling                                                        *
3186  *                                                                           *
3187 \*****************************************************************************/
3188
3189 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
3190 {
3191         BUG_ON(intmask == 0);
3192
3193         if (!host->cmd) {
3194                 pr_err("%s: Got command interrupt 0x%08x even "
3195                         "though no command operation was in progress.\n",
3196                         mmc_hostname(host->mmc), (unsigned)intmask);
3197                 sdhci_dumpregs(host);
3198                 return;
3199         }
3200
3201         if (intmask & SDHCI_INT_TIMEOUT) {
3202                 host->cmd->error = -ETIMEDOUT;
3203         } else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
3204                         SDHCI_INT_INDEX)) {
3205                 host->cmd->error = -EILSEQ;
3206                 sdhci_dumpregs(host);
3207                 if (intmask & SDHCI_INT_INDEX)
3208                         pr_err("%s: Command END bit error, intmask: %x Interface clock = %uHz\n",
3209                         mmc_hostname(host->mmc), intmask, host->max_clk);
3210                 else
3211                         pr_err("%s: Command CRC error, intmask: %x Interface clock = %uHz\n",
3212                         mmc_hostname(host->mmc), intmask, host->max_clk);
3213         }
3214
3215         if (host->cmd->error) {
3216                 if (MMC_CHECK_CMDQ_MODE(host))
3217                         tasklet_schedule(&host->finish_cmd_tasklet);
3218                 else
3219                         tasklet_schedule(&host->finish_tasklet);
3220                 return;
3221         }
3222
3223         /*
3224          * The host can send and interrupt when the busy state has
3225          * ended, allowing us to wait without wasting CPU cycles.
3226          * Unfortunately this is overloaded on the "data complete"
3227          * interrupt, so we need to take some care when handling
3228          * it.
3229          *
3230          * Note: The 1.0 specification is a bit ambiguous about this
3231          *       feature so there might be some problems with older
3232          *       controllers.
3233          */
3234         if (host->cmd->flags & MMC_RSP_BUSY) {
3235                 if (host->cmd->data)
3236                         DBG("Cannot wait for busy signal when also "
3237                                 "doing a data transfer");
3238                 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
3239                         return;
3240
3241                 /* The controller does not support the end-of-busy IRQ,
3242                  * fall through and take the SDHCI_INT_RESPONSE */
3243         }
3244
3245         if (intmask & SDHCI_INT_RESPONSE)
3246                 sdhci_finish_command(host);
3247 }
3248
3249 #ifdef CONFIG_MMC_DEBUG
3250 static void sdhci_show_adma_error(struct sdhci_host *host)
3251 {
3252         const char *name = mmc_hostname(host->mmc);
3253         u8 *desc = host->adma_desc;
3254         __le32 *dma;
3255         __le16 *len;
3256         u8 attr;
3257
3258         u32 ctrl;
3259         int next_desc;
3260         ctrl = sdhci_readl(host, SDHCI_ACMD12_ERR);
3261         if (ctrl & SDHCI_ADDRESSING_64BIT_EN) {
3262                 if (ctrl & SDHCI_HOST_VERSION_4_EN)
3263                         next_desc = 16;
3264                 else
3265                         next_desc = 12;
3266         } else {
3267                 /* 32 bit DMA mode supported*/
3268                 next_desc = 8;
3269         }
3270
3271         sdhci_dumpregs(host);
3272
3273         while (true) {
3274                 dma = (__le32 *)(desc + 4);
3275                 len = (__le16 *)(desc + 2);
3276                 attr = *desc;
3277
3278                 if (next_desc == 8) {
3279                         DBG("%s: %p: DMA-32 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
3280                                 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
3281                 } else if (next_desc == 16) {
3282                         DBG("%s: %p: DMA-64 0x%16x, LEN 0x%04x, Attr=0x%02x\n",
3283                                 name, desc, le64_to_cpu(*((__le64 *)dma)), le16_to_cpu(*len), attr);
3284                 }
3285                 desc += next_desc;
3286                 if (attr & 2)
3287                         break;
3288         }
3289 }
3290 #else
3291 static void sdhci_show_adma_error(struct sdhci_host *host) { }
3292 #endif
3293
3294 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
3295 {
3296         u32 command;
3297         BUG_ON(intmask == 0);
3298
3299         /* CMD19, CMD21 generates _only_ Buffer Read Ready interrupt */
3300         if (intmask & SDHCI_INT_DATA_AVAIL) {
3301                 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
3302                 if (command == MMC_SEND_TUNING_BLOCK ||
3303                     command == MMC_SEND_TUNING_BLOCK_HS200) {
3304                         host->tuning_done = 1;
3305                         wake_up(&host->buf_ready_int);
3306                         return;
3307                 }
3308         }
3309
3310         if (!host->data) {
3311                 /*
3312                  * The "data complete" interrupt is also used to
3313                  * indicate that a busy state has ended. See comment
3314                  * above in sdhci_cmd_irq().
3315                  */
3316                 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
3317                         if (intmask & SDHCI_INT_DATA_END) {
3318                                 sdhci_finish_command(host);
3319                                 return;
3320                         }
3321                 }
3322
3323                 pr_err("%s: Got data interrupt 0x%08x even "
3324                         "though no data operation was in progress.\n",
3325                         mmc_hostname(host->mmc), (unsigned)intmask);
3326                 sdhci_dumpregs(host);
3327
3328                 return;
3329         }
3330
3331         if (intmask & SDHCI_INT_DATA_TIMEOUT) {
3332                 host->data->error = -ETIMEDOUT;
3333                 pr_err("%s: Data Timeout error, intmask: %x Interface clock = %uHz\n",
3334                         mmc_hostname(host->mmc), intmask, host->max_clk);
3335                 sdhci_dumpregs(host);
3336         } else if (intmask & SDHCI_INT_DATA_END_BIT) {
3337                 host->data->error = -EILSEQ;
3338                 pr_err("%s: Data END Bit error, intmask: %x Interface clock = %uHz\n",
3339                         mmc_hostname(host->mmc), intmask, host->max_clk);
3340         } else if ((intmask & SDHCI_INT_DATA_CRC) &&
3341                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
3342                         != MMC_BUS_TEST_R) {
3343                 host->data->error = -EILSEQ;
3344                 pr_err("%s: Data CRC error, intmask: %x Interface clock = %uHz\n",
3345                         mmc_hostname(host->mmc), intmask, host->max_clk);
3346                 sdhci_dumpregs(host);
3347         } else if (intmask & SDHCI_INT_ADMA_ERROR) {
3348                 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
3349                 sdhci_dumpregs(host);
3350                 sdhci_show_adma_error(host);
3351                 host->data->error = -EIO;
3352                 if (host->ops->adma_workaround)
3353                         host->ops->adma_workaround(host, intmask);
3354         }
3355
3356         if (host->data->error)
3357                 sdhci_finish_data(host);
3358         else {
3359                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
3360                         sdhci_transfer_pio(host);
3361
3362                 /*
3363                  * We currently don't do anything fancy with DMA
3364                  * boundaries, but as we can't disable the feature
3365                  * we need to at least restart the transfer.
3366                  *
3367                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
3368                  * should return a valid address to continue from, but as
3369                  * some controllers are faulty, don't trust them.
3370                  */
3371                 if (intmask & SDHCI_INT_DMA_END) {
3372                         u32 dmastart, dmanow;
3373                         dmastart = sg_dma_address(host->data->sg);
3374                         dmanow = dmastart + host->data->bytes_xfered;
3375                         /*
3376                          * Force update to the next DMA block boundary.
3377                          */
3378                         dmanow = (dmanow &
3379                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
3380                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
3381                         host->data->bytes_xfered = dmanow - dmastart;
3382                         DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
3383                                 " next 0x%08x\n",
3384                                 mmc_hostname(host->mmc), dmastart,
3385                                 host->data->bytes_xfered, dmanow);
3386                         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
3387                 }
3388
3389                 if (intmask & SDHCI_INT_DATA_END) {
3390                         if ((!MMC_CHECK_CMDQ_MODE(host) && host->cmd) ||
3391                                 (MMC_CHECK_CMDQ_MODE(host) && host->cmd && (host->mrq_dat->cmd == host->cmd))) {
3392
3393                                 /*
3394                                  * Data managed to finish before the
3395                                  * command completed. Make sure we do
3396                                  * things in the proper order.
3397                                  */
3398                                 host->data_early = 1;
3399                         } else
3400                                 sdhci_finish_data(host);
3401                 }
3402         }
3403 }
3404
3405 static irqreturn_t sdhci_irq(int irq, void *dev_id)
3406 {
3407         irqreturn_t result;
3408         struct sdhci_host *host = dev_id;
3409         u32 intmask, unexpected = 0;
3410         int cardint = 0, max_loops = 16;
3411
3412         spin_lock(&host->lock);
3413
3414         if (host->runtime_suspended) {
3415                 spin_unlock(&host->lock);
3416                 pr_warning("%s: got irq while runtime suspended\n",
3417                        mmc_hostname(host->mmc));
3418                 return IRQ_HANDLED;
3419         }
3420
3421         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
3422
3423         if (!intmask || intmask == 0xffffffff) {
3424                 result = IRQ_NONE;
3425                 goto out;
3426         }
3427
3428 again:
3429         DBG("*** %s got interrupt: 0x%08x\n",
3430                 mmc_hostname(host->mmc), intmask);
3431
3432         if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
3433                 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
3434                               SDHCI_CARD_PRESENT;
3435
3436                 /*
3437                  * There is a observation on i.mx esdhc.  INSERT bit will be
3438                  * immediately set again when it gets cleared, if a card is
3439                  * inserted.  We have to mask the irq to prevent interrupt
3440                  * storm which will freeze the system.  And the REMOVE gets
3441                  * the same situation.
3442                  *
3443                  * More testing are needed here to ensure it works for other
3444                  * platforms though.
3445                  */
3446                 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
3447                                                 SDHCI_INT_CARD_REMOVE);
3448                 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
3449                                                   SDHCI_INT_CARD_INSERT);
3450
3451                 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
3452                              SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3453                 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
3454                 tasklet_schedule(&host->card_tasklet);
3455         }
3456
3457 #ifdef CONFIG_CMD_DUMP
3458         if (mmc_hostname(host->mmc)[3] == '0')
3459                 dbg_add_host_log(host->mmc, 7,  intmask, 0xffffffff);
3460 #endif
3461
3462         if (intmask & SDHCI_INT_CMD_MASK) {
3463                 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
3464                         SDHCI_INT_STATUS);
3465                 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
3466         }
3467
3468         if (intmask & SDHCI_INT_DATA_MASK) {
3469                 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
3470                         SDHCI_INT_STATUS);
3471                 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
3472         }
3473
3474         if (intmask & SDHCI_INT_RETUNING_EVENT)
3475                 host->flags |= SDHCI_NEEDS_RETUNING;
3476
3477         if ((intmask & SDHCI_INT_DATA_MASK) || (intmask & SDHCI_INT_CMD_MASK))
3478                 if (host->ops->sd_error_stats)
3479                         host->ops->sd_error_stats(host, intmask);
3480
3481         intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
3482
3483         intmask &= ~SDHCI_INT_ERROR;
3484
3485         if (intmask & SDHCI_INT_BUS_POWER) {
3486                 pr_err("%s: Card is consuming too much power!\n",
3487                         mmc_hostname(host->mmc));
3488                 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
3489         }
3490
3491         intmask &= ~SDHCI_INT_BUS_POWER;
3492
3493         if (intmask & SDHCI_INT_CARD_INT)
3494                 cardint = 1;
3495
3496         intmask &= ~SDHCI_INT_CARD_INT;
3497
3498         if (intmask) {
3499                 unexpected |= intmask;
3500                 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3501         }
3502
3503         result = IRQ_HANDLED;
3504
3505         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
3506         if (intmask && --max_loops)
3507                 goto again;
3508 out:
3509         spin_unlock(&host->lock);
3510
3511         if (unexpected) {
3512                 pr_err("%s: Unexpected interrupt 0x%08x.\n",
3513                            mmc_hostname(host->mmc), unexpected);
3514                 sdhci_dumpregs(host);
3515         }
3516         /*
3517          * We have to delay this as it calls back into the driver.
3518          */
3519         if (cardint)
3520                 mmc_signal_sdio_irq(host->mmc);
3521
3522         return result;
3523 }
3524
3525 /*****************************************************************************\
3526  *                                                                           *
3527  * Suspend/resume                                                            *
3528  *                                                                           *
3529 \*****************************************************************************/
3530
3531 #ifdef CONFIG_PM
3532 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
3533 {
3534         u8 val;
3535         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
3536                         | SDHCI_WAKE_ON_INT;
3537
3538         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3539         val |= mask ;
3540         /* Avoid fake wake up */
3541         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
3542                 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
3543         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3544 }
3545 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
3546
3547 void sdhci_disable_irq_wakeups(struct sdhci_host *host)
3548 {
3549         u8 val;
3550         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
3551                         | SDHCI_WAKE_ON_INT;
3552
3553         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3554         val &= ~mask;
3555         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3556 }
3557 EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups);
3558
3559 int sdhci_suspend_host(struct sdhci_host *host)
3560 {
3561         int ret;
3562         struct mmc_host *mmc = host->mmc;
3563
3564         host->suspend_task = current;
3565
3566         if (host->ops->platform_suspend)
3567                 host->ops->platform_suspend(host);
3568
3569         sdhci_disable_card_detection(host);
3570
3571         /* Disable tuning since we are suspending */
3572         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
3573                 del_timer_sync(&host->tuning_timer);
3574                 host->flags &= ~SDHCI_NEEDS_RETUNING;
3575         }
3576
3577         /*
3578          * If eMMC cards are put in sleep state, Vccq can be disabled
3579          * but Vcc would still be powered on. In resume, we only restore
3580          * the controller context. So, set MMC_PM_KEEP_POWER flag.
3581          */
3582         if (mmc_card_can_sleep(mmc) && !(mmc->caps2 & MMC_CAP2_NO_SLEEP_CMD))
3583                 mmc->pm_flags |= MMC_PM_KEEP_POWER;
3584
3585         ret = mmc_suspend_host(host->mmc);
3586         if (ret) {
3587                 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
3588                         host->flags |= SDHCI_NEEDS_RETUNING;
3589                         mod_timer(&host->tuning_timer, jiffies +
3590                                         host->tuning_count * HZ);
3591                 }
3592
3593                 sdhci_enable_card_detection(host);
3594
3595                 host->suspend_task = NULL;
3596                 return ret;
3597         }
3598
3599         /* cancel delayed clk gate work */
3600         if (host->quirks2 & SDHCI_QUIRK2_DELAYED_CLK_GATE)
3601                 cancel_delayed_work_sync(&host->delayed_clk_gate_wrk);
3602
3603         /*
3604          * If host clock is disabled but the register access requires host
3605          * clock, then enable the clock, mask the interrupts and disable
3606          * the clock.
3607          */
3608         if (host->quirks2 & SDHCI_QUIRK2_REG_ACCESS_REQ_HOST_CLK)
3609                 if ((!host->clock && host->ops->set_clock) &&
3610                         (host->quirks2 & SDHCI_QUIRK2_DELAYED_CLK_GATE))
3611                         host->ops->set_clock(host, max(mmc->ios.clock, mmc->f_min));
3612
3613         if (mmc->pm_flags & MMC_PM_KEEP_POWER)
3614                 host->card_int_set = host->ier &
3615                         SDHCI_INT_CARD_INT;
3616
3617         if (!device_may_wakeup(mmc_dev(host->mmc))) {
3618                 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
3619
3620                 if (host->quirks2 & SDHCI_QUIRK2_REG_ACCESS_REQ_HOST_CLK)
3621                         if ((!host->clock && host->ops->set_clock) &&
3622                         (host->quirks2 & SDHCI_QUIRK2_DELAYED_CLK_GATE))
3623                                 host->ops->set_clock(host, 0);
3624
3625                 if (host->irq)
3626                         disable_irq(host->irq);
3627         } else {
3628                 sdhci_enable_irq_wakeups(host);
3629                 enable_irq_wake(host->irq);
3630
3631                 if (host->quirks2 & SDHCI_QUIRK2_REG_ACCESS_REQ_HOST_CLK)
3632                         if ((!host->clock && host->ops->set_clock) &&
3633                         (host->quirks2 & SDHCI_QUIRK2_DELAYED_CLK_GATE))
3634                                 host->ops->set_clock(host, 0);
3635         }
3636
3637         host->suspend_task = NULL;
3638
3639         return ret;
3640 }
3641
3642 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
3643
3644 int sdhci_resume_host(struct sdhci_host *host)
3645 {
3646         int ret;
3647         struct mmc_host *mmc = host->mmc;
3648
3649         host->suspend_task = current;
3650
3651
3652         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3653                 if (host->ops->enable_dma)
3654                         host->ops->enable_dma(host);
3655         }
3656
3657         if (!device_may_wakeup(mmc_dev(host->mmc))) {
3658                 if (host->irq)
3659                         enable_irq(host->irq);
3660         } else {
3661                 sdhci_disable_irq_wakeups(host);
3662                 disable_irq_wake(host->irq);
3663         }
3664
3665         if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
3666             (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
3667                 /* Card keeps power but host controller does not */
3668                 sdhci_init(host, 0);
3669                 host->pwr = 0;
3670                 host->clock = 0;
3671                 sdhci_do_set_ios(host, &host->mmc->ios);
3672         } else {
3673                 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
3674                 mmiowb();
3675         }
3676
3677         ret = mmc_resume_host(host->mmc);
3678         /* Enable card interrupt as it is overwritten in sdhci_init */
3679         if ((mmc->caps & MMC_CAP_SDIO_IRQ) &&
3680                 (mmc->pm_flags & MMC_PM_KEEP_POWER))
3681                         if (host->card_int_set)
3682                                 mmc->ops->enable_sdio_irq(mmc, true);
3683
3684         sdhci_enable_card_detection(host);
3685
3686         if (host->ops->platform_resume)
3687                 host->ops->platform_resume(host);
3688
3689         /* Set the re-tuning expiration flag */
3690         if (host->flags & SDHCI_USING_RETUNING_TIMER)
3691                 host->flags |= SDHCI_NEEDS_RETUNING;
3692
3693         host->suspend_task = NULL;
3694
3695         return ret;
3696 }
3697
3698 EXPORT_SYMBOL_GPL(sdhci_resume_host);
3699 #endif /* CONFIG_PM */
3700
3701 #ifdef CONFIG_PM_RUNTIME
3702
3703 static int sdhci_runtime_pm_get(struct sdhci_host *host)
3704 {
3705         int present;
3706
3707         if (!(host->quirks2 & SDHCI_QUIRK2_MMC_RTPM))
3708                 return 0;
3709
3710         present = mmc_gpio_get_cd(host->mmc);
3711         if (present < 0) {
3712                 /* If polling, assume that the card is always present. */
3713                 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
3714                         if (host->ops->get_cd)
3715                                 present = host->ops->get_cd(host);
3716                         else
3717                                 present = 1;
3718                 else
3719                         present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
3720                                         SDHCI_CARD_PRESENT;
3721         }
3722
3723         if ((present && !host->mmc->card && (host->runtime_suspended == false))
3724                                         || host->suspend_task == current) {
3725                 pm_runtime_get_noresume(host->mmc->parent);
3726                 return 0;
3727         }
3728
3729         return pm_runtime_get_sync(host->mmc->parent);
3730 }
3731
3732 static int sdhci_runtime_pm_put(struct sdhci_host *host)
3733 {
3734         int present;
3735
3736         if (!(host->quirks2 & SDHCI_QUIRK2_MMC_RTPM))
3737                 return 0;
3738
3739         present = mmc_gpio_get_cd(host->mmc);
3740         if (present < 0) {
3741                 /* If polling, assume that the card is always present. */
3742                 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
3743                         if (host->ops->get_cd)
3744                                 present = host->ops->get_cd(host);
3745                         else
3746                                 present = 1;
3747                 else
3748                         present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
3749                                         SDHCI_CARD_PRESENT;
3750         }
3751         if ((present && !host->mmc->card) || host->suspend_task == current) {
3752                 pm_runtime_mark_last_busy(host->mmc->parent);
3753                 pm_runtime_put_noidle(host->mmc->parent);
3754                 return 0;
3755         }
3756
3757         pm_runtime_mark_last_busy(host->mmc->parent);
3758         return pm_runtime_put_autosuspend(host->mmc->parent);
3759 }
3760
3761 int sdhci_runtime_suspend_host(struct sdhci_host *host)
3762 {
3763         unsigned long flags;
3764         int ret = 0;
3765
3766         if (!(host->quirks2 & SDHCI_QUIRK2_MMC_RTPM))
3767                 return 0;
3768
3769         if (host->quirks2 & SDHCI_QUIRK2_NON_STD_RTPM) {
3770                 spin_lock_irqsave(&host->lock, flags);
3771                 host->runtime_suspended = true;
3772                 spin_unlock_irqrestore(&host->lock, flags);
3773
3774                 if (host->mmc->ios.clock) {
3775                         sdhci_set_clock(host, 0);
3776                         if (host->ops->set_clock)
3777                                 host->ops->set_clock(host, 0);
3778                         sysedp_set_state(host->sysedpc, 0);
3779                 }
3780                 goto lbl_end;
3781         }
3782
3783         /* Disable tuning since we are suspending */
3784         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
3785                 del_timer_sync(&host->tuning_timer);
3786                 host->flags &= ~SDHCI_NEEDS_RETUNING;
3787         }
3788
3789         if (host->ops->set_clock)
3790                 host->ops->set_clock(host, host->mmc->f_min);
3791         sdhci_set_clock(host, host->mmc->f_min);
3792
3793         spin_lock_irqsave(&host->lock, flags);
3794         sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
3795         spin_unlock_irqrestore(&host->lock, flags);
3796
3797         synchronize_irq(host->irq);
3798
3799         spin_lock_irqsave(&host->lock, flags);
3800         host->runtime_suspended = true;
3801         spin_unlock_irqrestore(&host->lock, flags);
3802
3803         sdhci_set_clock(host, 0);
3804         if (host->ops->set_clock)
3805                 host->ops->set_clock(host, 0);
3806
3807 lbl_end:
3808         return ret;
3809 }
3810 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
3811
3812 int sdhci_runtime_resume_host(struct sdhci_host *host)
3813 {
3814         unsigned long flags;
3815         int ret = 0, host_flags = host->flags;
3816         unsigned int freq;
3817
3818         if (!(host->quirks2 & SDHCI_QUIRK2_MMC_RTPM))
3819                 return 0;
3820
3821         if (host->quirks2 & SDHCI_QUIRK2_NON_STD_RTPM) {
3822                 if (host->mmc->ios.clock) {
3823                         freq = host->mmc->ios.clock;
3824                 } else {
3825                         if (!host->mmc->f_min)
3826                                 host->mmc->f_min = MIN_SDMMC_FREQ;
3827                         freq = host->mmc->f_min;
3828                         host->clock = freq;
3829                 }
3830
3831                 if (host->ops->set_clock)
3832                         host->ops->set_clock(host, freq);
3833                 sdhci_set_clock(host, freq);
3834
3835                 sysedp_set_state(host->sysedpc, 1);
3836                 spin_lock_irqsave(&host->lock, flags);
3837                 host->runtime_suspended = false;
3838                 spin_unlock_irqrestore(&host->lock, flags);
3839                 goto lbl_end;
3840         }
3841
3842         if (host->ops->set_clock)
3843                 host->ops->set_clock(host, host->mmc->f_min);
3844         sdhci_set_clock(host, host->mmc->f_min);
3845
3846         if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3847                 if (host->ops->enable_dma)
3848                         host->ops->enable_dma(host);
3849         }
3850
3851         sdhci_init(host, 0);
3852
3853         /* Force clock and power re-program */
3854         host->pwr = 0;
3855         host->clock = 0;
3856         sdhci_do_set_ios(host, &host->mmc->ios);
3857
3858         if (host->mmc->ios.clock) {
3859                 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
3860         /* Do any post voltage switch platform specific configuration */
3861                 if (host->ops->switch_signal_voltage_exit)
3862                         host->ops->switch_signal_voltage_exit(host,
3863                                 host->mmc->ios.signal_voltage);
3864         }
3865
3866         if ((host_flags & SDHCI_PV_ENABLED) &&
3867                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
3868                 spin_lock_irqsave(&host->lock, flags);
3869                 sdhci_enable_preset_value(host, true);
3870                 spin_unlock_irqrestore(&host->lock, flags);
3871         }
3872
3873         /* Set the re-tuning expiration flag */
3874         if (host->flags & SDHCI_USING_RETUNING_TIMER)
3875                 host->flags |= SDHCI_NEEDS_RETUNING;
3876
3877         spin_lock_irqsave(&host->lock, flags);
3878
3879         host->runtime_suspended = false;
3880
3881         /* Enable SDIO IRQ */
3882         if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
3883                 sdhci_enable_sdio_irq_nolock(host, true);
3884
3885         /* Enable Card Detection */
3886         sdhci_enable_card_detection(host);
3887
3888         spin_unlock_irqrestore(&host->lock, flags);
3889
3890 lbl_end:
3891         return ret;
3892 }
3893 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
3894
3895 #endif
3896
3897 /*****************************************************************************\
3898  *                                                                           *
3899  * Device allocation/registration                                            *
3900  *                                                                           *
3901 \*****************************************************************************/
3902
3903 struct sdhci_host *sdhci_alloc_host(struct device *dev,
3904         size_t priv_size)
3905 {
3906         struct mmc_host *mmc;
3907         struct sdhci_host *host;
3908
3909         WARN_ON(dev == NULL);
3910
3911         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
3912         if (!mmc)
3913                 return ERR_PTR(-ENOMEM);
3914
3915         host = mmc_priv(mmc);
3916         host->mmc = mmc;
3917
3918         return host;
3919 }
3920
3921 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
3922
3923 #ifdef CONFIG_DEBUG_FS
3924 static int show_sdhci_perf_stats(struct seq_file *s, void *data)
3925 {
3926         struct sdhci_host *host = s->private;
3927         int i;
3928         u32 avg_perf2;
3929         u32 last_perf_in_class;
3930         struct data_stat_entry *stat = NULL;
3931         char buf[250];
3932         u64 my_total_bytes;
3933         u64 my_total_usecs;
3934         unsigned int overall_avg_perf2;
3935
3936         seq_printf(s, "SDHCI(%s): perf statistics stat_size=%d\n",
3937                 mmc_hostname(host->mmc),
3938                 host->sdhci_data_stat.stat_size
3939                 );
3940         if (host->sdhci_data_stat.stat_size) {
3941                 seq_printf(s, "SDHCI(%s): perf statistics:\n",
3942                         mmc_hostname(host->mmc));
3943                 seq_puts(s,
3944                 "Note: Performance figures in kilo bits per sec(kbps)\n");
3945                 seq_puts(s,
3946                 "S.No.    Block       Direction    Num blks/        Total     Total           Total          Last            Last usec          Avg kbps        Last kbps           Min kbps   Max kbps\n");
3947                 seq_puts(s,
3948                 "         Size        (R/W)        transfer         Bytes     Transfers       Time(usec)     Bytes           Duration           Perf            Perf                Perf       Perf\n");
3949         }
3950         my_total_bytes = 0;
3951         my_total_usecs = 0;
3952         for (i = 0; i < host->sdhci_data_stat.stat_size; i++) {
3953                 if (!stat)
3954                         stat = host->sdhci_data_stat.head;
3955                 else
3956                         stat = stat->next;
3957                 if (!stat) {
3958                         pr_err("%s %s: sdhci data stat head NULL i=%d\n",
3959                                 mmc_hostname(host->mmc), __func__, i);
3960                         break;
3961                 }
3962                 get_kbps_from_size_n_usec_64bit(
3963                         ((stat->total_bytes << 3) * 1000),
3964                         stat->total_usecs, &avg_perf2);
3965                 get_kbps_from_size_n_usec_32bit(
3966                         (((u32)stat->current_transferred_bytes << 3) * 1000),
3967                         stat->duration_usecs,
3968                         &last_perf_in_class);
3969                 my_total_bytes += stat->total_bytes;
3970                 my_total_usecs += stat->total_usecs;
3971                 snprintf(buf, 250,
3972                         "%2d    %4d           %c       %8d    %16lld    %8d        %16lld    %8d            %8d           %8d         %8d         %8d    %8d\n",
3973                         (i + 1),
3974                         stat->stat_blk_size,
3975                         stat->is_read ? 'R' : 'W',
3976                         stat->stat_blks_per_transfer,
3977                         stat->total_bytes,
3978                         stat->total_transfers,
3979                         stat->total_usecs,
3980                         stat->current_transferred_bytes,
3981                         stat->duration_usecs,
3982                         avg_perf2,
3983                         last_perf_in_class,
3984                         stat->min_kbps,
3985                         stat->max_kbps
3986                         );
3987                 seq_puts(s, buf);
3988         }
3989         get_kbps_from_size_n_usec_64bit(
3990                 ((my_total_bytes << 3) * 1000),
3991                 my_total_usecs, &overall_avg_perf2);
3992         snprintf(buf, 250,
3993                 "Total_bytes=%lldB, time=%lldusecs, overall kbps=%d\n",
3994                 my_total_bytes, my_total_usecs,
3995                 overall_avg_perf2);
3996         seq_puts(s, buf);
3997
3998         return 0;
3999 }
4000
4001 static int sdhci_perf_stats_dump(struct inode *inode, struct file *file)
4002 {
4003         return single_open(file, show_sdhci_perf_stats, inode->i_private);
4004 }
4005
4006 static const struct file_operations flush_sdhci_perf_stats_fops = {
4007         .open           = sdhci_perf_stats_dump,
4008         .read           = seq_read,
4009         .llseek         = seq_lseek,
4010         .release        = single_release,
4011 };
4012
4013 static int restart_sdhci_perf_stats(struct seq_file *s, void *data)
4014 {
4015         struct sdhci_host *host = s->private;
4016
4017         free_stats_nodes(host);
4018         return 0;
4019 }
4020
4021 static int sdhci_perf_stats_restart(struct inode *inode, struct file *file)
4022 {
4023         return single_open(file, restart_sdhci_perf_stats, inode->i_private);
4024 }
4025
4026 static const struct file_operations reset_sdhci_perf_stats_fops = {
4027         .open           = sdhci_perf_stats_restart,
4028         .read           = seq_read,
4029         .llseek         = seq_lseek,
4030         .release        = single_release,
4031 };
4032
4033 static void sdhci_debugfs_init(struct sdhci_host *host)
4034 {
4035         struct dentry *root = host->debugfs_root;
4036
4037         /*
4038          * debugfs nodes earlier were created from sdhci-tegra,
4039          * In this change root debugfs node is created first-come-first-serve
4040          */
4041         if (!root) {
4042                 root = debugfs_create_dir(dev_name(mmc_dev(host->mmc)), NULL);
4043                 if (IS_ERR_OR_NULL(root))
4044                         goto err_root;
4045                 host->debugfs_root = root;
4046         }
4047
4048         if (!debugfs_create_u32("enable_sdhci_perf_stats", S_IRUGO | S_IWUSR,
4049                 root, (u32 *)&host->enable_sdhci_perf_stats))
4050                 goto err_root;
4051
4052         if (!debugfs_create_file("reset_sdhci_perf_stats", S_IRUGO,
4053                 root, host, &reset_sdhci_perf_stats_fops))
4054                 goto err_root;
4055
4056         if (!debugfs_create_file("sdhci_perf_stats", S_IRUGO,
4057                 root, host, &flush_sdhci_perf_stats_fops))
4058                 goto err_root;
4059
4060         if (!debugfs_create_u32("sdhci_perf_no_data_transfer_count", S_IRUGO,
4061                 root, (u32 *)&host->no_data_transfer_count))
4062                 goto err_root;
4063
4064         if (!debugfs_create_u32("max_pio_size", S_IRUGO | S_IWUSR,
4065                 root, (u32 *)&host->max_pio_size))
4066                 goto err_root;
4067
4068         if (!debugfs_create_u32("max_pio_blocks", S_IRUGO | S_IWUSR,
4069                 root, (u32 *)&host->max_pio_blocks))
4070                 goto err_root;
4071
4072         return;
4073
4074 err_root:
4075         debugfs_remove_recursive(root);
4076         host->debugfs_root = NULL;
4077
4078         return;
4079 }
4080 #endif
4081
4082 /* runtime pm is not enabled before add host */
4083 int sdhci_add_host(struct sdhci_host *host)
4084 {
4085         struct mmc_host *mmc;
4086         u32 caps[2] = {0, 0};
4087         u32 max_current_caps;
4088         unsigned int ocr_avail;
4089         int ret;
4090
4091         WARN_ON(host == NULL);
4092         if (host == NULL)
4093                 return -EINVAL;
4094
4095         mmc = host->mmc;
4096
4097         if (debug_quirks)
4098                 host->quirks = debug_quirks;
4099         if (debug_quirks2)
4100                 host->quirks2 = debug_quirks2;
4101
4102         sdhci_reset(host, SDHCI_RESET_ALL);
4103
4104         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
4105         host->version = (host->version & SDHCI_SPEC_VER_MASK)
4106                                 >> SDHCI_SPEC_VER_SHIFT;
4107         if (host->version > SDHCI_SPEC_400) {
4108                 pr_err("%s: Unknown controller version (%d). "
4109                         "You may experience problems.\n", mmc_hostname(mmc),
4110                         host->version);
4111         }
4112
4113         host->mrq_cmd = NULL;
4114         host->mrq_dat = NULL;
4115         caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
4116                 sdhci_readl(host, SDHCI_CAPABILITIES);
4117
4118         if (host->version >= SDHCI_SPEC_300)
4119                 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
4120                         host->caps1 :
4121                         sdhci_readl(host, SDHCI_CAPABILITIES_1);
4122
4123         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
4124                 host->flags |= SDHCI_USE_SDMA;
4125         else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
4126                 DBG("Controller doesn't have SDMA capability\n");
4127         else
4128                 host->flags |= SDHCI_USE_SDMA;
4129
4130         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
4131                 (host->flags & SDHCI_USE_SDMA)) {
4132                 DBG("Disabling DMA as it is marked broken\n");
4133                 host->flags &= ~SDHCI_USE_SDMA;
4134         }
4135
4136         if ((host->version >= SDHCI_SPEC_200) &&
4137                 (caps[0] & SDHCI_CAN_DO_ADMA2))
4138                 host->flags |= SDHCI_USE_ADMA;
4139
4140         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
4141                 (host->flags & SDHCI_USE_ADMA)) {
4142                 DBG("Disabling ADMA as it is marked broken\n");
4143                 host->flags &= ~SDHCI_USE_ADMA;
4144         }
4145
4146         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
4147                 if (host->ops->enable_dma) {
4148                         if (host->ops->enable_dma(host)) {
4149                                 pr_warning("%s: No suitable DMA "
4150                                         "available. Falling back to PIO.\n",
4151                                         mmc_hostname(mmc));
4152                                 host->flags &=
4153                                         ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
4154                         }
4155                 }
4156         }
4157
4158         if (host->flags & SDHCI_USE_ADMA) {
4159                 /*
4160                  * We need to allocate descriptors for all sg entries
4161                  * (128) and potentially one alignment transfer for
4162                  * each of those entries. Simply allocating 128 bits
4163                  * for each entry
4164                  */
4165                 if (mmc_dev(host->mmc)->dma_mask &&
4166                                 mmc_dev(host->mmc)->coherent_dma_mask) {
4167                         host->adma_desc = dma_alloc_coherent(
4168                                         mmc_dev(host->mmc), (128 * 2 + 1) * 8,
4169                                         &host->adma_addr, GFP_KERNEL);
4170                         if (!host->adma_desc)
4171                                 goto err_dma_alloc;
4172
4173                         host->align_buffer = dma_alloc_coherent(
4174                                         mmc_dev(host->mmc), 128 * 8,
4175                                         &host->align_addr, GFP_KERNEL);
4176                         if (!host->align_buffer) {
4177                                 dma_free_coherent(mmc_dev(host->mmc),
4178                                                 (128 * 2 + 1) * 8,
4179                                                 host->adma_desc,
4180                                                 host->adma_addr);
4181                                 host->adma_desc = NULL;
4182                                 goto err_dma_alloc;
4183                         }
4184
4185                         host->use_dma_alloc = true;
4186
4187                         BUG_ON(host->adma_addr & 0x3);
4188                         BUG_ON(host->align_addr & 0x3);
4189                         goto out_dma_alloc;
4190                 }
4191 err_dma_alloc:
4192
4193                 host->adma_desc = kmalloc((128 * 2 + 1) * 8, GFP_KERNEL);
4194                 host->align_buffer = kmalloc(128 * 8, GFP_KERNEL);
4195                 if (!host->adma_desc || !host->align_buffer) {
4196                         kfree(host->adma_desc);
4197                         kfree(host->align_buffer);
4198                         pr_warning("%s: Unable to allocate ADMA "
4199                                 "buffers. Falling back to standard DMA.\n",
4200                                 mmc_hostname(mmc));
4201                         host->flags &= ~SDHCI_USE_ADMA;
4202                 }
4203         }
4204 out_dma_alloc:
4205
4206         /*
4207          * If we use DMA, then it's up to the caller to set the DMA
4208          * mask, but PIO does not need the hw shim so we set a new
4209          * mask here in that case.
4210          */
4211         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
4212                 host->dma_mask = DMA_BIT_MASK(64);
4213                 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
4214         }
4215
4216         if (host->version >= SDHCI_SPEC_300)
4217                 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
4218                         >> SDHCI_CLOCK_BASE_SHIFT;
4219         else
4220                 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
4221                         >> SDHCI_CLOCK_BASE_SHIFT;
4222
4223         host->max_clk *= 1000000;
4224
4225         if (mmc->caps2 & MMC_CAP2_HS533)
4226                 host->max_clk = MMC_HS533_MAX_DTR;
4227
4228         if (host->max_clk == 0 || host->quirks &
4229                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4230                 if (!host->ops->get_max_clock) {
4231                         pr_err("%s: Hardware doesn't specify base clock "
4232                                "frequency.\n", mmc_hostname(mmc));
4233                         return -ENODEV;
4234                 }
4235                 host->max_clk = host->ops->get_max_clock(host);
4236         }
4237
4238         /*
4239          * In case of Host Controller v3.00, find out whether clock
4240          * multiplier is supported.
4241          */
4242         host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
4243                         SDHCI_CLOCK_MUL_SHIFT;
4244
4245         /*
4246          * In case the value in Clock Multiplier is 0, then programmable
4247          * clock mode is not supported, otherwise the actual clock
4248          * multiplier is one more than the value of Clock Multiplier
4249          * in the Capabilities Register.
4250          */
4251         if (host->clk_mul)
4252                 host->clk_mul += 1;
4253
4254         /*
4255          * Set host parameters.
4256          */
4257         mmc->ops = &sdhci_ops;
4258         mmc->f_max = host->max_clk;
4259         if (host->ops->get_min_clock)
4260                 mmc->f_min = host->ops->get_min_clock(host);
4261         else if (host->version >= SDHCI_SPEC_300) {
4262                 if (host->clk_mul) {
4263                         mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
4264                         mmc->f_max = host->max_clk * host->clk_mul;
4265                 } else
4266                         mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
4267         } else
4268                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
4269
4270         host->timeout_clk =
4271                 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
4272         if (host->timeout_clk == 0) {
4273                 if (host->ops->get_timeout_clock) {
4274                         host->timeout_clk = host->ops->get_timeout_clock(host);
4275                 } else if (!(host->quirks &
4276                                 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
4277                         pr_err("%s: Hardware doesn't specify timeout clock "
4278                                "frequency.\n", mmc_hostname(mmc));
4279                         return -ENODEV;
4280                 }
4281         }
4282         if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
4283                 host->timeout_clk *= 1000;
4284
4285         if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
4286                 host->timeout_clk = mmc->f_max / 1000;
4287
4288         if (!(host->quirks2 & SDHCI_QUIRK2_NO_CALC_MAX_DISCARD_TO))
4289                 mmc->max_discard_to = (1 << 27) / host->timeout_clk;
4290
4291         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
4292                 host->flags |= SDHCI_AUTO_CMD12;
4293
4294         /* Auto-CMD23 stuff only works in ADMA or PIO. */
4295         if ((host->version >= SDHCI_SPEC_300) &&
4296             ((host->flags & SDHCI_USE_ADMA) ||
4297              !(host->flags & SDHCI_USE_SDMA))) {
4298                 host->flags |= SDHCI_AUTO_CMD23;
4299                 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
4300         } else {
4301                 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
4302         }
4303
4304         /*
4305          * A controller may support 8-bit width, but the board itself
4306          * might not have the pins brought out.  Boards that support
4307          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
4308          * their platform code before calling sdhci_add_host(), and we
4309          * won't assume 8-bit width for hosts without that CAP.
4310          */
4311         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
4312                 mmc->caps |= MMC_CAP_4_BIT_DATA;
4313
4314         if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
4315                 mmc->caps &= ~MMC_CAP_CMD23;
4316
4317         if (caps[0] & SDHCI_CAN_DO_HISPD)
4318                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
4319
4320         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
4321             !(host->mmc->caps & MMC_CAP_NONREMOVABLE) && !(host->ops->get_cd))
4322                 mmc->caps |= MMC_CAP_NEEDS_POLL;
4323
4324         /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
4325         host->vqmmc = regulator_get(mmc_dev(mmc), "vqmmc");
4326         if (IS_ERR_OR_NULL(host->vqmmc)) {
4327                 if (PTR_ERR(host->vqmmc) < 0) {
4328                         pr_info("%s: no vqmmc regulator found\n",
4329                                 mmc_hostname(mmc));
4330                         host->vqmmc = NULL;
4331                 }
4332         } else {
4333                 ret = regulator_enable(host->vqmmc);
4334                 if (!regulator_is_supported_voltage(host->vqmmc, 1700000,
4335                         1950000))
4336                         caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
4337                                         SDHCI_SUPPORT_SDR50 |
4338                                         SDHCI_SUPPORT_DDR50);
4339                 if (ret) {
4340                         pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
4341                                 mmc_hostname(mmc), ret);
4342                         host->vqmmc = NULL;
4343                 }
4344         }
4345
4346         if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
4347                 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4348                        SDHCI_SUPPORT_DDR50);
4349
4350         /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
4351         if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4352                        SDHCI_SUPPORT_DDR50))
4353                 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
4354
4355         /* SDR104 supports also implies SDR50 support */
4356         if (caps[1] & SDHCI_SUPPORT_SDR104)
4357                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
4358         else if (caps[1] & SDHCI_SUPPORT_SDR50)
4359                 mmc->caps |= MMC_CAP_UHS_SDR50;
4360
4361         if (caps[1] & SDHCI_SUPPORT_DDR50)
4362                 mmc->caps |= MMC_CAP_UHS_DDR50;
4363
4364         /* Does the host need tuning for SDR50? */
4365         if (caps[1] & SDHCI_USE_SDR50_TUNING)
4366                 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
4367
4368         /* Does the host need tuning for HS200? */
4369         if (mmc->caps2 & MMC_CAP2_HS200)
4370                 host->flags |= SDHCI_HS200_NEEDS_TUNING;
4371
4372         /* Driver Type(s) (A, C, D) supported by the host */
4373         if (caps[1] & SDHCI_DRIVER_TYPE_A)
4374                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
4375         if (caps[1] & SDHCI_DRIVER_TYPE_C)
4376                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
4377         if (caps[1] & SDHCI_DRIVER_TYPE_D)
4378                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
4379
4380         /* Initial value for re-tuning timer count */
4381         host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
4382                               SDHCI_RETUNING_TIMER_COUNT_SHIFT;
4383         /*
4384          * If the re-tuning timer count value is 0xF, the timer count
4385          * information should be obtained in a non-standard way.
4386          */
4387         if (host->tuning_count == 0xF) {
4388                 if (host->ops->get_tuning_counter) {
4389                         host->tuning_count =
4390                                 host->ops->get_tuning_counter(host);
4391                 } else {
4392                         host->tuning_count = 0;
4393                 }
4394         }
4395
4396         /*
4397          * In case Re-tuning Timer is not disabled, the actual value of
4398          * re-tuning timer will be 2 ^ (n - 1).
4399          */
4400         if (host->tuning_count)
4401                 host->tuning_count = 1 << (host->tuning_count - 1);
4402
4403         /* Re-tuning mode supported by the Host Controller */
4404         host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
4405                              SDHCI_RETUNING_MODE_SHIFT;
4406
4407         ocr_avail = 0;
4408
4409         host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
4410         if (IS_ERR_OR_NULL(host->vmmc)) {
4411                 if (PTR_ERR(host->vmmc) < 0) {
4412                         pr_info("%s: no vmmc regulator found\n",
4413                                 mmc_hostname(mmc));
4414                         host->vmmc = NULL;
4415                 }
4416         }
4417
4418 #ifdef CONFIG_REGULATOR
4419         /*
4420          * Voltage range check makes sense only if regulator reports
4421          * any voltage value.
4422          */
4423         if (host->vmmc && regulator_get_voltage(host->vmmc) > 0) {
4424                 ret = regulator_is_supported_voltage(host->vmmc, 2700000,
4425                         3600000);
4426                 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330)))
4427                         caps[0] &= ~SDHCI_CAN_VDD_330;
4428                 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300)))
4429                         caps[0] &= ~SDHCI_CAN_VDD_300;
4430                 ret = regulator_is_supported_voltage(host->vmmc, 1700000,
4431                         1950000);
4432                 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180)))
4433                         caps[0] &= ~SDHCI_CAN_VDD_180;
4434         }
4435 #endif /* CONFIG_REGULATOR */
4436
4437         /*
4438          * According to SD Host Controller spec v3.00, if the Host System
4439          * can afford more than 150mA, Host Driver should set XPC to 1. Also
4440          * the value is meaningful only if Voltage Support in the Capabilities
4441          * register is set. The actual current value is 4 times the register
4442          * value.
4443          */
4444         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
4445         if (!max_current_caps && host->vmmc) {
4446                 u32 curr = regulator_get_current_limit(host->vmmc);
4447                 if (curr > 0) {
4448
4449                         /* convert to SDHCI_MAX_CURRENT format */
4450                         curr = curr/1000;  /* convert to mA */
4451                         curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
4452
4453                         curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
4454                         max_current_caps =
4455                                 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
4456                                 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
4457                                 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
4458                 }
4459         }
4460
4461         if (caps[0] & SDHCI_CAN_VDD_330) {
4462                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
4463
4464                 mmc->max_current_330 = ((max_current_caps &
4465                                    SDHCI_MAX_CURRENT_330_MASK) >>
4466                                    SDHCI_MAX_CURRENT_330_SHIFT) *
4467                                    SDHCI_MAX_CURRENT_MULTIPLIER;
4468         }
4469         if (caps[0] & SDHCI_CAN_VDD_300) {
4470                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
4471
4472                 mmc->max_current_300 = ((max_current_caps &
4473                                    SDHCI_MAX_CURRENT_300_MASK) >>
4474                                    SDHCI_MAX_CURRENT_300_SHIFT) *
4475                                    SDHCI_MAX_CURRENT_MULTIPLIER;
4476         }
4477         if (caps[0] & SDHCI_CAN_VDD_180) {
4478                 ocr_avail |= MMC_VDD_165_195;
4479
4480                 mmc->max_current_180 = ((max_current_caps &
4481                                    SDHCI_MAX_CURRENT_180_MASK) >>
4482                                    SDHCI_MAX_CURRENT_180_SHIFT) *
4483                                    SDHCI_MAX_CURRENT_MULTIPLIER;
4484         }
4485
4486         mmc->ocr_avail = ocr_avail;
4487         mmc->ocr_avail_sdio = ocr_avail;
4488         if (host->ocr_avail_sdio)
4489                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
4490         mmc->ocr_avail_sd = ocr_avail;
4491         if (host->ocr_avail_sd)
4492                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
4493         else /* normal SD controllers don't support 1.8V */
4494                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
4495         mmc->ocr_avail_mmc = ocr_avail;
4496         if (host->ocr_avail_mmc)
4497                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
4498
4499         if (mmc->ocr_avail == 0) {
4500                 pr_err("%s: Hardware doesn't report any "
4501                         "support voltages.\n", mmc_hostname(mmc));
4502                 return -ENODEV;
4503         }
4504
4505         spin_lock_init(&host->lock);
4506
4507         /*
4508          * Maximum number of segments. Depends on if the hardware
4509          * can do scatter/gather or not.
4510          */
4511         if (host->flags & SDHCI_USE_ADMA)
4512                 mmc->max_segs = 128;
4513         else if (host->flags & SDHCI_USE_SDMA)
4514                 mmc->max_segs = 1;
4515         else /* PIO */
4516                 mmc->max_segs = 128;
4517
4518         /*
4519          * Maximum number of sectors in one transfer. Limited by DMA boundary
4520          * size (512KiB).
4521          */
4522         mmc->max_req_size = 524288;
4523
4524         /*
4525          * Maximum segment size. Could be one segment with the maximum number
4526          * of bytes. When doing hardware scatter/gather, each entry cannot
4527          * be larger than 64 KiB though.
4528          */
4529         if (host->flags & SDHCI_USE_ADMA) {
4530                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
4531                         mmc->max_seg_size = 65535;
4532                 else
4533                         mmc->max_seg_size = 65536;
4534         } else {
4535                 mmc->max_seg_size = mmc->max_req_size;
4536         }
4537
4538         /*
4539          * Maximum block size. This varies from controller to controller and
4540          * is specified in the capabilities register.
4541          */
4542         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
4543                 mmc->max_blk_size = 2;
4544         } else {
4545                 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
4546                                 SDHCI_MAX_BLOCK_SHIFT;
4547                 if (mmc->max_blk_size >= 3) {
4548                         pr_info("%s: Invalid maximum block size, "
4549                                 "assuming 512 bytes\n", mmc_hostname(mmc));
4550                         mmc->max_blk_size = 0;
4551                 }
4552         }
4553
4554         mmc->max_blk_size = 512 << mmc->max_blk_size;
4555
4556         /*
4557          * Maximum block count.
4558          */
4559         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
4560 #ifdef CONFIG_CMD_DUMP
4561         mmc->dbg_host_cnt = 0;
4562 #endif
4563
4564         /*
4565          * Init tasklets.
4566          */
4567         tasklet_init(&host->card_tasklet,
4568                 sdhci_tasklet_card, (unsigned long)host);
4569         tasklet_init(&host->finish_tasklet,
4570                 sdhci_tasklet_finish, (unsigned long)host);
4571         tasklet_init(&host->finish_cmd_tasklet,
4572                 sdhci_tasklet_cmd_finish, (unsigned long)host);
4573         tasklet_init(&host->finish_dat_tasklet,
4574                 sdhci_tasklet_dat_finish, (unsigned long)host);
4575
4576         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
4577
4578         if (host->version >= SDHCI_SPEC_300) {
4579                 init_waitqueue_head(&host->buf_ready_int);
4580
4581                 /* Initialize re-tuning timer */
4582                 init_timer(&host->tuning_timer);
4583                 host->tuning_timer.data = (unsigned long)host;
4584                 host->tuning_timer.function = sdhci_tuning_timer;
4585         }
4586
4587         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
4588                 mmc_hostname(mmc), host);
4589         if (ret) {
4590                 pr_err("%s: Failed to request IRQ %d: %d\n",
4591                        mmc_hostname(mmc), host->irq, ret);
4592                 goto untasklet;
4593         }
4594
4595         sdhci_init(host, 0);
4596
4597         host->sysedpc = sysedp_create_consumer(dev_name(mmc_dev(mmc)),
4598                                                dev_name(mmc_dev(mmc)));
4599
4600 #ifdef CONFIG_MMC_DEBUG
4601         sdhci_dumpregs(host);
4602 #endif
4603
4604 #ifdef SDHCI_USE_LEDS_CLASS
4605         snprintf(host->led_name, sizeof(host->led_name),
4606                 "%s::", mmc_hostname(mmc));
4607         host->led.name = host->led_name;
4608         host->led.brightness = LED_OFF;
4609         host->led.default_trigger = mmc_hostname(mmc);
4610         host->led.brightness_set = sdhci_led_control;
4611
4612         ret = led_classdev_register(mmc_dev(mmc), &host->led);
4613         if (ret) {
4614                 pr_err("%s: Failed to register LED device: %d\n",
4615                        mmc_hostname(mmc), ret);
4616                 goto reset;
4617         }
4618 #endif
4619
4620         mmiowb();
4621
4622         mmc_add_host(mmc);
4623
4624         pr_info("%s: SDHCI controller on %s [%s] using %s\n",
4625                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
4626                 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
4627                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
4628
4629         sdhci_enable_card_detection(host);
4630
4631         pm_runtime_enable(mmc_dev(mmc));
4632         pm_runtime_use_autosuspend(mmc_dev(mmc));
4633         if (host->quirks2 & SDHCI_QUIRK2_MMC_RTPM) {
4634                 /*
4635                  * Below Autosuspend delay can be increased/decreased based on
4636                  * power and perf data
4637                  */
4638                 pm_runtime_set_autosuspend_delay(mmc_dev(mmc),
4639                         MMC_RTPM_MSEC_TMOUT);
4640         }
4641         host->runtime_pm_init_done = true;
4642
4643 #ifdef CONFIG_DEBUG_FS
4644         /* Add debugfs nodes */
4645         sdhci_debugfs_init(host);
4646 #endif
4647
4648         return 0;
4649
4650 #ifdef SDHCI_USE_LEDS_CLASS
4651 reset:
4652         sdhci_reset(host, SDHCI_RESET_ALL);
4653         sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
4654         free_irq(host->irq, host);
4655 #endif
4656 untasklet:
4657         tasklet_kill(&host->card_tasklet);
4658         tasklet_kill(&host->finish_tasklet);
4659         tasklet_kill(&host->finish_cmd_tasklet);
4660         tasklet_kill(&host->finish_dat_tasklet);
4661
4662         return ret;
4663 }
4664
4665 EXPORT_SYMBOL_GPL(sdhci_add_host);
4666
4667 void sdhci_runtime_forbid(struct sdhci_host *host)
4668 {
4669         pm_runtime_forbid(mmc_dev(host->mmc));
4670 }
4671 EXPORT_SYMBOL_GPL(sdhci_runtime_forbid);
4672
4673 void sdhci_remove_host(struct sdhci_host *host, int dead)
4674 {
4675         unsigned long flags;
4676
4677         sdhci_runtime_pm_get(host);
4678         if (dead) {
4679                 spin_lock_irqsave(&host->lock, flags);
4680
4681                 host->flags |= SDHCI_DEVICE_DEAD;
4682
4683                 if (host->mrq_cmd || host->mrq_dat) {
4684                         pr_err("%s: Controller removed during "
4685                                 " transfer!\n", mmc_hostname(host->mmc));
4686
4687                         if (host->mrq_cmd) {
4688                                 host->mrq_cmd->cmd->error = -ENOMEDIUM;
4689                                 if (MMC_CHECK_CMDQ_MODE(host))
4690                                         tasklet_schedule(&host->finish_cmd_tasklet);
4691                                 else
4692                                         tasklet_schedule(&host->finish_tasklet);
4693                         }
4694                         if (host->mrq_dat) {
4695                                 host->mrq_dat->cmd->error = -ENOMEDIUM;
4696                                 if (MMC_CHECK_CMDQ_MODE(host))
4697                                         tasklet_schedule(&host->finish_dat_tasklet);
4698                                 else
4699                                         tasklet_schedule(&host->finish_tasklet);
4700                         }
4701                 }
4702
4703                 spin_unlock_irqrestore(&host->lock, flags);
4704         }
4705
4706         sdhci_disable_card_detection(host);
4707
4708         mmc_remove_host(host->mmc);
4709
4710 #ifdef SDHCI_USE_LEDS_CLASS
4711         led_classdev_unregister(&host->led);
4712 #endif
4713
4714         if (!dead)
4715                 sdhci_reset(host, SDHCI_RESET_ALL);
4716
4717         sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
4718         free_irq(host->irq, host);
4719
4720         del_timer_sync(&host->timer);
4721
4722         tasklet_kill(&host->card_tasklet);
4723         tasklet_kill(&host->finish_tasklet);
4724         tasklet_kill(&host->finish_cmd_tasklet);
4725         tasklet_kill(&host->finish_dat_tasklet);
4726
4727         if (host->vmmc) {
4728                 regulator_disable(host->vmmc);
4729                 regulator_put(host->vmmc);
4730         }
4731
4732         if (host->vqmmc) {
4733                 regulator_disable(host->vqmmc);
4734                 regulator_put(host->vqmmc);
4735         }
4736
4737         if (host->use_dma_alloc) {
4738                 dma_free_coherent(mmc_dev(host->mmc), (128 * 2 + 1) * 8,
4739                                 host->adma_desc, host->adma_addr);
4740                 dma_free_coherent(mmc_dev(host->mmc), 128 * 8,
4741                                 host->align_buffer, host->align_addr);
4742         } else {
4743                 kfree(host->adma_desc);
4744                 kfree(host->align_buffer);
4745         }
4746
4747         host->adma_desc = NULL;
4748         host->align_buffer = NULL;
4749
4750         sdhci_runtime_pm_put(host);
4751         sysedp_free_consumer(host->sysedpc);
4752         host->sysedpc = NULL;
4753 }
4754
4755 EXPORT_SYMBOL_GPL(sdhci_remove_host);
4756
4757 void sdhci_free_host(struct sdhci_host *host)
4758 {
4759         mmc_free_host(host->mmc);
4760 }
4761
4762 EXPORT_SYMBOL_GPL(sdhci_free_host);
4763
4764 /*****************************************************************************\
4765  *                                                                           *
4766  * Driver init/exit                                                          *
4767  *                                                                           *
4768 \*****************************************************************************/
4769
4770 static int __init sdhci_drv_init(void)
4771 {
4772         pr_info(DRIVER_NAME
4773                 ": Secure Digital Host Controller Interface driver\n");
4774         pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
4775
4776         return 0;
4777 }
4778
4779 static void __exit sdhci_drv_exit(void)
4780 {
4781 }
4782
4783 module_init(sdhci_drv_init);
4784 module_exit(sdhci_drv_exit);
4785
4786 module_param(debug_quirks, uint, 0444);
4787 module_param(debug_quirks2, uint, 0444);
4788
4789 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
4790 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
4791 MODULE_LICENSE("GPL");
4792
4793 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
4794 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");