bf7788ea123dae0eee2bc30bc237c33b42d3e369
[linux-3.10.git] / drivers / mmc / host / sdhci-tegra.c
1 /*
2  * Copyright (C) 2010 Google, Inc.
3  *
4  * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #include <linux/err.h>
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/platform_device.h>
21 #include <linux/clk.h>
22 #include <linux/io.h>
23 #include <linux/of.h>
24 #include <linux/of_device.h>
25 #include <linux/of_gpio.h>
26 #include <linux/gpio.h>
27 #include <linux/slab.h>
28 #include <linux/mmc/card.h>
29 #include <linux/mmc/host.h>
30 #include <linux/module.h>
31 #include <linux/mmc/sd.h>
32 #include <linux/regulator/consumer.h>
33 #include <linux/delay.h>
34 #include <linux/pm_runtime.h>
35
36 #ifndef CONFIG_ARM64
37 #include <asm/gpio.h>
38 #endif
39 #include <linux/debugfs.h>
40 #include <linux/seq_file.h>
41 #include <linux/reboot.h>
42 #include <linux/devfreq.h>
43
44 #include <mach/hardware.h>
45 #include <linux/platform_data/mmc-sdhci-tegra.h>
46 #include <mach/pinmux.h>
47 #include <mach/pm_domains.h>
48 #include <mach/clk.h>
49
50 #include "sdhci-pltfm.h"
51
52 #define SDHCI_VNDR_CLK_CTRL     0x100
53 #define SDHCI_VNDR_CLK_CTRL_SDMMC_CLK   0x1
54 #define SDHCI_VNDR_CLK_CTRL_PADPIPE_CLKEN_OVERRIDE      0x8
55 #define SDHCI_VNDR_CLK_CTRL_SPI_MODE_CLKEN_OVERRIDE     0x4
56 #define SDHCI_VNDR_CLK_CTRL_INPUT_IO_CLK                0x2
57 #define SDHCI_VNDR_CLK_CTRL_TAP_VALUE_SHIFT     16
58 #define SDHCI_VNDR_CLK_CTRL_TRIM_VALUE_SHIFT    24
59 #define SDHCI_VNDR_CLK_CTRL_SDR50_TUNING                0x20
60 #define SDHCI_VNDR_CLK_CTRL_INTERNAL_CLK        0x2
61
62 #define SDHCI_VNDR_MISC_CTRL            0x120
63 #define SDHCI_VNDR_MISC_CTRL_ENABLE_SDR104_SUPPORT      0x8
64 #define SDHCI_VNDR_MISC_CTRL_ENABLE_SDR50_SUPPORT       0x10
65 #define SDHCI_VNDR_MISC_CTRL_ENABLE_DDR50_SUPPORT       0x200
66 #define SDHCI_VNDR_MISC_CTRL_ENABLE_SD_3_0      0x20
67 #define SDHCI_VNDR_MISC_CTRL_INFINITE_ERASE_TIMEOUT     0x1
68 #define SDHCI_VNDR_MISC_CTRL_PIPE_STAGES_MASK   0x180
69
70 #define SDHCI_VNDR_PRESET_VAL0_0        0x1d4
71 #define SDCLK_FREQ_SEL_HS_SHIFT 20
72 #define SDCLK_FREQ_SEL_DEFAULT_SHIFT    10
73
74 #define SDHCI_VNDR_PRESET_VAL1_0        0x1d8
75 #define SDCLK_FREQ_SEL_SDR50_SHIFT      20
76 #define SDCLK_FREQ_SEL_SDR25_SHIFT      10
77
78 #define SDHCI_VNDR_PRESET_VAL2_0        0x1dc
79 #define SDCLK_FREQ_SEL_DDR50_SHIFT      10
80
81 #define SDMMC_SDMEMCOMPPADCTRL  0x1E0
82 #define SDMMC_SDMEMCOMPPADCTRL_VREF_SEL_MASK    0xF
83 #define SDMMC_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD_MASK       0x80000000
84
85 #define SDMMC_AUTO_CAL_CONFIG   0x1E4
86 #define SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_START    0x80000000
87 #define SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_ENABLE   0x20000000
88 #define SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET_SHIFT  0x8
89 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
90 #define SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET        0x1
91 #define SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PU_OFFSET        0x1
92 #else
93 #define SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET        0x70
94 #define SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PU_OFFSET        0x62
95 #endif
96
97 #define SDMMC_AUTO_CAL_STATUS   0x1EC
98 #define SDMMC_AUTO_CAL_STATUS_AUTO_CAL_ACTIVE   0x80000000
99 #define SDMMC_AUTO_CAL_STATUS_PULLDOWN_OFFSET   24
100 #define PULLUP_ADJUSTMENT_OFFSET        20
101
102 #define SDHOST_1V8_OCR_MASK     0x8
103 #define SDHOST_HIGH_VOLT_MIN    2700000
104 #define SDHOST_HIGH_VOLT_MAX    3600000
105 #define SDHOST_HIGH_VOLT_2V8    2800000
106 #define SDHOST_LOW_VOLT_MIN     1800000
107 #define SDHOST_LOW_VOLT_MAX     1800000
108 #define SDHOST_HIGH_VOLT_3V2    3200000
109
110 #define MAX_DIVISOR_VALUE       128
111 #define DEFAULT_SDHOST_FREQ     50000000
112
113 #define MMC_TUNING_BLOCK_SIZE_BUS_WIDTH_8       128
114 #define MMC_TUNING_BLOCK_SIZE_BUS_WIDTH_4       64
115 #define MAX_TAP_VALUES  255
116 #define TUNING_FREQ_COUNT       2
117 #define TUNING_VOLTAGES_COUNT   2
118
119 #define TUNING_RETRIES  1
120 #define SDMMC_AHB_MAX_FREQ      150000000
121 #define SDMMC_EMC_MAX_FREQ      150000000
122
123 static unsigned int uhs_max_freq_MHz[] = {
124         [MMC_TIMING_UHS_SDR50] = 100,
125         [MMC_TIMING_UHS_SDR104] = 208,
126         [MMC_TIMING_MMC_HS200] = 200,
127 };
128
129
130 /* Erratum: Version register is invalid in HW */
131 #define NVQUIRK_FORCE_SDHCI_SPEC_200            BIT(0)
132 /* Erratum: Enable block gap interrupt detection */
133 #define NVQUIRK_ENABLE_BLOCK_GAP_DET            BIT(1)
134 /* Do not enable auto calibration if the platform doesn't support */
135 #define NVQUIRK_DISABLE_AUTO_CALIBRATION        BIT(2)
136 /* Set Calibration Offsets */
137 #define NVQUIRK_SET_CALIBRATION_OFFSETS         BIT(3)
138 /* Set Drive Strengths */
139 #define NVQUIRK_SET_DRIVE_STRENGTH              BIT(4)
140 /* Enable PADPIPE CLKEN */
141 #define NVQUIRK_ENABLE_PADPIPE_CLKEN            BIT(5)
142 /* DISABLE SPI_MODE CLKEN */
143 #define NVQUIRK_DISABLE_SPI_MODE_CLKEN          BIT(6)
144 /* Set tap delay */
145 #define NVQUIRK_SET_TAP_DELAY                   BIT(7)
146 /* Set trim delay */
147 #define NVQUIRK_SET_TRIM_DELAY                  BIT(8)
148 /* Enable SDHOST v3.0 support */
149 #define NVQUIRK_ENABLE_SD_3_0                   BIT(9)
150 /* Enable SDR50 mode */
151 #define NVQUIRK_ENABLE_SDR50                    BIT(10)
152 /* Enable SDR104 mode */
153 #define NVQUIRK_ENABLE_SDR104                   BIT(11)
154 /*Enable DDR50 mode */
155 #define NVQUIRK_ENABLE_DDR50                    BIT(12)
156 /* Enable Frequency Tuning for SDR50 mode */
157 #define NVQUIRK_ENABLE_SDR50_TUNING             BIT(13)
158 /* Enable Infinite Erase Timeout*/
159 #define NVQUIRK_INFINITE_ERASE_TIMEOUT          BIT(14)
160 /* No Calibration for sdmmc4 */
161 #define NVQUIRK_DISABLE_SDMMC4_CALIB            BIT(15)
162 /* ENAABLE FEEDBACK IO CLOCK */
163 #define NVQUIRK_EN_FEEDBACK_CLK                 BIT(16)
164 /* Disable AUTO CMD23 */
165 #define NVQUIRK_DISABLE_AUTO_CMD23              BIT(17)
166 /* update PAD_E_INPUT_OR_E_PWRD bit */
167 #define NVQUIRK_SET_PAD_E_INPUT_OR_E_PWRD       BIT(18)
168 /* Shadow write xfer mode reg and write it alongwith CMD register */
169 #define NVQUIRK_SHADOW_XFER_MODE_REG            BIT(18)
170 /* In SDR50 mode, run the sdmmc controller at freq greater than
171  * 104MHz to ensure the core voltage is at 1.2V. If the core voltage
172  * is below 1.2V, CRC errors would occur during data transfers
173  */
174 #define NVQUIRK_BROKEN_SDR50_CONTROLLER_CLOCK   BIT(19)
175 /* Set Pipe stages value o zero */
176 #define NVQUIRK_SET_PIPE_STAGES_MASK_0          BIT(20)
177
178 struct sdhci_tegra_soc_data {
179         const struct sdhci_pltfm_data *pdata;
180         u32 nvquirks;
181 };
182
183 struct sdhci_tegra_sd_stats {
184         unsigned int data_crc_count;
185         unsigned int cmd_crc_count;
186         unsigned int data_to_count;
187         unsigned int cmd_to_count;
188 };
189
190 #ifdef CONFIG_MMC_FREQ_SCALING
191 struct freq_gov_params {
192         u8      idle_mon_cycles;
193         u8      polling_interval_ms;
194         u8      active_load_threshold;
195 };
196
197 static struct freq_gov_params gov_params[3] = {
198         [MMC_TYPE_MMC] = {
199                 .idle_mon_cycles = 3,
200                 .polling_interval_ms = 50,
201                 .active_load_threshold = 25,
202         },
203         [MMC_TYPE_SDIO] = {
204                 .idle_mon_cycles = 3,
205                 .polling_interval_ms = 50,
206                 .active_load_threshold = 25,
207         },
208         [MMC_TYPE_SD] = {
209                 .idle_mon_cycles = 3,
210                 .polling_interval_ms = 50,
211                 .active_load_threshold = 25,
212         },
213 };
214 #endif
215
216 enum tegra_tuning_freq {
217         TUNING_LOW_FREQ,
218         TUNING_HIGH_FREQ,
219 };
220
221 struct freq_tuning_params {
222         unsigned int    freq_hz;
223         unsigned int    nr_voltages;
224         unsigned int    voltages[TUNING_VOLTAGES_COUNT];
225 };
226
227 static struct freq_tuning_params tuning_params[TUNING_FREQ_COUNT] = {
228         [TUNING_LOW_FREQ] = {
229                 .freq_hz = 82000000,
230                 .nr_voltages = 1,
231                 .voltages = {UINT_MAX},
232         },
233 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
234         [TUNING_HIGH_FREQ] = {
235                 .freq_hz = 136000000,
236                 .nr_voltages = 2,
237                 .voltages = {ULONG_MAX, 1100},
238         },
239 #else
240         [TUNING_HIGH_FREQ] = {
241                 .freq_hz = 156000000,
242                 .nr_voltages = 2,
243                 .voltages = {ULONG_MAX, 1100},
244         },
245 #endif
246 };
247
248 struct tap_window_data {
249         unsigned int    partial_win;
250         unsigned int    full_win_begin;
251         unsigned int    full_win_end;
252         unsigned int    tuning_ui;
253         unsigned int    sampling_point;
254         bool            abandon_partial_win;
255         bool            abandon_full_win;
256 };
257
258 struct tegra_tuning_data {
259         unsigned int            best_tap_value;
260         bool                    select_partial_win;
261         bool                    nominal_vcore_tun_done;
262         bool                    override_vcore_tun_done;
263         bool                    one_shot_tuning;
264         struct tap_window_data  *tap_data[TUNING_VOLTAGES_COUNT];
265 };
266
267 struct tegra_freq_gov_data {
268         unsigned int            curr_active_load;
269         unsigned int            avg_active_load;
270         unsigned int            act_load_high_threshold;
271         unsigned int            max_idle_monitor_cycles;
272         unsigned int            curr_freq;
273         unsigned int            freqs[TUNING_FREQ_COUNT];
274         unsigned int            freq_switch_count;
275         bool                    monitor_idle_load;
276 };
277
278 struct sdhci_tegra {
279         const struct tegra_sdhci_platform_data *plat;
280         const struct sdhci_tegra_soc_data *soc_data;
281         bool    clk_enabled;
282         struct regulator *vdd_io_reg;
283         struct regulator *vdd_slot_reg;
284         struct regulator *vcore_reg;
285         /* Host controller instance */
286         unsigned int instance;
287         /* vddio_min */
288         unsigned int vddio_min_uv;
289         /* vddio_max */
290         unsigned int vddio_max_uv;
291         /* max clk supported by the platform */
292         unsigned int max_clk_limit;
293         /* max ddr clk supported by the platform */
294         unsigned int ddr_clk_limit;
295         bool card_present;
296         bool is_rail_enabled;
297         struct clk *emc_clk;
298         bool is_sdmmc_emc_clk_on;
299         struct clk *sclk;
300         bool is_sdmmc_sclk_on;
301         unsigned int emc_max_clk;
302         struct sdhci_tegra_sd_stats *sd_stat_head;
303         struct notifier_block reboot_notify;
304         bool is_parent_pllc;
305         unsigned int nominal_vcore_mv;
306         unsigned int min_vcore_override_mv;
307         /* Tuning related structures and variables */
308         /* Tuning opcode to be used */
309         unsigned int tuning_opcode;
310         /* Tuning packet size */
311         unsigned int tuning_bsize;
312         /* Tuning status */
313         unsigned int tuning_status;
314 #define TUNING_STATUS_DONE      1
315 #define TUNING_STATUS_RETUNE    2
316         /* Freq tuning information for each sampling clock freq */
317         struct tegra_tuning_data *tuning_data[TUNING_FREQ_COUNT];
318         bool set_tuning_override;
319         unsigned int best_tap_values[TUNING_FREQ_COUNT];
320         struct tegra_freq_gov_data *gov_data;
321 };
322
323 static struct clk *pll_c;
324 static struct clk *pll_p;
325 static unsigned long pll_c_rate;
326 static unsigned long pll_p_rate;
327
328 static void sdhci_tegra_set_tap_delay(struct sdhci_host *sdhci,
329         unsigned int tap_delay);
330 static unsigned long get_nearest_clock_freq(unsigned long pll_rate,
331                 unsigned long desired_rate);
332
333 static int show_error_stats_dump(struct seq_file *s, void *data)
334 {
335         struct sdhci_host *host = s->private;
336         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
337         struct sdhci_tegra *tegra_host = pltfm_host->priv;
338         struct sdhci_tegra_sd_stats *head;
339
340         seq_printf(s, "ErrorStatistics:\n");
341         seq_printf(s, "DataCRC\tCmdCRC\tDataTimeout\tCmdTimeout\n");
342         head = tegra_host->sd_stat_head;
343         if (head != NULL)
344                 seq_printf(s, "%d\t%d\t%d\t%d\n", head->data_crc_count,
345                         head->cmd_crc_count, head->data_to_count,
346                         head->cmd_to_count);
347         return 0;
348 }
349
350 static int show_dfs_stats_dump(struct seq_file *s, void *data)
351 {
352         struct sdhci_host *host = s->private;
353         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
354         struct sdhci_tegra *tegra_host = pltfm_host->priv;
355         struct tegra_freq_gov_data *gov_data = tegra_host->gov_data;
356
357         seq_printf(s, "DFS statistics:\n");
358
359         if (host->mmc->dev_stats != NULL)
360                 seq_printf(s, "Polling_period: %d\n",
361                         host->mmc->dev_stats->polling_interval);
362
363         if (gov_data != NULL) {
364                 seq_printf(s, "cur_active_load: %d\n",
365                         gov_data->curr_active_load);
366                 seq_printf(s, "avg_active_load: %d\n",
367                         gov_data->avg_active_load);
368                 seq_printf(s, "act_load_high_threshold: %d\n",
369                         gov_data->act_load_high_threshold);
370                 seq_printf(s, "freq_switch_count: %d\n",
371                         gov_data->freq_switch_count);
372         }
373         return 0;
374 }
375
376 static int sdhci_error_stats_dump(struct inode *inode, struct file *file)
377 {
378         return single_open(file, show_error_stats_dump, inode->i_private);
379 }
380
381 static int sdhci_dfs_stats_dump(struct inode *inode, struct file *file)
382 {
383         return single_open(file, show_dfs_stats_dump, inode->i_private);
384 }
385
386
387 static const struct file_operations sdhci_host_fops = {
388         .open           = sdhci_error_stats_dump,
389         .read           = seq_read,
390         .llseek         = seq_lseek,
391         .release        = single_release,
392 };
393
394 static const struct file_operations sdhci_host_dfs_fops = {
395         .open           = sdhci_dfs_stats_dump,
396         .read           = seq_read,
397         .llseek         = seq_lseek,
398         .release        = single_release,
399 };
400
401
402 static u32 tegra_sdhci_readl(struct sdhci_host *host, int reg)
403 {
404         u32 val;
405
406         if (unlikely(reg == SDHCI_PRESENT_STATE)) {
407                 /* Use wp_gpio here instead? */
408                 val = readl(host->ioaddr + reg);
409                 return val | SDHCI_WRITE_PROTECT;
410         }
411         return readl(host->ioaddr + reg);
412 }
413
414 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
415 {
416 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
417         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
418         struct sdhci_tegra *tegra_host = pltfm_host->priv;
419         const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
420
421         if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) &&
422                         (reg == SDHCI_HOST_VERSION))) {
423                 return SDHCI_SPEC_200;
424         }
425 #endif
426         return readw(host->ioaddr + reg);
427 }
428
429 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
430 {
431 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
432         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
433         struct sdhci_tegra *tegra_host = pltfm_host->priv;
434         const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
435 #endif
436
437         /* Seems like we're getting spurious timeout and crc errors, so
438          * disable signalling of them. In case of real errors software
439          * timers should take care of eventually detecting them.
440          */
441         if (unlikely(reg == SDHCI_SIGNAL_ENABLE))
442                 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC);
443
444         writel(val, host->ioaddr + reg);
445
446 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
447         if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) &&
448                         (reg == SDHCI_INT_ENABLE))) {
449                 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
450                 if (val & SDHCI_INT_CARD_INT)
451                         gap_ctrl |= 0x8;
452                 else
453                         gap_ctrl &= ~0x8;
454                 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
455         }
456 #endif
457 }
458
459 static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
460 {
461         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
462         struct sdhci_tegra *tegra_host = pltfm_host->priv;
463         const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
464
465         if (soc_data->nvquirks & NVQUIRK_SHADOW_XFER_MODE_REG) {
466                 switch (reg) {
467                 case SDHCI_TRANSFER_MODE:
468                         /*
469                          * Postpone this write, we must do it together with a
470                          * command write that is down below.
471                          */
472                         pltfm_host->xfer_mode_shadow = val;
473                         return;
474                 case SDHCI_COMMAND:
475                         writel((val << 16) | pltfm_host->xfer_mode_shadow,
476                                 host->ioaddr + SDHCI_TRANSFER_MODE);
477                         pltfm_host->xfer_mode_shadow = 0;
478                         return;
479                 }
480         }
481
482         writew(val, host->ioaddr + reg);
483 }
484
485 #ifdef CONFIG_MMC_FREQ_SCALING
486 /*
487  * Dynamic frequency calculation.
488  * The active load for the current period and the average active load
489  * are calculated at the end of each polling interval.
490  *
491  * If the current active load is greater than the threshold load, then the
492  * frequency is boosted(156MHz).
493  * If the active load is lower than the threshold, then the load is monitored
494  * for a max of three cycles before reducing the frequency(82MHz). If the
495  * average active load is lower, then the monitoring cycles is reduced.
496  *
497  * The active load threshold value for both eMMC and SDIO is set to 25 which
498  * is found to give the optimal power and performance. The polling interval is
499  * set to 50 msec.
500  *
501  * The polling interval and active load threshold values can be changed by
502  * the user through sysfs.
503 */
504 static unsigned long calculate_mmc_target_freq(
505         struct tegra_freq_gov_data *gov_data)
506 {
507         unsigned long desired_freq = gov_data->curr_freq;
508         unsigned int type = MMC_TYPE_MMC;
509
510         if (gov_data->curr_active_load >= gov_data->act_load_high_threshold) {
511                 desired_freq = gov_data->freqs[TUNING_HIGH_FREQ];
512                 gov_data->monitor_idle_load = false;
513                 gov_data->max_idle_monitor_cycles =
514                         gov_params[type].idle_mon_cycles;
515         } else {
516                 if (gov_data->monitor_idle_load) {
517                         if (!gov_data->max_idle_monitor_cycles) {
518                                 desired_freq = gov_data->freqs[TUNING_LOW_FREQ];
519                                 gov_data->max_idle_monitor_cycles =
520                                         gov_params[type].idle_mon_cycles;
521                         } else {
522                                 gov_data->max_idle_monitor_cycles--;
523                         }
524                 } else {
525                         gov_data->monitor_idle_load = true;
526                         gov_data->max_idle_monitor_cycles *=
527                                 gov_data->avg_active_load;
528                         gov_data->max_idle_monitor_cycles /= 100;
529                 }
530         }
531
532         return desired_freq;
533 }
534
535 static unsigned long calculate_sdio_target_freq(
536         struct tegra_freq_gov_data *gov_data)
537 {
538         unsigned long desired_freq = gov_data->curr_freq;
539         unsigned int type = MMC_TYPE_SDIO;
540
541         if (gov_data->curr_active_load >= gov_data->act_load_high_threshold) {
542                 desired_freq = gov_data->freqs[TUNING_HIGH_FREQ];
543                 gov_data->monitor_idle_load = false;
544                 gov_data->max_idle_monitor_cycles =
545                         gov_params[type].idle_mon_cycles;
546         } else {
547                 if (gov_data->monitor_idle_load) {
548                         if (!gov_data->max_idle_monitor_cycles) {
549                                 desired_freq = gov_data->freqs[TUNING_LOW_FREQ];
550                                 gov_data->max_idle_monitor_cycles =
551                                         gov_params[type].idle_mon_cycles;
552                         } else {
553                                 gov_data->max_idle_monitor_cycles--;
554                         }
555                 } else {
556                         gov_data->monitor_idle_load = true;
557                         gov_data->max_idle_monitor_cycles *=
558                                 gov_data->avg_active_load;
559                         gov_data->max_idle_monitor_cycles /= 100;
560                 }
561         }
562
563         return desired_freq;
564 }
565
566 static unsigned long calculate_sd_target_freq(
567         struct tegra_freq_gov_data *gov_data)
568 {
569         unsigned long desired_freq = gov_data->curr_freq;
570         unsigned int type = MMC_TYPE_SD;
571
572         if (gov_data->curr_active_load >= gov_data->act_load_high_threshold) {
573                 desired_freq = gov_data->freqs[TUNING_HIGH_FREQ];
574                 gov_data->monitor_idle_load = false;
575                 gov_data->max_idle_monitor_cycles =
576                         gov_params[type].idle_mon_cycles;
577         } else {
578                 if (gov_data->monitor_idle_load) {
579                         if (!gov_data->max_idle_monitor_cycles) {
580                                 desired_freq = gov_data->freqs[TUNING_LOW_FREQ];
581                                 gov_data->max_idle_monitor_cycles =
582                                         gov_params[type].idle_mon_cycles;
583                         } else {
584                                 gov_data->max_idle_monitor_cycles--;
585                         }
586                 } else {
587                         gov_data->monitor_idle_load = true;
588                         gov_data->max_idle_monitor_cycles *=
589                                 gov_data->avg_active_load;
590                         gov_data->max_idle_monitor_cycles /= 100;
591                 }
592         }
593
594         return desired_freq;
595 }
596
597 static unsigned long sdhci_tegra_get_target_freq(struct sdhci_host *sdhci,
598         struct devfreq_dev_status *dfs_stats)
599 {
600         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
601         struct sdhci_tegra *tegra_host = pltfm_host->priv;
602         struct tegra_freq_gov_data *gov_data = tegra_host->gov_data;
603         unsigned long freq = sdhci->mmc->actual_clock;
604
605         if (!gov_data) {
606                 dev_err(mmc_dev(sdhci->mmc),
607                         "No gov data. Continue using current freq %ld", freq);
608                 return freq;
609         }
610
611         /*
612          * If clock gating is enabled and clock is currently disabled, then
613          * return freq as 0.
614          */
615         if (!tegra_host->clk_enabled)
616                 return 0;
617
618         if (dfs_stats->total_time) {
619                 gov_data->curr_active_load = (dfs_stats->busy_time * 100) /
620                         dfs_stats->total_time;
621         } else {
622                 gov_data->curr_active_load = 0;
623         }
624
625         gov_data->avg_active_load += gov_data->curr_active_load;
626         gov_data->avg_active_load >>= 1;
627
628         if (sdhci->mmc->card) {
629                 if (sdhci->mmc->card->type == MMC_TYPE_SDIO)
630                         freq = calculate_sdio_target_freq(gov_data);
631                 else if (sdhci->mmc->card->type == MMC_TYPE_MMC)
632                         freq = calculate_mmc_target_freq(gov_data);
633                 else if (sdhci->mmc->card->type == MMC_TYPE_SD)
634                         freq = calculate_sd_target_freq(gov_data);
635                 if (gov_data->curr_freq != freq)
636                         gov_data->freq_switch_count++;
637                 gov_data->curr_freq = freq;
638         }
639
640         return freq;
641 }
642
643 static int sdhci_tegra_freq_gov_init(struct sdhci_host *sdhci)
644 {
645         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
646         struct sdhci_tegra *tegra_host = pltfm_host->priv;
647         unsigned int i;
648         unsigned int freq;
649         unsigned int type;
650
651         if (!((sdhci->mmc->ios.timing == MMC_TIMING_UHS_SDR104) ||
652                 (sdhci->mmc->ios.timing == MMC_TIMING_MMC_HS200))) {
653                 dev_info(mmc_dev(sdhci->mmc),
654                         "DFS not required for current operating mode\n");
655                 return -EACCES;
656         }
657
658         if (!tegra_host->gov_data) {
659                 tegra_host->gov_data = devm_kzalloc(mmc_dev(sdhci->mmc),
660                         sizeof(struct tegra_freq_gov_data), GFP_KERNEL);
661                 if (!tegra_host->gov_data) {
662                         dev_err(mmc_dev(sdhci->mmc),
663                                 "Failed to allocate memory for dfs data\n");
664                         return -ENOMEM;
665                 }
666         }
667
668         /* Find the supported frequencies */
669         for (i = 0; i < TUNING_FREQ_COUNT; i++) {
670                 freq = tuning_params[i].freq_hz;
671                 /*
672                  * Check the nearest possible clock with pll_c and pll_p as
673                  * the clock sources. Choose the higher frequency.
674                  */
675                 tegra_host->gov_data->freqs[i] =
676                         get_nearest_clock_freq(pll_c_rate, freq);
677                 freq = get_nearest_clock_freq(pll_p_rate, freq);
678                 if (freq > tegra_host->gov_data->freqs[i])
679                         tegra_host->gov_data->freqs[i] = freq;
680         }
681
682         tegra_host->gov_data->monitor_idle_load = false;
683         tegra_host->gov_data->curr_freq = sdhci->mmc->actual_clock;
684         if (sdhci->mmc->card) {
685                 type = sdhci->mmc->card->type;
686                 sdhci->mmc->dev_stats->polling_interval =
687                         gov_params[type].polling_interval_ms;
688                 tegra_host->gov_data->act_load_high_threshold =
689                         gov_params[type].active_load_threshold;
690                 tegra_host->gov_data->max_idle_monitor_cycles =
691                         gov_params[type].idle_mon_cycles;
692         }
693
694         return 0;
695 }
696
697 #endif
698
699 static unsigned int tegra_sdhci_get_cd(struct sdhci_host *sdhci)
700 {
701         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
702         struct sdhci_tegra *tegra_host = pltfm_host->priv;
703
704         return tegra_host->card_present;
705 }
706
707 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *sdhci)
708 {
709         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
710         struct sdhci_tegra *tegra_host = pltfm_host->priv;
711         const struct tegra_sdhci_platform_data *plat = tegra_host->plat;
712
713         if (!gpio_is_valid(plat->wp_gpio))
714                 return -1;
715
716         return gpio_get_value_cansleep(plat->wp_gpio);
717 }
718
719 static int tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
720                 unsigned int uhs)
721 {
722         u16 clk, ctrl_2;
723         u32 vndr_ctrl;
724         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
725         struct sdhci_tegra *tegra_host = pltfm_host->priv;
726         const struct tegra_sdhci_platform_data *plat = tegra_host->plat;
727
728         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
729
730         /* Select Bus Speed Mode for host */
731         /* For HS200 we need to set UHS_MODE_SEL to SDR104.
732          * It works as SDR 104 in SD 4-bit mode and HS200 in eMMC 8-bit mode.
733          */
734         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
735         switch (uhs) {
736         case MMC_TIMING_UHS_SDR12:
737                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
738                 break;
739         case MMC_TIMING_UHS_SDR25:
740                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
741                 break;
742         case MMC_TIMING_UHS_SDR50:
743                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
744                 break;
745         case MMC_TIMING_UHS_SDR104:
746         case MMC_TIMING_MMC_HS200:
747                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
748                 break;
749         case MMC_TIMING_UHS_DDR50:
750                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
751                 break;
752         }
753
754         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
755
756         if (uhs == MMC_TIMING_UHS_DDR50) {
757                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
758                 clk &= ~(0xFF << SDHCI_DIVIDER_SHIFT);
759                 clk |= 1 << SDHCI_DIVIDER_SHIFT;
760                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
761
762                 /* Set the ddr mode trim delay if required */
763                 if (plat->ddr_trim_delay != -1) {
764                         vndr_ctrl = sdhci_readl(host, SDHCI_VNDR_CLK_CTRL);
765                         vndr_ctrl &= ~(0x1F <<
766                                 SDHCI_VNDR_CLK_CTRL_TRIM_VALUE_SHIFT);
767                         vndr_ctrl |= (plat->ddr_trim_delay <<
768                                 SDHCI_VNDR_CLK_CTRL_TRIM_VALUE_SHIFT);
769                         sdhci_writel(host, vndr_ctrl, SDHCI_VNDR_CLK_CTRL);
770                 }
771         }
772         return 0;
773 }
774
775 static void sdhci_status_notify_cb(int card_present, void *dev_id)
776 {
777         struct sdhci_host *sdhci = (struct sdhci_host *)dev_id;
778         struct platform_device *pdev = to_platform_device(mmc_dev(sdhci->mmc));
779         struct tegra_sdhci_platform_data *plat;
780         unsigned int status, oldstat;
781
782         pr_debug("%s: card_present %d\n", mmc_hostname(sdhci->mmc),
783                 card_present);
784
785         plat = pdev->dev.platform_data;
786         if (!plat->mmc_data.status) {
787                 mmc_detect_change(sdhci->mmc, 0);
788                 return;
789         }
790
791         status = plat->mmc_data.status(mmc_dev(sdhci->mmc));
792
793         oldstat = plat->mmc_data.card_present;
794         plat->mmc_data.card_present = status;
795         if (status ^ oldstat) {
796                 pr_debug("%s: Slot status change detected (%d -> %d)\n",
797                         mmc_hostname(sdhci->mmc), oldstat, status);
798                 if (status && !plat->mmc_data.built_in)
799                         mmc_detect_change(sdhci->mmc, (5 * HZ) / 2);
800                 else
801                         mmc_detect_change(sdhci->mmc, 0);
802         }
803 }
804
805 static irqreturn_t carddetect_irq(int irq, void *data)
806 {
807         struct sdhci_host *sdhost = (struct sdhci_host *)data;
808         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhost);
809         struct sdhci_tegra *tegra_host = pltfm_host->priv;
810         struct platform_device *pdev = to_platform_device(mmc_dev(sdhost->mmc));
811         struct tegra_sdhci_platform_data *plat;
812
813         plat = pdev->dev.platform_data;
814
815         tegra_host->card_present =
816                         (gpio_get_value_cansleep(plat->cd_gpio) == 0);
817
818         if (tegra_host->card_present) {
819                 if (!tegra_host->is_rail_enabled) {
820                         if (tegra_host->vdd_slot_reg)
821                                 regulator_enable(tegra_host->vdd_slot_reg);
822                         if (tegra_host->vdd_io_reg)
823                                 regulator_enable(tegra_host->vdd_io_reg);
824                         tegra_host->is_rail_enabled = 1;
825                 }
826         } else {
827                 if (tegra_host->is_rail_enabled) {
828                         if (tegra_host->vdd_io_reg)
829                                 regulator_disable(tegra_host->vdd_io_reg);
830                         if (tegra_host->vdd_slot_reg)
831                                 regulator_disable(tegra_host->vdd_slot_reg);
832                         tegra_host->is_rail_enabled = 0;
833                 }
834                 /*
835                  * Set retune request as tuning should be done next time
836                  * a card is inserted.
837                  */
838                 tegra_host->tuning_status = TUNING_STATUS_RETUNE;
839         }
840
841         tasklet_schedule(&sdhost->card_tasklet);
842         return IRQ_HANDLED;
843 };
844
845 static void tegra_sdhci_reset_exit(struct sdhci_host *host, u8 mask)
846 {
847         u16 misc_ctrl;
848         u32 vendor_ctrl;
849         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
850         struct sdhci_tegra *tegra_host = pltfm_host->priv;
851         const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
852         const struct tegra_sdhci_platform_data *plat = tegra_host->plat;
853         unsigned int best_tap_value;
854
855         if (!(mask & SDHCI_RESET_ALL))
856                 return;
857
858         if (tegra_host->sd_stat_head != NULL) {
859                 tegra_host->sd_stat_head->data_crc_count = 0;
860                 tegra_host->sd_stat_head->cmd_crc_count = 0;
861                 tegra_host->sd_stat_head->data_to_count = 0;
862                 tegra_host->sd_stat_head->cmd_to_count = 0;
863         }
864
865         if (tegra_host->gov_data != NULL)
866                 tegra_host->gov_data->freq_switch_count = 0;
867
868         vendor_ctrl = sdhci_readl(host, SDHCI_VNDR_CLK_CTRL);
869         if (soc_data->nvquirks & NVQUIRK_ENABLE_PADPIPE_CLKEN) {
870                 vendor_ctrl |=
871                         SDHCI_VNDR_CLK_CTRL_PADPIPE_CLKEN_OVERRIDE;
872         }
873         if (soc_data->nvquirks & NVQUIRK_DISABLE_SPI_MODE_CLKEN) {
874                 vendor_ctrl &=
875                         ~SDHCI_VNDR_CLK_CTRL_SPI_MODE_CLKEN_OVERRIDE;
876         }
877         if (soc_data->nvquirks & NVQUIRK_EN_FEEDBACK_CLK) {
878                 vendor_ctrl &=
879                         ~SDHCI_VNDR_CLK_CTRL_INPUT_IO_CLK;
880         } else {
881                 vendor_ctrl |= SDHCI_VNDR_CLK_CTRL_INTERNAL_CLK;
882         }
883
884         if (soc_data->nvquirks & NVQUIRK_SET_TAP_DELAY) {
885                 if ((tegra_host->tuning_status == TUNING_STATUS_DONE)
886                         && (host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
887                         if (host->mmc->ios.clock >
888                                 tuning_params[TUNING_LOW_FREQ].freq_hz)
889                                 best_tap_value = tegra_host->best_tap_values[1];
890                         else
891                                 best_tap_value = tegra_host->best_tap_values[0];
892                 } else {
893                         best_tap_value = plat->tap_delay;
894                 }
895                 vendor_ctrl &= ~(0xFF << SDHCI_VNDR_CLK_CTRL_TAP_VALUE_SHIFT);
896                 vendor_ctrl |= (best_tap_value <<
897                         SDHCI_VNDR_CLK_CTRL_TAP_VALUE_SHIFT);
898         }
899
900         if (soc_data->nvquirks & NVQUIRK_SET_TRIM_DELAY) {
901                 vendor_ctrl &= ~(0x1F <<
902                 SDHCI_VNDR_CLK_CTRL_TRIM_VALUE_SHIFT);
903                 vendor_ctrl |= (plat->trim_delay <<
904                 SDHCI_VNDR_CLK_CTRL_TRIM_VALUE_SHIFT);
905         }
906         if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50_TUNING)
907                 vendor_ctrl |= SDHCI_VNDR_CLK_CTRL_SDR50_TUNING;
908         sdhci_writel(host, vendor_ctrl, SDHCI_VNDR_CLK_CTRL);
909
910         misc_ctrl = sdhci_readw(host, SDHCI_VNDR_MISC_CTRL);
911         if (soc_data->nvquirks & NVQUIRK_ENABLE_SD_3_0)
912                 misc_ctrl |= SDHCI_VNDR_MISC_CTRL_ENABLE_SD_3_0;
913         if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) {
914                 misc_ctrl |=
915                 SDHCI_VNDR_MISC_CTRL_ENABLE_SDR104_SUPPORT;
916         }
917         if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) {
918                 misc_ctrl |=
919                 SDHCI_VNDR_MISC_CTRL_ENABLE_SDR50_SUPPORT;
920         }
921         /* Enable DDR mode support only for SDMMC4 */
922         if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) {
923                 if (tegra_host->instance == 3) {
924                         misc_ctrl |=
925                         SDHCI_VNDR_MISC_CTRL_ENABLE_DDR50_SUPPORT;
926                 }
927         }
928         if (soc_data->nvquirks & NVQUIRK_INFINITE_ERASE_TIMEOUT) {
929                 misc_ctrl |=
930                 SDHCI_VNDR_MISC_CTRL_INFINITE_ERASE_TIMEOUT;
931         }
932         if (soc_data->nvquirks & NVQUIRK_SET_PIPE_STAGES_MASK_0)
933                 misc_ctrl &= ~SDHCI_VNDR_MISC_CTRL_PIPE_STAGES_MASK;
934         sdhci_writew(host, misc_ctrl, SDHCI_VNDR_MISC_CTRL);
935
936         if (soc_data->nvquirks & NVQUIRK_DISABLE_AUTO_CMD23)
937                 host->flags &= ~SDHCI_AUTO_CMD23;
938
939         /* Mask the support for any UHS modes if specified */
940         if (plat->uhs_mask & MMC_UHS_MASK_SDR104)
941                 host->mmc->caps &= ~MMC_CAP_UHS_SDR104;
942
943         if (plat->uhs_mask & MMC_UHS_MASK_DDR50)
944                 host->mmc->caps &= ~MMC_CAP_UHS_DDR50;
945
946         if (plat->uhs_mask & MMC_UHS_MASK_SDR50)
947                 host->mmc->caps &= ~MMC_CAP_UHS_SDR50;
948
949         if (plat->uhs_mask & MMC_UHS_MASK_SDR25)
950                 host->mmc->caps &= ~MMC_CAP_UHS_SDR25;
951
952         if (plat->uhs_mask & MMC_UHS_MASK_SDR12)
953                 host->mmc->caps &= ~MMC_CAP_UHS_SDR12;
954
955         if (plat->uhs_mask & MMC_MASK_HS200)
956                 host->mmc->caps2 &= ~MMC_CAP2_HS200;
957 }
958
959 static int tegra_sdhci_buswidth(struct sdhci_host *sdhci, int bus_width)
960 {
961         struct platform_device *pdev = to_platform_device(mmc_dev(sdhci->mmc));
962         const struct tegra_sdhci_platform_data *plat;
963         u32 ctrl;
964
965         plat = pdev->dev.platform_data;
966
967         ctrl = sdhci_readb(sdhci, SDHCI_HOST_CONTROL);
968         if (plat->is_8bit && bus_width == MMC_BUS_WIDTH_8) {
969                 ctrl &= ~SDHCI_CTRL_4BITBUS;
970                 ctrl |= SDHCI_CTRL_8BITBUS;
971         } else {
972                 ctrl &= ~SDHCI_CTRL_8BITBUS;
973                 if (bus_width == MMC_BUS_WIDTH_4)
974                         ctrl |= SDHCI_CTRL_4BITBUS;
975                 else
976                         ctrl &= ~SDHCI_CTRL_4BITBUS;
977         }
978         sdhci_writeb(sdhci, ctrl, SDHCI_HOST_CONTROL);
979         return 0;
980 }
981
982 /*
983 * Calculation of nearest clock frequency for desired rate:
984 * Get the divisor value, div = p / d_rate
985 * 1. If it is nearer to ceil(p/d_rate) then increment the div value by 0.5 and
986 * nearest_rate, i.e. result = p / (div + 0.5) = (p << 1)/((div << 1) + 1).
987 * 2. If not, result = p / div
988 * As the nearest clk freq should be <= to desired_rate,
989 * 3. If result > desired_rate then increment the div by 0.5
990 * and do, (p << 1)/((div << 1) + 1)
991 * 4. Else return result
992 * Here, If condtions 1 & 3 are both satisfied then to keep track of div value,
993 * defined index variable.
994 */
995 static unsigned long get_nearest_clock_freq(unsigned long pll_rate,
996                 unsigned long desired_rate)
997 {
998         unsigned long result;
999         int div;
1000         int index = 1;
1001
1002         div = pll_rate / desired_rate;
1003         if (div > MAX_DIVISOR_VALUE) {
1004                 div = MAX_DIVISOR_VALUE;
1005                 result = pll_rate / div;
1006         } else {
1007                 if ((pll_rate % desired_rate) >= (desired_rate / 2))
1008                         result = (pll_rate << 1) / ((div << 1) + index++);
1009                 else
1010                         result = pll_rate / div;
1011
1012                 if (desired_rate < result) {
1013                         /*
1014                         * Trying to get lower clock freq than desired clock,
1015                         * by increasing the divisor value by 0.5
1016                         */
1017                         result = (pll_rate << 1) / ((div << 1) + index);
1018                 }
1019         }
1020
1021         return result;
1022 }
1023
1024 static void tegra_sdhci_clock_set_parent(struct sdhci_host *host,
1025                 unsigned long desired_rate)
1026 {
1027         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1028         struct sdhci_tegra *tegra_host = pltfm_host->priv;
1029         struct clk *parent_clk;
1030         unsigned long pll_c_freq;
1031         unsigned long pll_p_freq;
1032         int rc;
1033
1034 #ifdef CONFIG_TEGRA_FPGA_PLATFORM
1035         return;
1036 #endif
1037         pll_c_freq = (pll_c_rate >= desired_rate) ?
1038                 get_nearest_clock_freq(pll_c_rate, desired_rate) : pll_c_rate;
1039         pll_p_freq = (pll_p_rate >= desired_rate) ?
1040                 get_nearest_clock_freq(pll_p_rate, desired_rate) : pll_p_rate;
1041
1042         if (pll_c_freq > pll_p_freq) {
1043                 if (!tegra_host->is_parent_pllc) {
1044                         parent_clk = pll_c;
1045                         tegra_host->is_parent_pllc = true;
1046                         clk_set_rate(pltfm_host->clk, DEFAULT_SDHOST_FREQ);
1047                 } else
1048                         return;
1049         } else if (tegra_host->is_parent_pllc) {
1050                 parent_clk = pll_p;
1051                 tegra_host->is_parent_pllc = false;
1052         } else
1053                 return;
1054
1055         rc = clk_set_parent(pltfm_host->clk, parent_clk);
1056         if (rc)
1057                 pr_err("%s: failed to set pll parent clock %d\n",
1058                         mmc_hostname(host->mmc), rc);
1059 }
1060
1061 static void tegra_sdhci_set_clk_rate(struct sdhci_host *sdhci,
1062         unsigned int clock)
1063 {
1064         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
1065         struct sdhci_tegra *tegra_host = pltfm_host->priv;
1066         const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
1067         unsigned int clk_rate;
1068         unsigned int emc_clk;
1069
1070         if (sdhci->mmc->ios.timing == MMC_TIMING_UHS_DDR50) {
1071                 /*
1072                  * In ddr mode, tegra sdmmc controller clock frequency
1073                  * should be double the card clock frequency.
1074                  */
1075                 if (tegra_host->ddr_clk_limit) {
1076                         clk_rate = tegra_host->ddr_clk_limit * 2;
1077                         if (tegra_host->emc_clk) {
1078                                 emc_clk = clk_get_rate(tegra_host->emc_clk);
1079                                 if (emc_clk == tegra_host->emc_max_clk)
1080                                         clk_rate = clock * 2;
1081                         }
1082                 } else {
1083                         clk_rate = clock * 2;
1084                 }
1085         } else {
1086                 if ((sdhci->mmc->ios.timing == MMC_TIMING_UHS_SDR50) &&
1087                 (soc_data->nvquirks & NVQUIRK_BROKEN_SDR50_CONTROLLER_CLOCK))
1088                         clk_rate = clock * 2;
1089                 else
1090                         clk_rate = clock;
1091         }
1092         if (tegra_host->max_clk_limit &&
1093                 (clk_rate > tegra_host->max_clk_limit))
1094                 clk_rate = tegra_host->max_clk_limit;
1095
1096         tegra_sdhci_clock_set_parent(sdhci, clk_rate);
1097         clk_set_rate(pltfm_host->clk, clk_rate);
1098         sdhci->max_clk = clk_get_rate(pltfm_host->clk);
1099
1100         /* FPGA supports 26MHz of clock for SDMMC. */
1101         if (tegra_platform_is_fpga())
1102                 sdhci->max_clk = 26000000;
1103 #ifdef CONFIG_MMC_FREQ_SCALING
1104         /* Set the tap delay if tuning is done and dfs is enabled */
1105         if (sdhci->mmc->df &&
1106                 (tegra_host->tuning_status == TUNING_STATUS_DONE)) {
1107                 if (clock > tuning_params[TUNING_LOW_FREQ].freq_hz)
1108                         sdhci_tegra_set_tap_delay(sdhci,
1109                                 tegra_host->best_tap_values[TUNING_HIGH_FREQ]);
1110                 else
1111                         sdhci_tegra_set_tap_delay(sdhci,
1112                                 tegra_host->best_tap_values[TUNING_LOW_FREQ]);
1113         }
1114 #endif
1115
1116 }
1117
1118 static void tegra_sdhci_set_clock(struct sdhci_host *sdhci, unsigned int clock)
1119 {
1120         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
1121         struct sdhci_tegra *tegra_host = pltfm_host->priv;
1122         struct platform_device *pdev = to_platform_device(mmc_dev(sdhci->mmc));
1123         u8 ctrl;
1124
1125         pr_debug("%s %s %u enabled=%u\n", __func__,
1126                 mmc_hostname(sdhci->mmc), clock, tegra_host->clk_enabled);
1127
1128         if (clock) {
1129                 if (!tegra_host->clk_enabled) {
1130                         pm_runtime_get_sync(&pdev->dev);
1131                         clk_prepare_enable(pltfm_host->clk);
1132                         ctrl = sdhci_readb(sdhci, SDHCI_VNDR_CLK_CTRL);
1133                         ctrl |= SDHCI_VNDR_CLK_CTRL_SDMMC_CLK;
1134                         sdhci_writeb(sdhci, ctrl, SDHCI_VNDR_CLK_CTRL);
1135                         tegra_host->clk_enabled = true;
1136                 }
1137                 tegra_sdhci_set_clk_rate(sdhci, clock);
1138                 if (tegra_host->emc_clk && (!tegra_host->is_sdmmc_emc_clk_on)) {
1139                         clk_prepare_enable(tegra_host->emc_clk);
1140                         tegra_host->is_sdmmc_emc_clk_on = true;
1141                 }
1142                 if (tegra_host->sclk && (!tegra_host->is_sdmmc_sclk_on)) {
1143                         clk_prepare_enable(tegra_host->sclk);
1144                         tegra_host->is_sdmmc_sclk_on = true;
1145                 }
1146         } else if (!clock && tegra_host->clk_enabled) {
1147                 if (tegra_host->emc_clk && tegra_host->is_sdmmc_emc_clk_on) {
1148                         clk_disable_unprepare(tegra_host->emc_clk);
1149                         tegra_host->is_sdmmc_emc_clk_on = false;
1150                 }
1151                 if (tegra_host->sclk && tegra_host->is_sdmmc_sclk_on) {
1152                         clk_disable_unprepare(tegra_host->sclk);
1153                         tegra_host->is_sdmmc_sclk_on = false;
1154                 }
1155                 ctrl = sdhci_readb(sdhci, SDHCI_VNDR_CLK_CTRL);
1156                 ctrl &= ~SDHCI_VNDR_CLK_CTRL_SDMMC_CLK;
1157                 sdhci_writeb(sdhci, ctrl, SDHCI_VNDR_CLK_CTRL);
1158                 clk_disable_unprepare(pltfm_host->clk);
1159                 pm_runtime_put_sync(&pdev->dev);
1160                 tegra_host->clk_enabled = false;
1161         }
1162 }
1163
1164 static void tegra_sdhci_do_calibration(struct sdhci_host *sdhci)
1165 {
1166         unsigned int val;
1167         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
1168         struct sdhci_tegra *tegra_host = pltfm_host->priv;
1169         const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
1170         unsigned int timeout = 10;
1171
1172         /* No Calibration for sdmmc4 */
1173         if (unlikely(soc_data->nvquirks & NVQUIRK_DISABLE_SDMMC4_CALIB) &&
1174                 (tegra_host->instance == 3))
1175                 return;
1176
1177         if (unlikely(soc_data->nvquirks & NVQUIRK_DISABLE_AUTO_CALIBRATION))
1178                 return;
1179
1180         val = sdhci_readl(sdhci, SDMMC_SDMEMCOMPPADCTRL);
1181         val &= ~SDMMC_SDMEMCOMPPADCTRL_VREF_SEL_MASK;
1182         if (soc_data->nvquirks & NVQUIRK_SET_PAD_E_INPUT_OR_E_PWRD)
1183                 val |= SDMMC_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD_MASK;
1184         val |= 0x7;
1185         sdhci_writel(sdhci, val, SDMMC_SDMEMCOMPPADCTRL);
1186
1187         /* Enable Auto Calibration*/
1188         val = sdhci_readl(sdhci, SDMMC_AUTO_CAL_CONFIG);
1189         val |= SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_ENABLE;
1190         val |= SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_START;
1191         if (unlikely(soc_data->nvquirks & NVQUIRK_SET_CALIBRATION_OFFSETS)) {
1192 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
1193                 /*
1194                  * Based on characterization results for T14x platforms,
1195                  * calibration offsets should be set only sdmmc4.
1196                  */
1197                 if (tegra_host->instance != 3)
1198                         goto skip_setting_calib_offsets;
1199 #endif
1200                 /* Program Auto cal PD offset(bits 8:14) */
1201                 val &= ~(0x7F <<
1202                         SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET_SHIFT);
1203                 val |= (SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET <<
1204                         SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET_SHIFT);
1205                 /* Program Auto cal PU offset(bits 0:6) */
1206                 val &= ~0x7F;
1207                 val |= SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PU_OFFSET;
1208         }
1209 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
1210 skip_setting_calib_offsets:
1211 #endif
1212         sdhci_writel(sdhci, val, SDMMC_AUTO_CAL_CONFIG);
1213
1214         /* Wait until the calibration is done */
1215         do {
1216                 if (!(sdhci_readl(sdhci, SDMMC_AUTO_CAL_STATUS) &
1217                         SDMMC_AUTO_CAL_STATUS_AUTO_CAL_ACTIVE))
1218                         break;
1219
1220                 mdelay(1);
1221                 timeout--;
1222         } while (timeout);
1223
1224         if (!timeout)
1225                 dev_err(mmc_dev(sdhci->mmc), "Auto calibration failed\n");
1226
1227         /* Disable Auto calibration */
1228         val = sdhci_readl(sdhci, SDMMC_AUTO_CAL_CONFIG);
1229         val &= ~SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_ENABLE;
1230         sdhci_writel(sdhci, val, SDMMC_AUTO_CAL_CONFIG);
1231
1232         if (soc_data->nvquirks & NVQUIRK_SET_PAD_E_INPUT_OR_E_PWRD) {
1233                 val = sdhci_readl(sdhci, SDMMC_SDMEMCOMPPADCTRL);
1234                 val &= ~SDMMC_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD_MASK;
1235                 sdhci_writel(sdhci, val, SDMMC_SDMEMCOMPPADCTRL);
1236         }
1237
1238         if (unlikely(soc_data->nvquirks & NVQUIRK_SET_DRIVE_STRENGTH)) {
1239                 unsigned int pulldown_code;
1240                 unsigned int pullup_code;
1241                 int pg;
1242                 int err;
1243
1244                 pg = tegra_drive_get_pingroup(mmc_dev(sdhci->mmc));
1245                 if (pg != -1) {
1246                         /* Get the pull down codes from auto cal status reg */
1247                         pulldown_code = (
1248                                 sdhci_readl(sdhci, SDMMC_AUTO_CAL_STATUS) >>
1249                                 SDMMC_AUTO_CAL_STATUS_PULLDOWN_OFFSET);
1250                         /* Set the pull down in the pinmux reg */
1251                         err = tegra_drive_pinmux_set_pull_down(pg,
1252                                 pulldown_code);
1253                         if (err)
1254                                 dev_err(mmc_dev(sdhci->mmc),
1255                                 "Failed to set pulldown codes %d err %d\n",
1256                                 pulldown_code, err);
1257
1258                         /* Calculate the pull up codes */
1259                         pullup_code = pulldown_code + PULLUP_ADJUSTMENT_OFFSET;
1260                         if (pullup_code >= TEGRA_MAX_PULL)
1261                                 pullup_code = TEGRA_MAX_PULL - 1;
1262                         /* Set the pull up code in the pinmux reg */
1263                         err = tegra_drive_pinmux_set_pull_up(pg, pullup_code);
1264                         if (err)
1265                                 dev_err(mmc_dev(sdhci->mmc),
1266                                 "Failed to set pullup codes %d err %d\n",
1267                                 pullup_code, err);
1268                 }
1269         }
1270 }
1271
1272 static int tegra_sdhci_signal_voltage_switch(struct sdhci_host *sdhci,
1273         unsigned int signal_voltage)
1274 {
1275         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
1276         struct sdhci_tegra *tegra_host = pltfm_host->priv;
1277         unsigned int min_uV = tegra_host->vddio_min_uv;
1278         unsigned int max_uV = tegra_host->vddio_max_uv;
1279         unsigned int rc = 0;
1280         u16 clk, ctrl;
1281
1282
1283         ctrl = sdhci_readw(sdhci, SDHCI_HOST_CONTROL2);
1284         if (signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
1285                 ctrl |= SDHCI_CTRL_VDD_180;
1286                 min_uV = SDHOST_LOW_VOLT_MIN;
1287                 max_uV = SDHOST_LOW_VOLT_MAX;
1288         } else if (signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1289                 if (ctrl & SDHCI_CTRL_VDD_180)
1290                         ctrl &= ~SDHCI_CTRL_VDD_180;
1291         }
1292
1293         /* Check if the slot can support the required voltage */
1294         if (min_uV > tegra_host->vddio_max_uv)
1295                 return 0;
1296
1297         /* Switch OFF the card clock to prevent glitches on the clock line */
1298         clk = sdhci_readw(sdhci, SDHCI_CLOCK_CONTROL);
1299         clk &= ~SDHCI_CLOCK_CARD_EN;
1300         sdhci_writew(sdhci, clk, SDHCI_CLOCK_CONTROL);
1301
1302         /* Set/clear the 1.8V signalling */
1303         sdhci_writew(sdhci, ctrl, SDHCI_HOST_CONTROL2);
1304
1305         /* Switch the I/O rail voltage */
1306         if (tegra_host->vdd_io_reg) {
1307                 rc = regulator_set_voltage(tegra_host->vdd_io_reg,
1308                         min_uV, max_uV);
1309                 if (rc) {
1310                         dev_err(mmc_dev(sdhci->mmc), "switching to 1.8V"
1311                         "failed . Switching back to 3.3V\n");
1312                         rc = regulator_set_voltage(tegra_host->vdd_io_reg,
1313                                 SDHOST_HIGH_VOLT_MIN,
1314                                 SDHOST_HIGH_VOLT_MAX);
1315                         if (rc)
1316                                 dev_err(mmc_dev(sdhci->mmc),
1317                                 "switching to 3.3V also failed\n");
1318                 }
1319         }
1320
1321         /* Wait for 10 msec for the voltage to be switched */
1322         mdelay(10);
1323
1324         /* Enable the card clock */
1325         clk |= SDHCI_CLOCK_CARD_EN;
1326         sdhci_writew(sdhci, clk, SDHCI_CLOCK_CONTROL);
1327
1328         /* Wait for 1 msec after enabling clock */
1329         mdelay(1);
1330
1331         return rc;
1332 }
1333
1334 static void tegra_sdhci_reset(struct sdhci_host *sdhci, u8 mask)
1335 {
1336         unsigned long timeout;
1337
1338         sdhci_writeb(sdhci, mask, SDHCI_SOFTWARE_RESET);
1339
1340         /* Wait max 100 ms */
1341         timeout = 100;
1342
1343         /* hw clears the bit when it's done */
1344         while (sdhci_readb(sdhci, SDHCI_SOFTWARE_RESET) & mask) {
1345                 if (timeout == 0) {
1346                         dev_err(mmc_dev(sdhci->mmc), "Reset 0x%x never"
1347                                 "completed.\n", (int)mask);
1348                         return;
1349                 }
1350                 timeout--;
1351                 mdelay(1);
1352         }
1353
1354         tegra_sdhci_reset_exit(sdhci, mask);
1355 }
1356
1357 static void sdhci_tegra_set_tap_delay(struct sdhci_host *sdhci,
1358         unsigned int tap_delay)
1359 {
1360         u32 vendor_ctrl;
1361
1362         /* Max tap delay value is 255 */
1363         BUG_ON(tap_delay > MAX_TAP_VALUES);
1364
1365         vendor_ctrl = sdhci_readl(sdhci, SDHCI_VNDR_CLK_CTRL);
1366         vendor_ctrl &= ~(0xFF << SDHCI_VNDR_CLK_CTRL_TAP_VALUE_SHIFT);
1367         vendor_ctrl |= (tap_delay << SDHCI_VNDR_CLK_CTRL_TAP_VALUE_SHIFT);
1368         sdhci_writel(sdhci, vendor_ctrl, SDHCI_VNDR_CLK_CTRL);
1369 }
1370
1371 static int sdhci_tegra_sd_error_stats(struct sdhci_host *host, u32 int_status)
1372 {
1373         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1374         struct sdhci_tegra *tegra_host = pltfm_host->priv;
1375         struct sdhci_tegra_sd_stats *head = tegra_host->sd_stat_head;
1376
1377         if (int_status & SDHCI_INT_DATA_CRC)
1378                 head->data_crc_count++;
1379         if (int_status & SDHCI_INT_CRC)
1380                 head->cmd_crc_count++;
1381         if (int_status & SDHCI_INT_TIMEOUT)
1382                 head->cmd_to_count++;
1383         if (int_status & SDHCI_INT_DATA_TIMEOUT)
1384                 head->data_to_count++;
1385         return 0;
1386 }
1387
1388 static void sdhci_tegra_dump_tuning_data(struct sdhci_host *sdhci, u8 freq_band)
1389 {
1390         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
1391         struct sdhci_tegra *tegra_host = pltfm_host->priv;
1392         struct tegra_tuning_data *tuning_data;
1393
1394         tuning_data = tegra_host->tuning_data[freq_band];
1395         if (tuning_data->tap_data[0]) {
1396                 dev_info(mmc_dev(sdhci->mmc), "Tuning window data at 1.25V\n");
1397                 pr_info("Partial window %d\n",
1398                         tuning_data->tap_data[0]->partial_win);
1399                 pr_info("full window start %d\n",
1400                         tuning_data->tap_data[0]->full_win_begin);
1401                 pr_info("full window end %d\n",
1402                         tuning_data->tap_data[0]->full_win_end);
1403         }
1404
1405         if ((freq_band == TUNING_HIGH_FREQ) &&
1406                 (tuning_data->tap_data[1])) {
1407                 dev_info(mmc_dev(sdhci->mmc), "Tuning window data at 1.1V\n");
1408                 pr_info("partial window %d\n",
1409                         tuning_data->tap_data[1]->partial_win);
1410                 pr_info("full window being %d\n",
1411                         tuning_data->tap_data[1]->full_win_begin);
1412                 pr_info("full window end %d\n",
1413                         tuning_data->tap_data[1]->full_win_end);
1414         }
1415                 pr_info("%s window chosen\n",
1416                         tuning_data->select_partial_win ? "partial" : "full");
1417                 pr_info("Best tap value %d\n",
1418                         tuning_data->best_tap_value);
1419 }
1420
1421 /*
1422  * Calculation of best tap value for low frequencies(82MHz).
1423  * X = Partial win, Y = Full win start, Z = Full win end.
1424  * UI = Z - X.
1425  * Full Window = Z - Y.
1426  * Taps margin = mid-point of 1/2*(curr_freq/max_frequency)*UI
1427  *                    = (1/2)*(1/2)*(82/200)*UI
1428  *                    = (0.1025)*UI
1429  * if Partial win<(0.22)*UI
1430  * best tap = Y+(0.1025*UI)
1431  * else
1432  * best tap = (X-(Z-Y))+(0.1025*UI)
1433  * If best tap<0, best tap = 0
1434  */
1435 static void calculate_low_freq_tap_value(struct sdhci_host *sdhci)
1436 {
1437         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
1438         struct sdhci_tegra *tegra_host = pltfm_host->priv;
1439         unsigned int curr_clock;
1440         unsigned int max_clock;
1441         int best_tap_value;
1442         struct tap_window_data *tap_data;
1443         struct tegra_tuning_data *tuning_data;
1444
1445         tuning_data = tegra_host->tuning_data[TUNING_LOW_FREQ];
1446         tap_data = tuning_data->tap_data[0];
1447
1448         if (tap_data->abandon_full_win) {
1449                 if (tap_data->abandon_partial_win) {
1450                         tuning_data->best_tap_value = 0;
1451                         return;
1452                 } else {
1453                         tuning_data->select_partial_win = true;
1454                         goto calculate_best_tap;
1455                 }
1456         }
1457
1458         tap_data->tuning_ui = tap_data->full_win_end - tap_data->partial_win;
1459
1460         /* Calculate the sampling point */
1461         curr_clock = sdhci->max_clk / 1000000;
1462         max_clock = uhs_max_freq_MHz[sdhci->mmc->ios.timing];
1463         tap_data->sampling_point = ((tap_data->tuning_ui * curr_clock) /
1464                 max_clock);
1465         tap_data->sampling_point >>= 2;
1466
1467         /*
1468          * Check whether partial window should be used. Use partial window
1469          * if partial window > 0.22(UI).
1470          */
1471         if ((!tap_data->abandon_partial_win) &&
1472                 (tap_data->partial_win > ((22 * tap_data->tuning_ui) / 100)))
1473                         tuning_data->select_partial_win = true;
1474
1475 calculate_best_tap:
1476         if (tuning_data->select_partial_win) {
1477                 best_tap_value = (tap_data->partial_win -
1478                         (tap_data->full_win_end - tap_data->full_win_begin)) +
1479                         tap_data->sampling_point;
1480                 tuning_data->best_tap_value = (best_tap_value < 0) ? 0 :
1481                         best_tap_value;
1482         } else {
1483                 tuning_data->best_tap_value = tap_data->full_win_begin +
1484                         tap_data->sampling_point;
1485         }
1486 }
1487
1488 /*
1489  * Calculation of best tap value for high frequencies(156MHz).
1490  * Tap window data at 1.25V core voltage
1491  * X = Partial win, Y = Full win start, Z = Full win end.
1492  * Full Window = Z-Y.
1493  * UI = Z-X.
1494  * Tap_margin = (0.20375)UI
1495  *
1496  * Tap window data at 1.1V core voltage
1497  * X' = Partial win, Y' = Full win start, Z' = Full win end.
1498  * UI' = Z'-X'.
1499  * Full Window' = Z'-Y'.
1500  * Tap_margin' = (0.20375)UI'
1501  *
1502  * Full_window_tap=[(Z'-0.20375UI')+(Y+0.20375UI)]/2
1503  * Partial_window_tap=[(X'-0.20375UI')+(X-(Z-Y)+0x20375UI)]/2
1504  * if(Partial_window_tap < 0), Partial_window_tap=0
1505  *
1506  * Full_window_quality=[(Z'-0.20375UI')-(Y+0.20375UI)]/2
1507  * Partial_window_quality=(X'-0.20375UI')-Partial_window_tap
1508  * if(Full_window_quality>Partial_window_quality) choose full window,
1509  * else choose partial window.
1510  * If there is no margin window for both cases,
1511  * best tap=(Y+Z')/2.
1512  */
1513 static void calculate_high_freq_tap_value(struct sdhci_host *sdhci)
1514 {
1515         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
1516         struct sdhci_tegra *tegra_host = pltfm_host->priv;
1517         unsigned int curr_clock;
1518         unsigned int max_clock;
1519         struct tap_window_data *vmax_tap_data;
1520         struct tap_window_data *vmid_tap_data;
1521         struct tegra_tuning_data *tuning_data;
1522         unsigned int full_win_tap;
1523         int partial_win_start;
1524         int partial_win_tap;
1525         int full_win_quality;
1526         int partial_win_quality;
1527
1528         tuning_data = tegra_host->tuning_data[TUNING_HIGH_FREQ];
1529         vmax_tap_data = tuning_data->tap_data[0];
1530         vmid_tap_data = tuning_data->tap_data[1];
1531
1532         /*
1533          * If tuning at min override voltage is not done or one shot tuning is
1534          * done, set the best tap value as 50% of the full window.
1535          */
1536         if (!tuning_data->override_vcore_tun_done ||
1537                 tuning_data->one_shot_tuning) {
1538                 dev_info(mmc_dev(sdhci->mmc),
1539                         "Setting best tap as 50 percent of the full window\n");
1540                 tuning_data->best_tap_value = (vmax_tap_data->full_win_begin +
1541                         ((vmax_tap_data->full_win_end -
1542                         vmax_tap_data->full_win_begin) >> 1));
1543                 return;
1544         }
1545
1546         curr_clock = sdhci->max_clk / 1000000;
1547         max_clock = uhs_max_freq_MHz[sdhci->mmc->ios.timing];
1548
1549         /*
1550          * Calculate the tuning_ui and sampling points for tap windows found
1551          * at all core voltages.
1552          */
1553         vmax_tap_data->tuning_ui = vmax_tap_data->full_win_end -
1554                 vmax_tap_data->partial_win;
1555         vmax_tap_data->sampling_point =
1556                 (vmax_tap_data->tuning_ui * curr_clock) / max_clock;
1557         vmax_tap_data->sampling_point >>= 2;
1558
1559         vmid_tap_data->tuning_ui = vmid_tap_data->full_win_end -
1560                 vmid_tap_data->partial_win;
1561         vmid_tap_data->sampling_point =
1562                 (vmid_tap_data->tuning_ui * curr_clock) / max_clock;
1563         vmid_tap_data->sampling_point >>= 2;
1564
1565         full_win_tap = ((vmid_tap_data->full_win_end -
1566                 vmid_tap_data->sampling_point) +
1567                 (vmax_tap_data->full_win_begin +
1568                 vmax_tap_data->sampling_point));
1569         full_win_tap >>= 1;
1570         full_win_quality = (vmid_tap_data->full_win_end -
1571                 vmid_tap_data->sampling_point) -
1572                 (vmax_tap_data->full_win_begin +
1573                 vmax_tap_data->sampling_point);
1574         full_win_quality >>= 1;
1575
1576         partial_win_start = (vmax_tap_data->partial_win -
1577                 (vmax_tap_data->full_win_end -
1578                 vmax_tap_data->full_win_begin));
1579         partial_win_tap = ((vmid_tap_data->partial_win -
1580                 vmid_tap_data->sampling_point) +
1581                 (partial_win_start + vmax_tap_data->sampling_point)) / 2;
1582         if (partial_win_tap < 0)
1583                 partial_win_tap = 0;
1584         partial_win_quality = (vmid_tap_data->partial_win -
1585                 vmid_tap_data->sampling_point) - partial_win_tap;
1586
1587         if ((full_win_quality <= 0) && (partial_win_quality)) {
1588                 dev_warn(mmc_dev(sdhci->mmc),
1589                         "No margin window for both windows\n");
1590                 tuning_data->best_tap_value = vmax_tap_data->full_win_begin +
1591                         vmid_tap_data->full_win_end;
1592                 tuning_data->best_tap_value >>= 1;
1593         } else {
1594                 if (full_win_quality > partial_win_quality) {
1595                         tuning_data->best_tap_value = full_win_tap;
1596                 } else {
1597                         tuning_data->best_tap_value = partial_win_tap;
1598                         tuning_data->select_partial_win = true;
1599                 }
1600         }
1601 }
1602
1603 static int sdhci_tegra_run_frequency_tuning(struct sdhci_host *sdhci)
1604 {
1605         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
1606         struct sdhci_tegra *tegra_host = pltfm_host->priv;
1607         int err = 0;
1608         u8 ctrl;
1609         u32 mask;
1610         unsigned int timeout = 10;
1611         int flags;
1612         u32 intstatus;
1613
1614         mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
1615         while (sdhci_readl(sdhci, SDHCI_PRESENT_STATE) & mask) {
1616                 if (timeout == 0) {
1617                         dev_err(mmc_dev(sdhci->mmc), "Controller never"
1618                                 "released inhibit bit(s).\n");
1619                         err = -ETIMEDOUT;
1620                         goto out;
1621                 }
1622                 timeout--;
1623                 mdelay(1);
1624         }
1625
1626         ctrl = sdhci_readb(sdhci, SDHCI_HOST_CONTROL2);
1627         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1628         sdhci_writeb(sdhci, ctrl, SDHCI_HOST_CONTROL2);
1629
1630         ctrl = sdhci_readb(sdhci, SDHCI_HOST_CONTROL2);
1631         ctrl |= SDHCI_CTRL_EXEC_TUNING;
1632         sdhci_writeb(sdhci, ctrl, SDHCI_HOST_CONTROL2);
1633
1634         /*
1635          * In response to CMD19, the card sends 64 bytes of tuning
1636          * block to the Host Controller. So we set the block size
1637          * to 64 here.
1638          * In response to CMD21, the card sends 128 bytes of tuning
1639          * block for MMC_BUS_WIDTH_8 and 64 bytes for MMC_BUS_WIDTH_4
1640          * to the Host Controller. So we set the block size to 64 here.
1641          */
1642         sdhci_writew(sdhci, SDHCI_MAKE_BLKSZ(7, tegra_host->tuning_bsize),
1643                 SDHCI_BLOCK_SIZE);
1644
1645         sdhci_writeb(sdhci, 0xE, SDHCI_TIMEOUT_CONTROL);
1646
1647         sdhci_writew(sdhci, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1648
1649         sdhci_writel(sdhci, 0x0, SDHCI_ARGUMENT);
1650
1651         /* Set the cmd flags */
1652         flags = SDHCI_CMD_RESP_SHORT | SDHCI_CMD_CRC | SDHCI_CMD_DATA;
1653         /* Issue the command */
1654         sdhci_writew(sdhci, SDHCI_MAKE_CMD(
1655                 tegra_host->tuning_opcode, flags), SDHCI_COMMAND);
1656
1657         timeout = 5;
1658         do {
1659                 timeout--;
1660                 mdelay(1);
1661                 intstatus = sdhci_readl(sdhci, SDHCI_INT_STATUS);
1662                 if (intstatus) {
1663                         sdhci_writel(sdhci, intstatus, SDHCI_INT_STATUS);
1664                         break;
1665                 }
1666         } while(timeout);
1667
1668         if ((intstatus & SDHCI_INT_DATA_AVAIL) &&
1669                 !(intstatus & SDHCI_INT_DATA_CRC)) {
1670                 err = 0;
1671                 sdhci->tuning_done = 1;
1672         } else {
1673                 tegra_sdhci_reset(sdhci, SDHCI_RESET_CMD);
1674                 tegra_sdhci_reset(sdhci, SDHCI_RESET_DATA);
1675                 err = -EIO;
1676         }
1677
1678         if (sdhci->tuning_done) {
1679                 sdhci->tuning_done = 0;
1680                 ctrl = sdhci_readb(sdhci, SDHCI_HOST_CONTROL2);
1681                 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING) &&
1682                         (ctrl & SDHCI_CTRL_TUNED_CLK))
1683                         err = 0;
1684                 else
1685                         err = -EIO;
1686         }
1687         mdelay(1);
1688 out:
1689         return err;
1690 }
1691
1692 static int sdhci_tegra_scan_tap_values(struct sdhci_host *sdhci,
1693         unsigned int starting_tap, bool expect_failure)
1694 {
1695         unsigned int tap_value = starting_tap;
1696         int err;
1697         unsigned int retry = TUNING_RETRIES;
1698
1699         do {
1700                 /* Set the tap delay */
1701                 sdhci_tegra_set_tap_delay(sdhci, tap_value);
1702
1703                 /* Run frequency tuning */
1704                 err = sdhci_tegra_run_frequency_tuning(sdhci);
1705                 if (err && retry) {
1706                         retry--;
1707                         continue;
1708                 } else {
1709                         retry = TUNING_RETRIES;
1710                         if ((expect_failure && !err) ||
1711                                 (!expect_failure && err))
1712                                 break;
1713                 }
1714                 tap_value++;
1715         } while (tap_value <= MAX_TAP_VALUES);
1716
1717         return tap_value;
1718 }
1719
1720 /*
1721  * While scanning for tap values, first get the partial window followed by the
1722  * full window. Note that, when scanning for full win start, tuning has to be
1723  * run until a passing tap value is found. Hence, failure is expected during
1724  * this process and ignored.
1725  */
1726 static int sdhci_tegra_get_tap_window_data(struct sdhci_host *sdhci,
1727         struct tap_window_data *tap_data)
1728 {
1729         unsigned int tap_value;
1730         int err = 0;
1731
1732         if (!tap_data) {
1733                 dev_err(mmc_dev(sdhci->mmc), "Invalid tap data\n");
1734                 return -ENODATA;
1735         }
1736
1737         /* Get the partial window data */
1738         tap_value = 0;
1739         tap_value = sdhci_tegra_scan_tap_values(sdhci, tap_value, false);
1740         if (!tap_value) {
1741                 tap_data->abandon_partial_win = true;
1742                 tap_data->partial_win = 0;
1743         } else if (tap_value > MAX_TAP_VALUES) {
1744                 /*
1745                  * If tap value is more than 0xFF, we have hit the miracle case
1746                  * of all tap values passing. Discard full window as passing
1747                  * window has covered all taps.
1748                  */
1749                 tap_data->partial_win = MAX_TAP_VALUES;
1750                 tap_data->abandon_full_win = true;
1751                 goto out;
1752         } else {
1753                 tap_data->partial_win = tap_value - 1;
1754                 if (tap_value == MAX_TAP_VALUES) {
1755                         /* All tap values exhausted. No full window */
1756                         tap_data->abandon_full_win = true;
1757                         goto out;
1758                 }
1759         }
1760
1761         /* Get the full window start */
1762         tap_value++;
1763         tap_value = sdhci_tegra_scan_tap_values(sdhci, tap_value, true);
1764         if (tap_value > MAX_TAP_VALUES) {
1765                 /* All tap values exhausted. No full window */
1766                 tap_data->abandon_full_win = true;
1767                 goto out;
1768         } else {
1769                 tap_data->full_win_begin = tap_value;
1770                 /*
1771                  * If full win start is 0xFF, then set that as full win end
1772                  * and exit.
1773                  */
1774                 if (tap_value == MAX_TAP_VALUES) {
1775                         tap_data->full_win_end = tap_value;
1776                         goto out;
1777                 }
1778         }
1779
1780         /* Get the full window end */
1781         tap_value++;
1782         tap_value = sdhci_tegra_scan_tap_values(sdhci, tap_value, false);
1783         tap_data->full_win_end = tap_value - 1;
1784         if (tap_value > MAX_TAP_VALUES)
1785                 tap_data->full_win_end = MAX_TAP_VALUES;
1786 out:
1787         /*
1788          * Mark tuning as failed if both partial and full windows are
1789          * abandoned.
1790          */
1791         if (tap_data->abandon_partial_win && tap_data->abandon_full_win)
1792                 err = -EIO;
1793         return err;
1794 }
1795
1796 static int sdhci_tegra_execute_tuning(struct sdhci_host *sdhci, u32 opcode)
1797 {
1798         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
1799         struct sdhci_tegra *tegra_host = pltfm_host->priv;
1800         struct tegra_tuning_data *tuning_data;
1801         struct tap_window_data *tap_data;
1802         int err;
1803         u16 ctrl_2;
1804         u32 ier;
1805         unsigned int freq_band;
1806         unsigned int i;
1807         unsigned int voltage = 0;
1808 #ifdef CONFIG_MMC_FREQ_SCALING
1809         unsigned int dfs_freq = 0;
1810         bool single_freq_tuning = false;
1811 #endif
1812         bool vcore_override_failed = false;
1813         static unsigned int vcore_lvl;
1814
1815         /* Tuning is valid only in SDR104 and SDR50 modes */
1816         ctrl_2 = sdhci_readw(sdhci, SDHCI_HOST_CONTROL2);
1817         if (!(((ctrl_2 & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1818                 (((ctrl_2 & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1819                 (sdhci->flags & SDHCI_SDR50_NEEDS_TUNING))))
1820                         return 0;
1821
1822         /* Tuning should be done only for MMC_BUS_WIDTH_8 and MMC_BUS_WIDTH_4 */
1823         if (sdhci->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1824                 tegra_host->tuning_bsize = MMC_TUNING_BLOCK_SIZE_BUS_WIDTH_8;
1825         else if (sdhci->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1826                 tegra_host->tuning_bsize = MMC_TUNING_BLOCK_SIZE_BUS_WIDTH_4;
1827         else
1828                 return -EINVAL;
1829
1830         sdhci->flags &= ~SDHCI_NEEDS_RETUNING;
1831
1832         /* Set the tuning command to be used */
1833         tegra_host->tuning_opcode = opcode;
1834
1835         /*
1836          * Disable all interrupts signalling.Enable interrupt status
1837          * detection for buffer read ready and data crc. We use
1838          * polling for tuning as it involves less overhead.
1839          */
1840         ier = sdhci_readl(sdhci, SDHCI_INT_ENABLE);
1841         sdhci_writel(sdhci, 0, SDHCI_SIGNAL_ENABLE);
1842         sdhci_writel(sdhci, SDHCI_INT_DATA_AVAIL |
1843                 SDHCI_INT_DATA_CRC, SDHCI_INT_ENABLE);
1844
1845         if (sdhci->max_clk > tuning_params[TUNING_LOW_FREQ].freq_hz)
1846                 freq_band = TUNING_HIGH_FREQ;
1847         else
1848                 freq_band = TUNING_LOW_FREQ;
1849         tuning_data = tegra_host->tuning_data[freq_band];
1850
1851         /*
1852          * If tuning is already done and retune request is not set, then skip
1853          * best tap value calculation and use the old best tap value.
1854          */
1855         if (tegra_host->tuning_status == TUNING_STATUS_DONE) {
1856                 dev_info(mmc_dev(sdhci->mmc),
1857                         "Tuning already done. Setting tuned tap value %d\n",
1858                         tegra_host->tuning_data[freq_band]->best_tap_value);
1859                 goto set_best_tap;
1860         }
1861
1862 #ifdef CONFIG_MMC_FREQ_SCALING
1863         for (dfs_freq = 0; dfs_freq < TUNING_FREQ_COUNT; dfs_freq++) {
1864                 if (sdhci->mmc->caps2 & MMC_CAP2_FREQ_SCALING) {
1865                         spin_unlock(&sdhci->lock);
1866                         tegra_sdhci_set_clk_rate(sdhci,
1867                                 tuning_params[dfs_freq].freq_hz);
1868                         spin_lock(&sdhci->lock);
1869                 } else {
1870                         single_freq_tuning = true;
1871                 }
1872 #endif
1873                 if (sdhci->max_clk > tuning_params[TUNING_LOW_FREQ].freq_hz)
1874                         freq_band = TUNING_HIGH_FREQ;
1875                 else
1876                         freq_band = TUNING_LOW_FREQ;
1877                 /* Remove any previously set override voltages */
1878                 if (tegra_host->set_tuning_override) {
1879                         spin_unlock(&sdhci->lock);
1880                         tegra_dvfs_override_core_voltage(0);
1881                         spin_lock(&sdhci->lock);
1882                         vcore_lvl = 0;
1883                         tegra_host->set_tuning_override = false;
1884                 }
1885
1886                 /*
1887                  * Run tuning and get the passing tap window info for all
1888                  * frequencies and core voltages required to calculate the
1889                  * final tap value. The standard driver calls this platform
1890                  * specific tuning callback after holding a lock. The spinlock
1891                  * needs to be released when calling non-atomic context
1892                  * functions like regulator calls etc.
1893                  */
1894                 spin_unlock(&sdhci->lock);
1895                 if (!tegra_host->tuning_data[freq_band]) {
1896                         tegra_host->tuning_data[freq_band] =
1897                                 devm_kzalloc(mmc_dev(sdhci->mmc),
1898                                 sizeof(struct tegra_tuning_data),
1899                                 GFP_KERNEL);
1900                         if (!tegra_host->tuning_data[freq_band]) {
1901                                 err = -ENOMEM;
1902                                 dev_err(mmc_dev(sdhci->mmc),
1903                                 "Insufficient memory for tap window info\n");
1904                                 spin_lock(&sdhci->lock);
1905                                 goto out;
1906                         }
1907                 }
1908                 spin_lock(&sdhci->lock);
1909                 tuning_data = tegra_host->tuning_data[freq_band];
1910                 for (i = 0; i < tuning_params[freq_band].nr_voltages; i++) {
1911                         spin_unlock(&sdhci->lock);
1912                         if (!tuning_data->tap_data[i]) {
1913                                 tuning_data->tap_data[i] = devm_kzalloc(
1914                                         mmc_dev(sdhci->mmc),
1915                                         sizeof(struct tap_window_data),
1916                                         GFP_KERNEL);
1917                                 if (!tuning_data->tap_data[i]) {
1918                                         err = -ENOMEM;
1919                                         dev_err(mmc_dev(sdhci->mmc),
1920                                         "Insufficient memory for tap window info\n");
1921                                         spin_lock(&sdhci->lock);
1922                                         goto out;
1923                                 }
1924                         }
1925                         tap_data = tuning_data->tap_data[i];
1926                         /*
1927                          * If nominal vcore is not specified, run tuning once
1928                          * and set the tap value. Tuning might fail but this is
1929                          * a better option than not trying tuning at all.
1930                          */
1931                         if (!tegra_host->nominal_vcore_mv) {
1932                                 dev_err(mmc_dev(sdhci->mmc),
1933                                 "Missing nominal vcore. Tuning might fail\n");
1934                                 tuning_data->one_shot_tuning = true;
1935                                 spin_lock(&sdhci->lock);
1936                                 goto skip_vcore_override;
1937                         }
1938
1939                         voltage = tuning_params[freq_band].voltages[i];
1940                         if (voltage > tegra_host->nominal_vcore_mv) {
1941                                 voltage = tegra_host->nominal_vcore_mv;
1942                                 if ((tuning_data->nominal_vcore_tun_done) &&
1943                                 (tuning_params[freq_band].nr_voltages == 1)) {
1944                                         spin_lock(&sdhci->lock);
1945                                         continue;
1946                                 }
1947                         } else if (voltage <
1948                                         tegra_host->min_vcore_override_mv) {
1949                                 voltage = tegra_host->min_vcore_override_mv;
1950                                 if ((tuning_data->override_vcore_tun_done) &&
1951                                 (tuning_params[freq_band].nr_voltages == 1)) {
1952                                         spin_lock(&sdhci->lock);
1953                                         continue;
1954                                 }
1955                         }
1956
1957                         if (voltage != vcore_lvl) {
1958                                 err = tegra_dvfs_override_core_voltage(voltage);
1959                                 if (err) {
1960                                         vcore_override_failed = true;
1961                                         dev_err(mmc_dev(sdhci->mmc),
1962                                         "Setting tuning override_mv %d failed %d\n",
1963                                         voltage, err);
1964                                 } else {
1965                                         vcore_lvl = voltage;
1966                                 }
1967                         }
1968                         spin_lock(&sdhci->lock);
1969
1970 skip_vcore_override:
1971                         /* Get the tuning window info */
1972                         err = sdhci_tegra_get_tap_window_data(sdhci, tap_data);
1973                         if (err) {
1974                                 dev_err(mmc_dev(sdhci->mmc), "No tuning window\n");
1975                                 goto out;
1976                         }
1977
1978                         /*
1979                          * Nominal and min override core voltages are missing.
1980                          * Set tuning as done for one shot tuning.
1981                          */
1982                         if (tuning_data->one_shot_tuning) {
1983                                 tuning_data->nominal_vcore_tun_done = true;
1984                                 tuning_data->override_vcore_tun_done = true;
1985                                 break;
1986                         }
1987
1988                         /* Release the override voltage setting */
1989                         spin_unlock(&sdhci->lock);
1990                         err = tegra_dvfs_override_core_voltage(0);
1991                         if (err)
1992                                 dev_err(mmc_dev(sdhci->mmc),
1993                                 "Clearing tuning override voltage failed %d\n",
1994                                         err);
1995                         else
1996                                 vcore_lvl = 0;
1997                         spin_lock(&sdhci->lock);
1998
1999                         if (!vcore_override_failed) {
2000                                 if (voltage == tegra_host->nominal_vcore_mv)
2001                                         tuning_data->nominal_vcore_tun_done =
2002                                                 true;
2003                                 if (voltage >=
2004                                         tegra_host->min_vcore_override_mv)
2005                                         tuning_data->override_vcore_tun_done =
2006                                                 true;
2007                         }
2008                 }
2009
2010                 /*
2011                  * If tuning is required only at nominal core voltage, set the
2012                  * min override tuning as done to avoid unnecessary
2013                  * vcore override settings.
2014                  */
2015                 if ((tuning_params[freq_band].nr_voltages == 1) &&
2016                         tuning_data->nominal_vcore_tun_done)
2017                         tuning_data->override_vcore_tun_done = true;
2018
2019                 /*
2020                  * If setting min override voltage failed for the first time,
2021                  * set nominal core voltage as override until retuning is done.
2022                  */
2023                 if ((tegra_host->tuning_status != TUNING_STATUS_RETUNE) &&
2024                         tuning_data->nominal_vcore_tun_done &&
2025                         !tuning_data->override_vcore_tun_done)
2026                         tegra_host->set_tuning_override = true;
2027
2028                 /* Calculate best tap for current freq band */
2029                 if (freq_band == TUNING_LOW_FREQ)
2030                         calculate_low_freq_tap_value(sdhci);
2031                 else
2032                         calculate_high_freq_tap_value(sdhci);
2033
2034 set_best_tap:
2035                 /* Dump the tap window data */
2036                 sdhci_tegra_dump_tuning_data(sdhci, freq_band);
2037
2038                 sdhci_tegra_set_tap_delay(sdhci,
2039                         tegra_host->tuning_data[freq_band]->best_tap_value);
2040                 /*
2041                  * Run tuning with the best tap value. If tuning fails, set the
2042                  * status for retuning next time enumeration is done.
2043                  */
2044                 err = sdhci_tegra_run_frequency_tuning(sdhci);
2045                 if (err) {
2046                         dev_err(mmc_dev(sdhci->mmc),
2047                                 "Freq tuning with best tap value failed %d\n",
2048                                         err);
2049                         tuning_data->nominal_vcore_tun_done = false;
2050                         tuning_data->override_vcore_tun_done = false;
2051                         tegra_host->tuning_status = TUNING_STATUS_RETUNE;
2052                 } else {
2053                         if (tuning_data->nominal_vcore_tun_done &&
2054                                 tuning_data->override_vcore_tun_done)
2055                                 tegra_host->tuning_status = TUNING_STATUS_DONE;
2056                         else
2057                                 tegra_host->tuning_status =
2058                                         TUNING_STATUS_RETUNE;
2059                 }
2060                 tegra_host->best_tap_values[freq_band] =
2061                         tegra_host->tuning_data[freq_band]->best_tap_value;
2062 #ifdef CONFIG_MMC_FREQ_SCALING
2063                 if (single_freq_tuning)
2064                         break;
2065         }
2066 #endif
2067 out:
2068         /*
2069          * Lock down the core voltage if tuning at override voltage failed
2070          * for the first time. The override setting will be removed once
2071          * retuning is called.
2072          */
2073         if (tegra_host->set_tuning_override) {
2074                 dev_info(mmc_dev(sdhci->mmc),
2075                         "Nominal core voltage being set until retuning\n");
2076                 spin_unlock(&sdhci->lock);
2077                 err = tegra_dvfs_override_core_voltage(
2078                                 tegra_host->nominal_vcore_mv);
2079                 if (err)
2080                         dev_err(mmc_dev(sdhci->mmc),
2081                                 "Setting tuning override voltage failed %d\n",
2082                                         err);
2083                 else
2084                         vcore_lvl = tegra_host->nominal_vcore_mv;
2085                 spin_lock(&sdhci->lock);
2086
2087                 /* Schedule for the retuning */
2088                 mod_timer(&sdhci->tuning_timer, jiffies +
2089                         10 * HZ);
2090         }
2091
2092         /* Enable interrupts. Enable full range for core voltage */
2093         sdhci_writel(sdhci, ier, SDHCI_INT_ENABLE);
2094         sdhci_writel(sdhci, ier, SDHCI_SIGNAL_ENABLE);
2095         return err;
2096 }
2097
2098 static int tegra_sdhci_suspend(struct sdhci_host *sdhci)
2099 {
2100         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
2101         struct sdhci_tegra *tegra_host = pltfm_host->priv;
2102
2103         tegra_sdhci_set_clock(sdhci, 0);
2104
2105         /* Disable the power rails if any */
2106         if (tegra_host->card_present) {
2107                 if (tegra_host->is_rail_enabled) {
2108                         if (tegra_host->vdd_io_reg)
2109                                 regulator_disable(tegra_host->vdd_io_reg);
2110                         if (tegra_host->vdd_slot_reg)
2111                                 regulator_disable(tegra_host->vdd_slot_reg);
2112                         tegra_host->is_rail_enabled = 0;
2113                 }
2114         }
2115
2116         return 0;
2117 }
2118
2119 static int tegra_sdhci_resume(struct sdhci_host *sdhci)
2120 {
2121         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
2122         struct sdhci_tegra *tegra_host = pltfm_host->priv;
2123         struct platform_device *pdev;
2124         struct tegra_sdhci_platform_data *plat;
2125
2126         pdev = to_platform_device(mmc_dev(sdhci->mmc));
2127         plat = pdev->dev.platform_data;
2128
2129         if (gpio_is_valid(plat->cd_gpio)) {
2130                 tegra_host->card_present =
2131                         (gpio_get_value_cansleep(plat->cd_gpio) == 0);
2132         }
2133
2134         /* Enable the power rails if any */
2135         if (tegra_host->card_present) {
2136                 if (!tegra_host->is_rail_enabled) {
2137                         if (tegra_host->vdd_slot_reg)
2138                                 regulator_enable(tegra_host->vdd_slot_reg);
2139                         if (tegra_host->vdd_io_reg) {
2140                                 regulator_enable(tegra_host->vdd_io_reg);
2141                                 if (plat->mmc_data.ocr_mask &
2142                                                         SDHOST_1V8_OCR_MASK)
2143                                         tegra_sdhci_signal_voltage_switch(sdhci,
2144                                                         MMC_SIGNAL_VOLTAGE_180);
2145                                 else
2146                                         tegra_sdhci_signal_voltage_switch(sdhci,
2147                                                         MMC_SIGNAL_VOLTAGE_330);
2148                         }
2149                         tegra_host->is_rail_enabled = 1;
2150                 }
2151         }
2152
2153         /* Setting the min identification clock of freq 400KHz */
2154         tegra_sdhci_set_clock(sdhci, 400000);
2155
2156         /* Reset the controller and power on if MMC_KEEP_POWER flag is set*/
2157         if (sdhci->mmc->pm_flags & MMC_PM_KEEP_POWER) {
2158                 tegra_sdhci_reset(sdhci, SDHCI_RESET_ALL);
2159                 sdhci_writeb(sdhci, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
2160                 sdhci->pwr = 0;
2161         }
2162
2163         return 0;
2164 }
2165
2166 static int show_polling_period(void *data, u64 *value)
2167 {
2168         struct sdhci_host *host = (struct sdhci_host *)data;
2169
2170         if (host->mmc->dev_stats != NULL)
2171                 *value = host->mmc->dev_stats->polling_interval;
2172
2173         return 0;
2174 }
2175
2176 static int set_polling_period(void *data, u64 value)
2177 {
2178         struct sdhci_host *host = (struct sdhci_host *)data;
2179
2180         if (host->mmc->dev_stats != NULL) {
2181                 /* Limiting the maximum polling period to 1 sec */
2182                 if (value > 1000)
2183                         value = 1000;
2184                 host->mmc->dev_stats->polling_interval = value;
2185         }
2186
2187         return 0;
2188 }
2189 static int show_active_load_high_threshold(void *data, u64 *value)
2190 {
2191         struct sdhci_host *host = (struct sdhci_host *)data;
2192         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2193         struct sdhci_tegra *tegra_host = pltfm_host->priv;
2194         struct tegra_freq_gov_data *gov_data = tegra_host->gov_data;
2195
2196         if (gov_data != NULL)
2197                 *value = gov_data->act_load_high_threshold;
2198
2199         return 0;
2200 }
2201
2202 static int set_active_load_high_threshold(void *data, u64 value)
2203 {
2204         struct sdhci_host *host = (struct sdhci_host *)data;
2205         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2206         struct sdhci_tegra *tegra_host = pltfm_host->priv;
2207         struct tegra_freq_gov_data *gov_data = tegra_host->gov_data;
2208
2209         if (gov_data != NULL) {
2210                 /* Maximum threshold load percentage is 100.*/
2211                 if (value > 100)
2212                         value = 100;
2213                 gov_data->act_load_high_threshold = value;
2214         }
2215
2216         return 0;
2217 }
2218
2219 DEFINE_SIMPLE_ATTRIBUTE(sdhci_polling_period_fops, show_polling_period,
2220                 set_polling_period, "%llu\n");
2221 DEFINE_SIMPLE_ATTRIBUTE(sdhci_active_load_high_threshold_fops,
2222                 show_active_load_high_threshold,
2223                 set_active_load_high_threshold, "%llu\n");
2224
2225 static void sdhci_tegra_error_stats_debugfs(struct sdhci_host *host)
2226 {
2227         struct dentry *root;
2228         struct dentry *dfs_root;
2229
2230         root = debugfs_create_dir(dev_name(mmc_dev(host->mmc)), NULL);
2231         if (IS_ERR_OR_NULL(root))
2232                 goto err_root;
2233         host->debugfs_root = root;
2234
2235         dfs_root = debugfs_create_dir("dfs_stats_dir", root);
2236         if (IS_ERR_OR_NULL(dfs_root))
2237                 goto err_node;
2238
2239         if (!debugfs_create_file("error_stats", S_IRUSR, root, host,
2240                                 &sdhci_host_fops))
2241                 goto err_node;
2242         if (!debugfs_create_file("dfs_stats", S_IRUSR, dfs_root, host,
2243                                 &sdhci_host_dfs_fops))
2244                 goto err_node;
2245         if (!debugfs_create_file("polling_period", 0644, dfs_root, (void *)host,
2246                                 &sdhci_polling_period_fops))
2247                 goto err_node;
2248         if (!debugfs_create_file("active_load_high_threshold", 0644,
2249                                 dfs_root, (void *)host,
2250                                 &sdhci_active_load_high_threshold_fops))
2251                 goto err_node;
2252         return;
2253
2254 err_node:
2255         debugfs_remove_recursive(root);
2256         host->debugfs_root = NULL;
2257 err_root:
2258         pr_err("%s: Failed to initialize debugfs functionality\n", __func__);
2259         return;
2260 }
2261
2262 static void tegra_sdhci_post_resume(struct sdhci_host *sdhci)
2263 {
2264         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
2265         struct sdhci_tegra *tegra_host = pltfm_host->priv;
2266
2267         /* Turn OFF the clocks if the card is not present */
2268         if (!(tegra_host->card_present) && tegra_host->clk_enabled)
2269                 tegra_sdhci_set_clock(sdhci, 0);
2270 }
2271
2272 static const struct sdhci_ops tegra_sdhci_ops = {
2273         .get_ro     = tegra_sdhci_get_ro,
2274         .get_cd     = tegra_sdhci_get_cd,
2275         .read_l     = tegra_sdhci_readl,
2276         .read_w     = tegra_sdhci_readw,
2277         .write_l    = tegra_sdhci_writel,
2278         .write_w    = tegra_sdhci_writew,
2279         .platform_bus_width = tegra_sdhci_buswidth,
2280         .set_clock              = tegra_sdhci_set_clock,
2281         .suspend                = tegra_sdhci_suspend,
2282         .resume                 = tegra_sdhci_resume,
2283         .platform_resume        = tegra_sdhci_post_resume,
2284         .platform_reset_exit    = tegra_sdhci_reset_exit,
2285         .set_uhs_signaling      = tegra_sdhci_set_uhs_signaling,
2286         .switch_signal_voltage  = tegra_sdhci_signal_voltage_switch,
2287         .switch_signal_voltage_exit = tegra_sdhci_do_calibration,
2288         .execute_freq_tuning    = sdhci_tegra_execute_tuning,
2289         .sd_error_stats         = sdhci_tegra_sd_error_stats,
2290 #ifdef CONFIG_MMC_FREQ_SCALING
2291         .dfs_gov_init           = sdhci_tegra_freq_gov_init,
2292         .dfs_gov_get_target_freq        = sdhci_tegra_get_target_freq,
2293 #endif
2294 };
2295
2296 static const struct sdhci_pltfm_data sdhci_tegra20_pdata = {
2297         .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
2298 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2299                   SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
2300                   SDHCI_QUIRK_NON_STD_VOLTAGE_SWITCHING |
2301                   SDHCI_QUIRK_NON_STANDARD_TUNING |
2302 #endif
2303 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
2304                   SDHCI_QUIRK_DISABLE_CARD_CLOCK |
2305                   SDHCI_QUIRK_DO_DUMMY_WRITE |
2306 #endif
2307 #if defined(CONFIG_ARCH_TEGRA_12x_SOC)
2308                   SDHCI_QUIRK_SUPPORT_64BIT_DMA |
2309 #endif
2310                   SDHCI_QUIRK_SINGLE_POWER_WRITE |
2311                   SDHCI_QUIRK_NO_HISPD_BIT |
2312                   SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
2313                   SDHCI_QUIRK_BROKEN_CARD_DETECTION |
2314                   SDHCI_QUIRK_NO_CALC_MAX_DISCARD_TO,
2315         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
2316         .ops  = &tegra_sdhci_ops,
2317 };
2318
2319 static struct sdhci_tegra_soc_data soc_data_tegra20 = {
2320         .pdata = &sdhci_tegra20_pdata,
2321         .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 |
2322 #if defined(CONFIG_ARCH_TEGRA_3x_SOC) || defined(CONFIG_ARCH_TEGRA_14x_SOC)
2323                     NVQUIRK_SET_CALIBRATION_OFFSETS |
2324 #endif
2325 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
2326                    NVQUIRK_ENABLE_PADPIPE_CLKEN |
2327                    NVQUIRK_DISABLE_SPI_MODE_CLKEN |
2328 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
2329                    NVQUIRK_EN_FEEDBACK_CLK |
2330 #endif
2331                    NVQUIRK_SET_TAP_DELAY |
2332                    NVQUIRK_ENABLE_SDR50_TUNING |
2333                    NVQUIRK_ENABLE_SDR50 |
2334                    NVQUIRK_ENABLE_SDR104 |
2335                    NVQUIRK_SHADOW_XFER_MODE_REG |
2336 #endif
2337 #if defined(CONFIG_ARCH_TEGRA_11x_SOC)
2338                     NVQUIRK_SET_DRIVE_STRENGTH |
2339                     NVQUIRK_DISABLE_SDMMC4_CALIB |
2340 #endif
2341 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
2342                     NVQUIRK_DISABLE_AUTO_CALIBRATION |
2343 #elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
2344                     NVQUIRK_ENABLE_SD_3_0 |
2345                     NVQUIRK_BROKEN_SDR50_CONTROLLER_CLOCK |
2346 #else
2347                     NVQUIRK_SET_TRIM_DELAY |
2348                     NVQUIRK_ENABLE_DDR50 |
2349                     NVQUIRK_INFINITE_ERASE_TIMEOUT |
2350                     NVQUIRK_DISABLE_AUTO_CMD23 |
2351 #ifdef CONFIG_TEGRA_FPGA_PLATFORM
2352                     NVQUIRK_DISABLE_AUTO_CALIBRATION |
2353 #endif
2354 #endif
2355 #if defined(CONFIG_ARCH_TEGRA_12x_SOC)
2356                     NVQUIRK_SET_PAD_E_INPUT_OR_E_PWRD |
2357 #endif
2358                     NVQUIRK_ENABLE_BLOCK_GAP_DET,
2359 };
2360
2361 static const struct of_device_id sdhci_tegra_dt_match[] = {
2362 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
2363         { .compatible = "nvidia,tegra148-sdhci", .data = &soc_data_tegra20 },
2364 #endif
2365 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
2366         { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra20 },
2367 #endif
2368 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
2369         { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra20 },
2370 #endif
2371 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2372         { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
2373 #endif
2374         {}
2375 };
2376 MODULE_DEVICE_TABLE(of, sdhci_dt_ids);
2377
2378 static struct tegra_sdhci_platform_data *sdhci_tegra_dt_parse_pdata(
2379                                                 struct platform_device *pdev)
2380 {
2381         int val;
2382         struct tegra_sdhci_platform_data *plat;
2383         struct device_node *np = pdev->dev.of_node;
2384         u32 bus_width;
2385         struct property *prop;
2386         const __be32 *p;
2387         u32 u;
2388         int i = 0;
2389
2390         if (!np)
2391                 return NULL;
2392
2393         plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL);
2394         if (!plat) {
2395                 dev_err(&pdev->dev, "Can't allocate platform data\n");
2396                 return NULL;
2397         }
2398
2399         plat->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
2400         plat->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
2401         plat->power_gpio = of_get_named_gpio(np, "power-gpios", 0);
2402
2403         if (of_property_read_u32(np, "bus-width", &bus_width) == 0 &&
2404             bus_width == 8)
2405                 plat->is_8bit = 1;
2406
2407         if (of_find_property(np, "edp_support", NULL)) {
2408                 plat->edp_support = true;
2409                 of_property_for_each_u32(np, "edp_states", prop, p, u) {
2410                         if (i == SD_EDP_NUM_STATES)
2411                                 break;
2412                         plat->edp_states[i] = u;
2413                         i++;
2414                 }
2415                 p = NULL;
2416                 prop = NULL;
2417         }
2418
2419         of_property_read_u32(np, "tap-delay", &plat->tap_delay);
2420         of_property_read_u32(np, "trim-delay", &plat->trim_delay);
2421         of_property_read_u32(np, "ddr-clk-limit", &plat->ddr_clk_limit);
2422         of_property_read_u32(np, "max-clk-limit", &plat->max_clk_limit);
2423
2424         of_property_read_u32(np, "uhs_mask", &plat->uhs_mask);
2425
2426         if (of_find_property(np, "built-in", NULL))
2427                 plat->mmc_data.built_in = 1;
2428
2429         if (!of_property_read_u32(np, "mmc-ocr-mask", &val)) {
2430                 if (val == 0)
2431                         plat->mmc_data.ocr_mask = MMC_OCR_1V8_MASK;
2432                 else if (val == 1)
2433                         plat->mmc_data.ocr_mask = MMC_OCR_2V8_MASK;
2434                 else if (val == 2)
2435                         plat->mmc_data.ocr_mask = MMC_OCR_3V2_MASK;
2436         }
2437         return plat;
2438 }
2439
2440 static void tegra_sdhci_rail_off(struct sdhci_tegra *tegra_host)
2441 {
2442         if (tegra_host->is_rail_enabled) {
2443                 if (tegra_host->vdd_slot_reg)
2444                         regulator_disable(tegra_host->vdd_slot_reg);
2445                 if (tegra_host->vdd_io_reg)
2446                         regulator_disable(tegra_host->vdd_io_reg);
2447                 tegra_host->is_rail_enabled = false;
2448         }
2449 }
2450
2451 static int tegra_sdhci_reboot_notify(struct notifier_block *nb,
2452                                 unsigned long event, void *data)
2453 {
2454         struct sdhci_tegra *tegra_host =
2455                 container_of(nb, struct sdhci_tegra, reboot_notify);
2456
2457         switch (event) {
2458         case SYS_RESTART:
2459         case SYS_POWER_OFF:
2460                 tegra_sdhci_rail_off(tegra_host);
2461                 return NOTIFY_OK;
2462         }
2463         return NOTIFY_DONE;
2464 }
2465
2466 static int sdhci_tegra_probe(struct platform_device *pdev)
2467 {
2468         const struct of_device_id *match;
2469         const struct sdhci_tegra_soc_data *soc_data;
2470         struct sdhci_host *host;
2471         struct sdhci_pltfm_host *pltfm_host;
2472         struct tegra_sdhci_platform_data *plat;
2473         struct sdhci_tegra *tegra_host;
2474         int rc;
2475
2476         match = of_match_device(sdhci_tegra_dt_match, &pdev->dev);
2477         if (match)
2478                 soc_data = match->data;
2479         else
2480                 soc_data = &soc_data_tegra20;
2481
2482         host = sdhci_pltfm_init(pdev, soc_data->pdata);
2483         if (IS_ERR(host))
2484                 return PTR_ERR(host);
2485
2486         pltfm_host = sdhci_priv(host);
2487
2488         plat = pdev->dev.platform_data;
2489
2490         if (plat == NULL)
2491                 plat = sdhci_tegra_dt_parse_pdata(pdev);
2492
2493         if (plat == NULL) {
2494                 dev_err(mmc_dev(host->mmc), "missing platform data\n");
2495                 rc = -ENXIO;
2496                 goto err_no_plat;
2497         }
2498
2499         tegra_host = devm_kzalloc(&pdev->dev, sizeof(*tegra_host), GFP_KERNEL);
2500         if (!tegra_host) {
2501                 dev_err(mmc_dev(host->mmc), "failed to allocate tegra_host\n");
2502                 rc = -ENOMEM;
2503                 goto err_no_plat;
2504         }
2505
2506         tegra_host->plat = plat;
2507         pdev->dev.platform_data = plat;
2508
2509         tegra_host->sd_stat_head = devm_kzalloc(&pdev->dev,
2510                 sizeof(struct sdhci_tegra_sd_stats), GFP_KERNEL);
2511         if (!tegra_host->sd_stat_head) {
2512                 dev_err(mmc_dev(host->mmc), "failed to allocate sd_stat_head\n");
2513                 rc = -ENOMEM;
2514                 goto err_power_req;
2515         }
2516
2517         tegra_host->soc_data = soc_data;
2518         pltfm_host->priv = tegra_host;
2519
2520         pll_c = clk_get_sys(NULL, "pll_c");
2521         if (IS_ERR(pll_c)) {
2522                 rc = PTR_ERR(pll_c);
2523                 dev_err(mmc_dev(host->mmc),
2524                         "clk error in getting pll_c: %d\n", rc);
2525         }
2526
2527         pll_p = clk_get_sys(NULL, "pll_p");
2528         if (IS_ERR(pll_p)) {
2529                 rc = PTR_ERR(pll_p);
2530                 dev_err(mmc_dev(host->mmc),
2531                         "clk error in getting pll_p: %d\n", rc);
2532         }
2533
2534         pll_c_rate = clk_get_rate(pll_c);
2535         pll_p_rate = clk_get_rate(pll_p);
2536
2537 #ifdef CONFIG_MMC_EMBEDDED_SDIO
2538         if (plat->mmc_data.embedded_sdio)
2539                 mmc_set_embedded_sdio_data(host->mmc,
2540                         &plat->mmc_data.embedded_sdio->cis,
2541                         &plat->mmc_data.embedded_sdio->cccr,
2542                         plat->mmc_data.embedded_sdio->funcs,
2543                         plat->mmc_data.embedded_sdio->num_funcs);
2544 #endif
2545
2546         if (gpio_is_valid(plat->power_gpio)) {
2547                 rc = gpio_request(plat->power_gpio, "sdhci_power");
2548                 if (rc) {
2549                         dev_err(mmc_dev(host->mmc),
2550                                 "failed to allocate power gpio\n");
2551                         goto err_power_req;
2552                 }
2553                 gpio_direction_output(plat->power_gpio, 1);
2554         }
2555
2556         if (gpio_is_valid(plat->cd_gpio)) {
2557                 rc = gpio_request(plat->cd_gpio, "sdhci_cd");
2558                 if (rc) {
2559                         dev_err(mmc_dev(host->mmc),
2560                                 "failed to allocate cd gpio\n");
2561                         goto err_cd_req;
2562                 }
2563                 gpio_direction_input(plat->cd_gpio);
2564
2565                 tegra_host->card_present =
2566                         (gpio_get_value_cansleep(plat->cd_gpio) == 0);
2567
2568         } else if (plat->mmc_data.register_status_notify) {
2569                 plat->mmc_data.register_status_notify(sdhci_status_notify_cb, host);
2570         }
2571
2572         if (plat->mmc_data.status) {
2573                 plat->mmc_data.card_present = plat->mmc_data.status(mmc_dev(host->mmc));
2574         }
2575
2576         if (gpio_is_valid(plat->wp_gpio)) {
2577                 rc = gpio_request(plat->wp_gpio, "sdhci_wp");
2578                 if (rc) {
2579                         dev_err(mmc_dev(host->mmc),
2580                                 "failed to allocate wp gpio\n");
2581                         goto err_wp_req;
2582                 }
2583                 gpio_direction_input(plat->wp_gpio);
2584         }
2585
2586         /*
2587          * If there is no card detect gpio, assume that the
2588          * card is always present.
2589          */
2590         if (!gpio_is_valid(plat->cd_gpio))
2591                 tegra_host->card_present = 1;
2592
2593         if (plat->mmc_data.ocr_mask & SDHOST_1V8_OCR_MASK) {
2594                 tegra_host->vddio_min_uv = SDHOST_LOW_VOLT_MIN;
2595                 tegra_host->vddio_max_uv = SDHOST_LOW_VOLT_MAX;
2596         } else if (plat->mmc_data.ocr_mask & MMC_OCR_2V8_MASK) {
2597                         tegra_host->vddio_min_uv = SDHOST_HIGH_VOLT_2V8;
2598                         tegra_host->vddio_max_uv = SDHOST_HIGH_VOLT_MAX;
2599         } else if (plat->mmc_data.ocr_mask & MMC_OCR_3V2_MASK) {
2600                         tegra_host->vddio_min_uv = SDHOST_HIGH_VOLT_3V2;
2601                         tegra_host->vddio_max_uv = SDHOST_HIGH_VOLT_MAX;
2602         } else {
2603                 /*
2604                  * Set the minV and maxV to default
2605                  * voltage range of 2.7V - 3.6V
2606                  */
2607                 tegra_host->vddio_min_uv = SDHOST_HIGH_VOLT_MIN;
2608                 tegra_host->vddio_max_uv = SDHOST_HIGH_VOLT_MAX;
2609         }
2610
2611         tegra_host->vdd_io_reg = regulator_get(mmc_dev(host->mmc),
2612                                                         "vddio_sdmmc");
2613         if (IS_ERR_OR_NULL(tegra_host->vdd_io_reg)) {
2614                 dev_info(mmc_dev(host->mmc), "%s regulator not found: %ld."
2615                         "Assuming vddio_sdmmc is not required.\n",
2616                         "vddio_sdmmc", PTR_ERR(tegra_host->vdd_io_reg));
2617                 tegra_host->vdd_io_reg = NULL;
2618         } else {
2619                 rc = regulator_set_voltage(tegra_host->vdd_io_reg,
2620                         tegra_host->vddio_min_uv,
2621                         tegra_host->vddio_max_uv);
2622                 if (rc) {
2623                         dev_err(mmc_dev(host->mmc), "%s regulator_set_voltage failed: %d",
2624                                 "vddio_sdmmc", rc);
2625                         regulator_put(tegra_host->vdd_io_reg);
2626                         tegra_host->vdd_io_reg = NULL;
2627                 }
2628         }
2629
2630         tegra_host->vdd_slot_reg = regulator_get(mmc_dev(host->mmc),
2631                                                         "vddio_sd_slot");
2632         if (IS_ERR_OR_NULL(tegra_host->vdd_slot_reg)) {
2633                 dev_info(mmc_dev(host->mmc), "%s regulator not found: %ld."
2634                         " Assuming vddio_sd_slot is not required.\n",
2635                         "vddio_sd_slot", PTR_ERR(tegra_host->vdd_slot_reg));
2636                 tegra_host->vdd_slot_reg = NULL;
2637         }
2638
2639         if (tegra_host->card_present) {
2640                 if (tegra_host->vdd_slot_reg)
2641                         regulator_enable(tegra_host->vdd_slot_reg);
2642                 if (tegra_host->vdd_io_reg)
2643                         regulator_enable(tegra_host->vdd_io_reg);
2644                 tegra_host->is_rail_enabled = 1;
2645         }
2646
2647         tegra_pd_add_device(&pdev->dev);
2648         pm_runtime_enable(&pdev->dev);
2649         pltfm_host->clk = clk_get(mmc_dev(host->mmc), NULL);
2650         if (IS_ERR(pltfm_host->clk)) {
2651                 dev_err(mmc_dev(host->mmc), "clk err\n");
2652                 rc = PTR_ERR(pltfm_host->clk);
2653                 goto err_clk_get;
2654         }
2655
2656         if (clk_get_parent(pltfm_host->clk) == pll_c)
2657                 tegra_host->is_parent_pllc = true;
2658
2659         pm_runtime_get_sync(&pdev->dev);
2660         rc = clk_prepare_enable(pltfm_host->clk);
2661         if (rc != 0)
2662                 goto err_clk_put;
2663
2664         tegra_host->emc_clk = devm_clk_get(mmc_dev(host->mmc), "emc");
2665         if (IS_ERR_OR_NULL(tegra_host->emc_clk)) {
2666                 dev_err(mmc_dev(host->mmc), "Can't get emc clk\n");
2667                 tegra_host->emc_clk = NULL;
2668         } else {
2669                 tegra_host->emc_max_clk =
2670                         clk_round_rate(tegra_host->emc_clk, ULONG_MAX);
2671                 clk_set_rate(tegra_host->emc_clk, SDMMC_EMC_MAX_FREQ);
2672         }
2673
2674         tegra_host->sclk = devm_clk_get(mmc_dev(host->mmc), "sclk");
2675         if (IS_ERR_OR_NULL(tegra_host->sclk)) {
2676                 dev_err(mmc_dev(host->mmc), "Can't get sclk clock\n");
2677                 tegra_host->sclk = NULL;
2678         } else {
2679                 clk_set_rate(tegra_host->sclk, SDMMC_AHB_MAX_FREQ);
2680         }
2681         pltfm_host->priv = tegra_host;
2682         tegra_host->clk_enabled = true;
2683         tegra_host->max_clk_limit = plat->max_clk_limit;
2684         tegra_host->ddr_clk_limit = plat->ddr_clk_limit;
2685         tegra_host->instance = pdev->id;
2686
2687         host->mmc->pm_caps |= plat->pm_caps;
2688         host->mmc->pm_flags |= plat->pm_flags;
2689
2690         host->mmc->caps |= MMC_CAP_ERASE;
2691         /* enable 1/8V DDR capable */
2692         host->mmc->caps |= MMC_CAP_1_8V_DDR;
2693         if (plat->is_8bit)
2694                 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
2695         host->mmc->caps |= MMC_CAP_SDIO_IRQ;
2696         host->mmc->pm_caps |= MMC_PM_KEEP_POWER | MMC_PM_IGNORE_PM_NOTIFY;
2697         if (plat->mmc_data.built_in) {
2698                 host->mmc->caps |= MMC_CAP_NONREMOVABLE;
2699         }
2700         host->mmc->pm_flags |= MMC_PM_IGNORE_PM_NOTIFY;
2701
2702         /* disable access to boot partitions */
2703         host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC;
2704
2705 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
2706         host->mmc->caps2 |= MMC_CAP2_HS200;
2707 #ifdef CONFIG_TEGRA_FPGA_PLATFORM
2708         /* Enable HS200 mode */
2709         host->mmc->caps2 |= MMC_CAP2_HS200;
2710 #else
2711         host->mmc->caps2 |= MMC_CAP2_CACHE_CTRL;
2712         host->mmc->caps |= MMC_CAP_CMD23;
2713         host->mmc->caps2 |= MMC_CAP2_PACKED_CMD;
2714 #endif
2715 #endif
2716
2717 #ifdef CONFIG_MMC_FREQ_SCALING
2718         /*
2719          * Enable dyamic frequency scaling support only if the platform clock
2720          * limit is higher than the lowest supported frequency by tuning.
2721          */
2722         if (plat->en_freq_scaling && (plat->max_clk_limit >
2723                 tuning_params[TUNING_LOW_FREQ].freq_hz))
2724                 host->mmc->caps2 |= MMC_CAP2_FREQ_SCALING;
2725 #endif
2726
2727
2728         if (plat->nominal_vcore_mv)
2729                 tegra_host->nominal_vcore_mv = plat->nominal_vcore_mv;
2730         if (plat->min_vcore_override_mv)
2731                 tegra_host->min_vcore_override_mv = plat->min_vcore_override_mv;
2732
2733         host->edp_support = plat->edp_support ? true : false;
2734         if (host->edp_support)
2735                 for (rc = 0; rc < SD_EDP_NUM_STATES; rc++)
2736                         host->edp_states[rc] = plat->edp_states[rc];
2737
2738         rc = sdhci_add_host(host);
2739         if (rc)
2740                 goto err_add_host;
2741
2742         if (gpio_is_valid(plat->cd_gpio)) {
2743                 rc = request_threaded_irq(gpio_to_irq(plat->cd_gpio), NULL,
2744                         carddetect_irq,
2745                         IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING | IRQF_ONESHOT,
2746                         mmc_hostname(host->mmc), host);
2747                 if (rc) {
2748                         dev_err(mmc_dev(host->mmc), "request irq error\n");
2749                         goto err_cd_irq_req;
2750                 }
2751                 if (!plat->cd_wakeup_incapable) {
2752                         rc = enable_irq_wake(gpio_to_irq(plat->cd_gpio));
2753                         if (rc < 0)
2754                                 dev_err(mmc_dev(host->mmc),
2755                                         "SD card wake-up event registration "
2756                                         "failed with error: %d\n", rc);
2757                 }
2758         }
2759         sdhci_tegra_error_stats_debugfs(host);
2760
2761         /* Enable async suspend/resume to reduce LP0 latency */
2762         device_enable_async_suspend(&pdev->dev);
2763
2764         if (plat->power_off_rail) {
2765                 tegra_host->reboot_notify.notifier_call =
2766                         tegra_sdhci_reboot_notify;
2767                 register_reboot_notifier(&tegra_host->reboot_notify);
2768         }
2769         return 0;
2770
2771 err_cd_irq_req:
2772         if (gpio_is_valid(plat->cd_gpio))
2773                 gpio_free(plat->cd_gpio);
2774 err_add_host:
2775         clk_disable_unprepare(pltfm_host->clk);
2776         pm_runtime_put_sync(&pdev->dev);
2777 err_clk_put:
2778         clk_put(pltfm_host->clk);
2779 err_clk_get:
2780         if (gpio_is_valid(plat->wp_gpio))
2781                 gpio_free(plat->wp_gpio);
2782 err_wp_req:
2783         if (gpio_is_valid(plat->cd_gpio))
2784                 free_irq(gpio_to_irq(plat->cd_gpio), host);
2785 err_cd_req:
2786         if (gpio_is_valid(plat->power_gpio))
2787                 gpio_free(plat->power_gpio);
2788 err_power_req:
2789 err_no_plat:
2790         sdhci_pltfm_free(pdev);
2791         return rc;
2792 }
2793
2794 static int sdhci_tegra_remove(struct platform_device *pdev)
2795 {
2796         struct sdhci_host *host = platform_get_drvdata(pdev);
2797         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2798         struct sdhci_tegra *tegra_host = pltfm_host->priv;
2799         const struct tegra_sdhci_platform_data *plat = tegra_host->plat;
2800         int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
2801
2802         sdhci_remove_host(host, dead);
2803
2804         disable_irq_wake(gpio_to_irq(plat->cd_gpio));
2805
2806         if (tegra_host->vdd_slot_reg) {
2807                 regulator_disable(tegra_host->vdd_slot_reg);
2808                 regulator_put(tegra_host->vdd_slot_reg);
2809         }
2810
2811         if (tegra_host->vdd_io_reg) {
2812                 regulator_disable(tegra_host->vdd_io_reg);
2813                 regulator_put(tegra_host->vdd_io_reg);
2814         }
2815
2816         if (gpio_is_valid(plat->wp_gpio))
2817                 gpio_free(plat->wp_gpio);
2818
2819         if (gpio_is_valid(plat->cd_gpio)) {
2820                 free_irq(gpio_to_irq(plat->cd_gpio), host);
2821                 gpio_free(plat->cd_gpio);
2822         }
2823
2824         if (gpio_is_valid(plat->power_gpio))
2825                 gpio_free(plat->power_gpio);
2826
2827         if (tegra_host->clk_enabled) {
2828                 clk_disable_unprepare(pltfm_host->clk);
2829                 pm_runtime_put_sync(&pdev->dev);
2830         }
2831         clk_put(pltfm_host->clk);
2832
2833         if (tegra_host->emc_clk && tegra_host->is_sdmmc_emc_clk_on)
2834                 clk_disable_unprepare(tegra_host->emc_clk);
2835         if (tegra_host->sclk && tegra_host->is_sdmmc_sclk_on)
2836                 clk_disable_unprepare(tegra_host->sclk);
2837         if (plat->power_off_rail)
2838                 unregister_reboot_notifier(&tegra_host->reboot_notify);
2839
2840         sdhci_pltfm_free(pdev);
2841
2842         return 0;
2843 }
2844
2845 static struct platform_driver sdhci_tegra_driver = {
2846         .driver         = {
2847                 .name   = "sdhci-tegra",
2848                 .owner  = THIS_MODULE,
2849                 .of_match_table = sdhci_tegra_dt_match,
2850                 .pm     = SDHCI_PLTFM_PMOPS,
2851         },
2852         .probe          = sdhci_tegra_probe,
2853         .remove         = sdhci_tegra_remove,
2854 };
2855
2856 module_platform_driver(sdhci_tegra_driver);
2857
2858 MODULE_DESCRIPTION("SDHCI driver for Tegra");
2859 MODULE_AUTHOR("Google, Inc.");
2860 MODULE_LICENSE("GPL v2");