include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[linux-3.10.git] / drivers / media / dvb / ngene / ngene-core.c
1 /*
2  * ngene.c: nGene PCIe bridge driver
3  *
4  * Copyright (C) 2005-2007 Micronas
5  *
6  * Copyright (C) 2008-2009 Ralph Metzler <rjkm@metzlerbros.de>
7  *                         Modifications for new nGene firmware,
8  *                         support for EEPROM-copying,
9  *                         support for new dual DVB-S2 card prototype
10  *
11  *
12  * This program is free software; you can redistribute it and/or
13  * modify it under the terms of the GNU General Public License
14  * version 2 only, as published by the Free Software Foundation.
15  *
16  *
17  * This program is distributed in the hope that it will be useful,
18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
20  * GNU General Public License for more details.
21  *
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software
25  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
26  * 02110-1301, USA
27  * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
28  */
29
30 #include <linux/module.h>
31 #include <linux/init.h>
32 #include <linux/delay.h>
33 #include <linux/poll.h>
34 #include <linux/io.h>
35 #include <asm/div64.h>
36 #include <linux/pci.h>
37 #include <linux/pci_ids.h>
38 #include <linux/smp_lock.h>
39 #include <linux/timer.h>
40 #include <linux/version.h>
41 #include <linux/byteorder/generic.h>
42 #include <linux/firmware.h>
43 #include <linux/vmalloc.h>
44
45 #include "ngene.h"
46
47 #include "stv6110x.h"
48 #include "stv090x.h"
49 #include "lnbh24.h"
50
51 static int one_adapter = 1;
52 module_param(one_adapter, int, 0444);
53 MODULE_PARM_DESC(one_adapter, "Use only one adapter.");
54
55
56 static int debug;
57 module_param(debug, int, 0444);
58 MODULE_PARM_DESC(debug, "Print debugging information.");
59
60 DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
61
62 #define COMMAND_TIMEOUT_WORKAROUND
63
64 #define dprintk if (debug) printk
65
66 #define DEVICE_NAME "ngene"
67
68 #define ngwriteb(dat, adr)         writeb((dat), (char *)(dev->iomem + (adr)))
69 #define ngwritel(dat, adr)         writel((dat), (char *)(dev->iomem + (adr)))
70 #define ngwriteb(dat, adr)         writeb((dat), (char *)(dev->iomem + (adr)))
71 #define ngreadl(adr)               readl(dev->iomem + (adr))
72 #define ngreadb(adr)               readb(dev->iomem + (adr))
73 #define ngcpyto(adr, src, count)   memcpy_toio((char *) \
74                                    (dev->iomem + (adr)), (src), (count))
75 #define ngcpyfrom(dst, adr, count) memcpy_fromio((dst), (char *) \
76                                    (dev->iomem + (adr)), (count))
77
78 /****************************************************************************/
79 /* nGene interrupt handler **************************************************/
80 /****************************************************************************/
81
82 static void event_tasklet(unsigned long data)
83 {
84         struct ngene *dev = (struct ngene *)data;
85
86         while (dev->EventQueueReadIndex != dev->EventQueueWriteIndex) {
87                 struct EVENT_BUFFER Event =
88                         dev->EventQueue[dev->EventQueueReadIndex];
89                 dev->EventQueueReadIndex =
90                         (dev->EventQueueReadIndex + 1) & (EVENT_QUEUE_SIZE - 1);
91
92                 if ((Event.UARTStatus & 0x01) && (dev->TxEventNotify))
93                         dev->TxEventNotify(dev, Event.TimeStamp);
94                 if ((Event.UARTStatus & 0x02) && (dev->RxEventNotify))
95                         dev->RxEventNotify(dev, Event.TimeStamp,
96                                            Event.RXCharacter);
97         }
98 }
99
100 static void demux_tasklet(unsigned long data)
101 {
102         struct ngene_channel *chan = (struct ngene_channel *)data;
103         struct SBufferHeader *Cur = chan->nextBuffer;
104
105         spin_lock_irq(&chan->state_lock);
106
107         while (Cur->ngeneBuffer.SR.Flags & 0x80) {
108                 if (chan->mode & NGENE_IO_TSOUT) {
109                         u32 Flags = chan->DataFormatFlags;
110                         if (Cur->ngeneBuffer.SR.Flags & 0x20)
111                                 Flags |= BEF_OVERFLOW;
112                         if (chan->pBufferExchange) {
113                                 if (!chan->pBufferExchange(chan,
114                                                            Cur->Buffer1,
115                                                            chan->Capture1Length,
116                                                            Cur->ngeneBuffer.SR.
117                                                            Clock, Flags)) {
118                                         /*
119                                            We didn't get data
120                                            Clear in service flag to make sure we
121                                            get called on next interrupt again.
122                                            leave fill/empty (0x80) flag alone
123                                            to avoid hardware running out of
124                                            buffers during startup, we hold only
125                                            in run state ( the source may be late
126                                            delivering data )
127                                         */
128
129                                         if (chan->HWState == HWSTATE_RUN) {
130                                                 Cur->ngeneBuffer.SR.Flags &=
131                                                         ~0x40;
132                                                 break;
133                                                 /* Stop proccessing stream */
134                                         }
135                                 } else {
136                                         /* We got a valid buffer,
137                                            so switch to run state */
138                                         chan->HWState = HWSTATE_RUN;
139                                 }
140                         } else {
141                                 printk(KERN_ERR DEVICE_NAME ": OOPS\n");
142                                 if (chan->HWState == HWSTATE_RUN) {
143                                         Cur->ngeneBuffer.SR.Flags &= ~0x40;
144                                         break;  /* Stop proccessing stream */
145                                 }
146                         }
147                         if (chan->AudioDTOUpdated) {
148                                 printk(KERN_INFO DEVICE_NAME
149                                        ": Update AudioDTO = %d\n",
150                                        chan->AudioDTOValue);
151                                 Cur->ngeneBuffer.SR.DTOUpdate =
152                                         chan->AudioDTOValue;
153                                 chan->AudioDTOUpdated = 0;
154                         }
155                 } else {
156                         if (chan->HWState == HWSTATE_RUN) {
157                                 u32 Flags = 0;
158                                 if (Cur->ngeneBuffer.SR.Flags & 0x01)
159                                         Flags |= BEF_EVEN_FIELD;
160                                 if (Cur->ngeneBuffer.SR.Flags & 0x20)
161                                         Flags |= BEF_OVERFLOW;
162                                 if (chan->pBufferExchange)
163                                         chan->pBufferExchange(chan,
164                                                               Cur->Buffer1,
165                                                               chan->
166                                                               Capture1Length,
167                                                               Cur->ngeneBuffer.
168                                                               SR.Clock, Flags);
169                                 if (chan->pBufferExchange2)
170                                         chan->pBufferExchange2(chan,
171                                                                Cur->Buffer2,
172                                                                chan->
173                                                                Capture2Length,
174                                                                Cur->ngeneBuffer.
175                                                                SR.Clock, Flags);
176                         } else if (chan->HWState != HWSTATE_STOP)
177                                 chan->HWState = HWSTATE_RUN;
178                 }
179                 Cur->ngeneBuffer.SR.Flags = 0x00;
180                 Cur = Cur->Next;
181         }
182         chan->nextBuffer = Cur;
183
184         spin_unlock_irq(&chan->state_lock);
185 }
186
187 static irqreturn_t irq_handler(int irq, void *dev_id)
188 {
189         struct ngene *dev = (struct ngene *)dev_id;
190         u32 icounts = 0;
191         irqreturn_t rc = IRQ_NONE;
192         u32 i = MAX_STREAM;
193         u8 *tmpCmdDoneByte;
194
195         if (dev->BootFirmware) {
196                 icounts = ngreadl(NGENE_INT_COUNTS);
197                 if (icounts != dev->icounts) {
198                         ngwritel(0, FORCE_NMI);
199                         dev->cmd_done = 1;
200                         wake_up(&dev->cmd_wq);
201                         dev->icounts = icounts;
202                         rc = IRQ_HANDLED;
203                 }
204                 return rc;
205         }
206
207         ngwritel(0, FORCE_NMI);
208
209         spin_lock(&dev->cmd_lock);
210         tmpCmdDoneByte = dev->CmdDoneByte;
211         if (tmpCmdDoneByte &&
212             (*tmpCmdDoneByte ||
213             (dev->ngenetohost[0] == 1 && dev->ngenetohost[1] != 0))) {
214                 dev->CmdDoneByte = NULL;
215                 dev->cmd_done = 1;
216                 wake_up(&dev->cmd_wq);
217                 rc = IRQ_HANDLED;
218         }
219         spin_unlock(&dev->cmd_lock);
220
221         if (dev->EventBuffer->EventStatus & 0x80) {
222                 u8 nextWriteIndex =
223                         (dev->EventQueueWriteIndex + 1) &
224                         (EVENT_QUEUE_SIZE - 1);
225                 if (nextWriteIndex != dev->EventQueueReadIndex) {
226                         dev->EventQueue[dev->EventQueueWriteIndex] =
227                                 *(dev->EventBuffer);
228                         dev->EventQueueWriteIndex = nextWriteIndex;
229                 } else {
230                         printk(KERN_ERR DEVICE_NAME ": event overflow\n");
231                         dev->EventQueueOverflowCount += 1;
232                         dev->EventQueueOverflowFlag = 1;
233                 }
234                 dev->EventBuffer->EventStatus &= ~0x80;
235                 tasklet_schedule(&dev->event_tasklet);
236                 rc = IRQ_HANDLED;
237         }
238
239         while (i > 0) {
240                 i--;
241                 spin_lock(&dev->channel[i].state_lock);
242                 /* if (dev->channel[i].State>=KSSTATE_RUN) { */
243                 if (dev->channel[i].nextBuffer) {
244                         if ((dev->channel[i].nextBuffer->
245                              ngeneBuffer.SR.Flags & 0xC0) == 0x80) {
246                                 dev->channel[i].nextBuffer->
247                                         ngeneBuffer.SR.Flags |= 0x40;
248                                 tasklet_schedule(
249                                         &dev->channel[i].demux_tasklet);
250                                 rc = IRQ_HANDLED;
251                         }
252                 }
253                 spin_unlock(&dev->channel[i].state_lock);
254         }
255
256         /* Request might have been processed by a previous call. */
257         return IRQ_HANDLED;
258 }
259
260 /****************************************************************************/
261 /* nGene command interface **************************************************/
262 /****************************************************************************/
263
264 static void dump_command_io(struct ngene *dev)
265 {
266         u8 buf[8], *b;
267
268         ngcpyfrom(buf, HOST_TO_NGENE, 8);
269         printk(KERN_ERR "host_to_ngene (%04x): %02x %02x %02x %02x %02x %02x %02x %02x\n",
270                 HOST_TO_NGENE, buf[0], buf[1], buf[2], buf[3],
271                 buf[4], buf[5], buf[6], buf[7]);
272
273         ngcpyfrom(buf, NGENE_TO_HOST, 8);
274         printk(KERN_ERR "ngene_to_host (%04x): %02x %02x %02x %02x %02x %02x %02x %02x\n",
275                 NGENE_TO_HOST, buf[0], buf[1], buf[2], buf[3],
276                 buf[4], buf[5], buf[6], buf[7]);
277
278         b = dev->hosttongene;
279         printk(KERN_ERR "dev->hosttongene (%p): %02x %02x %02x %02x %02x %02x %02x %02x\n",
280                 b, b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]);
281
282         b = dev->ngenetohost;
283         printk(KERN_ERR "dev->ngenetohost (%p): %02x %02x %02x %02x %02x %02x %02x %02x\n",
284                 b, b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]);
285 }
286
287 static int ngene_command_mutex(struct ngene *dev, struct ngene_command *com)
288 {
289         int ret;
290         u8 *tmpCmdDoneByte;
291
292         dev->cmd_done = 0;
293
294         if (com->cmd.hdr.Opcode == CMD_FWLOAD_PREPARE) {
295                 dev->BootFirmware = 1;
296                 dev->icounts = ngreadl(NGENE_INT_COUNTS);
297                 ngwritel(0, NGENE_COMMAND);
298                 ngwritel(0, NGENE_COMMAND_HI);
299                 ngwritel(0, NGENE_STATUS);
300                 ngwritel(0, NGENE_STATUS_HI);
301                 ngwritel(0, NGENE_EVENT);
302                 ngwritel(0, NGENE_EVENT_HI);
303         } else if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH) {
304                 u64 fwio = dev->PAFWInterfaceBuffer;
305
306                 ngwritel(fwio & 0xffffffff, NGENE_COMMAND);
307                 ngwritel(fwio >> 32, NGENE_COMMAND_HI);
308                 ngwritel((fwio + 256) & 0xffffffff, NGENE_STATUS);
309                 ngwritel((fwio + 256) >> 32, NGENE_STATUS_HI);
310                 ngwritel((fwio + 512) & 0xffffffff, NGENE_EVENT);
311                 ngwritel((fwio + 512) >> 32, NGENE_EVENT_HI);
312         }
313
314         memcpy(dev->FWInterfaceBuffer, com->cmd.raw8, com->in_len + 2);
315
316         if (dev->BootFirmware)
317                 ngcpyto(HOST_TO_NGENE, com->cmd.raw8, com->in_len + 2);
318
319         spin_lock_irq(&dev->cmd_lock);
320         tmpCmdDoneByte = dev->ngenetohost + com->out_len;
321         if (!com->out_len)
322                 tmpCmdDoneByte++;
323         *tmpCmdDoneByte = 0;
324         dev->ngenetohost[0] = 0;
325         dev->ngenetohost[1] = 0;
326         dev->CmdDoneByte = tmpCmdDoneByte;
327         spin_unlock_irq(&dev->cmd_lock);
328
329         /* Notify 8051. */
330         ngwritel(1, FORCE_INT);
331
332         ret = wait_event_timeout(dev->cmd_wq, dev->cmd_done == 1, 2 * HZ);
333         if (!ret) {
334                 /*ngwritel(0, FORCE_NMI);*/
335
336                 printk(KERN_ERR DEVICE_NAME
337                        ": Command timeout cmd=%02x prev=%02x\n",
338                        com->cmd.hdr.Opcode, dev->prev_cmd);
339                 dump_command_io(dev);
340                 return -1;
341         }
342         if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH)
343                 dev->BootFirmware = 0;
344
345         dev->prev_cmd = com->cmd.hdr.Opcode;
346
347         if (!com->out_len)
348                 return 0;
349
350         memcpy(com->cmd.raw8, dev->ngenetohost, com->out_len);
351
352         return 0;
353 }
354
355 static int ngene_command(struct ngene *dev, struct ngene_command *com)
356 {
357         int result;
358
359         down(&dev->cmd_mutex);
360         result = ngene_command_mutex(dev, com);
361         up(&dev->cmd_mutex);
362         return result;
363 }
364
365
366 static int ngene_command_i2c_read(struct ngene *dev, u8 adr,
367                            u8 *out, u8 outlen, u8 *in, u8 inlen, int flag)
368 {
369         struct ngene_command com;
370
371         com.cmd.hdr.Opcode = CMD_I2C_READ;
372         com.cmd.hdr.Length = outlen + 3;
373         com.cmd.I2CRead.Device = adr << 1;
374         memcpy(com.cmd.I2CRead.Data, out, outlen);
375         com.cmd.I2CRead.Data[outlen] = inlen;
376         com.cmd.I2CRead.Data[outlen + 1] = 0;
377         com.in_len = outlen + 3;
378         com.out_len = inlen + 1;
379
380         if (ngene_command(dev, &com) < 0)
381                 return -EIO;
382
383         if ((com.cmd.raw8[0] >> 1) != adr)
384                 return -EIO;
385
386         if (flag)
387                 memcpy(in, com.cmd.raw8, inlen + 1);
388         else
389                 memcpy(in, com.cmd.raw8 + 1, inlen);
390         return 0;
391 }
392
393 static int ngene_command_i2c_write(struct ngene *dev, u8 adr,
394                                    u8 *out, u8 outlen)
395 {
396         struct ngene_command com;
397
398
399         com.cmd.hdr.Opcode = CMD_I2C_WRITE;
400         com.cmd.hdr.Length = outlen + 1;
401         com.cmd.I2CRead.Device = adr << 1;
402         memcpy(com.cmd.I2CRead.Data, out, outlen);
403         com.in_len = outlen + 1;
404         com.out_len = 1;
405
406         if (ngene_command(dev, &com) < 0)
407                 return -EIO;
408
409         if (com.cmd.raw8[0] == 1)
410                 return -EIO;
411
412         return 0;
413 }
414
415 static int ngene_command_load_firmware(struct ngene *dev,
416                                        u8 *ngene_fw, u32 size)
417 {
418 #define FIRSTCHUNK (1024)
419         u32 cleft;
420         struct ngene_command com;
421
422         com.cmd.hdr.Opcode = CMD_FWLOAD_PREPARE;
423         com.cmd.hdr.Length = 0;
424         com.in_len = 0;
425         com.out_len = 0;
426
427         ngene_command(dev, &com);
428
429         cleft = (size + 3) & ~3;
430         if (cleft > FIRSTCHUNK) {
431                 ngcpyto(PROGRAM_SRAM + FIRSTCHUNK, ngene_fw + FIRSTCHUNK,
432                         cleft - FIRSTCHUNK);
433                 cleft = FIRSTCHUNK;
434         }
435         ngcpyto(DATA_FIFO_AREA, ngene_fw, cleft);
436
437         memset(&com, 0, sizeof(struct ngene_command));
438         com.cmd.hdr.Opcode = CMD_FWLOAD_FINISH;
439         com.cmd.hdr.Length = 4;
440         com.cmd.FWLoadFinish.Address = DATA_FIFO_AREA;
441         com.cmd.FWLoadFinish.Length = (unsigned short)cleft;
442         com.in_len = 4;
443         com.out_len = 0;
444
445         return ngene_command(dev, &com);
446 }
447
448
449 static int ngene_command_config_buf(struct ngene *dev, u8 config)
450 {
451         struct ngene_command com;
452
453         com.cmd.hdr.Opcode = CMD_CONFIGURE_BUFFER;
454         com.cmd.hdr.Length = 1;
455         com.cmd.ConfigureBuffers.config = config;
456         com.in_len = 1;
457         com.out_len = 0;
458
459         if (ngene_command(dev, &com) < 0)
460                 return -EIO;
461         return 0;
462 }
463
464 static int ngene_command_config_free_buf(struct ngene *dev, u8 *config)
465 {
466         struct ngene_command com;
467
468         com.cmd.hdr.Opcode = CMD_CONFIGURE_FREE_BUFFER;
469         com.cmd.hdr.Length = 6;
470         memcpy(&com.cmd.ConfigureBuffers.config, config, 6);
471         com.in_len = 6;
472         com.out_len = 0;
473
474         if (ngene_command(dev, &com) < 0)
475                 return -EIO;
476
477         return 0;
478 }
479
480 static int ngene_command_gpio_set(struct ngene *dev, u8 select, u8 level)
481 {
482         struct ngene_command com;
483
484         com.cmd.hdr.Opcode = CMD_SET_GPIO_PIN;
485         com.cmd.hdr.Length = 1;
486         com.cmd.SetGpioPin.select = select | (level << 7);
487         com.in_len = 1;
488         com.out_len = 0;
489
490         return ngene_command(dev, &com);
491 }
492
493
494 /*
495  02000640 is sample on rising edge.
496  02000740 is sample on falling edge.
497  02000040 is ignore "valid" signal
498
499  0: FD_CTL1 Bit 7,6 must be 0,1
500     7   disable(fw controlled)
501     6   0-AUX,1-TS
502     5   0-par,1-ser
503     4   0-lsb/1-msb
504     3,2 reserved
505     1,0 0-no sync, 1-use ext. start, 2-use 0x47, 3-both
506  1: FD_CTL2 has 3-valid must be hi, 2-use valid, 1-edge
507  2: FD_STA is read-only. 0-sync
508  3: FD_INSYNC is number of 47s to trigger "in sync".
509  4: FD_OUTSYNC is number of 47s to trigger "out of sync".
510  5: FD_MAXBYTE1 is low-order of bytes per packet.
511  6: FD_MAXBYTE2 is high-order of bytes per packet.
512  7: Top byte is unused.
513 */
514
515 /****************************************************************************/
516
517 static u8 TSFeatureDecoderSetup[8 * 4] = {
518         0x42, 0x00, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00,
519         0x40, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXH */
520         0x71, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXHser */
521         0x72, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* S2ser */
522 };
523
524 /* Set NGENE I2S Config to 16 bit packed */
525 static u8 I2SConfiguration[] = {
526         0x00, 0x10, 0x00, 0x00,
527         0x80, 0x10, 0x00, 0x00,
528 };
529
530 static u8 SPDIFConfiguration[10] = {
531         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
532 };
533
534 /* Set NGENE I2S Config to transport stream compatible mode */
535
536 static u8 TS_I2SConfiguration[4] = { 0x3E, 0x1A, 0x00, 0x00 }; /*3e 18 00 00 ?*/
537
538 static u8 TS_I2SOutConfiguration[4] = { 0x80, 0x20, 0x00, 0x00 };
539
540 static u8 ITUDecoderSetup[4][16] = {
541         {0x1c, 0x13, 0x01, 0x68, 0x3d, 0x90, 0x14, 0x20,  /* SDTV */
542          0x00, 0x00, 0x01, 0xb0, 0x9c, 0x00, 0x00, 0x00},
543         {0x9c, 0x03, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00,
544          0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
545         {0x9f, 0x00, 0x23, 0xC0, 0x60, 0x0F, 0x13, 0x00,  /* HDTV 1080i50 */
546          0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
547         {0x9c, 0x01, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00,  /* HDTV 1080i60 */
548          0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
549 };
550
551 /*
552  * 50 48 60 gleich
553  * 27p50 9f 00 22 80 42 69 18 ...
554  * 27p60 93 00 22 80 82 69 1c ...
555  */
556
557 /* Maxbyte to 1144 (for raw data) */
558 static u8 ITUFeatureDecoderSetup[8] = {
559         0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x04, 0x00
560 };
561
562 static void FillTSBuffer(void *Buffer, int Length, u32 Flags)
563 {
564         u32 *ptr = Buffer;
565
566         memset(Buffer, 0xff, Length);
567         while (Length > 0) {
568                 if (Flags & DF_SWAP32)
569                         *ptr = 0x471FFF10;
570                 else
571                         *ptr = 0x10FF1F47;
572                 ptr += (188 / 4);
573                 Length -= 188;
574         }
575 }
576
577
578 static void flush_buffers(struct ngene_channel *chan)
579 {
580         u8 val;
581
582         do {
583                 msleep(1);
584                 spin_lock_irq(&chan->state_lock);
585                 val = chan->nextBuffer->ngeneBuffer.SR.Flags & 0x80;
586                 spin_unlock_irq(&chan->state_lock);
587         } while (val);
588 }
589
590 static void clear_buffers(struct ngene_channel *chan)
591 {
592         struct SBufferHeader *Cur = chan->nextBuffer;
593
594         do {
595                 memset(&Cur->ngeneBuffer.SR, 0, sizeof(Cur->ngeneBuffer.SR));
596                 if (chan->mode & NGENE_IO_TSOUT)
597                         FillTSBuffer(Cur->Buffer1,
598                                      chan->Capture1Length,
599                                      chan->DataFormatFlags);
600                 Cur = Cur->Next;
601         } while (Cur != chan->nextBuffer);
602
603         if (chan->mode & NGENE_IO_TSOUT) {
604                 chan->nextBuffer->ngeneBuffer.SR.DTOUpdate =
605                         chan->AudioDTOValue;
606                 chan->AudioDTOUpdated = 0;
607
608                 Cur = chan->TSIdleBuffer.Head;
609
610                 do {
611                         memset(&Cur->ngeneBuffer.SR, 0,
612                                sizeof(Cur->ngeneBuffer.SR));
613                         FillTSBuffer(Cur->Buffer1,
614                                      chan->Capture1Length,
615                                      chan->DataFormatFlags);
616                         Cur = Cur->Next;
617                 } while (Cur != chan->TSIdleBuffer.Head);
618         }
619 }
620
621 static int ngene_command_stream_control(struct ngene *dev, u8 stream,
622                                         u8 control, u8 mode, u8 flags)
623 {
624         struct ngene_channel *chan = &dev->channel[stream];
625         struct ngene_command com;
626         u16 BsUVI = ((stream & 1) ? 0x9400 : 0x9300);
627         u16 BsSDI = ((stream & 1) ? 0x9600 : 0x9500);
628         u16 BsSPI = ((stream & 1) ? 0x9800 : 0x9700);
629         u16 BsSDO = 0x9B00;
630
631         /* down(&dev->stream_mutex); */
632         while (down_trylock(&dev->stream_mutex)) {
633                 printk(KERN_INFO DEVICE_NAME ": SC locked\n");
634                 msleep(1);
635         }
636         memset(&com, 0, sizeof(com));
637         com.cmd.hdr.Opcode = CMD_CONTROL;
638         com.cmd.hdr.Length = sizeof(struct FW_STREAM_CONTROL) - 2;
639         com.cmd.StreamControl.Stream = stream | (control ? 8 : 0);
640         if (chan->mode & NGENE_IO_TSOUT)
641                 com.cmd.StreamControl.Stream |= 0x07;
642         com.cmd.StreamControl.Control = control |
643                 (flags & SFLAG_ORDER_LUMA_CHROMA);
644         com.cmd.StreamControl.Mode = mode;
645         com.in_len = sizeof(struct FW_STREAM_CONTROL);
646         com.out_len = 0;
647
648         dprintk(KERN_INFO DEVICE_NAME
649                 ": Stream=%02x, Control=%02x, Mode=%02x\n",
650                 com.cmd.StreamControl.Stream, com.cmd.StreamControl.Control,
651                 com.cmd.StreamControl.Mode);
652
653         chan->Mode = mode;
654
655         if (!(control & 0x80)) {
656                 spin_lock_irq(&chan->state_lock);
657                 if (chan->State == KSSTATE_RUN) {
658                         chan->State = KSSTATE_ACQUIRE;
659                         chan->HWState = HWSTATE_STOP;
660                         spin_unlock_irq(&chan->state_lock);
661                         if (ngene_command(dev, &com) < 0) {
662                                 up(&dev->stream_mutex);
663                                 return -1;
664                         }
665                         /* clear_buffers(chan); */
666                         flush_buffers(chan);
667                         up(&dev->stream_mutex);
668                         return 0;
669                 }
670                 spin_unlock_irq(&chan->state_lock);
671                 up(&dev->stream_mutex);
672                 return 0;
673         }
674
675         if (mode & SMODE_AUDIO_CAPTURE) {
676                 com.cmd.StreamControl.CaptureBlockCount =
677                         chan->Capture1Length / AUDIO_BLOCK_SIZE;
678                 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead;
679         } else if (mode & SMODE_TRANSPORT_STREAM) {
680                 com.cmd.StreamControl.CaptureBlockCount =
681                         chan->Capture1Length / TS_BLOCK_SIZE;
682                 com.cmd.StreamControl.MaxLinesPerField =
683                         chan->Capture1Length / TS_BLOCK_SIZE;
684                 com.cmd.StreamControl.Buffer_Address =
685                         chan->TSRingBuffer.PAHead;
686                 if (chan->mode & NGENE_IO_TSOUT) {
687                         com.cmd.StreamControl.BytesPerVBILine =
688                                 chan->Capture1Length / TS_BLOCK_SIZE;
689                         com.cmd.StreamControl.Stream |= 0x07;
690                 }
691         } else {
692                 com.cmd.StreamControl.BytesPerVideoLine = chan->nBytesPerLine;
693                 com.cmd.StreamControl.MaxLinesPerField = chan->nLines;
694                 com.cmd.StreamControl.MinLinesPerField = 100;
695                 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead;
696
697                 if (mode & SMODE_VBI_CAPTURE) {
698                         com.cmd.StreamControl.MaxVBILinesPerField =
699                                 chan->nVBILines;
700                         com.cmd.StreamControl.MinVBILinesPerField = 0;
701                         com.cmd.StreamControl.BytesPerVBILine =
702                                 chan->nBytesPerVBILine;
703                 }
704                 if (flags & SFLAG_COLORBAR)
705                         com.cmd.StreamControl.Stream |= 0x04;
706         }
707
708         spin_lock_irq(&chan->state_lock);
709         if (mode & SMODE_AUDIO_CAPTURE) {
710                 chan->nextBuffer = chan->RingBuffer.Head;
711                 if (mode & SMODE_AUDIO_SPDIF) {
712                         com.cmd.StreamControl.SetupDataLen =
713                                 sizeof(SPDIFConfiguration);
714                         com.cmd.StreamControl.SetupDataAddr = BsSPI;
715                         memcpy(com.cmd.StreamControl.SetupData,
716                                SPDIFConfiguration, sizeof(SPDIFConfiguration));
717                 } else {
718                         com.cmd.StreamControl.SetupDataLen = 4;
719                         com.cmd.StreamControl.SetupDataAddr = BsSDI;
720                         memcpy(com.cmd.StreamControl.SetupData,
721                                I2SConfiguration +
722                                4 * dev->card_info->i2s[stream], 4);
723                 }
724         } else if (mode & SMODE_TRANSPORT_STREAM) {
725                 chan->nextBuffer = chan->TSRingBuffer.Head;
726                 if (stream >= STREAM_AUDIOIN1) {
727                         if (chan->mode & NGENE_IO_TSOUT) {
728                                 com.cmd.StreamControl.SetupDataLen =
729                                         sizeof(TS_I2SOutConfiguration);
730                                 com.cmd.StreamControl.SetupDataAddr = BsSDO;
731                                 memcpy(com.cmd.StreamControl.SetupData,
732                                        TS_I2SOutConfiguration,
733                                        sizeof(TS_I2SOutConfiguration));
734                         } else {
735                                 com.cmd.StreamControl.SetupDataLen =
736                                         sizeof(TS_I2SConfiguration);
737                                 com.cmd.StreamControl.SetupDataAddr = BsSDI;
738                                 memcpy(com.cmd.StreamControl.SetupData,
739                                        TS_I2SConfiguration,
740                                        sizeof(TS_I2SConfiguration));
741                         }
742                 } else {
743                         com.cmd.StreamControl.SetupDataLen = 8;
744                         com.cmd.StreamControl.SetupDataAddr = BsUVI + 0x10;
745                         memcpy(com.cmd.StreamControl.SetupData,
746                                TSFeatureDecoderSetup +
747                                8 * dev->card_info->tsf[stream], 8);
748                 }
749         } else {
750                 chan->nextBuffer = chan->RingBuffer.Head;
751                 com.cmd.StreamControl.SetupDataLen =
752                         16 + sizeof(ITUFeatureDecoderSetup);
753                 com.cmd.StreamControl.SetupDataAddr = BsUVI;
754                 memcpy(com.cmd.StreamControl.SetupData,
755                        ITUDecoderSetup[chan->itumode], 16);
756                 memcpy(com.cmd.StreamControl.SetupData + 16,
757                        ITUFeatureDecoderSetup, sizeof(ITUFeatureDecoderSetup));
758         }
759         clear_buffers(chan);
760         chan->State = KSSTATE_RUN;
761         if (mode & SMODE_TRANSPORT_STREAM)
762                 chan->HWState = HWSTATE_RUN;
763         else
764                 chan->HWState = HWSTATE_STARTUP;
765         spin_unlock_irq(&chan->state_lock);
766
767         if (ngene_command(dev, &com) < 0) {
768                 up(&dev->stream_mutex);
769                 return -1;
770         }
771         up(&dev->stream_mutex);
772         return 0;
773 }
774
775
776 /****************************************************************************/
777 /* I2C **********************************************************************/
778 /****************************************************************************/
779
780 static void ngene_i2c_set_bus(struct ngene *dev, int bus)
781 {
782         if (!(dev->card_info->i2c_access & 2))
783                 return;
784         if (dev->i2c_current_bus == bus)
785                 return;
786
787         switch (bus) {
788         case 0:
789                 ngene_command_gpio_set(dev, 3, 0);
790                 ngene_command_gpio_set(dev, 2, 1);
791                 break;
792
793         case 1:
794                 ngene_command_gpio_set(dev, 2, 0);
795                 ngene_command_gpio_set(dev, 3, 1);
796                 break;
797         }
798         dev->i2c_current_bus = bus;
799 }
800
801 static int ngene_i2c_master_xfer(struct i2c_adapter *adapter,
802                                  struct i2c_msg msg[], int num)
803 {
804         struct ngene_channel *chan =
805                 (struct ngene_channel *)i2c_get_adapdata(adapter);
806         struct ngene *dev = chan->dev;
807
808         down(&dev->i2c_switch_mutex);
809         ngene_i2c_set_bus(dev, chan->number);
810
811         if (num == 2 && msg[1].flags & I2C_M_RD && !(msg[0].flags & I2C_M_RD))
812                 if (!ngene_command_i2c_read(dev, msg[0].addr,
813                                             msg[0].buf, msg[0].len,
814                                             msg[1].buf, msg[1].len, 0))
815                         goto done;
816
817         if (num == 1 && !(msg[0].flags & I2C_M_RD))
818                 if (!ngene_command_i2c_write(dev, msg[0].addr,
819                                              msg[0].buf, msg[0].len))
820                         goto done;
821         if (num == 1 && (msg[0].flags & I2C_M_RD))
822                 if (!ngene_command_i2c_read(dev, msg[0].addr, 0, 0,
823                                             msg[0].buf, msg[0].len, 0))
824                         goto done;
825
826         up(&dev->i2c_switch_mutex);
827         return -EIO;
828
829 done:
830         up(&dev->i2c_switch_mutex);
831         return num;
832 }
833
834
835 static u32 ngene_i2c_functionality(struct i2c_adapter *adap)
836 {
837         return I2C_FUNC_SMBUS_EMUL;
838 }
839
840 static struct i2c_algorithm ngene_i2c_algo = {
841         .master_xfer = ngene_i2c_master_xfer,
842         .functionality = ngene_i2c_functionality,
843 };
844
845 static int ngene_i2c_init(struct ngene *dev, int dev_nr)
846 {
847         struct i2c_adapter *adap = &(dev->channel[dev_nr].i2c_adapter);
848
849         i2c_set_adapdata(adap, &(dev->channel[dev_nr]));
850         adap->class = I2C_CLASS_TV_DIGITAL | I2C_CLASS_TV_ANALOG;
851
852         strcpy(adap->name, "nGene");
853
854         adap->algo = &ngene_i2c_algo;
855         adap->algo_data = (void *)&(dev->channel[dev_nr]);
856         adap->dev.parent = &dev->pci_dev->dev;
857
858         return i2c_add_adapter(adap);
859 }
860
861
862 /****************************************************************************/
863 /* DVB functions and API interface ******************************************/
864 /****************************************************************************/
865
866 static void swap_buffer(u32 *p, u32 len)
867 {
868         while (len) {
869                 *p = swab32(*p);
870                 p++;
871                 len -= 4;
872         }
873 }
874
875
876 static void *tsin_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags)
877 {
878         struct ngene_channel *chan = priv;
879
880
881 #ifdef COMMAND_TIMEOUT_WORKAROUND
882         if (chan->users > 0)
883 #endif
884                 dvb_dmx_swfilter(&chan->demux, buf, len);
885         return 0;
886 }
887
888 u8 fill_ts[188] = { 0x47, 0x1f, 0xff, 0x10 };
889
890 static void *tsout_exchange(void *priv, void *buf, u32 len,
891                             u32 clock, u32 flags)
892 {
893         struct ngene_channel *chan = priv;
894         struct ngene *dev = chan->dev;
895         u32 alen;
896
897         alen = dvb_ringbuffer_avail(&dev->tsout_rbuf);
898         alen -= alen % 188;
899
900         if (alen < len)
901                 FillTSBuffer(buf + alen, len - alen, flags);
902         else
903                 alen = len;
904         dvb_ringbuffer_read(&dev->tsout_rbuf, buf, alen);
905         if (flags & DF_SWAP32)
906                 swap_buffer((u32 *)buf, alen);
907         wake_up_interruptible(&dev->tsout_rbuf.queue);
908         return buf;
909 }
910
911
912 static void set_transfer(struct ngene_channel *chan, int state)
913 {
914         u8 control = 0, mode = 0, flags = 0;
915         struct ngene *dev = chan->dev;
916         int ret;
917
918         /*
919         printk(KERN_INFO DEVICE_NAME ": st %d\n", state);
920         msleep(100);
921         */
922
923         if (state) {
924                 if (chan->running) {
925                         printk(KERN_INFO DEVICE_NAME ": already running\n");
926                         return;
927                 }
928         } else {
929                 if (!chan->running) {
930                         printk(KERN_INFO DEVICE_NAME ": already stopped\n");
931                         return;
932                 }
933         }
934
935         if (dev->card_info->switch_ctrl)
936                 dev->card_info->switch_ctrl(chan, 1, state ^ 1);
937
938         if (state) {
939                 spin_lock_irq(&chan->state_lock);
940
941                 /* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n",
942                           ngreadl(0x9310)); */
943                 dvb_ringbuffer_flush(&dev->tsout_rbuf);
944                 control = 0x80;
945                 if (chan->mode & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
946                         chan->Capture1Length = 512 * 188;
947                         mode = SMODE_TRANSPORT_STREAM;
948                 }
949                 if (chan->mode & NGENE_IO_TSOUT) {
950                         chan->pBufferExchange = tsout_exchange;
951                         /* 0x66666666 = 50MHz *2^33 /250MHz */
952                         chan->AudioDTOValue = 0x66666666;
953                         /* set_dto(chan, 38810700+1000); */
954                         /* set_dto(chan, 19392658); */
955                 }
956                 if (chan->mode & NGENE_IO_TSIN)
957                         chan->pBufferExchange = tsin_exchange;
958                 /* ngwritel(0, 0x9310); */
959                 spin_unlock_irq(&chan->state_lock);
960         } else
961                 ;/* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n",
962                            ngreadl(0x9310)); */
963
964         ret = ngene_command_stream_control(dev, chan->number,
965                                            control, mode, flags);
966         if (!ret)
967                 chan->running = state;
968         else
969                 printk(KERN_ERR DEVICE_NAME ": set_transfer %d failed\n",
970                        state);
971         if (!state) {
972                 spin_lock_irq(&chan->state_lock);
973                 chan->pBufferExchange = 0;
974                 dvb_ringbuffer_flush(&dev->tsout_rbuf);
975                 spin_unlock_irq(&chan->state_lock);
976         }
977 }
978
979 static int ngene_start_feed(struct dvb_demux_feed *dvbdmxfeed)
980 {
981         struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
982         struct ngene_channel *chan = dvbdmx->priv;
983
984         if (chan->users == 0) {
985 #ifdef COMMAND_TIMEOUT_WORKAROUND
986                 if (!chan->running)
987 #endif
988                         set_transfer(chan, 1);
989                 /* msleep(10); */
990         }
991
992         return ++chan->users;
993 }
994
995 static int ngene_stop_feed(struct dvb_demux_feed *dvbdmxfeed)
996 {
997         struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
998         struct ngene_channel *chan = dvbdmx->priv;
999
1000         if (--chan->users)
1001                 return chan->users;
1002
1003 #ifndef COMMAND_TIMEOUT_WORKAROUND
1004         set_transfer(chan, 0);
1005 #endif
1006
1007         return 0;
1008 }
1009
1010
1011
1012 static int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id,
1013                                    int (*start_feed)(struct dvb_demux_feed *),
1014                                    int (*stop_feed)(struct dvb_demux_feed *),
1015                                    void *priv)
1016 {
1017         dvbdemux->priv = priv;
1018
1019         dvbdemux->filternum = 256;
1020         dvbdemux->feednum = 256;
1021         dvbdemux->start_feed = start_feed;
1022         dvbdemux->stop_feed = stop_feed;
1023         dvbdemux->write_to_decoder = 0;
1024         dvbdemux->dmx.capabilities = (DMX_TS_FILTERING |
1025                                       DMX_SECTION_FILTERING |
1026                                       DMX_MEMORY_BASED_FILTERING);
1027         return dvb_dmx_init(dvbdemux);
1028 }
1029
1030 static int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev,
1031                                       struct dvb_demux *dvbdemux,
1032                                       struct dmx_frontend *hw_frontend,
1033                                       struct dmx_frontend *mem_frontend,
1034                                       struct dvb_adapter *dvb_adapter)
1035 {
1036         int ret;
1037
1038         dmxdev->filternum = 256;
1039         dmxdev->demux = &dvbdemux->dmx;
1040         dmxdev->capabilities = 0;
1041         ret = dvb_dmxdev_init(dmxdev, dvb_adapter);
1042         if (ret < 0)
1043                 return ret;
1044
1045         hw_frontend->source = DMX_FRONTEND_0;
1046         dvbdemux->dmx.add_frontend(&dvbdemux->dmx, hw_frontend);
1047         mem_frontend->source = DMX_MEMORY_FE;
1048         dvbdemux->dmx.add_frontend(&dvbdemux->dmx, mem_frontend);
1049         return dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, hw_frontend);
1050 }
1051
1052
1053 /****************************************************************************/
1054 /* nGene hardware init and release functions ********************************/
1055 /****************************************************************************/
1056
1057 static void free_ringbuffer(struct ngene *dev, struct SRingBufferDescriptor *rb)
1058 {
1059         struct SBufferHeader *Cur = rb->Head;
1060         u32 j;
1061
1062         if (!Cur)
1063                 return;
1064
1065         for (j = 0; j < rb->NumBuffers; j++, Cur = Cur->Next) {
1066                 if (Cur->Buffer1)
1067                         pci_free_consistent(dev->pci_dev,
1068                                             rb->Buffer1Length,
1069                                             Cur->Buffer1,
1070                                             Cur->scList1->Address);
1071
1072                 if (Cur->Buffer2)
1073                         pci_free_consistent(dev->pci_dev,
1074                                             rb->Buffer2Length,
1075                                             Cur->Buffer2,
1076                                             Cur->scList2->Address);
1077         }
1078
1079         if (rb->SCListMem)
1080                 pci_free_consistent(dev->pci_dev, rb->SCListMemSize,
1081                                     rb->SCListMem, rb->PASCListMem);
1082
1083         pci_free_consistent(dev->pci_dev, rb->MemSize, rb->Head, rb->PAHead);
1084 }
1085
1086 static void free_idlebuffer(struct ngene *dev,
1087                      struct SRingBufferDescriptor *rb,
1088                      struct SRingBufferDescriptor *tb)
1089 {
1090         int j;
1091         struct SBufferHeader *Cur = tb->Head;
1092
1093         if (!rb->Head)
1094                 return;
1095         free_ringbuffer(dev, rb);
1096         for (j = 0; j < tb->NumBuffers; j++, Cur = Cur->Next) {
1097                 Cur->Buffer2 = 0;
1098                 Cur->scList2 = 0;
1099                 Cur->ngeneBuffer.Address_of_first_entry_2 = 0;
1100                 Cur->ngeneBuffer.Number_of_entries_2 = 0;
1101         }
1102 }
1103
1104 static void free_common_buffers(struct ngene *dev)
1105 {
1106         u32 i;
1107         struct ngene_channel *chan;
1108
1109         for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) {
1110                 chan = &dev->channel[i];
1111                 free_idlebuffer(dev, &chan->TSIdleBuffer, &chan->TSRingBuffer);
1112                 free_ringbuffer(dev, &chan->RingBuffer);
1113                 free_ringbuffer(dev, &chan->TSRingBuffer);
1114         }
1115
1116         if (dev->OverflowBuffer)
1117                 pci_free_consistent(dev->pci_dev,
1118                                     OVERFLOW_BUFFER_SIZE,
1119                                     dev->OverflowBuffer, dev->PAOverflowBuffer);
1120
1121         if (dev->FWInterfaceBuffer)
1122                 pci_free_consistent(dev->pci_dev,
1123                                     4096,
1124                                     dev->FWInterfaceBuffer,
1125                                     dev->PAFWInterfaceBuffer);
1126 }
1127
1128 /****************************************************************************/
1129 /* Ring buffer handling *****************************************************/
1130 /****************************************************************************/
1131
1132 static int create_ring_buffer(struct pci_dev *pci_dev,
1133                        struct SRingBufferDescriptor *descr, u32 NumBuffers)
1134 {
1135         dma_addr_t tmp;
1136         struct SBufferHeader *Head;
1137         u32 i;
1138         u32 MemSize = SIZEOF_SBufferHeader * NumBuffers;
1139         u64 PARingBufferHead;
1140         u64 PARingBufferCur;
1141         u64 PARingBufferNext;
1142         struct SBufferHeader *Cur, *Next;
1143
1144         descr->Head = 0;
1145         descr->MemSize = 0;
1146         descr->PAHead = 0;
1147         descr->NumBuffers = 0;
1148
1149         if (MemSize < 4096)
1150                 MemSize = 4096;
1151
1152         Head = pci_alloc_consistent(pci_dev, MemSize, &tmp);
1153         PARingBufferHead = tmp;
1154
1155         if (!Head)
1156                 return -ENOMEM;
1157
1158         memset(Head, 0, MemSize);
1159
1160         PARingBufferCur = PARingBufferHead;
1161         Cur = Head;
1162
1163         for (i = 0; i < NumBuffers - 1; i++) {
1164                 Next = (struct SBufferHeader *)
1165                         (((u8 *) Cur) + SIZEOF_SBufferHeader);
1166                 PARingBufferNext = PARingBufferCur + SIZEOF_SBufferHeader;
1167                 Cur->Next = Next;
1168                 Cur->ngeneBuffer.Next = PARingBufferNext;
1169                 Cur = Next;
1170                 PARingBufferCur = PARingBufferNext;
1171         }
1172         /* Last Buffer points back to first one */
1173         Cur->Next = Head;
1174         Cur->ngeneBuffer.Next = PARingBufferHead;
1175
1176         descr->Head       = Head;
1177         descr->MemSize    = MemSize;
1178         descr->PAHead     = PARingBufferHead;
1179         descr->NumBuffers = NumBuffers;
1180
1181         return 0;
1182 }
1183
1184 static int AllocateRingBuffers(struct pci_dev *pci_dev,
1185                                dma_addr_t of,
1186                                struct SRingBufferDescriptor *pRingBuffer,
1187                                u32 Buffer1Length, u32 Buffer2Length)
1188 {
1189         dma_addr_t tmp;
1190         u32 i, j;
1191         int status = 0;
1192         u32 SCListMemSize = pRingBuffer->NumBuffers
1193                 * ((Buffer2Length != 0) ? (NUM_SCATTER_GATHER_ENTRIES * 2) :
1194                     NUM_SCATTER_GATHER_ENTRIES)
1195                 * sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1196
1197         u64 PASCListMem;
1198         struct HW_SCATTER_GATHER_ELEMENT *SCListEntry;
1199         u64 PASCListEntry;
1200         struct SBufferHeader *Cur;
1201         void *SCListMem;
1202
1203         if (SCListMemSize < 4096)
1204                 SCListMemSize = 4096;
1205
1206         SCListMem = pci_alloc_consistent(pci_dev, SCListMemSize, &tmp);
1207
1208         PASCListMem = tmp;
1209         if (SCListMem == NULL)
1210                 return -ENOMEM;
1211
1212         memset(SCListMem, 0, SCListMemSize);
1213
1214         pRingBuffer->SCListMem = SCListMem;
1215         pRingBuffer->PASCListMem = PASCListMem;
1216         pRingBuffer->SCListMemSize = SCListMemSize;
1217         pRingBuffer->Buffer1Length = Buffer1Length;
1218         pRingBuffer->Buffer2Length = Buffer2Length;
1219
1220         SCListEntry = SCListMem;
1221         PASCListEntry = PASCListMem;
1222         Cur = pRingBuffer->Head;
1223
1224         for (i = 0; i < pRingBuffer->NumBuffers; i += 1, Cur = Cur->Next) {
1225                 u64 PABuffer;
1226
1227                 void *Buffer = pci_alloc_consistent(pci_dev, Buffer1Length,
1228                                                     &tmp);
1229                 PABuffer = tmp;
1230
1231                 if (Buffer == NULL)
1232                         return -ENOMEM;
1233
1234                 Cur->Buffer1 = Buffer;
1235
1236                 SCListEntry->Address = PABuffer;
1237                 SCListEntry->Length  = Buffer1Length;
1238
1239                 Cur->scList1 = SCListEntry;
1240                 Cur->ngeneBuffer.Address_of_first_entry_1 = PASCListEntry;
1241                 Cur->ngeneBuffer.Number_of_entries_1 =
1242                         NUM_SCATTER_GATHER_ENTRIES;
1243
1244                 SCListEntry += 1;
1245                 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1246
1247 #if NUM_SCATTER_GATHER_ENTRIES > 1
1248                 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j += 1) {
1249                         SCListEntry->Address = of;
1250                         SCListEntry->Length = OVERFLOW_BUFFER_SIZE;
1251                         SCListEntry += 1;
1252                         PASCListEntry +=
1253                                 sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1254                 }
1255 #endif
1256
1257                 if (!Buffer2Length)
1258                         continue;
1259
1260                 Buffer = pci_alloc_consistent(pci_dev, Buffer2Length, &tmp);
1261                 PABuffer = tmp;
1262
1263                 if (Buffer == NULL)
1264                         return -ENOMEM;
1265
1266                 Cur->Buffer2 = Buffer;
1267
1268                 SCListEntry->Address = PABuffer;
1269                 SCListEntry->Length  = Buffer2Length;
1270
1271                 Cur->scList2 = SCListEntry;
1272                 Cur->ngeneBuffer.Address_of_first_entry_2 = PASCListEntry;
1273                 Cur->ngeneBuffer.Number_of_entries_2 =
1274                         NUM_SCATTER_GATHER_ENTRIES;
1275
1276                 SCListEntry   += 1;
1277                 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1278
1279 #if NUM_SCATTER_GATHER_ENTRIES > 1
1280                 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j++) {
1281                         SCListEntry->Address = of;
1282                         SCListEntry->Length = OVERFLOW_BUFFER_SIZE;
1283                         SCListEntry += 1;
1284                         PASCListEntry +=
1285                                 sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1286                 }
1287 #endif
1288
1289         }
1290
1291         return status;
1292 }
1293
1294 static int FillTSIdleBuffer(struct SRingBufferDescriptor *pIdleBuffer,
1295                             struct SRingBufferDescriptor *pRingBuffer)
1296 {
1297         int status = 0;
1298
1299         /* Copy pointer to scatter gather list in TSRingbuffer
1300            structure for buffer 2
1301            Load number of buffer
1302         */
1303         u32 n = pRingBuffer->NumBuffers;
1304
1305         /* Point to first buffer entry */
1306         struct SBufferHeader *Cur = pRingBuffer->Head;
1307         int i;
1308         /* Loop thru all buffer and set Buffer 2 pointers to TSIdlebuffer */
1309         for (i = 0; i < n; i++) {
1310                 Cur->Buffer2 = pIdleBuffer->Head->Buffer1;
1311                 Cur->scList2 = pIdleBuffer->Head->scList1;
1312                 Cur->ngeneBuffer.Address_of_first_entry_2 =
1313                         pIdleBuffer->Head->ngeneBuffer.
1314                         Address_of_first_entry_1;
1315                 Cur->ngeneBuffer.Number_of_entries_2 =
1316                         pIdleBuffer->Head->ngeneBuffer.Number_of_entries_1;
1317                 Cur = Cur->Next;
1318         }
1319         return status;
1320 }
1321
1322 static u32 RingBufferSizes[MAX_STREAM] = {
1323         RING_SIZE_VIDEO,
1324         RING_SIZE_VIDEO,
1325         RING_SIZE_AUDIO,
1326         RING_SIZE_AUDIO,
1327         RING_SIZE_AUDIO,
1328 };
1329
1330 static u32 Buffer1Sizes[MAX_STREAM] = {
1331         MAX_VIDEO_BUFFER_SIZE,
1332         MAX_VIDEO_BUFFER_SIZE,
1333         MAX_AUDIO_BUFFER_SIZE,
1334         MAX_AUDIO_BUFFER_SIZE,
1335         MAX_AUDIO_BUFFER_SIZE
1336 };
1337
1338 static u32 Buffer2Sizes[MAX_STREAM] = {
1339         MAX_VBI_BUFFER_SIZE,
1340         MAX_VBI_BUFFER_SIZE,
1341         0,
1342         0,
1343         0
1344 };
1345
1346
1347 static int AllocCommonBuffers(struct ngene *dev)
1348 {
1349         int status = 0, i;
1350
1351         dev->FWInterfaceBuffer = pci_alloc_consistent(dev->pci_dev, 4096,
1352                                                      &dev->PAFWInterfaceBuffer);
1353         if (!dev->FWInterfaceBuffer)
1354                 return -ENOMEM;
1355         dev->hosttongene = dev->FWInterfaceBuffer;
1356         dev->ngenetohost = dev->FWInterfaceBuffer + 256;
1357         dev->EventBuffer = dev->FWInterfaceBuffer + 512;
1358
1359         dev->OverflowBuffer = pci_alloc_consistent(dev->pci_dev,
1360                                                    OVERFLOW_BUFFER_SIZE,
1361                                                    &dev->PAOverflowBuffer);
1362         if (!dev->OverflowBuffer)
1363                 return -ENOMEM;
1364         memset(dev->OverflowBuffer, 0, OVERFLOW_BUFFER_SIZE);
1365
1366         for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) {
1367                 int type = dev->card_info->io_type[i];
1368
1369                 dev->channel[i].State = KSSTATE_STOP;
1370
1371                 if (type & (NGENE_IO_TV | NGENE_IO_HDTV | NGENE_IO_AIN)) {
1372                         status = create_ring_buffer(dev->pci_dev,
1373                                                     &dev->channel[i].RingBuffer,
1374                                                     RingBufferSizes[i]);
1375                         if (status < 0)
1376                                 break;
1377
1378                         if (type & (NGENE_IO_TV | NGENE_IO_AIN)) {
1379                                 status = AllocateRingBuffers(dev->pci_dev,
1380                                                              dev->
1381                                                              PAOverflowBuffer,
1382                                                              &dev->channel[i].
1383                                                              RingBuffer,
1384                                                              Buffer1Sizes[i],
1385                                                              Buffer2Sizes[i]);
1386                                 if (status < 0)
1387                                         break;
1388                         } else if (type & NGENE_IO_HDTV) {
1389                                 status = AllocateRingBuffers(dev->pci_dev,
1390                                                              dev->
1391                                                              PAOverflowBuffer,
1392                                                              &dev->channel[i].
1393                                                              RingBuffer,
1394                                                            MAX_HDTV_BUFFER_SIZE,
1395                                                              0);
1396                                 if (status < 0)
1397                                         break;
1398                         }
1399                 }
1400
1401                 if (type & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1402
1403                         status = create_ring_buffer(dev->pci_dev,
1404                                                     &dev->channel[i].
1405                                                     TSRingBuffer, RING_SIZE_TS);
1406                         if (status < 0)
1407                                 break;
1408
1409                         status = AllocateRingBuffers(dev->pci_dev,
1410                                                      dev->PAOverflowBuffer,
1411                                                      &dev->channel[i].
1412                                                      TSRingBuffer,
1413                                                      MAX_TS_BUFFER_SIZE, 0);
1414                         if (status)
1415                                 break;
1416                 }
1417
1418                 if (type & NGENE_IO_TSOUT) {
1419                         status = create_ring_buffer(dev->pci_dev,
1420                                                     &dev->channel[i].
1421                                                     TSIdleBuffer, 1);
1422                         if (status < 0)
1423                                 break;
1424                         status = AllocateRingBuffers(dev->pci_dev,
1425                                                      dev->PAOverflowBuffer,
1426                                                      &dev->channel[i].
1427                                                      TSIdleBuffer,
1428                                                      MAX_TS_BUFFER_SIZE, 0);
1429                         if (status)
1430                                 break;
1431                         FillTSIdleBuffer(&dev->channel[i].TSIdleBuffer,
1432                                          &dev->channel[i].TSRingBuffer);
1433                 }
1434         }
1435         return status;
1436 }
1437
1438 static void ngene_release_buffers(struct ngene *dev)
1439 {
1440         if (dev->iomem)
1441                 iounmap(dev->iomem);
1442         free_common_buffers(dev);
1443         vfree(dev->tsout_buf);
1444         vfree(dev->ain_buf);
1445         vfree(dev->vin_buf);
1446         vfree(dev);
1447 }
1448
1449 static int ngene_get_buffers(struct ngene *dev)
1450 {
1451         if (AllocCommonBuffers(dev))
1452                 return -ENOMEM;
1453         if (dev->card_info->io_type[4] & NGENE_IO_TSOUT) {
1454                 dev->tsout_buf = vmalloc(TSOUT_BUF_SIZE);
1455                 if (!dev->tsout_buf)
1456                         return -ENOMEM;
1457                 dvb_ringbuffer_init(&dev->tsout_rbuf,
1458                                     dev->tsout_buf, TSOUT_BUF_SIZE);
1459         }
1460         if (dev->card_info->io_type[2] & NGENE_IO_AIN) {
1461                 dev->ain_buf = vmalloc(AIN_BUF_SIZE);
1462                 if (!dev->ain_buf)
1463                         return -ENOMEM;
1464                 dvb_ringbuffer_init(&dev->ain_rbuf, dev->ain_buf, AIN_BUF_SIZE);
1465         }
1466         if (dev->card_info->io_type[0] & NGENE_IO_HDTV) {
1467                 dev->vin_buf = vmalloc(VIN_BUF_SIZE);
1468                 if (!dev->vin_buf)
1469                         return -ENOMEM;
1470                 dvb_ringbuffer_init(&dev->vin_rbuf, dev->vin_buf, VIN_BUF_SIZE);
1471         }
1472         dev->iomem = ioremap(pci_resource_start(dev->pci_dev, 0),
1473                              pci_resource_len(dev->pci_dev, 0));
1474         if (!dev->iomem)
1475                 return -ENOMEM;
1476
1477         return 0;
1478 }
1479
1480 static void ngene_init(struct ngene *dev)
1481 {
1482         int i;
1483
1484         tasklet_init(&dev->event_tasklet, event_tasklet, (unsigned long)dev);
1485
1486         memset_io(dev->iomem + 0xc000, 0x00, 0x220);
1487         memset_io(dev->iomem + 0xc400, 0x00, 0x100);
1488
1489         for (i = 0; i < MAX_STREAM; i++) {
1490                 dev->channel[i].dev = dev;
1491                 dev->channel[i].number = i;
1492         }
1493
1494         dev->fw_interface_version = 0;
1495
1496         ngwritel(0, NGENE_INT_ENABLE);
1497
1498         dev->icounts = ngreadl(NGENE_INT_COUNTS);
1499
1500         dev->device_version = ngreadl(DEV_VER) & 0x0f;
1501         printk(KERN_INFO DEVICE_NAME ": Device version %d\n",
1502                dev->device_version);
1503 }
1504
1505 static int ngene_load_firm(struct ngene *dev)
1506 {
1507         u32 size;
1508         const struct firmware *fw = NULL;
1509         u8 *ngene_fw;
1510         char *fw_name;
1511         int err, version;
1512
1513         version = dev->card_info->fw_version;
1514
1515         switch (version) {
1516         default:
1517         case 15:
1518                 version = 15;
1519                 size = 23466;
1520                 fw_name = "ngene_15.fw";
1521                 break;
1522         case 16:
1523                 size = 23498;
1524                 fw_name = "ngene_16.fw";
1525                 break;
1526         case 17:
1527                 size = 24446;
1528                 fw_name = "ngene_17.fw";
1529                 break;
1530         }
1531
1532         if (request_firmware(&fw, fw_name, &dev->pci_dev->dev) < 0) {
1533                 printk(KERN_ERR DEVICE_NAME
1534                         ": Could not load firmware file %s.\n", fw_name);
1535                 printk(KERN_INFO DEVICE_NAME
1536                         ": Copy %s to your hotplug directory!\n", fw_name);
1537                 return -1;
1538         }
1539         if (size != fw->size) {
1540                 printk(KERN_ERR DEVICE_NAME
1541                         ": Firmware %s has invalid size!", fw_name);
1542                 err = -1;
1543         } else {
1544                 printk(KERN_INFO DEVICE_NAME
1545                         ": Loading firmware file %s.\n", fw_name);
1546                 ngene_fw = (u8 *) fw->data;
1547                 err = ngene_command_load_firmware(dev, ngene_fw, size);
1548         }
1549
1550         release_firmware(fw);
1551
1552         return err;
1553 }
1554
1555 static void ngene_stop(struct ngene *dev)
1556 {
1557         down(&dev->cmd_mutex);
1558         i2c_del_adapter(&(dev->channel[0].i2c_adapter));
1559         i2c_del_adapter(&(dev->channel[1].i2c_adapter));
1560         ngwritel(0, NGENE_INT_ENABLE);
1561         ngwritel(0, NGENE_COMMAND);
1562         ngwritel(0, NGENE_COMMAND_HI);
1563         ngwritel(0, NGENE_STATUS);
1564         ngwritel(0, NGENE_STATUS_HI);
1565         ngwritel(0, NGENE_EVENT);
1566         ngwritel(0, NGENE_EVENT_HI);
1567         free_irq(dev->pci_dev->irq, dev);
1568 }
1569
1570 static int ngene_start(struct ngene *dev)
1571 {
1572         int stat;
1573         int i;
1574
1575         pci_set_master(dev->pci_dev);
1576         ngene_init(dev);
1577
1578         stat = request_irq(dev->pci_dev->irq, irq_handler,
1579                            IRQF_SHARED, "nGene",
1580                            (void *)dev);
1581         if (stat < 0)
1582                 return stat;
1583
1584         init_waitqueue_head(&dev->cmd_wq);
1585         init_waitqueue_head(&dev->tx_wq);
1586         init_waitqueue_head(&dev->rx_wq);
1587         sema_init(&dev->cmd_mutex, 1);
1588         sema_init(&dev->stream_mutex, 1);
1589         sema_init(&dev->pll_mutex, 1);
1590         sema_init(&dev->i2c_switch_mutex, 1);
1591         spin_lock_init(&dev->cmd_lock);
1592         for (i = 0; i < MAX_STREAM; i++)
1593                 spin_lock_init(&dev->channel[i].state_lock);
1594         ngwritel(1, TIMESTAMPS);
1595
1596         ngwritel(1, NGENE_INT_ENABLE);
1597
1598         stat = ngene_load_firm(dev);
1599         if (stat < 0)
1600                 goto fail;
1601
1602         stat = ngene_i2c_init(dev, 0);
1603         if (stat < 0)
1604                 goto fail;
1605
1606         stat = ngene_i2c_init(dev, 1);
1607         if (stat < 0)
1608                 goto fail;
1609
1610         if (dev->card_info->fw_version == 17) {
1611                 u8 tsin4_config[6] = {
1612                         3072 / 64, 3072 / 64, 0, 3072 / 64, 3072 / 64, 0};
1613                 u8 default_config[6] = {
1614                         4096 / 64, 4096 / 64, 0, 2048 / 64, 2048 / 64, 0};
1615                 u8 *bconf = default_config;
1616
1617                 if (dev->card_info->io_type[3] == NGENE_IO_TSIN)
1618                         bconf = tsin4_config;
1619                 dprintk(KERN_DEBUG DEVICE_NAME ": FW 17 buffer config\n");
1620                 stat = ngene_command_config_free_buf(dev, bconf);
1621         } else {
1622                 int bconf = BUFFER_CONFIG_4422;
1623                 if (dev->card_info->io_type[3] == NGENE_IO_TSIN)
1624                         bconf = BUFFER_CONFIG_3333;
1625                 stat = ngene_command_config_buf(dev, bconf);
1626         }
1627         return stat;
1628 fail:
1629         ngwritel(0, NGENE_INT_ENABLE);
1630         free_irq(dev->pci_dev->irq, dev);
1631         return stat;
1632 }
1633
1634
1635
1636 /****************************************************************************/
1637 /* Switch control (I2C gates, etc.) *****************************************/
1638 /****************************************************************************/
1639
1640
1641 /****************************************************************************/
1642 /* Demod/tuner attachment ***************************************************/
1643 /****************************************************************************/
1644
1645 static int tuner_attach_stv6110(struct ngene_channel *chan)
1646 {
1647         struct stv090x_config *feconf = (struct stv090x_config *)
1648                 chan->dev->card_info->fe_config[chan->number];
1649         struct stv6110x_config *tunerconf = (struct stv6110x_config *)
1650                 chan->dev->card_info->tuner_config[chan->number];
1651         struct stv6110x_devctl *ctl;
1652
1653         ctl = dvb_attach(stv6110x_attach, chan->fe, tunerconf,
1654                          &chan->i2c_adapter);
1655         if (ctl == NULL) {
1656                 printk(KERN_ERR DEVICE_NAME ": No STV6110X found!\n");
1657                 return -ENODEV;
1658         }
1659
1660         feconf->tuner_init          = ctl->tuner_init;
1661         feconf->tuner_set_mode      = ctl->tuner_set_mode;
1662         feconf->tuner_set_frequency = ctl->tuner_set_frequency;
1663         feconf->tuner_get_frequency = ctl->tuner_get_frequency;
1664         feconf->tuner_set_bandwidth = ctl->tuner_set_bandwidth;
1665         feconf->tuner_get_bandwidth = ctl->tuner_get_bandwidth;
1666         feconf->tuner_set_bbgain    = ctl->tuner_set_bbgain;
1667         feconf->tuner_get_bbgain    = ctl->tuner_get_bbgain;
1668         feconf->tuner_set_refclk    = ctl->tuner_set_refclk;
1669         feconf->tuner_get_status    = ctl->tuner_get_status;
1670
1671         return 0;
1672 }
1673
1674
1675 static int demod_attach_stv0900(struct ngene_channel *chan)
1676 {
1677         struct stv090x_config *feconf = (struct stv090x_config *)
1678                 chan->dev->card_info->fe_config[chan->number];
1679
1680         chan->fe = dvb_attach(stv090x_attach,
1681                         feconf,
1682                         &chan->i2c_adapter,
1683                         chan->number == 0 ? STV090x_DEMODULATOR_0 :
1684                                             STV090x_DEMODULATOR_1);
1685         if (chan->fe == NULL) {
1686                 printk(KERN_ERR DEVICE_NAME ": No STV0900 found!\n");
1687                 return -ENODEV;
1688         }
1689
1690         if (!dvb_attach(lnbh24_attach, chan->fe, &chan->i2c_adapter, 0,
1691                         0, chan->dev->card_info->lnb[chan->number])) {
1692                 printk(KERN_ERR DEVICE_NAME ": No LNBH24 found!\n");
1693                 dvb_frontend_detach(chan->fe);
1694                 return -ENODEV;
1695         }
1696
1697         return 0;
1698 }
1699
1700 /****************************************************************************/
1701 /****************************************************************************/
1702 /****************************************************************************/
1703
1704 static void release_channel(struct ngene_channel *chan)
1705 {
1706         struct dvb_demux *dvbdemux = &chan->demux;
1707         struct ngene *dev = chan->dev;
1708         struct ngene_info *ni = dev->card_info;
1709         int io = ni->io_type[chan->number];
1710
1711 #ifdef COMMAND_TIMEOUT_WORKAROUND
1712         if (chan->running)
1713                 set_transfer(chan, 0);
1714 #endif
1715
1716         tasklet_kill(&chan->demux_tasklet);
1717
1718         if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1719                 if (chan->fe) {
1720                         dvb_unregister_frontend(chan->fe);
1721                         dvb_frontend_detach(chan->fe);
1722                         chan->fe = 0;
1723                 }
1724                 dvbdemux->dmx.close(&dvbdemux->dmx);
1725                 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
1726                                               &chan->hw_frontend);
1727                 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
1728                                               &chan->mem_frontend);
1729                 dvb_dmxdev_release(&chan->dmxdev);
1730                 dvb_dmx_release(&chan->demux);
1731
1732                 if (chan->number == 0 || !one_adapter)
1733                         dvb_unregister_adapter(&dev->adapter[chan->number]);
1734         }
1735 }
1736
1737 static int init_channel(struct ngene_channel *chan)
1738 {
1739         int ret = 0, nr = chan->number;
1740         struct dvb_adapter *adapter = NULL;
1741         struct dvb_demux *dvbdemux = &chan->demux;
1742         struct ngene *dev = chan->dev;
1743         struct ngene_info *ni = dev->card_info;
1744         int io = ni->io_type[nr];
1745
1746         tasklet_init(&chan->demux_tasklet, demux_tasklet, (unsigned long)chan);
1747         chan->users = 0;
1748         chan->type = io;
1749         chan->mode = chan->type;        /* for now only one mode */
1750
1751         if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1752                 if (nr >= STREAM_AUDIOIN1)
1753                         chan->DataFormatFlags = DF_SWAP32;
1754                 if (nr == 0 || !one_adapter) {
1755                         adapter = &dev->adapter[nr];
1756                         ret = dvb_register_adapter(adapter, "nGene",
1757                                                    THIS_MODULE,
1758                                                    &chan->dev->pci_dev->dev,
1759                                                    adapter_nr);
1760                         if (ret < 0)
1761                                 return ret;
1762                 } else {
1763                         adapter = &dev->adapter[0];
1764                 }
1765
1766                 ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux",
1767                                               ngene_start_feed,
1768                                               ngene_stop_feed, chan);
1769                 ret = my_dvb_dmxdev_ts_card_init(&chan->dmxdev, &chan->demux,
1770                                                  &chan->hw_frontend,
1771                                                  &chan->mem_frontend, adapter);
1772         }
1773
1774         if (io & NGENE_IO_TSIN) {
1775                 chan->fe = NULL;
1776                 if (ni->demod_attach[nr])
1777                         ni->demod_attach[nr](chan);
1778                 if (chan->fe) {
1779                         if (dvb_register_frontend(adapter, chan->fe) < 0) {
1780                                 if (chan->fe->ops.release)
1781                                         chan->fe->ops.release(chan->fe);
1782                                 chan->fe = NULL;
1783                         }
1784                 }
1785                 if (chan->fe && ni->tuner_attach[nr])
1786                         if (ni->tuner_attach[nr] (chan) < 0) {
1787                                 printk(KERN_ERR DEVICE_NAME
1788                                        ": Tuner attach failed on channel %d!\n",
1789                                        nr);
1790                         }
1791         }
1792         return ret;
1793 }
1794
1795 static int init_channels(struct ngene *dev)
1796 {
1797         int i, j;
1798
1799         for (i = 0; i < MAX_STREAM; i++) {
1800                 if (init_channel(&dev->channel[i]) < 0) {
1801                         for (j = i - 1; j >= 0; j--)
1802                                 release_channel(&dev->channel[j]);
1803                         return -1;
1804                 }
1805         }
1806         return 0;
1807 }
1808
1809 /****************************************************************************/
1810 /* device probe/remove calls ************************************************/
1811 /****************************************************************************/
1812
1813 static void __devexit ngene_remove(struct pci_dev *pdev)
1814 {
1815         struct ngene *dev = (struct ngene *)pci_get_drvdata(pdev);
1816         int i;
1817
1818         tasklet_kill(&dev->event_tasklet);
1819         for (i = MAX_STREAM - 1; i >= 0; i--)
1820                 release_channel(&dev->channel[i]);
1821         ngene_stop(dev);
1822         ngene_release_buffers(dev);
1823         pci_set_drvdata(pdev, 0);
1824         pci_disable_device(pdev);
1825 }
1826
1827 static int __devinit ngene_probe(struct pci_dev *pci_dev,
1828                                  const struct pci_device_id *id)
1829 {
1830         struct ngene *dev;
1831         int stat = 0;
1832
1833         if (pci_enable_device(pci_dev) < 0)
1834                 return -ENODEV;
1835
1836         dev = vmalloc(sizeof(struct ngene));
1837         if (dev == NULL) {
1838                 stat = -ENOMEM;
1839                 goto fail0;
1840         }
1841         memset(dev, 0, sizeof(struct ngene));
1842
1843         dev->pci_dev = pci_dev;
1844         dev->card_info = (struct ngene_info *)id->driver_data;
1845         printk(KERN_INFO DEVICE_NAME ": Found %s\n", dev->card_info->name);
1846
1847         pci_set_drvdata(pci_dev, dev);
1848
1849         /* Alloc buffers and start nGene */
1850         stat = ngene_get_buffers(dev);
1851         if (stat < 0)
1852                 goto fail1;
1853         stat = ngene_start(dev);
1854         if (stat < 0)
1855                 goto fail1;
1856
1857         dev->i2c_current_bus = -1;
1858
1859         /* Register DVB adapters and devices for both channels */
1860         if (init_channels(dev) < 0)
1861                 goto fail2;
1862
1863         return 0;
1864
1865 fail2:
1866         ngene_stop(dev);
1867 fail1:
1868         ngene_release_buffers(dev);
1869 fail0:
1870         pci_disable_device(pci_dev);
1871         pci_set_drvdata(pci_dev, 0);
1872         return stat;
1873 }
1874
1875 /****************************************************************************/
1876 /* Card configs *************************************************************/
1877 /****************************************************************************/
1878
1879 static struct stv090x_config fe_cineS2 = {
1880         .device         = STV0900,
1881         .demod_mode     = STV090x_DUAL,
1882         .clk_mode       = STV090x_CLK_EXT,
1883
1884         .xtal           = 27000000,
1885         .address        = 0x68,
1886
1887         .ts1_mode       = STV090x_TSMODE_SERIAL_PUNCTURED,
1888         .ts2_mode       = STV090x_TSMODE_SERIAL_PUNCTURED,
1889
1890         .repeater_level = STV090x_RPTLEVEL_16,
1891
1892         .adc1_range     = STV090x_ADC_1Vpp,
1893         .adc2_range     = STV090x_ADC_1Vpp,
1894
1895         .diseqc_envelope_mode = true,
1896 };
1897
1898 static struct stv6110x_config tuner_cineS2_0 = {
1899         .addr   = 0x60,
1900         .refclk = 27000000,
1901         .clk_div = 1,
1902 };
1903
1904 static struct stv6110x_config tuner_cineS2_1 = {
1905         .addr   = 0x63,
1906         .refclk = 27000000,
1907         .clk_div = 1,
1908 };
1909
1910 static struct ngene_info ngene_info_cineS2 = {
1911         .type           = NGENE_SIDEWINDER,
1912         .name           = "Linux4Media cineS2 DVB-S2 Twin Tuner",
1913         .io_type        = {NGENE_IO_TSIN, NGENE_IO_TSIN},
1914         .demod_attach   = {demod_attach_stv0900, demod_attach_stv0900},
1915         .tuner_attach   = {tuner_attach_stv6110, tuner_attach_stv6110},
1916         .fe_config      = {&fe_cineS2, &fe_cineS2},
1917         .tuner_config   = {&tuner_cineS2_0, &tuner_cineS2_1},
1918         .lnb            = {0x0b, 0x08},
1919         .tsf            = {3, 3},
1920         .fw_version     = 15,
1921 };
1922
1923 static struct ngene_info ngene_info_satixs2 = {
1924         .type           = NGENE_SIDEWINDER,
1925         .name           = "Mystique SaTiX-S2 Dual",
1926         .io_type        = {NGENE_IO_TSIN, NGENE_IO_TSIN},
1927         .demod_attach   = {demod_attach_stv0900, demod_attach_stv0900},
1928         .tuner_attach   = {tuner_attach_stv6110, tuner_attach_stv6110},
1929         .fe_config      = {&fe_cineS2, &fe_cineS2},
1930         .tuner_config   = {&tuner_cineS2_0, &tuner_cineS2_1},
1931         .lnb            = {0x0b, 0x08},
1932         .tsf            = {3, 3},
1933         .fw_version     = 15,
1934 };
1935
1936 /****************************************************************************/
1937
1938
1939
1940 /****************************************************************************/
1941 /* PCI Subsystem ID *********************************************************/
1942 /****************************************************************************/
1943
1944 #define NGENE_ID(_subvend, _subdev, _driverdata) { \
1945         .vendor = NGENE_VID, .device = NGENE_PID, \
1946         .subvendor = _subvend, .subdevice = _subdev, \
1947         .driver_data = (unsigned long) &_driverdata }
1948
1949 /****************************************************************************/
1950
1951 static const struct pci_device_id ngene_id_tbl[] __devinitdata = {
1952         NGENE_ID(0x18c3, 0xabc3, ngene_info_cineS2),
1953         NGENE_ID(0x18c3, 0xabc4, ngene_info_cineS2),
1954         NGENE_ID(0x18c3, 0xdb01, ngene_info_satixs2),
1955         {0}
1956 };
1957 MODULE_DEVICE_TABLE(pci, ngene_id_tbl);
1958
1959 /****************************************************************************/
1960 /* Init/Exit ****************************************************************/
1961 /****************************************************************************/
1962
1963 static pci_ers_result_t ngene_error_detected(struct pci_dev *dev,
1964                                              enum pci_channel_state state)
1965 {
1966         printk(KERN_ERR DEVICE_NAME ": PCI error\n");
1967         if (state == pci_channel_io_perm_failure)
1968                 return PCI_ERS_RESULT_DISCONNECT;
1969         if (state == pci_channel_io_frozen)
1970                 return PCI_ERS_RESULT_NEED_RESET;
1971         return PCI_ERS_RESULT_CAN_RECOVER;
1972 }
1973
1974 static pci_ers_result_t ngene_link_reset(struct pci_dev *dev)
1975 {
1976         printk(KERN_INFO DEVICE_NAME ": link reset\n");
1977         return 0;
1978 }
1979
1980 static pci_ers_result_t ngene_slot_reset(struct pci_dev *dev)
1981 {
1982         printk(KERN_INFO DEVICE_NAME ": slot reset\n");
1983         return 0;
1984 }
1985
1986 static void ngene_resume(struct pci_dev *dev)
1987 {
1988         printk(KERN_INFO DEVICE_NAME ": resume\n");
1989 }
1990
1991 static struct pci_error_handlers ngene_errors = {
1992         .error_detected = ngene_error_detected,
1993         .link_reset = ngene_link_reset,
1994         .slot_reset = ngene_slot_reset,
1995         .resume = ngene_resume,
1996 };
1997
1998 static struct pci_driver ngene_pci_driver = {
1999         .name        = "ngene",
2000         .id_table    = ngene_id_tbl,
2001         .probe       = ngene_probe,
2002         .remove      = __devexit_p(ngene_remove),
2003         .err_handler = &ngene_errors,
2004 };
2005
2006 static __init int module_init_ngene(void)
2007 {
2008         printk(KERN_INFO
2009                "nGene PCIE bridge driver, Copyright (C) 2005-2007 Micronas\n");
2010         return pci_register_driver(&ngene_pci_driver);
2011 }
2012
2013 static __exit void module_exit_ngene(void)
2014 {
2015         pci_unregister_driver(&ngene_pci_driver);
2016 }
2017
2018 module_init(module_init_ngene);
2019 module_exit(module_exit_ngene);
2020
2021 MODULE_DESCRIPTION("nGene");
2022 MODULE_AUTHOR("Micronas, Ralph Metzler, Manfred Voelkel");
2023 MODULE_LICENSE("GPL");