drivers/iommu/tegra-smmu.c

   1 /*
   2  * IOMMU API for SMMU in Tegra30
   3  *
   4  * Copyright (c) 2011-2013, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program; if not, write to the Free Software Foundation, Inc.,
  17  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18  */
  19
  20 #define pr_fmt(fmt)     "%s(): " fmt, __func__
  21
  22 #include <linux/err.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/slab.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/mm.h>
  29 #include <linux/pagemap.h>
  30 #include <linux/device.h>
  31 #include <linux/sched.h>
  32 #include <linux/iommu.h>
  33 #include <linux/io.h>
  34 #include <linux/of.h>
  35 #include <linux/of_iommu.h>
  36 #include <linux/debugfs.h>
  37 #include <linux/seq_file.h>
  38 #include <linux/tegra-ahb.h>
  39
  40 #include <asm/page.h>
  41 #include <asm/cacheflush.h>
  42
  43 #include <mach/tegra_smmu.h>
  44
  45 enum smmu_hwgrp {
  46         HWGRP_AFI,
  47         HWGRP_AVPC,
  48         HWGRP_DC,
  49         HWGRP_DCB,
  50         HWGRP_EPP,
  51         HWGRP_G2,
  52         HWGRP_HC,
  53         HWGRP_HDA,
  54         HWGRP_ISP,
  55         HWGRP_MPE,
  56         HWGRP_NV,
  57         HWGRP_NV2,
  58         HWGRP_PPCS,
  59         HWGRP_SATA,
  60         HWGRP_VDE,
  61         HWGRP_VI,
  62
  63         HWGRP_COUNT,
  64
  65         HWGRP_END = ~0,
  66 };
  67
  68 #define HWG_AFI         (1 << HWGRP_AFI)
  69 #define HWG_AVPC        (1 << HWGRP_AVPC)
  70 #define HWG_DC          (1 << HWGRP_DC)
  71 #define HWG_DCB         (1 << HWGRP_DCB)
  72 #define HWG_EPP         (1 << HWGRP_EPP)
  73 #define HWG_G2          (1 << HWGRP_G2)
  74 #define HWG_HC          (1 << HWGRP_HC)
  75 #define HWG_HDA         (1 << HWGRP_HDA)
  76 #define HWG_ISP         (1 << HWGRP_ISP)
  77 #define HWG_MPE         (1 << HWGRP_MPE)
  78 #define HWG_NV          (1 << HWGRP_NV)
  79 #define HWG_NV2         (1 << HWGRP_NV2)
  80 #define HWG_PPCS        (1 << HWGRP_PPCS)
  81 #define HWG_SATA        (1 << HWGRP_SATA)
  82 #define HWG_VDE         (1 << HWGRP_VDE)
  83 #define HWG_VI          (1 << HWGRP_VI)
  84
  85 /* REVISIT: With new configurations for t114/124/148 passed from DT */
  86 #define SKIP_SWGRP_CHECK
  87
  88 /* bitmap of the page sizes currently supported */
  89 #define SMMU_IOMMU_PGSIZES      (SZ_4K)
  90
  91 #define SMMU_CONFIG                             0x10
  92 #define SMMU_CONFIG_DISABLE                     0
  93 #define SMMU_CONFIG_ENABLE                      1
  94
  95 /* REVISIT: To support multiple MCs */
  96 enum {
  97         _MC = 0,
  98 };
  99
 100 enum {
 101         _TLB = 0,
 102         _PTC,
 103 };
 104
 105 #define SMMU_CACHE_CONFIG_BASE                  0x14
 106 #define __SMMU_CACHE_CONFIG(mc, cache)          (SMMU_CACHE_CONFIG_BASE + 4 * cache)
 107 #define SMMU_CACHE_CONFIG(cache)                __SMMU_CACHE_CONFIG(_MC, cache)
 108
 109 #define SMMU_CACHE_CONFIG_STATS_SHIFT           31
 110 #define SMMU_CACHE_CONFIG_STATS_ENABLE          (1 << SMMU_CACHE_CONFIG_STATS_SHIFT)
 111 #define SMMU_CACHE_CONFIG_STATS_TEST_SHIFT      30
 112 #define SMMU_CACHE_CONFIG_STATS_TEST            (1 << SMMU_CACHE_CONFIG_STATS_TEST_SHIFT)
 113
 114 #define SMMU_TLB_CONFIG_HIT_UNDER_MISS__ENABLE  (1 << 29)
 115 #define SMMU_TLB_CONFIG_ACTIVE_LINES__VALUE     0x10
 116 #define SMMU_TLB_CONFIG_RESET_VAL               0x20000010
 117
 118 #define SMMU_PTC_CONFIG_CACHE__ENABLE           (1 << 29)
 119 #define SMMU_PTC_CONFIG_INDEX_MAP__PATTERN      0x3f
 120 #define SMMU_PTC_CONFIG_RESET_VAL               0x2000003f
 121
 122 #define SMMU_PTB_ASID                           0x1c
 123 #define SMMU_PTB_ASID_CURRENT_SHIFT             0
 124
 125 #define SMMU_PTB_DATA                           0x20
 126 #define SMMU_PTB_DATA_RESET_VAL                 0
 127 #define SMMU_PTB_DATA_ASID_NONSECURE_SHIFT      29
 128 #define SMMU_PTB_DATA_ASID_WRITABLE_SHIFT       30
 129 #define SMMU_PTB_DATA_ASID_READABLE_SHIFT       31
 130
 131 #define SMMU_TLB_FLUSH                          0x30
 132 #define SMMU_TLB_FLUSH_VA_MATCH_ALL             0
 133 #define SMMU_TLB_FLUSH_VA_MATCH_SECTION         2
 134 #define SMMU_TLB_FLUSH_VA_MATCH_GROUP           3
 135 #define SMMU_TLB_FLUSH_ASID_SHIFT               29
 136 #define SMMU_TLB_FLUSH_ASID_MATCH_DISABLE       0
 137 #define SMMU_TLB_FLUSH_ASID_MATCH_ENABLE        1
 138 #define SMMU_TLB_FLUSH_ASID_MATCH_SHIFT         31
 139
 140 #define SMMU_PTC_FLUSH                          0x34
 141 #define SMMU_PTC_FLUSH_TYPE_ALL                 0
 142 #define SMMU_PTC_FLUSH_TYPE_ADR                 1
 143 #define SMMU_PTC_FLUSH_ADR_SHIFT                4
 144
 145 #define SMMU_ASID_SECURITY                      0x38
 146
 147 #define SMMU_STATS_CACHE_COUNT_BASE             0x1f0
 148
 149 #define SMMU_STATS_CACHE_COUNT(mc, cache, hitmiss)              \
 150         (SMMU_STATS_CACHE_COUNT_BASE + 8 * cache + 4 * hitmiss)
 151
 152 #define SMMU_TRANSLATION_ENABLE_0               0x228
 153 #define SMMU_TRANSLATION_ENABLE_1               0x22c
 154 #define SMMU_TRANSLATION_ENABLE_2               0x230
 155
 156 #define SMMU_AFI_ASID   0x238   /* PCIE */
 157 #define SMMU_AVPC_ASID  0x23c   /* AVP */
 158 #define SMMU_DC_ASID    0x240   /* Display controller */
 159 #define SMMU_DCB_ASID   0x244   /* Display controller B */
 160 #define SMMU_EPP_ASID   0x248   /* Encoder pre-processor */
 161 #define SMMU_G2_ASID    0x24c   /* 2D engine */
 162 #define SMMU_HC_ASID    0x250   /* Host1x */
 163 #define SMMU_HDA_ASID   0x254   /* High-def audio */
 164 #define SMMU_ISP_ASID   0x258   /* Image signal processor */
 165 #define SMMU_MPE_ASID   0x264   /* MPEG encoder */
 166 #define SMMU_NV_ASID    0x268   /* (3D) */
 167 #define SMMU_NV2_ASID   0x26c   /* (3D) */
 168 #define SMMU_PPCS_ASID  0x270   /* AHB */
 169 #define SMMU_SATA_ASID  0x278   /* SATA */
 170 #define SMMU_VDE_ASID   0x27c   /* Video decoder */
 171 #define SMMU_VI_ASID    0x280   /* Video input */
 172
 173 #define SMMU_PDE_NEXT_SHIFT             28
 174
 175 #define SMMU_TLB_FLUSH_VA_SECTION__MASK         0xffc00000
 176 #define SMMU_TLB_FLUSH_VA_SECTION__SHIFT        12 /* right shift */
 177 #define SMMU_TLB_FLUSH_VA_GROUP__MASK           0xffffc000
 178 #define SMMU_TLB_FLUSH_VA_GROUP__SHIFT          12 /* right shift */
 179 #define SMMU_TLB_FLUSH_VA(iova, which)  \
 180         ((((iova) & SMMU_TLB_FLUSH_VA_##which##__MASK) >> \
 181                 SMMU_TLB_FLUSH_VA_##which##__SHIFT) |   \
 182         SMMU_TLB_FLUSH_VA_MATCH_##which)
 183 #define SMMU_PTB_ASID_CUR(n)    \
 184                 ((n) << SMMU_PTB_ASID_CURRENT_SHIFT)
 185 #define SMMU_TLB_FLUSH_ASID_MATCH_disable               \
 186                 (SMMU_TLB_FLUSH_ASID_MATCH_DISABLE <<   \
 187                         SMMU_TLB_FLUSH_ASID_MATCH_SHIFT)
 188 #define SMMU_TLB_FLUSH_ASID_MATCH__ENABLE               \
 189                 (SMMU_TLB_FLUSH_ASID_MATCH_ENABLE <<    \
 190                         SMMU_TLB_FLUSH_ASID_MATCH_SHIFT)
 191
 192 #define SMMU_PAGE_SHIFT 12
 193 #define SMMU_PAGE_SIZE  (1 << SMMU_PAGE_SHIFT)
 194 #define SMMU_PAGE_MASK  ((1 << SMMU_PAGE_SHIFT) - 1)
 195
 196 #define SMMU_PDIR_COUNT 1024
 197 #define SMMU_PDIR_SIZE  (sizeof(unsigned long) * SMMU_PDIR_COUNT)
 198 #define SMMU_PTBL_COUNT 1024
 199 #define SMMU_PTBL_SIZE  (sizeof(unsigned long) * SMMU_PTBL_COUNT)
 200 #define SMMU_PDIR_SHIFT 12
 201 #define SMMU_PDE_SHIFT  12
 202 #define SMMU_PTE_SHIFT  12
 203 #define SMMU_PFN_MASK   0x000fffff
 204
 205 #define SMMU_ADDR_TO_PFN(addr)  ((addr) >> 12)
 206 #define SMMU_ADDR_TO_PDN(addr)  ((addr) >> 22)
 207 #define SMMU_PDN_TO_ADDR(pdn)   ((pdn) << 22)
 208
 209 #define _READABLE       (1 << SMMU_PTB_DATA_ASID_READABLE_SHIFT)
 210 #define _WRITABLE       (1 << SMMU_PTB_DATA_ASID_WRITABLE_SHIFT)
 211 #define _NONSECURE      (1 << SMMU_PTB_DATA_ASID_NONSECURE_SHIFT)
 212 #define _PDE_NEXT       (1 << SMMU_PDE_NEXT_SHIFT)
 213 #define _MASK_ATTR      (_READABLE | _WRITABLE | _NONSECURE)
 214
 215 #define _PDIR_ATTR      (_READABLE | _WRITABLE | _NONSECURE)
 216
 217 #define _PDE_ATTR       (_READABLE | _WRITABLE | _NONSECURE)
 218 #define _PDE_ATTR_N     (_PDE_ATTR | _PDE_NEXT)
 219 #define _PDE_VACANT(pdn)        (((pdn) << 10) | _PDE_ATTR)
 220
 221 #define _PTE_ATTR       (_READABLE | _WRITABLE | _NONSECURE)
 222 #define _PTE_VACANT(addr)       (((addr) >> SMMU_PAGE_SHIFT) | _PTE_ATTR)
 223
 224 #define SMMU_MK_PDIR(page, attr)        \
 225                 ((page_to_phys(page) >> SMMU_PDIR_SHIFT) | (attr))
 226 #define SMMU_MK_PDE(page, attr)         \
 227                 (unsigned long)((page_to_phys(page) >> SMMU_PDE_SHIFT) | (attr))
 228 #define SMMU_EX_PTBL_PAGE(pde)          \
 229                 pfn_to_page((unsigned long)(pde) & SMMU_PFN_MASK)
 230 #define SMMU_PFN_TO_PTE(pfn, attr)      (unsigned long)((pfn) | (attr))
 231
 232 #define SMMU_ASID_ENABLE(asid)  ((asid) | (1 << 31))
 233 #define SMMU_ASID_DISABLE       0
 234 #define SMMU_ASID_ASID(n)       ((n) & ~SMMU_ASID_ENABLE(0))
 235
 236 #define NUM_SMMU_REG_BANKS      3
 237
 238 #define smmu_client_enable_hwgrp(c, m)  smmu_client_set_hwgrp(c, m, 1)
 239 #define smmu_client_disable_hwgrp(c)    smmu_client_set_hwgrp(c, 0, 0)
 240 #define __smmu_client_enable_hwgrp(c, m) __smmu_client_set_hwgrp(c, m, 1)
 241 #define __smmu_client_disable_hwgrp(c)  __smmu_client_set_hwgrp(c, 0, 0)
 242
 243 #define HWGRP_INIT(client) [HWGRP_##client] = SMMU_##client##_ASID
 244
 245 static const u32 smmu_hwgrp_asid_reg[] = {
 246         HWGRP_INIT(AFI),
 247         HWGRP_INIT(AVPC),
 248         HWGRP_INIT(DC),
 249         HWGRP_INIT(DCB),
 250         HWGRP_INIT(EPP),
 251         HWGRP_INIT(G2),
 252         HWGRP_INIT(HC),
 253         HWGRP_INIT(HDA),
 254         HWGRP_INIT(ISP),
 255         HWGRP_INIT(MPE),
 256         HWGRP_INIT(NV),
 257         HWGRP_INIT(NV2),
 258         HWGRP_INIT(PPCS),
 259         HWGRP_INIT(SATA),
 260         HWGRP_INIT(VDE),
 261         HWGRP_INIT(VI),
 262 };
 263 #define HWGRP_ASID_REG(x) (smmu_hwgrp_asid_reg[x])
 264
 265 /*
 266  * Per client for address space
 267  */
 268 struct smmu_client {
 269         struct device           *dev;
 270         struct list_head        list;
 271         struct smmu_as          *as;
 272         u32                     hwgrp;
 273 };
 274
 275 /*
 276  * Per address space
 277  */
 278 struct smmu_as {
 279         struct smmu_device      *smmu;  /* back pointer to container */
 280         unsigned int            asid;
 281         spinlock_t              lock;   /* for pagetable */
 282         struct page             *pdir_page;
 283         unsigned long           pdir_attr;
 284         unsigned long           pde_attr;
 285         unsigned long           pte_attr;
 286         unsigned int            *pte_count;
 287
 288         struct list_head        client;
 289         spinlock_t              client_lock; /* for client list */
 290 };
 291
 292 struct smmu_debugfs_info {
 293         struct smmu_device *smmu;
 294         int mc;
 295         int cache;
 296 };
 297
 298 /*
 299  * Per SMMU device - IOMMU device
 300  */
 301 struct smmu_device {
 302         void __iomem    *regbase;       /* register offset base */
 303         void __iomem    **regs;         /* register block start address array */
 304         void __iomem    **rege;         /* register block end address array */
 305         int             nregs;          /* number of register blocks */
 306
 307         unsigned long   iovmm_base;     /* remappable base address */
 308         unsigned long   page_count;     /* total remappable size */
 309         spinlock_t      lock;
 310         char            *name;
 311         struct device   *dev;
 312         struct page *avp_vector_page;   /* dummy page shared by all AS's */
 313
 314         /*
 315          * Register image savers for suspend/resume
 316          */
 317         unsigned long translation_enable_0;
 318         unsigned long translation_enable_1;
 319         unsigned long translation_enable_2;
 320         unsigned long asid_security;
 321
 322         struct dentry *debugfs_root;
 323         struct smmu_debugfs_info *debugfs_info;
 324
 325         struct device_node *ahb;
 326
 327         int             num_as;
 328         struct smmu_as  as[0];          /* Run-time allocated array */
 329 };
 330
 331 static struct smmu_device *smmu_handle; /* unique for a system */
 332
 333 /*
 334  *      SMMU register accessors
 335  */
 336 static bool inline smmu_valid_reg(struct smmu_device *smmu,
 337                                   void __iomem *addr)
 338 {
 339         int i;
 340
 341         for (i = 0; i < smmu->nregs; i++) {
 342                 if (addr < smmu->regs[i])
 343                         break;
 344                 if (addr <= smmu->rege[i])
 345                         return true;
 346         }
 347
 348         return false;
 349 }
 350
 351 static inline u32 smmu_read(struct smmu_device *smmu, size_t offs)
 352 {
 353         void __iomem *addr = smmu->regbase + offs;
 354
 355         BUG_ON(!smmu_valid_reg(smmu, addr));
 356
 357         return readl(addr);
 358 }
 359
 360 static inline void smmu_write(struct smmu_device *smmu, u32 val, size_t offs)
 361 {
 362         void __iomem *addr = smmu->regbase + offs;
 363
 364         BUG_ON(!smmu_valid_reg(smmu, addr));
 365
 366         writel(val, addr);
 367 }
 368
 369 #define VA_PAGE_TO_PA(va, page) \
 370         (page_to_phys(page) + ((unsigned long)(va) & ~PAGE_MASK))
 371
 372 #define FLUSH_CPU_DCACHE(va, page, size)        \
 373         do {    \
 374                 unsigned long _pa_ = VA_PAGE_TO_PA(va, page);           \
 375                 __cpuc_flush_dcache_area((void *)(va), (size_t)(size)); \
 376                 outer_flush_range(_pa_, _pa_+(size_t)(size));           \
 377         } while (0)
 378
 379 /*
 380  * Any interaction between any block on PPSB and a block on APB or AHB
 381  * must have these read-back barriers to ensure the APB/AHB bus
 382  * transaction is complete before initiating activity on the PPSB
 383  * block.
 384  */
 385 #define FLUSH_SMMU_REGS(smmu)   smmu_read(smmu, SMMU_CONFIG)
 386
 387 #define smmu_client_hwgrp(c) (u32)((c)->dev->platform_data)
 388
 389 static int __smmu_client_set_hwgrp(struct smmu_client *c,
 390                                    unsigned long map, int on)
 391 {
 392         int i;
 393         struct smmu_as *as = c->as;
 394         u32 val, offs, mask = SMMU_ASID_ENABLE(as->asid);
 395         struct smmu_device *smmu = as->smmu;
 396
 397         WARN_ON(!on && map);
 398         if (on && !map)
 399                 return -EINVAL;
 400         if (!on)
 401                 map = smmu_client_hwgrp(c);
 402
 403         for_each_set_bit(i, &map, HWGRP_COUNT) {
 404                 offs = HWGRP_ASID_REG(i);
 405                 val = smmu_read(smmu, offs);
 406                 if (on) {
 407 #if !defined(SKIP_SWGRP_CHECK)
 408                         if (WARN_ON(val & mask))
 409                                 goto err_hw_busy;
 410 #endif
 411                         val |= mask;
 412                 } else {
 413 #if !defined(SKIP_SWGRP_CHECK)
 414                         WARN_ON((val & mask) == mask);
 415 #endif
 416                         val &= ~mask;
 417                 }
 418                 smmu_write(smmu, val, offs);
 419         }
 420         FLUSH_SMMU_REGS(smmu);
 421         c->hwgrp = map;
 422         return 0;
 423
 424 err_hw_busy:
 425         for_each_set_bit(i, &map, HWGRP_COUNT) {
 426                 offs = HWGRP_ASID_REG(i);
 427                 val = smmu_read(smmu, offs);
 428                 val &= ~mask;
 429                 smmu_write(smmu, val, offs);
 430         }
 431         return -EBUSY;
 432 }
 433
 434 static int smmu_client_set_hwgrp(struct smmu_client *c, u32 map, int on)
 435 {
 436         u32 val;
 437         unsigned long flags;
 438         struct smmu_as *as = c->as;
 439         struct smmu_device *smmu = as->smmu;
 440
 441         spin_lock_irqsave(&smmu->lock, flags);
 442         val = __smmu_client_set_hwgrp(c, map, on);
 443         spin_unlock_irqrestore(&smmu->lock, flags);
 444         return val;
 445 }
 446
 447 /*
 448  * Flush all TLB entries and all PTC entries
 449  * Caller must lock smmu
 450  */
 451 static void smmu_flush_regs(struct smmu_device *smmu, int enable)
 452 {
 453         u32 val;
 454
 455         smmu_write(smmu, SMMU_PTC_FLUSH_TYPE_ALL, SMMU_PTC_FLUSH);
 456         FLUSH_SMMU_REGS(smmu);
 457         val = SMMU_TLB_FLUSH_VA_MATCH_ALL |
 458                 SMMU_TLB_FLUSH_ASID_MATCH_disable;
 459         smmu_write(smmu, val, SMMU_TLB_FLUSH);
 460
 461         if (enable)
 462                 smmu_write(smmu, SMMU_CONFIG_ENABLE, SMMU_CONFIG);
 463         FLUSH_SMMU_REGS(smmu);
 464 }
 465
 466 static int smmu_setup_regs(struct smmu_device *smmu)
 467 {
 468         int i;
 469         u32 val;
 470
 471         for (i = 0; i < smmu->num_as; i++) {
 472                 struct smmu_as *as = &smmu->as[i];
 473                 struct smmu_client *c;
 474
 475                 smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID);
 476                 val = as->pdir_page ?
 477                         SMMU_MK_PDIR(as->pdir_page, as->pdir_attr) :
 478                         SMMU_PTB_DATA_RESET_VAL;
 479                 smmu_write(smmu, val, SMMU_PTB_DATA);
 480
 481                 list_for_each_entry(c, &as->client, list)
 482                         __smmu_client_set_hwgrp(c, c->hwgrp, 1);
 483         }
 484
 485         smmu_write(smmu, smmu->translation_enable_0, SMMU_TRANSLATION_ENABLE_0);
 486         smmu_write(smmu, smmu->translation_enable_1, SMMU_TRANSLATION_ENABLE_1);
 487         smmu_write(smmu, smmu->translation_enable_2, SMMU_TRANSLATION_ENABLE_2);
 488         smmu_write(smmu, smmu->asid_security, SMMU_ASID_SECURITY);
 489         smmu_write(smmu, SMMU_TLB_CONFIG_RESET_VAL, SMMU_CACHE_CONFIG(_TLB));
 490         smmu_write(smmu, SMMU_PTC_CONFIG_RESET_VAL, SMMU_CACHE_CONFIG(_PTC));
 491
 492         smmu_flush_regs(smmu, 1);
 493
 494         return tegra_ahb_enable_smmu(smmu->ahb);
 495 }
 496
 497 static void flush_ptc_and_tlb(struct smmu_device *smmu,
 498                       struct smmu_as *as, dma_addr_t iova,
 499                       unsigned long *pte, struct page *page, int is_pde)
 500 {
 501         u32 val;
 502         unsigned long tlb_flush_va = is_pde
 503                 ?  SMMU_TLB_FLUSH_VA(iova, SECTION)
 504                 :  SMMU_TLB_FLUSH_VA(iova, GROUP);
 505
 506         val = SMMU_PTC_FLUSH_TYPE_ADR | VA_PAGE_TO_PA(pte, page);
 507         smmu_write(smmu, val, SMMU_PTC_FLUSH);
 508         FLUSH_SMMU_REGS(smmu);
 509         val = tlb_flush_va |
 510                 SMMU_TLB_FLUSH_ASID_MATCH__ENABLE |
 511                 (as->asid << SMMU_TLB_FLUSH_ASID_SHIFT);
 512         smmu_write(smmu, val, SMMU_TLB_FLUSH);
 513         FLUSH_SMMU_REGS(smmu);
 514 }
 515
 516 static void free_ptbl(struct smmu_as *as, dma_addr_t iova)
 517 {
 518         unsigned long pdn = SMMU_ADDR_TO_PDN(iova);
 519         unsigned long *pdir = (unsigned long *)page_address(as->pdir_page);
 520
 521         if (pdir[pdn] != _PDE_VACANT(pdn)) {
 522                 dev_dbg(as->smmu->dev, "pdn: %lx\n", pdn);
 523
 524                 ClearPageReserved(SMMU_EX_PTBL_PAGE(pdir[pdn]));
 525                 __free_page(SMMU_EX_PTBL_PAGE(pdir[pdn]));
 526                 pdir[pdn] = _PDE_VACANT(pdn);
 527                 FLUSH_CPU_DCACHE(&pdir[pdn], as->pdir_page, sizeof pdir[pdn]);
 528                 flush_ptc_and_tlb(as->smmu, as, iova, &pdir[pdn],
 529                                   as->pdir_page, 1);
 530         }
 531 }
 532
 533 static void free_pdir(struct smmu_as *as)
 534 {
 535         unsigned addr;
 536         int count;
 537         struct device *dev = as->smmu->dev;
 538
 539         if (!as->pdir_page)
 540                 return;
 541
 542         addr = as->smmu->iovmm_base;
 543         count = as->smmu->page_count;
 544         while (count-- > 0) {
 545                 free_ptbl(as, addr);
 546                 addr += SMMU_PAGE_SIZE * SMMU_PTBL_COUNT;
 547         }
 548         ClearPageReserved(as->pdir_page);
 549         __free_page(as->pdir_page);
 550         as->pdir_page = NULL;
 551         devm_kfree(dev, as->pte_count);
 552         as->pte_count = NULL;
 553 }
 554
 555 /*
 556  * Maps PTBL for given iova and returns the PTE address
 557  * Caller must unmap the mapped PTBL returned in *ptbl_page_p
 558  */
 559 static unsigned long *locate_pte(struct smmu_as *as,
 560                                  dma_addr_t iova, bool allocate,
 561                                  struct page **ptbl_page_p,
 562                                  unsigned int **count)
 563 {
 564         unsigned long ptn = SMMU_ADDR_TO_PFN(iova);
 565         unsigned long pdn = SMMU_ADDR_TO_PDN(iova);
 566         unsigned long *pdir = page_address(as->pdir_page);
 567         unsigned long *ptbl;
 568
 569         if (pdir[pdn] != _PDE_VACANT(pdn)) {
 570                 /* Mapped entry table already exists */
 571                 *ptbl_page_p = SMMU_EX_PTBL_PAGE(pdir[pdn]);
 572                 ptbl = page_address(*ptbl_page_p);
 573         } else if (!allocate) {
 574                 return NULL;
 575         } else {
 576                 int pn;
 577                 unsigned long addr = SMMU_PDN_TO_ADDR(pdn);
 578
 579                 /* Vacant - allocate a new page table */
 580                 dev_dbg(as->smmu->dev, "New PTBL pdn: %lx\n", pdn);
 581
 582                 *ptbl_page_p = alloc_page(GFP_ATOMIC);
 583                 if (!*ptbl_page_p) {
 584                         dev_err(as->smmu->dev,
 585                                 "failed to allocate smmu_device page table\n");
 586                         return NULL;
 587                 }
 588                 SetPageReserved(*ptbl_page_p);
 589                 ptbl = (unsigned long *)page_address(*ptbl_page_p);
 590                 for (pn = 0; pn < SMMU_PTBL_COUNT;
 591                      pn++, addr += SMMU_PAGE_SIZE) {
 592                         ptbl[pn] = _PTE_VACANT(addr);
 593                 }
 594                 FLUSH_CPU_DCACHE(ptbl, *ptbl_page_p, SMMU_PTBL_SIZE);
 595                 pdir[pdn] = SMMU_MK_PDE(*ptbl_page_p,
 596                                         as->pde_attr | _PDE_NEXT);
 597                 FLUSH_CPU_DCACHE(&pdir[pdn], as->pdir_page, sizeof pdir[pdn]);
 598                 flush_ptc_and_tlb(as->smmu, as, iova, &pdir[pdn],
 599                                   as->pdir_page, 1);
 600         }
 601         *count = &as->pte_count[pdn];
 602
 603         return &ptbl[ptn % SMMU_PTBL_COUNT];
 604 }
 605
 606 #ifdef CONFIG_SMMU_SIG_DEBUG
 607 static void put_signature(struct smmu_as *as,
 608                           dma_addr_t iova, unsigned long pfn)
 609 {
 610         struct page *page;
 611         unsigned long *vaddr;
 612
 613         page = pfn_to_page(pfn);
 614         vaddr = page_address(page);
 615         if (!vaddr)
 616                 return;
 617
 618         vaddr[0] = iova;
 619         vaddr[1] = pfn << PAGE_SHIFT;
 620         FLUSH_CPU_DCACHE(vaddr, page, sizeof(vaddr[0]) * 2);
 621 }
 622 #else
 623 static inline void put_signature(struct smmu_as *as,
 624                                  unsigned long addr, unsigned long pfn)
 625 {
 626 }
 627 #endif
 628
 629 /*
 630  * Caller must not hold as->lock
 631  */
 632 static int alloc_pdir(struct smmu_as *as)
 633 {
 634         unsigned long *pdir, flags;
 635         int pdn, err = 0;
 636         u32 val;
 637         struct smmu_device *smmu = as->smmu;
 638         struct page *page;
 639         unsigned int *cnt;
 640
 641         /*
 642          * do the allocation, then grab as->lock
 643          */
 644         cnt = devm_kzalloc(smmu->dev,
 645                            sizeof(cnt[0]) * SMMU_PDIR_COUNT,
 646                            GFP_KERNEL);
 647         page = alloc_page(GFP_KERNEL | __GFP_DMA);
 648
 649         spin_lock_irqsave(&as->lock, flags);
 650
 651         if (as->pdir_page) {
 652                 /* We raced, free the redundant */
 653                 err = -EAGAIN;
 654                 goto err_out;
 655         }
 656
 657         if (!page || !cnt) {
 658                 dev_err(smmu->dev, "failed to allocate at %s\n", __func__);
 659                 err = -ENOMEM;
 660                 goto err_out;
 661         }
 662
 663         as->pdir_page = page;
 664         as->pte_count = cnt;
 665
 666         SetPageReserved(as->pdir_page);
 667         pdir = page_address(as->pdir_page);
 668
 669         for (pdn = 0; pdn < SMMU_PDIR_COUNT; pdn++)
 670                 pdir[pdn] = _PDE_VACANT(pdn);
 671         FLUSH_CPU_DCACHE(pdir, as->pdir_page, SMMU_PDIR_SIZE);
 672         val = SMMU_PTC_FLUSH_TYPE_ADR | VA_PAGE_TO_PA(pdir, as->pdir_page);
 673         smmu_write(smmu, val, SMMU_PTC_FLUSH);
 674         FLUSH_SMMU_REGS(as->smmu);
 675         val = SMMU_TLB_FLUSH_VA_MATCH_ALL |
 676                 SMMU_TLB_FLUSH_ASID_MATCH__ENABLE |
 677                 (as->asid << SMMU_TLB_FLUSH_ASID_SHIFT);
 678         smmu_write(smmu, val, SMMU_TLB_FLUSH);
 679         FLUSH_SMMU_REGS(as->smmu);
 680
 681         spin_unlock_irqrestore(&as->lock, flags);
 682
 683         return 0;
 684
 685 err_out:
 686         spin_unlock_irqrestore(&as->lock, flags);
 687
 688         devm_kfree(smmu->dev, cnt);
 689         if (page)
 690                 __free_page(page);
 691         return err;
 692 }
 693
 694 static void __smmu_iommu_unmap(struct smmu_as *as, dma_addr_t iova)
 695 {
 696         unsigned long *pte;
 697         struct page *page;
 698         unsigned int *count;
 699
 700         pte = locate_pte(as, iova, false, &page, &count);
 701         if (WARN_ON(!pte))
 702                 return;
 703
 704         if (WARN_ON(*pte == _PTE_VACANT(iova)))
 705                 return;
 706
 707         *pte = _PTE_VACANT(iova);
 708         FLUSH_CPU_DCACHE(pte, page, sizeof(*pte));
 709         flush_ptc_and_tlb(as->smmu, as, iova, pte, page, 0);
 710         if (!--(*count))
 711                 free_ptbl(as, iova);
 712 }
 713
 714 static void __smmu_iommu_map_pfn(struct smmu_as *as, dma_addr_t iova,
 715                                  unsigned long pfn)
 716 {
 717         struct smmu_device *smmu = as->smmu;
 718         unsigned long *pte;
 719         unsigned int *count;
 720         struct page *page;
 721
 722         pte = locate_pte(as, iova, true, &page, &count);
 723         if (WARN_ON(!pte))
 724                 return;
 725
 726         if (*pte == _PTE_VACANT(iova))
 727                 (*count)++;
 728         *pte = SMMU_PFN_TO_PTE(pfn, as->pte_attr);
 729         if (unlikely((*pte == _PTE_VACANT(iova))))
 730                 (*count)--;
 731         FLUSH_CPU_DCACHE(pte, page, sizeof(*pte));
 732         flush_ptc_and_tlb(smmu, as, iova, pte, page, 0);
 733         put_signature(as, iova, pfn);
 734 }
 735
 736 static int smmu_iommu_map(struct iommu_domain *domain, unsigned long iova,
 737                           phys_addr_t pa, size_t bytes, int prot)
 738 {
 739         struct smmu_as *as = domain->priv;
 740         unsigned long pfn = __phys_to_pfn(pa);
 741         unsigned long flags;
 742
 743         dev_dbg(as->smmu->dev, "[%d] %08lx:%08x\n", as->asid, iova, pa);
 744
 745         if (!pfn_valid(pfn))
 746                 return -ENOMEM;
 747
 748         spin_lock_irqsave(&as->lock, flags);
 749         __smmu_iommu_map_pfn(as, iova, pfn);
 750         spin_unlock_irqrestore(&as->lock, flags);
 751         return 0;
 752 }
 753
 754 static size_t smmu_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
 755                                size_t bytes)
 756 {
 757         struct smmu_as *as = domain->priv;
 758         unsigned long flags;
 759
 760         dev_dbg(as->smmu->dev, "[%d] %08lx\n", as->asid, iova);
 761
 762         spin_lock_irqsave(&as->lock, flags);
 763         __smmu_iommu_unmap(as, iova);
 764         spin_unlock_irqrestore(&as->lock, flags);
 765         return SMMU_PAGE_SIZE;
 766 }
 767
 768 static phys_addr_t smmu_iommu_iova_to_phys(struct iommu_domain *domain,
 769                                            dma_addr_t iova)
 770 {
 771         struct smmu_as *as = domain->priv;
 772         unsigned long *pte;
 773         unsigned int *count;
 774         struct page *page;
 775         unsigned long pfn;
 776         unsigned long flags;
 777
 778         spin_lock_irqsave(&as->lock, flags);
 779
 780         pte = locate_pte(as, iova, true, &page, &count);
 781         pfn = *pte & SMMU_PFN_MASK;
 782         WARN_ON(!pfn_valid(pfn));
 783         dev_dbg(as->smmu->dev,
 784                 "iova:%08llx pfn:%08lx asid:%d\n", (unsigned long long)iova,
 785                  pfn, as->asid);
 786
 787         spin_unlock_irqrestore(&as->lock, flags);
 788         return PFN_PHYS(pfn);
 789 }
 790
 791 static int smmu_iommu_domain_has_cap(struct iommu_domain *domain,
 792                                      unsigned long cap)
 793 {
 794         return 0;
 795 }
 796
 797 static int smmu_iommu_attach_dev(struct iommu_domain *domain,
 798                                  struct device *dev)
 799 {
 800         struct smmu_as *as = domain->priv;
 801         struct smmu_device *smmu = as->smmu;
 802         struct smmu_client *client, *c;
 803         u32 map;
 804         int err;
 805
 806         client = devm_kzalloc(smmu->dev, sizeof(*c), GFP_KERNEL);
 807         if (!client)
 808                 return -ENOMEM;
 809         client->dev = dev;
 810         client->as = as;
 811
 812 #ifdef SKIP_SWGRP_CHECK
 813         /* Enable all SWGRP blindly by default */
 814         map = (1 << HWGRP_COUNT) - 1;
 815 #else
 816         map = (unsigned long)dev->platform_data;
 817         if (!map)
 818                 return -EINVAL;
 819 #endif
 820
 821         err = smmu_client_enable_hwgrp(client, map);
 822         if (err)
 823                 goto err_hwgrp;
 824
 825         spin_lock(&as->client_lock);
 826         list_for_each_entry(c, &as->client, list) {
 827                 if (c->dev == dev) {
 828                         dev_err(smmu->dev,
 829                                 "%s is already attached\n", dev_name(c->dev));
 830                         err = -EINVAL;
 831                         goto err_client;
 832                 }
 833         }
 834         list_add(&client->list, &as->client);
 835         spin_unlock(&as->client_lock);
 836
 837         /*
 838          * Reserve "page zero" for AVP vectors using a common dummy
 839          * page.
 840          */
 841         if (map & HWG_AVPC) {
 842                 struct page *page;
 843
 844                 page = as->smmu->avp_vector_page;
 845                 __smmu_iommu_map_pfn(as, 0, page_to_pfn(page));
 846
 847                 pr_info("Reserve \"page zero\" for AVP vectors using a common dummy\n");
 848         }
 849
 850         dev_dbg(smmu->dev, "%s is attached\n", dev_name(dev));
 851         return 0;
 852
 853 err_client:
 854         smmu_client_disable_hwgrp(client);
 855         spin_unlock(&as->client_lock);
 856 err_hwgrp:
 857         devm_kfree(smmu->dev, client);
 858         return err;
 859 }
 860
 861 static void smmu_iommu_detach_dev(struct iommu_domain *domain,
 862                                   struct device *dev)
 863 {
 864         struct smmu_as *as = domain->priv;
 865         struct smmu_device *smmu = as->smmu;
 866         struct smmu_client *c;
 867
 868         spin_lock(&as->client_lock);
 869
 870         list_for_each_entry(c, &as->client, list) {
 871                 if (c->dev == dev) {
 872                         smmu_client_disable_hwgrp(c);
 873                         list_del(&c->list);
 874                         devm_kfree(smmu->dev, c);
 875                         c->as = NULL;
 876                         dev_dbg(smmu->dev,
 877                                 "%s is detached\n", dev_name(c->dev));
 878                         goto out;
 879                 }
 880         }
 881         dev_err(smmu->dev, "Couldn't find %s\n", dev_name(dev));
 882 out:
 883         spin_unlock(&as->client_lock);
 884 }
 885
 886 static int smmu_iommu_domain_init(struct iommu_domain *domain)
 887 {
 888         int i, err = -EAGAIN;
 889         unsigned long flags;
 890         struct smmu_as *as;
 891         struct smmu_device *smmu = smmu_handle;
 892
 893         /* Look for a free AS with lock held */
 894         for  (i = 0; i < smmu->num_as; i++) {
 895                 as = &smmu->as[i];
 896
 897                 if (as->pdir_page)
 898                         continue;
 899
 900                 err = alloc_pdir(as);
 901                 if (!err)
 902                         goto found;
 903
 904                 if (err != -EAGAIN)
 905                         break;
 906         }
 907         if (i == smmu->num_as)
 908                 dev_err(smmu->dev,  "no free AS\n");
 909         return err;
 910
 911 found:
 912         spin_lock_irqsave(&smmu->lock, flags);
 913
 914         /* Update PDIR register */
 915         smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID);
 916         smmu_write(smmu,
 917                    SMMU_MK_PDIR(as->pdir_page, as->pdir_attr), SMMU_PTB_DATA);
 918         FLUSH_SMMU_REGS(smmu);
 919
 920         spin_unlock_irqrestore(&smmu->lock, flags);
 921
 922         domain->priv = as;
 923
 924         domain->geometry.aperture_start = smmu->iovmm_base;
 925         domain->geometry.aperture_end   = smmu->iovmm_base +
 926                 smmu->page_count * SMMU_PAGE_SIZE - 1;
 927         domain->geometry.force_aperture = true;
 928
 929         dev_dbg(smmu->dev, "smmu_as@%p\n", as);
 930
 931         return 0;
 932 }
 933
 934 static void smmu_iommu_domain_destroy(struct iommu_domain *domain)
 935 {
 936         struct smmu_as *as = domain->priv;
 937         struct smmu_device *smmu = as->smmu;
 938         unsigned long flags;
 939
 940         spin_lock_irqsave(&as->lock, flags);
 941
 942         if (as->pdir_page) {
 943                 spin_lock(&smmu->lock);
 944                 smmu_write(smmu, SMMU_PTB_ASID_CUR(as->asid), SMMU_PTB_ASID);
 945                 smmu_write(smmu, SMMU_PTB_DATA_RESET_VAL, SMMU_PTB_DATA);
 946                 FLUSH_SMMU_REGS(smmu);
 947                 spin_unlock(&smmu->lock);
 948
 949                 free_pdir(as);
 950         }
 951
 952         if (!list_empty(&as->client)) {
 953                 struct smmu_client *c;
 954
 955                 list_for_each_entry(c, &as->client, list)
 956                         smmu_iommu_detach_dev(domain, c->dev);
 957         }
 958
 959         spin_unlock_irqrestore(&as->lock, flags);
 960
 961         domain->priv = NULL;
 962         dev_dbg(smmu->dev, "smmu_as@%p\n", as);
 963 }
 964
 965 static struct iommu_ops smmu_iommu_ops = {
 966         .domain_init    = smmu_iommu_domain_init,
 967         .domain_destroy = smmu_iommu_domain_destroy,
 968         .attach_dev     = smmu_iommu_attach_dev,
 969         .detach_dev     = smmu_iommu_detach_dev,
 970         .map            = smmu_iommu_map,
 971         .unmap          = smmu_iommu_unmap,
 972         .iova_to_phys   = smmu_iommu_iova_to_phys,
 973         .domain_has_cap = smmu_iommu_domain_has_cap,
 974         .pgsize_bitmap  = SMMU_IOMMU_PGSIZES,
 975 };
 976
 977 /* Should be in the order of enum */
 978 static const char * const smmu_debugfs_mc[] = { "mc", };
 979 static const char * const smmu_debugfs_cache[] = {  "tlb", "ptc", };
 980
 981 static ssize_t smmu_debugfs_stats_write(struct file *file,
 982                                         const char __user *buffer,
 983                                         size_t count, loff_t *pos)
 984 {
 985         struct smmu_debugfs_info *info;
 986         struct smmu_device *smmu;
 987         int i;
 988         enum {
 989                 _OFF = 0,
 990                 _ON,
 991                 _RESET,
 992         };
 993         const char * const command[] = {
 994                 [_OFF]          = "off",
 995                 [_ON]           = "on",
 996                 [_RESET]        = "reset",
 997         };
 998         char str[] = "reset";
 999         u32 val;
1000         size_t offs;
1001
1002         count = min_t(size_t, count, sizeof(str));
1003         if (copy_from_user(str, buffer, count))
1004                 return -EINVAL;
1005
1006         for (i = 0; i < ARRAY_SIZE(command); i++)
1007                 if (strncmp(str, command[i],
1008                             strlen(command[i])) == 0)
1009                         break;
1010
1011         if (i == ARRAY_SIZE(command))
1012                 return -EINVAL;
1013
1014         info = file_inode(file)->i_private;
1015         smmu = info->smmu;
1016
1017         offs = SMMU_CACHE_CONFIG(info->cache);
1018         val = smmu_read(smmu, offs);
1019         switch (i) {
1020         case _OFF:
1021                 val &= ~SMMU_CACHE_CONFIG_STATS_ENABLE;
1022                 val &= ~SMMU_CACHE_CONFIG_STATS_TEST;
1023                 smmu_write(smmu, val, offs);
1024                 break;
1025         case _ON:
1026                 val |= SMMU_CACHE_CONFIG_STATS_ENABLE;
1027                 val &= ~SMMU_CACHE_CONFIG_STATS_TEST;
1028                 smmu_write(smmu, val, offs);
1029                 break;
1030         case _RESET:
1031                 val |= SMMU_CACHE_CONFIG_STATS_TEST;
1032                 smmu_write(smmu, val, offs);
1033                 val &= ~SMMU_CACHE_CONFIG_STATS_TEST;
1034                 smmu_write(smmu, val, offs);
1035                 break;
1036         default:
1037                 BUG();
1038                 break;
1039         }
1040
1041         dev_dbg(smmu->dev, "%s() %08x, %08x @%08x\n", __func__,
1042                 val, smmu_read(smmu, offs), offs);
1043
1044         return count;
1045 }
1046
1047 static int smmu_debugfs_stats_show(struct seq_file *s, void *v)
1048 {
1049         struct smmu_debugfs_info *info = s->private;
1050         struct smmu_device *smmu = info->smmu;
1051         int i;
1052         const char * const stats[] = { "hit", "miss", };
1053
1054
1055         for (i = 0; i < ARRAY_SIZE(stats); i++) {
1056                 u32 val;
1057                 size_t offs;
1058
1059                 offs = SMMU_STATS_CACHE_COUNT(info->mc, info->cache, i);
1060                 val = smmu_read(smmu, offs);
1061                 seq_printf(s, "%s:%08x ", stats[i], val);
1062
1063                 dev_dbg(smmu->dev, "%s() %s %08x @%08x\n", __func__,
1064                         stats[i], val, offs);
1065         }
1066         seq_printf(s, "\n");
1067         return 0;
1068 }
1069
1070 static int smmu_debugfs_stats_open(struct inode *inode, struct file *file)
1071 {
1072         return single_open(file, smmu_debugfs_stats_show, inode->i_private);
1073 }
1074
1075 static const struct file_operations smmu_debugfs_stats_fops = {
1076         .open           = smmu_debugfs_stats_open,
1077         .read           = seq_read,
1078         .llseek         = seq_lseek,
1079         .release        = single_release,
1080         .write          = smmu_debugfs_stats_write,
1081 };
1082
1083 static void smmu_debugfs_delete(struct smmu_device *smmu)
1084 {
1085         debugfs_remove_recursive(smmu->debugfs_root);
1086         kfree(smmu->debugfs_info);
1087 }
1088
1089 static void smmu_debugfs_create(struct smmu_device *smmu)
1090 {
1091         int i;
1092         size_t bytes;
1093         struct dentry *root;
1094
1095         bytes = ARRAY_SIZE(smmu_debugfs_mc) * ARRAY_SIZE(smmu_debugfs_cache) *
1096                 sizeof(*smmu->debugfs_info);
1097         smmu->debugfs_info = kmalloc(bytes, GFP_KERNEL);
1098         if (!smmu->debugfs_info)
1099                 return;
1100
1101         root = debugfs_create_dir(dev_name(smmu->dev), NULL);
1102         if (!root)
1103                 goto err_out;
1104         smmu->debugfs_root = root;
1105
1106         for (i = 0; i < ARRAY_SIZE(smmu_debugfs_mc); i++) {
1107                 int j;
1108                 struct dentry *mc;
1109
1110                 mc = debugfs_create_dir(smmu_debugfs_mc[i], root);
1111                 if (!mc)
1112                         goto err_out;
1113
1114                 for (j = 0; j < ARRAY_SIZE(smmu_debugfs_cache); j++) {
1115                         struct dentry *cache;
1116                         struct smmu_debugfs_info *info;
1117
1118                         info = smmu->debugfs_info;
1119                         info += i * ARRAY_SIZE(smmu_debugfs_mc) + j;
1120                         info->smmu = smmu;
1121                         info->mc = i;
1122                         info->cache = j;
1123
1124                         cache = debugfs_create_file(smmu_debugfs_cache[j],
1125                                                     S_IWUGO | S_IRUGO, mc,
1126                                                     (void *)info,
1127                                                     &smmu_debugfs_stats_fops);
1128                         if (!cache)
1129                                 goto err_out;
1130                 }
1131         }
1132
1133         return;
1134
1135 err_out:
1136         smmu_debugfs_delete(smmu);
1137 }
1138
1139 static int tegra_smmu_suspend(struct device *dev)
1140 {
1141         struct smmu_device *smmu = dev_get_drvdata(dev);
1142
1143         smmu->translation_enable_0 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_0);
1144         smmu->translation_enable_1 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_1);
1145         smmu->translation_enable_2 = smmu_read(smmu, SMMU_TRANSLATION_ENABLE_2);
1146         smmu->asid_security = smmu_read(smmu, SMMU_ASID_SECURITY);
1147         return 0;
1148 }
1149
1150 static int tegra_smmu_resume(struct device *dev)
1151 {
1152         struct smmu_device *smmu = dev_get_drvdata(dev);
1153         unsigned long flags;
1154         int err;
1155
1156         spin_lock_irqsave(&smmu->lock, flags);
1157         err = smmu_setup_regs(smmu);
1158         spin_unlock_irqrestore(&smmu->lock, flags);
1159         return err;
1160 }
1161
1162 static int tegra_smmu_probe(struct platform_device *pdev)
1163 {
1164         struct smmu_device *smmu;
1165         struct device *dev = &pdev->dev;
1166         int i, asids, err = 0;
1167         dma_addr_t uninitialized_var(base);
1168         size_t bytes, uninitialized_var(size);
1169
1170         if (smmu_handle)
1171                 return -EIO;
1172
1173         BUILD_BUG_ON(PAGE_SHIFT != SMMU_PAGE_SHIFT);
1174
1175         if (of_property_read_u32(dev->of_node, "nvidia,#asids", &asids))
1176                 return -ENODEV;
1177
1178         bytes = sizeof(*smmu) + asids * sizeof(*smmu->as);
1179         smmu = devm_kzalloc(dev, bytes, GFP_KERNEL);
1180         if (!smmu) {
1181                 dev_err(dev, "failed to allocate smmu_device\n");
1182                 return -ENOMEM;
1183         }
1184
1185         smmu->nregs = pdev->num_resources;
1186         smmu->regs = devm_kzalloc(dev, 2 * smmu->nregs * sizeof(*smmu->regs),
1187                                   GFP_KERNEL);
1188         smmu->rege = smmu->regs + smmu->nregs;
1189         if (!smmu->regs)
1190                 return -ENOMEM;
1191         for (i = 0; i < smmu->nregs; i++) {
1192                 struct resource *res;
1193
1194                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
1195                 if (!res)
1196                         return -ENODEV;
1197                 smmu->regs[i] = devm_ioremap_resource(&pdev->dev, res);
1198                 if (IS_ERR(smmu->regs[i]))
1199                         return PTR_ERR(smmu->regs[i]);
1200                 smmu->rege[i] = smmu->regs[i] + resource_size(res) - 1;
1201         }
1202         /* Same as "mc" 1st regiter block start address */
1203         smmu->regbase = (void __iomem *)((u32)smmu->regs[0] & PAGE_MASK);
1204
1205         err = of_get_dma_window(dev->of_node, NULL, 0, NULL, &base, &size);
1206         if (err)
1207                 return -ENODEV;
1208
1209         if (size & SMMU_PAGE_MASK)
1210                 return -EINVAL;
1211
1212         size >>= SMMU_PAGE_SHIFT;
1213         if (!size)
1214                 return -EINVAL;
1215
1216         smmu->ahb = of_parse_phandle(dev->of_node, "nvidia,ahb", 0);
1217         if (!smmu->ahb)
1218                 return -ENODEV;
1219
1220         smmu->dev = dev;
1221         smmu->num_as = asids;
1222         smmu->iovmm_base = base;
1223         smmu->page_count = size;
1224
1225         smmu->translation_enable_0 = ~0;
1226         smmu->translation_enable_1 = ~0;
1227         smmu->translation_enable_2 = ~0;
1228         smmu->asid_security = 0;
1229
1230         for (i = 0; i < smmu->num_as; i++) {
1231                 struct smmu_as *as = &smmu->as[i];
1232
1233                 as->smmu = smmu;
1234                 as->asid = i;
1235                 as->pdir_attr = _PDIR_ATTR;
1236                 as->pde_attr = _PDE_ATTR;
1237                 as->pte_attr = _PTE_ATTR;
1238
1239                 spin_lock_init(&as->lock);
1240                 spin_lock_init(&as->client_lock);
1241                 INIT_LIST_HEAD(&as->client);
1242         }
1243         spin_lock_init(&smmu->lock);
1244         err = smmu_setup_regs(smmu);
1245         if (err)
1246                 return err;
1247         platform_set_drvdata(pdev, smmu);
1248
1249         smmu->avp_vector_page = alloc_page(GFP_KERNEL);
1250         if (!smmu->avp_vector_page)
1251                 return -ENOMEM;
1252
1253         smmu_debugfs_create(smmu);
1254         smmu_handle = smmu;
1255         bus_set_iommu(&platform_bus_type, &smmu_iommu_ops);
1256         return 0;
1257 }
1258
1259 static int tegra_smmu_remove(struct platform_device *pdev)
1260 {
1261         struct smmu_device *smmu = platform_get_drvdata(pdev);
1262         int i;
1263
1264         smmu_debugfs_delete(smmu);
1265
1266         smmu_write(smmu, SMMU_CONFIG_DISABLE, SMMU_CONFIG);
1267         for (i = 0; i < smmu->num_as; i++)
1268                 free_pdir(&smmu->as[i]);
1269         __free_page(smmu->avp_vector_page);
1270         smmu_handle = NULL;
1271         return 0;
1272 }
1273
1274 const struct dev_pm_ops tegra_smmu_pm_ops = {
1275         .suspend        = tegra_smmu_suspend,
1276         .resume         = tegra_smmu_resume,
1277 };
1278
1279 static struct of_device_id tegra_smmu_of_match[] = {
1280         { .compatible = "nvidia,tegra30-smmu", },
1281         { },
1282 };
1283 MODULE_DEVICE_TABLE(of, tegra_smmu_of_match);
1284
1285 static struct platform_driver tegra_smmu_driver = {
1286         .probe          = tegra_smmu_probe,
1287         .remove         = tegra_smmu_remove,
1288         .driver = {
1289                 .owner  = THIS_MODULE,
1290                 .name   = "tegra-smmu",
1291                 .pm     = &tegra_smmu_pm_ops,
1292                 .of_match_table = tegra_smmu_of_match,
1293         },
1294 };
1295
1296 static int tegra_smmu_init(void)
1297 {
1298         return platform_driver_register(&tegra_smmu_driver);
1299 }
1300
1301 static void __exit tegra_smmu_exit(void)
1302 {
1303         platform_driver_unregister(&tegra_smmu_driver);
1304 }
1305
1306 core_initcall(tegra_smmu_init);
1307 module_exit(tegra_smmu_exit);
1308
1309 MODULE_DESCRIPTION("IOMMU API for SMMU in Tegra30");
1310 MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
1311 MODULE_ALIAS("platform:tegra-smmu");
1312 MODULE_LICENSE("GPL v2");