Merge branches 'cxgb3', 'endian', 'ipath', 'ipoib', 'iser', 'mad', 'misc', 'mlx4...
[linux-3.10.git] / drivers / infiniband / hw / nes / nes_hw.h
1 /*
2 * Copyright (c) 2006 - 2009 Intel-NE, Inc.  All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses.  You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 *     Redistribution and use in source and binary forms, with or
11 *     without modification, are permitted provided that the following
12 *     conditions are met:
13 *
14 *      - Redistributions of source code must retain the above
15 *        copyright notice, this list of conditions and the following
16 *        disclaimer.
17 *
18 *      - Redistributions in binary form must reproduce the above
19 *        copyright notice, this list of conditions and the following
20 *        disclaimer in the documentation and/or other materials
21 *        provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef __NES_HW_H
34 #define __NES_HW_H
35
36 #include <linux/inet_lro.h>
37
38 #define NES_PHY_TYPE_1G        2
39 #define NES_PHY_TYPE_IRIS      3
40 #define NES_PHY_TYPE_ARGUS     4
41 #define NES_PHY_TYPE_PUMA_1G   5
42 #define NES_PHY_TYPE_PUMA_10G  6
43 #define NES_PHY_TYPE_GLADIUS   7
44
45 #define NES_MULTICAST_PF_MAX 8
46
47 enum pci_regs {
48         NES_INT_STAT = 0x0000,
49         NES_INT_MASK = 0x0004,
50         NES_INT_PENDING = 0x0008,
51         NES_INTF_INT_STAT = 0x000C,
52         NES_INTF_INT_MASK = 0x0010,
53         NES_TIMER_STAT = 0x0014,
54         NES_PERIODIC_CONTROL = 0x0018,
55         NES_ONE_SHOT_CONTROL = 0x001C,
56         NES_EEPROM_COMMAND = 0x0020,
57         NES_EEPROM_DATA = 0x0024,
58         NES_FLASH_COMMAND = 0x0028,
59         NES_FLASH_DATA  = 0x002C,
60         NES_SOFTWARE_RESET = 0x0030,
61         NES_CQ_ACK = 0x0034,
62         NES_WQE_ALLOC = 0x0040,
63         NES_CQE_ALLOC = 0x0044,
64         NES_AEQ_ALLOC = 0x0048
65 };
66
67 enum indexed_regs {
68         NES_IDX_CREATE_CQP_LOW = 0x0000,
69         NES_IDX_CREATE_CQP_HIGH = 0x0004,
70         NES_IDX_QP_CONTROL = 0x0040,
71         NES_IDX_FLM_CONTROL = 0x0080,
72         NES_IDX_INT_CPU_STATUS = 0x00a0,
73         NES_IDX_GPIO_CONTROL = 0x00f0,
74         NES_IDX_GPIO_DATA = 0x00f4,
75         NES_IDX_TCP_CONFIG0 = 0x01e4,
76         NES_IDX_TCP_TIMER_CONFIG = 0x01ec,
77         NES_IDX_TCP_NOW = 0x01f0,
78         NES_IDX_QP_MAX_CFG_SIZES = 0x0200,
79         NES_IDX_QP_CTX_SIZE = 0x0218,
80         NES_IDX_TCP_TIMER_SIZE0 = 0x0238,
81         NES_IDX_TCP_TIMER_SIZE1 = 0x0240,
82         NES_IDX_ARP_CACHE_SIZE = 0x0258,
83         NES_IDX_CQ_CTX_SIZE = 0x0260,
84         NES_IDX_MRT_SIZE = 0x0278,
85         NES_IDX_PBL_REGION_SIZE = 0x0280,
86         NES_IDX_IRRQ_COUNT = 0x02b0,
87         NES_IDX_RX_WINDOW_BUFFER_PAGE_TABLE_SIZE = 0x02f0,
88         NES_IDX_RX_WINDOW_BUFFER_SIZE = 0x0300,
89         NES_IDX_DST_IP_ADDR = 0x0400,
90         NES_IDX_PCIX_DIAG = 0x08e8,
91         NES_IDX_MPP_DEBUG = 0x0a00,
92         NES_IDX_PORT_RX_DISCARDS = 0x0a30,
93         NES_IDX_PORT_TX_DISCARDS = 0x0a34,
94         NES_IDX_MPP_LB_DEBUG = 0x0b00,
95         NES_IDX_DENALI_CTL_22 = 0x1058,
96         NES_IDX_MAC_TX_CONTROL = 0x2000,
97         NES_IDX_MAC_TX_CONFIG = 0x2004,
98         NES_IDX_MAC_TX_PAUSE_QUANTA = 0x2008,
99         NES_IDX_MAC_RX_CONTROL = 0x200c,
100         NES_IDX_MAC_RX_CONFIG = 0x2010,
101         NES_IDX_MAC_EXACT_MATCH_BOTTOM = 0x201c,
102         NES_IDX_MAC_MDIO_CONTROL = 0x2084,
103         NES_IDX_MAC_TX_OCTETS_LOW = 0x2100,
104         NES_IDX_MAC_TX_OCTETS_HIGH = 0x2104,
105         NES_IDX_MAC_TX_FRAMES_LOW = 0x2108,
106         NES_IDX_MAC_TX_FRAMES_HIGH = 0x210c,
107         NES_IDX_MAC_TX_PAUSE_FRAMES = 0x2118,
108         NES_IDX_MAC_TX_ERRORS = 0x2138,
109         NES_IDX_MAC_RX_OCTETS_LOW = 0x213c,
110         NES_IDX_MAC_RX_OCTETS_HIGH = 0x2140,
111         NES_IDX_MAC_RX_FRAMES_LOW = 0x2144,
112         NES_IDX_MAC_RX_FRAMES_HIGH = 0x2148,
113         NES_IDX_MAC_RX_BC_FRAMES_LOW = 0x214c,
114         NES_IDX_MAC_RX_MC_FRAMES_HIGH = 0x2150,
115         NES_IDX_MAC_RX_PAUSE_FRAMES = 0x2154,
116         NES_IDX_MAC_RX_SHORT_FRAMES = 0x2174,
117         NES_IDX_MAC_RX_OVERSIZED_FRAMES = 0x2178,
118         NES_IDX_MAC_RX_JABBER_FRAMES = 0x217c,
119         NES_IDX_MAC_RX_CRC_ERR_FRAMES = 0x2180,
120         NES_IDX_MAC_RX_LENGTH_ERR_FRAMES = 0x2184,
121         NES_IDX_MAC_RX_SYMBOL_ERR_FRAMES = 0x2188,
122         NES_IDX_MAC_INT_STATUS = 0x21f0,
123         NES_IDX_MAC_INT_MASK = 0x21f4,
124         NES_IDX_PHY_PCS_CONTROL_STATUS0 = 0x2800,
125         NES_IDX_PHY_PCS_CONTROL_STATUS1 = 0x2a00,
126         NES_IDX_ETH_SERDES_COMMON_CONTROL0 = 0x2808,
127         NES_IDX_ETH_SERDES_COMMON_CONTROL1 = 0x2a08,
128         NES_IDX_ETH_SERDES_COMMON_STATUS0 = 0x280c,
129         NES_IDX_ETH_SERDES_COMMON_STATUS1 = 0x2a0c,
130         NES_IDX_ETH_SERDES_TX_EMP0 = 0x2810,
131         NES_IDX_ETH_SERDES_TX_EMP1 = 0x2a10,
132         NES_IDX_ETH_SERDES_TX_DRIVE0 = 0x2814,
133         NES_IDX_ETH_SERDES_TX_DRIVE1 = 0x2a14,
134         NES_IDX_ETH_SERDES_RX_MODE0 = 0x2818,
135         NES_IDX_ETH_SERDES_RX_MODE1 = 0x2a18,
136         NES_IDX_ETH_SERDES_RX_SIGDET0 = 0x281c,
137         NES_IDX_ETH_SERDES_RX_SIGDET1 = 0x2a1c,
138         NES_IDX_ETH_SERDES_BYPASS0 = 0x2820,
139         NES_IDX_ETH_SERDES_BYPASS1 = 0x2a20,
140         NES_IDX_ETH_SERDES_LOOPBACK_CONTROL0 = 0x2824,
141         NES_IDX_ETH_SERDES_LOOPBACK_CONTROL1 = 0x2a24,
142         NES_IDX_ETH_SERDES_RX_EQ_CONTROL0 = 0x2828,
143         NES_IDX_ETH_SERDES_RX_EQ_CONTROL1 = 0x2a28,
144         NES_IDX_ETH_SERDES_RX_EQ_STATUS0 = 0x282c,
145         NES_IDX_ETH_SERDES_RX_EQ_STATUS1 = 0x2a2c,
146         NES_IDX_ETH_SERDES_CDR_RESET0 = 0x2830,
147         NES_IDX_ETH_SERDES_CDR_RESET1 = 0x2a30,
148         NES_IDX_ETH_SERDES_CDR_CONTROL0 = 0x2834,
149         NES_IDX_ETH_SERDES_CDR_CONTROL1 = 0x2a34,
150         NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE0 = 0x2838,
151         NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE1 = 0x2a38,
152         NES_IDX_ENDNODE0_NSTAT_RX_DISCARD = 0x3080,
153         NES_IDX_ENDNODE0_NSTAT_RX_OCTETS_LO = 0x3000,
154         NES_IDX_ENDNODE0_NSTAT_RX_OCTETS_HI = 0x3004,
155         NES_IDX_ENDNODE0_NSTAT_RX_FRAMES_LO = 0x3008,
156         NES_IDX_ENDNODE0_NSTAT_RX_FRAMES_HI = 0x300c,
157         NES_IDX_ENDNODE0_NSTAT_TX_OCTETS_LO = 0x7000,
158         NES_IDX_ENDNODE0_NSTAT_TX_OCTETS_HI = 0x7004,
159         NES_IDX_ENDNODE0_NSTAT_TX_FRAMES_LO = 0x7008,
160         NES_IDX_ENDNODE0_NSTAT_TX_FRAMES_HI = 0x700c,
161         NES_IDX_WQM_CONFIG1 = 0x5004,
162         NES_IDX_CM_CONFIG = 0x5100,
163         NES_IDX_NIC_LOGPORT_TO_PHYPORT = 0x6000,
164         NES_IDX_NIC_PHYPORT_TO_USW = 0x6008,
165         NES_IDX_NIC_ACTIVE = 0x6010,
166         NES_IDX_NIC_UNICAST_ALL = 0x6018,
167         NES_IDX_NIC_MULTICAST_ALL = 0x6020,
168         NES_IDX_NIC_MULTICAST_ENABLE = 0x6028,
169         NES_IDX_NIC_BROADCAST_ON = 0x6030,
170         NES_IDX_USED_CHUNKS_TX = 0x60b0,
171         NES_IDX_TX_POOL_SIZE = 0x60b8,
172         NES_IDX_QUAD_HASH_TABLE_SIZE = 0x6148,
173         NES_IDX_PERFECT_FILTER_LOW = 0x6200,
174         NES_IDX_PERFECT_FILTER_HIGH = 0x6204,
175         NES_IDX_IPV4_TCP_REXMITS = 0x7080,
176         NES_IDX_DEBUG_ERROR_CONTROL_STATUS = 0x913c,
177         NES_IDX_DEBUG_ERROR_MASKS0 = 0x9140,
178         NES_IDX_DEBUG_ERROR_MASKS1 = 0x9144,
179         NES_IDX_DEBUG_ERROR_MASKS2 = 0x9148,
180         NES_IDX_DEBUG_ERROR_MASKS3 = 0x914c,
181         NES_IDX_DEBUG_ERROR_MASKS4 = 0x9150,
182         NES_IDX_DEBUG_ERROR_MASKS5 = 0x9154,
183 };
184
185 #define NES_IDX_MAC_TX_CONFIG_ENABLE_PAUSE   1
186 #define NES_IDX_MPP_DEBUG_PORT_DISABLE_PAUSE (1 << 17)
187
188 enum nes_cqp_opcodes {
189         NES_CQP_CREATE_QP = 0x00,
190         NES_CQP_MODIFY_QP = 0x01,
191         NES_CQP_DESTROY_QP = 0x02,
192         NES_CQP_CREATE_CQ = 0x03,
193         NES_CQP_MODIFY_CQ = 0x04,
194         NES_CQP_DESTROY_CQ = 0x05,
195         NES_CQP_ALLOCATE_STAG = 0x09,
196         NES_CQP_REGISTER_STAG = 0x0a,
197         NES_CQP_QUERY_STAG = 0x0b,
198         NES_CQP_REGISTER_SHARED_STAG = 0x0c,
199         NES_CQP_DEALLOCATE_STAG = 0x0d,
200         NES_CQP_MANAGE_ARP_CACHE = 0x0f,
201         NES_CQP_SUSPEND_QPS = 0x11,
202         NES_CQP_UPLOAD_CONTEXT = 0x13,
203         NES_CQP_CREATE_CEQ = 0x16,
204         NES_CQP_DESTROY_CEQ = 0x18,
205         NES_CQP_CREATE_AEQ = 0x19,
206         NES_CQP_DESTROY_AEQ = 0x1b,
207         NES_CQP_LMI_ACCESS = 0x20,
208         NES_CQP_FLUSH_WQES = 0x22,
209         NES_CQP_MANAGE_APBVT = 0x23
210 };
211
212 enum nes_cqp_wqe_word_idx {
213         NES_CQP_WQE_OPCODE_IDX = 0,
214         NES_CQP_WQE_ID_IDX = 1,
215         NES_CQP_WQE_COMP_CTX_LOW_IDX = 2,
216         NES_CQP_WQE_COMP_CTX_HIGH_IDX = 3,
217         NES_CQP_WQE_COMP_SCRATCH_LOW_IDX = 4,
218         NES_CQP_WQE_COMP_SCRATCH_HIGH_IDX = 5,
219 };
220
221 enum nes_cqp_cq_wqeword_idx {
222         NES_CQP_CQ_WQE_PBL_LOW_IDX = 6,
223         NES_CQP_CQ_WQE_PBL_HIGH_IDX = 7,
224         NES_CQP_CQ_WQE_CQ_CONTEXT_LOW_IDX = 8,
225         NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX = 9,
226         NES_CQP_CQ_WQE_DOORBELL_INDEX_HIGH_IDX = 10,
227 };
228
229 enum nes_cqp_stag_wqeword_idx {
230         NES_CQP_STAG_WQE_PBL_BLK_COUNT_IDX = 1,
231         NES_CQP_STAG_WQE_LEN_HIGH_PD_IDX = 6,
232         NES_CQP_STAG_WQE_LEN_LOW_IDX = 7,
233         NES_CQP_STAG_WQE_STAG_IDX = 8,
234         NES_CQP_STAG_WQE_VA_LOW_IDX = 10,
235         NES_CQP_STAG_WQE_VA_HIGH_IDX = 11,
236         NES_CQP_STAG_WQE_PA_LOW_IDX = 12,
237         NES_CQP_STAG_WQE_PA_HIGH_IDX = 13,
238         NES_CQP_STAG_WQE_PBL_LEN_IDX = 14
239 };
240
241 #define NES_CQP_OP_IWARP_STATE_SHIFT 28
242
243 enum nes_cqp_qp_bits {
244         NES_CQP_QP_ARP_VALID = (1<<8),
245         NES_CQP_QP_WINBUF_VALID = (1<<9),
246         NES_CQP_QP_CONTEXT_VALID = (1<<10),
247         NES_CQP_QP_ORD_VALID = (1<<11),
248         NES_CQP_QP_WINBUF_DATAIND_EN = (1<<12),
249         NES_CQP_QP_VIRT_WQS = (1<<13),
250         NES_CQP_QP_DEL_HTE = (1<<14),
251         NES_CQP_QP_CQS_VALID = (1<<15),
252         NES_CQP_QP_TYPE_TSA = 0,
253         NES_CQP_QP_TYPE_IWARP = (1<<16),
254         NES_CQP_QP_TYPE_CQP = (4<<16),
255         NES_CQP_QP_TYPE_NIC = (5<<16),
256         NES_CQP_QP_MSS_CHG = (1<<20),
257         NES_CQP_QP_STATIC_RESOURCES = (1<<21),
258         NES_CQP_QP_IGNORE_MW_BOUND = (1<<22),
259         NES_CQP_QP_VWQ_USE_LMI = (1<<23),
260         NES_CQP_QP_IWARP_STATE_IDLE = (1<<NES_CQP_OP_IWARP_STATE_SHIFT),
261         NES_CQP_QP_IWARP_STATE_RTS = (2<<NES_CQP_OP_IWARP_STATE_SHIFT),
262         NES_CQP_QP_IWARP_STATE_CLOSING = (3<<NES_CQP_OP_IWARP_STATE_SHIFT),
263         NES_CQP_QP_IWARP_STATE_TERMINATE = (5<<NES_CQP_OP_IWARP_STATE_SHIFT),
264         NES_CQP_QP_IWARP_STATE_ERROR = (6<<NES_CQP_OP_IWARP_STATE_SHIFT),
265         NES_CQP_QP_IWARP_STATE_MASK = (7<<NES_CQP_OP_IWARP_STATE_SHIFT),
266         NES_CQP_QP_RESET = (1<<31),
267 };
268
269 enum nes_cqp_qp_wqe_word_idx {
270         NES_CQP_QP_WQE_CONTEXT_LOW_IDX = 6,
271         NES_CQP_QP_WQE_CONTEXT_HIGH_IDX = 7,
272         NES_CQP_QP_WQE_NEW_MSS_IDX = 15,
273 };
274
275 enum nes_nic_ctx_bits {
276         NES_NIC_CTX_RQ_SIZE_32 = (3<<8),
277         NES_NIC_CTX_RQ_SIZE_512 = (3<<8),
278         NES_NIC_CTX_SQ_SIZE_32 = (1<<10),
279         NES_NIC_CTX_SQ_SIZE_512 = (3<<10),
280 };
281
282 enum nes_nic_qp_ctx_word_idx {
283         NES_NIC_CTX_MISC_IDX = 0,
284         NES_NIC_CTX_SQ_LOW_IDX = 2,
285         NES_NIC_CTX_SQ_HIGH_IDX = 3,
286         NES_NIC_CTX_RQ_LOW_IDX = 4,
287         NES_NIC_CTX_RQ_HIGH_IDX = 5,
288 };
289
290 enum nes_cqp_cq_bits {
291         NES_CQP_CQ_CEQE_MASK = (1<<9),
292         NES_CQP_CQ_CEQ_VALID = (1<<10),
293         NES_CQP_CQ_RESIZE = (1<<11),
294         NES_CQP_CQ_CHK_OVERFLOW = (1<<12),
295         NES_CQP_CQ_4KB_CHUNK = (1<<14),
296         NES_CQP_CQ_VIRT = (1<<15),
297 };
298
299 enum nes_cqp_stag_bits {
300         NES_CQP_STAG_VA_TO = (1<<9),
301         NES_CQP_STAG_DEALLOC_PBLS = (1<<10),
302         NES_CQP_STAG_PBL_BLK_SIZE = (1<<11),
303         NES_CQP_STAG_MR = (1<<13),
304         NES_CQP_STAG_RIGHTS_LOCAL_READ = (1<<16),
305         NES_CQP_STAG_RIGHTS_LOCAL_WRITE = (1<<17),
306         NES_CQP_STAG_RIGHTS_REMOTE_READ = (1<<18),
307         NES_CQP_STAG_RIGHTS_REMOTE_WRITE = (1<<19),
308         NES_CQP_STAG_RIGHTS_WINDOW_BIND = (1<<20),
309         NES_CQP_STAG_REM_ACC_EN = (1<<21),
310         NES_CQP_STAG_LEAVE_PENDING = (1<<31),
311 };
312
313 enum nes_cqp_ceq_wqeword_idx {
314         NES_CQP_CEQ_WQE_ELEMENT_COUNT_IDX = 1,
315         NES_CQP_CEQ_WQE_PBL_LOW_IDX = 6,
316         NES_CQP_CEQ_WQE_PBL_HIGH_IDX = 7,
317 };
318
319 enum nes_cqp_ceq_bits {
320         NES_CQP_CEQ_4KB_CHUNK = (1<<14),
321         NES_CQP_CEQ_VIRT = (1<<15),
322 };
323
324 enum nes_cqp_aeq_wqeword_idx {
325         NES_CQP_AEQ_WQE_ELEMENT_COUNT_IDX = 1,
326         NES_CQP_AEQ_WQE_PBL_LOW_IDX = 6,
327         NES_CQP_AEQ_WQE_PBL_HIGH_IDX = 7,
328 };
329
330 enum nes_cqp_aeq_bits {
331         NES_CQP_AEQ_4KB_CHUNK = (1<<14),
332         NES_CQP_AEQ_VIRT = (1<<15),
333 };
334
335 enum nes_cqp_lmi_wqeword_idx {
336         NES_CQP_LMI_WQE_LMI_OFFSET_IDX = 1,
337         NES_CQP_LMI_WQE_FRAG_LOW_IDX = 8,
338         NES_CQP_LMI_WQE_FRAG_HIGH_IDX = 9,
339         NES_CQP_LMI_WQE_FRAG_LEN_IDX = 10,
340 };
341
342 enum nes_cqp_arp_wqeword_idx {
343         NES_CQP_ARP_WQE_MAC_ADDR_LOW_IDX = 6,
344         NES_CQP_ARP_WQE_MAC_HIGH_IDX = 7,
345         NES_CQP_ARP_WQE_REACHABILITY_MAX_IDX = 1,
346 };
347
348 enum nes_cqp_upload_wqeword_idx {
349         NES_CQP_UPLOAD_WQE_CTXT_LOW_IDX = 6,
350         NES_CQP_UPLOAD_WQE_CTXT_HIGH_IDX = 7,
351         NES_CQP_UPLOAD_WQE_HTE_IDX = 8,
352 };
353
354 enum nes_cqp_arp_bits {
355         NES_CQP_ARP_VALID = (1<<8),
356         NES_CQP_ARP_PERM = (1<<9),
357 };
358
359 enum nes_cqp_flush_bits {
360         NES_CQP_FLUSH_SQ = (1<<30),
361         NES_CQP_FLUSH_RQ = (1<<31),
362 };
363
364 enum nes_cqe_opcode_bits {
365         NES_CQE_STAG_VALID = (1<<6),
366         NES_CQE_ERROR = (1<<7),
367         NES_CQE_SQ = (1<<8),
368         NES_CQE_SE = (1<<9),
369         NES_CQE_PSH = (1<<29),
370         NES_CQE_FIN = (1<<30),
371         NES_CQE_VALID = (1<<31),
372 };
373
374
375 enum nes_cqe_word_idx {
376         NES_CQE_PAYLOAD_LENGTH_IDX = 0,
377         NES_CQE_COMP_COMP_CTX_LOW_IDX = 2,
378         NES_CQE_COMP_COMP_CTX_HIGH_IDX = 3,
379         NES_CQE_INV_STAG_IDX = 4,
380         NES_CQE_QP_ID_IDX = 5,
381         NES_CQE_ERROR_CODE_IDX = 6,
382         NES_CQE_OPCODE_IDX = 7,
383 };
384
385 enum nes_ceqe_word_idx {
386         NES_CEQE_CQ_CTX_LOW_IDX = 0,
387         NES_CEQE_CQ_CTX_HIGH_IDX = 1,
388 };
389
390 enum nes_ceqe_status_bit {
391         NES_CEQE_VALID = (1<<31),
392 };
393
394 enum nes_int_bits {
395         NES_INT_CEQ0 = (1<<0),
396         NES_INT_CEQ1 = (1<<1),
397         NES_INT_CEQ2 = (1<<2),
398         NES_INT_CEQ3 = (1<<3),
399         NES_INT_CEQ4 = (1<<4),
400         NES_INT_CEQ5 = (1<<5),
401         NES_INT_CEQ6 = (1<<6),
402         NES_INT_CEQ7 = (1<<7),
403         NES_INT_CEQ8 = (1<<8),
404         NES_INT_CEQ9 = (1<<9),
405         NES_INT_CEQ10 = (1<<10),
406         NES_INT_CEQ11 = (1<<11),
407         NES_INT_CEQ12 = (1<<12),
408         NES_INT_CEQ13 = (1<<13),
409         NES_INT_CEQ14 = (1<<14),
410         NES_INT_CEQ15 = (1<<15),
411         NES_INT_AEQ0 = (1<<16),
412         NES_INT_AEQ1 = (1<<17),
413         NES_INT_AEQ2 = (1<<18),
414         NES_INT_AEQ3 = (1<<19),
415         NES_INT_AEQ4 = (1<<20),
416         NES_INT_AEQ5 = (1<<21),
417         NES_INT_AEQ6 = (1<<22),
418         NES_INT_AEQ7 = (1<<23),
419         NES_INT_MAC0 = (1<<24),
420         NES_INT_MAC1 = (1<<25),
421         NES_INT_MAC2 = (1<<26),
422         NES_INT_MAC3 = (1<<27),
423         NES_INT_TSW = (1<<28),
424         NES_INT_TIMER = (1<<29),
425         NES_INT_INTF = (1<<30),
426 };
427
428 enum nes_intf_int_bits {
429         NES_INTF_INT_PCIERR = (1<<0),
430         NES_INTF_PERIODIC_TIMER = (1<<2),
431         NES_INTF_ONE_SHOT_TIMER = (1<<3),
432         NES_INTF_INT_CRITERR = (1<<14),
433         NES_INTF_INT_AEQ0_OFLOW = (1<<16),
434         NES_INTF_INT_AEQ1_OFLOW = (1<<17),
435         NES_INTF_INT_AEQ2_OFLOW = (1<<18),
436         NES_INTF_INT_AEQ3_OFLOW = (1<<19),
437         NES_INTF_INT_AEQ4_OFLOW = (1<<20),
438         NES_INTF_INT_AEQ5_OFLOW = (1<<21),
439         NES_INTF_INT_AEQ6_OFLOW = (1<<22),
440         NES_INTF_INT_AEQ7_OFLOW = (1<<23),
441         NES_INTF_INT_AEQ_OFLOW = (0xff<<16),
442 };
443
444 enum nes_mac_int_bits {
445         NES_MAC_INT_LINK_STAT_CHG = (1<<1),
446         NES_MAC_INT_XGMII_EXT = (1<<2),
447         NES_MAC_INT_TX_UNDERFLOW = (1<<6),
448         NES_MAC_INT_TX_ERROR = (1<<7),
449 };
450
451 enum nes_cqe_allocate_bits {
452         NES_CQE_ALLOC_INC_SELECT = (1<<28),
453         NES_CQE_ALLOC_NOTIFY_NEXT = (1<<29),
454         NES_CQE_ALLOC_NOTIFY_SE = (1<<30),
455         NES_CQE_ALLOC_RESET = (1<<31),
456 };
457
458 enum nes_nic_rq_wqe_word_idx {
459         NES_NIC_RQ_WQE_LENGTH_1_0_IDX = 0,
460         NES_NIC_RQ_WQE_LENGTH_3_2_IDX = 1,
461         NES_NIC_RQ_WQE_FRAG0_LOW_IDX = 2,
462         NES_NIC_RQ_WQE_FRAG0_HIGH_IDX = 3,
463         NES_NIC_RQ_WQE_FRAG1_LOW_IDX = 4,
464         NES_NIC_RQ_WQE_FRAG1_HIGH_IDX = 5,
465         NES_NIC_RQ_WQE_FRAG2_LOW_IDX = 6,
466         NES_NIC_RQ_WQE_FRAG2_HIGH_IDX = 7,
467         NES_NIC_RQ_WQE_FRAG3_LOW_IDX = 8,
468         NES_NIC_RQ_WQE_FRAG3_HIGH_IDX = 9,
469 };
470
471 enum nes_nic_sq_wqe_word_idx {
472         NES_NIC_SQ_WQE_MISC_IDX = 0,
473         NES_NIC_SQ_WQE_TOTAL_LENGTH_IDX = 1,
474         NES_NIC_SQ_WQE_LSO_INFO_IDX = 2,
475         NES_NIC_SQ_WQE_LENGTH_0_TAG_IDX = 3,
476         NES_NIC_SQ_WQE_LENGTH_2_1_IDX = 4,
477         NES_NIC_SQ_WQE_LENGTH_4_3_IDX = 5,
478         NES_NIC_SQ_WQE_FRAG0_LOW_IDX = 6,
479         NES_NIC_SQ_WQE_FRAG0_HIGH_IDX = 7,
480         NES_NIC_SQ_WQE_FRAG1_LOW_IDX = 8,
481         NES_NIC_SQ_WQE_FRAG1_HIGH_IDX = 9,
482         NES_NIC_SQ_WQE_FRAG2_LOW_IDX = 10,
483         NES_NIC_SQ_WQE_FRAG2_HIGH_IDX = 11,
484         NES_NIC_SQ_WQE_FRAG3_LOW_IDX = 12,
485         NES_NIC_SQ_WQE_FRAG3_HIGH_IDX = 13,
486         NES_NIC_SQ_WQE_FRAG4_LOW_IDX = 14,
487         NES_NIC_SQ_WQE_FRAG4_HIGH_IDX = 15,
488 };
489
490 enum nes_iwarp_sq_wqe_word_idx {
491         NES_IWARP_SQ_WQE_MISC_IDX = 0,
492         NES_IWARP_SQ_WQE_TOTAL_PAYLOAD_IDX = 1,
493         NES_IWARP_SQ_WQE_COMP_CTX_LOW_IDX = 2,
494         NES_IWARP_SQ_WQE_COMP_CTX_HIGH_IDX = 3,
495         NES_IWARP_SQ_WQE_COMP_SCRATCH_LOW_IDX = 4,
496         NES_IWARP_SQ_WQE_COMP_SCRATCH_HIGH_IDX = 5,
497         NES_IWARP_SQ_WQE_INV_STAG_LOW_IDX = 7,
498         NES_IWARP_SQ_WQE_RDMA_TO_LOW_IDX = 8,
499         NES_IWARP_SQ_WQE_RDMA_TO_HIGH_IDX = 9,
500         NES_IWARP_SQ_WQE_RDMA_LENGTH_IDX = 10,
501         NES_IWARP_SQ_WQE_RDMA_STAG_IDX = 11,
502         NES_IWARP_SQ_WQE_IMM_DATA_START_IDX = 12,
503         NES_IWARP_SQ_WQE_FRAG0_LOW_IDX = 16,
504         NES_IWARP_SQ_WQE_FRAG0_HIGH_IDX = 17,
505         NES_IWARP_SQ_WQE_LENGTH0_IDX = 18,
506         NES_IWARP_SQ_WQE_STAG0_IDX = 19,
507         NES_IWARP_SQ_WQE_FRAG1_LOW_IDX = 20,
508         NES_IWARP_SQ_WQE_FRAG1_HIGH_IDX = 21,
509         NES_IWARP_SQ_WQE_LENGTH1_IDX = 22,
510         NES_IWARP_SQ_WQE_STAG1_IDX = 23,
511         NES_IWARP_SQ_WQE_FRAG2_LOW_IDX = 24,
512         NES_IWARP_SQ_WQE_FRAG2_HIGH_IDX = 25,
513         NES_IWARP_SQ_WQE_LENGTH2_IDX = 26,
514         NES_IWARP_SQ_WQE_STAG2_IDX = 27,
515         NES_IWARP_SQ_WQE_FRAG3_LOW_IDX = 28,
516         NES_IWARP_SQ_WQE_FRAG3_HIGH_IDX = 29,
517         NES_IWARP_SQ_WQE_LENGTH3_IDX = 30,
518         NES_IWARP_SQ_WQE_STAG3_IDX = 31,
519 };
520
521 enum nes_iwarp_sq_bind_wqe_word_idx {
522         NES_IWARP_SQ_BIND_WQE_MR_IDX = 6,
523         NES_IWARP_SQ_BIND_WQE_MW_IDX = 7,
524         NES_IWARP_SQ_BIND_WQE_LENGTH_LOW_IDX = 8,
525         NES_IWARP_SQ_BIND_WQE_LENGTH_HIGH_IDX = 9,
526         NES_IWARP_SQ_BIND_WQE_VA_FBO_LOW_IDX = 10,
527         NES_IWARP_SQ_BIND_WQE_VA_FBO_HIGH_IDX = 11,
528 };
529
530 enum nes_iwarp_sq_fmr_wqe_word_idx {
531         NES_IWARP_SQ_FMR_WQE_MR_STAG_IDX = 7,
532         NES_IWARP_SQ_FMR_WQE_LENGTH_LOW_IDX = 8,
533         NES_IWARP_SQ_FMR_WQE_LENGTH_HIGH_IDX = 9,
534         NES_IWARP_SQ_FMR_WQE_VA_FBO_LOW_IDX = 10,
535         NES_IWARP_SQ_FMR_WQE_VA_FBO_HIGH_IDX = 11,
536         NES_IWARP_SQ_FMR_WQE_PBL_ADDR_LOW_IDX = 12,
537         NES_IWARP_SQ_FMR_WQE_PBL_ADDR_HIGH_IDX = 13,
538         NES_IWARP_SQ_FMR_WQE_PBL_LENGTH_IDX = 14,
539 };
540
541 enum nes_iwarp_sq_locinv_wqe_word_idx {
542         NES_IWARP_SQ_LOCINV_WQE_INV_STAG_IDX = 6,
543 };
544
545
546 enum nes_iwarp_rq_wqe_word_idx {
547         NES_IWARP_RQ_WQE_TOTAL_PAYLOAD_IDX = 1,
548         NES_IWARP_RQ_WQE_COMP_CTX_LOW_IDX = 2,
549         NES_IWARP_RQ_WQE_COMP_CTX_HIGH_IDX = 3,
550         NES_IWARP_RQ_WQE_COMP_SCRATCH_LOW_IDX = 4,
551         NES_IWARP_RQ_WQE_COMP_SCRATCH_HIGH_IDX = 5,
552         NES_IWARP_RQ_WQE_FRAG0_LOW_IDX = 8,
553         NES_IWARP_RQ_WQE_FRAG0_HIGH_IDX = 9,
554         NES_IWARP_RQ_WQE_LENGTH0_IDX = 10,
555         NES_IWARP_RQ_WQE_STAG0_IDX = 11,
556         NES_IWARP_RQ_WQE_FRAG1_LOW_IDX = 12,
557         NES_IWARP_RQ_WQE_FRAG1_HIGH_IDX = 13,
558         NES_IWARP_RQ_WQE_LENGTH1_IDX = 14,
559         NES_IWARP_RQ_WQE_STAG1_IDX = 15,
560         NES_IWARP_RQ_WQE_FRAG2_LOW_IDX = 16,
561         NES_IWARP_RQ_WQE_FRAG2_HIGH_IDX = 17,
562         NES_IWARP_RQ_WQE_LENGTH2_IDX = 18,
563         NES_IWARP_RQ_WQE_STAG2_IDX = 19,
564         NES_IWARP_RQ_WQE_FRAG3_LOW_IDX = 20,
565         NES_IWARP_RQ_WQE_FRAG3_HIGH_IDX = 21,
566         NES_IWARP_RQ_WQE_LENGTH3_IDX = 22,
567         NES_IWARP_RQ_WQE_STAG3_IDX = 23,
568 };
569
570 enum nes_nic_sq_wqe_bits {
571         NES_NIC_SQ_WQE_PHDR_CS_READY =  (1<<21),
572         NES_NIC_SQ_WQE_LSO_ENABLE = (1<<22),
573         NES_NIC_SQ_WQE_TAGVALUE_ENABLE = (1<<23),
574         NES_NIC_SQ_WQE_DISABLE_CHKSUM = (1<<30),
575         NES_NIC_SQ_WQE_COMPLETION = (1<<31),
576 };
577
578 enum nes_nic_cqe_word_idx {
579         NES_NIC_CQE_ACCQP_ID_IDX = 0,
580         NES_NIC_CQE_TAG_PKT_TYPE_IDX = 2,
581         NES_NIC_CQE_MISC_IDX = 3,
582 };
583
584 #define NES_PKT_TYPE_APBVT_BITS 0xC112
585 #define NES_PKT_TYPE_APBVT_MASK 0xff3e
586
587 #define NES_PKT_TYPE_PVALID_BITS 0x10000000
588 #define NES_PKT_TYPE_PVALID_MASK 0x30000000
589
590 #define NES_PKT_TYPE_TCPV4_BITS 0x0110
591 #define NES_PKT_TYPE_TCPV4_MASK 0x3f30
592
593 #define NES_PKT_TYPE_UDPV4_BITS 0x0210
594 #define NES_PKT_TYPE_UDPV4_MASK 0x3f30
595
596 #define NES_PKT_TYPE_IPV4_BITS  0x0010
597 #define NES_PKT_TYPE_IPV4_MASK  0x3f30
598
599 #define NES_PKT_TYPE_OTHER_BITS 0x0000
600 #define NES_PKT_TYPE_OTHER_MASK 0x0030
601
602 #define NES_NIC_CQE_ERRV_SHIFT 16
603 enum nes_nic_ev_bits {
604         NES_NIC_ERRV_BITS_MODE = (1<<0),
605         NES_NIC_ERRV_BITS_IPV4_CSUM_ERR = (1<<1),
606         NES_NIC_ERRV_BITS_TCPUDP_CSUM_ERR = (1<<2),
607         NES_NIC_ERRV_BITS_WQE_OVERRUN = (1<<3),
608         NES_NIC_ERRV_BITS_IPH_ERR = (1<<4),
609 };
610
611 enum nes_nic_cqe_bits {
612         NES_NIC_CQE_ERRV_MASK = (0xff<<NES_NIC_CQE_ERRV_SHIFT),
613         NES_NIC_CQE_SQ = (1<<24),
614         NES_NIC_CQE_ACCQP_PORT = (1<<28),
615         NES_NIC_CQE_ACCQP_VALID = (1<<29),
616         NES_NIC_CQE_TAG_VALID = (1<<30),
617         NES_NIC_CQE_VALID = (1<<31),
618 };
619
620 enum nes_aeqe_word_idx {
621         NES_AEQE_COMP_CTXT_LOW_IDX = 0,
622         NES_AEQE_COMP_CTXT_HIGH_IDX = 1,
623         NES_AEQE_COMP_QP_CQ_ID_IDX = 2,
624         NES_AEQE_MISC_IDX = 3,
625 };
626
627 enum nes_aeqe_bits {
628         NES_AEQE_QP = (1<<16),
629         NES_AEQE_CQ = (1<<17),
630         NES_AEQE_SQ = (1<<18),
631         NES_AEQE_INBOUND_RDMA = (1<<19),
632         NES_AEQE_IWARP_STATE_MASK = (7<<20),
633         NES_AEQE_TCP_STATE_MASK = (0xf<<24),
634         NES_AEQE_VALID = (1<<31),
635 };
636
637 #define NES_AEQE_IWARP_STATE_SHIFT      20
638 #define NES_AEQE_TCP_STATE_SHIFT        24
639
640 enum nes_aeqe_iwarp_state {
641         NES_AEQE_IWARP_STATE_NON_EXISTANT = 0,
642         NES_AEQE_IWARP_STATE_IDLE = 1,
643         NES_AEQE_IWARP_STATE_RTS = 2,
644         NES_AEQE_IWARP_STATE_CLOSING = 3,
645         NES_AEQE_IWARP_STATE_TERMINATE = 5,
646         NES_AEQE_IWARP_STATE_ERROR = 6
647 };
648
649 enum nes_aeqe_tcp_state {
650         NES_AEQE_TCP_STATE_NON_EXISTANT = 0,
651         NES_AEQE_TCP_STATE_CLOSED = 1,
652         NES_AEQE_TCP_STATE_LISTEN = 2,
653         NES_AEQE_TCP_STATE_SYN_SENT = 3,
654         NES_AEQE_TCP_STATE_SYN_RCVD = 4,
655         NES_AEQE_TCP_STATE_ESTABLISHED = 5,
656         NES_AEQE_TCP_STATE_CLOSE_WAIT = 6,
657         NES_AEQE_TCP_STATE_FIN_WAIT_1 = 7,
658         NES_AEQE_TCP_STATE_CLOSING = 8,
659         NES_AEQE_TCP_STATE_LAST_ACK = 9,
660         NES_AEQE_TCP_STATE_FIN_WAIT_2 = 10,
661         NES_AEQE_TCP_STATE_TIME_WAIT = 11
662 };
663
664 enum nes_aeqe_aeid {
665         NES_AEQE_AEID_AMP_UNALLOCATED_STAG                            = 0x0102,
666         NES_AEQE_AEID_AMP_INVALID_STAG                                = 0x0103,
667         NES_AEQE_AEID_AMP_BAD_QP                                      = 0x0104,
668         NES_AEQE_AEID_AMP_BAD_PD                                      = 0x0105,
669         NES_AEQE_AEID_AMP_BAD_STAG_KEY                                = 0x0106,
670         NES_AEQE_AEID_AMP_BAD_STAG_INDEX                              = 0x0107,
671         NES_AEQE_AEID_AMP_BOUNDS_VIOLATION                            = 0x0108,
672         NES_AEQE_AEID_AMP_RIGHTS_VIOLATION                            = 0x0109,
673         NES_AEQE_AEID_AMP_TO_WRAP                                     = 0x010a,
674         NES_AEQE_AEID_AMP_FASTREG_SHARED                              = 0x010b,
675         NES_AEQE_AEID_AMP_FASTREG_VALID_STAG                          = 0x010c,
676         NES_AEQE_AEID_AMP_FASTREG_MW_STAG                             = 0x010d,
677         NES_AEQE_AEID_AMP_FASTREG_INVALID_RIGHTS                      = 0x010e,
678         NES_AEQE_AEID_AMP_FASTREG_PBL_TABLE_OVERFLOW                  = 0x010f,
679         NES_AEQE_AEID_AMP_FASTREG_INVALID_LENGTH                      = 0x0110,
680         NES_AEQE_AEID_AMP_INVALIDATE_SHARED                           = 0x0111,
681         NES_AEQE_AEID_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS          = 0x0112,
682         NES_AEQE_AEID_AMP_INVALIDATE_MR_WITH_BOUND_WINDOWS            = 0x0113,
683         NES_AEQE_AEID_AMP_MWBIND_VALID_STAG                           = 0x0114,
684         NES_AEQE_AEID_AMP_MWBIND_OF_MR_STAG                           = 0x0115,
685         NES_AEQE_AEID_AMP_MWBIND_TO_ZERO_BASED_STAG                   = 0x0116,
686         NES_AEQE_AEID_AMP_MWBIND_TO_MW_STAG                           = 0x0117,
687         NES_AEQE_AEID_AMP_MWBIND_INVALID_RIGHTS                       = 0x0118,
688         NES_AEQE_AEID_AMP_MWBIND_INVALID_BOUNDS                       = 0x0119,
689         NES_AEQE_AEID_AMP_MWBIND_TO_INVALID_PARENT                    = 0x011a,
690         NES_AEQE_AEID_AMP_MWBIND_BIND_DISABLED                        = 0x011b,
691         NES_AEQE_AEID_BAD_CLOSE                                       = 0x0201,
692         NES_AEQE_AEID_RDMAP_ROE_BAD_LLP_CLOSE                         = 0x0202,
693         NES_AEQE_AEID_CQ_OPERATION_ERROR                              = 0x0203,
694         NES_AEQE_AEID_PRIV_OPERATION_DENIED                           = 0x0204,
695         NES_AEQE_AEID_RDMA_READ_WHILE_ORD_ZERO                        = 0x0205,
696         NES_AEQE_AEID_STAG_ZERO_INVALID                               = 0x0206,
697         NES_AEQE_AEID_DDP_INVALID_MSN_GAP_IN_MSN                      = 0x0301,
698         NES_AEQE_AEID_DDP_INVALID_MSN_RANGE_IS_NOT_VALID              = 0x0302,
699         NES_AEQE_AEID_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER = 0x0303,
700         NES_AEQE_AEID_DDP_UBE_INVALID_DDP_VERSION                     = 0x0304,
701         NES_AEQE_AEID_DDP_UBE_INVALID_MO                              = 0x0305,
702         NES_AEQE_AEID_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE         = 0x0306,
703         NES_AEQE_AEID_DDP_UBE_INVALID_QN                              = 0x0307,
704         NES_AEQE_AEID_DDP_NO_L_BIT                                    = 0x0308,
705         NES_AEQE_AEID_RDMAP_ROE_INVALID_RDMAP_VERSION                 = 0x0311,
706         NES_AEQE_AEID_RDMAP_ROE_UNEXPECTED_OPCODE                     = 0x0312,
707         NES_AEQE_AEID_ROE_INVALID_RDMA_READ_REQUEST                   = 0x0313,
708         NES_AEQE_AEID_ROE_INVALID_RDMA_WRITE_OR_READ_RESP             = 0x0314,
709         NES_AEQE_AEID_INVALID_ARP_ENTRY                               = 0x0401,
710         NES_AEQE_AEID_INVALID_TCP_OPTION_RCVD                         = 0x0402,
711         NES_AEQE_AEID_STALE_ARP_ENTRY                                 = 0x0403,
712         NES_AEQE_AEID_LLP_CLOSE_COMPLETE                              = 0x0501,
713         NES_AEQE_AEID_LLP_CONNECTION_RESET                            = 0x0502,
714         NES_AEQE_AEID_LLP_FIN_RECEIVED                                = 0x0503,
715         NES_AEQE_AEID_LLP_RECEIVED_MARKER_AND_LENGTH_FIELDS_DONT_MATCH =  0x0504,
716         NES_AEQE_AEID_LLP_RECEIVED_MPA_CRC_ERROR                      = 0x0505,
717         NES_AEQE_AEID_LLP_SEGMENT_TOO_LARGE                           = 0x0506,
718         NES_AEQE_AEID_LLP_SEGMENT_TOO_SMALL                           = 0x0507,
719         NES_AEQE_AEID_LLP_SYN_RECEIVED                                = 0x0508,
720         NES_AEQE_AEID_LLP_TERMINATE_RECEIVED                          = 0x0509,
721         NES_AEQE_AEID_LLP_TOO_MANY_RETRIES                            = 0x050a,
722         NES_AEQE_AEID_LLP_TOO_MANY_KEEPALIVE_RETRIES                  = 0x050b,
723         NES_AEQE_AEID_RESET_SENT                                      = 0x0601,
724         NES_AEQE_AEID_TERMINATE_SENT                                  = 0x0602,
725         NES_AEQE_AEID_DDP_LCE_LOCAL_CATASTROPHIC                      = 0x0700
726 };
727
728 enum nes_iwarp_sq_opcodes {
729         NES_IWARP_SQ_WQE_WRPDU = (1<<15),
730         NES_IWARP_SQ_WQE_PSH = (1<<21),
731         NES_IWARP_SQ_WQE_STREAMING = (1<<23),
732         NES_IWARP_SQ_WQE_IMM_DATA = (1<<28),
733         NES_IWARP_SQ_WQE_READ_FENCE = (1<<29),
734         NES_IWARP_SQ_WQE_LOCAL_FENCE = (1<<30),
735         NES_IWARP_SQ_WQE_SIGNALED_COMPL = (1<<31),
736 };
737
738 enum nes_iwarp_sq_wqe_bits {
739         NES_IWARP_SQ_OP_RDMAW = 0,
740         NES_IWARP_SQ_OP_RDMAR = 1,
741         NES_IWARP_SQ_OP_SEND = 3,
742         NES_IWARP_SQ_OP_SENDINV = 4,
743         NES_IWARP_SQ_OP_SENDSE = 5,
744         NES_IWARP_SQ_OP_SENDSEINV = 6,
745         NES_IWARP_SQ_OP_BIND = 8,
746         NES_IWARP_SQ_OP_FAST_REG = 9,
747         NES_IWARP_SQ_OP_LOCINV = 10,
748         NES_IWARP_SQ_OP_RDMAR_LOCINV = 11,
749         NES_IWARP_SQ_OP_NOP = 12,
750 };
751
752 #define NES_EEPROM_READ_REQUEST (1<<16)
753 #define NES_MAC_ADDR_VALID      (1<<20)
754
755 /*
756  * NES index registers init values.
757  */
758 struct nes_init_values {
759         u32 index;
760         u32 data;
761         u8  wrt;
762 };
763
764 /*
765  * NES registers in BAR0.
766  */
767 struct nes_pci_regs {
768         u32 int_status;
769         u32 int_mask;
770         u32 int_pending;
771         u32 intf_int_status;
772         u32 intf_int_mask;
773         u32 other_regs[59];      /* pad out to 256 bytes for now */
774 };
775
776 #define NES_CQP_SQ_SIZE    128
777 #define NES_CCQ_SIZE       128
778 #define NES_NIC_WQ_SIZE    512
779 #define NES_NIC_CTX_SIZE   ((NES_NIC_CTX_RQ_SIZE_512) | (NES_NIC_CTX_SQ_SIZE_512))
780 #define NES_NIC_BACK_STORE 0x00038000
781
782 struct nes_device;
783
784 struct nes_hw_nic_qp_context {
785         __le32 context_words[6];
786 };
787
788 struct nes_hw_nic_sq_wqe {
789         __le32 wqe_words[16];
790 };
791
792 struct nes_hw_nic_rq_wqe {
793         __le32 wqe_words[16];
794 };
795
796 struct nes_hw_nic_cqe {
797         __le32 cqe_words[4];
798 };
799
800 struct nes_hw_cqp_qp_context {
801         __le32 context_words[4];
802 };
803
804 struct nes_hw_cqp_wqe {
805         __le32 wqe_words[16];
806 };
807
808 struct nes_hw_qp_wqe {
809         __le32 wqe_words[32];
810 };
811
812 struct nes_hw_cqe {
813         __le32 cqe_words[8];
814 };
815
816 struct nes_hw_ceqe {
817         __le32 ceqe_words[2];
818 };
819
820 struct nes_hw_aeqe {
821         __le32 aeqe_words[4];
822 };
823
824 struct nes_cqp_request {
825         union {
826                 u64 cqp_callback_context;
827                 void *cqp_callback_pointer;
828         };
829         wait_queue_head_t     waitq;
830         struct nes_hw_cqp_wqe cqp_wqe;
831         struct list_head      list;
832         atomic_t              refcount;
833         void (*cqp_callback)(struct nes_device *nesdev, struct nes_cqp_request *cqp_request);
834         u16                   major_code;
835         u16                   minor_code;
836         u8                    waiting;
837         u8                    request_done;
838         u8                    dynamic;
839         u8                    callback;
840 };
841
842 struct nes_hw_cqp {
843         struct nes_hw_cqp_wqe *sq_vbase;
844         dma_addr_t            sq_pbase;
845         spinlock_t            lock;
846         wait_queue_head_t     waitq;
847         u16                   qp_id;
848         u16                   sq_head;
849         u16                   sq_tail;
850         u16                   sq_size;
851 };
852
853 #define NES_FIRST_FRAG_SIZE 128
854 struct nes_first_frag {
855         u8 buffer[NES_FIRST_FRAG_SIZE];
856 };
857
858 struct nes_hw_nic {
859         struct nes_first_frag    *first_frag_vbase;     /* virtual address of first frags */
860         struct nes_hw_nic_sq_wqe *sq_vbase;                     /* virtual address of sq */
861         struct nes_hw_nic_rq_wqe *rq_vbase;                     /* virtual address of rq */
862         struct sk_buff           *tx_skb[NES_NIC_WQ_SIZE];
863         struct sk_buff           *rx_skb[NES_NIC_WQ_SIZE];
864         dma_addr_t frag_paddr[NES_NIC_WQ_SIZE];
865         unsigned long first_frag_overflow[BITS_TO_LONGS(NES_NIC_WQ_SIZE)];
866         dma_addr_t sq_pbase;                    /* PCI memory for host rings */
867         dma_addr_t rq_pbase;                    /* PCI memory for host rings */
868
869         u16 qp_id;
870         u16 sq_head;
871         u16 sq_tail;
872         u16 sq_size;
873         u16 rq_head;
874         u16 rq_tail;
875         u16 rq_size;
876         u8 replenishing_rq;
877         u8 reserved;
878
879         spinlock_t rq_lock;
880 };
881
882 struct nes_hw_nic_cq {
883         struct nes_hw_nic_cqe volatile *cq_vbase;       /* PCI memory for host rings */
884         void (*ce_handler)(struct nes_device *nesdev, struct nes_hw_nic_cq *cq);
885         dma_addr_t cq_pbase;    /* PCI memory for host rings */
886         int rx_cqes_completed;
887         int cqe_allocs_pending;
888         int rx_pkts_indicated;
889         u16 cq_head;
890         u16 cq_size;
891         u16 cq_number;
892         u8  cqes_pending;
893 };
894
895 struct nes_hw_qp {
896         struct nes_hw_qp_wqe *sq_vbase;         /* PCI memory for host rings */
897         struct nes_hw_qp_wqe *rq_vbase;         /* PCI memory for host rings */
898         void                 *q2_vbase;                 /* PCI memory for host rings */
899         dma_addr_t sq_pbase;    /* PCI memory for host rings */
900         dma_addr_t rq_pbase;    /* PCI memory for host rings */
901         dma_addr_t q2_pbase;    /* PCI memory for host rings */
902         u32 qp_id;
903         u16 sq_head;
904         u16 sq_tail;
905         u16 sq_size;
906         u16 rq_head;
907         u16 rq_tail;
908         u16 rq_size;
909         u8  rq_encoded_size;
910         u8  sq_encoded_size;
911 };
912
913 struct nes_hw_cq {
914         struct nes_hw_cqe *cq_vbase;    /* PCI memory for host rings */
915         void (*ce_handler)(struct nes_device *nesdev, struct nes_hw_cq *cq);
916         dma_addr_t cq_pbase;    /* PCI memory for host rings */
917         u16 cq_head;
918         u16 cq_size;
919         u16 cq_number;
920 };
921
922 struct nes_hw_ceq {
923         struct nes_hw_ceqe volatile *ceq_vbase; /* PCI memory for host rings */
924         dma_addr_t ceq_pbase;   /* PCI memory for host rings */
925         u16 ceq_head;
926         u16 ceq_size;
927 };
928
929 struct nes_hw_aeq {
930         struct nes_hw_aeqe volatile *aeq_vbase; /* PCI memory for host rings */
931         dma_addr_t aeq_pbase;   /* PCI memory for host rings */
932         u16 aeq_head;
933         u16 aeq_size;
934 };
935
936 struct nic_qp_map {
937         u8 qpid;
938         u8 nic_index;
939         u8 logical_port;
940         u8 is_hnic;
941 };
942
943 #define NES_CQP_ARP_AEQ_INDEX_MASK  0x000f0000
944 #define NES_CQP_ARP_AEQ_INDEX_SHIFT 16
945
946 #define NES_CQP_APBVT_ADD                       0x00008000
947 #define NES_CQP_APBVT_NIC_SHIFT         16
948
949 #define NES_ARP_ADD     1
950 #define NES_ARP_DELETE  2
951 #define NES_ARP_RESOLVE 3
952
953 #define NES_MAC_SW_IDLE      0
954 #define NES_MAC_SW_INTERRUPT 1
955 #define NES_MAC_SW_MH        2
956
957 struct nes_arp_entry {
958         u32 ip_addr;
959         u8  mac_addr[ETH_ALEN];
960 };
961
962 #define NES_NIC_FAST_TIMER          96
963 #define NES_NIC_FAST_TIMER_LOW      40
964 #define NES_NIC_FAST_TIMER_HIGH     1000
965 #define DEFAULT_NES_QL_HIGH         256
966 #define DEFAULT_NES_QL_LOW          16
967 #define DEFAULT_NES_QL_TARGET       64
968 #define DEFAULT_JUMBO_NES_QL_LOW    12
969 #define DEFAULT_JUMBO_NES_QL_TARGET 40
970 #define DEFAULT_JUMBO_NES_QL_HIGH   128
971 #define NES_NIC_CQ_DOWNWARD_TREND   16
972 #define NES_PFT_SIZE                48
973
974 struct nes_hw_tune_timer {
975     /* u16 cq_count; */
976     u16 threshold_low;
977     u16 threshold_target;
978     u16 threshold_high;
979     u16 timer_in_use;
980     u16 timer_in_use_old;
981     u16 timer_in_use_min;
982     u16 timer_in_use_max;
983     u8  timer_direction_upward;
984     u8  timer_direction_downward;
985     u16 cq_count_old;
986     u8  cq_direction_downward;
987 };
988
989 #define NES_TIMER_INT_LIMIT         2
990 #define NES_TIMER_INT_LIMIT_DYNAMIC 10
991 #define NES_TIMER_ENABLE_LIMIT      4
992 #define NES_MAX_LINK_INTERRUPTS     128
993 #define NES_MAX_LINK_CHECK          200
994 #define NES_MAX_LRO_DESCRIPTORS     32
995 #define NES_LRO_MAX_AGGR            64
996
997 struct nes_adapter {
998         u64              fw_ver;
999         unsigned long    *allocated_qps;
1000         unsigned long    *allocated_cqs;
1001         unsigned long    *allocated_mrs;
1002         unsigned long    *allocated_pds;
1003         unsigned long    *allocated_arps;
1004         struct nes_qp    **qp_table;
1005         struct workqueue_struct *work_q;
1006
1007         struct list_head list;
1008         struct list_head active_listeners;
1009         /* list of the netdev's associated with each logical port */
1010         struct list_head nesvnic_list[4];
1011
1012         struct timer_list  mh_timer;
1013         struct timer_list  lc_timer;
1014         struct work_struct work;
1015         spinlock_t         resource_lock;
1016         spinlock_t         phy_lock;
1017         spinlock_t         pbl_lock;
1018         spinlock_t         periodic_timer_lock;
1019
1020         struct nes_arp_entry arp_table[NES_MAX_ARP_TABLE_SIZE];
1021
1022         /* Adapter CEQ and AEQs */
1023         struct nes_hw_ceq ceq[16];
1024         struct nes_hw_aeq aeq[8];
1025
1026         struct nes_hw_tune_timer tune_timer;
1027
1028         unsigned long doorbell_start;
1029
1030         u32 hw_rev;
1031         u32 vendor_id;
1032         u32 vendor_part_id;
1033         u32 device_cap_flags;
1034         u32 tick_delta;
1035         u32 timer_int_req;
1036         u32 arp_table_size;
1037         u32 next_arp_index;
1038
1039         u32 max_mr;
1040         u32 max_256pbl;
1041         u32 max_4kpbl;
1042         u32 free_256pbl;
1043         u32 free_4kpbl;
1044         u32 max_mr_size;
1045         u32 max_qp;
1046         u32 next_qp;
1047         u32 max_irrq;
1048         u32 max_qp_wr;
1049         u32 max_sge;
1050         u32 max_cq;
1051         u32 next_cq;
1052         u32 max_cqe;
1053         u32 max_pd;
1054         u32 base_pd;
1055         u32 next_pd;
1056         u32 hte_index_mask;
1057
1058         /* EEPROM information */
1059         u32 rx_pool_size;
1060         u32 tx_pool_size;
1061         u32 rx_threshold;
1062         u32 tcp_timer_core_clk_divisor;
1063         u32 iwarp_config;
1064         u32 cm_config;
1065         u32 sws_timer_config;
1066         u32 tcp_config1;
1067         u32 wqm_wat;
1068         u32 core_clock;
1069         u32 firmware_version;
1070
1071         u32 nic_rx_eth_route_err;
1072
1073         u32 et_rx_coalesce_usecs;
1074         u32     et_rx_max_coalesced_frames;
1075         u32 et_rx_coalesce_usecs_irq;
1076         u32 et_rx_max_coalesced_frames_irq;
1077         u32 et_pkt_rate_low;
1078         u32 et_rx_coalesce_usecs_low;
1079         u32 et_rx_max_coalesced_frames_low;
1080         u32 et_pkt_rate_high;
1081         u32 et_rx_coalesce_usecs_high;
1082         u32 et_rx_max_coalesced_frames_high;
1083         u32 et_rate_sample_interval;
1084         u32 timer_int_limit;
1085         u32 wqm_quanta;
1086
1087         /* Adapter base MAC address */
1088         u32 mac_addr_low;
1089         u16 mac_addr_high;
1090
1091         u16 firmware_eeprom_offset;
1092         u16 software_eeprom_offset;
1093
1094         u16 max_irrq_wr;
1095
1096         /* pd config for each port */
1097         u16 pd_config_size[4];
1098         u16 pd_config_base[4];
1099
1100         u16 link_interrupt_count[4];
1101         u8 crit_error_count[32];
1102
1103         /* the phy index for each port */
1104         u8  phy_index[4];
1105         u8  mac_sw_state[4];
1106         u8  mac_link_down[4];
1107         u8  phy_type[4];
1108         u8  log_port;
1109
1110         /* PCI information */
1111         unsigned int  devfn;
1112         unsigned char bus_number;
1113         unsigned char OneG_Mode;
1114
1115         unsigned char ref_count;
1116         u8            netdev_count;
1117         u8            netdev_max;       /* from host nic address count in EEPROM */
1118         u8            port_count;
1119         u8            virtwq;
1120         u8            et_use_adaptive_rx_coalesce;
1121         u8            adapter_fcn_count;
1122         u8 pft_mcast_map[NES_PFT_SIZE];
1123 };
1124
1125 struct nes_pbl {
1126         u64              *pbl_vbase;
1127         dma_addr_t       pbl_pbase;
1128         struct page      *page;
1129         unsigned long    user_base;
1130         u32              pbl_size;
1131         struct list_head list;
1132         /* TODO: need to add list for two level tables */
1133 };
1134
1135 struct nes_listener {
1136         struct work_struct      work;
1137         struct workqueue_struct *wq;
1138         struct nes_vnic         *nesvnic;
1139         struct iw_cm_id         *cm_id;
1140         struct list_head        list;
1141         unsigned long           socket;
1142         u8                      accept_failed;
1143 };
1144
1145 struct nes_ib_device;
1146
1147 struct nes_vnic {
1148         struct nes_ib_device *nesibdev;
1149         u64 sq_full;
1150         u64 tso_requests;
1151         u64 segmented_tso_requests;
1152         u64 linearized_skbs;
1153         u64 tx_sw_dropped;
1154         u64 endnode_nstat_rx_discard;
1155         u64 endnode_nstat_rx_octets;
1156         u64 endnode_nstat_rx_frames;
1157         u64 endnode_nstat_tx_octets;
1158         u64 endnode_nstat_tx_frames;
1159         u64 endnode_ipv4_tcp_retransmits;
1160         /* void *mem; */
1161         struct nes_device *nesdev;
1162         struct net_device *netdev;
1163         struct vlan_group *vlan_grp;
1164         atomic_t          rx_skbs_needed;
1165         atomic_t          rx_skb_timer_running;
1166         int               budget;
1167         u32               msg_enable;
1168         /* u32 tx_avail; */
1169         __be32            local_ipaddr;
1170         struct napi_struct   napi;
1171         spinlock_t           tx_lock;   /* could use netdev tx lock? */
1172         struct timer_list    rq_wqes_timer;
1173         u32                  nic_mem_size;
1174         void                 *nic_vbase;
1175         dma_addr_t           nic_pbase;
1176         struct nes_hw_nic    nic;
1177         struct nes_hw_nic_cq nic_cq;
1178         u32    mcrq_qp_id;
1179         struct nes_ucontext *mcrq_ucontext;
1180         struct nes_cqp_request* (*get_cqp_request)(struct nes_device *nesdev);
1181         void (*post_cqp_request)(struct nes_device*, struct nes_cqp_request *);
1182         int (*mcrq_mcast_filter)( struct nes_vnic* nesvnic, __u8* dmi_addr );
1183         struct net_device_stats netstats;
1184         /* used to put the netdev on the adapters logical port list */
1185         struct list_head list;
1186         u16 max_frame_size;
1187         u8  netdev_open;
1188         u8  linkup;
1189         u8  logical_port;
1190         u8  netdev_index;  /* might not be needed, indexes nesdev->netdev */
1191         u8  perfect_filter_index;
1192         u8  nic_index;
1193         u8  qp_nic_index[4];
1194         u8  next_qp_nic_index;
1195         u8  of_device_registered;
1196         u8  rdma_enabled;
1197         u8  rx_checksum_disabled;
1198         u32 lro_max_aggr;
1199         struct net_lro_mgr lro_mgr;
1200         struct net_lro_desc lro_desc[NES_MAX_LRO_DESCRIPTORS];
1201 };
1202
1203 struct nes_ib_device {
1204         struct ib_device ibdev;
1205         struct nes_vnic *nesvnic;
1206
1207         /* Virtual RNIC Limits */
1208         u32 max_mr;
1209         u32 max_qp;
1210         u32 max_cq;
1211         u32 max_pd;
1212         u32 num_mr;
1213         u32 num_qp;
1214         u32 num_cq;
1215         u32 num_pd;
1216 };
1217
1218 #define nes_vlan_rx vlan_hwaccel_receive_skb
1219 #define nes_netif_rx netif_receive_skb
1220
1221 #endif          /* __NES_HW_H */