19661b2f040630bfd5dded6a63eab3e6a6de19d6
[linux-3.10.git] / drivers / infiniband / hw / cxgb3 / iwch_qp.c
1 /*
2  * Copyright (c) 2006 Chelsio, Inc. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 #include "iwch_provider.h"
33 #include "iwch.h"
34 #include "iwch_cm.h"
35 #include "cxio_hal.h"
36 #include "cxio_resource.h"
37
38 #define NO_SUPPORT -1
39
40 static int build_rdma_send(union t3_wr *wqe, struct ib_send_wr *wr,
41                                 u8 * flit_cnt)
42 {
43         int i;
44         u32 plen;
45
46         switch (wr->opcode) {
47         case IB_WR_SEND:
48                 if (wr->send_flags & IB_SEND_SOLICITED)
49                         wqe->send.rdmaop = T3_SEND_WITH_SE;
50                 else
51                         wqe->send.rdmaop = T3_SEND;
52                 wqe->send.rem_stag = 0;
53                 break;
54         case IB_WR_SEND_WITH_INV:
55                 if (wr->send_flags & IB_SEND_SOLICITED)
56                         wqe->send.rdmaop = T3_SEND_WITH_SE_INV;
57                 else
58                         wqe->send.rdmaop = T3_SEND_WITH_INV;
59                 wqe->send.rem_stag = cpu_to_be32(wr->ex.invalidate_rkey);
60                 break;
61         default:
62                 return -EINVAL;
63         }
64         if (wr->num_sge > T3_MAX_SGE)
65                 return -EINVAL;
66         wqe->send.reserved[0] = 0;
67         wqe->send.reserved[1] = 0;
68         wqe->send.reserved[2] = 0;
69         plen = 0;
70         for (i = 0; i < wr->num_sge; i++) {
71                 if ((plen + wr->sg_list[i].length) < plen)
72                         return -EMSGSIZE;
73
74                 plen += wr->sg_list[i].length;
75                 wqe->send.sgl[i].stag = cpu_to_be32(wr->sg_list[i].lkey);
76                 wqe->send.sgl[i].len = cpu_to_be32(wr->sg_list[i].length);
77                 wqe->send.sgl[i].to = cpu_to_be64(wr->sg_list[i].addr);
78         }
79         wqe->send.num_sgle = cpu_to_be32(wr->num_sge);
80         *flit_cnt = 4 + ((wr->num_sge) << 1);
81         wqe->send.plen = cpu_to_be32(plen);
82         return 0;
83 }
84
85 static int build_rdma_write(union t3_wr *wqe, struct ib_send_wr *wr,
86                                  u8 *flit_cnt)
87 {
88         int i;
89         u32 plen;
90         if (wr->num_sge > T3_MAX_SGE)
91                 return -EINVAL;
92         wqe->write.rdmaop = T3_RDMA_WRITE;
93         wqe->write.reserved[0] = 0;
94         wqe->write.reserved[1] = 0;
95         wqe->write.reserved[2] = 0;
96         wqe->write.stag_sink = cpu_to_be32(wr->wr.rdma.rkey);
97         wqe->write.to_sink = cpu_to_be64(wr->wr.rdma.remote_addr);
98
99         if (wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) {
100                 plen = 4;
101                 wqe->write.sgl[0].stag = wr->ex.imm_data;
102                 wqe->write.sgl[0].len = __constant_cpu_to_be32(0);
103                 wqe->write.num_sgle = __constant_cpu_to_be32(0);
104                 *flit_cnt = 6;
105         } else {
106                 plen = 0;
107                 for (i = 0; i < wr->num_sge; i++) {
108                         if ((plen + wr->sg_list[i].length) < plen) {
109                                 return -EMSGSIZE;
110                         }
111                         plen += wr->sg_list[i].length;
112                         wqe->write.sgl[i].stag =
113                             cpu_to_be32(wr->sg_list[i].lkey);
114                         wqe->write.sgl[i].len =
115                             cpu_to_be32(wr->sg_list[i].length);
116                         wqe->write.sgl[i].to =
117                             cpu_to_be64(wr->sg_list[i].addr);
118                 }
119                 wqe->write.num_sgle = cpu_to_be32(wr->num_sge);
120                 *flit_cnt = 5 + ((wr->num_sge) << 1);
121         }
122         wqe->write.plen = cpu_to_be32(plen);
123         return 0;
124 }
125
126 static int build_rdma_read(union t3_wr *wqe, struct ib_send_wr *wr,
127                                 u8 *flit_cnt)
128 {
129         if (wr->num_sge > 1)
130                 return -EINVAL;
131         wqe->read.rdmaop = T3_READ_REQ;
132         if (wr->opcode == IB_WR_RDMA_READ_WITH_INV)
133                 wqe->read.local_inv = 1;
134         else
135                 wqe->read.local_inv = 0;
136         wqe->read.reserved[0] = 0;
137         wqe->read.reserved[1] = 0;
138         wqe->read.rem_stag = cpu_to_be32(wr->wr.rdma.rkey);
139         wqe->read.rem_to = cpu_to_be64(wr->wr.rdma.remote_addr);
140         wqe->read.local_stag = cpu_to_be32(wr->sg_list[0].lkey);
141         wqe->read.local_len = cpu_to_be32(wr->sg_list[0].length);
142         wqe->read.local_to = cpu_to_be64(wr->sg_list[0].addr);
143         *flit_cnt = sizeof(struct t3_rdma_read_wr) >> 3;
144         return 0;
145 }
146
147 static int build_fastreg(union t3_wr *wqe, struct ib_send_wr *wr,
148                                 u8 *flit_cnt, int *wr_cnt, struct t3_wq *wq)
149 {
150         int i;
151         __be64 *p;
152
153         if (wr->wr.fast_reg.page_list_len > T3_MAX_FASTREG_DEPTH)
154                 return -EINVAL;
155         *wr_cnt = 1;
156         wqe->fastreg.stag = cpu_to_be32(wr->wr.fast_reg.rkey);
157         wqe->fastreg.len = cpu_to_be32(wr->wr.fast_reg.length);
158         wqe->fastreg.va_base_hi = cpu_to_be32(wr->wr.fast_reg.iova_start >> 32);
159         wqe->fastreg.va_base_lo_fbo =
160                                 cpu_to_be32(wr->wr.fast_reg.iova_start & 0xffffffff);
161         wqe->fastreg.page_type_perms = cpu_to_be32(
162                 V_FR_PAGE_COUNT(wr->wr.fast_reg.page_list_len) |
163                 V_FR_PAGE_SIZE(wr->wr.fast_reg.page_shift-12) |
164                 V_FR_TYPE(TPT_VATO) |
165                 V_FR_PERMS(iwch_ib_to_tpt_access(wr->wr.fast_reg.access_flags)));
166         p = &wqe->fastreg.pbl_addrs[0];
167         for (i = 0; i < wr->wr.fast_reg.page_list_len; i++, p++) {
168
169                 /* If we need a 2nd WR, then set it up */
170                 if (i == T3_MAX_FASTREG_FRAG) {
171                         *wr_cnt = 2;
172                         wqe = (union t3_wr *)(wq->queue +
173                                 Q_PTR2IDX((wq->wptr+1), wq->size_log2));
174                         build_fw_riwrh((void *)wqe, T3_WR_FASTREG, 0,
175                                Q_GENBIT(wq->wptr + 1, wq->size_log2),
176                                0, 1 + wr->wr.fast_reg.page_list_len - T3_MAX_FASTREG_FRAG,
177                                T3_EOP);
178
179                         p = &wqe->pbl_frag.pbl_addrs[0];
180                 }
181                 *p = cpu_to_be64((u64)wr->wr.fast_reg.page_list->page_list[i]);
182         }
183         *flit_cnt = 5 + wr->wr.fast_reg.page_list_len;
184         if (*flit_cnt > 15)
185                 *flit_cnt = 15;
186         return 0;
187 }
188
189 static int build_inv_stag(union t3_wr *wqe, struct ib_send_wr *wr,
190                                 u8 *flit_cnt)
191 {
192         wqe->local_inv.stag = cpu_to_be32(wr->ex.invalidate_rkey);
193         wqe->local_inv.reserved = 0;
194         *flit_cnt = sizeof(struct t3_local_inv_wr) >> 3;
195         return 0;
196 }
197
198 /*
199  * TBD: this is going to be moved to firmware. Missing pdid/qpid check for now.
200  */
201 static int iwch_sgl2pbl_map(struct iwch_dev *rhp, struct ib_sge *sg_list,
202                             u32 num_sgle, u32 * pbl_addr, u8 * page_size)
203 {
204         int i;
205         struct iwch_mr *mhp;
206         u32 offset;
207         for (i = 0; i < num_sgle; i++) {
208
209                 mhp = get_mhp(rhp, (sg_list[i].lkey) >> 8);
210                 if (!mhp) {
211                         PDBG("%s %d\n", __func__, __LINE__);
212                         return -EIO;
213                 }
214                 if (!mhp->attr.state) {
215                         PDBG("%s %d\n", __func__, __LINE__);
216                         return -EIO;
217                 }
218                 if (mhp->attr.zbva) {
219                         PDBG("%s %d\n", __func__, __LINE__);
220                         return -EIO;
221                 }
222
223                 if (sg_list[i].addr < mhp->attr.va_fbo) {
224                         PDBG("%s %d\n", __func__, __LINE__);
225                         return -EINVAL;
226                 }
227                 if (sg_list[i].addr + ((u64) sg_list[i].length) <
228                     sg_list[i].addr) {
229                         PDBG("%s %d\n", __func__, __LINE__);
230                         return -EINVAL;
231                 }
232                 if (sg_list[i].addr + ((u64) sg_list[i].length) >
233                     mhp->attr.va_fbo + ((u64) mhp->attr.len)) {
234                         PDBG("%s %d\n", __func__, __LINE__);
235                         return -EINVAL;
236                 }
237                 offset = sg_list[i].addr - mhp->attr.va_fbo;
238                 offset += ((u32) mhp->attr.va_fbo) %
239                           (1UL << (12 + mhp->attr.page_size));
240                 pbl_addr[i] = ((mhp->attr.pbl_addr -
241                                 rhp->rdev.rnic_info.pbl_base) >> 3) +
242                               (offset >> (12 + mhp->attr.page_size));
243                 page_size[i] = mhp->attr.page_size;
244         }
245         return 0;
246 }
247
248 static int build_rdma_recv(struct iwch_qp *qhp, union t3_wr *wqe,
249                                 struct ib_recv_wr *wr)
250 {
251         int i, err = 0;
252         u32 pbl_addr[T3_MAX_SGE];
253         u8 page_size[T3_MAX_SGE];
254
255         err = iwch_sgl2pbl_map(qhp->rhp, wr->sg_list, wr->num_sge, pbl_addr,
256                                page_size);
257         if (err)
258                 return err;
259         wqe->recv.pagesz[0] = page_size[0];
260         wqe->recv.pagesz[1] = page_size[1];
261         wqe->recv.pagesz[2] = page_size[2];
262         wqe->recv.pagesz[3] = page_size[3];
263         wqe->recv.num_sgle = cpu_to_be32(wr->num_sge);
264         for (i = 0; i < wr->num_sge; i++) {
265                 wqe->recv.sgl[i].stag = cpu_to_be32(wr->sg_list[i].lkey);
266                 wqe->recv.sgl[i].len = cpu_to_be32(wr->sg_list[i].length);
267
268                 /* to in the WQE == the offset into the page */
269                 wqe->recv.sgl[i].to = cpu_to_be64(((u32) wr->sg_list[i].addr) %
270                                 (1UL << (12 + page_size[i])));
271
272                 /* pbl_addr is the adapters address in the PBL */
273                 wqe->recv.pbl_addr[i] = cpu_to_be32(pbl_addr[i]);
274         }
275         for (; i < T3_MAX_SGE; i++) {
276                 wqe->recv.sgl[i].stag = 0;
277                 wqe->recv.sgl[i].len = 0;
278                 wqe->recv.sgl[i].to = 0;
279                 wqe->recv.pbl_addr[i] = 0;
280         }
281         qhp->wq.rq[Q_PTR2IDX(qhp->wq.rq_wptr,
282                              qhp->wq.rq_size_log2)].wr_id = wr->wr_id;
283         qhp->wq.rq[Q_PTR2IDX(qhp->wq.rq_wptr,
284                              qhp->wq.rq_size_log2)].pbl_addr = 0;
285         return 0;
286 }
287
288 static int build_zero_stag_recv(struct iwch_qp *qhp, union t3_wr *wqe,
289                                 struct ib_recv_wr *wr)
290 {
291         int i;
292         u32 pbl_addr;
293         u32 pbl_offset;
294
295
296         /*
297          * The T3 HW requires the PBL in the HW recv descriptor to reference
298          * a PBL entry.  So we allocate the max needed PBL memory here and pass
299          * it to the uP in the recv WR.  The uP will build the PBL and setup
300          * the HW recv descriptor.
301          */
302         pbl_addr = cxio_hal_pblpool_alloc(&qhp->rhp->rdev, T3_STAG0_PBL_SIZE);
303         if (!pbl_addr)
304                 return -ENOMEM;
305
306         /*
307          * Compute the 8B aligned offset.
308          */
309         pbl_offset = (pbl_addr - qhp->rhp->rdev.rnic_info.pbl_base) >> 3;
310
311         wqe->recv.num_sgle = cpu_to_be32(wr->num_sge);
312
313         for (i = 0; i < wr->num_sge; i++) {
314
315                 /*
316                  * Use a 128MB page size. This and an imposed 128MB
317                  * sge length limit allows us to require only a 2-entry HW
318                  * PBL for each SGE.  This restriction is acceptable since
319                  * since it is not possible to allocate 128MB of contiguous
320                  * DMA coherent memory!
321                  */
322                 if (wr->sg_list[i].length > T3_STAG0_MAX_PBE_LEN)
323                         return -EINVAL;
324                 wqe->recv.pagesz[i] = T3_STAG0_PAGE_SHIFT;
325
326                 /*
327                  * T3 restricts a recv to all zero-stag or all non-zero-stag.
328                  */
329                 if (wr->sg_list[i].lkey != 0)
330                         return -EINVAL;
331                 wqe->recv.sgl[i].stag = 0;
332                 wqe->recv.sgl[i].len = cpu_to_be32(wr->sg_list[i].length);
333                 wqe->recv.sgl[i].to = cpu_to_be64(wr->sg_list[i].addr);
334                 wqe->recv.pbl_addr[i] = cpu_to_be32(pbl_offset);
335                 pbl_offset += 2;
336         }
337         for (; i < T3_MAX_SGE; i++) {
338                 wqe->recv.pagesz[i] = 0;
339                 wqe->recv.sgl[i].stag = 0;
340                 wqe->recv.sgl[i].len = 0;
341                 wqe->recv.sgl[i].to = 0;
342                 wqe->recv.pbl_addr[i] = 0;
343         }
344         qhp->wq.rq[Q_PTR2IDX(qhp->wq.rq_wptr,
345                              qhp->wq.rq_size_log2)].wr_id = wr->wr_id;
346         qhp->wq.rq[Q_PTR2IDX(qhp->wq.rq_wptr,
347                              qhp->wq.rq_size_log2)].pbl_addr = pbl_addr;
348         return 0;
349 }
350
351 int iwch_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
352                       struct ib_send_wr **bad_wr)
353 {
354         int err = 0;
355         u8 uninitialized_var(t3_wr_flit_cnt);
356         enum t3_wr_opcode t3_wr_opcode = 0;
357         enum t3_wr_flags t3_wr_flags;
358         struct iwch_qp *qhp;
359         u32 idx;
360         union t3_wr *wqe;
361         u32 num_wrs;
362         unsigned long flag;
363         struct t3_swsq *sqp;
364         int wr_cnt = 1;
365
366         qhp = to_iwch_qp(ibqp);
367         spin_lock_irqsave(&qhp->lock, flag);
368         if (qhp->attr.state > IWCH_QP_STATE_RTS) {
369                 spin_unlock_irqrestore(&qhp->lock, flag);
370                 return -EINVAL;
371         }
372         num_wrs = Q_FREECNT(qhp->wq.sq_rptr, qhp->wq.sq_wptr,
373                   qhp->wq.sq_size_log2);
374         if (num_wrs <= 0) {
375                 spin_unlock_irqrestore(&qhp->lock, flag);
376                 return -ENOMEM;
377         }
378         while (wr) {
379                 if (num_wrs == 0) {
380                         err = -ENOMEM;
381                         *bad_wr = wr;
382                         break;
383                 }
384                 idx = Q_PTR2IDX(qhp->wq.wptr, qhp->wq.size_log2);
385                 wqe = (union t3_wr *) (qhp->wq.queue + idx);
386                 t3_wr_flags = 0;
387                 if (wr->send_flags & IB_SEND_SOLICITED)
388                         t3_wr_flags |= T3_SOLICITED_EVENT_FLAG;
389                 if (wr->send_flags & IB_SEND_SIGNALED)
390                         t3_wr_flags |= T3_COMPLETION_FLAG;
391                 sqp = qhp->wq.sq +
392                       Q_PTR2IDX(qhp->wq.sq_wptr, qhp->wq.sq_size_log2);
393                 switch (wr->opcode) {
394                 case IB_WR_SEND:
395                 case IB_WR_SEND_WITH_INV:
396                         if (wr->send_flags & IB_SEND_FENCE)
397                                 t3_wr_flags |= T3_READ_FENCE_FLAG;
398                         t3_wr_opcode = T3_WR_SEND;
399                         err = build_rdma_send(wqe, wr, &t3_wr_flit_cnt);
400                         break;
401                 case IB_WR_RDMA_WRITE:
402                 case IB_WR_RDMA_WRITE_WITH_IMM:
403                         t3_wr_opcode = T3_WR_WRITE;
404                         err = build_rdma_write(wqe, wr, &t3_wr_flit_cnt);
405                         break;
406                 case IB_WR_RDMA_READ:
407                 case IB_WR_RDMA_READ_WITH_INV:
408                         t3_wr_opcode = T3_WR_READ;
409                         t3_wr_flags = 0; /* T3 reads are always signaled */
410                         err = build_rdma_read(wqe, wr, &t3_wr_flit_cnt);
411                         if (err)
412                                 break;
413                         sqp->read_len = wqe->read.local_len;
414                         if (!qhp->wq.oldest_read)
415                                 qhp->wq.oldest_read = sqp;
416                         break;
417                 case IB_WR_FAST_REG_MR:
418                         t3_wr_opcode = T3_WR_FASTREG;
419                         err = build_fastreg(wqe, wr, &t3_wr_flit_cnt,
420                                                  &wr_cnt, &qhp->wq);
421                         break;
422                 case IB_WR_LOCAL_INV:
423                         if (wr->send_flags & IB_SEND_FENCE)
424                                 t3_wr_flags |= T3_LOCAL_FENCE_FLAG;
425                         t3_wr_opcode = T3_WR_INV_STAG;
426                         err = build_inv_stag(wqe, wr, &t3_wr_flit_cnt);
427                         break;
428                 default:
429                         PDBG("%s post of type=%d TBD!\n", __func__,
430                              wr->opcode);
431                         err = -EINVAL;
432                 }
433                 if (err) {
434                         *bad_wr = wr;
435                         break;
436                 }
437                 wqe->send.wrid.id0.hi = qhp->wq.sq_wptr;
438                 sqp->wr_id = wr->wr_id;
439                 sqp->opcode = wr2opcode(t3_wr_opcode);
440                 sqp->sq_wptr = qhp->wq.sq_wptr;
441                 sqp->complete = 0;
442                 sqp->signaled = (wr->send_flags & IB_SEND_SIGNALED);
443
444                 build_fw_riwrh((void *) wqe, t3_wr_opcode, t3_wr_flags,
445                                Q_GENBIT(qhp->wq.wptr, qhp->wq.size_log2),
446                                0, t3_wr_flit_cnt,
447                                (wr_cnt == 1) ? T3_SOPEOP : T3_SOP);
448                 PDBG("%s cookie 0x%llx wq idx 0x%x swsq idx %ld opcode %d\n",
449                      __func__, (unsigned long long) wr->wr_id, idx,
450                      Q_PTR2IDX(qhp->wq.sq_wptr, qhp->wq.sq_size_log2),
451                      sqp->opcode);
452                 wr = wr->next;
453                 num_wrs--;
454                 qhp->wq.wptr += wr_cnt;
455                 ++(qhp->wq.sq_wptr);
456         }
457         spin_unlock_irqrestore(&qhp->lock, flag);
458         ring_doorbell(qhp->wq.doorbell, qhp->wq.qpid);
459         return err;
460 }
461
462 int iwch_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
463                       struct ib_recv_wr **bad_wr)
464 {
465         int err = 0;
466         struct iwch_qp *qhp;
467         u32 idx;
468         union t3_wr *wqe;
469         u32 num_wrs;
470         unsigned long flag;
471
472         qhp = to_iwch_qp(ibqp);
473         spin_lock_irqsave(&qhp->lock, flag);
474         if (qhp->attr.state > IWCH_QP_STATE_RTS) {
475                 spin_unlock_irqrestore(&qhp->lock, flag);
476                 return -EINVAL;
477         }
478         num_wrs = Q_FREECNT(qhp->wq.rq_rptr, qhp->wq.rq_wptr,
479                             qhp->wq.rq_size_log2) - 1;
480         if (!wr) {
481                 spin_unlock_irqrestore(&qhp->lock, flag);
482                 return -EINVAL;
483         }
484         while (wr) {
485                 if (wr->num_sge > T3_MAX_SGE) {
486                         err = -EINVAL;
487                         *bad_wr = wr;
488                         break;
489                 }
490                 idx = Q_PTR2IDX(qhp->wq.wptr, qhp->wq.size_log2);
491                 wqe = (union t3_wr *) (qhp->wq.queue + idx);
492                 if (num_wrs)
493                         if (wr->sg_list[0].lkey)
494                                 err = build_rdma_recv(qhp, wqe, wr);
495                         else
496                                 err = build_zero_stag_recv(qhp, wqe, wr);
497                 else
498                         err = -ENOMEM;
499                 if (err) {
500                         *bad_wr = wr;
501                         break;
502                 }
503                 build_fw_riwrh((void *) wqe, T3_WR_RCV, T3_COMPLETION_FLAG,
504                                Q_GENBIT(qhp->wq.wptr, qhp->wq.size_log2),
505                                0, sizeof(struct t3_receive_wr) >> 3, T3_SOPEOP);
506                 PDBG("%s cookie 0x%llx idx 0x%x rq_wptr 0x%x rw_rptr 0x%x "
507                      "wqe %p \n", __func__, (unsigned long long) wr->wr_id,
508                      idx, qhp->wq.rq_wptr, qhp->wq.rq_rptr, wqe);
509                 ++(qhp->wq.rq_wptr);
510                 ++(qhp->wq.wptr);
511                 wr = wr->next;
512                 num_wrs--;
513         }
514         spin_unlock_irqrestore(&qhp->lock, flag);
515         ring_doorbell(qhp->wq.doorbell, qhp->wq.qpid);
516         return err;
517 }
518
519 int iwch_bind_mw(struct ib_qp *qp,
520                              struct ib_mw *mw,
521                              struct ib_mw_bind *mw_bind)
522 {
523         struct iwch_dev *rhp;
524         struct iwch_mw *mhp;
525         struct iwch_qp *qhp;
526         union t3_wr *wqe;
527         u32 pbl_addr;
528         u8 page_size;
529         u32 num_wrs;
530         unsigned long flag;
531         struct ib_sge sgl;
532         int err=0;
533         enum t3_wr_flags t3_wr_flags;
534         u32 idx;
535         struct t3_swsq *sqp;
536
537         qhp = to_iwch_qp(qp);
538         mhp = to_iwch_mw(mw);
539         rhp = qhp->rhp;
540
541         spin_lock_irqsave(&qhp->lock, flag);
542         if (qhp->attr.state > IWCH_QP_STATE_RTS) {
543                 spin_unlock_irqrestore(&qhp->lock, flag);
544                 return -EINVAL;
545         }
546         num_wrs = Q_FREECNT(qhp->wq.sq_rptr, qhp->wq.sq_wptr,
547                             qhp->wq.sq_size_log2);
548         if ((num_wrs) <= 0) {
549                 spin_unlock_irqrestore(&qhp->lock, flag);
550                 return -ENOMEM;
551         }
552         idx = Q_PTR2IDX(qhp->wq.wptr, qhp->wq.size_log2);
553         PDBG("%s: idx 0x%0x, mw 0x%p, mw_bind 0x%p\n", __func__, idx,
554              mw, mw_bind);
555         wqe = (union t3_wr *) (qhp->wq.queue + idx);
556
557         t3_wr_flags = 0;
558         if (mw_bind->send_flags & IB_SEND_SIGNALED)
559                 t3_wr_flags = T3_COMPLETION_FLAG;
560
561         sgl.addr = mw_bind->addr;
562         sgl.lkey = mw_bind->mr->lkey;
563         sgl.length = mw_bind->length;
564         wqe->bind.reserved = 0;
565         wqe->bind.type = TPT_VATO;
566
567         /* TBD: check perms */
568         wqe->bind.perms = iwch_ib_to_tpt_bind_access(mw_bind->mw_access_flags);
569         wqe->bind.mr_stag = cpu_to_be32(mw_bind->mr->lkey);
570         wqe->bind.mw_stag = cpu_to_be32(mw->rkey);
571         wqe->bind.mw_len = cpu_to_be32(mw_bind->length);
572         wqe->bind.mw_va = cpu_to_be64(mw_bind->addr);
573         err = iwch_sgl2pbl_map(rhp, &sgl, 1, &pbl_addr, &page_size);
574         if (err) {
575                 spin_unlock_irqrestore(&qhp->lock, flag);
576                 return err;
577         }
578         wqe->send.wrid.id0.hi = qhp->wq.sq_wptr;
579         sqp = qhp->wq.sq + Q_PTR2IDX(qhp->wq.sq_wptr, qhp->wq.sq_size_log2);
580         sqp->wr_id = mw_bind->wr_id;
581         sqp->opcode = T3_BIND_MW;
582         sqp->sq_wptr = qhp->wq.sq_wptr;
583         sqp->complete = 0;
584         sqp->signaled = (mw_bind->send_flags & IB_SEND_SIGNALED);
585         wqe->bind.mr_pbl_addr = cpu_to_be32(pbl_addr);
586         wqe->bind.mr_pagesz = page_size;
587         build_fw_riwrh((void *)wqe, T3_WR_BIND, t3_wr_flags,
588                        Q_GENBIT(qhp->wq.wptr, qhp->wq.size_log2), 0,
589                        sizeof(struct t3_bind_mw_wr) >> 3, T3_SOPEOP);
590         ++(qhp->wq.wptr);
591         ++(qhp->wq.sq_wptr);
592         spin_unlock_irqrestore(&qhp->lock, flag);
593
594         ring_doorbell(qhp->wq.doorbell, qhp->wq.qpid);
595
596         return err;
597 }
598
599 static inline void build_term_codes(struct respQ_msg_t *rsp_msg,
600                                     u8 *layer_type, u8 *ecode)
601 {
602         int status = TPT_ERR_INTERNAL_ERR;
603         int tagged = 0;
604         int opcode = -1;
605         int rqtype = 0;
606         int send_inv = 0;
607
608         if (rsp_msg) {
609                 status = CQE_STATUS(rsp_msg->cqe);
610                 opcode = CQE_OPCODE(rsp_msg->cqe);
611                 rqtype = RQ_TYPE(rsp_msg->cqe);
612                 send_inv = (opcode == T3_SEND_WITH_INV) ||
613                            (opcode == T3_SEND_WITH_SE_INV);
614                 tagged = (opcode == T3_RDMA_WRITE) ||
615                          (rqtype && (opcode == T3_READ_RESP));
616         }
617
618         switch (status) {
619         case TPT_ERR_STAG:
620                 if (send_inv) {
621                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
622                         *ecode = RDMAP_CANT_INV_STAG;
623                 } else {
624                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
625                         *ecode = RDMAP_INV_STAG;
626                 }
627                 break;
628         case TPT_ERR_PDID:
629                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
630                 if ((opcode == T3_SEND_WITH_INV) ||
631                     (opcode == T3_SEND_WITH_SE_INV))
632                         *ecode = RDMAP_CANT_INV_STAG;
633                 else
634                         *ecode = RDMAP_STAG_NOT_ASSOC;
635                 break;
636         case TPT_ERR_QPID:
637                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
638                 *ecode = RDMAP_STAG_NOT_ASSOC;
639                 break;
640         case TPT_ERR_ACCESS:
641                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
642                 *ecode = RDMAP_ACC_VIOL;
643                 break;
644         case TPT_ERR_WRAP:
645                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
646                 *ecode = RDMAP_TO_WRAP;
647                 break;
648         case TPT_ERR_BOUND:
649                 if (tagged) {
650                         *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
651                         *ecode = DDPT_BASE_BOUNDS;
652                 } else {
653                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
654                         *ecode = RDMAP_BASE_BOUNDS;
655                 }
656                 break;
657         case TPT_ERR_INVALIDATE_SHARED_MR:
658         case TPT_ERR_INVALIDATE_MR_WITH_MW_BOUND:
659                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
660                 *ecode = RDMAP_CANT_INV_STAG;
661                 break;
662         case TPT_ERR_ECC:
663         case TPT_ERR_ECC_PSTAG:
664         case TPT_ERR_INTERNAL_ERR:
665                 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
666                 *ecode = 0;
667                 break;
668         case TPT_ERR_OUT_OF_RQE:
669                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
670                 *ecode = DDPU_INV_MSN_NOBUF;
671                 break;
672         case TPT_ERR_PBL_ADDR_BOUND:
673                 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
674                 *ecode = DDPT_BASE_BOUNDS;
675                 break;
676         case TPT_ERR_CRC:
677                 *layer_type = LAYER_MPA|DDP_LLP;
678                 *ecode = MPA_CRC_ERR;
679                 break;
680         case TPT_ERR_MARKER:
681                 *layer_type = LAYER_MPA|DDP_LLP;
682                 *ecode = MPA_MARKER_ERR;
683                 break;
684         case TPT_ERR_PDU_LEN_ERR:
685                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
686                 *ecode = DDPU_MSG_TOOBIG;
687                 break;
688         case TPT_ERR_DDP_VERSION:
689                 if (tagged) {
690                         *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
691                         *ecode = DDPT_INV_VERS;
692                 } else {
693                         *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
694                         *ecode = DDPU_INV_VERS;
695                 }
696                 break;
697         case TPT_ERR_RDMA_VERSION:
698                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
699                 *ecode = RDMAP_INV_VERS;
700                 break;
701         case TPT_ERR_OPCODE:
702                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
703                 *ecode = RDMAP_INV_OPCODE;
704                 break;
705         case TPT_ERR_DDP_QUEUE_NUM:
706                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
707                 *ecode = DDPU_INV_QN;
708                 break;
709         case TPT_ERR_MSN:
710         case TPT_ERR_MSN_GAP:
711         case TPT_ERR_MSN_RANGE:
712         case TPT_ERR_IRD_OVERFLOW:
713                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
714                 *ecode = DDPU_INV_MSN_RANGE;
715                 break;
716         case TPT_ERR_TBIT:
717                 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
718                 *ecode = 0;
719                 break;
720         case TPT_ERR_MO:
721                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
722                 *ecode = DDPU_INV_MO;
723                 break;
724         default:
725                 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
726                 *ecode = 0;
727                 break;
728         }
729 }
730
731 int iwch_post_zb_read(struct iwch_qp *qhp)
732 {
733         union t3_wr *wqe;
734         struct sk_buff *skb;
735         u8 flit_cnt = sizeof(struct t3_rdma_read_wr) >> 3;
736
737         PDBG("%s enter\n", __func__);
738         skb = alloc_skb(40, GFP_KERNEL);
739         if (!skb) {
740                 printk(KERN_ERR "%s cannot send zb_read!!\n", __func__);
741                 return -ENOMEM;
742         }
743         wqe = (union t3_wr *)skb_put(skb, sizeof(struct t3_rdma_read_wr));
744         memset(wqe, 0, sizeof(struct t3_rdma_read_wr));
745         wqe->read.rdmaop = T3_READ_REQ;
746         wqe->read.reserved[0] = 0;
747         wqe->read.reserved[1] = 0;
748         wqe->read.rem_stag = cpu_to_be32(1);
749         wqe->read.rem_to = cpu_to_be64(1);
750         wqe->read.local_stag = cpu_to_be32(1);
751         wqe->read.local_len = cpu_to_be32(0);
752         wqe->read.local_to = cpu_to_be64(1);
753         wqe->send.wrh.op_seop_flags = cpu_to_be32(V_FW_RIWR_OP(T3_WR_READ));
754         wqe->send.wrh.gen_tid_len = cpu_to_be32(V_FW_RIWR_TID(qhp->ep->hwtid)|
755                                                 V_FW_RIWR_LEN(flit_cnt));
756         skb->priority = CPL_PRIORITY_DATA;
757         return cxgb3_ofld_send(qhp->rhp->rdev.t3cdev_p, skb);
758 }
759
760 /*
761  * This posts a TERMINATE with layer=RDMA, type=catastrophic.
762  */
763 int iwch_post_terminate(struct iwch_qp *qhp, struct respQ_msg_t *rsp_msg)
764 {
765         union t3_wr *wqe;
766         struct terminate_message *term;
767         struct sk_buff *skb;
768
769         PDBG("%s %d\n", __func__, __LINE__);
770         skb = alloc_skb(40, GFP_ATOMIC);
771         if (!skb) {
772                 printk(KERN_ERR "%s cannot send TERMINATE!\n", __func__);
773                 return -ENOMEM;
774         }
775         wqe = (union t3_wr *)skb_put(skb, 40);
776         memset(wqe, 0, 40);
777         wqe->send.rdmaop = T3_TERMINATE;
778
779         /* immediate data length */
780         wqe->send.plen = htonl(4);
781
782         /* immediate data starts here. */
783         term = (struct terminate_message *)wqe->send.sgl;
784         build_term_codes(rsp_msg, &term->layer_etype, &term->ecode);
785         wqe->send.wrh.op_seop_flags = cpu_to_be32(V_FW_RIWR_OP(T3_WR_SEND) |
786                          V_FW_RIWR_FLAGS(T3_COMPLETION_FLAG | T3_NOTIFY_FLAG));
787         wqe->send.wrh.gen_tid_len = cpu_to_be32(V_FW_RIWR_TID(qhp->ep->hwtid));
788         skb->priority = CPL_PRIORITY_DATA;
789         return cxgb3_ofld_send(qhp->rhp->rdev.t3cdev_p, skb);
790 }
791
792 /*
793  * Assumes qhp lock is held.
794  */
795 static void __flush_qp(struct iwch_qp *qhp, unsigned long *flag)
796 {
797         struct iwch_cq *rchp, *schp;
798         int count;
799         int flushed;
800
801         rchp = get_chp(qhp->rhp, qhp->attr.rcq);
802         schp = get_chp(qhp->rhp, qhp->attr.scq);
803
804         PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp);
805         /* take a ref on the qhp since we must release the lock */
806         atomic_inc(&qhp->refcnt);
807         spin_unlock_irqrestore(&qhp->lock, *flag);
808
809         /* locking heirarchy: cq lock first, then qp lock. */
810         spin_lock_irqsave(&rchp->lock, *flag);
811         spin_lock(&qhp->lock);
812         cxio_flush_hw_cq(&rchp->cq);
813         cxio_count_rcqes(&rchp->cq, &qhp->wq, &count);
814         flushed = cxio_flush_rq(&qhp->wq, &rchp->cq, count);
815         spin_unlock(&qhp->lock);
816         spin_unlock_irqrestore(&rchp->lock, *flag);
817         if (flushed)
818                 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
819
820         /* locking heirarchy: cq lock first, then qp lock. */
821         spin_lock_irqsave(&schp->lock, *flag);
822         spin_lock(&qhp->lock);
823         cxio_flush_hw_cq(&schp->cq);
824         cxio_count_scqes(&schp->cq, &qhp->wq, &count);
825         flushed = cxio_flush_sq(&qhp->wq, &schp->cq, count);
826         spin_unlock(&qhp->lock);
827         spin_unlock_irqrestore(&schp->lock, *flag);
828         if (flushed)
829                 (*schp->ibcq.comp_handler)(&schp->ibcq, schp->ibcq.cq_context);
830
831         /* deref */
832         if (atomic_dec_and_test(&qhp->refcnt))
833                 wake_up(&qhp->wait);
834
835         spin_lock_irqsave(&qhp->lock, *flag);
836 }
837
838 static void flush_qp(struct iwch_qp *qhp, unsigned long *flag)
839 {
840         if (qhp->ibqp.uobject)
841                 cxio_set_wq_in_error(&qhp->wq);
842         else
843                 __flush_qp(qhp, flag);
844 }
845
846
847 /*
848  * Return count of RECV WRs posted
849  */
850 u16 iwch_rqes_posted(struct iwch_qp *qhp)
851 {
852         union t3_wr *wqe = qhp->wq.queue;
853         u16 count = 0;
854         while ((count+1) != 0 && fw_riwrh_opcode((struct fw_riwrh *)wqe) == T3_WR_RCV) {
855                 count++;
856                 wqe++;
857         }
858         PDBG("%s qhp %p count %u\n", __func__, qhp, count);
859         return count;
860 }
861
862 static int rdma_init(struct iwch_dev *rhp, struct iwch_qp *qhp,
863                                 enum iwch_qp_attr_mask mask,
864                                 struct iwch_qp_attributes *attrs)
865 {
866         struct t3_rdma_init_attr init_attr;
867         int ret;
868
869         init_attr.tid = qhp->ep->hwtid;
870         init_attr.qpid = qhp->wq.qpid;
871         init_attr.pdid = qhp->attr.pd;
872         init_attr.scqid = qhp->attr.scq;
873         init_attr.rcqid = qhp->attr.rcq;
874         init_attr.rq_addr = qhp->wq.rq_addr;
875         init_attr.rq_size = 1 << qhp->wq.rq_size_log2;
876         init_attr.mpaattrs = uP_RI_MPA_IETF_ENABLE |
877                 qhp->attr.mpa_attr.recv_marker_enabled |
878                 (qhp->attr.mpa_attr.xmit_marker_enabled << 1) |
879                 (qhp->attr.mpa_attr.crc_enabled << 2);
880
881         init_attr.qpcaps = uP_RI_QP_RDMA_READ_ENABLE |
882                            uP_RI_QP_RDMA_WRITE_ENABLE |
883                            uP_RI_QP_BIND_ENABLE;
884         if (!qhp->ibqp.uobject)
885                 init_attr.qpcaps |= uP_RI_QP_STAG0_ENABLE |
886                                     uP_RI_QP_FAST_REGISTER_ENABLE;
887
888         init_attr.tcp_emss = qhp->ep->emss;
889         init_attr.ord = qhp->attr.max_ord;
890         init_attr.ird = qhp->attr.max_ird;
891         init_attr.qp_dma_addr = qhp->wq.dma_addr;
892         init_attr.qp_dma_size = (1UL << qhp->wq.size_log2);
893         init_attr.rqe_count = iwch_rqes_posted(qhp);
894         init_attr.flags = qhp->attr.mpa_attr.initiator ? MPA_INITIATOR : 0;
895         if (peer2peer) {
896                 init_attr.rtr_type = RTR_READ;
897                 if (init_attr.ord == 0 && qhp->attr.mpa_attr.initiator)
898                         init_attr.ord = 1;
899                 if (init_attr.ird == 0 && !qhp->attr.mpa_attr.initiator)
900                         init_attr.ird = 1;
901         } else
902                 init_attr.rtr_type = 0;
903         init_attr.irs = qhp->ep->rcv_seq;
904         PDBG("%s init_attr.rq_addr 0x%x init_attr.rq_size = %d "
905              "flags 0x%x qpcaps 0x%x\n", __func__,
906              init_attr.rq_addr, init_attr.rq_size,
907              init_attr.flags, init_attr.qpcaps);
908         ret = cxio_rdma_init(&rhp->rdev, &init_attr);
909         PDBG("%s ret %d\n", __func__, ret);
910         return ret;
911 }
912
913 int iwch_modify_qp(struct iwch_dev *rhp, struct iwch_qp *qhp,
914                                 enum iwch_qp_attr_mask mask,
915                                 struct iwch_qp_attributes *attrs,
916                                 int internal)
917 {
918         int ret = 0;
919         struct iwch_qp_attributes newattr = qhp->attr;
920         unsigned long flag;
921         int disconnect = 0;
922         int terminate = 0;
923         int abort = 0;
924         int free = 0;
925         struct iwch_ep *ep = NULL;
926
927         PDBG("%s qhp %p qpid 0x%x ep %p state %d -> %d\n", __func__,
928              qhp, qhp->wq.qpid, qhp->ep, qhp->attr.state,
929              (mask & IWCH_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
930
931         spin_lock_irqsave(&qhp->lock, flag);
932
933         /* Process attr changes if in IDLE */
934         if (mask & IWCH_QP_ATTR_VALID_MODIFY) {
935                 if (qhp->attr.state != IWCH_QP_STATE_IDLE) {
936                         ret = -EIO;
937                         goto out;
938                 }
939                 if (mask & IWCH_QP_ATTR_ENABLE_RDMA_READ)
940                         newattr.enable_rdma_read = attrs->enable_rdma_read;
941                 if (mask & IWCH_QP_ATTR_ENABLE_RDMA_WRITE)
942                         newattr.enable_rdma_write = attrs->enable_rdma_write;
943                 if (mask & IWCH_QP_ATTR_ENABLE_RDMA_BIND)
944                         newattr.enable_bind = attrs->enable_bind;
945                 if (mask & IWCH_QP_ATTR_MAX_ORD) {
946                         if (attrs->max_ord >
947                             rhp->attr.max_rdma_read_qp_depth) {
948                                 ret = -EINVAL;
949                                 goto out;
950                         }
951                         newattr.max_ord = attrs->max_ord;
952                 }
953                 if (mask & IWCH_QP_ATTR_MAX_IRD) {
954                         if (attrs->max_ird >
955                             rhp->attr.max_rdma_reads_per_qp) {
956                                 ret = -EINVAL;
957                                 goto out;
958                         }
959                         newattr.max_ird = attrs->max_ird;
960                 }
961                 qhp->attr = newattr;
962         }
963
964         if (!(mask & IWCH_QP_ATTR_NEXT_STATE))
965                 goto out;
966         if (qhp->attr.state == attrs->next_state)
967                 goto out;
968
969         switch (qhp->attr.state) {
970         case IWCH_QP_STATE_IDLE:
971                 switch (attrs->next_state) {
972                 case IWCH_QP_STATE_RTS:
973                         if (!(mask & IWCH_QP_ATTR_LLP_STREAM_HANDLE)) {
974                                 ret = -EINVAL;
975                                 goto out;
976                         }
977                         if (!(mask & IWCH_QP_ATTR_MPA_ATTR)) {
978                                 ret = -EINVAL;
979                                 goto out;
980                         }
981                         qhp->attr.mpa_attr = attrs->mpa_attr;
982                         qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
983                         qhp->ep = qhp->attr.llp_stream_handle;
984                         qhp->attr.state = IWCH_QP_STATE_RTS;
985
986                         /*
987                          * Ref the endpoint here and deref when we
988                          * disassociate the endpoint from the QP.  This
989                          * happens in CLOSING->IDLE transition or *->ERROR
990                          * transition.
991                          */
992                         get_ep(&qhp->ep->com);
993                         spin_unlock_irqrestore(&qhp->lock, flag);
994                         ret = rdma_init(rhp, qhp, mask, attrs);
995                         spin_lock_irqsave(&qhp->lock, flag);
996                         if (ret)
997                                 goto err;
998                         break;
999                 case IWCH_QP_STATE_ERROR:
1000                         qhp->attr.state = IWCH_QP_STATE_ERROR;
1001                         flush_qp(qhp, &flag);
1002                         break;
1003                 default:
1004                         ret = -EINVAL;
1005                         goto out;
1006                 }
1007                 break;
1008         case IWCH_QP_STATE_RTS:
1009                 switch (attrs->next_state) {
1010                 case IWCH_QP_STATE_CLOSING:
1011                         BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2);
1012                         qhp->attr.state = IWCH_QP_STATE_CLOSING;
1013                         if (!internal) {
1014                                 abort=0;
1015                                 disconnect = 1;
1016                                 ep = qhp->ep;
1017                                 get_ep(&ep->com);
1018                         }
1019                         break;
1020                 case IWCH_QP_STATE_TERMINATE:
1021                         qhp->attr.state = IWCH_QP_STATE_TERMINATE;
1022                         if (qhp->ibqp.uobject)
1023                                 cxio_set_wq_in_error(&qhp->wq);
1024                         if (!internal)
1025                                 terminate = 1;
1026                         break;
1027                 case IWCH_QP_STATE_ERROR:
1028                         qhp->attr.state = IWCH_QP_STATE_ERROR;
1029                         if (!internal) {
1030                                 abort=1;
1031                                 disconnect = 1;
1032                                 ep = qhp->ep;
1033                                 get_ep(&ep->com);
1034                         }
1035                         goto err;
1036                         break;
1037                 default:
1038                         ret = -EINVAL;
1039                         goto out;
1040                 }
1041                 break;
1042         case IWCH_QP_STATE_CLOSING:
1043                 if (!internal) {
1044                         ret = -EINVAL;
1045                         goto out;
1046                 }
1047                 switch (attrs->next_state) {
1048                         case IWCH_QP_STATE_IDLE:
1049                                 flush_qp(qhp, &flag);
1050                                 qhp->attr.state = IWCH_QP_STATE_IDLE;
1051                                 qhp->attr.llp_stream_handle = NULL;
1052                                 put_ep(&qhp->ep->com);
1053                                 qhp->ep = NULL;
1054                                 wake_up(&qhp->wait);
1055                                 break;
1056                         case IWCH_QP_STATE_ERROR:
1057                                 goto err;
1058                         default:
1059                                 ret = -EINVAL;
1060                                 goto err;
1061                 }
1062                 break;
1063         case IWCH_QP_STATE_ERROR:
1064                 if (attrs->next_state != IWCH_QP_STATE_IDLE) {
1065                         ret = -EINVAL;
1066                         goto out;
1067                 }
1068
1069                 if (!Q_EMPTY(qhp->wq.sq_rptr, qhp->wq.sq_wptr) ||
1070                     !Q_EMPTY(qhp->wq.rq_rptr, qhp->wq.rq_wptr)) {
1071                         ret = -EINVAL;
1072                         goto out;
1073                 }
1074                 qhp->attr.state = IWCH_QP_STATE_IDLE;
1075                 memset(&qhp->attr, 0, sizeof(qhp->attr));
1076                 break;
1077         case IWCH_QP_STATE_TERMINATE:
1078                 if (!internal) {
1079                         ret = -EINVAL;
1080                         goto out;
1081                 }
1082                 goto err;
1083                 break;
1084         default:
1085                 printk(KERN_ERR "%s in a bad state %d\n",
1086                        __func__, qhp->attr.state);
1087                 ret = -EINVAL;
1088                 goto err;
1089                 break;
1090         }
1091         goto out;
1092 err:
1093         PDBG("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep,
1094              qhp->wq.qpid);
1095
1096         /* disassociate the LLP connection */
1097         qhp->attr.llp_stream_handle = NULL;
1098         ep = qhp->ep;
1099         qhp->ep = NULL;
1100         qhp->attr.state = IWCH_QP_STATE_ERROR;
1101         free=1;
1102         wake_up(&qhp->wait);
1103         BUG_ON(!ep);
1104         flush_qp(qhp, &flag);
1105 out:
1106         spin_unlock_irqrestore(&qhp->lock, flag);
1107
1108         if (terminate)
1109                 iwch_post_terminate(qhp, NULL);
1110
1111         /*
1112          * If disconnect is 1, then we need to initiate a disconnect
1113          * on the EP.  This can be a normal close (RTS->CLOSING) or
1114          * an abnormal close (RTS/CLOSING->ERROR).
1115          */
1116         if (disconnect) {
1117                 iwch_ep_disconnect(ep, abort, GFP_KERNEL);
1118                 put_ep(&ep->com);
1119         }
1120
1121         /*
1122          * If free is 1, then we've disassociated the EP from the QP
1123          * and we need to dereference the EP.
1124          */
1125         if (free)
1126                 put_ep(&ep->com);
1127
1128         PDBG("%s exit state %d\n", __func__, qhp->attr.state);
1129         return ret;
1130 }
1131
1132 static int quiesce_qp(struct iwch_qp *qhp)
1133 {
1134         spin_lock_irq(&qhp->lock);
1135         iwch_quiesce_tid(qhp->ep);
1136         qhp->flags |= QP_QUIESCED;
1137         spin_unlock_irq(&qhp->lock);
1138         return 0;
1139 }
1140
1141 static int resume_qp(struct iwch_qp *qhp)
1142 {
1143         spin_lock_irq(&qhp->lock);
1144         iwch_resume_tid(qhp->ep);
1145         qhp->flags &= ~QP_QUIESCED;
1146         spin_unlock_irq(&qhp->lock);
1147         return 0;
1148 }
1149
1150 int iwch_quiesce_qps(struct iwch_cq *chp)
1151 {
1152         int i;
1153         struct iwch_qp *qhp;
1154
1155         for (i=0; i < T3_MAX_NUM_QP; i++) {
1156                 qhp = get_qhp(chp->rhp, i);
1157                 if (!qhp)
1158                         continue;
1159                 if ((qhp->attr.rcq == chp->cq.cqid) && !qp_quiesced(qhp)) {
1160                         quiesce_qp(qhp);
1161                         continue;
1162                 }
1163                 if ((qhp->attr.scq == chp->cq.cqid) && !qp_quiesced(qhp))
1164                         quiesce_qp(qhp);
1165         }
1166         return 0;
1167 }
1168
1169 int iwch_resume_qps(struct iwch_cq *chp)
1170 {
1171         int i;
1172         struct iwch_qp *qhp;
1173
1174         for (i=0; i < T3_MAX_NUM_QP; i++) {
1175                 qhp = get_qhp(chp->rhp, i);
1176                 if (!qhp)
1177                         continue;
1178                 if ((qhp->attr.rcq == chp->cq.cqid) && qp_quiesced(qhp)) {
1179                         resume_qp(qhp);
1180                         continue;
1181                 }
1182                 if ((qhp->attr.scq == chp->cq.cqid) && qp_quiesced(qhp))
1183                         resume_qp(qhp);
1184         }
1185         return 0;
1186 }