RDMA/cxgb3: Enforce required firmware
[linux-3.10.git] / drivers / infiniband / hw / cxgb3 / cxio_hal.c
1 /*
2  * Copyright (c) 2006 Chelsio, Inc. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 #include <asm/delay.h>
33
34 #include <linux/mutex.h>
35 #include <linux/netdevice.h>
36 #include <linux/sched.h>
37 #include <linux/spinlock.h>
38 #include <linux/pci.h>
39 #include <linux/dma-mapping.h>
40 #include <net/net_namespace.h>
41
42 #include "cxio_resource.h"
43 #include "cxio_hal.h"
44 #include "cxgb3_offload.h"
45 #include "sge_defs.h"
46
47 static LIST_HEAD(rdev_list);
48 static cxio_hal_ev_callback_func_t cxio_ev_cb = NULL;
49
50 static struct cxio_rdev *cxio_hal_find_rdev_by_name(char *dev_name)
51 {
52         struct cxio_rdev *rdev;
53
54         list_for_each_entry(rdev, &rdev_list, entry)
55                 if (!strcmp(rdev->dev_name, dev_name))
56                         return rdev;
57         return NULL;
58 }
59
60 static struct cxio_rdev *cxio_hal_find_rdev_by_t3cdev(struct t3cdev *tdev)
61 {
62         struct cxio_rdev *rdev;
63
64         list_for_each_entry(rdev, &rdev_list, entry)
65                 if (rdev->t3cdev_p == tdev)
66                         return rdev;
67         return NULL;
68 }
69
70 int cxio_hal_cq_op(struct cxio_rdev *rdev_p, struct t3_cq *cq,
71                    enum t3_cq_opcode op, u32 credit)
72 {
73         int ret;
74         struct t3_cqe *cqe;
75         u32 rptr;
76
77         struct rdma_cq_op setup;
78         setup.id = cq->cqid;
79         setup.credits = (op == CQ_CREDIT_UPDATE) ? credit : 0;
80         setup.op = op;
81         ret = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_OP, &setup);
82
83         if ((ret < 0) || (op == CQ_CREDIT_UPDATE))
84                 return ret;
85
86         /*
87          * If the rearm returned an index other than our current index,
88          * then there might be CQE's in flight (being DMA'd).  We must wait
89          * here for them to complete or the consumer can miss a notification.
90          */
91         if (Q_PTR2IDX((cq->rptr), cq->size_log2) != ret) {
92                 int i=0;
93
94                 rptr = cq->rptr;
95
96                 /*
97                  * Keep the generation correct by bumping rptr until it
98                  * matches the index returned by the rearm - 1.
99                  */
100                 while (Q_PTR2IDX((rptr+1), cq->size_log2) != ret)
101                         rptr++;
102
103                 /*
104                  * Now rptr is the index for the (last) cqe that was
105                  * in-flight at the time the HW rearmed the CQ.  We
106                  * spin until that CQE is valid.
107                  */
108                 cqe = cq->queue + Q_PTR2IDX(rptr, cq->size_log2);
109                 while (!CQ_VLD_ENTRY(rptr, cq->size_log2, cqe)) {
110                         udelay(1);
111                         if (i++ > 1000000) {
112                                 BUG_ON(1);
113                                 printk(KERN_ERR "%s: stalled rnic\n",
114                                        rdev_p->dev_name);
115                                 return -EIO;
116                         }
117                 }
118
119                 return 1;
120         }
121
122         return 0;
123 }
124
125 static int cxio_hal_clear_cq_ctx(struct cxio_rdev *rdev_p, u32 cqid)
126 {
127         struct rdma_cq_setup setup;
128         setup.id = cqid;
129         setup.base_addr = 0;    /* NULL address */
130         setup.size = 0;         /* disaable the CQ */
131         setup.credits = 0;
132         setup.credit_thres = 0;
133         setup.ovfl_mode = 0;
134         return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
135 }
136
137 static int cxio_hal_clear_qp_ctx(struct cxio_rdev *rdev_p, u32 qpid)
138 {
139         u64 sge_cmd;
140         struct t3_modify_qp_wr *wqe;
141         struct sk_buff *skb = alloc_skb(sizeof(*wqe), GFP_KERNEL);
142         if (!skb) {
143                 PDBG("%s alloc_skb failed\n", __func__);
144                 return -ENOMEM;
145         }
146         wqe = (struct t3_modify_qp_wr *) skb_put(skb, sizeof(*wqe));
147         memset(wqe, 0, sizeof(*wqe));
148         build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_QP_MOD,
149                        T3_COMPLETION_FLAG | T3_NOTIFY_FLAG, 0, qpid, 7,
150                        T3_SOPEOP);
151         wqe->flags = cpu_to_be32(MODQP_WRITE_EC);
152         sge_cmd = qpid << 8 | 3;
153         wqe->sge_cmd = cpu_to_be64(sge_cmd);
154         skb->priority = CPL_PRIORITY_CONTROL;
155         return (cxgb3_ofld_send(rdev_p->t3cdev_p, skb));
156 }
157
158 int cxio_create_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq)
159 {
160         struct rdma_cq_setup setup;
161         int size = (1UL << (cq->size_log2)) * sizeof(struct t3_cqe);
162
163         cq->cqid = cxio_hal_get_cqid(rdev_p->rscp);
164         if (!cq->cqid)
165                 return -ENOMEM;
166         cq->sw_queue = kzalloc(size, GFP_KERNEL);
167         if (!cq->sw_queue)
168                 return -ENOMEM;
169         cq->queue = dma_alloc_coherent(&(rdev_p->rnic_info.pdev->dev),
170                                              (1UL << (cq->size_log2)) *
171                                              sizeof(struct t3_cqe),
172                                              &(cq->dma_addr), GFP_KERNEL);
173         if (!cq->queue) {
174                 kfree(cq->sw_queue);
175                 return -ENOMEM;
176         }
177         pci_unmap_addr_set(cq, mapping, cq->dma_addr);
178         memset(cq->queue, 0, size);
179         setup.id = cq->cqid;
180         setup.base_addr = (u64) (cq->dma_addr);
181         setup.size = 1UL << cq->size_log2;
182         setup.credits = 65535;
183         setup.credit_thres = 1;
184         if (rdev_p->t3cdev_p->type != T3A)
185                 setup.ovfl_mode = 0;
186         else
187                 setup.ovfl_mode = 1;
188         return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
189 }
190
191 int cxio_resize_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq)
192 {
193         struct rdma_cq_setup setup;
194         setup.id = cq->cqid;
195         setup.base_addr = (u64) (cq->dma_addr);
196         setup.size = 1UL << cq->size_log2;
197         setup.credits = setup.size;
198         setup.credit_thres = setup.size;        /* TBD: overflow recovery */
199         setup.ovfl_mode = 1;
200         return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
201 }
202
203 static u32 get_qpid(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
204 {
205         struct cxio_qpid_list *entry;
206         u32 qpid;
207         int i;
208
209         mutex_lock(&uctx->lock);
210         if (!list_empty(&uctx->qpids)) {
211                 entry = list_entry(uctx->qpids.next, struct cxio_qpid_list,
212                                    entry);
213                 list_del(&entry->entry);
214                 qpid = entry->qpid;
215                 kfree(entry);
216         } else {
217                 qpid = cxio_hal_get_qpid(rdev_p->rscp);
218                 if (!qpid)
219                         goto out;
220                 for (i = qpid+1; i & rdev_p->qpmask; i++) {
221                         entry = kmalloc(sizeof *entry, GFP_KERNEL);
222                         if (!entry)
223                                 break;
224                         entry->qpid = i;
225                         list_add_tail(&entry->entry, &uctx->qpids);
226                 }
227         }
228 out:
229         mutex_unlock(&uctx->lock);
230         PDBG("%s qpid 0x%x\n", __func__, qpid);
231         return qpid;
232 }
233
234 static void put_qpid(struct cxio_rdev *rdev_p, u32 qpid,
235                      struct cxio_ucontext *uctx)
236 {
237         struct cxio_qpid_list *entry;
238
239         entry = kmalloc(sizeof *entry, GFP_KERNEL);
240         if (!entry)
241                 return;
242         PDBG("%s qpid 0x%x\n", __func__, qpid);
243         entry->qpid = qpid;
244         mutex_lock(&uctx->lock);
245         list_add_tail(&entry->entry, &uctx->qpids);
246         mutex_unlock(&uctx->lock);
247 }
248
249 void cxio_release_ucontext(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
250 {
251         struct list_head *pos, *nxt;
252         struct cxio_qpid_list *entry;
253
254         mutex_lock(&uctx->lock);
255         list_for_each_safe(pos, nxt, &uctx->qpids) {
256                 entry = list_entry(pos, struct cxio_qpid_list, entry);
257                 list_del_init(&entry->entry);
258                 if (!(entry->qpid & rdev_p->qpmask))
259                         cxio_hal_put_qpid(rdev_p->rscp, entry->qpid);
260                 kfree(entry);
261         }
262         mutex_unlock(&uctx->lock);
263 }
264
265 void cxio_init_ucontext(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
266 {
267         INIT_LIST_HEAD(&uctx->qpids);
268         mutex_init(&uctx->lock);
269 }
270
271 int cxio_create_qp(struct cxio_rdev *rdev_p, u32 kernel_domain,
272                    struct t3_wq *wq, struct cxio_ucontext *uctx)
273 {
274         int depth = 1UL << wq->size_log2;
275         int rqsize = 1UL << wq->rq_size_log2;
276
277         wq->qpid = get_qpid(rdev_p, uctx);
278         if (!wq->qpid)
279                 return -ENOMEM;
280
281         wq->rq = kzalloc(depth * sizeof(struct t3_swrq), GFP_KERNEL);
282         if (!wq->rq)
283                 goto err1;
284
285         wq->rq_addr = cxio_hal_rqtpool_alloc(rdev_p, rqsize);
286         if (!wq->rq_addr)
287                 goto err2;
288
289         wq->sq = kzalloc(depth * sizeof(struct t3_swsq), GFP_KERNEL);
290         if (!wq->sq)
291                 goto err3;
292
293         wq->queue = dma_alloc_coherent(&(rdev_p->rnic_info.pdev->dev),
294                                              depth * sizeof(union t3_wr),
295                                              &(wq->dma_addr), GFP_KERNEL);
296         if (!wq->queue)
297                 goto err4;
298
299         memset(wq->queue, 0, depth * sizeof(union t3_wr));
300         pci_unmap_addr_set(wq, mapping, wq->dma_addr);
301         wq->doorbell = (void __iomem *)rdev_p->rnic_info.kdb_addr;
302         if (!kernel_domain)
303                 wq->udb = (u64)rdev_p->rnic_info.udbell_physbase +
304                                         (wq->qpid << rdev_p->qpshift);
305         wq->rdev = rdev_p;
306         PDBG("%s qpid 0x%x doorbell 0x%p udb 0x%llx\n", __func__,
307              wq->qpid, wq->doorbell, (unsigned long long) wq->udb);
308         return 0;
309 err4:
310         kfree(wq->sq);
311 err3:
312         cxio_hal_rqtpool_free(rdev_p, wq->rq_addr, rqsize);
313 err2:
314         kfree(wq->rq);
315 err1:
316         put_qpid(rdev_p, wq->qpid, uctx);
317         return -ENOMEM;
318 }
319
320 int cxio_destroy_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq)
321 {
322         int err;
323         err = cxio_hal_clear_cq_ctx(rdev_p, cq->cqid);
324         kfree(cq->sw_queue);
325         dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
326                           (1UL << (cq->size_log2))
327                           * sizeof(struct t3_cqe), cq->queue,
328                           pci_unmap_addr(cq, mapping));
329         cxio_hal_put_cqid(rdev_p->rscp, cq->cqid);
330         return err;
331 }
332
333 int cxio_destroy_qp(struct cxio_rdev *rdev_p, struct t3_wq *wq,
334                     struct cxio_ucontext *uctx)
335 {
336         dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
337                           (1UL << (wq->size_log2))
338                           * sizeof(union t3_wr), wq->queue,
339                           pci_unmap_addr(wq, mapping));
340         kfree(wq->sq);
341         cxio_hal_rqtpool_free(rdev_p, wq->rq_addr, (1UL << wq->rq_size_log2));
342         kfree(wq->rq);
343         put_qpid(rdev_p, wq->qpid, uctx);
344         return 0;
345 }
346
347 static void insert_recv_cqe(struct t3_wq *wq, struct t3_cq *cq)
348 {
349         struct t3_cqe cqe;
350
351         PDBG("%s wq %p cq %p sw_rptr 0x%x sw_wptr 0x%x\n", __func__,
352              wq, cq, cq->sw_rptr, cq->sw_wptr);
353         memset(&cqe, 0, sizeof(cqe));
354         cqe.header = cpu_to_be32(V_CQE_STATUS(TPT_ERR_SWFLUSH) |
355                                  V_CQE_OPCODE(T3_SEND) |
356                                  V_CQE_TYPE(0) |
357                                  V_CQE_SWCQE(1) |
358                                  V_CQE_QPID(wq->qpid) |
359                                  V_CQE_GENBIT(Q_GENBIT(cq->sw_wptr,
360                                                        cq->size_log2)));
361         *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2)) = cqe;
362         cq->sw_wptr++;
363 }
364
365 int cxio_flush_rq(struct t3_wq *wq, struct t3_cq *cq, int count)
366 {
367         u32 ptr;
368         int flushed = 0;
369
370         PDBG("%s wq %p cq %p\n", __func__, wq, cq);
371
372         /* flush RQ */
373         PDBG("%s rq_rptr %u rq_wptr %u skip count %u\n", __func__,
374             wq->rq_rptr, wq->rq_wptr, count);
375         ptr = wq->rq_rptr + count;
376         while (ptr++ != wq->rq_wptr) {
377                 insert_recv_cqe(wq, cq);
378                 flushed++;
379         }
380         return flushed;
381 }
382
383 static void insert_sq_cqe(struct t3_wq *wq, struct t3_cq *cq,
384                           struct t3_swsq *sqp)
385 {
386         struct t3_cqe cqe;
387
388         PDBG("%s wq %p cq %p sw_rptr 0x%x sw_wptr 0x%x\n", __func__,
389              wq, cq, cq->sw_rptr, cq->sw_wptr);
390         memset(&cqe, 0, sizeof(cqe));
391         cqe.header = cpu_to_be32(V_CQE_STATUS(TPT_ERR_SWFLUSH) |
392                                  V_CQE_OPCODE(sqp->opcode) |
393                                  V_CQE_TYPE(1) |
394                                  V_CQE_SWCQE(1) |
395                                  V_CQE_QPID(wq->qpid) |
396                                  V_CQE_GENBIT(Q_GENBIT(cq->sw_wptr,
397                                                        cq->size_log2)));
398         cqe.u.scqe.wrid_hi = sqp->sq_wptr;
399
400         *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2)) = cqe;
401         cq->sw_wptr++;
402 }
403
404 int cxio_flush_sq(struct t3_wq *wq, struct t3_cq *cq, int count)
405 {
406         __u32 ptr;
407         int flushed = 0;
408         struct t3_swsq *sqp = wq->sq + Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2);
409
410         ptr = wq->sq_rptr + count;
411         sqp = wq->sq + Q_PTR2IDX(ptr, wq->sq_size_log2);
412         while (ptr != wq->sq_wptr) {
413                 insert_sq_cqe(wq, cq, sqp);
414                 ptr++;
415                 sqp = wq->sq + Q_PTR2IDX(ptr, wq->sq_size_log2);
416                 flushed++;
417         }
418         return flushed;
419 }
420
421 /*
422  * Move all CQEs from the HWCQ into the SWCQ.
423  */
424 void cxio_flush_hw_cq(struct t3_cq *cq)
425 {
426         struct t3_cqe *cqe, *swcqe;
427
428         PDBG("%s cq %p cqid 0x%x\n", __func__, cq, cq->cqid);
429         cqe = cxio_next_hw_cqe(cq);
430         while (cqe) {
431                 PDBG("%s flushing hwcq rptr 0x%x to swcq wptr 0x%x\n",
432                      __func__, cq->rptr, cq->sw_wptr);
433                 swcqe = cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2);
434                 *swcqe = *cqe;
435                 swcqe->header |= cpu_to_be32(V_CQE_SWCQE(1));
436                 cq->sw_wptr++;
437                 cq->rptr++;
438                 cqe = cxio_next_hw_cqe(cq);
439         }
440 }
441
442 static int cqe_completes_wr(struct t3_cqe *cqe, struct t3_wq *wq)
443 {
444         if (CQE_OPCODE(*cqe) == T3_TERMINATE)
445                 return 0;
446
447         if ((CQE_OPCODE(*cqe) == T3_RDMA_WRITE) && RQ_TYPE(*cqe))
448                 return 0;
449
450         if ((CQE_OPCODE(*cqe) == T3_READ_RESP) && SQ_TYPE(*cqe))
451                 return 0;
452
453         if (CQE_SEND_OPCODE(*cqe) && RQ_TYPE(*cqe) &&
454             Q_EMPTY(wq->rq_rptr, wq->rq_wptr))
455                 return 0;
456
457         return 1;
458 }
459
460 void cxio_count_scqes(struct t3_cq *cq, struct t3_wq *wq, int *count)
461 {
462         struct t3_cqe *cqe;
463         u32 ptr;
464
465         *count = 0;
466         ptr = cq->sw_rptr;
467         while (!Q_EMPTY(ptr, cq->sw_wptr)) {
468                 cqe = cq->sw_queue + (Q_PTR2IDX(ptr, cq->size_log2));
469                 if ((SQ_TYPE(*cqe) ||
470                      ((CQE_OPCODE(*cqe) == T3_READ_RESP) && wq->oldest_read)) &&
471                     (CQE_QPID(*cqe) == wq->qpid))
472                         (*count)++;
473                 ptr++;
474         }
475         PDBG("%s cq %p count %d\n", __func__, cq, *count);
476 }
477
478 void cxio_count_rcqes(struct t3_cq *cq, struct t3_wq *wq, int *count)
479 {
480         struct t3_cqe *cqe;
481         u32 ptr;
482
483         *count = 0;
484         PDBG("%s count zero %d\n", __func__, *count);
485         ptr = cq->sw_rptr;
486         while (!Q_EMPTY(ptr, cq->sw_wptr)) {
487                 cqe = cq->sw_queue + (Q_PTR2IDX(ptr, cq->size_log2));
488                 if (RQ_TYPE(*cqe) && (CQE_OPCODE(*cqe) != T3_READ_RESP) &&
489                     (CQE_QPID(*cqe) == wq->qpid) && cqe_completes_wr(cqe, wq))
490                         (*count)++;
491                 ptr++;
492         }
493         PDBG("%s cq %p count %d\n", __func__, cq, *count);
494 }
495
496 static int cxio_hal_init_ctrl_cq(struct cxio_rdev *rdev_p)
497 {
498         struct rdma_cq_setup setup;
499         setup.id = 0;
500         setup.base_addr = 0;    /* NULL address */
501         setup.size = 1;         /* enable the CQ */
502         setup.credits = 0;
503
504         /* force SGE to redirect to RspQ and interrupt */
505         setup.credit_thres = 0;
506         setup.ovfl_mode = 1;
507         return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
508 }
509
510 static int cxio_hal_init_ctrl_qp(struct cxio_rdev *rdev_p)
511 {
512         int err;
513         u64 sge_cmd, ctx0, ctx1;
514         u64 base_addr;
515         struct t3_modify_qp_wr *wqe;
516         struct sk_buff *skb;
517
518         skb = alloc_skb(sizeof(*wqe), GFP_KERNEL);
519         if (!skb) {
520                 PDBG("%s alloc_skb failed\n", __func__);
521                 return -ENOMEM;
522         }
523         err = cxio_hal_init_ctrl_cq(rdev_p);
524         if (err) {
525                 PDBG("%s err %d initializing ctrl_cq\n", __func__, err);
526                 goto err;
527         }
528         rdev_p->ctrl_qp.workq = dma_alloc_coherent(
529                                         &(rdev_p->rnic_info.pdev->dev),
530                                         (1 << T3_CTRL_QP_SIZE_LOG2) *
531                                         sizeof(union t3_wr),
532                                         &(rdev_p->ctrl_qp.dma_addr),
533                                         GFP_KERNEL);
534         if (!rdev_p->ctrl_qp.workq) {
535                 PDBG("%s dma_alloc_coherent failed\n", __func__);
536                 err = -ENOMEM;
537                 goto err;
538         }
539         pci_unmap_addr_set(&rdev_p->ctrl_qp, mapping,
540                            rdev_p->ctrl_qp.dma_addr);
541         rdev_p->ctrl_qp.doorbell = (void __iomem *)rdev_p->rnic_info.kdb_addr;
542         memset(rdev_p->ctrl_qp.workq, 0,
543                (1 << T3_CTRL_QP_SIZE_LOG2) * sizeof(union t3_wr));
544
545         mutex_init(&rdev_p->ctrl_qp.lock);
546         init_waitqueue_head(&rdev_p->ctrl_qp.waitq);
547
548         /* update HW Ctrl QP context */
549         base_addr = rdev_p->ctrl_qp.dma_addr;
550         base_addr >>= 12;
551         ctx0 = (V_EC_SIZE((1 << T3_CTRL_QP_SIZE_LOG2)) |
552                 V_EC_BASE_LO((u32) base_addr & 0xffff));
553         ctx0 <<= 32;
554         ctx0 |= V_EC_CREDITS(FW_WR_NUM);
555         base_addr >>= 16;
556         ctx1 = (u32) base_addr;
557         base_addr >>= 32;
558         ctx1 |= ((u64) (V_EC_BASE_HI((u32) base_addr & 0xf) | V_EC_RESPQ(0) |
559                         V_EC_TYPE(0) | V_EC_GEN(1) |
560                         V_EC_UP_TOKEN(T3_CTL_QP_TID) | F_EC_VALID)) << 32;
561         wqe = (struct t3_modify_qp_wr *) skb_put(skb, sizeof(*wqe));
562         memset(wqe, 0, sizeof(*wqe));
563         build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_QP_MOD, 0, 0,
564                        T3_CTL_QP_TID, 7, T3_SOPEOP);
565         wqe->flags = cpu_to_be32(MODQP_WRITE_EC);
566         sge_cmd = (3ULL << 56) | FW_RI_SGEEC_START << 8 | 3;
567         wqe->sge_cmd = cpu_to_be64(sge_cmd);
568         wqe->ctx1 = cpu_to_be64(ctx1);
569         wqe->ctx0 = cpu_to_be64(ctx0);
570         PDBG("CtrlQP dma_addr 0x%llx workq %p size %d\n",
571              (unsigned long long) rdev_p->ctrl_qp.dma_addr,
572              rdev_p->ctrl_qp.workq, 1 << T3_CTRL_QP_SIZE_LOG2);
573         skb->priority = CPL_PRIORITY_CONTROL;
574         return (cxgb3_ofld_send(rdev_p->t3cdev_p, skb));
575 err:
576         kfree_skb(skb);
577         return err;
578 }
579
580 static int cxio_hal_destroy_ctrl_qp(struct cxio_rdev *rdev_p)
581 {
582         dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
583                           (1UL << T3_CTRL_QP_SIZE_LOG2)
584                           * sizeof(union t3_wr), rdev_p->ctrl_qp.workq,
585                           pci_unmap_addr(&rdev_p->ctrl_qp, mapping));
586         return cxio_hal_clear_qp_ctx(rdev_p, T3_CTRL_QP_ID);
587 }
588
589 /* write len bytes of data into addr (32B aligned address)
590  * If data is NULL, clear len byte of memory to zero.
591  * caller aquires the ctrl_qp lock before the call
592  */
593 static int cxio_hal_ctrl_qp_write_mem(struct cxio_rdev *rdev_p, u32 addr,
594                                       u32 len, void *data)
595 {
596         u32 i, nr_wqe, copy_len;
597         u8 *copy_data;
598         u8 wr_len, utx_len;     /* length in 8 byte flit */
599         enum t3_wr_flags flag;
600         __be64 *wqe;
601         u64 utx_cmd;
602         addr &= 0x7FFFFFF;
603         nr_wqe = len % 96 ? len / 96 + 1 : len / 96;    /* 96B max per WQE */
604         PDBG("%s wptr 0x%x rptr 0x%x len %d, nr_wqe %d data %p addr 0x%0x\n",
605              __func__, rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, len,
606              nr_wqe, data, addr);
607         utx_len = 3;            /* in 32B unit */
608         for (i = 0; i < nr_wqe; i++) {
609                 if (Q_FULL(rdev_p->ctrl_qp.rptr, rdev_p->ctrl_qp.wptr,
610                            T3_CTRL_QP_SIZE_LOG2)) {
611                         PDBG("%s ctrl_qp full wtpr 0x%0x rptr 0x%0x, "
612                              "wait for more space i %d\n", __func__,
613                              rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, i);
614                         if (wait_event_interruptible(rdev_p->ctrl_qp.waitq,
615                                              !Q_FULL(rdev_p->ctrl_qp.rptr,
616                                                      rdev_p->ctrl_qp.wptr,
617                                                      T3_CTRL_QP_SIZE_LOG2))) {
618                                 PDBG("%s ctrl_qp workq interrupted\n",
619                                      __func__);
620                                 return -ERESTARTSYS;
621                         }
622                         PDBG("%s ctrl_qp wakeup, continue posting work request "
623                              "i %d\n", __func__, i);
624                 }
625                 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr %
626                                                 (1 << T3_CTRL_QP_SIZE_LOG2)));
627                 flag = 0;
628                 if (i == (nr_wqe - 1)) {
629                         /* last WQE */
630                         flag = T3_COMPLETION_FLAG;
631                         if (len % 32)
632                                 utx_len = len / 32 + 1;
633                         else
634                                 utx_len = len / 32;
635                 }
636
637                 /*
638                  * Force a CQE to return the credit to the workq in case
639                  * we posted more than half the max QP size of WRs
640                  */
641                 if ((i != 0) &&
642                     (i % (((1 << T3_CTRL_QP_SIZE_LOG2)) >> 1) == 0)) {
643                         flag = T3_COMPLETION_FLAG;
644                         PDBG("%s force completion at i %d\n", __func__, i);
645                 }
646
647                 /* build the utx mem command */
648                 wqe += (sizeof(struct t3_bypass_wr) >> 3);
649                 utx_cmd = (T3_UTX_MEM_WRITE << 28) | (addr + i * 3);
650                 utx_cmd <<= 32;
651                 utx_cmd |= (utx_len << 28) | ((utx_len << 2) + 1);
652                 *wqe = cpu_to_be64(utx_cmd);
653                 wqe++;
654                 copy_data = (u8 *) data + i * 96;
655                 copy_len = len > 96 ? 96 : len;
656
657                 /* clear memory content if data is NULL */
658                 if (data)
659                         memcpy(wqe, copy_data, copy_len);
660                 else
661                         memset(wqe, 0, copy_len);
662                 if (copy_len % 32)
663                         memset(((u8 *) wqe) + copy_len, 0,
664                                32 - (copy_len % 32));
665                 wr_len = ((sizeof(struct t3_bypass_wr)) >> 3) + 1 +
666                          (utx_len << 2);
667                 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr %
668                               (1 << T3_CTRL_QP_SIZE_LOG2)));
669
670                 /* wptr in the WRID[31:0] */
671                 ((union t3_wrid *)(wqe+1))->id0.low = rdev_p->ctrl_qp.wptr;
672
673                 /*
674                  * This must be the last write with a memory barrier
675                  * for the genbit
676                  */
677                 build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_BP, flag,
678                                Q_GENBIT(rdev_p->ctrl_qp.wptr,
679                                         T3_CTRL_QP_SIZE_LOG2), T3_CTRL_QP_ID,
680                                wr_len, T3_SOPEOP);
681                 if (flag == T3_COMPLETION_FLAG)
682                         ring_doorbell(rdev_p->ctrl_qp.doorbell, T3_CTRL_QP_ID);
683                 len -= 96;
684                 rdev_p->ctrl_qp.wptr++;
685         }
686         return 0;
687 }
688
689 /* IN: stag key, pdid, perm, zbva, to, len, page_size, pbl_size and pbl_addr
690  * OUT: stag index
691  * TBD: shared memory region support
692  */
693 static int __cxio_tpt_op(struct cxio_rdev *rdev_p, u32 reset_tpt_entry,
694                          u32 *stag, u8 stag_state, u32 pdid,
695                          enum tpt_mem_type type, enum tpt_mem_perm perm,
696                          u32 zbva, u64 to, u32 len, u8 page_size,
697                          u32 pbl_size, u32 pbl_addr)
698 {
699         int err;
700         struct tpt_entry tpt;
701         u32 stag_idx;
702         u32 wptr;
703
704         stag_state = stag_state > 0;
705         stag_idx = (*stag) >> 8;
706
707         if ((!reset_tpt_entry) && !(*stag != T3_STAG_UNSET)) {
708                 stag_idx = cxio_hal_get_stag(rdev_p->rscp);
709                 if (!stag_idx)
710                         return -ENOMEM;
711                 *stag = (stag_idx << 8) | ((*stag) & 0xFF);
712         }
713         PDBG("%s stag_state 0x%0x type 0x%0x pdid 0x%0x, stag_idx 0x%x\n",
714              __func__, stag_state, type, pdid, stag_idx);
715
716         mutex_lock(&rdev_p->ctrl_qp.lock);
717
718         /* write TPT entry */
719         if (reset_tpt_entry)
720                 memset(&tpt, 0, sizeof(tpt));
721         else {
722                 tpt.valid_stag_pdid = cpu_to_be32(F_TPT_VALID |
723                                 V_TPT_STAG_KEY((*stag) & M_TPT_STAG_KEY) |
724                                 V_TPT_STAG_STATE(stag_state) |
725                                 V_TPT_STAG_TYPE(type) | V_TPT_PDID(pdid));
726                 BUG_ON(page_size >= 28);
727                 tpt.flags_pagesize_qpid = cpu_to_be32(V_TPT_PERM(perm) |
728                         ((perm & TPT_MW_BIND) ? F_TPT_MW_BIND_ENABLE : 0) |
729                         V_TPT_ADDR_TYPE((zbva ? TPT_ZBTO : TPT_VATO)) |
730                         V_TPT_PAGE_SIZE(page_size));
731                 tpt.rsvd_pbl_addr = reset_tpt_entry ? 0 :
732                                     cpu_to_be32(V_TPT_PBL_ADDR(PBL_OFF(rdev_p, pbl_addr)>>3));
733                 tpt.len = cpu_to_be32(len);
734                 tpt.va_hi = cpu_to_be32((u32) (to >> 32));
735                 tpt.va_low_or_fbo = cpu_to_be32((u32) (to & 0xFFFFFFFFULL));
736                 tpt.rsvd_bind_cnt_or_pstag = 0;
737                 tpt.rsvd_pbl_size = reset_tpt_entry ? 0 :
738                                   cpu_to_be32(V_TPT_PBL_SIZE(pbl_size >> 2));
739         }
740         err = cxio_hal_ctrl_qp_write_mem(rdev_p,
741                                        stag_idx +
742                                        (rdev_p->rnic_info.tpt_base >> 5),
743                                        sizeof(tpt), &tpt);
744
745         /* release the stag index to free pool */
746         if (reset_tpt_entry)
747                 cxio_hal_put_stag(rdev_p->rscp, stag_idx);
748
749         wptr = rdev_p->ctrl_qp.wptr;
750         mutex_unlock(&rdev_p->ctrl_qp.lock);
751         if (!err)
752                 if (wait_event_interruptible(rdev_p->ctrl_qp.waitq,
753                                              SEQ32_GE(rdev_p->ctrl_qp.rptr,
754                                                       wptr)))
755                         return -ERESTARTSYS;
756         return err;
757 }
758
759 int cxio_write_pbl(struct cxio_rdev *rdev_p, __be64 *pbl,
760                    u32 pbl_addr, u32 pbl_size)
761 {
762         u32 wptr;
763         int err;
764
765         PDBG("%s *pdb_addr 0x%x, pbl_base 0x%x, pbl_size %d\n",
766              __func__, pbl_addr, rdev_p->rnic_info.pbl_base,
767              pbl_size);
768
769         mutex_lock(&rdev_p->ctrl_qp.lock);
770         err = cxio_hal_ctrl_qp_write_mem(rdev_p, pbl_addr >> 5, pbl_size << 3,
771                                          pbl);
772         wptr = rdev_p->ctrl_qp.wptr;
773         mutex_unlock(&rdev_p->ctrl_qp.lock);
774         if (err)
775                 return err;
776
777         if (wait_event_interruptible(rdev_p->ctrl_qp.waitq,
778                                      SEQ32_GE(rdev_p->ctrl_qp.rptr,
779                                               wptr)))
780                 return -ERESTARTSYS;
781
782         return 0;
783 }
784
785 int cxio_register_phys_mem(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid,
786                            enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len,
787                            u8 page_size, u32 pbl_size, u32 pbl_addr)
788 {
789         *stag = T3_STAG_UNSET;
790         return __cxio_tpt_op(rdev_p, 0, stag, 1, pdid, TPT_NON_SHARED_MR, perm,
791                              zbva, to, len, page_size, pbl_size, pbl_addr);
792 }
793
794 int cxio_reregister_phys_mem(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid,
795                            enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len,
796                            u8 page_size, u32 pbl_size, u32 pbl_addr)
797 {
798         return __cxio_tpt_op(rdev_p, 0, stag, 1, pdid, TPT_NON_SHARED_MR, perm,
799                              zbva, to, len, page_size, pbl_size, pbl_addr);
800 }
801
802 int cxio_dereg_mem(struct cxio_rdev *rdev_p, u32 stag, u32 pbl_size,
803                    u32 pbl_addr)
804 {
805         return __cxio_tpt_op(rdev_p, 1, &stag, 0, 0, 0, 0, 0, 0ULL, 0, 0,
806                              pbl_size, pbl_addr);
807 }
808
809 int cxio_allocate_window(struct cxio_rdev *rdev_p, u32 * stag, u32 pdid)
810 {
811         *stag = T3_STAG_UNSET;
812         return __cxio_tpt_op(rdev_p, 0, stag, 0, pdid, TPT_MW, 0, 0, 0ULL, 0, 0,
813                              0, 0);
814 }
815
816 int cxio_deallocate_window(struct cxio_rdev *rdev_p, u32 stag)
817 {
818         return __cxio_tpt_op(rdev_p, 1, &stag, 0, 0, 0, 0, 0, 0ULL, 0, 0,
819                              0, 0);
820 }
821
822 int cxio_allocate_stag(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid, u32 pbl_size, u32 pbl_addr)
823 {
824         *stag = T3_STAG_UNSET;
825         return __cxio_tpt_op(rdev_p, 0, stag, 0, pdid, TPT_NON_SHARED_MR,
826                              0, 0, 0ULL, 0, 0, pbl_size, pbl_addr);
827 }
828
829 int cxio_rdma_init(struct cxio_rdev *rdev_p, struct t3_rdma_init_attr *attr)
830 {
831         struct t3_rdma_init_wr *wqe;
832         struct sk_buff *skb = alloc_skb(sizeof(*wqe), GFP_ATOMIC);
833         if (!skb)
834                 return -ENOMEM;
835         PDBG("%s rdev_p %p\n", __func__, rdev_p);
836         wqe = (struct t3_rdma_init_wr *) __skb_put(skb, sizeof(*wqe));
837         wqe->wrh.op_seop_flags = cpu_to_be32(V_FW_RIWR_OP(T3_WR_INIT));
838         wqe->wrh.gen_tid_len = cpu_to_be32(V_FW_RIWR_TID(attr->tid) |
839                                            V_FW_RIWR_LEN(sizeof(*wqe) >> 3));
840         wqe->wrid.id1 = 0;
841         wqe->qpid = cpu_to_be32(attr->qpid);
842         wqe->pdid = cpu_to_be32(attr->pdid);
843         wqe->scqid = cpu_to_be32(attr->scqid);
844         wqe->rcqid = cpu_to_be32(attr->rcqid);
845         wqe->rq_addr = cpu_to_be32(attr->rq_addr - rdev_p->rnic_info.rqt_base);
846         wqe->rq_size = cpu_to_be32(attr->rq_size);
847         wqe->mpaattrs = attr->mpaattrs;
848         wqe->qpcaps = attr->qpcaps;
849         wqe->ulpdu_size = cpu_to_be16(attr->tcp_emss);
850         wqe->rqe_count = cpu_to_be16(attr->rqe_count);
851         wqe->flags_rtr_type = cpu_to_be16(attr->flags|V_RTR_TYPE(attr->rtr_type));
852         wqe->ord = cpu_to_be32(attr->ord);
853         wqe->ird = cpu_to_be32(attr->ird);
854         wqe->qp_dma_addr = cpu_to_be64(attr->qp_dma_addr);
855         wqe->qp_dma_size = cpu_to_be32(attr->qp_dma_size);
856         wqe->irs = cpu_to_be32(attr->irs);
857         skb->priority = 0;      /* 0=>ToeQ; 1=>CtrlQ */
858         return (cxgb3_ofld_send(rdev_p->t3cdev_p, skb));
859 }
860
861 void cxio_register_ev_cb(cxio_hal_ev_callback_func_t ev_cb)
862 {
863         cxio_ev_cb = ev_cb;
864 }
865
866 void cxio_unregister_ev_cb(cxio_hal_ev_callback_func_t ev_cb)
867 {
868         cxio_ev_cb = NULL;
869 }
870
871 static int cxio_hal_ev_handler(struct t3cdev *t3cdev_p, struct sk_buff *skb)
872 {
873         static int cnt;
874         struct cxio_rdev *rdev_p = NULL;
875         struct respQ_msg_t *rsp_msg = (struct respQ_msg_t *) skb->data;
876         PDBG("%d: %s cq_id 0x%x cq_ptr 0x%x genbit %0x overflow %0x an %0x"
877              " se %0x notify %0x cqbranch %0x creditth %0x\n",
878              cnt, __func__, RSPQ_CQID(rsp_msg), RSPQ_CQPTR(rsp_msg),
879              RSPQ_GENBIT(rsp_msg), RSPQ_OVERFLOW(rsp_msg), RSPQ_AN(rsp_msg),
880              RSPQ_SE(rsp_msg), RSPQ_NOTIFY(rsp_msg), RSPQ_CQBRANCH(rsp_msg),
881              RSPQ_CREDIT_THRESH(rsp_msg));
882         PDBG("CQE: QPID 0x%0x genbit %0x type 0x%0x status 0x%0x opcode %d "
883              "len 0x%0x wrid_hi_stag 0x%x wrid_low_msn 0x%x\n",
884              CQE_QPID(rsp_msg->cqe), CQE_GENBIT(rsp_msg->cqe),
885              CQE_TYPE(rsp_msg->cqe), CQE_STATUS(rsp_msg->cqe),
886              CQE_OPCODE(rsp_msg->cqe), CQE_LEN(rsp_msg->cqe),
887              CQE_WRID_HI(rsp_msg->cqe), CQE_WRID_LOW(rsp_msg->cqe));
888         rdev_p = (struct cxio_rdev *)t3cdev_p->ulp;
889         if (!rdev_p) {
890                 PDBG("%s called by t3cdev %p with null ulp\n", __func__,
891                      t3cdev_p);
892                 return 0;
893         }
894         if (CQE_QPID(rsp_msg->cqe) == T3_CTRL_QP_ID) {
895                 rdev_p->ctrl_qp.rptr = CQE_WRID_LOW(rsp_msg->cqe) + 1;
896                 wake_up_interruptible(&rdev_p->ctrl_qp.waitq);
897                 dev_kfree_skb_irq(skb);
898         } else if (CQE_QPID(rsp_msg->cqe) == 0xfff8)
899                 dev_kfree_skb_irq(skb);
900         else if (cxio_ev_cb)
901                 (*cxio_ev_cb) (rdev_p, skb);
902         else
903                 dev_kfree_skb_irq(skb);
904         cnt++;
905         return 0;
906 }
907
908 /* Caller takes care of locking if needed */
909 int cxio_rdev_open(struct cxio_rdev *rdev_p)
910 {
911         struct net_device *netdev_p = NULL;
912         int err = 0;
913         if (strlen(rdev_p->dev_name)) {
914                 if (cxio_hal_find_rdev_by_name(rdev_p->dev_name)) {
915                         return -EBUSY;
916                 }
917                 netdev_p = dev_get_by_name(&init_net, rdev_p->dev_name);
918                 if (!netdev_p) {
919                         return -EINVAL;
920                 }
921                 dev_put(netdev_p);
922         } else if (rdev_p->t3cdev_p) {
923                 if (cxio_hal_find_rdev_by_t3cdev(rdev_p->t3cdev_p)) {
924                         return -EBUSY;
925                 }
926                 netdev_p = rdev_p->t3cdev_p->lldev;
927                 strncpy(rdev_p->dev_name, rdev_p->t3cdev_p->name,
928                         T3_MAX_DEV_NAME_LEN);
929         } else {
930                 PDBG("%s t3cdev_p or dev_name must be set\n", __func__);
931                 return -EINVAL;
932         }
933
934         list_add_tail(&rdev_p->entry, &rdev_list);
935
936         PDBG("%s opening rnic dev %s\n", __func__, rdev_p->dev_name);
937         memset(&rdev_p->ctrl_qp, 0, sizeof(rdev_p->ctrl_qp));
938         if (!rdev_p->t3cdev_p)
939                 rdev_p->t3cdev_p = dev2t3cdev(netdev_p);
940         rdev_p->t3cdev_p->ulp = (void *) rdev_p;
941
942         err = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, GET_EMBEDDED_INFO,
943                                          &(rdev_p->fw_info));
944         if (err) {
945                 printk(KERN_ERR "%s t3cdev_p(%p)->ctl returned error %d.\n",
946                      __func__, rdev_p->t3cdev_p, err);
947                 goto err1;
948         }
949         if (G_FW_VERSION_MAJOR(rdev_p->fw_info.fw_vers) != CXIO_FW_MAJ) {
950                 printk(KERN_ERR MOD "fatal firmware version mismatch: "
951                        "need version %u but adapter has version %u\n",
952                        CXIO_FW_MAJ,
953                        G_FW_VERSION_MAJOR(rdev_p->fw_info.fw_vers));
954                 err = -EINVAL;
955                 goto err1;
956         }
957
958         err = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_GET_PARAMS,
959                                          &(rdev_p->rnic_info));
960         if (err) {
961                 printk(KERN_ERR "%s t3cdev_p(%p)->ctl returned error %d.\n",
962                      __func__, rdev_p->t3cdev_p, err);
963                 goto err1;
964         }
965         err = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, GET_PORTS,
966                                     &(rdev_p->port_info));
967         if (err) {
968                 printk(KERN_ERR "%s t3cdev_p(%p)->ctl returned error %d.\n",
969                      __func__, rdev_p->t3cdev_p, err);
970                 goto err1;
971         }
972
973         /*
974          * qpshift is the number of bits to shift the qpid left in order
975          * to get the correct address of the doorbell for that qp.
976          */
977         cxio_init_ucontext(rdev_p, &rdev_p->uctx);
978         rdev_p->qpshift = PAGE_SHIFT -
979                           ilog2(65536 >>
980                                     ilog2(rdev_p->rnic_info.udbell_len >>
981                                               PAGE_SHIFT));
982         rdev_p->qpnr = rdev_p->rnic_info.udbell_len >> PAGE_SHIFT;
983         rdev_p->qpmask = (65536 >> ilog2(rdev_p->qpnr)) - 1;
984         PDBG("%s rnic %s info: tpt_base 0x%0x tpt_top 0x%0x num stags %d "
985              "pbl_base 0x%0x pbl_top 0x%0x rqt_base 0x%0x, rqt_top 0x%0x\n",
986              __func__, rdev_p->dev_name, rdev_p->rnic_info.tpt_base,
987              rdev_p->rnic_info.tpt_top, cxio_num_stags(rdev_p),
988              rdev_p->rnic_info.pbl_base,
989              rdev_p->rnic_info.pbl_top, rdev_p->rnic_info.rqt_base,
990              rdev_p->rnic_info.rqt_top);
991         PDBG("udbell_len 0x%0x udbell_physbase 0x%lx kdb_addr %p qpshift %lu "
992              "qpnr %d qpmask 0x%x\n",
993              rdev_p->rnic_info.udbell_len,
994              rdev_p->rnic_info.udbell_physbase, rdev_p->rnic_info.kdb_addr,
995              rdev_p->qpshift, rdev_p->qpnr, rdev_p->qpmask);
996
997         err = cxio_hal_init_ctrl_qp(rdev_p);
998         if (err) {
999                 printk(KERN_ERR "%s error %d initializing ctrl_qp.\n",
1000                        __func__, err);
1001                 goto err1;
1002         }
1003         err = cxio_hal_init_resource(rdev_p, cxio_num_stags(rdev_p), 0,
1004                                      0, T3_MAX_NUM_QP, T3_MAX_NUM_CQ,
1005                                      T3_MAX_NUM_PD);
1006         if (err) {
1007                 printk(KERN_ERR "%s error %d initializing hal resources.\n",
1008                        __func__, err);
1009                 goto err2;
1010         }
1011         err = cxio_hal_pblpool_create(rdev_p);
1012         if (err) {
1013                 printk(KERN_ERR "%s error %d initializing pbl mem pool.\n",
1014                        __func__, err);
1015                 goto err3;
1016         }
1017         err = cxio_hal_rqtpool_create(rdev_p);
1018         if (err) {
1019                 printk(KERN_ERR "%s error %d initializing rqt mem pool.\n",
1020                        __func__, err);
1021                 goto err4;
1022         }
1023         return 0;
1024 err4:
1025         cxio_hal_pblpool_destroy(rdev_p);
1026 err3:
1027         cxio_hal_destroy_resource(rdev_p->rscp);
1028 err2:
1029         cxio_hal_destroy_ctrl_qp(rdev_p);
1030 err1:
1031         list_del(&rdev_p->entry);
1032         return err;
1033 }
1034
1035 void cxio_rdev_close(struct cxio_rdev *rdev_p)
1036 {
1037         if (rdev_p) {
1038                 cxio_hal_pblpool_destroy(rdev_p);
1039                 cxio_hal_rqtpool_destroy(rdev_p);
1040                 list_del(&rdev_p->entry);
1041                 rdev_p->t3cdev_p->ulp = NULL;
1042                 cxio_hal_destroy_ctrl_qp(rdev_p);
1043                 cxio_hal_destroy_resource(rdev_p->rscp);
1044         }
1045 }
1046
1047 int __init cxio_hal_init(void)
1048 {
1049         if (cxio_hal_init_rhdl_resource(T3_MAX_NUM_RI))
1050                 return -ENOMEM;
1051         t3_register_cpl_handler(CPL_ASYNC_NOTIF, cxio_hal_ev_handler);
1052         return 0;
1053 }
1054
1055 void __exit cxio_hal_exit(void)
1056 {
1057         struct cxio_rdev *rdev, *tmp;
1058
1059         t3_register_cpl_handler(CPL_ASYNC_NOTIF, NULL);
1060         list_for_each_entry_safe(rdev, tmp, &rdev_list, entry)
1061                 cxio_rdev_close(rdev);
1062         cxio_hal_destroy_rhdl_resource();
1063 }
1064
1065 static void flush_completed_wrs(struct t3_wq *wq, struct t3_cq *cq)
1066 {
1067         struct t3_swsq *sqp;
1068         __u32 ptr = wq->sq_rptr;
1069         int count = Q_COUNT(wq->sq_rptr, wq->sq_wptr);
1070
1071         sqp = wq->sq + Q_PTR2IDX(ptr, wq->sq_size_log2);
1072         while (count--)
1073                 if (!sqp->signaled) {
1074                         ptr++;
1075                         sqp = wq->sq + Q_PTR2IDX(ptr,  wq->sq_size_log2);
1076                 } else if (sqp->complete) {
1077
1078                         /*
1079                          * Insert this completed cqe into the swcq.
1080                          */
1081                         PDBG("%s moving cqe into swcq sq idx %ld cq idx %ld\n",
1082                              __func__, Q_PTR2IDX(ptr,  wq->sq_size_log2),
1083                              Q_PTR2IDX(cq->sw_wptr, cq->size_log2));
1084                         sqp->cqe.header |= htonl(V_CQE_SWCQE(1));
1085                         *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2))
1086                                 = sqp->cqe;
1087                         cq->sw_wptr++;
1088                         sqp->signaled = 0;
1089                         break;
1090                 } else
1091                         break;
1092 }
1093
1094 static void create_read_req_cqe(struct t3_wq *wq, struct t3_cqe *hw_cqe,
1095                                 struct t3_cqe *read_cqe)
1096 {
1097         read_cqe->u.scqe.wrid_hi = wq->oldest_read->sq_wptr;
1098         read_cqe->len = wq->oldest_read->read_len;
1099         read_cqe->header = htonl(V_CQE_QPID(CQE_QPID(*hw_cqe)) |
1100                                  V_CQE_SWCQE(SW_CQE(*hw_cqe)) |
1101                                  V_CQE_OPCODE(T3_READ_REQ) |
1102                                  V_CQE_TYPE(1));
1103 }
1104
1105 /*
1106  * Return a ptr to the next read wr in the SWSQ or NULL.
1107  */
1108 static void advance_oldest_read(struct t3_wq *wq)
1109 {
1110
1111         u32 rptr = wq->oldest_read - wq->sq + 1;
1112         u32 wptr = Q_PTR2IDX(wq->sq_wptr, wq->sq_size_log2);
1113
1114         while (Q_PTR2IDX(rptr, wq->sq_size_log2) != wptr) {
1115                 wq->oldest_read = wq->sq + Q_PTR2IDX(rptr, wq->sq_size_log2);
1116
1117                 if (wq->oldest_read->opcode == T3_READ_REQ)
1118                         return;
1119                 rptr++;
1120         }
1121         wq->oldest_read = NULL;
1122 }
1123
1124 /*
1125  * cxio_poll_cq
1126  *
1127  * Caller must:
1128  *     check the validity of the first CQE,
1129  *     supply the wq assicated with the qpid.
1130  *
1131  * credit: cq credit to return to sge.
1132  * cqe_flushed: 1 iff the CQE is flushed.
1133  * cqe: copy of the polled CQE.
1134  *
1135  * return value:
1136  *     0       CQE returned,
1137  *    -1       CQE skipped, try again.
1138  */
1139 int cxio_poll_cq(struct t3_wq *wq, struct t3_cq *cq, struct t3_cqe *cqe,
1140                      u8 *cqe_flushed, u64 *cookie, u32 *credit)
1141 {
1142         int ret = 0;
1143         struct t3_cqe *hw_cqe, read_cqe;
1144
1145         *cqe_flushed = 0;
1146         *credit = 0;
1147         hw_cqe = cxio_next_cqe(cq);
1148
1149         PDBG("%s CQE OOO %d qpid 0x%0x genbit %d type %d status 0x%0x"
1150              " opcode 0x%0x len 0x%0x wrid_hi_stag 0x%x wrid_low_msn 0x%x\n",
1151              __func__, CQE_OOO(*hw_cqe), CQE_QPID(*hw_cqe),
1152              CQE_GENBIT(*hw_cqe), CQE_TYPE(*hw_cqe), CQE_STATUS(*hw_cqe),
1153              CQE_OPCODE(*hw_cqe), CQE_LEN(*hw_cqe), CQE_WRID_HI(*hw_cqe),
1154              CQE_WRID_LOW(*hw_cqe));
1155
1156         /*
1157          * skip cqe's not affiliated with a QP.
1158          */
1159         if (wq == NULL) {
1160                 ret = -1;
1161                 goto skip_cqe;
1162         }
1163
1164         /*
1165          * Gotta tweak READ completions:
1166          *      1) the cqe doesn't contain the sq_wptr from the wr.
1167          *      2) opcode not reflected from the wr.
1168          *      3) read_len not reflected from the wr.
1169          *      4) cq_type is RQ_TYPE not SQ_TYPE.
1170          */
1171         if (RQ_TYPE(*hw_cqe) && (CQE_OPCODE(*hw_cqe) == T3_READ_RESP)) {
1172
1173                 /*
1174                  * If this is an unsolicited read response, then the read
1175                  * was generated by the kernel driver as part of peer-2-peer
1176                  * connection setup.  So ignore the completion.
1177                  */
1178                 if (!wq->oldest_read) {
1179                         if (CQE_STATUS(*hw_cqe))
1180                                 wq->error = 1;
1181                         ret = -1;
1182                         goto skip_cqe;
1183                 }
1184
1185                 /*
1186                  * Don't write to the HWCQ, so create a new read req CQE
1187                  * in local memory.
1188                  */
1189                 create_read_req_cqe(wq, hw_cqe, &read_cqe);
1190                 hw_cqe = &read_cqe;
1191                 advance_oldest_read(wq);
1192         }
1193
1194         /*
1195          * T3A: Discard TERMINATE CQEs.
1196          */
1197         if (CQE_OPCODE(*hw_cqe) == T3_TERMINATE) {
1198                 ret = -1;
1199                 wq->error = 1;
1200                 goto skip_cqe;
1201         }
1202
1203         if (CQE_STATUS(*hw_cqe) || wq->error) {
1204                 *cqe_flushed = wq->error;
1205                 wq->error = 1;
1206
1207                 /*
1208                  * T3A inserts errors into the CQE.  We cannot return
1209                  * these as work completions.
1210                  */
1211                 /* incoming write failures */
1212                 if ((CQE_OPCODE(*hw_cqe) == T3_RDMA_WRITE)
1213                      && RQ_TYPE(*hw_cqe)) {
1214                         ret = -1;
1215                         goto skip_cqe;
1216                 }
1217                 /* incoming read request failures */
1218                 if ((CQE_OPCODE(*hw_cqe) == T3_READ_RESP) && SQ_TYPE(*hw_cqe)) {
1219                         ret = -1;
1220                         goto skip_cqe;
1221                 }
1222
1223                 /* incoming SEND with no receive posted failures */
1224                 if (CQE_SEND_OPCODE(*hw_cqe) && RQ_TYPE(*hw_cqe) &&
1225                     Q_EMPTY(wq->rq_rptr, wq->rq_wptr)) {
1226                         ret = -1;
1227                         goto skip_cqe;
1228                 }
1229                 BUG_ON((*cqe_flushed == 0) && !SW_CQE(*hw_cqe));
1230                 goto proc_cqe;
1231         }
1232
1233         /*
1234          * RECV completion.
1235          */
1236         if (RQ_TYPE(*hw_cqe)) {
1237
1238                 /*
1239                  * HW only validates 4 bits of MSN.  So we must validate that
1240                  * the MSN in the SEND is the next expected MSN.  If its not,
1241                  * then we complete this with TPT_ERR_MSN and mark the wq in
1242                  * error.
1243                  */
1244
1245                 if (Q_EMPTY(wq->rq_rptr, wq->rq_wptr)) {
1246                         wq->error = 1;
1247                         ret = -1;
1248                         goto skip_cqe;
1249                 }
1250
1251                 if (unlikely((CQE_WRID_MSN(*hw_cqe) != (wq->rq_rptr + 1)))) {
1252                         wq->error = 1;
1253                         hw_cqe->header |= htonl(V_CQE_STATUS(TPT_ERR_MSN));
1254                         goto proc_cqe;
1255                 }
1256                 goto proc_cqe;
1257         }
1258
1259         /*
1260          * If we get here its a send completion.
1261          *
1262          * Handle out of order completion. These get stuffed
1263          * in the SW SQ. Then the SW SQ is walked to move any
1264          * now in-order completions into the SW CQ.  This handles
1265          * 2 cases:
1266          *      1) reaping unsignaled WRs when the first subsequent
1267          *         signaled WR is completed.
1268          *      2) out of order read completions.
1269          */
1270         if (!SW_CQE(*hw_cqe) && (CQE_WRID_SQ_WPTR(*hw_cqe) != wq->sq_rptr)) {
1271                 struct t3_swsq *sqp;
1272
1273                 PDBG("%s out of order completion going in swsq at idx %ld\n",
1274                      __func__,
1275                      Q_PTR2IDX(CQE_WRID_SQ_WPTR(*hw_cqe), wq->sq_size_log2));
1276                 sqp = wq->sq +
1277                       Q_PTR2IDX(CQE_WRID_SQ_WPTR(*hw_cqe), wq->sq_size_log2);
1278                 sqp->cqe = *hw_cqe;
1279                 sqp->complete = 1;
1280                 ret = -1;
1281                 goto flush_wq;
1282         }
1283
1284 proc_cqe:
1285         *cqe = *hw_cqe;
1286
1287         /*
1288          * Reap the associated WR(s) that are freed up with this
1289          * completion.
1290          */
1291         if (SQ_TYPE(*hw_cqe)) {
1292                 wq->sq_rptr = CQE_WRID_SQ_WPTR(*hw_cqe);
1293                 PDBG("%s completing sq idx %ld\n", __func__,
1294                      Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2));
1295                 *cookie = wq->sq[Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2)].wr_id;
1296                 wq->sq_rptr++;
1297         } else {
1298                 PDBG("%s completing rq idx %ld\n", __func__,
1299                      Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2));
1300                 *cookie = wq->rq[Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2)].wr_id;
1301                 if (wq->rq[Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2)].pbl_addr)
1302                         cxio_hal_pblpool_free(wq->rdev,
1303                                 wq->rq[Q_PTR2IDX(wq->rq_rptr,
1304                                 wq->rq_size_log2)].pbl_addr, T3_STAG0_PBL_SIZE);
1305                 BUG_ON(Q_EMPTY(wq->rq_rptr, wq->rq_wptr));
1306                 wq->rq_rptr++;
1307         }
1308
1309 flush_wq:
1310         /*
1311          * Flush any completed cqes that are now in-order.
1312          */
1313         flush_completed_wrs(wq, cq);
1314
1315 skip_cqe:
1316         if (SW_CQE(*hw_cqe)) {
1317                 PDBG("%s cq %p cqid 0x%x skip sw cqe sw_rptr 0x%x\n",
1318                      __func__, cq, cq->cqid, cq->sw_rptr);
1319                 ++cq->sw_rptr;
1320         } else {
1321                 PDBG("%s cq %p cqid 0x%x skip hw cqe rptr 0x%x\n",
1322                      __func__, cq, cq->cqid, cq->rptr);
1323                 ++cq->rptr;
1324
1325                 /*
1326                  * T3A: compute credits.
1327                  */
1328                 if (((cq->rptr - cq->wptr) > (1 << (cq->size_log2 - 1)))
1329                     || ((cq->rptr - cq->wptr) >= 128)) {
1330                         *credit = cq->rptr - cq->wptr;
1331                         cq->wptr = cq->rptr;
1332                 }
1333         }
1334         return ret;
1335 }