Merge branch 'linus' into sched/core
[linux-3.10.git] / drivers / i2c / busses / i2c-s3c2410.c
1 /* linux/drivers/i2c/busses/i2c-s3c2410.c
2  *
3  * Copyright (C) 2004,2005,2009 Simtec Electronics
4  *      Ben Dooks <ben@simtec.co.uk>
5  *
6  * S3C2410 I2C Controller
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
21 */
22
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25
26 #include <linux/i2c.h>
27 #include <linux/i2c-id.h>
28 #include <linux/init.h>
29 #include <linux/time.h>
30 #include <linux/interrupt.h>
31 #include <linux/delay.h>
32 #include <linux/errno.h>
33 #include <linux/err.h>
34 #include <linux/platform_device.h>
35 #include <linux/clk.h>
36 #include <linux/cpufreq.h>
37 #include <linux/slab.h>
38
39 #include <asm/irq.h>
40 #include <asm/io.h>
41
42 #include <plat/regs-iic.h>
43 #include <plat/iic.h>
44
45 /* i2c controller state */
46
47 enum s3c24xx_i2c_state {
48         STATE_IDLE,
49         STATE_START,
50         STATE_READ,
51         STATE_WRITE,
52         STATE_STOP
53 };
54
55 enum s3c24xx_i2c_type {
56         TYPE_S3C2410,
57         TYPE_S3C2440,
58 };
59
60 struct s3c24xx_i2c {
61         spinlock_t              lock;
62         wait_queue_head_t       wait;
63         unsigned int            suspended:1;
64
65         struct i2c_msg          *msg;
66         unsigned int            msg_num;
67         unsigned int            msg_idx;
68         unsigned int            msg_ptr;
69
70         unsigned int            tx_setup;
71         unsigned int            irq;
72
73         enum s3c24xx_i2c_state  state;
74         unsigned long           clkrate;
75
76         void __iomem            *regs;
77         struct clk              *clk;
78         struct device           *dev;
79         struct resource         *ioarea;
80         struct i2c_adapter      adap;
81
82 #ifdef CONFIG_CPU_FREQ
83         struct notifier_block   freq_transition;
84 #endif
85 };
86
87 /* default platform data removed, dev should always carry data. */
88
89 /* s3c24xx_i2c_is2440()
90  *
91  * return true is this is an s3c2440
92 */
93
94 static inline int s3c24xx_i2c_is2440(struct s3c24xx_i2c *i2c)
95 {
96         struct platform_device *pdev = to_platform_device(i2c->dev);
97         enum s3c24xx_i2c_type type;
98
99         type = platform_get_device_id(pdev)->driver_data;
100         return type == TYPE_S3C2440;
101 }
102
103 /* s3c24xx_i2c_master_complete
104  *
105  * complete the message and wake up the caller, using the given return code,
106  * or zero to mean ok.
107 */
108
109 static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
110 {
111         dev_dbg(i2c->dev, "master_complete %d\n", ret);
112
113         i2c->msg_ptr = 0;
114         i2c->msg = NULL;
115         i2c->msg_idx++;
116         i2c->msg_num = 0;
117         if (ret)
118                 i2c->msg_idx = ret;
119
120         wake_up(&i2c->wait);
121 }
122
123 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
124 {
125         unsigned long tmp;
126
127         tmp = readl(i2c->regs + S3C2410_IICCON);
128         writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
129 }
130
131 static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
132 {
133         unsigned long tmp;
134
135         tmp = readl(i2c->regs + S3C2410_IICCON);
136         writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
137 }
138
139 /* irq enable/disable functions */
140
141 static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
142 {
143         unsigned long tmp;
144
145         tmp = readl(i2c->regs + S3C2410_IICCON);
146         writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
147 }
148
149 static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
150 {
151         unsigned long tmp;
152
153         tmp = readl(i2c->regs + S3C2410_IICCON);
154         writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
155 }
156
157
158 /* s3c24xx_i2c_message_start
159  *
160  * put the start of a message onto the bus
161 */
162
163 static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
164                                       struct i2c_msg *msg)
165 {
166         unsigned int addr = (msg->addr & 0x7f) << 1;
167         unsigned long stat;
168         unsigned long iiccon;
169
170         stat = 0;
171         stat |=  S3C2410_IICSTAT_TXRXEN;
172
173         if (msg->flags & I2C_M_RD) {
174                 stat |= S3C2410_IICSTAT_MASTER_RX;
175                 addr |= 1;
176         } else
177                 stat |= S3C2410_IICSTAT_MASTER_TX;
178
179         if (msg->flags & I2C_M_REV_DIR_ADDR)
180                 addr ^= 1;
181
182         /* todo - check for wether ack wanted or not */
183         s3c24xx_i2c_enable_ack(i2c);
184
185         iiccon = readl(i2c->regs + S3C2410_IICCON);
186         writel(stat, i2c->regs + S3C2410_IICSTAT);
187
188         dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
189         writeb(addr, i2c->regs + S3C2410_IICDS);
190
191         /* delay here to ensure the data byte has gotten onto the bus
192          * before the transaction is started */
193
194         ndelay(i2c->tx_setup);
195
196         dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
197         writel(iiccon, i2c->regs + S3C2410_IICCON);
198
199         stat |= S3C2410_IICSTAT_START;
200         writel(stat, i2c->regs + S3C2410_IICSTAT);
201 }
202
203 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
204 {
205         unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT);
206
207         dev_dbg(i2c->dev, "STOP\n");
208
209         /* stop the transfer */
210         iicstat &= ~S3C2410_IICSTAT_START;
211         writel(iicstat, i2c->regs + S3C2410_IICSTAT);
212
213         i2c->state = STATE_STOP;
214
215         s3c24xx_i2c_master_complete(i2c, ret);
216         s3c24xx_i2c_disable_irq(i2c);
217 }
218
219 /* helper functions to determine the current state in the set of
220  * messages we are sending */
221
222 /* is_lastmsg()
223  *
224  * returns TRUE if the current message is the last in the set
225 */
226
227 static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
228 {
229         return i2c->msg_idx >= (i2c->msg_num - 1);
230 }
231
232 /* is_msglast
233  *
234  * returns TRUE if we this is the last byte in the current message
235 */
236
237 static inline int is_msglast(struct s3c24xx_i2c *i2c)
238 {
239         return i2c->msg_ptr == i2c->msg->len-1;
240 }
241
242 /* is_msgend
243  *
244  * returns TRUE if we reached the end of the current message
245 */
246
247 static inline int is_msgend(struct s3c24xx_i2c *i2c)
248 {
249         return i2c->msg_ptr >= i2c->msg->len;
250 }
251
252 /* i2s_s3c_irq_nextbyte
253  *
254  * process an interrupt and work out what to do
255  */
256
257 static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
258 {
259         unsigned long tmp;
260         unsigned char byte;
261         int ret = 0;
262
263         switch (i2c->state) {
264
265         case STATE_IDLE:
266                 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__);
267                 goto out;
268                 break;
269
270         case STATE_STOP:
271                 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
272                 s3c24xx_i2c_disable_irq(i2c);
273                 goto out_ack;
274
275         case STATE_START:
276                 /* last thing we did was send a start condition on the
277                  * bus, or started a new i2c message
278                  */
279
280                 if (iicstat & S3C2410_IICSTAT_LASTBIT &&
281                     !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
282                         /* ack was not received... */
283
284                         dev_dbg(i2c->dev, "ack was not received\n");
285                         s3c24xx_i2c_stop(i2c, -ENXIO);
286                         goto out_ack;
287                 }
288
289                 if (i2c->msg->flags & I2C_M_RD)
290                         i2c->state = STATE_READ;
291                 else
292                         i2c->state = STATE_WRITE;
293
294                 /* terminate the transfer if there is nothing to do
295                  * as this is used by the i2c probe to find devices. */
296
297                 if (is_lastmsg(i2c) && i2c->msg->len == 0) {
298                         s3c24xx_i2c_stop(i2c, 0);
299                         goto out_ack;
300                 }
301
302                 if (i2c->state == STATE_READ)
303                         goto prepare_read;
304
305                 /* fall through to the write state, as we will need to
306                  * send a byte as well */
307
308         case STATE_WRITE:
309                 /* we are writing data to the device... check for the
310                  * end of the message, and if so, work out what to do
311                  */
312
313                 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
314                         if (iicstat & S3C2410_IICSTAT_LASTBIT) {
315                                 dev_dbg(i2c->dev, "WRITE: No Ack\n");
316
317                                 s3c24xx_i2c_stop(i2c, -ECONNREFUSED);
318                                 goto out_ack;
319                         }
320                 }
321
322  retry_write:
323
324                 if (!is_msgend(i2c)) {
325                         byte = i2c->msg->buf[i2c->msg_ptr++];
326                         writeb(byte, i2c->regs + S3C2410_IICDS);
327
328                         /* delay after writing the byte to allow the
329                          * data setup time on the bus, as writing the
330                          * data to the register causes the first bit
331                          * to appear on SDA, and SCL will change as
332                          * soon as the interrupt is acknowledged */
333
334                         ndelay(i2c->tx_setup);
335
336                 } else if (!is_lastmsg(i2c)) {
337                         /* we need to go to the next i2c message */
338
339                         dev_dbg(i2c->dev, "WRITE: Next Message\n");
340
341                         i2c->msg_ptr = 0;
342                         i2c->msg_idx++;
343                         i2c->msg++;
344
345                         /* check to see if we need to do another message */
346                         if (i2c->msg->flags & I2C_M_NOSTART) {
347
348                                 if (i2c->msg->flags & I2C_M_RD) {
349                                         /* cannot do this, the controller
350                                          * forces us to send a new START
351                                          * when we change direction */
352
353                                         s3c24xx_i2c_stop(i2c, -EINVAL);
354                                 }
355
356                                 goto retry_write;
357                         } else {
358                                 /* send the new start */
359                                 s3c24xx_i2c_message_start(i2c, i2c->msg);
360                                 i2c->state = STATE_START;
361                         }
362
363                 } else {
364                         /* send stop */
365
366                         s3c24xx_i2c_stop(i2c, 0);
367                 }
368                 break;
369
370         case STATE_READ:
371                 /* we have a byte of data in the data register, do
372                  * something with it, and then work out wether we are
373                  * going to do any more read/write
374                  */
375
376                 byte = readb(i2c->regs + S3C2410_IICDS);
377                 i2c->msg->buf[i2c->msg_ptr++] = byte;
378
379  prepare_read:
380                 if (is_msglast(i2c)) {
381                         /* last byte of buffer */
382
383                         if (is_lastmsg(i2c))
384                                 s3c24xx_i2c_disable_ack(i2c);
385
386                 } else if (is_msgend(i2c)) {
387                         /* ok, we've read the entire buffer, see if there
388                          * is anything else we need to do */
389
390                         if (is_lastmsg(i2c)) {
391                                 /* last message, send stop and complete */
392                                 dev_dbg(i2c->dev, "READ: Send Stop\n");
393
394                                 s3c24xx_i2c_stop(i2c, 0);
395                         } else {
396                                 /* go to the next transfer */
397                                 dev_dbg(i2c->dev, "READ: Next Transfer\n");
398
399                                 i2c->msg_ptr = 0;
400                                 i2c->msg_idx++;
401                                 i2c->msg++;
402                         }
403                 }
404
405                 break;
406         }
407
408         /* acknowlegde the IRQ and get back on with the work */
409
410  out_ack:
411         tmp = readl(i2c->regs + S3C2410_IICCON);
412         tmp &= ~S3C2410_IICCON_IRQPEND;
413         writel(tmp, i2c->regs + S3C2410_IICCON);
414  out:
415         return ret;
416 }
417
418 /* s3c24xx_i2c_irq
419  *
420  * top level IRQ servicing routine
421 */
422
423 static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id)
424 {
425         struct s3c24xx_i2c *i2c = dev_id;
426         unsigned long status;
427         unsigned long tmp;
428
429         status = readl(i2c->regs + S3C2410_IICSTAT);
430
431         if (status & S3C2410_IICSTAT_ARBITR) {
432                 /* deal with arbitration loss */
433                 dev_err(i2c->dev, "deal with arbitration loss\n");
434         }
435
436         if (i2c->state == STATE_IDLE) {
437                 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
438
439                 tmp = readl(i2c->regs + S3C2410_IICCON);
440                 tmp &= ~S3C2410_IICCON_IRQPEND;
441                 writel(tmp, i2c->regs +  S3C2410_IICCON);
442                 goto out;
443         }
444
445         /* pretty much this leaves us with the fact that we've
446          * transmitted or received whatever byte we last sent */
447
448         i2s_s3c_irq_nextbyte(i2c, status);
449
450  out:
451         return IRQ_HANDLED;
452 }
453
454
455 /* s3c24xx_i2c_set_master
456  *
457  * get the i2c bus for a master transaction
458 */
459
460 static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
461 {
462         unsigned long iicstat;
463         int timeout = 400;
464
465         while (timeout-- > 0) {
466                 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
467
468                 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
469                         return 0;
470
471                 msleep(1);
472         }
473
474         return -ETIMEDOUT;
475 }
476
477 /* s3c24xx_i2c_doxfer
478  *
479  * this starts an i2c transfer
480 */
481
482 static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
483                               struct i2c_msg *msgs, int num)
484 {
485         unsigned long timeout;
486         int ret;
487
488         if (i2c->suspended)
489                 return -EIO;
490
491         ret = s3c24xx_i2c_set_master(i2c);
492         if (ret != 0) {
493                 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
494                 ret = -EAGAIN;
495                 goto out;
496         }
497
498         spin_lock_irq(&i2c->lock);
499
500         i2c->msg     = msgs;
501         i2c->msg_num = num;
502         i2c->msg_ptr = 0;
503         i2c->msg_idx = 0;
504         i2c->state   = STATE_START;
505
506         s3c24xx_i2c_enable_irq(i2c);
507         s3c24xx_i2c_message_start(i2c, msgs);
508         spin_unlock_irq(&i2c->lock);
509
510         timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
511
512         ret = i2c->msg_idx;
513
514         /* having these next two as dev_err() makes life very
515          * noisy when doing an i2cdetect */
516
517         if (timeout == 0)
518                 dev_dbg(i2c->dev, "timeout\n");
519         else if (ret != num)
520                 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
521
522         /* ensure the stop has been through the bus */
523
524         msleep(1);
525
526  out:
527         return ret;
528 }
529
530 /* s3c24xx_i2c_xfer
531  *
532  * first port of call from the i2c bus code when an message needs
533  * transferring across the i2c bus.
534 */
535
536 static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,
537                         struct i2c_msg *msgs, int num)
538 {
539         struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data;
540         int retry;
541         int ret;
542
543         for (retry = 0; retry < adap->retries; retry++) {
544
545                 ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
546
547                 if (ret != -EAGAIN)
548                         return ret;
549
550                 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
551
552                 udelay(100);
553         }
554
555         return -EREMOTEIO;
556 }
557
558 /* declare our i2c functionality */
559 static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)
560 {
561         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
562 }
563
564 /* i2c bus registration info */
565
566 static const struct i2c_algorithm s3c24xx_i2c_algorithm = {
567         .master_xfer            = s3c24xx_i2c_xfer,
568         .functionality          = s3c24xx_i2c_func,
569 };
570
571 /* s3c24xx_i2c_calcdivisor
572  *
573  * return the divisor settings for a given frequency
574 */
575
576 static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,
577                                    unsigned int *div1, unsigned int *divs)
578 {
579         unsigned int calc_divs = clkin / wanted;
580         unsigned int calc_div1;
581
582         if (calc_divs > (16*16))
583                 calc_div1 = 512;
584         else
585                 calc_div1 = 16;
586
587         calc_divs += calc_div1-1;
588         calc_divs /= calc_div1;
589
590         if (calc_divs == 0)
591                 calc_divs = 1;
592         if (calc_divs > 17)
593                 calc_divs = 17;
594
595         *divs = calc_divs;
596         *div1 = calc_div1;
597
598         return clkin / (calc_divs * calc_div1);
599 }
600
601 /* s3c24xx_i2c_clockrate
602  *
603  * work out a divisor for the user requested frequency setting,
604  * either by the requested frequency, or scanning the acceptable
605  * range of frequencies until something is found
606 */
607
608 static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
609 {
610         struct s3c2410_platform_i2c *pdata = i2c->dev->platform_data;
611         unsigned long clkin = clk_get_rate(i2c->clk);
612         unsigned int divs, div1;
613         unsigned long target_frequency;
614         u32 iiccon;
615         int freq;
616
617         i2c->clkrate = clkin;
618         clkin /= 1000;          /* clkin now in KHz */
619
620         dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency);
621
622         target_frequency = pdata->frequency ? pdata->frequency : 100000;
623
624         target_frequency /= 1000; /* Target frequency now in KHz */
625
626         freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs);
627
628         if (freq > target_frequency) {
629                 dev_err(i2c->dev,
630                         "Unable to achieve desired frequency %luKHz."   \
631                         " Lowest achievable %dKHz\n", target_frequency, freq);
632                 return -EINVAL;
633         }
634
635         *got = freq;
636
637         iiccon = readl(i2c->regs + S3C2410_IICCON);
638         iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512);
639         iiccon |= (divs-1);
640
641         if (div1 == 512)
642                 iiccon |= S3C2410_IICCON_TXDIV_512;
643
644         writel(iiccon, i2c->regs + S3C2410_IICCON);
645
646         if (s3c24xx_i2c_is2440(i2c)) {
647                 unsigned long sda_delay;
648
649                 if (pdata->sda_delay) {
650                         sda_delay = (freq / 1000) * pdata->sda_delay;
651                         sda_delay /= 1000000;
652                         sda_delay = DIV_ROUND_UP(sda_delay, 5);
653                         if (sda_delay > 3)
654                                 sda_delay = 3;
655                         sda_delay |= S3C2410_IICLC_FILTER_ON;
656                 } else
657                         sda_delay = 0;
658
659                 dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay);
660                 writel(sda_delay, i2c->regs + S3C2440_IICLC);
661         }
662
663         return 0;
664 }
665
666 #ifdef CONFIG_CPU_FREQ
667
668 #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition)
669
670 static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb,
671                                           unsigned long val, void *data)
672 {
673         struct s3c24xx_i2c *i2c = freq_to_i2c(nb);
674         unsigned long flags;
675         unsigned int got;
676         int delta_f;
677         int ret;
678
679         delta_f = clk_get_rate(i2c->clk) - i2c->clkrate;
680
681         /* if we're post-change and the input clock has slowed down
682          * or at pre-change and the clock is about to speed up, then
683          * adjust our clock rate. <0 is slow, >0 speedup.
684          */
685
686         if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) ||
687             (val == CPUFREQ_PRECHANGE && delta_f > 0)) {
688                 spin_lock_irqsave(&i2c->lock, flags);
689                 ret = s3c24xx_i2c_clockrate(i2c, &got);
690                 spin_unlock_irqrestore(&i2c->lock, flags);
691
692                 if (ret < 0)
693                         dev_err(i2c->dev, "cannot find frequency\n");
694                 else
695                         dev_info(i2c->dev, "setting freq %d\n", got);
696         }
697
698         return 0;
699 }
700
701 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
702 {
703         i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition;
704
705         return cpufreq_register_notifier(&i2c->freq_transition,
706                                          CPUFREQ_TRANSITION_NOTIFIER);
707 }
708
709 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
710 {
711         cpufreq_unregister_notifier(&i2c->freq_transition,
712                                     CPUFREQ_TRANSITION_NOTIFIER);
713 }
714
715 #else
716 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
717 {
718         return 0;
719 }
720
721 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
722 {
723 }
724 #endif
725
726 /* s3c24xx_i2c_init
727  *
728  * initialise the controller, set the IO lines and frequency
729 */
730
731 static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
732 {
733         unsigned long iicon = S3C2410_IICCON_IRQEN | S3C2410_IICCON_ACKEN;
734         struct s3c2410_platform_i2c *pdata;
735         unsigned int freq;
736
737         /* get the plafrom data */
738
739         pdata = i2c->dev->platform_data;
740
741         /* inititalise the gpio */
742
743         if (pdata->cfg_gpio)
744                 pdata->cfg_gpio(to_platform_device(i2c->dev));
745
746         /* write slave address */
747
748         writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
749
750         dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
751
752         writel(iicon, i2c->regs + S3C2410_IICCON);
753
754         /* we need to work out the divisors for the clock... */
755
756         if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) {
757                 writel(0, i2c->regs + S3C2410_IICCON);
758                 dev_err(i2c->dev, "cannot meet bus frequency required\n");
759                 return -EINVAL;
760         }
761
762         /* todo - check that the i2c lines aren't being dragged anywhere */
763
764         dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq);
765         dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02lx\n", iicon);
766
767         return 0;
768 }
769
770 /* s3c24xx_i2c_probe
771  *
772  * called by the bus driver when a suitable device is found
773 */
774
775 static int s3c24xx_i2c_probe(struct platform_device *pdev)
776 {
777         struct s3c24xx_i2c *i2c;
778         struct s3c2410_platform_i2c *pdata;
779         struct resource *res;
780         int ret;
781
782         pdata = pdev->dev.platform_data;
783         if (!pdata) {
784                 dev_err(&pdev->dev, "no platform data\n");
785                 return -EINVAL;
786         }
787
788         i2c = kzalloc(sizeof(struct s3c24xx_i2c), GFP_KERNEL);
789         if (!i2c) {
790                 dev_err(&pdev->dev, "no memory for state\n");
791                 return -ENOMEM;
792         }
793
794         strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));
795         i2c->adap.owner   = THIS_MODULE;
796         i2c->adap.algo    = &s3c24xx_i2c_algorithm;
797         i2c->adap.retries = 2;
798         i2c->adap.class   = I2C_CLASS_HWMON | I2C_CLASS_SPD;
799         i2c->tx_setup     = 50;
800
801         spin_lock_init(&i2c->lock);
802         init_waitqueue_head(&i2c->wait);
803
804         /* find the clock and enable it */
805
806         i2c->dev = &pdev->dev;
807         i2c->clk = clk_get(&pdev->dev, "i2c");
808         if (IS_ERR(i2c->clk)) {
809                 dev_err(&pdev->dev, "cannot get clock\n");
810                 ret = -ENOENT;
811                 goto err_noclk;
812         }
813
814         dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
815
816         clk_enable(i2c->clk);
817
818         /* map the registers */
819
820         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
821         if (res == NULL) {
822                 dev_err(&pdev->dev, "cannot find IO resource\n");
823                 ret = -ENOENT;
824                 goto err_clk;
825         }
826
827         i2c->ioarea = request_mem_region(res->start, resource_size(res),
828                                          pdev->name);
829
830         if (i2c->ioarea == NULL) {
831                 dev_err(&pdev->dev, "cannot request IO\n");
832                 ret = -ENXIO;
833                 goto err_clk;
834         }
835
836         i2c->regs = ioremap(res->start, resource_size(res));
837
838         if (i2c->regs == NULL) {
839                 dev_err(&pdev->dev, "cannot map IO\n");
840                 ret = -ENXIO;
841                 goto err_ioarea;
842         }
843
844         dev_dbg(&pdev->dev, "registers %p (%p, %p)\n",
845                 i2c->regs, i2c->ioarea, res);
846
847         /* setup info block for the i2c core */
848
849         i2c->adap.algo_data = i2c;
850         i2c->adap.dev.parent = &pdev->dev;
851
852         /* initialise the i2c controller */
853
854         ret = s3c24xx_i2c_init(i2c);
855         if (ret != 0)
856                 goto err_iomap;
857
858         /* find the IRQ for this unit (note, this relies on the init call to
859          * ensure no current IRQs pending
860          */
861
862         i2c->irq = ret = platform_get_irq(pdev, 0);
863         if (ret <= 0) {
864                 dev_err(&pdev->dev, "cannot find IRQ\n");
865                 goto err_iomap;
866         }
867
868         ret = request_irq(i2c->irq, s3c24xx_i2c_irq, IRQF_DISABLED,
869                           dev_name(&pdev->dev), i2c);
870
871         if (ret != 0) {
872                 dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
873                 goto err_iomap;
874         }
875
876         ret = s3c24xx_i2c_register_cpufreq(i2c);
877         if (ret < 0) {
878                 dev_err(&pdev->dev, "failed to register cpufreq notifier\n");
879                 goto err_irq;
880         }
881
882         /* Note, previous versions of the driver used i2c_add_adapter()
883          * to add the bus at any number. We now pass the bus number via
884          * the platform data, so if unset it will now default to always
885          * being bus 0.
886          */
887
888         i2c->adap.nr = pdata->bus_num;
889
890         ret = i2c_add_numbered_adapter(&i2c->adap);
891         if (ret < 0) {
892                 dev_err(&pdev->dev, "failed to add bus to i2c core\n");
893                 goto err_cpufreq;
894         }
895
896         platform_set_drvdata(pdev, i2c);
897
898         dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev));
899         return 0;
900
901  err_cpufreq:
902         s3c24xx_i2c_deregister_cpufreq(i2c);
903
904  err_irq:
905         free_irq(i2c->irq, i2c);
906
907  err_iomap:
908         iounmap(i2c->regs);
909
910  err_ioarea:
911         release_resource(i2c->ioarea);
912         kfree(i2c->ioarea);
913
914  err_clk:
915         clk_disable(i2c->clk);
916         clk_put(i2c->clk);
917
918  err_noclk:
919         kfree(i2c);
920         return ret;
921 }
922
923 /* s3c24xx_i2c_remove
924  *
925  * called when device is removed from the bus
926 */
927
928 static int s3c24xx_i2c_remove(struct platform_device *pdev)
929 {
930         struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
931
932         s3c24xx_i2c_deregister_cpufreq(i2c);
933
934         i2c_del_adapter(&i2c->adap);
935         free_irq(i2c->irq, i2c);
936
937         clk_disable(i2c->clk);
938         clk_put(i2c->clk);
939
940         iounmap(i2c->regs);
941
942         release_resource(i2c->ioarea);
943         kfree(i2c->ioarea);
944         kfree(i2c);
945
946         return 0;
947 }
948
949 #ifdef CONFIG_PM
950 static int s3c24xx_i2c_suspend_noirq(struct device *dev)
951 {
952         struct platform_device *pdev = to_platform_device(dev);
953         struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
954
955         i2c->suspended = 1;
956
957         return 0;
958 }
959
960 static int s3c24xx_i2c_resume(struct device *dev)
961 {
962         struct platform_device *pdev = to_platform_device(dev);
963         struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
964
965         i2c->suspended = 0;
966         s3c24xx_i2c_init(i2c);
967
968         return 0;
969 }
970
971 static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = {
972         .suspend_noirq = s3c24xx_i2c_suspend_noirq,
973         .resume = s3c24xx_i2c_resume,
974 };
975
976 #define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops)
977 #else
978 #define S3C24XX_DEV_PM_OPS NULL
979 #endif
980
981 /* device driver for platform bus bits */
982
983 static struct platform_device_id s3c24xx_driver_ids[] = {
984         {
985                 .name           = "s3c2410-i2c",
986                 .driver_data    = TYPE_S3C2410,
987         }, {
988                 .name           = "s3c2440-i2c",
989                 .driver_data    = TYPE_S3C2440,
990         }, { },
991 };
992 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
993
994 static struct platform_driver s3c24xx_i2c_driver = {
995         .probe          = s3c24xx_i2c_probe,
996         .remove         = s3c24xx_i2c_remove,
997         .id_table       = s3c24xx_driver_ids,
998         .driver         = {
999                 .owner  = THIS_MODULE,
1000                 .name   = "s3c-i2c",
1001                 .pm     = S3C24XX_DEV_PM_OPS,
1002         },
1003 };
1004
1005 static int __init i2c_adap_s3c_init(void)
1006 {
1007         return platform_driver_register(&s3c24xx_i2c_driver);
1008 }
1009 subsys_initcall(i2c_adap_s3c_init);
1010
1011 static void __exit i2c_adap_s3c_exit(void)
1012 {
1013         platform_driver_unregister(&s3c24xx_i2c_driver);
1014 }
1015 module_exit(i2c_adap_s3c_exit);
1016
1017 MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
1018 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
1019 MODULE_LICENSE("GPL");