drivers/i2c/busses/i2c-pxa.c

   1 /*
   2  *  i2c_adap_pxa.c
   3  *
   4  *  I2C adapter for the PXA I2C bus access.
   5  *
   6  *  Copyright (C) 2002 Intrinsyc Software Inc.
   7  *  Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
   8  *
   9  *  This program is free software; you can redistribute it and/or modify
  10  *  it under the terms of the GNU General Public License version 2 as
  11  *  published by the Free Software Foundation.
  12  *
  13  *  History:
  14  *    Apr 2002: Initial version [CS]
  15  *    Jun 2002: Properly seperated algo/adap [FB]
  16  *    Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
  17  *    Jan 2003: added limited signal handling [Kai-Uwe Bloem]
  18  *    Sep 2004: Major rework to ensure efficient bus handling [RMK]
  19  *    Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
  20  *    Feb 2005: Rework slave mode handling [RMK]
  21  */
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/i2c.h>
  25 #include <linux/i2c-id.h>
  26 #include <linux/init.h>
  27 #include <linux/time.h>
  28 #include <linux/sched.h>
  29 #include <linux/delay.h>
  30 #include <linux/errno.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/i2c-pxa.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/err.h>
  35 #include <linux/clk.h>
  36
  37 #include <mach/hardware.h>
  38 #include <asm/irq.h>
  39 #include <asm/io.h>
  40 #include <mach/i2c.h>
  41 #include <mach/pxa-regs.h>
  42
  43 struct pxa_i2c {
  44         spinlock_t              lock;
  45         wait_queue_head_t       wait;
  46         struct i2c_msg          *msg;
  47         unsigned int            msg_num;
  48         unsigned int            msg_idx;
  49         unsigned int            msg_ptr;
  50         unsigned int            slave_addr;
  51
  52         struct i2c_adapter      adap;
  53         struct clk              *clk;
  54 #ifdef CONFIG_I2C_PXA_SLAVE
  55         struct i2c_slave_client *slave;
  56 #endif
  57
  58         unsigned int            irqlogidx;
  59         u32                     isrlog[32];
  60         u32                     icrlog[32];
  61
  62         void __iomem            *reg_base;
  63         unsigned int            reg_shift;
  64
  65         unsigned long           iobase;
  66         unsigned long           iosize;
  67
  68         int                     irq;
  69         int                     use_pio;
  70 };
  71
  72 #define _IBMR(i2c)      ((i2c)->reg_base + (0x0 << (i2c)->reg_shift))
  73 #define _IDBR(i2c)      ((i2c)->reg_base + (0x4 << (i2c)->reg_shift))
  74 #define _ICR(i2c)       ((i2c)->reg_base + (0x8 << (i2c)->reg_shift))
  75 #define _ISR(i2c)       ((i2c)->reg_base + (0xc << (i2c)->reg_shift))
  76 #define _ISAR(i2c)      ((i2c)->reg_base + (0x10 << (i2c)->reg_shift))
  77
  78 /*
  79  * I2C Slave mode address
  80  */
  81 #define I2C_PXA_SLAVE_ADDR      0x1
  82
  83 #ifdef DEBUG
  84
  85 struct bits {
  86         u32     mask;
  87         const char *set;
  88         const char *unset;
  89 };
  90 #define PXA_BIT(m, s, u)        { .mask = m, .set = s, .unset = u }
  91
  92 static inline void
  93 decode_bits(const char *prefix, const struct bits *bits, int num, u32 val)
  94 {
  95         printk("%s %08x: ", prefix, val);
  96         while (num--) {
  97                 const char *str = val & bits->mask ? bits->set : bits->unset;
  98                 if (str)
  99                         printk("%s ", str);
 100                 bits++;
 101         }
 102 }
 103
 104 static const struct bits isr_bits[] = {
 105         PXA_BIT(ISR_RWM,        "RX",           "TX"),
 106         PXA_BIT(ISR_ACKNAK,     "NAK",          "ACK"),
 107         PXA_BIT(ISR_UB,         "Bsy",          "Rdy"),
 108         PXA_BIT(ISR_IBB,        "BusBsy",       "BusRdy"),
 109         PXA_BIT(ISR_SSD,        "SlaveStop",    NULL),
 110         PXA_BIT(ISR_ALD,        "ALD",          NULL),
 111         PXA_BIT(ISR_ITE,        "TxEmpty",      NULL),
 112         PXA_BIT(ISR_IRF,        "RxFull",       NULL),
 113         PXA_BIT(ISR_GCAD,       "GenCall",      NULL),
 114         PXA_BIT(ISR_SAD,        "SlaveAddr",    NULL),
 115         PXA_BIT(ISR_BED,        "BusErr",       NULL),
 116 };
 117
 118 static void decode_ISR(unsigned int val)
 119 {
 120         decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val);
 121         printk("\n");
 122 }
 123
 124 static const struct bits icr_bits[] = {
 125         PXA_BIT(ICR_START,  "START",    NULL),
 126         PXA_BIT(ICR_STOP,   "STOP",     NULL),
 127         PXA_BIT(ICR_ACKNAK, "ACKNAK",   NULL),
 128         PXA_BIT(ICR_TB,     "TB",       NULL),
 129         PXA_BIT(ICR_MA,     "MA",       NULL),
 130         PXA_BIT(ICR_SCLE,   "SCLE",     "scle"),
 131         PXA_BIT(ICR_IUE,    "IUE",      "iue"),
 132         PXA_BIT(ICR_GCD,    "GCD",      NULL),
 133         PXA_BIT(ICR_ITEIE,  "ITEIE",    NULL),
 134         PXA_BIT(ICR_IRFIE,  "IRFIE",    NULL),
 135         PXA_BIT(ICR_BEIE,   "BEIE",     NULL),
 136         PXA_BIT(ICR_SSDIE,  "SSDIE",    NULL),
 137         PXA_BIT(ICR_ALDIE,  "ALDIE",    NULL),
 138         PXA_BIT(ICR_SADIE,  "SADIE",    NULL),
 139         PXA_BIT(ICR_UR,     "UR",               "ur"),
 140 };
 141
 142 #ifdef CONFIG_I2C_PXA_SLAVE
 143 static void decode_ICR(unsigned int val)
 144 {
 145         decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val);
 146         printk("\n");
 147 }
 148 #endif
 149
 150 static unsigned int i2c_debug = DEBUG;
 151
 152 static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
 153 {
 154         dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno,
 155                 readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
 156 }
 157
 158 #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__)
 159 #else
 160 #define i2c_debug       0
 161
 162 #define show_state(i2c) do { } while (0)
 163 #define decode_ISR(val) do { } while (0)
 164 #define decode_ICR(val) do { } while (0)
 165 #endif
 166
 167 #define eedbg(lvl, x...) do { if ((lvl) < 1) { printk(KERN_DEBUG "" x); } } while(0)
 168
 169 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
 170 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id);
 171
 172 static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
 173 {
 174         unsigned int i;
 175         printk("i2c: error: %s\n", why);
 176         printk("i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n",
 177                 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
 178         printk("i2c: ICR: %08x ISR: %08x\n"
 179                "i2c: log: ", readl(_ICR(i2c)), readl(_ISR(i2c)));
 180         for (i = 0; i < i2c->irqlogidx; i++)
 181                 printk("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]);
 182         printk("\n");
 183 }
 184
 185 static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
 186 {
 187         return !(readl(_ICR(i2c)) & ICR_SCLE);
 188 }
 189
 190 static void i2c_pxa_abort(struct pxa_i2c *i2c)
 191 {
 192         int i = 250;
 193
 194         if (i2c_pxa_is_slavemode(i2c)) {
 195                 dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__);
 196                 return;
 197         }
 198
 199         while ((i > 0) && (readl(_IBMR(i2c)) & 0x1) == 0) {
 200                 unsigned long icr = readl(_ICR(i2c));
 201
 202                 icr &= ~ICR_START;
 203                 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB;
 204
 205                 writel(icr, _ICR(i2c));
 206
 207                 show_state(i2c);
 208
 209                 mdelay(1);
 210                 i --;
 211         }
 212
 213         writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP),
 214                _ICR(i2c));
 215 }
 216
 217 static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
 218 {
 219         int timeout = DEF_TIMEOUT;
 220
 221         while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
 222                 if ((readl(_ISR(i2c)) & ISR_SAD) != 0)
 223                         timeout += 4;
 224
 225                 msleep(2);
 226                 show_state(i2c);
 227         }
 228
 229         if (timeout <= 0)
 230                 show_state(i2c);
 231
 232         return timeout <= 0 ? I2C_RETRY : 0;
 233 }
 234
 235 static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
 236 {
 237         unsigned long timeout = jiffies + HZ*4;
 238
 239         while (time_before(jiffies, timeout)) {
 240                 if (i2c_debug > 1)
 241                         dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
 242                                 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
 243
 244                 if (readl(_ISR(i2c)) & ISR_SAD) {
 245                         if (i2c_debug > 0)
 246                                 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__);
 247                         goto out;
 248                 }
 249
 250                 /* wait for unit and bus being not busy, and we also do a
 251                  * quick check of the i2c lines themselves to ensure they've
 252                  * gone high...
 253                  */
 254                 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 && readl(_IBMR(i2c)) == 3) {
 255                         if (i2c_debug > 0)
 256                                 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
 257                         return 1;
 258                 }
 259
 260                 msleep(1);
 261         }
 262
 263         if (i2c_debug > 0)
 264                 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
 265  out:
 266         return 0;
 267 }
 268
 269 static int i2c_pxa_set_master(struct pxa_i2c *i2c)
 270 {
 271         if (i2c_debug)
 272                 dev_dbg(&i2c->adap.dev, "setting to bus master\n");
 273
 274         if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) {
 275                 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
 276                 if (!i2c_pxa_wait_master(i2c)) {
 277                         dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
 278                         return I2C_RETRY;
 279                 }
 280         }
 281
 282         writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
 283         return 0;
 284 }
 285
 286 #ifdef CONFIG_I2C_PXA_SLAVE
 287 static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
 288 {
 289         unsigned long timeout = jiffies + HZ*1;
 290
 291         /* wait for stop */
 292
 293         show_state(i2c);
 294
 295         while (time_before(jiffies, timeout)) {
 296                 if (i2c_debug > 1)
 297                         dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
 298                                 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
 299
 300                 if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 ||
 301                     (readl(_ISR(i2c)) & ISR_SAD) != 0 ||
 302                     (readl(_ICR(i2c)) & ICR_SCLE) == 0) {
 303                         if (i2c_debug > 1)
 304                                 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
 305                         return 1;
 306                 }
 307
 308                 msleep(1);
 309         }
 310
 311         if (i2c_debug > 0)
 312                 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
 313         return 0;
 314 }
 315
 316 /*
 317  * clear the hold on the bus, and take of anything else
 318  * that has been configured
 319  */
 320 static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
 321 {
 322         show_state(i2c);
 323
 324         if (errcode < 0) {
 325                 udelay(100);   /* simple delay */
 326         } else {
 327                 /* we need to wait for the stop condition to end */
 328
 329                 /* if we where in stop, then clear... */
 330                 if (readl(_ICR(i2c)) & ICR_STOP) {
 331                         udelay(100);
 332                         writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c));
 333                 }
 334
 335                 if (!i2c_pxa_wait_slave(i2c)) {
 336                         dev_err(&i2c->adap.dev, "%s: wait timedout\n",
 337                                 __func__);
 338                         return;
 339                 }
 340         }
 341
 342         writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c));
 343         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
 344
 345         if (i2c_debug) {
 346                 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c)));
 347                 decode_ICR(readl(_ICR(i2c)));
 348         }
 349 }
 350 #else
 351 #define i2c_pxa_set_slave(i2c, err)     do { } while (0)
 352 #endif
 353
 354 static void i2c_pxa_reset(struct pxa_i2c *i2c)
 355 {
 356         pr_debug("Resetting I2C Controller Unit\n");
 357
 358         /* abort any transfer currently under way */
 359         i2c_pxa_abort(i2c);
 360
 361         /* reset according to 9.8 */
 362         writel(ICR_UR, _ICR(i2c));
 363         writel(I2C_ISR_INIT, _ISR(i2c));
 364         writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c));
 365
 366         writel(i2c->slave_addr, _ISAR(i2c));
 367
 368         /* set control register values */
 369         writel(I2C_ICR_INIT, _ICR(i2c));
 370
 371 #ifdef CONFIG_I2C_PXA_SLAVE
 372         dev_info(&i2c->adap.dev, "Enabling slave mode\n");
 373         writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c));
 374 #endif
 375
 376         i2c_pxa_set_slave(i2c, 0);
 377
 378         /* enable unit */
 379         writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c));
 380         udelay(100);
 381 }
 382
 383
 384 #ifdef CONFIG_I2C_PXA_SLAVE
 385 /*
 386  * PXA I2C Slave mode
 387  */
 388
 389 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
 390 {
 391         if (isr & ISR_BED) {
 392                 /* what should we do here? */
 393         } else {
 394                 int ret = 0;
 395
 396                 if (i2c->slave != NULL)
 397                         ret = i2c->slave->read(i2c->slave->data);
 398
 399                 writel(ret, _IDBR(i2c));
 400                 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));   /* allow next byte */
 401         }
 402 }
 403
 404 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
 405 {
 406         unsigned int byte = readl(_IDBR(i2c));
 407
 408         if (i2c->slave != NULL)
 409                 i2c->slave->write(i2c->slave->data, byte);
 410
 411         writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
 412 }
 413
 414 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
 415 {
 416         int timeout;
 417
 418         if (i2c_debug > 0)
 419                 dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n",
 420                        (isr & ISR_RWM) ? 'r' : 't');
 421
 422         if (i2c->slave != NULL)
 423                 i2c->slave->event(i2c->slave->data,
 424                                  (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE);
 425
 426         /*
 427          * slave could interrupt in the middle of us generating a
 428          * start condition... if this happens, we'd better back off
 429          * and stop holding the poor thing up
 430          */
 431         writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
 432         writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
 433
 434         timeout = 0x10000;
 435
 436         while (1) {
 437                 if ((readl(_IBMR(i2c)) & 2) == 2)
 438                         break;
 439
 440                 timeout--;
 441
 442                 if (timeout <= 0) {
 443                         dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
 444                         break;
 445                 }
 446         }
 447
 448         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
 449 }
 450
 451 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
 452 {
 453         if (i2c_debug > 2)
 454                 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n");
 455
 456         if (i2c->slave != NULL)
 457                 i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP);
 458
 459         if (i2c_debug > 2)
 460                 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n");
 461
 462         /*
 463          * If we have a master-mode message waiting,
 464          * kick it off now that the slave has completed.
 465          */
 466         if (i2c->msg)
 467                 i2c_pxa_master_complete(i2c, I2C_RETRY);
 468 }
 469 #else
 470 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
 471 {
 472         if (isr & ISR_BED) {
 473                 /* what should we do here? */
 474         } else {
 475                 writel(0, _IDBR(i2c));
 476                 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
 477         }
 478 }
 479
 480 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
 481 {
 482         writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
 483 }
 484
 485 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
 486 {
 487         int timeout;
 488
 489         /*
 490          * slave could interrupt in the middle of us generating a
 491          * start condition... if this happens, we'd better back off
 492          * and stop holding the poor thing up
 493          */
 494         writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
 495         writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
 496
 497         timeout = 0x10000;
 498
 499         while (1) {
 500                 if ((readl(_IBMR(i2c)) & 2) == 2)
 501                         break;
 502
 503                 timeout--;
 504
 505                 if (timeout <= 0) {
 506                         dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
 507                         break;
 508                 }
 509         }
 510
 511         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
 512 }
 513
 514 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
 515 {
 516         if (i2c->msg)
 517                 i2c_pxa_master_complete(i2c, I2C_RETRY);
 518 }
 519 #endif
 520
 521 /*
 522  * PXA I2C Master mode
 523  */
 524
 525 static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg)
 526 {
 527         unsigned int addr = (msg->addr & 0x7f) << 1;
 528
 529         if (msg->flags & I2C_M_RD)
 530                 addr |= 1;
 531
 532         return addr;
 533 }
 534
 535 static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
 536 {
 537         u32 icr;
 538
 539         /*
 540          * Step 1: target slave address into IDBR
 541          */
 542         writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
 543
 544         /*
 545          * Step 2: initiate the write.
 546          */
 547         icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
 548         writel(icr | ICR_START | ICR_TB, _ICR(i2c));
 549 }
 550
 551 static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c)
 552 {
 553         u32 icr;
 554
 555         /*
 556          * Clear the STOP and ACK flags
 557          */
 558         icr = readl(_ICR(i2c));
 559         icr &= ~(ICR_STOP | ICR_ACKNAK);
 560         writel(icr, _ICR(i2c));
 561 }
 562
 563 static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c)
 564 {
 565         /* make timeout the same as for interrupt based functions */
 566         long timeout = 2 * DEF_TIMEOUT;
 567
 568         /*
 569          * Wait for the bus to become free.
 570          */
 571         while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
 572                 udelay(1000);
 573                 show_state(i2c);
 574         }
 575
 576         if (timeout <= 0) {
 577                 show_state(i2c);
 578                 dev_err(&i2c->adap.dev,
 579                         "i2c_pxa: timeout waiting for bus free\n");
 580                 return I2C_RETRY;
 581         }
 582
 583         /*
 584          * Set master mode.
 585          */
 586         writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
 587
 588         return 0;
 589 }
 590
 591 static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c,
 592                                struct i2c_msg *msg, int num)
 593 {
 594         unsigned long timeout = 500000; /* 5 seconds */
 595         int ret = 0;
 596
 597         ret = i2c_pxa_pio_set_master(i2c);
 598         if (ret)
 599                 goto out;
 600
 601         i2c->msg = msg;
 602         i2c->msg_num = num;
 603         i2c->msg_idx = 0;
 604         i2c->msg_ptr = 0;
 605         i2c->irqlogidx = 0;
 606
 607         i2c_pxa_start_message(i2c);
 608
 609         while (timeout-- && i2c->msg_num > 0) {
 610                 i2c_pxa_handler(0, i2c);
 611                 udelay(10);
 612         }
 613
 614         i2c_pxa_stop_message(i2c);
 615
 616         /*
 617          * We place the return code in i2c->msg_idx.
 618          */
 619         ret = i2c->msg_idx;
 620
 621 out:
 622         if (timeout == 0)
 623                 i2c_pxa_scream_blue_murder(i2c, "timeout");
 624
 625         return ret;
 626 }
 627
 628 /*
 629  * We are protected by the adapter bus mutex.
 630  */
 631 static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num)
 632 {
 633         long timeout;
 634         int ret;
 635
 636         /*
 637          * Wait for the bus to become free.
 638          */
 639         ret = i2c_pxa_wait_bus_not_busy(i2c);
 640         if (ret) {
 641                 dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
 642                 goto out;
 643         }
 644
 645         /*
 646          * Set master mode.
 647          */
 648         ret = i2c_pxa_set_master(i2c);
 649         if (ret) {
 650                 dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
 651                 goto out;
 652         }
 653
 654         spin_lock_irq(&i2c->lock);
 655
 656         i2c->msg = msg;
 657         i2c->msg_num = num;
 658         i2c->msg_idx = 0;
 659         i2c->msg_ptr = 0;
 660         i2c->irqlogidx = 0;
 661
 662         i2c_pxa_start_message(i2c);
 663
 664         spin_unlock_irq(&i2c->lock);
 665
 666         /*
 667          * The rest of the processing occurs in the interrupt handler.
 668          */
 669         timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
 670         i2c_pxa_stop_message(i2c);
 671
 672         /*
 673          * We place the return code in i2c->msg_idx.
 674          */
 675         ret = i2c->msg_idx;
 676
 677         if (timeout == 0)
 678                 i2c_pxa_scream_blue_murder(i2c, "timeout");
 679
 680  out:
 681         return ret;
 682 }
 683
 684 static int i2c_pxa_pio_xfer(struct i2c_adapter *adap,
 685                             struct i2c_msg msgs[], int num)
 686 {
 687         struct pxa_i2c *i2c = adap->algo_data;
 688         int ret, i;
 689
 690         /* If the I2C controller is disabled we need to reset it
 691           (probably due to a suspend/resume destroying state). We do
 692           this here as we can then avoid worrying about resuming the
 693           controller before its users. */
 694         if (!(readl(_ICR(i2c)) & ICR_IUE))
 695                 i2c_pxa_reset(i2c);
 696
 697         for (i = adap->retries; i >= 0; i--) {
 698                 ret = i2c_pxa_do_pio_xfer(i2c, msgs, num);
 699                 if (ret != I2C_RETRY)
 700                         goto out;
 701
 702                 if (i2c_debug)
 703                         dev_dbg(&adap->dev, "Retrying transmission\n");
 704                 udelay(100);
 705         }
 706         i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
 707         ret = -EREMOTEIO;
 708  out:
 709         i2c_pxa_set_slave(i2c, ret);
 710         return ret;
 711 }
 712
 713 /*
 714  * i2c_pxa_master_complete - complete the message and wake up.
 715  */
 716 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret)
 717 {
 718         i2c->msg_ptr = 0;
 719         i2c->msg = NULL;
 720         i2c->msg_idx ++;
 721         i2c->msg_num = 0;
 722         if (ret)
 723                 i2c->msg_idx = ret;
 724         if (!i2c->use_pio)
 725                 wake_up(&i2c->wait);
 726 }
 727
 728 static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
 729 {
 730         u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
 731
 732  again:
 733         /*
 734          * If ISR_ALD is set, we lost arbitration.
 735          */
 736         if (isr & ISR_ALD) {
 737                 /*
 738                  * Do we need to do anything here?  The PXA docs
 739                  * are vague about what happens.
 740                  */
 741                 i2c_pxa_scream_blue_murder(i2c, "ALD set");
 742
 743                 /*
 744                  * We ignore this error.  We seem to see spurious ALDs
 745                  * for seemingly no reason.  If we handle them as I think
 746                  * they should, we end up causing an I2C error, which
 747                  * is painful for some systems.
 748                  */
 749                 return; /* ignore */
 750         }
 751
 752         if (isr & ISR_BED) {
 753                 int ret = BUS_ERROR;
 754
 755                 /*
 756                  * I2C bus error - either the device NAK'd us, or
 757                  * something more serious happened.  If we were NAK'd
 758                  * on the initial address phase, we can retry.
 759                  */
 760                 if (isr & ISR_ACKNAK) {
 761                         if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)
 762                                 ret = I2C_RETRY;
 763                         else
 764                                 ret = XFER_NAKED;
 765                 }
 766                 i2c_pxa_master_complete(i2c, ret);
 767         } else if (isr & ISR_RWM) {
 768                 /*
 769                  * Read mode.  We have just sent the address byte, and
 770                  * now we must initiate the transfer.
 771                  */
 772                 if (i2c->msg_ptr == i2c->msg->len - 1 &&
 773                     i2c->msg_idx == i2c->msg_num - 1)
 774                         icr |= ICR_STOP | ICR_ACKNAK;
 775
 776                 icr |= ICR_ALDIE | ICR_TB;
 777         } else if (i2c->msg_ptr < i2c->msg->len) {
 778                 /*
 779                  * Write mode.  Write the next data byte.
 780                  */
 781                 writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c));
 782
 783                 icr |= ICR_ALDIE | ICR_TB;
 784
 785                 /*
 786                  * If this is the last byte of the last message, send
 787                  * a STOP.
 788                  */
 789                 if (i2c->msg_ptr == i2c->msg->len &&
 790                     i2c->msg_idx == i2c->msg_num - 1)
 791                         icr |= ICR_STOP;
 792         } else if (i2c->msg_idx < i2c->msg_num - 1) {
 793                 /*
 794                  * Next segment of the message.
 795                  */
 796                 i2c->msg_ptr = 0;
 797                 i2c->msg_idx ++;
 798                 i2c->msg++;
 799
 800                 /*
 801                  * If we aren't doing a repeated start and address,
 802                  * go back and try to send the next byte.  Note that
 803                  * we do not support switching the R/W direction here.
 804                  */
 805                 if (i2c->msg->flags & I2C_M_NOSTART)
 806                         goto again;
 807
 808                 /*
 809                  * Write the next address.
 810                  */
 811                 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
 812
 813                 /*
 814                  * And trigger a repeated start, and send the byte.
 815                  */
 816                 icr &= ~ICR_ALDIE;
 817                 icr |= ICR_START | ICR_TB;
 818         } else {
 819                 if (i2c->msg->len == 0) {
 820                         /*
 821                          * Device probes have a message length of zero
 822                          * and need the bus to be reset before it can
 823                          * be used again.
 824                          */
 825                         i2c_pxa_reset(i2c);
 826                 }
 827                 i2c_pxa_master_complete(i2c, 0);
 828         }
 829
 830         i2c->icrlog[i2c->irqlogidx-1] = icr;
 831
 832         writel(icr, _ICR(i2c));
 833         show_state(i2c);
 834 }
 835
 836 static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
 837 {
 838         u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
 839
 840         /*
 841          * Read the byte.
 842          */
 843         i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c));
 844
 845         if (i2c->msg_ptr < i2c->msg->len) {
 846                 /*
 847                  * If this is the last byte of the last
 848                  * message, send a STOP.
 849                  */
 850                 if (i2c->msg_ptr == i2c->msg->len - 1)
 851                         icr |= ICR_STOP | ICR_ACKNAK;
 852
 853                 icr |= ICR_ALDIE | ICR_TB;
 854         } else {
 855                 i2c_pxa_master_complete(i2c, 0);
 856         }
 857
 858         i2c->icrlog[i2c->irqlogidx-1] = icr;
 859
 860         writel(icr, _ICR(i2c));
 861 }
 862
 863 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id)
 864 {
 865         struct pxa_i2c *i2c = dev_id;
 866         u32 isr = readl(_ISR(i2c));
 867
 868         if (i2c_debug > 2 && 0) {
 869                 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
 870                         __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c)));
 871                 decode_ISR(isr);
 872         }
 873
 874         if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog))
 875                 i2c->isrlog[i2c->irqlogidx++] = isr;
 876
 877         show_state(i2c);
 878
 879         /*
 880          * Always clear all pending IRQs.
 881          */
 882         writel(isr & (ISR_SSD|ISR_ALD|ISR_ITE|ISR_IRF|ISR_SAD|ISR_BED), _ISR(i2c));
 883
 884         if (isr & ISR_SAD)
 885                 i2c_pxa_slave_start(i2c, isr);
 886         if (isr & ISR_SSD)
 887                 i2c_pxa_slave_stop(i2c);
 888
 889         if (i2c_pxa_is_slavemode(i2c)) {
 890                 if (isr & ISR_ITE)
 891                         i2c_pxa_slave_txempty(i2c, isr);
 892                 if (isr & ISR_IRF)
 893                         i2c_pxa_slave_rxfull(i2c, isr);
 894         } else if (i2c->msg) {
 895                 if (isr & ISR_ITE)
 896                         i2c_pxa_irq_txempty(i2c, isr);
 897                 if (isr & ISR_IRF)
 898                         i2c_pxa_irq_rxfull(i2c, isr);
 899         } else {
 900                 i2c_pxa_scream_blue_murder(i2c, "spurious irq");
 901         }
 902
 903         return IRQ_HANDLED;
 904 }
 905
 906
 907 static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 908 {
 909         struct pxa_i2c *i2c = adap->algo_data;
 910         int ret, i;
 911
 912         for (i = adap->retries; i >= 0; i--) {
 913                 ret = i2c_pxa_do_xfer(i2c, msgs, num);
 914                 if (ret != I2C_RETRY)
 915                         goto out;
 916
 917                 if (i2c_debug)
 918                         dev_dbg(&adap->dev, "Retrying transmission\n");
 919                 udelay(100);
 920         }
 921         i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
 922         ret = -EREMOTEIO;
 923  out:
 924         i2c_pxa_set_slave(i2c, ret);
 925         return ret;
 926 }
 927
 928 static u32 i2c_pxa_functionality(struct i2c_adapter *adap)
 929 {
 930         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 931 }
 932
 933 static const struct i2c_algorithm i2c_pxa_algorithm = {
 934         .master_xfer    = i2c_pxa_xfer,
 935         .functionality  = i2c_pxa_functionality,
 936 };
 937
 938 static const struct i2c_algorithm i2c_pxa_pio_algorithm = {
 939         .master_xfer    = i2c_pxa_pio_xfer,
 940         .functionality  = i2c_pxa_functionality,
 941 };
 942
 943 #define res_len(r)              ((r)->end - (r)->start + 1)
 944 static int i2c_pxa_probe(struct platform_device *dev)
 945 {
 946         struct pxa_i2c *i2c;
 947         struct resource *res;
 948         struct i2c_pxa_platform_data *plat = dev->dev.platform_data;
 949         int ret;
 950         int irq;
 951
 952         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
 953         irq = platform_get_irq(dev, 0);
 954         if (res == NULL || irq < 0)
 955                 return -ENODEV;
 956
 957         if (!request_mem_region(res->start, res_len(res), res->name))
 958                 return -ENOMEM;
 959
 960         i2c = kzalloc(sizeof(struct pxa_i2c), GFP_KERNEL);
 961         if (!i2c) {
 962                 ret = -ENOMEM;
 963                 goto emalloc;
 964         }
 965
 966         i2c->adap.owner   = THIS_MODULE;
 967         i2c->adap.retries = 5;
 968
 969         spin_lock_init(&i2c->lock);
 970         init_waitqueue_head(&i2c->wait);
 971
 972         /*
 973          * If "dev->id" is negative we consider it as zero.
 974          * The reason to do so is to avoid sysfs names that only make
 975          * sense when there are multiple adapters.
 976          */
 977         i2c->adap.nr = dev->id != -1 ? dev->id : 0;
 978         snprintf(i2c->adap.name, sizeof(i2c->adap.name), "pxa_i2c-i2c.%u",
 979                  i2c->adap.nr);
 980
 981         i2c->clk = clk_get(&dev->dev, "I2CCLK");
 982         if (IS_ERR(i2c->clk)) {
 983                 ret = PTR_ERR(i2c->clk);
 984                 goto eclk;
 985         }
 986
 987         i2c->reg_base = ioremap(res->start, res_len(res));
 988         if (!i2c->reg_base) {
 989                 ret = -EIO;
 990                 goto eremap;
 991         }
 992         i2c->reg_shift = (cpu_is_pxa3xx() && (dev->id == 1)) ? 0 : 1;
 993
 994         i2c->iobase = res->start;
 995         i2c->iosize = res_len(res);
 996
 997         i2c->irq = irq;
 998
 999         i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
1000
1001 #ifdef CONFIG_I2C_PXA_SLAVE
1002         if (plat) {
1003                 i2c->slave_addr = plat->slave_addr;
1004                 i2c->slave = plat->slave;
1005         }
1006 #endif
1007
1008         clk_enable(i2c->clk);
1009
1010         if (plat) {
1011                 i2c->adap.class = plat->class;
1012                 i2c->use_pio = plat->use_pio;
1013         }
1014
1015         if (i2c->use_pio) {
1016                 i2c->adap.algo = &i2c_pxa_pio_algorithm;
1017         } else {
1018                 i2c->adap.algo = &i2c_pxa_algorithm;
1019                 ret = request_irq(irq, i2c_pxa_handler, IRQF_DISABLED,
1020                                   i2c->adap.name, i2c);
1021                 if (ret)
1022                         goto ereqirq;
1023         }
1024
1025         i2c_pxa_reset(i2c);
1026
1027         i2c->adap.algo_data = i2c;
1028         i2c->adap.dev.parent = &dev->dev;
1029
1030         ret = i2c_add_numbered_adapter(&i2c->adap);
1031         if (ret < 0) {
1032                 printk(KERN_INFO "I2C: Failed to add bus\n");
1033                 goto eadapt;
1034         }
1035
1036         platform_set_drvdata(dev, i2c);
1037
1038 #ifdef CONFIG_I2C_PXA_SLAVE
1039         printk(KERN_INFO "I2C: %s: PXA I2C adapter, slave address %d\n",
1040                i2c->adap.dev.bus_id, i2c->slave_addr);
1041 #else
1042         printk(KERN_INFO "I2C: %s: PXA I2C adapter\n",
1043                i2c->adap.dev.bus_id);
1044 #endif
1045         return 0;
1046
1047 eadapt:
1048         if (!i2c->use_pio)
1049                 free_irq(irq, i2c);
1050 ereqirq:
1051         clk_disable(i2c->clk);
1052         iounmap(i2c->reg_base);
1053 eremap:
1054         clk_put(i2c->clk);
1055 eclk:
1056         kfree(i2c);
1057 emalloc:
1058         release_mem_region(res->start, res_len(res));
1059         return ret;
1060 }
1061
1062 static int __exit i2c_pxa_remove(struct platform_device *dev)
1063 {
1064         struct pxa_i2c *i2c = platform_get_drvdata(dev);
1065
1066         platform_set_drvdata(dev, NULL);
1067
1068         i2c_del_adapter(&i2c->adap);
1069         if (!i2c->use_pio)
1070                 free_irq(i2c->irq, i2c);
1071
1072         clk_disable(i2c->clk);
1073         clk_put(i2c->clk);
1074
1075         iounmap(i2c->reg_base);
1076         release_mem_region(i2c->iobase, i2c->iosize);
1077         kfree(i2c);
1078
1079         return 0;
1080 }
1081
1082 #ifdef CONFIG_PM
1083 static int i2c_pxa_suspend_late(struct platform_device *dev, pm_message_t state)
1084 {
1085         struct pxa_i2c *i2c = platform_get_drvdata(dev);
1086         clk_disable(i2c->clk);
1087         return 0;
1088 }
1089
1090 static int i2c_pxa_resume_early(struct platform_device *dev)
1091 {
1092         struct pxa_i2c *i2c = platform_get_drvdata(dev);
1093
1094         clk_enable(i2c->clk);
1095         i2c_pxa_reset(i2c);
1096
1097         return 0;
1098 }
1099 #else
1100 #define i2c_pxa_suspend_late NULL
1101 #define i2c_pxa_resume_early NULL
1102 #endif
1103
1104 static struct platform_driver i2c_pxa_driver = {
1105         .probe          = i2c_pxa_probe,
1106         .remove         = __exit_p(i2c_pxa_remove),
1107         .suspend_late   = i2c_pxa_suspend_late,
1108         .resume_early   = i2c_pxa_resume_early,
1109         .driver         = {
1110                 .name   = "pxa2xx-i2c",
1111                 .owner  = THIS_MODULE,
1112         },
1113 };
1114
1115 static int __init i2c_adap_pxa_init(void)
1116 {
1117         return platform_driver_register(&i2c_pxa_driver);
1118 }
1119
1120 static void __exit i2c_adap_pxa_exit(void)
1121 {
1122         platform_driver_unregister(&i2c_pxa_driver);
1123 }
1124
1125 MODULE_LICENSE("GPL");
1126 MODULE_ALIAS("platform:pxa2xx-i2c");
1127
1128 subsys_initcall(i2c_adap_pxa_init);
1129 module_exit(i2c_adap_pxa_exit);