i2c: Rename the PEC functionality bit
[linux-3.10.git] / drivers / i2c / busses / i2c-amd8111.c
1 /*
2  * SMBus 2.0 driver for AMD-8111 IO-Hub.
3  *
4  * Copyright (c) 2002 Vojtech Pavlik
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation version 2.
9  */
10
11 #include <linux/module.h>
12 #include <linux/pci.h>
13 #include <linux/kernel.h>
14 #include <linux/stddef.h>
15 #include <linux/ioport.h>
16 #include <linux/init.h>
17 #include <linux/i2c.h>
18 #include <linux/delay.h>
19 #include <asm/io.h>
20
21 MODULE_LICENSE("GPL");
22 MODULE_AUTHOR ("Vojtech Pavlik <vojtech@suse.cz>");
23 MODULE_DESCRIPTION("AMD8111 SMBus 2.0 driver");
24
25 struct amd_smbus {
26         struct pci_dev *dev;
27         struct i2c_adapter adapter;
28         int base;
29         int size;
30 };
31
32 static struct pci_driver amd8111_driver;
33
34 /*
35  * AMD PCI control registers definitions.
36  */
37
38 #define AMD_PCI_MISC    0x48
39
40 #define AMD_PCI_MISC_SCI        0x04    /* deliver SCI */
41 #define AMD_PCI_MISC_INT        0x02    /* deliver PCI IRQ */
42 #define AMD_PCI_MISC_SPEEDUP    0x01    /* 16x clock speedup */
43
44 /*
45  * ACPI 2.0 chapter 13 PCI interface definitions.
46  */
47
48 #define AMD_EC_DATA     0x00    /* data register */
49 #define AMD_EC_SC       0x04    /* status of controller */
50 #define AMD_EC_CMD      0x04    /* command register */
51 #define AMD_EC_ICR      0x08    /* interrupt control register */
52
53 #define AMD_EC_SC_SMI   0x04    /* smi event pending */
54 #define AMD_EC_SC_SCI   0x02    /* sci event pending */
55 #define AMD_EC_SC_BURST 0x01    /* burst mode enabled */
56 #define AMD_EC_SC_CMD   0x08    /* byte in data reg is command */
57 #define AMD_EC_SC_IBF   0x02    /* data ready for embedded controller */
58 #define AMD_EC_SC_OBF   0x01    /* data ready for host */
59
60 #define AMD_EC_CMD_RD   0x80    /* read EC */
61 #define AMD_EC_CMD_WR   0x81    /* write EC */
62 #define AMD_EC_CMD_BE   0x82    /* enable burst mode */
63 #define AMD_EC_CMD_BD   0x83    /* disable burst mode */
64 #define AMD_EC_CMD_QR   0x84    /* query EC */
65
66 /*
67  * ACPI 2.0 chapter 13 access of registers of the EC
68  */
69
70 static unsigned int amd_ec_wait_write(struct amd_smbus *smbus)
71 {
72         int timeout = 500;
73
74         while (timeout-- && (inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_IBF))
75                 udelay(1);
76
77         if (!timeout) {
78                 dev_warn(&smbus->dev->dev,
79                          "Timeout while waiting for IBF to clear\n");
80                 return -1;
81         }
82
83         return 0;
84 }
85
86 static unsigned int amd_ec_wait_read(struct amd_smbus *smbus)
87 {
88         int timeout = 500;
89
90         while (timeout-- && (~inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_OBF))
91                 udelay(1);
92
93         if (!timeout) {
94                 dev_warn(&smbus->dev->dev,
95                          "Timeout while waiting for OBF to set\n");
96                 return -1;
97         }
98
99         return 0;
100 }
101
102 static unsigned int amd_ec_read(struct amd_smbus *smbus, unsigned char address,
103                 unsigned char *data)
104 {
105         if (amd_ec_wait_write(smbus))
106                 return -1;
107         outb(AMD_EC_CMD_RD, smbus->base + AMD_EC_CMD);
108
109         if (amd_ec_wait_write(smbus))
110                 return -1;
111         outb(address, smbus->base + AMD_EC_DATA);
112
113         if (amd_ec_wait_read(smbus))
114                 return -1;
115         *data = inb(smbus->base + AMD_EC_DATA);
116
117         return 0;
118 }
119
120 static unsigned int amd_ec_write(struct amd_smbus *smbus, unsigned char address,
121                 unsigned char data)
122 {
123         if (amd_ec_wait_write(smbus))
124                 return -1;
125         outb(AMD_EC_CMD_WR, smbus->base + AMD_EC_CMD);
126
127         if (amd_ec_wait_write(smbus))
128                 return -1;
129         outb(address, smbus->base + AMD_EC_DATA);
130
131         if (amd_ec_wait_write(smbus))
132                 return -1;
133         outb(data, smbus->base + AMD_EC_DATA);
134
135         return 0;
136 }
137
138 /*
139  * ACPI 2.0 chapter 13 SMBus 2.0 EC register model
140  */
141
142 #define AMD_SMB_PRTCL   0x00    /* protocol, PEC */
143 #define AMD_SMB_STS     0x01    /* status */
144 #define AMD_SMB_ADDR    0x02    /* address */
145 #define AMD_SMB_CMD     0x03    /* command */
146 #define AMD_SMB_DATA    0x04    /* 32 data registers */
147 #define AMD_SMB_BCNT    0x24    /* number of data bytes */
148 #define AMD_SMB_ALRM_A  0x25    /* alarm address */
149 #define AMD_SMB_ALRM_D  0x26    /* 2 bytes alarm data */
150
151 #define AMD_SMB_STS_DONE        0x80
152 #define AMD_SMB_STS_ALRM        0x40
153 #define AMD_SMB_STS_RES         0x20
154 #define AMD_SMB_STS_STATUS      0x1f
155
156 #define AMD_SMB_STATUS_OK       0x00
157 #define AMD_SMB_STATUS_FAIL     0x07
158 #define AMD_SMB_STATUS_DNAK     0x10
159 #define AMD_SMB_STATUS_DERR     0x11
160 #define AMD_SMB_STATUS_CMD_DENY 0x12
161 #define AMD_SMB_STATUS_UNKNOWN  0x13
162 #define AMD_SMB_STATUS_ACC_DENY 0x17
163 #define AMD_SMB_STATUS_TIMEOUT  0x18
164 #define AMD_SMB_STATUS_NOTSUP   0x19
165 #define AMD_SMB_STATUS_BUSY     0x1A
166 #define AMD_SMB_STATUS_PEC      0x1F
167
168 #define AMD_SMB_PRTCL_WRITE             0x00
169 #define AMD_SMB_PRTCL_READ              0x01
170 #define AMD_SMB_PRTCL_QUICK             0x02
171 #define AMD_SMB_PRTCL_BYTE              0x04
172 #define AMD_SMB_PRTCL_BYTE_DATA         0x06
173 #define AMD_SMB_PRTCL_WORD_DATA         0x08
174 #define AMD_SMB_PRTCL_BLOCK_DATA        0x0a
175 #define AMD_SMB_PRTCL_PROC_CALL         0x0c
176 #define AMD_SMB_PRTCL_BLOCK_PROC_CALL   0x0d
177 #define AMD_SMB_PRTCL_I2C_BLOCK_DATA    0x4a
178 #define AMD_SMB_PRTCL_PEC               0x80
179
180
181 static s32 amd8111_access(struct i2c_adapter * adap, u16 addr,
182                 unsigned short flags, char read_write, u8 command, int size,
183                 union i2c_smbus_data * data)
184 {
185         struct amd_smbus *smbus = adap->algo_data;
186         unsigned char protocol, len, pec, temp[2];
187         int i;
188
189         protocol = (read_write == I2C_SMBUS_READ) ? AMD_SMB_PRTCL_READ
190                                                   : AMD_SMB_PRTCL_WRITE;
191         pec = (flags & I2C_CLIENT_PEC) ? AMD_SMB_PRTCL_PEC : 0;
192
193         switch (size) {
194                 case I2C_SMBUS_QUICK:
195                         protocol |= AMD_SMB_PRTCL_QUICK;
196                         read_write = I2C_SMBUS_WRITE;
197                         break;
198
199                 case I2C_SMBUS_BYTE:
200                         if (read_write == I2C_SMBUS_WRITE)
201                                 amd_ec_write(smbus, AMD_SMB_CMD, command);
202                         protocol |= AMD_SMB_PRTCL_BYTE;
203                         break;
204
205                 case I2C_SMBUS_BYTE_DATA:
206                         amd_ec_write(smbus, AMD_SMB_CMD, command);
207                         if (read_write == I2C_SMBUS_WRITE)
208                                 amd_ec_write(smbus, AMD_SMB_DATA, data->byte);
209                         protocol |= AMD_SMB_PRTCL_BYTE_DATA;
210                         break;
211
212                 case I2C_SMBUS_WORD_DATA:
213                         amd_ec_write(smbus, AMD_SMB_CMD, command);
214                         if (read_write == I2C_SMBUS_WRITE) {
215                                 amd_ec_write(smbus, AMD_SMB_DATA,
216                                              data->word & 0xff);
217                                 amd_ec_write(smbus, AMD_SMB_DATA + 1,
218                                              data->word >> 8);
219                         }
220                         protocol |= AMD_SMB_PRTCL_WORD_DATA | pec;
221                         break;
222
223                 case I2C_SMBUS_BLOCK_DATA:
224                         amd_ec_write(smbus, AMD_SMB_CMD, command);
225                         if (read_write == I2C_SMBUS_WRITE) {
226                                 len = min_t(u8, data->block[0],
227                                             I2C_SMBUS_BLOCK_MAX);
228                                 amd_ec_write(smbus, AMD_SMB_BCNT, len);
229                                 for (i = 0; i < len; i++)
230                                         amd_ec_write(smbus, AMD_SMB_DATA + i,
231                                                      data->block[i + 1]);
232                         }
233                         protocol |= AMD_SMB_PRTCL_BLOCK_DATA | pec;
234                         break;
235
236                 case I2C_SMBUS_I2C_BLOCK_DATA:
237                         len = min_t(u8, data->block[0],
238                                     I2C_SMBUS_BLOCK_MAX);
239                         amd_ec_write(smbus, AMD_SMB_CMD, command);
240                         amd_ec_write(smbus, AMD_SMB_BCNT, len);
241                         if (read_write == I2C_SMBUS_WRITE)
242                                 for (i = 0; i < len; i++)
243                                         amd_ec_write(smbus, AMD_SMB_DATA + i,
244                                                      data->block[i + 1]);
245                         protocol |= AMD_SMB_PRTCL_I2C_BLOCK_DATA;
246                         break;
247
248                 case I2C_SMBUS_PROC_CALL:
249                         amd_ec_write(smbus, AMD_SMB_CMD, command);
250                         amd_ec_write(smbus, AMD_SMB_DATA, data->word & 0xff);
251                         amd_ec_write(smbus, AMD_SMB_DATA + 1, data->word >> 8);
252                         protocol = AMD_SMB_PRTCL_PROC_CALL | pec;
253                         read_write = I2C_SMBUS_READ;
254                         break;
255
256                 case I2C_SMBUS_BLOCK_PROC_CALL:
257                         len = min_t(u8, data->block[0],
258                                     I2C_SMBUS_BLOCK_MAX - 1);
259                         amd_ec_write(smbus, AMD_SMB_CMD, command);
260                         amd_ec_write(smbus, AMD_SMB_BCNT, len);
261                         for (i = 0; i < len; i++)
262                                 amd_ec_write(smbus, AMD_SMB_DATA + i,
263                                              data->block[i + 1]);
264                         protocol = AMD_SMB_PRTCL_BLOCK_PROC_CALL | pec;
265                         read_write = I2C_SMBUS_READ;
266                         break;
267
268                 default:
269                         dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
270                         return -1;
271         }
272
273         amd_ec_write(smbus, AMD_SMB_ADDR, addr << 1);
274         amd_ec_write(smbus, AMD_SMB_PRTCL, protocol);
275
276         amd_ec_read(smbus, AMD_SMB_STS, temp + 0);
277
278         if (~temp[0] & AMD_SMB_STS_DONE) {
279                 udelay(500);
280                 amd_ec_read(smbus, AMD_SMB_STS, temp + 0);
281         }
282
283         if (~temp[0] & AMD_SMB_STS_DONE) {
284                 msleep(1);
285                 amd_ec_read(smbus, AMD_SMB_STS, temp + 0);
286         }
287
288         if ((~temp[0] & AMD_SMB_STS_DONE) || (temp[0] & AMD_SMB_STS_STATUS))
289                 return -1;
290
291         if (read_write == I2C_SMBUS_WRITE)
292                 return 0;
293
294         switch (size) {
295                 case I2C_SMBUS_BYTE:
296                 case I2C_SMBUS_BYTE_DATA:
297                         amd_ec_read(smbus, AMD_SMB_DATA, &data->byte);
298                         break;
299
300                 case I2C_SMBUS_WORD_DATA:
301                 case I2C_SMBUS_PROC_CALL:
302                         amd_ec_read(smbus, AMD_SMB_DATA, temp + 0);
303                         amd_ec_read(smbus, AMD_SMB_DATA + 1, temp + 1);
304                         data->word = (temp[1] << 8) | temp[0];
305                         break;
306
307                 case I2C_SMBUS_BLOCK_DATA:
308                 case I2C_SMBUS_BLOCK_PROC_CALL:
309                         amd_ec_read(smbus, AMD_SMB_BCNT, &len);
310                         len = min_t(u8, len, I2C_SMBUS_BLOCK_MAX);
311                 case I2C_SMBUS_I2C_BLOCK_DATA:
312                         for (i = 0; i < len; i++)
313                                 amd_ec_read(smbus, AMD_SMB_DATA + i,
314                                             data->block + i + 1);
315                         data->block[0] = len;
316                         break;
317         }
318
319         return 0;
320 }
321
322
323 static u32 amd8111_func(struct i2c_adapter *adapter)
324 {
325         return  I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
326                 I2C_FUNC_SMBUS_BYTE_DATA |
327                 I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_BLOCK_DATA |
328                 I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
329                 I2C_FUNC_SMBUS_I2C_BLOCK | I2C_FUNC_SMBUS_PEC;
330 }
331
332 static const struct i2c_algorithm smbus_algorithm = {
333         .smbus_xfer = amd8111_access,
334         .functionality = amd8111_func,
335 };
336
337
338 static struct pci_device_id amd8111_ids[] = {
339         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS2) },
340         { 0, }
341 };
342
343 MODULE_DEVICE_TABLE (pci, amd8111_ids);
344
345 static int __devinit amd8111_probe(struct pci_dev *dev,
346                 const struct pci_device_id *id)
347 {
348         struct amd_smbus *smbus;
349         int error;
350
351         if (!(pci_resource_flags(dev, 0) & IORESOURCE_IO))
352                 return -ENODEV;
353
354         smbus = kzalloc(sizeof(struct amd_smbus), GFP_KERNEL);
355         if (!smbus)
356                 return -ENOMEM;
357
358         smbus->dev = dev;
359         smbus->base = pci_resource_start(dev, 0);
360         smbus->size = pci_resource_len(dev, 0);
361
362         if (!request_region(smbus->base, smbus->size, amd8111_driver.name)) {
363                 error = -EBUSY;
364                 goto out_kfree;
365         }
366
367         smbus->adapter.owner = THIS_MODULE;
368         snprintf(smbus->adapter.name, sizeof(smbus->adapter.name),
369                 "SMBus2 AMD8111 adapter at %04x", smbus->base);
370         smbus->adapter.id = I2C_HW_SMBUS_AMD8111;
371         smbus->adapter.class = I2C_CLASS_HWMON;
372         smbus->adapter.algo = &smbus_algorithm;
373         smbus->adapter.algo_data = smbus;
374
375         /* set up the sysfs linkage to our parent device */
376         smbus->adapter.dev.parent = &dev->dev;
377
378         pci_write_config_dword(smbus->dev, AMD_PCI_MISC, 0);
379         error = i2c_add_adapter(&smbus->adapter);
380         if (error)
381                 goto out_release_region;
382
383         pci_set_drvdata(dev, smbus);
384         return 0;
385
386  out_release_region:
387         release_region(smbus->base, smbus->size);
388  out_kfree:
389         kfree(smbus);
390         return error;
391 }
392
393 static void __devexit amd8111_remove(struct pci_dev *dev)
394 {
395         struct amd_smbus *smbus = pci_get_drvdata(dev);
396
397         i2c_del_adapter(&smbus->adapter);
398         release_region(smbus->base, smbus->size);
399         kfree(smbus);
400 }
401
402 static struct pci_driver amd8111_driver = {
403         .name           = "amd8111_smbus2",
404         .id_table       = amd8111_ids,
405         .probe          = amd8111_probe,
406         .remove         = __devexit_p(amd8111_remove),
407 };
408
409 static int __init i2c_amd8111_init(void)
410 {
411         return pci_register_driver(&amd8111_driver);
412 }
413
414 static void __exit i2c_amd8111_exit(void)
415 {
416         pci_unregister_driver(&amd8111_driver);
417 }
418
419 module_init(i2c_amd8111_init);
420 module_exit(i2c_amd8111_exit);