gpu: nvgpu: Updated GM20b GPCPLL dynamic ramp setup
[linux-3.10.git] / drivers / gpu / nvgpu / gm20b / clk_gm20b.c
1 /*
2  * GM20B Clocks
3  *
4  * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/clk.h>
20 #include <linux/delay.h>        /* for mdelay */
21 #include <linux/module.h>
22 #include <linux/debugfs.h>
23 #include <linux/clk/tegra.h>
24 #include <mach/thermal.h>
25
26 #include "gk20a/gk20a.h"
27 #include "hw_trim_gm20b.h"
28 #include "hw_timer_gm20b.h"
29 #include "clk_gm20b.h"
30
31 #define gk20a_dbg_clk(fmt, arg...) \
32         gk20a_dbg(gpu_dbg_clk, fmt, ##arg)
33
34 /* from vbios PLL info table */
35 static struct pll_parms gpc_pll_params = {
36         128000,  2600000,       /* freq */
37         1300000, 2600000,       /* vco */
38         12000,   38400,         /* u */
39         1, 255,                 /* M */
40         8, 255,                 /* N */
41         1, 31,                  /* PL */
42 };
43
44 #ifdef CONFIG_DEBUG_FS
45 static int clk_gm20b_debugfs_init(struct gk20a *g);
46 #endif
47
48 /* 1:1 match between post divider settings and divisor value */
49 static inline u32 pl_to_div(u32 pl)
50 {
51         return pl;
52 }
53
54 static inline u32 div_to_pl(u32 div)
55 {
56         return div;
57 }
58
59 /* Calculate and update M/N/PL as well as pll->freq
60     ref_clk_f = clk_in_f;
61     u_f = ref_clk_f / M;
62     vco_f = u_f * N = ref_clk_f * N / M;
63     PLL output = gpc2clk = target clock frequency = vco_f / pl_to_pdiv(PL);
64     gpcclk = gpc2clk / 2; */
65 static int clk_config_pll(struct clk_gk20a *clk, struct pll *pll,
66         struct pll_parms *pll_params, u32 *target_freq, bool best_fit)
67 {
68         u32 min_vco_f, max_vco_f;
69         u32 best_M, best_N;
70         u32 low_PL, high_PL, best_PL;
71         u32 m, n, n2;
72         u32 target_vco_f, vco_f;
73         u32 ref_clk_f, target_clk_f, u_f;
74         u32 delta, lwv, best_delta = ~0;
75         u32 pl;
76
77         BUG_ON(target_freq == NULL);
78
79         gk20a_dbg_fn("request target freq %d MHz", *target_freq);
80
81         ref_clk_f = pll->clk_in;
82         target_clk_f = *target_freq;
83         max_vco_f = pll_params->max_vco;
84         min_vco_f = pll_params->min_vco;
85         best_M = pll_params->max_M;
86         best_N = pll_params->min_N;
87         best_PL = pll_params->min_PL;
88
89         target_vco_f = target_clk_f + target_clk_f / 50;
90         if (max_vco_f < target_vco_f)
91                 max_vco_f = target_vco_f;
92
93         /* Set PL search boundaries. */
94         high_PL = div_to_pl((max_vco_f + target_vco_f - 1) / target_vco_f);
95         high_PL = min(high_PL, pll_params->max_PL);
96         high_PL = max(high_PL, pll_params->min_PL);
97
98         low_PL = div_to_pl(min_vco_f / target_vco_f);
99         low_PL = min(low_PL, pll_params->max_PL);
100         low_PL = max(low_PL, pll_params->min_PL);
101
102         gk20a_dbg_info("low_PL %d(div%d), high_PL %d(div%d)",
103                         low_PL, pl_to_div(low_PL), high_PL, pl_to_div(high_PL));
104
105         for (pl = low_PL; pl <= high_PL; pl++) {
106                 target_vco_f = target_clk_f * pl_to_div(pl);
107
108                 for (m = pll_params->min_M; m <= pll_params->max_M; m++) {
109                         u_f = ref_clk_f / m;
110
111                         if (u_f < pll_params->min_u)
112                                 break;
113                         if (u_f > pll_params->max_u)
114                                 continue;
115
116                         n = (target_vco_f * m) / ref_clk_f;
117                         n2 = ((target_vco_f * m) + (ref_clk_f - 1)) / ref_clk_f;
118
119                         if (n > pll_params->max_N)
120                                 break;
121
122                         for (; n <= n2; n++) {
123                                 if (n < pll_params->min_N)
124                                         continue;
125                                 if (n > pll_params->max_N)
126                                         break;
127
128                                 vco_f = ref_clk_f * n / m;
129
130                                 if (vco_f >= min_vco_f && vco_f <= max_vco_f) {
131                                         lwv = (vco_f + (pl_to_div(pl) / 2))
132                                                 / pl_to_div(pl);
133                                         delta = abs(lwv - target_clk_f);
134
135                                         if (delta < best_delta) {
136                                                 best_delta = delta;
137                                                 best_M = m;
138                                                 best_N = n;
139                                                 best_PL = pl;
140
141                                                 if (best_delta == 0 ||
142                                                     /* 0.45% for non best fit */
143                                                     (!best_fit && (vco_f / best_delta > 218))) {
144                                                         goto found_match;
145                                                 }
146
147                                                 gk20a_dbg_info("delta %d @ M %d, N %d, PL %d",
148                                                         delta, m, n, pl);
149                                         }
150                                 }
151                         }
152                 }
153         }
154
155 found_match:
156         BUG_ON(best_delta == ~0);
157
158         if (best_fit && best_delta != 0)
159                 gk20a_dbg_clk("no best match for target @ %dMHz on gpc_pll",
160                         target_clk_f);
161
162         pll->M = best_M;
163         pll->N = best_N;
164         pll->PL = best_PL;
165
166         /* save current frequency */
167         pll->freq = ref_clk_f * pll->N / (pll->M * pl_to_div(pll->PL));
168
169         *target_freq = pll->freq;
170
171         gk20a_dbg_clk("actual target freq %d MHz, M %d, N %d, PL %d(div%d)",
172                 *target_freq, pll->M, pll->N, pll->PL, pl_to_div(pll->PL));
173
174         gk20a_dbg_fn("done");
175
176         return 0;
177 }
178
179 static void clk_setup_slide(struct gk20a *g, u32 clk_u)
180 {
181         u32 data, step_a, step_b;
182
183         switch (clk_u) {
184         case 12000:
185         case 12800:
186         case 13000:                     /* only on FPGA */
187                 step_a = 0x2B;
188                 step_b = 0x0B;
189                 break;
190         case 19200:
191                 step_a = 0x12;
192                 step_b = 0x08;
193                 break;
194         case 38400:
195                 step_a = 0x04;
196                 step_b = 0x05;
197                 break;
198         default:
199                 gk20a_err(dev_from_gk20a(g), "Unexpected reference rate %u kHz",
200                           clk_u);
201                 BUG();
202         }
203
204         /* setup */
205         data = gk20a_readl(g, trim_sys_gpcpll_cfg2_r());
206         data = set_field(data, trim_sys_gpcpll_cfg2_pll_stepa_m(),
207                         trim_sys_gpcpll_cfg2_pll_stepa_f(step_a));
208         gk20a_writel(g, trim_sys_gpcpll_cfg2_r(), data);
209         data = gk20a_readl(g, trim_sys_gpcpll_cfg3_r());
210         data = set_field(data, trim_sys_gpcpll_cfg3_pll_stepb_m(),
211                         trim_sys_gpcpll_cfg3_pll_stepb_f(step_b));
212         gk20a_writel(g, trim_sys_gpcpll_cfg3_r(), data);
213 }
214
215 static int clk_slide_gpc_pll(struct gk20a *g, u32 n)
216 {
217         u32 data, coeff;
218         u32 nold, m;
219         int ramp_timeout = 500;
220
221         /* get old coefficients */
222         coeff = gk20a_readl(g, trim_sys_gpcpll_coeff_r());
223         nold = trim_sys_gpcpll_coeff_ndiv_v(coeff);
224
225         /* do nothing if NDIV is same */
226         if (n == nold)
227                 return 0;
228
229         /* dynamic ramp setup based on update rate */
230         m = trim_sys_gpcpll_coeff_mdiv_v(coeff);
231         clk_setup_slide(g, g->clk.gpc_pll.clk_in / m);
232
233         /* pll slowdown mode */
234         data = gk20a_readl(g, trim_sys_gpcpll_ndiv_slowdown_r());
235         data = set_field(data,
236                         trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_m(),
237                         trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_yes_f());
238         gk20a_writel(g, trim_sys_gpcpll_ndiv_slowdown_r(), data);
239
240         /* new ndiv ready for ramp */
241         coeff = gk20a_readl(g, trim_sys_gpcpll_coeff_r());
242         coeff = set_field(coeff, trim_sys_gpcpll_coeff_ndiv_m(),
243                         trim_sys_gpcpll_coeff_ndiv_f(n));
244         udelay(1);
245         gk20a_writel(g, trim_sys_gpcpll_coeff_r(), coeff);
246
247         /* dynamic ramp to new ndiv */
248         data = gk20a_readl(g, trim_sys_gpcpll_ndiv_slowdown_r());
249         data = set_field(data,
250                         trim_sys_gpcpll_ndiv_slowdown_en_dynramp_m(),
251                         trim_sys_gpcpll_ndiv_slowdown_en_dynramp_yes_f());
252         udelay(1);
253         gk20a_writel(g, trim_sys_gpcpll_ndiv_slowdown_r(), data);
254
255         do {
256                 udelay(1);
257                 ramp_timeout--;
258                 data = gk20a_readl(
259                         g, trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_r());
260                 if (trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_pll_dynramp_done_synced_v(data))
261                         break;
262         } while (ramp_timeout > 0);
263
264         /* exit slowdown mode */
265         data = gk20a_readl(g, trim_sys_gpcpll_ndiv_slowdown_r());
266         data = set_field(data,
267                         trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_m(),
268                         trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_no_f());
269         data = set_field(data,
270                         trim_sys_gpcpll_ndiv_slowdown_en_dynramp_m(),
271                         trim_sys_gpcpll_ndiv_slowdown_en_dynramp_no_f());
272         gk20a_writel(g, trim_sys_gpcpll_ndiv_slowdown_r(), data);
273         gk20a_readl(g, trim_sys_gpcpll_ndiv_slowdown_r());
274
275         if (ramp_timeout <= 0) {
276                 gk20a_err(dev_from_gk20a(g), "gpcpll dynamic ramp timeout");
277                 return -ETIMEDOUT;
278         }
279         return 0;
280 }
281
282 static int clk_lock_gpc_pll_under_bypass(struct gk20a *g, u32 m, u32 n, u32 pl)
283 {
284         u32 data, cfg, coeff, timeout;
285
286         /* put PLL in bypass before programming it */
287         data = gk20a_readl(g, trim_sys_sel_vco_r());
288         data = set_field(data, trim_sys_sel_vco_gpc2clk_out_m(),
289                 trim_sys_sel_vco_gpc2clk_out_bypass_f());
290         gk20a_writel(g, trim_sys_sel_vco_r(), data);
291
292         cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r());
293         if (trim_sys_gpcpll_cfg_iddq_v(cfg)) {
294                 /* get out from IDDQ (1st power up) */
295                 cfg = set_field(cfg, trim_sys_gpcpll_cfg_iddq_m(),
296                                 trim_sys_gpcpll_cfg_iddq_power_on_v());
297                 gk20a_writel(g, trim_sys_gpcpll_cfg_r(), cfg);
298                 gk20a_readl(g, trim_sys_gpcpll_cfg_r());
299                 udelay(5);
300         } else {
301                 /* clear SYNC_MODE before disabling PLL */
302                 cfg = set_field(cfg, trim_sys_gpcpll_cfg_sync_mode_m(),
303                                 trim_sys_gpcpll_cfg_sync_mode_disable_f());
304                 gk20a_writel(g, trim_sys_gpcpll_cfg_r(), cfg);
305                 gk20a_readl(g, trim_sys_gpcpll_cfg_r());
306
307                 /* disable running PLL before changing coefficients */
308                 cfg = set_field(cfg, trim_sys_gpcpll_cfg_enable_m(),
309                                 trim_sys_gpcpll_cfg_enable_no_f());
310                 gk20a_writel(g, trim_sys_gpcpll_cfg_r(), cfg);
311                 gk20a_readl(g, trim_sys_gpcpll_cfg_r());
312         }
313
314         /* change coefficients */
315         coeff = trim_sys_gpcpll_coeff_mdiv_f(m) |
316                 trim_sys_gpcpll_coeff_ndiv_f(n) |
317                 trim_sys_gpcpll_coeff_pldiv_f(pl);
318         gk20a_writel(g, trim_sys_gpcpll_coeff_r(), coeff);
319
320         /* enable PLL after changing coefficients */
321         cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r());
322         cfg = set_field(cfg, trim_sys_gpcpll_cfg_enable_m(),
323                         trim_sys_gpcpll_cfg_enable_yes_f());
324         gk20a_writel(g, trim_sys_gpcpll_cfg_r(), cfg);
325
326         /* lock pll */
327         cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r());
328         if (cfg & trim_sys_gpcpll_cfg_enb_lckdet_power_off_f()){
329                 cfg = set_field(cfg, trim_sys_gpcpll_cfg_enb_lckdet_m(),
330                         trim_sys_gpcpll_cfg_enb_lckdet_power_on_f());
331                 gk20a_writel(g, trim_sys_gpcpll_cfg_r(), cfg);
332         }
333
334         /* wait pll lock */
335         timeout = g->clk.pll_delay / 2 + 1;
336         do {
337                 cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r());
338                 if (cfg & trim_sys_gpcpll_cfg_pll_lock_true_f())
339                         goto pll_locked;
340                 udelay(2);
341         } while (--timeout > 0);
342
343         /* PLL is messed up. What can we do here? */
344         BUG();
345         return -EBUSY;
346
347 pll_locked:
348         gk20a_dbg_clk("locked config_pll under bypass r=0x%x v=0x%x",
349                 trim_sys_gpcpll_cfg_r(), cfg);
350
351         /* set SYNC_MODE for glitchless switch out of bypass */
352         cfg = set_field(cfg, trim_sys_gpcpll_cfg_sync_mode_m(),
353                         trim_sys_gpcpll_cfg_sync_mode_enable_f());
354         gk20a_writel(g, trim_sys_gpcpll_cfg_r(), cfg);
355         gk20a_readl(g, trim_sys_gpcpll_cfg_r());
356
357         /* put PLL back on vco */
358         data = gk20a_readl(g, trim_sys_sel_vco_r());
359         data = set_field(data, trim_sys_sel_vco_gpc2clk_out_m(),
360                 trim_sys_sel_vco_gpc2clk_out_vco_f());
361         gk20a_writel(g, trim_sys_sel_vco_r(), data);
362
363         return 0;
364 }
365
366 static int clk_program_gpc_pll(struct gk20a *g, struct clk_gk20a *clk,
367                         int allow_slide)
368 {
369         u32 data, cfg, coeff;
370         u32 m, n, pl;
371         u32 nlo;
372
373         gk20a_dbg_fn("");
374
375         if (!tegra_platform_is_silicon())
376                 return 0;
377
378         /* get old coefficients */
379         coeff = gk20a_readl(g, trim_sys_gpcpll_coeff_r());
380         m = trim_sys_gpcpll_coeff_mdiv_v(coeff);
381         n = trim_sys_gpcpll_coeff_ndiv_v(coeff);
382         pl = trim_sys_gpcpll_coeff_pldiv_v(coeff);
383
384         /* do NDIV slide if there is no change in M and PL */
385         cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r());
386         if (allow_slide && clk->gpc_pll.M == m && clk->gpc_pll.PL == pl
387                 && trim_sys_gpcpll_cfg_enable_v(cfg)) {
388                 return clk_slide_gpc_pll(g, clk->gpc_pll.N);
389         }
390
391         /* slide down to NDIV_LO */
392         nlo = DIV_ROUND_UP(m * gpc_pll_params.min_vco, clk->gpc_pll.clk_in);
393         if (allow_slide && trim_sys_gpcpll_cfg_enable_v(cfg)) {
394                 int ret = clk_slide_gpc_pll(g, nlo);
395                 if (ret)
396                         return ret;
397         }
398
399         /* split FO-to-bypass jump in halfs by setting out divider 1:2 */
400         data = gk20a_readl(g, trim_sys_gpc2clk_out_r());
401         data = set_field(data, trim_sys_gpc2clk_out_vcodiv_m(),
402                 trim_sys_gpc2clk_out_vcodiv_f(2));
403         gk20a_writel(g, trim_sys_gpc2clk_out_r(), data);
404         gk20a_readl(g, trim_sys_gpc2clk_out_r());
405         udelay(2);
406
407         /*
408          * Program and lock pll under bypass. On exit PLL is out of bypass,
409          * enabled, and locked. VCO is at vco_min if sliding is allowed.
410          * Otherwise it is at VCO target (and therefore last slide call below
411          * is effectively NOP).
412          */
413         m = clk->gpc_pll.M;
414         nlo = DIV_ROUND_UP(m * gpc_pll_params.min_vco, clk->gpc_pll.clk_in);
415         n = allow_slide ? nlo : clk->gpc_pll.N;
416         pl = clk->gpc_pll.PL;
417         clk_lock_gpc_pll_under_bypass(g, m, n, pl);
418         clk->gpc_pll.enabled = true;
419
420         /* restore out divider 1:1 */
421         data = gk20a_readl(g, trim_sys_gpc2clk_out_r());
422         data = set_field(data, trim_sys_gpc2clk_out_vcodiv_m(),
423                 trim_sys_gpc2clk_out_vcodiv_by1_f());
424         udelay(2);
425         gk20a_writel(g, trim_sys_gpc2clk_out_r(), data);
426
427         /* slide up to target NDIV */
428         return clk_slide_gpc_pll(g, clk->gpc_pll.N);
429 }
430
431 static int clk_disable_gpcpll(struct gk20a *g, int allow_slide)
432 {
433         u32 cfg, coeff, m, nlo;
434         struct clk_gk20a *clk = &g->clk;
435
436         /* slide to VCO min */
437         cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r());
438         if (allow_slide && trim_sys_gpcpll_cfg_enable_v(cfg)) {
439                 coeff = gk20a_readl(g, trim_sys_gpcpll_coeff_r());
440                 m = trim_sys_gpcpll_coeff_mdiv_v(coeff);
441                 nlo = DIV_ROUND_UP(m * gpc_pll_params.min_vco,
442                                    clk->gpc_pll.clk_in);
443                 clk_slide_gpc_pll(g, nlo);
444         }
445
446         /* put PLL in bypass before disabling it */
447         cfg = gk20a_readl(g, trim_sys_sel_vco_r());
448         cfg = set_field(cfg, trim_sys_sel_vco_gpc2clk_out_m(),
449                         trim_sys_sel_vco_gpc2clk_out_bypass_f());
450         gk20a_writel(g, trim_sys_sel_vco_r(), cfg);
451
452         /* disable PLL */
453         cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r());
454         cfg = set_field(cfg, trim_sys_gpcpll_cfg_enable_m(),
455                         trim_sys_gpcpll_cfg_enable_no_f());
456         gk20a_writel(g, trim_sys_gpcpll_cfg_r(), cfg);
457         gk20a_readl(g, trim_sys_gpcpll_cfg_r());
458
459         clk->gpc_pll.enabled = false;
460         return 0;
461 }
462
463 static int gm20b_init_clk_reset_enable_hw(struct gk20a *g)
464 {
465         gk20a_dbg_fn("");
466         return 0;
467 }
468
469 struct clk *gm20b_clk_get(struct gk20a *g)
470 {
471         if (!g->clk.tegra_clk) {
472                 struct clk *clk;
473
474                 clk = clk_get_sys("tegra_gk20a", "gpu");
475                 if (IS_ERR(clk)) {
476                         gk20a_err(dev_from_gk20a(g),
477                                 "fail to get tegra gpu clk tegra_gk20a/gpu");
478                         return NULL;
479                 }
480                 g->clk.tegra_clk = clk;
481         }
482
483         return g->clk.tegra_clk;
484 }
485
486 static int gm20b_init_clk_setup_sw(struct gk20a *g)
487 {
488         struct clk_gk20a *clk = &g->clk;
489         static int initialized;
490         struct clk *ref;
491         unsigned long ref_rate;
492
493         gk20a_dbg_fn("");
494
495         if (clk->sw_ready) {
496                 gk20a_dbg_fn("skip init");
497                 return 0;
498         }
499
500         if (!gk20a_clk_get(g))
501                 return -EINVAL;
502
503         ref = clk_get_parent(clk_get_parent(clk->tegra_clk));
504         if (IS_ERR(ref)) {
505                 gk20a_err(dev_from_gk20a(g),
506                         "failed to get GPCPLL reference clock");
507                 return -EINVAL;
508         }
509         ref_rate = clk_get_rate(ref);
510
511         clk->pll_delay = 300; /* usec */
512
513         clk->gpc_pll.id = GK20A_GPC_PLL;
514         clk->gpc_pll.clk_in = ref_rate / KHZ;
515
516         /* Initial frequency: 1/3 VCO min (low enough to be safe at Vmin) */
517         if (!initialized) {
518                 initialized = 1;
519                 clk->gpc_pll.M = 1;
520                 clk->gpc_pll.N = DIV_ROUND_UP(gpc_pll_params.min_vco,
521                                         clk->gpc_pll.clk_in);
522                 clk->gpc_pll.PL = 3;
523                 clk->gpc_pll.freq = clk->gpc_pll.clk_in * clk->gpc_pll.N;
524                 clk->gpc_pll.freq /= pl_to_div(clk->gpc_pll.PL);
525         }
526
527         mutex_init(&clk->clk_mutex);
528
529         clk->sw_ready = true;
530
531         gk20a_dbg_fn("done");
532         return 0;
533 }
534
535 static int gm20b_init_clk_setup_hw(struct gk20a *g)
536 {
537         u32 data;
538
539         gk20a_dbg_fn("");
540
541         /* LDIV: Div4 mode (required); both  bypass and vco ratios 1:1 */
542         data = gk20a_readl(g, trim_sys_gpc2clk_out_r());
543         data = set_field(data,
544                         trim_sys_gpc2clk_out_sdiv14_m() |
545                         trim_sys_gpc2clk_out_vcodiv_m() |
546                         trim_sys_gpc2clk_out_bypdiv_m(),
547                         trim_sys_gpc2clk_out_sdiv14_indiv4_mode_f() |
548                         trim_sys_gpc2clk_out_vcodiv_by1_f() |
549                         trim_sys_gpc2clk_out_bypdiv_f(0));
550         gk20a_writel(g, trim_sys_gpc2clk_out_r(), data);
551
552         /*
553          * Clear global bypass control; PLL is still under bypass, since SEL_VCO
554          * is cleared by default.
555          */
556         data = gk20a_readl(g, trim_sys_bypassctrl_r());
557         data = set_field(data, trim_sys_bypassctrl_gpcpll_m(),
558                          trim_sys_bypassctrl_gpcpll_vco_f());
559         gk20a_writel(g, trim_sys_bypassctrl_r(), data);
560
561         return 0;
562 }
563
564 static int set_pll_target(struct gk20a *g, u32 freq, u32 old_freq)
565 {
566         struct clk_gk20a *clk = &g->clk;
567
568         if (freq > gpc_pll_params.max_freq)
569                 freq = gpc_pll_params.max_freq;
570         else if (freq < gpc_pll_params.min_freq)
571                 freq = gpc_pll_params.min_freq;
572
573         if (freq != old_freq) {
574                 /* gpc_pll.freq is changed to new value here */
575                 if (clk_config_pll(clk, &clk->gpc_pll, &gpc_pll_params,
576                                    &freq, true)) {
577                         gk20a_err(dev_from_gk20a(g),
578                                    "failed to set pll target for %d", freq);
579                         return -EINVAL;
580                 }
581         }
582         return 0;
583 }
584
585 static int set_pll_freq(struct gk20a *g, u32 freq, u32 old_freq)
586 {
587         struct clk_gk20a *clk = &g->clk;
588         int err = 0;
589
590         gk20a_dbg_fn("curr freq: %dMHz, target freq %dMHz", old_freq, freq);
591
592         if ((freq == old_freq) && clk->gpc_pll.enabled)
593                 return 0;
594
595         /* change frequency only if power is on */
596         if (g->clk.clk_hw_on) {
597                 err = clk_program_gpc_pll(g, clk, 1);
598                 if (err)
599                         err = clk_program_gpc_pll(g, clk, 0);
600         }
601
602         /* Just report error but not restore PLL since dvfs could already change
603             voltage even when it returns error. */
604         if (err)
605                 gk20a_err(dev_from_gk20a(g),
606                         "failed to set pll to %d", freq);
607         return err;
608 }
609
610 static int gm20b_clk_export_set_rate(void *data, unsigned long *rate)
611 {
612         u32 old_freq;
613         int ret = -ENODATA;
614         struct gk20a *g = data;
615         struct clk_gk20a *clk = &g->clk;
616
617         if (rate) {
618                 mutex_lock(&clk->clk_mutex);
619                 old_freq = clk->gpc_pll.freq;
620                 ret = set_pll_target(g, rate_gpu_to_gpc2clk(*rate), old_freq);
621                 if (!ret && clk->gpc_pll.enabled)
622                         ret = set_pll_freq(g, clk->gpc_pll.freq, old_freq);
623                 if (!ret)
624                         *rate = rate_gpc2clk_to_gpu(clk->gpc_pll.freq);
625                 mutex_unlock(&clk->clk_mutex);
626         }
627         return ret;
628 }
629
630 static int gm20b_clk_export_enable(void *data)
631 {
632         int ret;
633         struct gk20a *g = data;
634         struct clk_gk20a *clk = &g->clk;
635
636         mutex_lock(&clk->clk_mutex);
637         ret = set_pll_freq(g, clk->gpc_pll.freq, clk->gpc_pll.freq);
638         mutex_unlock(&clk->clk_mutex);
639         return ret;
640 }
641
642 static void gm20b_clk_export_disable(void *data)
643 {
644         struct gk20a *g = data;
645         struct clk_gk20a *clk = &g->clk;
646
647         mutex_lock(&clk->clk_mutex);
648         if (g->clk.clk_hw_on)
649                 clk_disable_gpcpll(g, 1);
650         mutex_unlock(&clk->clk_mutex);
651 }
652
653 static void gm20b_clk_export_init(void *data, unsigned long *rate, bool *state)
654 {
655         struct gk20a *g = data;
656         struct clk_gk20a *clk = &g->clk;
657
658         mutex_lock(&clk->clk_mutex);
659         if (state)
660                 *state = clk->gpc_pll.enabled;
661         if (rate)
662                 *rate = rate_gpc2clk_to_gpu(clk->gpc_pll.freq);
663         mutex_unlock(&clk->clk_mutex);
664 }
665
666 static struct tegra_clk_export_ops gm20b_clk_export_ops = {
667         .init = gm20b_clk_export_init,
668         .enable = gm20b_clk_export_enable,
669         .disable = gm20b_clk_export_disable,
670         .set_rate = gm20b_clk_export_set_rate,
671 };
672
673 static int gm20b_clk_register_export_ops(struct gk20a *g)
674 {
675         int ret;
676         struct clk *c;
677
678         if (gm20b_clk_export_ops.data)
679                 return 0;
680
681         gm20b_clk_export_ops.data = (void *)g;
682         c = g->clk.tegra_clk;
683         if (!c || !clk_get_parent(c))
684                 return -ENOSYS;
685
686         ret = tegra_clk_register_export_ops(clk_get_parent(c),
687                                             &gm20b_clk_export_ops);
688
689         return ret;
690 }
691
692 static int gm20b_init_clk_support(struct gk20a *g)
693 {
694         struct clk_gk20a *clk = &g->clk;
695         u32 err;
696
697         gk20a_dbg_fn("");
698
699         clk->g = g;
700
701         err = gm20b_init_clk_reset_enable_hw(g);
702         if (err)
703                 return err;
704
705         err = gm20b_init_clk_setup_sw(g);
706         if (err)
707                 return err;
708
709         mutex_lock(&clk->clk_mutex);
710         clk->clk_hw_on = true;
711
712         err = gm20b_init_clk_setup_hw(g);
713         mutex_unlock(&clk->clk_mutex);
714         if (err)
715                 return err;
716
717         err = gm20b_clk_register_export_ops(g);
718         if (err)
719                 return err;
720
721         /* FIXME: this effectively prevents host level clock gating */
722         err = clk_enable(g->clk.tegra_clk);
723         if (err)
724                 return err;
725
726         /* The prev call may not enable PLL if gbus is unbalanced - force it */
727         mutex_lock(&clk->clk_mutex);
728         err = set_pll_freq(g, clk->gpc_pll.freq, clk->gpc_pll.freq);
729         mutex_unlock(&clk->clk_mutex);
730         if (err)
731                 return err;
732
733 #ifdef CONFIG_DEBUG_FS
734         if (!clk->debugfs_set) {
735                 if (!clk_gm20b_debugfs_init(g))
736                         clk->debugfs_set = true;
737         }
738 #endif
739         return err;
740 }
741
742 static int gm20b_suspend_clk_support(struct gk20a *g)
743 {
744         int ret;
745
746         clk_disable(g->clk.tegra_clk);
747
748         /* The prev call may not disable PLL if gbus is unbalanced - force it */
749         mutex_lock(&g->clk.clk_mutex);
750         ret = clk_disable_gpcpll(g, 1);
751         g->clk.clk_hw_on = false;
752         mutex_unlock(&g->clk.clk_mutex);
753         return ret;
754 }
755
756 void gm20b_init_clk_ops(struct gpu_ops *gops)
757 {
758         gops->clk.init_clk_support = gm20b_init_clk_support;
759         gops->clk.suspend_clk_support = gm20b_suspend_clk_support;
760 }
761
762 #ifdef CONFIG_DEBUG_FS
763
764 static int rate_get(void *data, u64 *val)
765 {
766         struct gk20a *g = (struct gk20a *)data;
767         *val = (u64)gk20a_clk_get_rate(g);
768         return 0;
769 }
770 static int rate_set(void *data, u64 val)
771 {
772         struct gk20a *g = (struct gk20a *)data;
773         return gk20a_clk_set_rate(g, (u32)val);
774 }
775 DEFINE_SIMPLE_ATTRIBUTE(rate_fops, rate_get, rate_set, "%llu\n");
776
777 static int pll_reg_show(struct seq_file *s, void *data)
778 {
779         struct gk20a *g = s->private;
780         u32 reg, m, n, pl, f;
781
782         mutex_lock(&g->clk.clk_mutex);
783         if (!g->clk.clk_hw_on) {
784                 seq_printf(s, "gk20a powered down - no access to registers\n");
785                 mutex_unlock(&g->clk.clk_mutex);
786                 return 0;
787         }
788
789         reg = gk20a_readl(g, trim_sys_bypassctrl_r());
790         seq_printf(s, "bypassctrl = %s, ", reg ? "bypass" : "vco");
791         reg = gk20a_readl(g, trim_sys_sel_vco_r());
792         seq_printf(s, "sel_vco = %s, ", reg ? "vco" : "bypass");
793
794         reg = gk20a_readl(g, trim_sys_gpcpll_cfg_r());
795         seq_printf(s, "cfg  = 0x%x : %s : %s : %s\n", reg,
796                 trim_sys_gpcpll_cfg_enable_v(reg) ? "enabled" : "disabled",
797                 trim_sys_gpcpll_cfg_pll_lock_v(reg) ? "locked" : "unlocked",
798                 trim_sys_gpcpll_cfg_sync_mode_v(reg) ? "sync_on" : "sync_off");
799
800         reg = gk20a_readl(g, trim_sys_gpcpll_coeff_r());
801         m = trim_sys_gpcpll_coeff_mdiv_v(reg);
802         n = trim_sys_gpcpll_coeff_ndiv_v(reg);
803         pl = trim_sys_gpcpll_coeff_pldiv_v(reg);
804         f = g->clk.gpc_pll.clk_in * n / (m * pl_to_div(pl));
805         seq_printf(s, "coef = 0x%x : m = %u : n = %u : pl = %u", reg, m, n, pl);
806         seq_printf(s, " : pll_f(gpu_f) = %u(%u) kHz\n", f, f/2);
807         mutex_unlock(&g->clk.clk_mutex);
808         return 0;
809 }
810
811 static int pll_reg_open(struct inode *inode, struct file *file)
812 {
813         return single_open(file, pll_reg_show, inode->i_private);
814 }
815
816 static const struct file_operations pll_reg_fops = {
817         .open           = pll_reg_open,
818         .read           = seq_read,
819         .llseek         = seq_lseek,
820         .release        = single_release,
821 };
822
823 static int monitor_get(void *data, u64 *val)
824 {
825         struct gk20a *g = (struct gk20a *)data;
826         struct clk_gk20a *clk = &g->clk;
827         int err;
828
829         u32 ncycle = 100; /* count GPCCLK for ncycle of clkin */
830         u64 freq = clk->gpc_pll.clk_in;
831         u32 count1, count2;
832
833         err = gk20a_busy(g->dev);
834         if (err)
835                 return err;
836
837         gk20a_writel(g, trim_gpc_clk_cntr_ncgpcclk_cfg_r(0),
838                      trim_gpc_clk_cntr_ncgpcclk_cfg_reset_asserted_f());
839         gk20a_writel(g, trim_gpc_clk_cntr_ncgpcclk_cfg_r(0),
840                      trim_gpc_clk_cntr_ncgpcclk_cfg_enable_asserted_f() |
841                      trim_gpc_clk_cntr_ncgpcclk_cfg_write_en_asserted_f() |
842                      trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(ncycle));
843         /* start */
844
845         /* It should take about 8us to finish 100 cycle of 12MHz.
846            But longer than 100us delay is required here. */
847         gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cfg_r(0));
848         udelay(2000);
849
850         count1 = gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cnt_r(0));
851         udelay(100);
852         count2 = gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cnt_r(0));
853         freq *= trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(count2);
854         do_div(freq, ncycle);
855         *val = freq;
856
857         gk20a_idle(g->dev);
858
859         if (count1 != count2)
860                 return -EBUSY;
861         return 0;
862 }
863 DEFINE_SIMPLE_ATTRIBUTE(monitor_fops, monitor_get, NULL, "%llu\n");
864
865 static int clk_gm20b_debugfs_init(struct gk20a *g)
866 {
867         struct dentry *d;
868         struct gk20a_platform *platform = platform_get_drvdata(g->dev);
869
870         d = debugfs_create_file(
871                 "rate", S_IRUGO|S_IWUSR, platform->debugfs, g, &rate_fops);
872         if (!d)
873                 goto err_out;
874
875         d = debugfs_create_file(
876                 "pll_reg", S_IRUGO, platform->debugfs, g, &pll_reg_fops);
877         if (!d)
878                 goto err_out;
879
880         d = debugfs_create_file(
881                 "monitor", S_IRUGO, platform->debugfs, g, &monitor_fops);
882         if (!d)
883                 goto err_out;
884
885         return 0;
886
887 err_out:
888         pr_err("%s: Failed to make debugfs node\n", __func__);
889         debugfs_remove_recursive(platform->debugfs);
890         return -ENOMEM;
891 }
892
893 #endif /* CONFIG_DEBUG_FS */