gpu: nvgpu: Re-factor GM20b clk_program_gpc_pll()
[linux-3.10.git] / drivers / gpu / nvgpu / gm20b / clk_gm20b.c
1 /*
2  * GM20B Clocks
3  *
4  * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/clk.h>
20 #include <linux/delay.h>        /* for mdelay */
21 #include <linux/module.h>
22 #include <linux/debugfs.h>
23 #include <linux/uaccess.h>
24 #include <linux/clk/tegra.h>
25
26 #include "gk20a/gk20a.h"
27 #include "hw_trim_gm20b.h"
28 #include "hw_timer_gm20b.h"
29 #include "hw_therm_gm20b.h"
30 #include "clk_gm20b.h"
31
32 #define gk20a_dbg_clk(fmt, arg...) \
33         gk20a_dbg(gpu_dbg_clk, fmt, ##arg)
34
35 /* from vbios PLL info table */
36 static struct pll_parms gpc_pll_params = {
37         128000,  2600000,       /* freq */
38         1300000, 2600000,       /* vco */
39         12000,   38400,         /* u */
40         1, 255,                 /* M */
41         8, 255,                 /* N */
42         1, 31,                  /* PL */
43 };
44
45 #ifdef CONFIG_DEBUG_FS
46 static int clk_gm20b_debugfs_init(struct gk20a *g);
47 #endif
48
49 /* 1:1 match between post divider settings and divisor value */
50 static inline u32 pl_to_div(u32 pl)
51 {
52         return pl;
53 }
54
55 static inline u32 div_to_pl(u32 div)
56 {
57         return div;
58 }
59
60 /* FIXME: remove after on-silicon testing */
61 #define PLDIV_GLITCHLESS 1
62
63 /* Calculate and update M/N/PL as well as pll->freq
64     ref_clk_f = clk_in_f;
65     u_f = ref_clk_f / M;
66     vco_f = u_f * N = ref_clk_f * N / M;
67     PLL output = gpc2clk = target clock frequency = vco_f / pl_to_pdiv(PL);
68     gpcclk = gpc2clk / 2; */
69 static int clk_config_pll(struct clk_gk20a *clk, struct pll *pll,
70         struct pll_parms *pll_params, u32 *target_freq, bool best_fit)
71 {
72         u32 min_vco_f, max_vco_f;
73         u32 best_M, best_N;
74         u32 low_PL, high_PL, best_PL;
75         u32 m, n, n2;
76         u32 target_vco_f, vco_f;
77         u32 ref_clk_f, target_clk_f, u_f;
78         u32 delta, lwv, best_delta = ~0;
79         u32 pl;
80
81         BUG_ON(target_freq == NULL);
82
83         gk20a_dbg_fn("request target freq %d MHz", *target_freq);
84
85         ref_clk_f = pll->clk_in;
86         target_clk_f = *target_freq;
87         max_vco_f = pll_params->max_vco;
88         min_vco_f = pll_params->min_vco;
89         best_M = pll_params->max_M;
90         best_N = pll_params->min_N;
91         best_PL = pll_params->min_PL;
92
93         target_vco_f = target_clk_f + target_clk_f / 50;
94         if (max_vco_f < target_vco_f)
95                 max_vco_f = target_vco_f;
96
97         /* Set PL search boundaries. */
98         high_PL = div_to_pl((max_vco_f + target_vco_f - 1) / target_vco_f);
99         high_PL = min(high_PL, pll_params->max_PL);
100         high_PL = max(high_PL, pll_params->min_PL);
101
102         low_PL = div_to_pl(min_vco_f / target_vco_f);
103         low_PL = min(low_PL, pll_params->max_PL);
104         low_PL = max(low_PL, pll_params->min_PL);
105
106         gk20a_dbg_info("low_PL %d(div%d), high_PL %d(div%d)",
107                         low_PL, pl_to_div(low_PL), high_PL, pl_to_div(high_PL));
108
109         for (pl = low_PL; pl <= high_PL; pl++) {
110                 target_vco_f = target_clk_f * pl_to_div(pl);
111
112                 for (m = pll_params->min_M; m <= pll_params->max_M; m++) {
113                         u_f = ref_clk_f / m;
114
115                         if (u_f < pll_params->min_u)
116                                 break;
117                         if (u_f > pll_params->max_u)
118                                 continue;
119
120                         n = (target_vco_f * m) / ref_clk_f;
121                         n2 = ((target_vco_f * m) + (ref_clk_f - 1)) / ref_clk_f;
122
123                         if (n > pll_params->max_N)
124                                 break;
125
126                         for (; n <= n2; n++) {
127                                 if (n < pll_params->min_N)
128                                         continue;
129                                 if (n > pll_params->max_N)
130                                         break;
131
132                                 vco_f = ref_clk_f * n / m;
133
134                                 if (vco_f >= min_vco_f && vco_f <= max_vco_f) {
135                                         lwv = (vco_f + (pl_to_div(pl) / 2))
136                                                 / pl_to_div(pl);
137                                         delta = abs(lwv - target_clk_f);
138
139                                         if (delta < best_delta) {
140                                                 best_delta = delta;
141                                                 best_M = m;
142                                                 best_N = n;
143                                                 best_PL = pl;
144
145                                                 if (best_delta == 0 ||
146                                                     /* 0.45% for non best fit */
147                                                     (!best_fit && (vco_f / best_delta > 218))) {
148                                                         goto found_match;
149                                                 }
150
151                                                 gk20a_dbg_info("delta %d @ M %d, N %d, PL %d",
152                                                         delta, m, n, pl);
153                                         }
154                                 }
155                         }
156                 }
157         }
158
159 found_match:
160         BUG_ON(best_delta == ~0);
161
162         if (best_fit && best_delta != 0)
163                 gk20a_dbg_clk("no best match for target @ %dMHz on gpc_pll",
164                         target_clk_f);
165
166         pll->M = best_M;
167         pll->N = best_N;
168         pll->PL = best_PL;
169
170         /* save current frequency */
171         pll->freq = ref_clk_f * pll->N / (pll->M * pl_to_div(pll->PL));
172
173         *target_freq = pll->freq;
174
175         gk20a_dbg_clk("actual target freq %d MHz, M %d, N %d, PL %d(div%d)",
176                 *target_freq, pll->M, pll->N, pll->PL, pl_to_div(pll->PL));
177
178         gk20a_dbg_fn("done");
179
180         return 0;
181 }
182
183 static void clk_setup_slide(struct gk20a *g, u32 clk_u)
184 {
185         u32 data, step_a, step_b;
186
187         switch (clk_u) {
188         case 12000:
189         case 12800:
190         case 13000:                     /* only on FPGA */
191                 step_a = 0x2B;
192                 step_b = 0x0B;
193                 break;
194         case 19200:
195                 step_a = 0x12;
196                 step_b = 0x08;
197                 break;
198         case 38400:
199                 step_a = 0x04;
200                 step_b = 0x05;
201                 break;
202         default:
203                 gk20a_err(dev_from_gk20a(g), "Unexpected reference rate %u kHz",
204                           clk_u);
205                 BUG();
206         }
207
208         /* setup */
209         data = gk20a_readl(g, trim_sys_gpcpll_cfg2_r());
210         data = set_field(data, trim_sys_gpcpll_cfg2_pll_stepa_m(),
211                         trim_sys_gpcpll_cfg2_pll_stepa_f(step_a));
212         gk20a_writel(g, trim_sys_gpcpll_cfg2_r(), data);
213         data = gk20a_readl(g, trim_sys_gpcpll_cfg3_r());
214         data = set_field(data, trim_sys_gpcpll_cfg3_pll_stepb_m(),
215                         trim_sys_gpcpll_cfg3_pll_stepb_f(step_b));
216         gk20a_writel(g, trim_sys_gpcpll_cfg3_r(), data);
217 }
218
219 static int clk_slide_gpc_pll(struct gk20a *g, u32 n)
220 {
221         u32 data, coeff;
222         u32 nold, m;
223         int ramp_timeout = 500;
224
225         /* get old coefficients */
226         coeff = gk20a_readl(g, trim_sys_gpcpll_coeff_r());
227         nold = trim_sys_gpcpll_coeff_ndiv_v(coeff);
228
229         /* do nothing if NDIV is same */
230         if (n == nold)
231                 return 0;
232
233         /* dynamic ramp setup based on update rate */
234         m = trim_sys_gpcpll_coeff_mdiv_v(coeff);
235         clk_setup_slide(g, g->clk.gpc_pll.clk_in / m);
236
237         /* pll slowdown mode */
238         data = gk20a_readl(g, trim_sys_gpcpll_ndiv_slowdown_r());
239         data = set_field(data,
240                         trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_m(),
241                         trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_yes_f());
242         gk20a_writel(g, trim_sys_gpcpll_ndiv_slowdown_r(), data);
243
244         /* new ndiv ready for ramp */
245         coeff = gk20a_readl(g, trim_sys_gpcpll_coeff_r());
246         coeff = set_field(coeff, trim_sys_gpcpll_coeff_ndiv_m(),
247                         trim_sys_gpcpll_coeff_ndiv_f(n));
248         udelay(1);
249         gk20a_writel(g, trim_sys_gpcpll_coeff_r(), coeff);
250
251         /* dynamic ramp to new ndiv */
252         data = gk20a_readl(g, trim_sys_gpcpll_ndiv_slowdown_r());
253         data = set_field(data,
254                         trim_sys_gpcpll_ndiv_slowdown_en_dynramp_m(),
255                         trim_sys_gpcpll_ndiv_slowdown_en_dynramp_yes_f());
256         udelay(1);
257         gk20a_writel(g, trim_sys_gpcpll_ndiv_slowdown_r(), data);
258
259         do {
260                 udelay(1);
261                 ramp_timeout--;
262                 data = gk20a_readl(
263                         g, trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_r());
264                 if (trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_pll_dynramp_done_synced_v(data))
265                         break;
266         } while (ramp_timeout > 0);
267
268         /* exit slowdown mode */
269         data = gk20a_readl(g, trim_sys_gpcpll_ndiv_slowdown_r());
270         data = set_field(data,
271                         trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_m(),
272                         trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_no_f());
273         data = set_field(data,
274                         trim_sys_gpcpll_ndiv_slowdown_en_dynramp_m(),
275                         trim_sys_gpcpll_ndiv_slowdown_en_dynramp_no_f());
276         gk20a_writel(g, trim_sys_gpcpll_ndiv_slowdown_r(), data);
277         gk20a_readl(g, trim_sys_gpcpll_ndiv_slowdown_r());
278
279         if (ramp_timeout <= 0) {
280                 gk20a_err(dev_from_gk20a(g), "gpcpll dynamic ramp timeout");
281                 return -ETIMEDOUT;
282         }
283         return 0;
284 }
285
286 static int clk_lock_gpc_pll_under_bypass(struct gk20a *g, u32 m, u32 n, u32 pl)
287 {
288         u32 data, cfg, coeff, timeout;
289
290         /* put PLL in bypass before programming it */
291         data = gk20a_readl(g, trim_sys_sel_vco_r());
292         data = set_field(data, trim_sys_sel_vco_gpc2clk_out_m(),
293                 trim_sys_sel_vco_gpc2clk_out_bypass_f());
294         gk20a_writel(g, trim_sys_sel_vco_r(), data);
295
296         cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r());
297         if (trim_sys_gpcpll_cfg_iddq_v(cfg)) {
298                 /* get out from IDDQ (1st power up) */
299                 cfg = set_field(cfg, trim_sys_gpcpll_cfg_iddq_m(),
300                                 trim_sys_gpcpll_cfg_iddq_power_on_v());
301                 gk20a_writel(g, trim_sys_gpcpll_cfg_r(), cfg);
302                 gk20a_readl(g, trim_sys_gpcpll_cfg_r());
303                 udelay(5);
304         } else {
305                 /* clear SYNC_MODE before disabling PLL */
306                 cfg = set_field(cfg, trim_sys_gpcpll_cfg_sync_mode_m(),
307                                 trim_sys_gpcpll_cfg_sync_mode_disable_f());
308                 gk20a_writel(g, trim_sys_gpcpll_cfg_r(), cfg);
309                 gk20a_readl(g, trim_sys_gpcpll_cfg_r());
310
311                 /* disable running PLL before changing coefficients */
312                 cfg = set_field(cfg, trim_sys_gpcpll_cfg_enable_m(),
313                                 trim_sys_gpcpll_cfg_enable_no_f());
314                 gk20a_writel(g, trim_sys_gpcpll_cfg_r(), cfg);
315                 gk20a_readl(g, trim_sys_gpcpll_cfg_r());
316         }
317
318         /* change coefficients */
319         coeff = trim_sys_gpcpll_coeff_mdiv_f(m) |
320                 trim_sys_gpcpll_coeff_ndiv_f(n) |
321                 trim_sys_gpcpll_coeff_pldiv_f(pl);
322         gk20a_writel(g, trim_sys_gpcpll_coeff_r(), coeff);
323
324         /* enable PLL after changing coefficients */
325         cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r());
326         cfg = set_field(cfg, trim_sys_gpcpll_cfg_enable_m(),
327                         trim_sys_gpcpll_cfg_enable_yes_f());
328         gk20a_writel(g, trim_sys_gpcpll_cfg_r(), cfg);
329
330         /* lock pll */
331         cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r());
332         if (cfg & trim_sys_gpcpll_cfg_enb_lckdet_power_off_f()){
333                 cfg = set_field(cfg, trim_sys_gpcpll_cfg_enb_lckdet_m(),
334                         trim_sys_gpcpll_cfg_enb_lckdet_power_on_f());
335                 gk20a_writel(g, trim_sys_gpcpll_cfg_r(), cfg);
336         }
337
338         /* wait pll lock */
339         timeout = g->clk.pll_delay / 2 + 1;
340         do {
341                 cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r());
342                 if (cfg & trim_sys_gpcpll_cfg_pll_lock_true_f())
343                         goto pll_locked;
344                 udelay(2);
345         } while (--timeout > 0);
346
347         /* PLL is messed up. What can we do here? */
348         BUG();
349         return -EBUSY;
350
351 pll_locked:
352         gk20a_dbg_clk("locked config_pll under bypass r=0x%x v=0x%x",
353                 trim_sys_gpcpll_cfg_r(), cfg);
354
355         /* set SYNC_MODE for glitchless switch out of bypass */
356         cfg = set_field(cfg, trim_sys_gpcpll_cfg_sync_mode_m(),
357                         trim_sys_gpcpll_cfg_sync_mode_enable_f());
358         gk20a_writel(g, trim_sys_gpcpll_cfg_r(), cfg);
359         gk20a_readl(g, trim_sys_gpcpll_cfg_r());
360
361         /* put PLL back on vco */
362         data = gk20a_readl(g, trim_sys_sel_vco_r());
363         data = set_field(data, trim_sys_sel_vco_gpc2clk_out_m(),
364                 trim_sys_sel_vco_gpc2clk_out_vco_f());
365         gk20a_writel(g, trim_sys_sel_vco_r(), data);
366
367         return 0;
368 }
369
370 static int clk_program_gpc_pll(struct gk20a *g, struct pll *gpll_new,
371                         int allow_slide)
372 {
373 #if PLDIV_GLITCHLESS
374         bool skip_bypass;
375 #else
376         u32 data;
377 #endif
378         u32 cfg, coeff;
379         u32 m, n, pl, nlo;
380         bool can_slide;
381
382         gk20a_dbg_fn("");
383
384         if (!tegra_platform_is_silicon())
385                 return 0;
386
387         /* get old coefficients */
388         coeff = gk20a_readl(g, trim_sys_gpcpll_coeff_r());
389         m = trim_sys_gpcpll_coeff_mdiv_v(coeff);
390         n = trim_sys_gpcpll_coeff_ndiv_v(coeff);
391         pl = trim_sys_gpcpll_coeff_pldiv_v(coeff);
392
393         /* do NDIV slide if there is no change in M and PL */
394         cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r());
395         can_slide = allow_slide && trim_sys_gpcpll_cfg_enable_v(cfg);
396
397         if (can_slide && (gpll_new->M == m) && (gpll_new->PL == pl))
398                 return clk_slide_gpc_pll(g, gpll_new->N);
399
400         /* slide down to NDIV_LO */
401         nlo = DIV_ROUND_UP(m * gpc_pll_params.min_vco, gpll_new->clk_in);
402         if (can_slide) {
403                 int ret = clk_slide_gpc_pll(g, nlo);
404                 if (ret)
405                         return ret;
406         }
407
408 #if PLDIV_GLITCHLESS
409         /*
410          * Limit either FO-to-FO (path A below) or FO-to-bypass (path B below)
411          * jump to min_vco/2 by setting post divider >= 1:2.
412          */
413         skip_bypass = can_slide && (gpll_new->M == m);
414         coeff = gk20a_readl(g, trim_sys_gpcpll_coeff_r());
415         if ((skip_bypass && (gpll_new->PL < 2)) || (pl < 2)) {
416                 if (pl != 2) {
417                         coeff = set_field(coeff,
418                                 trim_sys_gpcpll_coeff_pldiv_m(),
419                                 trim_sys_gpcpll_coeff_pldiv_f(2));
420                         gk20a_writel(g, trim_sys_gpcpll_coeff_r(), coeff);
421                         coeff = gk20a_readl(g, trim_sys_gpcpll_coeff_r());
422                         udelay(2);
423                 }
424         }
425
426         if (skip_bypass)
427                 goto set_pldiv; /* path A: no need to bypass */
428
429         /* path B: bypass if either M changes or PLL is disabled */
430 #else
431         /* split FO-to-bypass jump in halfs by setting out divider 1:2 */
432         data = gk20a_readl(g, trim_sys_gpc2clk_out_r());
433         data = set_field(data, trim_sys_gpc2clk_out_vcodiv_m(),
434                 trim_sys_gpc2clk_out_vcodiv_f(2));
435         gk20a_writel(g, trim_sys_gpc2clk_out_r(), data);
436         gk20a_readl(g, trim_sys_gpc2clk_out_r());
437         udelay(2);
438 #endif
439         /*
440          * Program and lock pll under bypass. On exit PLL is out of bypass,
441          * enabled, and locked. VCO is at vco_min if sliding is allowed.
442          * Otherwise it is at VCO target (and therefore last slide call below
443          * is effectively NOP). PL is preserved (not set to target) of post
444          * divider is glitchless. Otherwise it is at PL target.
445          */
446         m = gpll_new->M;
447         nlo = DIV_ROUND_UP(m * gpc_pll_params.min_vco, gpll_new->clk_in);
448         n = allow_slide ? nlo : gpll_new->N;
449 #if PLDIV_GLITCHLESS
450         pl = (gpll_new->PL < 2) ? 2 : gpll_new->PL;
451 #else
452         pl = gpll_new->PL;
453 #endif
454         clk_lock_gpc_pll_under_bypass(g, m, n, pl);
455         gpll_new->enabled = true;
456
457 #if PLDIV_GLITCHLESS
458         coeff = gk20a_readl(g, trim_sys_gpcpll_coeff_r());
459         udelay(2);
460
461 set_pldiv:
462         /* coeff must be current from either path A or B */
463         if (trim_sys_gpcpll_coeff_pldiv_v(coeff) != gpll_new->PL) {
464                 coeff = set_field(coeff, trim_sys_gpcpll_coeff_pldiv_m(),
465                         trim_sys_gpcpll_coeff_pldiv_f(gpll_new->PL));
466                 gk20a_writel(g, trim_sys_gpcpll_coeff_r(), coeff);
467         }
468 #else
469         /* restore out divider 1:1 */
470         data = gk20a_readl(g, trim_sys_gpc2clk_out_r());
471         data = set_field(data, trim_sys_gpc2clk_out_vcodiv_m(),
472                 trim_sys_gpc2clk_out_vcodiv_by1_f());
473         udelay(2);
474         gk20a_writel(g, trim_sys_gpc2clk_out_r(), data);
475 #endif
476         /* slide up to target NDIV */
477         return clk_slide_gpc_pll(g, gpll_new->N);
478 }
479
480 static int clk_disable_gpcpll(struct gk20a *g, int allow_slide)
481 {
482         u32 cfg, coeff, m, nlo;
483         struct clk_gk20a *clk = &g->clk;
484
485         /* slide to VCO min */
486         cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r());
487         if (allow_slide && trim_sys_gpcpll_cfg_enable_v(cfg)) {
488                 coeff = gk20a_readl(g, trim_sys_gpcpll_coeff_r());
489                 m = trim_sys_gpcpll_coeff_mdiv_v(coeff);
490                 nlo = DIV_ROUND_UP(m * gpc_pll_params.min_vco,
491                                    clk->gpc_pll.clk_in);
492                 clk_slide_gpc_pll(g, nlo);
493         }
494
495         /* put PLL in bypass before disabling it */
496         cfg = gk20a_readl(g, trim_sys_sel_vco_r());
497         cfg = set_field(cfg, trim_sys_sel_vco_gpc2clk_out_m(),
498                         trim_sys_sel_vco_gpc2clk_out_bypass_f());
499         gk20a_writel(g, trim_sys_sel_vco_r(), cfg);
500
501         /* clear SYNC_MODE before disabling PLL */
502         cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r());
503         cfg = set_field(cfg, trim_sys_gpcpll_cfg_sync_mode_m(),
504                         trim_sys_gpcpll_cfg_sync_mode_disable_f());
505         gk20a_writel(g, trim_sys_gpcpll_cfg_r(), cfg);
506
507         /* disable PLL */
508         cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r());
509         cfg = set_field(cfg, trim_sys_gpcpll_cfg_enable_m(),
510                         trim_sys_gpcpll_cfg_enable_no_f());
511         gk20a_writel(g, trim_sys_gpcpll_cfg_r(), cfg);
512         gk20a_readl(g, trim_sys_gpcpll_cfg_r());
513
514         clk->gpc_pll.enabled = false;
515         return 0;
516 }
517
518 static int gm20b_init_clk_reset_enable_hw(struct gk20a *g)
519 {
520         gk20a_dbg_fn("");
521         return 0;
522 }
523
524 struct clk *gm20b_clk_get(struct gk20a *g)
525 {
526         if (!g->clk.tegra_clk) {
527                 struct clk *clk;
528
529                 clk = clk_get_sys("tegra_gk20a", "gpu");
530                 if (IS_ERR(clk)) {
531                         gk20a_err(dev_from_gk20a(g),
532                                 "fail to get tegra gpu clk tegra_gk20a/gpu");
533                         return NULL;
534                 }
535                 g->clk.tegra_clk = clk;
536         }
537
538         return g->clk.tegra_clk;
539 }
540
541 static int gm20b_init_clk_setup_sw(struct gk20a *g)
542 {
543         struct clk_gk20a *clk = &g->clk;
544         static int initialized;
545         struct clk *ref;
546         unsigned long ref_rate;
547
548         gk20a_dbg_fn("");
549
550         if (clk->sw_ready) {
551                 gk20a_dbg_fn("skip init");
552                 return 0;
553         }
554
555         if (!gk20a_clk_get(g))
556                 return -EINVAL;
557
558         ref = clk_get_parent(clk_get_parent(clk->tegra_clk));
559         if (IS_ERR(ref)) {
560                 gk20a_err(dev_from_gk20a(g),
561                         "failed to get GPCPLL reference clock");
562                 return -EINVAL;
563         }
564         ref_rate = clk_get_rate(ref);
565
566         clk->pll_delay = 300; /* usec */
567
568         clk->gpc_pll.id = GK20A_GPC_PLL;
569         clk->gpc_pll.clk_in = ref_rate / KHZ;
570
571         /* Initial frequency: 1/3 VCO min (low enough to be safe at Vmin) */
572         if (!initialized) {
573                 initialized = 1;
574                 clk->gpc_pll.M = 1;
575                 clk->gpc_pll.N = DIV_ROUND_UP(gpc_pll_params.min_vco,
576                                         clk->gpc_pll.clk_in);
577                 clk->gpc_pll.PL = 3;
578                 clk->gpc_pll.freq = clk->gpc_pll.clk_in * clk->gpc_pll.N;
579                 clk->gpc_pll.freq /= pl_to_div(clk->gpc_pll.PL);
580         }
581
582         mutex_init(&clk->clk_mutex);
583
584         clk->sw_ready = true;
585
586         gk20a_dbg_fn("done");
587         return 0;
588 }
589
590 static int gm20b_init_clk_setup_hw(struct gk20a *g)
591 {
592         u32 data;
593
594         gk20a_dbg_fn("");
595
596         /* LDIV: Div4 mode (required); both  bypass and vco ratios 1:1 */
597         data = gk20a_readl(g, trim_sys_gpc2clk_out_r());
598         data = set_field(data,
599                         trim_sys_gpc2clk_out_sdiv14_m() |
600                         trim_sys_gpc2clk_out_vcodiv_m() |
601                         trim_sys_gpc2clk_out_bypdiv_m(),
602                         trim_sys_gpc2clk_out_sdiv14_indiv4_mode_f() |
603                         trim_sys_gpc2clk_out_vcodiv_by1_f() |
604                         trim_sys_gpc2clk_out_bypdiv_f(0));
605         gk20a_writel(g, trim_sys_gpc2clk_out_r(), data);
606
607         /*
608          * Clear global bypass control; PLL is still under bypass, since SEL_VCO
609          * is cleared by default.
610          */
611         data = gk20a_readl(g, trim_sys_bypassctrl_r());
612         data = set_field(data, trim_sys_bypassctrl_gpcpll_m(),
613                          trim_sys_bypassctrl_gpcpll_vco_f());
614         gk20a_writel(g, trim_sys_bypassctrl_r(), data);
615
616         /* Disable idle slow down */
617         data = gk20a_readl(g, therm_clk_slowdown_r(0));
618         data = set_field(data, therm_clk_slowdown_idle_factor_m(),
619                          therm_clk_slowdown_idle_factor_disabled_f());
620         gk20a_writel(g, therm_clk_slowdown_r(0), data);
621         gk20a_readl(g, therm_clk_slowdown_r(0));
622
623         return 0;
624 }
625
626 static int set_pll_target(struct gk20a *g, u32 freq, u32 old_freq)
627 {
628         struct clk_gk20a *clk = &g->clk;
629
630         if (freq > gpc_pll_params.max_freq)
631                 freq = gpc_pll_params.max_freq;
632         else if (freq < gpc_pll_params.min_freq)
633                 freq = gpc_pll_params.min_freq;
634
635         if (freq != old_freq) {
636                 /* gpc_pll.freq is changed to new value here */
637                 if (clk_config_pll(clk, &clk->gpc_pll, &gpc_pll_params,
638                                    &freq, true)) {
639                         gk20a_err(dev_from_gk20a(g),
640                                    "failed to set pll target for %d", freq);
641                         return -EINVAL;
642                 }
643         }
644         return 0;
645 }
646
647 static int set_pll_freq(struct gk20a *g, u32 freq, u32 old_freq)
648 {
649         struct clk_gk20a *clk = &g->clk;
650         int err = 0;
651
652         gk20a_dbg_fn("curr freq: %dMHz, target freq %dMHz", old_freq, freq);
653
654         if ((freq == old_freq) && clk->gpc_pll.enabled)
655                 return 0;
656
657         /* change frequency only if power is on */
658         if (g->clk.clk_hw_on) {
659                 err = clk_program_gpc_pll(g, &clk->gpc_pll, 1);
660                 if (err)
661                         err = clk_program_gpc_pll(g, &clk->gpc_pll, 0);
662         }
663
664         /* Just report error but not restore PLL since dvfs could already change
665             voltage even when it returns error. */
666         if (err)
667                 gk20a_err(dev_from_gk20a(g),
668                         "failed to set pll to %d", freq);
669         return err;
670 }
671
672 static int gm20b_clk_export_set_rate(void *data, unsigned long *rate)
673 {
674         u32 old_freq;
675         int ret = -ENODATA;
676         struct gk20a *g = data;
677         struct clk_gk20a *clk = &g->clk;
678
679         if (rate) {
680                 mutex_lock(&clk->clk_mutex);
681                 old_freq = clk->gpc_pll.freq;
682                 ret = set_pll_target(g, rate_gpu_to_gpc2clk(*rate), old_freq);
683                 if (!ret && clk->gpc_pll.enabled)
684                         ret = set_pll_freq(g, clk->gpc_pll.freq, old_freq);
685                 if (!ret)
686                         *rate = rate_gpc2clk_to_gpu(clk->gpc_pll.freq);
687                 mutex_unlock(&clk->clk_mutex);
688         }
689         return ret;
690 }
691
692 static int gm20b_clk_export_enable(void *data)
693 {
694         int ret;
695         struct gk20a *g = data;
696         struct clk_gk20a *clk = &g->clk;
697
698         mutex_lock(&clk->clk_mutex);
699         ret = set_pll_freq(g, clk->gpc_pll.freq, clk->gpc_pll.freq);
700         mutex_unlock(&clk->clk_mutex);
701         return ret;
702 }
703
704 static void gm20b_clk_export_disable(void *data)
705 {
706         struct gk20a *g = data;
707         struct clk_gk20a *clk = &g->clk;
708
709         mutex_lock(&clk->clk_mutex);
710         if (g->clk.clk_hw_on)
711                 clk_disable_gpcpll(g, 1);
712         mutex_unlock(&clk->clk_mutex);
713 }
714
715 static void gm20b_clk_export_init(void *data, unsigned long *rate, bool *state)
716 {
717         struct gk20a *g = data;
718         struct clk_gk20a *clk = &g->clk;
719
720         mutex_lock(&clk->clk_mutex);
721         if (state)
722                 *state = clk->gpc_pll.enabled;
723         if (rate)
724                 *rate = rate_gpc2clk_to_gpu(clk->gpc_pll.freq);
725         mutex_unlock(&clk->clk_mutex);
726 }
727
728 static struct tegra_clk_export_ops gm20b_clk_export_ops = {
729         .init = gm20b_clk_export_init,
730         .enable = gm20b_clk_export_enable,
731         .disable = gm20b_clk_export_disable,
732         .set_rate = gm20b_clk_export_set_rate,
733 };
734
735 static int gm20b_clk_register_export_ops(struct gk20a *g)
736 {
737         int ret;
738         struct clk *c;
739
740         if (gm20b_clk_export_ops.data)
741                 return 0;
742
743         gm20b_clk_export_ops.data = (void *)g;
744         c = g->clk.tegra_clk;
745         if (!c || !clk_get_parent(c))
746                 return -ENOSYS;
747
748         ret = tegra_clk_register_export_ops(clk_get_parent(c),
749                                             &gm20b_clk_export_ops);
750
751         return ret;
752 }
753
754 static int gm20b_init_clk_support(struct gk20a *g)
755 {
756         struct clk_gk20a *clk = &g->clk;
757         u32 err;
758
759         gk20a_dbg_fn("");
760
761         clk->g = g;
762
763         err = gm20b_init_clk_reset_enable_hw(g);
764         if (err)
765                 return err;
766
767         err = gm20b_init_clk_setup_sw(g);
768         if (err)
769                 return err;
770
771         mutex_lock(&clk->clk_mutex);
772         clk->clk_hw_on = true;
773
774         err = gm20b_init_clk_setup_hw(g);
775         mutex_unlock(&clk->clk_mutex);
776         if (err)
777                 return err;
778
779         err = gm20b_clk_register_export_ops(g);
780         if (err)
781                 return err;
782
783         /* FIXME: this effectively prevents host level clock gating */
784         err = clk_enable(g->clk.tegra_clk);
785         if (err)
786                 return err;
787
788         /* The prev call may not enable PLL if gbus is unbalanced - force it */
789         mutex_lock(&clk->clk_mutex);
790         err = set_pll_freq(g, clk->gpc_pll.freq, clk->gpc_pll.freq);
791         mutex_unlock(&clk->clk_mutex);
792         if (err)
793                 return err;
794
795 #ifdef CONFIG_DEBUG_FS
796         if (!clk->debugfs_set) {
797                 if (!clk_gm20b_debugfs_init(g))
798                         clk->debugfs_set = true;
799         }
800 #endif
801         return err;
802 }
803
804 static int gm20b_suspend_clk_support(struct gk20a *g)
805 {
806         int ret;
807
808         clk_disable(g->clk.tegra_clk);
809
810         /* The prev call may not disable PLL if gbus is unbalanced - force it */
811         mutex_lock(&g->clk.clk_mutex);
812         ret = clk_disable_gpcpll(g, 1);
813         g->clk.clk_hw_on = false;
814         mutex_unlock(&g->clk.clk_mutex);
815         return ret;
816 }
817
818 void gm20b_init_clk_ops(struct gpu_ops *gops)
819 {
820         gops->clk.init_clk_support = gm20b_init_clk_support;
821         gops->clk.suspend_clk_support = gm20b_suspend_clk_support;
822 }
823
824 #ifdef CONFIG_DEBUG_FS
825
826 static int rate_get(void *data, u64 *val)
827 {
828         struct gk20a *g = (struct gk20a *)data;
829         *val = (u64)gk20a_clk_get_rate(g);
830         return 0;
831 }
832 static int rate_set(void *data, u64 val)
833 {
834         struct gk20a *g = (struct gk20a *)data;
835         return gk20a_clk_set_rate(g, (u32)val);
836 }
837 DEFINE_SIMPLE_ATTRIBUTE(rate_fops, rate_get, rate_set, "%llu\n");
838
839 static int pll_reg_show(struct seq_file *s, void *data)
840 {
841         struct gk20a *g = s->private;
842         u32 reg, m, n, pl, f;
843
844         mutex_lock(&g->clk.clk_mutex);
845         if (!g->clk.clk_hw_on) {
846                 seq_printf(s, "gk20a powered down - no access to registers\n");
847                 mutex_unlock(&g->clk.clk_mutex);
848                 return 0;
849         }
850
851         reg = gk20a_readl(g, trim_sys_bypassctrl_r());
852         seq_printf(s, "bypassctrl = %s, ", reg ? "bypass" : "vco");
853         reg = gk20a_readl(g, trim_sys_sel_vco_r());
854         seq_printf(s, "sel_vco = %s, ", reg ? "vco" : "bypass");
855
856         reg = gk20a_readl(g, trim_sys_gpcpll_cfg_r());
857         seq_printf(s, "cfg  = 0x%x : %s : %s : %s\n", reg,
858                 trim_sys_gpcpll_cfg_enable_v(reg) ? "enabled" : "disabled",
859                 trim_sys_gpcpll_cfg_pll_lock_v(reg) ? "locked" : "unlocked",
860                 trim_sys_gpcpll_cfg_sync_mode_v(reg) ? "sync_on" : "sync_off");
861
862         reg = gk20a_readl(g, trim_sys_gpcpll_coeff_r());
863         m = trim_sys_gpcpll_coeff_mdiv_v(reg);
864         n = trim_sys_gpcpll_coeff_ndiv_v(reg);
865         pl = trim_sys_gpcpll_coeff_pldiv_v(reg);
866         f = g->clk.gpc_pll.clk_in * n / (m * pl_to_div(pl));
867         seq_printf(s, "coef = 0x%x : m = %u : n = %u : pl = %u", reg, m, n, pl);
868         seq_printf(s, " : pll_f(gpu_f) = %u(%u) kHz\n", f, f/2);
869         mutex_unlock(&g->clk.clk_mutex);
870         return 0;
871 }
872
873 static int pll_reg_open(struct inode *inode, struct file *file)
874 {
875         return single_open(file, pll_reg_show, inode->i_private);
876 }
877
878 static const struct file_operations pll_reg_fops = {
879         .open           = pll_reg_open,
880         .read           = seq_read,
881         .llseek         = seq_lseek,
882         .release        = single_release,
883 };
884
885 static int pll_reg_raw_show(struct seq_file *s, void *data)
886 {
887         struct gk20a *g = s->private;
888         u32 reg;
889
890         mutex_lock(&g->clk.clk_mutex);
891         if (!g->clk.clk_hw_on) {
892                 seq_puts(s, "gk20a powered down - no access to registers\n");
893                 mutex_unlock(&g->clk.clk_mutex);
894                 return 0;
895         }
896
897         seq_puts(s, "GPCPLL REGISTERS:\n");
898         for (reg = trim_sys_gpcpll_cfg_r(); reg <= trim_sys_gpcpll_dvfs2_r();
899               reg += sizeof(u32))
900                 seq_printf(s, "[0x%02x] = 0x%08x\n", reg, gk20a_readl(g, reg));
901
902         seq_puts(s, "\nGPC CLK OUT REGISTERS:\n");
903
904         reg = trim_sys_sel_vco_r();
905         seq_printf(s, "[0x%02x] = 0x%08x\n", reg, gk20a_readl(g, reg));
906         reg = trim_sys_gpc2clk_out_r();
907         seq_printf(s, "[0x%02x] = 0x%08x\n", reg, gk20a_readl(g, reg));
908         reg = trim_sys_bypassctrl_r();
909         seq_printf(s, "[0x%02x] = 0x%08x\n", reg, gk20a_readl(g, reg));
910
911         mutex_unlock(&g->clk.clk_mutex);
912         return 0;
913 }
914
915 static int pll_reg_raw_open(struct inode *inode, struct file *file)
916 {
917         return single_open(file, pll_reg_raw_show, inode->i_private);
918 }
919
920 static ssize_t pll_reg_raw_write(struct file *file,
921         const char __user *userbuf, size_t count, loff_t *ppos)
922 {
923         struct gk20a *g = file->f_path.dentry->d_inode->i_private;
924         char buf[80];
925         u32 reg, val;
926
927         if (sizeof(buf) <= count)
928                 return -EINVAL;
929
930         if (copy_from_user(buf, userbuf, count))
931                 return -EFAULT;
932
933         /* terminate buffer and trim - white spaces may be appended
934          *  at the end when invoked from shell command line */
935         buf[count] = '\0';
936         strim(buf);
937
938         if (sscanf(buf, "[0x%x] = 0x%x", &reg, &val) != 2)
939                 return -EINVAL;
940
941         if (((reg < trim_sys_gpcpll_cfg_r()) ||
942             (reg > trim_sys_gpcpll_dvfs2_r())) &&
943             (reg != trim_sys_sel_vco_r()) &&
944             (reg != trim_sys_gpc2clk_out_r()) &&
945             (reg != trim_sys_bypassctrl_r()))
946                 return -EPERM;
947
948         mutex_lock(&g->clk.clk_mutex);
949         if (!g->clk.clk_hw_on) {
950                 mutex_unlock(&g->clk.clk_mutex);
951                 return -EBUSY;
952         }
953         gk20a_writel(g, reg, val);
954         mutex_unlock(&g->clk.clk_mutex);
955         return count;
956 }
957
958 static const struct file_operations pll_reg_raw_fops = {
959         .open           = pll_reg_raw_open,
960         .read           = seq_read,
961         .write          = pll_reg_raw_write,
962         .llseek         = seq_lseek,
963         .release        = single_release,
964 };
965
966 static int monitor_get(void *data, u64 *val)
967 {
968         struct gk20a *g = (struct gk20a *)data;
969         struct clk_gk20a *clk = &g->clk;
970         u32 clk_slowdown, clk_slowdown_save;
971         int err;
972
973         u32 ncycle = 100; /* count GPCCLK for ncycle of clkin */
974         u64 freq = clk->gpc_pll.clk_in;
975         u32 count1, count2;
976
977         err = gk20a_busy(g->dev);
978         if (err)
979                 return err;
980
981         mutex_lock(&g->clk.clk_mutex);
982
983         /* Disable clock slowdown during measurements */
984         clk_slowdown_save = gk20a_readl(g, therm_clk_slowdown_r(0));
985         clk_slowdown = set_field(clk_slowdown_save,
986                                  therm_clk_slowdown_idle_factor_m(),
987                                  therm_clk_slowdown_idle_factor_disabled_f());
988         gk20a_writel(g, therm_clk_slowdown_r(0), clk_slowdown);
989         gk20a_readl(g, therm_clk_slowdown_r(0));
990
991         gk20a_writel(g, trim_gpc_clk_cntr_ncgpcclk_cfg_r(0),
992                      trim_gpc_clk_cntr_ncgpcclk_cfg_reset_asserted_f());
993         gk20a_writel(g, trim_gpc_clk_cntr_ncgpcclk_cfg_r(0),
994                      trim_gpc_clk_cntr_ncgpcclk_cfg_enable_asserted_f() |
995                      trim_gpc_clk_cntr_ncgpcclk_cfg_write_en_asserted_f() |
996                      trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(ncycle));
997         /* start */
998
999         /* It should take less than 5us to finish 100 cycle of 38.4MHz.
1000            But longer than 100us delay is required here. */
1001         gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cfg_r(0));
1002         udelay(200);
1003
1004         count1 = gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cnt_r(0));
1005         udelay(100);
1006         count2 = gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cnt_r(0));
1007         freq *= trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(count2);
1008         do_div(freq, ncycle);
1009         *val = freq;
1010
1011         /* Restore clock slowdown */
1012         gk20a_writel(g, therm_clk_slowdown_r(0), clk_slowdown_save);
1013         mutex_unlock(&g->clk.clk_mutex);
1014
1015         gk20a_idle(g->dev);
1016
1017         if (count1 != count2)
1018                 return -EBUSY;
1019         return 0;
1020 }
1021 DEFINE_SIMPLE_ATTRIBUTE(monitor_fops, monitor_get, NULL, "%llu\n");
1022
1023 static int clk_gm20b_debugfs_init(struct gk20a *g)
1024 {
1025         struct dentry *d;
1026         struct gk20a_platform *platform = platform_get_drvdata(g->dev);
1027
1028         d = debugfs_create_file(
1029                 "rate", S_IRUGO|S_IWUSR, platform->debugfs, g, &rate_fops);
1030         if (!d)
1031                 goto err_out;
1032
1033         d = debugfs_create_file(
1034                 "pll_reg", S_IRUGO, platform->debugfs, g, &pll_reg_fops);
1035         if (!d)
1036                 goto err_out;
1037
1038         d = debugfs_create_file("pll_reg_raw",
1039                 S_IRUGO, platform->debugfs, g, &pll_reg_raw_fops);
1040         if (!d)
1041                 goto err_out;
1042
1043         d = debugfs_create_file(
1044                 "monitor", S_IRUGO, platform->debugfs, g, &monitor_fops);
1045         if (!d)
1046                 goto err_out;
1047
1048         return 0;
1049
1050 err_out:
1051         pr_err("%s: Failed to make debugfs node\n", __func__);
1052         debugfs_remove_recursive(platform->debugfs);
1053         return -ENOMEM;
1054 }
1055
1056 #endif /* CONFIG_DEBUG_FS */