gpu: nvgpu: Update GM20b GPCPLL parameters
[linux-3.10.git] / drivers / gpu / nvgpu / gm20b / clk_gm20b.c
1 /*
2  * GM20B Clocks
3  *
4  * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/clk.h>
20 #include <linux/delay.h>        /* for mdelay */
21 #include <linux/module.h>
22 #include <linux/debugfs.h>
23 #include <linux/clk/tegra.h>
24 #include <mach/thermal.h>
25
26 #include "gk20a/gk20a.h"
27 #include "hw_trim_gm20b.h"
28 #include "hw_timer_gm20b.h"
29 #include "clk_gm20b.h"
30
31 #define gk20a_dbg_clk(fmt, arg...) \
32         gk20a_dbg(gpu_dbg_clk, fmt, ##arg)
33
34 /* from vbios PLL info table */
35 static struct pll_parms gpc_pll_params = {
36         128000,  2600000,       /* freq */
37         1300000, 2600000,       /* vco */
38         12000,   38400,         /* u */
39         1, 255,                 /* M */
40         8, 255,                 /* N */
41         1, 31,                  /* PL */
42 };
43
44 #ifdef CONFIG_DEBUG_FS
45 static int clk_gm20b_debugfs_init(struct gk20a *g);
46 #endif
47
48 /* 1:1 match between post divider settings and divisor value */
49 static inline u32 pl_to_div(u32 pl)
50 {
51         return pl;
52 }
53
54 static inline u32 div_to_pl(u32 div)
55 {
56         return div;
57 }
58
59 /* Calculate and update M/N/PL as well as pll->freq
60     ref_clk_f = clk_in_f;
61     u_f = ref_clk_f / M;
62     vco_f = u_f * N = ref_clk_f * N / M;
63     PLL output = gpc2clk = target clock frequency = vco_f / pl_to_pdiv(PL);
64     gpcclk = gpc2clk / 2; */
65 static int clk_config_pll(struct clk_gk20a *clk, struct pll *pll,
66         struct pll_parms *pll_params, u32 *target_freq, bool best_fit)
67 {
68         u32 min_vco_f, max_vco_f;
69         u32 best_M, best_N;
70         u32 low_PL, high_PL, best_PL;
71         u32 m, n, n2;
72         u32 target_vco_f, vco_f;
73         u32 ref_clk_f, target_clk_f, u_f;
74         u32 delta, lwv, best_delta = ~0;
75         u32 pl;
76
77         BUG_ON(target_freq == NULL);
78
79         gk20a_dbg_fn("request target freq %d MHz", *target_freq);
80
81         ref_clk_f = pll->clk_in;
82         target_clk_f = *target_freq;
83         max_vco_f = pll_params->max_vco;
84         min_vco_f = pll_params->min_vco;
85         best_M = pll_params->max_M;
86         best_N = pll_params->min_N;
87         best_PL = pll_params->min_PL;
88
89         target_vco_f = target_clk_f + target_clk_f / 50;
90         if (max_vco_f < target_vco_f)
91                 max_vco_f = target_vco_f;
92
93         /* Set PL search boundaries. */
94         high_PL = div_to_pl((max_vco_f + target_vco_f - 1) / target_vco_f);
95         high_PL = min(high_PL, pll_params->max_PL);
96         high_PL = max(high_PL, pll_params->min_PL);
97
98         low_PL = div_to_pl(min_vco_f / target_vco_f);
99         low_PL = min(low_PL, pll_params->max_PL);
100         low_PL = max(low_PL, pll_params->min_PL);
101
102         gk20a_dbg_info("low_PL %d(div%d), high_PL %d(div%d)",
103                         low_PL, pl_to_div(low_PL), high_PL, pl_to_div(high_PL));
104
105         for (pl = low_PL; pl <= high_PL; pl++) {
106                 target_vco_f = target_clk_f * pl_to_div(pl);
107
108                 for (m = pll_params->min_M; m <= pll_params->max_M; m++) {
109                         u_f = ref_clk_f / m;
110
111                         if (u_f < pll_params->min_u)
112                                 break;
113                         if (u_f > pll_params->max_u)
114                                 continue;
115
116                         n = (target_vco_f * m) / ref_clk_f;
117                         n2 = ((target_vco_f * m) + (ref_clk_f - 1)) / ref_clk_f;
118
119                         if (n > pll_params->max_N)
120                                 break;
121
122                         for (; n <= n2; n++) {
123                                 if (n < pll_params->min_N)
124                                         continue;
125                                 if (n > pll_params->max_N)
126                                         break;
127
128                                 vco_f = ref_clk_f * n / m;
129
130                                 if (vco_f >= min_vco_f && vco_f <= max_vco_f) {
131                                         lwv = (vco_f + (pl_to_div(pl) / 2))
132                                                 / pl_to_div(pl);
133                                         delta = abs(lwv - target_clk_f);
134
135                                         if (delta < best_delta) {
136                                                 best_delta = delta;
137                                                 best_M = m;
138                                                 best_N = n;
139                                                 best_PL = pl;
140
141                                                 if (best_delta == 0 ||
142                                                     /* 0.45% for non best fit */
143                                                     (!best_fit && (vco_f / best_delta > 218))) {
144                                                         goto found_match;
145                                                 }
146
147                                                 gk20a_dbg_info("delta %d @ M %d, N %d, PL %d",
148                                                         delta, m, n, pl);
149                                         }
150                                 }
151                         }
152                 }
153         }
154
155 found_match:
156         BUG_ON(best_delta == ~0);
157
158         if (best_fit && best_delta != 0)
159                 gk20a_dbg_clk("no best match for target @ %dMHz on gpc_pll",
160                         target_clk_f);
161
162         pll->M = best_M;
163         pll->N = best_N;
164         pll->PL = best_PL;
165
166         /* save current frequency */
167         pll->freq = ref_clk_f * pll->N / (pll->M * pl_to_div(pll->PL));
168
169         *target_freq = pll->freq;
170
171         gk20a_dbg_clk("actual target freq %d MHz, M %d, N %d, PL %d(div%d)",
172                 *target_freq, pll->M, pll->N, pll->PL, pl_to_div(pll->PL));
173
174         gk20a_dbg_fn("done");
175
176         return 0;
177 }
178
179 static int clk_slide_gpc_pll(struct gk20a *g, u32 n)
180 {
181         u32 data, coeff;
182         u32 nold;
183         int ramp_timeout = 500;
184
185         /* get old coefficients */
186         coeff = gk20a_readl(g, trim_sys_gpcpll_coeff_r());
187         nold = trim_sys_gpcpll_coeff_ndiv_v(coeff);
188
189         /* do nothing if NDIV is same */
190         if (n == nold)
191                 return 0;
192
193         /* setup */
194         data = gk20a_readl(g, trim_sys_gpcpll_cfg2_r());
195         data = set_field(data, trim_sys_gpcpll_cfg2_pll_stepa_m(),
196                         trim_sys_gpcpll_cfg2_pll_stepa_f(0x2b));
197         gk20a_writel(g, trim_sys_gpcpll_cfg2_r(), data);
198         data = gk20a_readl(g, trim_sys_gpcpll_cfg3_r());
199         data = set_field(data, trim_sys_gpcpll_cfg3_pll_stepb_m(),
200                         trim_sys_gpcpll_cfg3_pll_stepb_f(0xb));
201         gk20a_writel(g, trim_sys_gpcpll_cfg3_r(), data);
202
203         /* pll slowdown mode */
204         data = gk20a_readl(g, trim_sys_gpcpll_ndiv_slowdown_r());
205         data = set_field(data,
206                         trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_m(),
207                         trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_yes_f());
208         gk20a_writel(g, trim_sys_gpcpll_ndiv_slowdown_r(), data);
209
210         /* new ndiv ready for ramp */
211         coeff = gk20a_readl(g, trim_sys_gpcpll_coeff_r());
212         coeff = set_field(coeff, trim_sys_gpcpll_coeff_ndiv_m(),
213                         trim_sys_gpcpll_coeff_ndiv_f(n));
214         udelay(1);
215         gk20a_writel(g, trim_sys_gpcpll_coeff_r(), coeff);
216
217         /* dynamic ramp to new ndiv */
218         data = gk20a_readl(g, trim_sys_gpcpll_ndiv_slowdown_r());
219         data = set_field(data,
220                         trim_sys_gpcpll_ndiv_slowdown_en_dynramp_m(),
221                         trim_sys_gpcpll_ndiv_slowdown_en_dynramp_yes_f());
222         udelay(1);
223         gk20a_writel(g, trim_sys_gpcpll_ndiv_slowdown_r(), data);
224
225         do {
226                 udelay(1);
227                 ramp_timeout--;
228                 data = gk20a_readl(
229                         g, trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_r());
230                 if (trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_pll_dynramp_done_synced_v(data))
231                         break;
232         } while (ramp_timeout > 0);
233
234         /* exit slowdown mode */
235         data = gk20a_readl(g, trim_sys_gpcpll_ndiv_slowdown_r());
236         data = set_field(data,
237                         trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_m(),
238                         trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_no_f());
239         data = set_field(data,
240                         trim_sys_gpcpll_ndiv_slowdown_en_dynramp_m(),
241                         trim_sys_gpcpll_ndiv_slowdown_en_dynramp_no_f());
242         gk20a_writel(g, trim_sys_gpcpll_ndiv_slowdown_r(), data);
243         gk20a_readl(g, trim_sys_gpcpll_ndiv_slowdown_r());
244
245         if (ramp_timeout <= 0) {
246                 gk20a_err(dev_from_gk20a(g), "gpcpll dynamic ramp timeout");
247                 return -ETIMEDOUT;
248         }
249         return 0;
250 }
251
252 static int clk_program_gpc_pll(struct gk20a *g, struct clk_gk20a *clk,
253                         int allow_slide)
254 {
255         u32 data, cfg, coeff, timeout;
256         u32 m, n, pl;
257         u32 nlo;
258
259         gk20a_dbg_fn("");
260
261         if (!tegra_platform_is_silicon())
262                 return 0;
263
264         /* get old coefficients */
265         coeff = gk20a_readl(g, trim_sys_gpcpll_coeff_r());
266         m = trim_sys_gpcpll_coeff_mdiv_v(coeff);
267         n = trim_sys_gpcpll_coeff_ndiv_v(coeff);
268         pl = trim_sys_gpcpll_coeff_pldiv_v(coeff);
269
270         /* do NDIV slide if there is no change in M and PL */
271         cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r());
272         if (allow_slide && clk->gpc_pll.M == m && clk->gpc_pll.PL == pl
273                 && trim_sys_gpcpll_cfg_enable_v(cfg)) {
274                 return clk_slide_gpc_pll(g, clk->gpc_pll.N);
275         }
276
277         /* slide down to NDIV_LO */
278         nlo = DIV_ROUND_UP(m * gpc_pll_params.min_vco, clk->gpc_pll.clk_in);
279         if (allow_slide && trim_sys_gpcpll_cfg_enable_v(cfg)) {
280                 int ret = clk_slide_gpc_pll(g, nlo);
281                 if (ret)
282                         return ret;
283         }
284
285         /* split FO-to-bypass jump in halfs by setting out divider 1:2 */
286         data = gk20a_readl(g, trim_sys_gpc2clk_out_r());
287         data = set_field(data, trim_sys_gpc2clk_out_vcodiv_m(),
288                 trim_sys_gpc2clk_out_vcodiv_f(2));
289         gk20a_writel(g, trim_sys_gpc2clk_out_r(), data);
290
291         /* put PLL in bypass before programming it */
292         data = gk20a_readl(g, trim_sys_sel_vco_r());
293         data = set_field(data, trim_sys_sel_vco_gpc2clk_out_m(),
294                 trim_sys_sel_vco_gpc2clk_out_bypass_f());
295         udelay(2);
296         gk20a_writel(g, trim_sys_sel_vco_r(), data);
297
298         /* get out from IDDQ */
299         cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r());
300         if (trim_sys_gpcpll_cfg_iddq_v(cfg)) {
301                 cfg = set_field(cfg, trim_sys_gpcpll_cfg_iddq_m(),
302                                 trim_sys_gpcpll_cfg_iddq_power_on_v());
303                 gk20a_writel(g, trim_sys_gpcpll_cfg_r(), cfg);
304                 gk20a_readl(g, trim_sys_gpcpll_cfg_r());
305                 udelay(2);
306         }
307
308         /* disable PLL before changing coefficients */
309         cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r());
310         cfg = set_field(cfg, trim_sys_gpcpll_cfg_enable_m(),
311                         trim_sys_gpcpll_cfg_enable_no_f());
312         gk20a_writel(g, trim_sys_gpcpll_cfg_r(), cfg);
313         gk20a_readl(g, trim_sys_gpcpll_cfg_r());
314
315         /* change coefficients */
316         nlo = DIV_ROUND_UP(clk->gpc_pll.M * gpc_pll_params.min_vco,
317                         clk->gpc_pll.clk_in);
318         coeff = trim_sys_gpcpll_coeff_mdiv_f(clk->gpc_pll.M) |
319                 trim_sys_gpcpll_coeff_ndiv_f(allow_slide ?
320                                              nlo : clk->gpc_pll.N) |
321                 trim_sys_gpcpll_coeff_pldiv_f(clk->gpc_pll.PL);
322         gk20a_writel(g, trim_sys_gpcpll_coeff_r(), coeff);
323
324         /* enable PLL after changing coefficients */
325         cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r());
326         cfg = set_field(cfg, trim_sys_gpcpll_cfg_enable_m(),
327                         trim_sys_gpcpll_cfg_enable_yes_f());
328         gk20a_writel(g, trim_sys_gpcpll_cfg_r(), cfg);
329
330         /* lock pll */
331         cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r());
332         if (cfg & trim_sys_gpcpll_cfg_enb_lckdet_power_off_f()){
333                 cfg = set_field(cfg, trim_sys_gpcpll_cfg_enb_lckdet_m(),
334                         trim_sys_gpcpll_cfg_enb_lckdet_power_on_f());
335                 gk20a_writel(g, trim_sys_gpcpll_cfg_r(), cfg);
336         }
337
338         /* wait pll lock */
339         timeout = clk->pll_delay / 2 + 1;
340         do {
341                 cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r());
342                 if (cfg & trim_sys_gpcpll_cfg_pll_lock_true_f())
343                         goto pll_locked;
344                 udelay(2);
345         } while (--timeout > 0);
346
347         /* PLL is messed up. What can we do here? */
348         BUG();
349         return -EBUSY;
350
351 pll_locked:
352         /* put PLL back on vco */
353         data = gk20a_readl(g, trim_sys_sel_vco_r());
354         data = set_field(data, trim_sys_sel_vco_gpc2clk_out_m(),
355                 trim_sys_sel_vco_gpc2clk_out_vco_f());
356         gk20a_writel(g, trim_sys_sel_vco_r(), data);
357         clk->gpc_pll.enabled = true;
358
359         /* restore out divider 1:1 */
360         data = gk20a_readl(g, trim_sys_gpc2clk_out_r());
361         data = set_field(data, trim_sys_gpc2clk_out_vcodiv_m(),
362                 trim_sys_gpc2clk_out_vcodiv_by1_f());
363         udelay(2);
364         gk20a_writel(g, trim_sys_gpc2clk_out_r(), data);
365
366         /* slide up to target NDIV */
367         return clk_slide_gpc_pll(g, clk->gpc_pll.N);
368 }
369
370 static int clk_disable_gpcpll(struct gk20a *g, int allow_slide)
371 {
372         u32 cfg, coeff, m, nlo;
373         struct clk_gk20a *clk = &g->clk;
374
375         /* slide to VCO min */
376         cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r());
377         if (allow_slide && trim_sys_gpcpll_cfg_enable_v(cfg)) {
378                 coeff = gk20a_readl(g, trim_sys_gpcpll_coeff_r());
379                 m = trim_sys_gpcpll_coeff_mdiv_v(coeff);
380                 nlo = DIV_ROUND_UP(m * gpc_pll_params.min_vco,
381                                    clk->gpc_pll.clk_in);
382                 clk_slide_gpc_pll(g, nlo);
383         }
384
385         /* put PLL in bypass before disabling it */
386         cfg = gk20a_readl(g, trim_sys_sel_vco_r());
387         cfg = set_field(cfg, trim_sys_sel_vco_gpc2clk_out_m(),
388                         trim_sys_sel_vco_gpc2clk_out_bypass_f());
389         gk20a_writel(g, trim_sys_sel_vco_r(), cfg);
390
391         /* disable PLL */
392         cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r());
393         cfg = set_field(cfg, trim_sys_gpcpll_cfg_enable_m(),
394                         trim_sys_gpcpll_cfg_enable_no_f());
395         gk20a_writel(g, trim_sys_gpcpll_cfg_r(), cfg);
396         gk20a_readl(g, trim_sys_gpcpll_cfg_r());
397
398         clk->gpc_pll.enabled = false;
399         return 0;
400 }
401
402 static int gm20b_init_clk_reset_enable_hw(struct gk20a *g)
403 {
404         gk20a_dbg_fn("");
405         return 0;
406 }
407
408 struct clk *gm20b_clk_get(struct gk20a *g)
409 {
410         if (!g->clk.tegra_clk) {
411                 struct clk *clk;
412
413                 clk = clk_get_sys("tegra_gk20a", "gpu");
414                 if (IS_ERR(clk)) {
415                         gk20a_err(dev_from_gk20a(g),
416                                 "fail to get tegra gpu clk tegra_gk20a/gpu");
417                         return NULL;
418                 }
419                 g->clk.tegra_clk = clk;
420         }
421
422         return g->clk.tegra_clk;
423 }
424
425 static int gm20b_init_clk_setup_sw(struct gk20a *g)
426 {
427         struct clk_gk20a *clk = &g->clk;
428         static int initialized;
429         struct clk *ref;
430         unsigned long ref_rate;
431
432         gk20a_dbg_fn("");
433
434         if (clk->sw_ready) {
435                 gk20a_dbg_fn("skip init");
436                 return 0;
437         }
438
439         if (!gk20a_clk_get(g))
440                 return -EINVAL;
441
442         ref = clk_get_parent(clk_get_parent(clk->tegra_clk));
443         if (IS_ERR(ref)) {
444                 gk20a_err(dev_from_gk20a(g),
445                         "failed to get GPCPLL reference clock");
446                 return -EINVAL;
447         }
448         ref_rate = clk_get_rate(ref);
449
450         clk->pll_delay = 300; /* usec */
451
452         clk->gpc_pll.id = GK20A_GPC_PLL;
453         clk->gpc_pll.clk_in = ref_rate / KHZ;
454
455         /* Initial frequency: 1/3 VCO min (low enough to be safe at Vmin) */
456         if (!initialized) {
457                 initialized = 1;
458                 clk->gpc_pll.M = 1;
459                 clk->gpc_pll.N = DIV_ROUND_UP(gpc_pll_params.min_vco,
460                                         clk->gpc_pll.clk_in);
461                 clk->gpc_pll.PL = 3;
462                 clk->gpc_pll.freq = clk->gpc_pll.clk_in * clk->gpc_pll.N;
463                 clk->gpc_pll.freq /= pl_to_div(clk->gpc_pll.PL);
464         }
465
466         mutex_init(&clk->clk_mutex);
467
468         clk->sw_ready = true;
469
470         gk20a_dbg_fn("done");
471         return 0;
472 }
473
474 static int gm20b_init_clk_setup_hw(struct gk20a *g)
475 {
476         u32 data;
477
478         gk20a_dbg_fn("");
479
480         /* LDIV: Div4 mode (required); both  bypass and vco ratios 1:1 */
481         data = gk20a_readl(g, trim_sys_gpc2clk_out_r());
482         data = set_field(data,
483                         trim_sys_gpc2clk_out_sdiv14_m() |
484                         trim_sys_gpc2clk_out_vcodiv_m() |
485                         trim_sys_gpc2clk_out_bypdiv_m(),
486                         trim_sys_gpc2clk_out_sdiv14_indiv4_mode_f() |
487                         trim_sys_gpc2clk_out_vcodiv_by1_f() |
488                         trim_sys_gpc2clk_out_bypdiv_f(0));
489         gk20a_writel(g, trim_sys_gpc2clk_out_r(), data);
490
491         /*
492          * Clear global bypass control; PLL is still under bypass, since SEL_VCO
493          * is cleared by default.
494          */
495         data = gk20a_readl(g, trim_sys_bypassctrl_r());
496         data = set_field(data, trim_sys_bypassctrl_gpcpll_m(),
497                          trim_sys_bypassctrl_gpcpll_vco_f());
498         gk20a_writel(g, trim_sys_bypassctrl_r(), data);
499
500         return 0;
501 }
502
503 static int set_pll_target(struct gk20a *g, u32 freq, u32 old_freq)
504 {
505         struct clk_gk20a *clk = &g->clk;
506
507         if (freq > gpc_pll_params.max_freq)
508                 freq = gpc_pll_params.max_freq;
509         else if (freq < gpc_pll_params.min_freq)
510                 freq = gpc_pll_params.min_freq;
511
512         if (freq != old_freq) {
513                 /* gpc_pll.freq is changed to new value here */
514                 if (clk_config_pll(clk, &clk->gpc_pll, &gpc_pll_params,
515                                    &freq, true)) {
516                         gk20a_err(dev_from_gk20a(g),
517                                    "failed to set pll target for %d", freq);
518                         return -EINVAL;
519                 }
520         }
521         return 0;
522 }
523
524 static int set_pll_freq(struct gk20a *g, u32 freq, u32 old_freq)
525 {
526         struct clk_gk20a *clk = &g->clk;
527         int err = 0;
528
529         gk20a_dbg_fn("curr freq: %dMHz, target freq %dMHz", old_freq, freq);
530
531         if ((freq == old_freq) && clk->gpc_pll.enabled)
532                 return 0;
533
534         /* change frequency only if power is on */
535         if (g->clk.clk_hw_on) {
536                 err = clk_program_gpc_pll(g, clk, 1);
537                 if (err)
538                         err = clk_program_gpc_pll(g, clk, 0);
539         }
540
541         /* Just report error but not restore PLL since dvfs could already change
542             voltage even when it returns error. */
543         if (err)
544                 gk20a_err(dev_from_gk20a(g),
545                         "failed to set pll to %d", freq);
546         return err;
547 }
548
549 static int gm20b_clk_export_set_rate(void *data, unsigned long *rate)
550 {
551         u32 old_freq;
552         int ret = -ENODATA;
553         struct gk20a *g = data;
554         struct clk_gk20a *clk = &g->clk;
555
556         if (rate) {
557                 mutex_lock(&clk->clk_mutex);
558                 old_freq = clk->gpc_pll.freq;
559                 ret = set_pll_target(g, rate_gpu_to_gpc2clk(*rate), old_freq);
560                 if (!ret && clk->gpc_pll.enabled)
561                         ret = set_pll_freq(g, clk->gpc_pll.freq, old_freq);
562                 if (!ret)
563                         *rate = rate_gpc2clk_to_gpu(clk->gpc_pll.freq);
564                 mutex_unlock(&clk->clk_mutex);
565         }
566         return ret;
567 }
568
569 static int gm20b_clk_export_enable(void *data)
570 {
571         int ret;
572         struct gk20a *g = data;
573         struct clk_gk20a *clk = &g->clk;
574
575         mutex_lock(&clk->clk_mutex);
576         ret = set_pll_freq(g, clk->gpc_pll.freq, clk->gpc_pll.freq);
577         mutex_unlock(&clk->clk_mutex);
578         return ret;
579 }
580
581 static void gm20b_clk_export_disable(void *data)
582 {
583         struct gk20a *g = data;
584         struct clk_gk20a *clk = &g->clk;
585
586         mutex_lock(&clk->clk_mutex);
587         if (g->clk.clk_hw_on)
588                 clk_disable_gpcpll(g, 1);
589         mutex_unlock(&clk->clk_mutex);
590 }
591
592 static void gm20b_clk_export_init(void *data, unsigned long *rate, bool *state)
593 {
594         struct gk20a *g = data;
595         struct clk_gk20a *clk = &g->clk;
596
597         mutex_lock(&clk->clk_mutex);
598         if (state)
599                 *state = clk->gpc_pll.enabled;
600         if (rate)
601                 *rate = rate_gpc2clk_to_gpu(clk->gpc_pll.freq);
602         mutex_unlock(&clk->clk_mutex);
603 }
604
605 static struct tegra_clk_export_ops gm20b_clk_export_ops = {
606         .init = gm20b_clk_export_init,
607         .enable = gm20b_clk_export_enable,
608         .disable = gm20b_clk_export_disable,
609         .set_rate = gm20b_clk_export_set_rate,
610 };
611
612 static int gm20b_clk_register_export_ops(struct gk20a *g)
613 {
614         int ret;
615         struct clk *c;
616
617         if (gm20b_clk_export_ops.data)
618                 return 0;
619
620         gm20b_clk_export_ops.data = (void *)g;
621         c = g->clk.tegra_clk;
622         if (!c || !clk_get_parent(c))
623                 return -ENOSYS;
624
625         ret = tegra_clk_register_export_ops(clk_get_parent(c),
626                                             &gm20b_clk_export_ops);
627
628         return ret;
629 }
630
631 static int gm20b_init_clk_support(struct gk20a *g)
632 {
633         struct clk_gk20a *clk = &g->clk;
634         u32 err;
635
636         gk20a_dbg_fn("");
637
638         clk->g = g;
639
640         err = gm20b_init_clk_reset_enable_hw(g);
641         if (err)
642                 return err;
643
644         err = gm20b_init_clk_setup_sw(g);
645         if (err)
646                 return err;
647
648         mutex_lock(&clk->clk_mutex);
649         clk->clk_hw_on = true;
650
651         err = gm20b_init_clk_setup_hw(g);
652         mutex_unlock(&clk->clk_mutex);
653         if (err)
654                 return err;
655
656         err = gm20b_clk_register_export_ops(g);
657         if (err)
658                 return err;
659
660         /* FIXME: this effectively prevents host level clock gating */
661         err = clk_enable(g->clk.tegra_clk);
662         if (err)
663                 return err;
664
665         /* The prev call may not enable PLL if gbus is unbalanced - force it */
666         mutex_lock(&clk->clk_mutex);
667         err = set_pll_freq(g, clk->gpc_pll.freq, clk->gpc_pll.freq);
668         mutex_unlock(&clk->clk_mutex);
669         if (err)
670                 return err;
671
672 #ifdef CONFIG_DEBUG_FS
673         if (!clk->debugfs_set) {
674                 if (!clk_gm20b_debugfs_init(g))
675                         clk->debugfs_set = true;
676         }
677 #endif
678         return err;
679 }
680
681 static int gm20b_suspend_clk_support(struct gk20a *g)
682 {
683         int ret;
684
685         clk_disable(g->clk.tegra_clk);
686
687         /* The prev call may not disable PLL if gbus is unbalanced - force it */
688         mutex_lock(&g->clk.clk_mutex);
689         ret = clk_disable_gpcpll(g, 1);
690         g->clk.clk_hw_on = false;
691         mutex_unlock(&g->clk.clk_mutex);
692         return ret;
693 }
694
695 void gm20b_init_clk_ops(struct gpu_ops *gops)
696 {
697         gops->clk.init_clk_support = gm20b_init_clk_support;
698         gops->clk.suspend_clk_support = gm20b_suspend_clk_support;
699 }
700
701 #ifdef CONFIG_DEBUG_FS
702
703 static int rate_get(void *data, u64 *val)
704 {
705         struct gk20a *g = (struct gk20a *)data;
706         *val = (u64)gk20a_clk_get_rate(g);
707         return 0;
708 }
709 static int rate_set(void *data, u64 val)
710 {
711         struct gk20a *g = (struct gk20a *)data;
712         return gk20a_clk_set_rate(g, (u32)val);
713 }
714 DEFINE_SIMPLE_ATTRIBUTE(rate_fops, rate_get, rate_set, "%llu\n");
715
716 static int pll_reg_show(struct seq_file *s, void *data)
717 {
718         struct gk20a *g = s->private;
719         u32 reg, m, n, pl, f;
720
721         mutex_lock(&g->clk.clk_mutex);
722         if (!g->clk.clk_hw_on) {
723                 seq_printf(s, "gk20a powered down - no access to registers\n");
724                 mutex_unlock(&g->clk.clk_mutex);
725                 return 0;
726         }
727
728         reg = gk20a_readl(g, trim_sys_bypassctrl_r());
729         seq_printf(s, "bypassctrl = %s, ", reg ? "bypass" : "vco");
730         reg = gk20a_readl(g, trim_sys_sel_vco_r());
731         seq_printf(s, "sel_vco = %s, ", reg ? "vco" : "bypass");
732
733         reg = gk20a_readl(g, trim_sys_gpcpll_cfg_r());
734         seq_printf(s, "cfg  = 0x%x : %s : %s\n", reg,
735                    trim_sys_gpcpll_cfg_enable_v(reg) ? "enabled" : "disabled",
736                    trim_sys_gpcpll_cfg_pll_lock_v(reg) ? "locked" : "unlocked");
737
738         reg = gk20a_readl(g, trim_sys_gpcpll_coeff_r());
739         m = trim_sys_gpcpll_coeff_mdiv_v(reg);
740         n = trim_sys_gpcpll_coeff_ndiv_v(reg);
741         pl = trim_sys_gpcpll_coeff_pldiv_v(reg);
742         f = g->clk.gpc_pll.clk_in * n / (m * pl_to_div(pl));
743         seq_printf(s, "coef = 0x%x : m = %u : n = %u : pl = %u", reg, m, n, pl);
744         seq_printf(s, " : pll_f(gpu_f) = %u(%u) kHz\n", f, f/2);
745         mutex_unlock(&g->clk.clk_mutex);
746         return 0;
747 }
748
749 static int pll_reg_open(struct inode *inode, struct file *file)
750 {
751         return single_open(file, pll_reg_show, inode->i_private);
752 }
753
754 static const struct file_operations pll_reg_fops = {
755         .open           = pll_reg_open,
756         .read           = seq_read,
757         .llseek         = seq_lseek,
758         .release        = single_release,
759 };
760
761 static int monitor_get(void *data, u64 *val)
762 {
763         struct gk20a *g = (struct gk20a *)data;
764         struct clk_gk20a *clk = &g->clk;
765         int err;
766
767         u32 ncycle = 100; /* count GPCCLK for ncycle of clkin */
768         u64 freq = clk->gpc_pll.clk_in;
769         u32 count1, count2;
770
771         err = gk20a_busy(g->dev);
772         if (err)
773                 return err;
774
775         gk20a_writel(g, trim_gpc_clk_cntr_ncgpcclk_cfg_r(0),
776                      trim_gpc_clk_cntr_ncgpcclk_cfg_reset_asserted_f());
777         gk20a_writel(g, trim_gpc_clk_cntr_ncgpcclk_cfg_r(0),
778                      trim_gpc_clk_cntr_ncgpcclk_cfg_enable_asserted_f() |
779                      trim_gpc_clk_cntr_ncgpcclk_cfg_write_en_asserted_f() |
780                      trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(ncycle));
781         /* start */
782
783         /* It should take about 8us to finish 100 cycle of 12MHz.
784            But longer than 100us delay is required here. */
785         gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cfg_r(0));
786         udelay(2000);
787
788         count1 = gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cnt_r(0));
789         udelay(100);
790         count2 = gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cnt_r(0));
791         freq *= trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(count2);
792         do_div(freq, ncycle);
793         *val = freq;
794
795         gk20a_idle(g->dev);
796
797         if (count1 != count2)
798                 return -EBUSY;
799         return 0;
800 }
801 DEFINE_SIMPLE_ATTRIBUTE(monitor_fops, monitor_get, NULL, "%llu\n");
802
803 static int clk_gm20b_debugfs_init(struct gk20a *g)
804 {
805         struct dentry *d;
806         struct gk20a_platform *platform = platform_get_drvdata(g->dev);
807
808         d = debugfs_create_file(
809                 "rate", S_IRUGO|S_IWUSR, platform->debugfs, g, &rate_fops);
810         if (!d)
811                 goto err_out;
812
813         d = debugfs_create_file(
814                 "pll_reg", S_IRUGO, platform->debugfs, g, &pll_reg_fops);
815         if (!d)
816                 goto err_out;
817
818         d = debugfs_create_file(
819                 "monitor", S_IRUGO, platform->debugfs, g, &monitor_fops);
820         if (!d)
821                 goto err_out;
822
823         return 0;
824
825 err_out:
826         pr_err("%s: Failed to make debugfs node\n", __func__);
827         debugfs_remove_recursive(platform->debugfs);
828         return -ENOMEM;
829 }
830
831 #endif /* CONFIG_DEBUG_FS */