drm/radeon/r600: fix tiling issues in CS checker.
[linux-3.10.git] / drivers / gpu / drm / radeon / r600_cs.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <linux/kernel.h>
29 #include "drmP.h"
30 #include "radeon.h"
31 #include "r600d.h"
32 #include "r600_reg_safe.h"
33
34 static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
35                                         struct radeon_cs_reloc **cs_reloc);
36 static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
37                                         struct radeon_cs_reloc **cs_reloc);
38 typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**);
39 static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm;
40 extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size);
41
42
43 struct r600_cs_track {
44         /* configuration we miror so that we use same code btw kms/ums */
45         u32                     group_size;
46         u32                     nbanks;
47         u32                     npipes;
48         /* value we track */
49         u32                     sq_config;
50         u32                     nsamples;
51         u32                     cb_color_base_last[8];
52         struct radeon_bo        *cb_color_bo[8];
53         u32                     cb_color_bo_offset[8];
54         struct radeon_bo        *cb_color_frag_bo[8];
55         struct radeon_bo        *cb_color_tile_bo[8];
56         u32                     cb_color_info[8];
57         u32                     cb_color_size_idx[8];
58         u32                     cb_target_mask;
59         u32                     cb_shader_mask;
60         u32                     cb_color_size[8];
61         u32                     vgt_strmout_en;
62         u32                     vgt_strmout_buffer_en;
63         u32                     db_depth_control;
64         u32                     db_depth_info;
65         u32                     db_depth_size_idx;
66         u32                     db_depth_view;
67         u32                     db_depth_size;
68         u32                     db_offset;
69         struct radeon_bo        *db_bo;
70 };
71
72 static inline int r600_bpe_from_format(u32 *bpe, u32 format)
73 {
74         switch (format) {
75         case V_038004_COLOR_8:
76         case V_038004_COLOR_4_4:
77         case V_038004_COLOR_3_3_2:
78         case V_038004_FMT_1:
79                 *bpe = 1;
80                 break;
81         case V_038004_COLOR_16:
82         case V_038004_COLOR_16_FLOAT:
83         case V_038004_COLOR_8_8:
84         case V_038004_COLOR_5_6_5:
85         case V_038004_COLOR_6_5_5:
86         case V_038004_COLOR_1_5_5_5:
87         case V_038004_COLOR_4_4_4_4:
88         case V_038004_COLOR_5_5_5_1:
89                 *bpe = 2;
90                 break;
91         case V_038004_FMT_8_8_8:
92                 *bpe = 3;
93                 break;
94         case V_038004_COLOR_32:
95         case V_038004_COLOR_32_FLOAT:
96         case V_038004_COLOR_16_16:
97         case V_038004_COLOR_16_16_FLOAT:
98         case V_038004_COLOR_8_24:
99         case V_038004_COLOR_8_24_FLOAT:
100         case V_038004_COLOR_24_8:
101         case V_038004_COLOR_24_8_FLOAT:
102         case V_038004_COLOR_10_11_11:
103         case V_038004_COLOR_10_11_11_FLOAT:
104         case V_038004_COLOR_11_11_10:
105         case V_038004_COLOR_11_11_10_FLOAT:
106         case V_038004_COLOR_2_10_10_10:
107         case V_038004_COLOR_8_8_8_8:
108         case V_038004_COLOR_10_10_10_2:
109         case V_038004_FMT_5_9_9_9_SHAREDEXP:
110         case V_038004_FMT_32_AS_8:
111         case V_038004_FMT_32_AS_8_8:
112                 *bpe = 4;
113                 break;
114         case V_038004_COLOR_X24_8_32_FLOAT:
115         case V_038004_COLOR_32_32:
116         case V_038004_COLOR_32_32_FLOAT:
117         case V_038004_COLOR_16_16_16_16:
118         case V_038004_COLOR_16_16_16_16_FLOAT:
119                 *bpe = 8;
120                 break;
121         case V_038004_FMT_16_16_16:
122         case V_038004_FMT_16_16_16_FLOAT:
123                 *bpe = 6;
124                 break;
125         case V_038004_FMT_32_32_32:
126         case V_038004_FMT_32_32_32_FLOAT:
127                 *bpe = 12;
128                 break;
129         case V_038004_COLOR_32_32_32_32:
130         case V_038004_COLOR_32_32_32_32_FLOAT:
131                 *bpe = 16;
132                 break;
133         case V_038004_FMT_GB_GR:
134         case V_038004_FMT_BG_RG:
135         case V_038004_COLOR_INVALID:
136         default:
137                 *bpe = 16;
138                 return -EINVAL;
139         }
140         return 0;
141 }
142
143 static void r600_cs_track_init(struct r600_cs_track *track)
144 {
145         int i;
146
147         /* assume DX9 mode */
148         track->sq_config = DX9_CONSTS;
149         for (i = 0; i < 8; i++) {
150                 track->cb_color_base_last[i] = 0;
151                 track->cb_color_size[i] = 0;
152                 track->cb_color_size_idx[i] = 0;
153                 track->cb_color_info[i] = 0;
154                 track->cb_color_bo[i] = NULL;
155                 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
156         }
157         track->cb_target_mask = 0xFFFFFFFF;
158         track->cb_shader_mask = 0xFFFFFFFF;
159         track->db_bo = NULL;
160         /* assume the biggest format and that htile is enabled */
161         track->db_depth_info = 7 | (1 << 25);
162         track->db_depth_view = 0xFFFFC000;
163         track->db_depth_size = 0xFFFFFFFF;
164         track->db_depth_size_idx = 0;
165         track->db_depth_control = 0xFFFFFFFF;
166 }
167
168 static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
169 {
170         struct r600_cs_track *track = p->track;
171         u32 bpe = 0, pitch, slice_tile_max, size, tmp, height, pitch_align;
172         volatile u32 *ib = p->ib->ptr;
173         unsigned array_mode;
174
175         if (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
176                 dev_warn(p->dev, "FMASK or CMASK buffer are not supported by this kernel\n");
177                 return -EINVAL;
178         }
179         size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i];
180         if (r600_bpe_from_format(&bpe, G_0280A0_FORMAT(track->cb_color_info[i]))) {
181                 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n",
182                          __func__, __LINE__, G_0280A0_FORMAT(track->cb_color_info[i]),
183                         i, track->cb_color_info[i]);
184                 return -EINVAL;
185         }
186         /* pitch is the number of 8x8 tiles per row */
187         pitch = G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1;
188         slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1;
189         slice_tile_max *= 64;
190         height = slice_tile_max / (pitch * 8);
191         if (height > 8192)
192                 height = 8192;
193         array_mode = G_0280A0_ARRAY_MODE(track->cb_color_info[i]);
194         switch (array_mode) {
195         case V_0280A0_ARRAY_LINEAR_GENERAL:
196                 /* technically height & 0x7 */
197                 break;
198         case V_0280A0_ARRAY_LINEAR_ALIGNED:
199                 pitch_align = max((u32)64, (u32)(track->group_size / bpe)) / 8;
200                 if (!IS_ALIGNED(pitch, pitch_align)) {
201                         dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
202                                  __func__, __LINE__, pitch);
203                         return -EINVAL;
204                 }
205                 if (!IS_ALIGNED(height, 8)) {
206                         dev_warn(p->dev, "%s:%d cb height (%d) invalid\n",
207                                  __func__, __LINE__, height);
208                         return -EINVAL;
209                 }
210                 break;
211         case V_0280A0_ARRAY_1D_TILED_THIN1:
212                 pitch_align = max((u32)8, (u32)(track->group_size / (8 * bpe * track->nsamples))) / 8;
213                 if (!IS_ALIGNED(pitch, pitch_align)) {
214                         dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
215                                  __func__, __LINE__, pitch);
216                         return -EINVAL;
217                 }
218                 if (!IS_ALIGNED(height, 8)) {
219                         dev_warn(p->dev, "%s:%d cb height (%d) invalid\n",
220                                  __func__, __LINE__, height);
221                         return -EINVAL;
222                 }
223                 break;
224         case V_0280A0_ARRAY_2D_TILED_THIN1:
225                 pitch_align = max((u32)track->nbanks,
226                                   (u32)(((track->group_size / 8) / (bpe * track->nsamples)) * track->nbanks)) / 8;
227                 if (!IS_ALIGNED(pitch, pitch_align)) {
228                         dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
229                                 __func__, __LINE__, pitch);
230                         return -EINVAL;
231                 }
232                 if (!IS_ALIGNED((height / 8), track->nbanks)) {
233                         dev_warn(p->dev, "%s:%d cb height (%d) invalid\n",
234                                  __func__, __LINE__, height);
235                         return -EINVAL;
236                 }
237                 break;
238         default:
239                 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
240                         G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
241                         track->cb_color_info[i]);
242                 return -EINVAL;
243         }
244         /* check offset */
245         tmp = height * pitch * 8 * bpe;
246         if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
247                 if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) {
248                         /* the initial DDX does bad things with the CB size occasionally */
249                         /* it rounds up height too far for slice tile max but the BO is smaller */
250                         tmp = (height - 7) * 8 * bpe;
251                         if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
252                                 dev_warn(p->dev, "%s offset[%d] %d %d %lu too big\n", __func__, i, track->cb_color_bo_offset[i], tmp, radeon_bo_size(track->cb_color_bo[i]));
253                                 return -EINVAL;
254                         }
255                 } else {
256                         dev_warn(p->dev, "%s offset[%d] %d %d %lu too big\n", __func__, i, track->cb_color_bo_offset[i], tmp, radeon_bo_size(track->cb_color_bo[i]));
257                         return -EINVAL;
258                 }
259         }
260         if (!IS_ALIGNED(track->cb_color_bo_offset[i], track->group_size)) {
261                 dev_warn(p->dev, "%s offset[%d] %d not aligned\n", __func__, i, track->cb_color_bo_offset[i]);
262                 return -EINVAL;
263         }
264         /* limit max tile */
265         tmp = (height * pitch * 8) >> 6;
266         if (tmp < slice_tile_max)
267                 slice_tile_max = tmp;
268         tmp = S_028060_PITCH_TILE_MAX(pitch - 1) |
269                 S_028060_SLICE_TILE_MAX(slice_tile_max - 1);
270         ib[track->cb_color_size_idx[i]] = tmp;
271         return 0;
272 }
273
274 static int r600_cs_track_check(struct radeon_cs_parser *p)
275 {
276         struct r600_cs_track *track = p->track;
277         u32 tmp;
278         int r, i;
279         volatile u32 *ib = p->ib->ptr;
280
281         /* on legacy kernel we don't perform advanced check */
282         if (p->rdev == NULL)
283                 return 0;
284         /* we don't support out buffer yet */
285         if (track->vgt_strmout_en || track->vgt_strmout_buffer_en) {
286                 dev_warn(p->dev, "this kernel doesn't support SMX output buffer\n");
287                 return -EINVAL;
288         }
289         /* check that we have a cb for each enabled target, we don't check
290          * shader_mask because it seems mesa isn't always setting it :(
291          */
292         tmp = track->cb_target_mask;
293         for (i = 0; i < 8; i++) {
294                 if ((tmp >> (i * 4)) & 0xF) {
295                         /* at least one component is enabled */
296                         if (track->cb_color_bo[i] == NULL) {
297                                 dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
298                                         __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
299                                 return -EINVAL;
300                         }
301                         /* perform rewrite of CB_COLOR[0-7]_SIZE */
302                         r = r600_cs_track_validate_cb(p, i);
303                         if (r)
304                                 return r;
305                 }
306         }
307         /* Check depth buffer */
308         if (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
309                 G_028800_Z_ENABLE(track->db_depth_control)) {
310                 u32 nviews, bpe, ntiles, pitch, pitch_align, height, size;
311                 if (track->db_bo == NULL) {
312                         dev_warn(p->dev, "z/stencil with no depth buffer\n");
313                         return -EINVAL;
314                 }
315                 if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) {
316                         dev_warn(p->dev, "this kernel doesn't support z/stencil htile\n");
317                         return -EINVAL;
318                 }
319                 switch (G_028010_FORMAT(track->db_depth_info)) {
320                 case V_028010_DEPTH_16:
321                         bpe = 2;
322                         break;
323                 case V_028010_DEPTH_X8_24:
324                 case V_028010_DEPTH_8_24:
325                 case V_028010_DEPTH_X8_24_FLOAT:
326                 case V_028010_DEPTH_8_24_FLOAT:
327                 case V_028010_DEPTH_32_FLOAT:
328                         bpe = 4;
329                         break;
330                 case V_028010_DEPTH_X24_8_32_FLOAT:
331                         bpe = 8;
332                         break;
333                 default:
334                         dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info));
335                         return -EINVAL;
336                 }
337                 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
338                         if (!track->db_depth_size_idx) {
339                                 dev_warn(p->dev, "z/stencil buffer size not set\n");
340                                 return -EINVAL;
341                         }
342                         tmp = radeon_bo_size(track->db_bo) - track->db_offset;
343                         tmp = (tmp / bpe) >> 6;
344                         if (!tmp) {
345                                 dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n",
346                                                 track->db_depth_size, bpe, track->db_offset,
347                                                 radeon_bo_size(track->db_bo));
348                                 return -EINVAL;
349                         }
350                         ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
351                 } else {
352                         size = radeon_bo_size(track->db_bo);
353                         pitch = G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1;
354                         height = size / (pitch * 8 * bpe);
355                         height &= ~0x7;
356                         if (!height)
357                                 height = 8;
358
359                         switch (G_028010_ARRAY_MODE(track->db_depth_info)) {
360                         case V_028010_ARRAY_1D_TILED_THIN1:
361                                 pitch_align = (max((u32)8, (u32)(track->group_size / (8 * bpe))) / 8);
362                                 if (!IS_ALIGNED(pitch, pitch_align)) {
363                                         dev_warn(p->dev, "%s:%d db pitch (%d) invalid\n",
364                                                  __func__, __LINE__, pitch);
365                                         return -EINVAL;
366                                 }
367                                 if (!IS_ALIGNED(height, 8)) {
368                                         dev_warn(p->dev, "%s:%d db height (%d) invalid\n",
369                                                  __func__, __LINE__, height);
370                                         return -EINVAL;
371                                 }
372                                 break;
373                         case V_028010_ARRAY_2D_TILED_THIN1:
374                                 pitch_align = max((u32)track->nbanks,
375                                                   (u32)(((track->group_size / 8) / bpe) * track->nbanks)) / 8;
376                                 if (!IS_ALIGNED(pitch, pitch_align)) {
377                                         dev_warn(p->dev, "%s:%d db pitch (%d) invalid\n",
378                                                  __func__, __LINE__, pitch);
379                                         return -EINVAL;
380                                 }
381                                 if ((height / 8) & (track->nbanks - 1)) {
382                                         dev_warn(p->dev, "%s:%d db height (%d) invalid\n",
383                                                  __func__, __LINE__, height);
384                                         return -EINVAL;
385                                 }
386                                 break;
387                         default:
388                                 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
389                                          G_028010_ARRAY_MODE(track->db_depth_info),
390                                          track->db_depth_info);
391                                 return -EINVAL;
392                         }
393                         if (!IS_ALIGNED(track->db_offset, track->group_size)) {
394                                 dev_warn(p->dev, "%s offset[%d] %d not aligned\n", __func__, i, track->db_offset);
395                                 return -EINVAL;
396                         }
397                         ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
398                         nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
399                         tmp = ntiles * bpe * 64 * nviews;
400                         if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
401                                 dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %d -> %d have %ld)\n",
402                                                 track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
403                                                 radeon_bo_size(track->db_bo));
404                                 return -EINVAL;
405                         }
406                 }
407         }
408         return 0;
409 }
410
411 /**
412  * r600_cs_packet_parse() - parse cp packet and point ib index to next packet
413  * @parser:     parser structure holding parsing context.
414  * @pkt:        where to store packet informations
415  *
416  * Assume that chunk_ib_index is properly set. Will return -EINVAL
417  * if packet is bigger than remaining ib size. or if packets is unknown.
418  **/
419 int r600_cs_packet_parse(struct radeon_cs_parser *p,
420                         struct radeon_cs_packet *pkt,
421                         unsigned idx)
422 {
423         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
424         uint32_t header;
425
426         if (idx >= ib_chunk->length_dw) {
427                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
428                           idx, ib_chunk->length_dw);
429                 return -EINVAL;
430         }
431         header = radeon_get_ib_value(p, idx);
432         pkt->idx = idx;
433         pkt->type = CP_PACKET_GET_TYPE(header);
434         pkt->count = CP_PACKET_GET_COUNT(header);
435         pkt->one_reg_wr = 0;
436         switch (pkt->type) {
437         case PACKET_TYPE0:
438                 pkt->reg = CP_PACKET0_GET_REG(header);
439                 break;
440         case PACKET_TYPE3:
441                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
442                 break;
443         case PACKET_TYPE2:
444                 pkt->count = -1;
445                 break;
446         default:
447                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
448                 return -EINVAL;
449         }
450         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
451                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
452                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
453                 return -EINVAL;
454         }
455         return 0;
456 }
457
458 /**
459  * r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3
460  * @parser:             parser structure holding parsing context.
461  * @data:               pointer to relocation data
462  * @offset_start:       starting offset
463  * @offset_mask:        offset mask (to align start offset on)
464  * @reloc:              reloc informations
465  *
466  * Check next packet is relocation packet3, do bo validation and compute
467  * GPU offset using the provided start.
468  **/
469 static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
470                                         struct radeon_cs_reloc **cs_reloc)
471 {
472         struct radeon_cs_chunk *relocs_chunk;
473         struct radeon_cs_packet p3reloc;
474         unsigned idx;
475         int r;
476
477         if (p->chunk_relocs_idx == -1) {
478                 DRM_ERROR("No relocation chunk !\n");
479                 return -EINVAL;
480         }
481         *cs_reloc = NULL;
482         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
483         r = r600_cs_packet_parse(p, &p3reloc, p->idx);
484         if (r) {
485                 return r;
486         }
487         p->idx += p3reloc.count + 2;
488         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
489                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
490                           p3reloc.idx);
491                 return -EINVAL;
492         }
493         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
494         if (idx >= relocs_chunk->length_dw) {
495                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
496                           idx, relocs_chunk->length_dw);
497                 return -EINVAL;
498         }
499         /* FIXME: we assume reloc size is 4 dwords */
500         *cs_reloc = p->relocs_ptr[(idx / 4)];
501         return 0;
502 }
503
504 /**
505  * r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3
506  * @parser:             parser structure holding parsing context.
507  * @data:               pointer to relocation data
508  * @offset_start:       starting offset
509  * @offset_mask:        offset mask (to align start offset on)
510  * @reloc:              reloc informations
511  *
512  * Check next packet is relocation packet3, do bo validation and compute
513  * GPU offset using the provided start.
514  **/
515 static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
516                                         struct radeon_cs_reloc **cs_reloc)
517 {
518         struct radeon_cs_chunk *relocs_chunk;
519         struct radeon_cs_packet p3reloc;
520         unsigned idx;
521         int r;
522
523         if (p->chunk_relocs_idx == -1) {
524                 DRM_ERROR("No relocation chunk !\n");
525                 return -EINVAL;
526         }
527         *cs_reloc = NULL;
528         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
529         r = r600_cs_packet_parse(p, &p3reloc, p->idx);
530         if (r) {
531                 return r;
532         }
533         p->idx += p3reloc.count + 2;
534         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
535                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
536                           p3reloc.idx);
537                 return -EINVAL;
538         }
539         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
540         if (idx >= relocs_chunk->length_dw) {
541                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
542                           idx, relocs_chunk->length_dw);
543                 return -EINVAL;
544         }
545         *cs_reloc = p->relocs;
546         (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32;
547         (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
548         return 0;
549 }
550
551 /**
552  * r600_cs_packet_next_is_pkt3_nop() - test if next packet is packet3 nop for reloc
553  * @parser:             parser structure holding parsing context.
554  *
555  * Check next packet is relocation packet3, do bo validation and compute
556  * GPU offset using the provided start.
557  **/
558 static inline int r600_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
559 {
560         struct radeon_cs_packet p3reloc;
561         int r;
562
563         r = r600_cs_packet_parse(p, &p3reloc, p->idx);
564         if (r) {
565                 return 0;
566         }
567         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
568                 return 0;
569         }
570         return 1;
571 }
572
573 /**
574  * r600_cs_packet_next_vline() - parse userspace VLINE packet
575  * @parser:             parser structure holding parsing context.
576  *
577  * Userspace sends a special sequence for VLINE waits.
578  * PACKET0 - VLINE_START_END + value
579  * PACKET3 - WAIT_REG_MEM poll vline status reg
580  * RELOC (P3) - crtc_id in reloc.
581  *
582  * This function parses this and relocates the VLINE START END
583  * and WAIT_REG_MEM packets to the correct crtc.
584  * It also detects a switched off crtc and nulls out the
585  * wait in that case.
586  */
587 static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
588 {
589         struct drm_mode_object *obj;
590         struct drm_crtc *crtc;
591         struct radeon_crtc *radeon_crtc;
592         struct radeon_cs_packet p3reloc, wait_reg_mem;
593         int crtc_id;
594         int r;
595         uint32_t header, h_idx, reg, wait_reg_mem_info;
596         volatile uint32_t *ib;
597
598         ib = p->ib->ptr;
599
600         /* parse the WAIT_REG_MEM */
601         r = r600_cs_packet_parse(p, &wait_reg_mem, p->idx);
602         if (r)
603                 return r;
604
605         /* check its a WAIT_REG_MEM */
606         if (wait_reg_mem.type != PACKET_TYPE3 ||
607             wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
608                 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
609                 r = -EINVAL;
610                 return r;
611         }
612
613         wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
614         /* bit 4 is reg (0) or mem (1) */
615         if (wait_reg_mem_info & 0x10) {
616                 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n");
617                 r = -EINVAL;
618                 return r;
619         }
620         /* waiting for value to be equal */
621         if ((wait_reg_mem_info & 0x7) != 0x3) {
622                 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
623                 r = -EINVAL;
624                 return r;
625         }
626         if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != AVIVO_D1MODE_VLINE_STATUS) {
627                 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
628                 r = -EINVAL;
629                 return r;
630         }
631
632         if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != AVIVO_D1MODE_VLINE_STAT) {
633                 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
634                 r = -EINVAL;
635                 return r;
636         }
637
638         /* jump over the NOP */
639         r = r600_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);
640         if (r)
641                 return r;
642
643         h_idx = p->idx - 2;
644         p->idx += wait_reg_mem.count + 2;
645         p->idx += p3reloc.count + 2;
646
647         header = radeon_get_ib_value(p, h_idx);
648         crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
649         reg = CP_PACKET0_GET_REG(header);
650
651         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
652         if (!obj) {
653                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
654                 r = -EINVAL;
655                 goto out;
656         }
657         crtc = obj_to_crtc(obj);
658         radeon_crtc = to_radeon_crtc(crtc);
659         crtc_id = radeon_crtc->crtc_id;
660
661         if (!crtc->enabled) {
662                 /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
663                 ib[h_idx + 2] = PACKET2(0);
664                 ib[h_idx + 3] = PACKET2(0);
665                 ib[h_idx + 4] = PACKET2(0);
666                 ib[h_idx + 5] = PACKET2(0);
667                 ib[h_idx + 6] = PACKET2(0);
668                 ib[h_idx + 7] = PACKET2(0);
669                 ib[h_idx + 8] = PACKET2(0);
670         } else if (crtc_id == 1) {
671                 switch (reg) {
672                 case AVIVO_D1MODE_VLINE_START_END:
673                         header &= ~R600_CP_PACKET0_REG_MASK;
674                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
675                         break;
676                 default:
677                         DRM_ERROR("unknown crtc reloc\n");
678                         r = -EINVAL;
679                         goto out;
680                 }
681                 ib[h_idx] = header;
682                 ib[h_idx + 4] = AVIVO_D2MODE_VLINE_STATUS >> 2;
683         }
684 out:
685         return r;
686 }
687
688 static int r600_packet0_check(struct radeon_cs_parser *p,
689                                 struct radeon_cs_packet *pkt,
690                                 unsigned idx, unsigned reg)
691 {
692         int r;
693
694         switch (reg) {
695         case AVIVO_D1MODE_VLINE_START_END:
696                 r = r600_cs_packet_parse_vline(p);
697                 if (r) {
698                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
699                                         idx, reg);
700                         return r;
701                 }
702                 break;
703         default:
704                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
705                        reg, idx);
706                 return -EINVAL;
707         }
708         return 0;
709 }
710
711 static int r600_cs_parse_packet0(struct radeon_cs_parser *p,
712                                 struct radeon_cs_packet *pkt)
713 {
714         unsigned reg, i;
715         unsigned idx;
716         int r;
717
718         idx = pkt->idx + 1;
719         reg = pkt->reg;
720         for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
721                 r = r600_packet0_check(p, pkt, idx, reg);
722                 if (r) {
723                         return r;
724                 }
725         }
726         return 0;
727 }
728
729 /**
730  * r600_cs_check_reg() - check if register is authorized or not
731  * @parser: parser structure holding parsing context
732  * @reg: register we are testing
733  * @idx: index into the cs buffer
734  *
735  * This function will test against r600_reg_safe_bm and return 0
736  * if register is safe. If register is not flag as safe this function
737  * will test it against a list of register needind special handling.
738  */
739 static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
740 {
741         struct r600_cs_track *track = (struct r600_cs_track *)p->track;
742         struct radeon_cs_reloc *reloc;
743         u32 last_reg = ARRAY_SIZE(r600_reg_safe_bm);
744         u32 m, i, tmp, *ib;
745         int r;
746
747         i = (reg >> 7);
748         if (i > last_reg) {
749                 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
750                 return -EINVAL;
751         }
752         m = 1 << ((reg >> 2) & 31);
753         if (!(r600_reg_safe_bm[i] & m))
754                 return 0;
755         ib = p->ib->ptr;
756         switch (reg) {
757         /* force following reg to 0 in an attemp to disable out buffer
758          * which will need us to better understand how it works to perform
759          * security check on it (Jerome)
760          */
761         case R_0288A8_SQ_ESGS_RING_ITEMSIZE:
762         case R_008C44_SQ_ESGS_RING_SIZE:
763         case R_0288B0_SQ_ESTMP_RING_ITEMSIZE:
764         case R_008C54_SQ_ESTMP_RING_SIZE:
765         case R_0288C0_SQ_FBUF_RING_ITEMSIZE:
766         case R_008C74_SQ_FBUF_RING_SIZE:
767         case R_0288B4_SQ_GSTMP_RING_ITEMSIZE:
768         case R_008C5C_SQ_GSTMP_RING_SIZE:
769         case R_0288AC_SQ_GSVS_RING_ITEMSIZE:
770         case R_008C4C_SQ_GSVS_RING_SIZE:
771         case R_0288BC_SQ_PSTMP_RING_ITEMSIZE:
772         case R_008C6C_SQ_PSTMP_RING_SIZE:
773         case R_0288C4_SQ_REDUC_RING_ITEMSIZE:
774         case R_008C7C_SQ_REDUC_RING_SIZE:
775         case R_0288B8_SQ_VSTMP_RING_ITEMSIZE:
776         case R_008C64_SQ_VSTMP_RING_SIZE:
777         case R_0288C8_SQ_GS_VERT_ITEMSIZE:
778                 /* get value to populate the IB don't remove */
779                 tmp =radeon_get_ib_value(p, idx);
780                 ib[idx] = 0;
781                 break;
782         case SQ_CONFIG:
783                 track->sq_config = radeon_get_ib_value(p, idx);
784                 break;
785         case R_028800_DB_DEPTH_CONTROL:
786                 track->db_depth_control = radeon_get_ib_value(p, idx);
787                 break;
788         case R_028010_DB_DEPTH_INFO:
789                 if (r600_cs_packet_next_is_pkt3_nop(p)) {
790                         r = r600_cs_packet_next_reloc(p, &reloc);
791                         if (r) {
792                                 dev_warn(p->dev, "bad SET_CONTEXT_REG "
793                                          "0x%04X\n", reg);
794                                 return -EINVAL;
795                         }
796                         track->db_depth_info = radeon_get_ib_value(p, idx);
797                         ib[idx] &= C_028010_ARRAY_MODE;
798                         track->db_depth_info &= C_028010_ARRAY_MODE;
799                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
800                                 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
801                                 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
802                         } else {
803                                 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
804                                 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
805                         }
806                 } else
807                         track->db_depth_info = radeon_get_ib_value(p, idx);
808                 break;
809         case R_028004_DB_DEPTH_VIEW:
810                 track->db_depth_view = radeon_get_ib_value(p, idx);
811                 break;
812         case R_028000_DB_DEPTH_SIZE:
813                 track->db_depth_size = radeon_get_ib_value(p, idx);
814                 track->db_depth_size_idx = idx;
815                 break;
816         case R_028AB0_VGT_STRMOUT_EN:
817                 track->vgt_strmout_en = radeon_get_ib_value(p, idx);
818                 break;
819         case R_028B20_VGT_STRMOUT_BUFFER_EN:
820                 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx);
821                 break;
822         case R_028238_CB_TARGET_MASK:
823                 track->cb_target_mask = radeon_get_ib_value(p, idx);
824                 break;
825         case R_02823C_CB_SHADER_MASK:
826                 track->cb_shader_mask = radeon_get_ib_value(p, idx);
827                 break;
828         case R_028C04_PA_SC_AA_CONFIG:
829                 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));
830                 track->nsamples = 1 << tmp;
831                 break;
832         case R_0280A0_CB_COLOR0_INFO:
833         case R_0280A4_CB_COLOR1_INFO:
834         case R_0280A8_CB_COLOR2_INFO:
835         case R_0280AC_CB_COLOR3_INFO:
836         case R_0280B0_CB_COLOR4_INFO:
837         case R_0280B4_CB_COLOR5_INFO:
838         case R_0280B8_CB_COLOR6_INFO:
839         case R_0280BC_CB_COLOR7_INFO:
840                 if (r600_cs_packet_next_is_pkt3_nop(p)) {
841                         r = r600_cs_packet_next_reloc(p, &reloc);
842                         if (r) {
843                                 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
844                                 return -EINVAL;
845                         }
846                         tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
847                         track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
848                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
849                                 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
850                                 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
851                         } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
852                                 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
853                                 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
854                         }
855                 } else {
856                         tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
857                         track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
858                 }
859                 break;
860         case R_028060_CB_COLOR0_SIZE:
861         case R_028064_CB_COLOR1_SIZE:
862         case R_028068_CB_COLOR2_SIZE:
863         case R_02806C_CB_COLOR3_SIZE:
864         case R_028070_CB_COLOR4_SIZE:
865         case R_028074_CB_COLOR5_SIZE:
866         case R_028078_CB_COLOR6_SIZE:
867         case R_02807C_CB_COLOR7_SIZE:
868                 tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4;
869                 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx);
870                 track->cb_color_size_idx[tmp] = idx;
871                 break;
872                 /* This register were added late, there is userspace
873                  * which does provide relocation for those but set
874                  * 0 offset. In order to avoid breaking old userspace
875                  * we detect this and set address to point to last
876                  * CB_COLOR0_BASE, note that if userspace doesn't set
877                  * CB_COLOR0_BASE before this register we will report
878                  * error. Old userspace always set CB_COLOR0_BASE
879                  * before any of this.
880                  */
881         case R_0280E0_CB_COLOR0_FRAG:
882         case R_0280E4_CB_COLOR1_FRAG:
883         case R_0280E8_CB_COLOR2_FRAG:
884         case R_0280EC_CB_COLOR3_FRAG:
885         case R_0280F0_CB_COLOR4_FRAG:
886         case R_0280F4_CB_COLOR5_FRAG:
887         case R_0280F8_CB_COLOR6_FRAG:
888         case R_0280FC_CB_COLOR7_FRAG:
889                 tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4;
890                 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
891                         if (!track->cb_color_base_last[tmp]) {
892                                 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
893                                 return -EINVAL;
894                         }
895                         ib[idx] = track->cb_color_base_last[tmp];
896                         track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];
897                 } else {
898                         r = r600_cs_packet_next_reloc(p, &reloc);
899                         if (r) {
900                                 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
901                                 return -EINVAL;
902                         }
903                         ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
904                         track->cb_color_frag_bo[tmp] = reloc->robj;
905                 }
906                 break;
907         case R_0280C0_CB_COLOR0_TILE:
908         case R_0280C4_CB_COLOR1_TILE:
909         case R_0280C8_CB_COLOR2_TILE:
910         case R_0280CC_CB_COLOR3_TILE:
911         case R_0280D0_CB_COLOR4_TILE:
912         case R_0280D4_CB_COLOR5_TILE:
913         case R_0280D8_CB_COLOR6_TILE:
914         case R_0280DC_CB_COLOR7_TILE:
915                 tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4;
916                 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
917                         if (!track->cb_color_base_last[tmp]) {
918                                 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
919                                 return -EINVAL;
920                         }
921                         ib[idx] = track->cb_color_base_last[tmp];
922                         track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];
923                 } else {
924                         r = r600_cs_packet_next_reloc(p, &reloc);
925                         if (r) {
926                                 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
927                                 return -EINVAL;
928                         }
929                         ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
930                         track->cb_color_tile_bo[tmp] = reloc->robj;
931                 }
932                 break;
933         case CB_COLOR0_BASE:
934         case CB_COLOR1_BASE:
935         case CB_COLOR2_BASE:
936         case CB_COLOR3_BASE:
937         case CB_COLOR4_BASE:
938         case CB_COLOR5_BASE:
939         case CB_COLOR6_BASE:
940         case CB_COLOR7_BASE:
941                 r = r600_cs_packet_next_reloc(p, &reloc);
942                 if (r) {
943                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
944                                         "0x%04X\n", reg);
945                         return -EINVAL;
946                 }
947                 tmp = (reg - CB_COLOR0_BASE) / 4;
948                 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
949                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
950                 track->cb_color_base_last[tmp] = ib[idx];
951                 track->cb_color_bo[tmp] = reloc->robj;
952                 break;
953         case DB_DEPTH_BASE:
954                 r = r600_cs_packet_next_reloc(p, &reloc);
955                 if (r) {
956                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
957                                         "0x%04X\n", reg);
958                         return -EINVAL;
959                 }
960                 track->db_offset = radeon_get_ib_value(p, idx) << 8;
961                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
962                 track->db_bo = reloc->robj;
963                 break;
964         case DB_HTILE_DATA_BASE:
965         case SQ_PGM_START_FS:
966         case SQ_PGM_START_ES:
967         case SQ_PGM_START_VS:
968         case SQ_PGM_START_GS:
969         case SQ_PGM_START_PS:
970         case SQ_ALU_CONST_CACHE_GS_0:
971         case SQ_ALU_CONST_CACHE_GS_1:
972         case SQ_ALU_CONST_CACHE_GS_2:
973         case SQ_ALU_CONST_CACHE_GS_3:
974         case SQ_ALU_CONST_CACHE_GS_4:
975         case SQ_ALU_CONST_CACHE_GS_5:
976         case SQ_ALU_CONST_CACHE_GS_6:
977         case SQ_ALU_CONST_CACHE_GS_7:
978         case SQ_ALU_CONST_CACHE_GS_8:
979         case SQ_ALU_CONST_CACHE_GS_9:
980         case SQ_ALU_CONST_CACHE_GS_10:
981         case SQ_ALU_CONST_CACHE_GS_11:
982         case SQ_ALU_CONST_CACHE_GS_12:
983         case SQ_ALU_CONST_CACHE_GS_13:
984         case SQ_ALU_CONST_CACHE_GS_14:
985         case SQ_ALU_CONST_CACHE_GS_15:
986         case SQ_ALU_CONST_CACHE_PS_0:
987         case SQ_ALU_CONST_CACHE_PS_1:
988         case SQ_ALU_CONST_CACHE_PS_2:
989         case SQ_ALU_CONST_CACHE_PS_3:
990         case SQ_ALU_CONST_CACHE_PS_4:
991         case SQ_ALU_CONST_CACHE_PS_5:
992         case SQ_ALU_CONST_CACHE_PS_6:
993         case SQ_ALU_CONST_CACHE_PS_7:
994         case SQ_ALU_CONST_CACHE_PS_8:
995         case SQ_ALU_CONST_CACHE_PS_9:
996         case SQ_ALU_CONST_CACHE_PS_10:
997         case SQ_ALU_CONST_CACHE_PS_11:
998         case SQ_ALU_CONST_CACHE_PS_12:
999         case SQ_ALU_CONST_CACHE_PS_13:
1000         case SQ_ALU_CONST_CACHE_PS_14:
1001         case SQ_ALU_CONST_CACHE_PS_15:
1002         case SQ_ALU_CONST_CACHE_VS_0:
1003         case SQ_ALU_CONST_CACHE_VS_1:
1004         case SQ_ALU_CONST_CACHE_VS_2:
1005         case SQ_ALU_CONST_CACHE_VS_3:
1006         case SQ_ALU_CONST_CACHE_VS_4:
1007         case SQ_ALU_CONST_CACHE_VS_5:
1008         case SQ_ALU_CONST_CACHE_VS_6:
1009         case SQ_ALU_CONST_CACHE_VS_7:
1010         case SQ_ALU_CONST_CACHE_VS_8:
1011         case SQ_ALU_CONST_CACHE_VS_9:
1012         case SQ_ALU_CONST_CACHE_VS_10:
1013         case SQ_ALU_CONST_CACHE_VS_11:
1014         case SQ_ALU_CONST_CACHE_VS_12:
1015         case SQ_ALU_CONST_CACHE_VS_13:
1016         case SQ_ALU_CONST_CACHE_VS_14:
1017         case SQ_ALU_CONST_CACHE_VS_15:
1018                 r = r600_cs_packet_next_reloc(p, &reloc);
1019                 if (r) {
1020                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1021                                         "0x%04X\n", reg);
1022                         return -EINVAL;
1023                 }
1024                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1025                 break;
1026         default:
1027                 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1028                 return -EINVAL;
1029         }
1030         return 0;
1031 }
1032
1033 static inline unsigned minify(unsigned size, unsigned levels)
1034 {
1035         size = size >> levels;
1036         if (size < 1)
1037                 size = 1;
1038         return size;
1039 }
1040
1041 static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned nlevels,
1042                               unsigned w0, unsigned h0, unsigned d0, unsigned bpe,
1043                               unsigned pitch_align,
1044                               unsigned *l0_size, unsigned *mipmap_size)
1045 {
1046         unsigned offset, i, level, face;
1047         unsigned width, height, depth, rowstride, size;
1048
1049         w0 = minify(w0, 0);
1050         h0 = minify(h0, 0);
1051         d0 = minify(d0, 0);
1052         for(i = 0, offset = 0, level = blevel; i < nlevels; i++, level++) {
1053                 width = minify(w0, i);
1054                 height = minify(h0, i);
1055                 depth = minify(d0, i);
1056                 for(face = 0; face < nfaces; face++) {
1057                         rowstride = ALIGN((width * bpe), pitch_align);
1058                         size = height * rowstride * depth;
1059                         offset += size;
1060                         offset = (offset + 0x1f) & ~0x1f;
1061                 }
1062         }
1063         *l0_size = ALIGN((w0 * bpe), pitch_align) * h0 * d0;
1064         *mipmap_size = offset;
1065         if (!nlevels)
1066                 *mipmap_size = *l0_size;
1067         if (!blevel)
1068                 *mipmap_size -= *l0_size;
1069 }
1070
1071 /**
1072  * r600_check_texture_resource() - check if register is authorized or not
1073  * @p: parser structure holding parsing context
1074  * @idx: index into the cs buffer
1075  * @texture: texture's bo structure
1076  * @mipmap: mipmap's bo structure
1077  *
1078  * This function will check that the resource has valid field and that
1079  * the texture and mipmap bo object are big enough to cover this resource.
1080  */
1081 static inline int r600_check_texture_resource(struct radeon_cs_parser *p,  u32 idx,
1082                                               struct radeon_bo *texture,
1083                                               struct radeon_bo *mipmap,
1084                                               u32 tiling_flags)
1085 {
1086         struct r600_cs_track *track = p->track;
1087         u32 nfaces, nlevels, blevel, w0, h0, d0, bpe = 0;
1088         u32 word0, word1, l0_size, mipmap_size, pitch, pitch_align;
1089
1090         /* on legacy kernel we don't perform advanced check */
1091         if (p->rdev == NULL)
1092                 return 0;
1093
1094         word0 = radeon_get_ib_value(p, idx + 0);
1095         if (tiling_flags & RADEON_TILING_MACRO)
1096                 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1097         else if (tiling_flags & RADEON_TILING_MICRO)
1098                 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1099         word1 = radeon_get_ib_value(p, idx + 1);
1100         w0 = G_038000_TEX_WIDTH(word0) + 1;
1101         h0 = G_038004_TEX_HEIGHT(word1) + 1;
1102         d0 = G_038004_TEX_DEPTH(word1);
1103         nfaces = 1;
1104         switch (G_038000_DIM(word0)) {
1105         case V_038000_SQ_TEX_DIM_1D:
1106         case V_038000_SQ_TEX_DIM_2D:
1107         case V_038000_SQ_TEX_DIM_3D:
1108                 break;
1109         case V_038000_SQ_TEX_DIM_CUBEMAP:
1110                 nfaces = 6;
1111                 break;
1112         case V_038000_SQ_TEX_DIM_1D_ARRAY:
1113         case V_038000_SQ_TEX_DIM_2D_ARRAY:
1114         case V_038000_SQ_TEX_DIM_2D_MSAA:
1115         case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA:
1116         default:
1117                 dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0));
1118                 return -EINVAL;
1119         }
1120         if (r600_bpe_from_format(&bpe,  G_038004_DATA_FORMAT(word1))) {
1121                 dev_warn(p->dev, "%s:%d texture invalid format %d\n",
1122                          __func__, __LINE__, G_038004_DATA_FORMAT(word1));
1123                 return -EINVAL;
1124         }
1125
1126         pitch = G_038000_PITCH(word0) + 1;
1127         switch (G_038000_TILE_MODE(word0)) {
1128         case V_038000_ARRAY_LINEAR_GENERAL:
1129                 pitch_align = 1;
1130                 /* XXX check height align */
1131                 break;
1132         case V_038000_ARRAY_LINEAR_ALIGNED:
1133                 pitch_align = max((u32)64, (u32)(track->group_size / bpe)) / 8;
1134                 if (!IS_ALIGNED(pitch, pitch_align)) {
1135                         dev_warn(p->dev, "%s:%d tex pitch (%d) invalid\n",
1136                                  __func__, __LINE__, pitch);
1137                         return -EINVAL;
1138                 }
1139                 /* XXX check height align */
1140                 break;
1141         case V_038000_ARRAY_1D_TILED_THIN1:
1142                 pitch_align = max((u32)8, (u32)(track->group_size / (8 * bpe))) / 8;
1143                 if (!IS_ALIGNED(pitch, pitch_align)) {
1144                         dev_warn(p->dev, "%s:%d tex pitch (%d) invalid\n",
1145                                  __func__, __LINE__, pitch);
1146                         return -EINVAL;
1147                 }
1148                 /* XXX check height align */
1149                 break;
1150         case V_038000_ARRAY_2D_TILED_THIN1:
1151                 pitch_align = max((u32)track->nbanks,
1152                                   (u32)(((track->group_size / 8) / bpe) * track->nbanks)) / 8;
1153                 if (!IS_ALIGNED(pitch, pitch_align)) {
1154                         dev_warn(p->dev, "%s:%d tex pitch (%d) invalid\n",
1155                                 __func__, __LINE__, pitch);
1156                         return -EINVAL;
1157                 }
1158                 /* XXX check height align */
1159                 break;
1160         default:
1161                 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
1162                          G_038000_TILE_MODE(word0), word0);
1163                 return -EINVAL;
1164         }
1165         /* XXX check offset align */
1166
1167         word0 = radeon_get_ib_value(p, idx + 4);
1168         word1 = radeon_get_ib_value(p, idx + 5);
1169         blevel = G_038010_BASE_LEVEL(word0);
1170         nlevels = G_038014_LAST_LEVEL(word1);
1171         r600_texture_size(nfaces, blevel, nlevels, w0, h0, d0, bpe,
1172                           (pitch_align * bpe),
1173                           &l0_size, &mipmap_size);
1174         /* using get ib will give us the offset into the texture bo */
1175         word0 = radeon_get_ib_value(p, idx + 2) << 8;
1176         if ((l0_size + word0) > radeon_bo_size(texture)) {
1177                 dev_warn(p->dev, "texture bo too small (%d %d %d %d -> %d have %ld)\n",
1178                         w0, h0, bpe, word0, l0_size, radeon_bo_size(texture));
1179                 return -EINVAL;
1180         }
1181         /* using get ib will give us the offset into the mipmap bo */
1182         word0 = radeon_get_ib_value(p, idx + 3) << 8;
1183         if ((mipmap_size + word0) > radeon_bo_size(mipmap)) {
1184                 /*dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n",
1185                   w0, h0, bpe, blevel, nlevels, word0, mipmap_size, radeon_bo_size(texture));*/
1186         }
1187         return 0;
1188 }
1189
1190 static int r600_packet3_check(struct radeon_cs_parser *p,
1191                                 struct radeon_cs_packet *pkt)
1192 {
1193         struct radeon_cs_reloc *reloc;
1194         struct r600_cs_track *track;
1195         volatile u32 *ib;
1196         unsigned idx;
1197         unsigned i;
1198         unsigned start_reg, end_reg, reg;
1199         int r;
1200         u32 idx_value;
1201
1202         track = (struct r600_cs_track *)p->track;
1203         ib = p->ib->ptr;
1204         idx = pkt->idx + 1;
1205         idx_value = radeon_get_ib_value(p, idx);
1206
1207         switch (pkt->opcode) {
1208         case PACKET3_START_3D_CMDBUF:
1209                 if (p->family >= CHIP_RV770 || pkt->count) {
1210                         DRM_ERROR("bad START_3D\n");
1211                         return -EINVAL;
1212                 }
1213                 break;
1214         case PACKET3_CONTEXT_CONTROL:
1215                 if (pkt->count != 1) {
1216                         DRM_ERROR("bad CONTEXT_CONTROL\n");
1217                         return -EINVAL;
1218                 }
1219                 break;
1220         case PACKET3_INDEX_TYPE:
1221         case PACKET3_NUM_INSTANCES:
1222                 if (pkt->count) {
1223                         DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n");
1224                         return -EINVAL;
1225                 }
1226                 break;
1227         case PACKET3_DRAW_INDEX:
1228                 if (pkt->count != 3) {
1229                         DRM_ERROR("bad DRAW_INDEX\n");
1230                         return -EINVAL;
1231                 }
1232                 r = r600_cs_packet_next_reloc(p, &reloc);
1233                 if (r) {
1234                         DRM_ERROR("bad DRAW_INDEX\n");
1235                         return -EINVAL;
1236                 }
1237                 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1238                 ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1239                 r = r600_cs_track_check(p);
1240                 if (r) {
1241                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1242                         return r;
1243                 }
1244                 break;
1245         case PACKET3_DRAW_INDEX_AUTO:
1246                 if (pkt->count != 1) {
1247                         DRM_ERROR("bad DRAW_INDEX_AUTO\n");
1248                         return -EINVAL;
1249                 }
1250                 r = r600_cs_track_check(p);
1251                 if (r) {
1252                         dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
1253                         return r;
1254                 }
1255                 break;
1256         case PACKET3_DRAW_INDEX_IMMD_BE:
1257         case PACKET3_DRAW_INDEX_IMMD:
1258                 if (pkt->count < 2) {
1259                         DRM_ERROR("bad DRAW_INDEX_IMMD\n");
1260                         return -EINVAL;
1261                 }
1262                 r = r600_cs_track_check(p);
1263                 if (r) {
1264                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1265                         return r;
1266                 }
1267                 break;
1268         case PACKET3_WAIT_REG_MEM:
1269                 if (pkt->count != 5) {
1270                         DRM_ERROR("bad WAIT_REG_MEM\n");
1271                         return -EINVAL;
1272                 }
1273                 /* bit 4 is reg (0) or mem (1) */
1274                 if (idx_value & 0x10) {
1275                         r = r600_cs_packet_next_reloc(p, &reloc);
1276                         if (r) {
1277                                 DRM_ERROR("bad WAIT_REG_MEM\n");
1278                                 return -EINVAL;
1279                         }
1280                         ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1281                         ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1282                 }
1283                 break;
1284         case PACKET3_SURFACE_SYNC:
1285                 if (pkt->count != 3) {
1286                         DRM_ERROR("bad SURFACE_SYNC\n");
1287                         return -EINVAL;
1288                 }
1289                 /* 0xffffffff/0x0 is flush all cache flag */
1290                 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
1291                     radeon_get_ib_value(p, idx + 2) != 0) {
1292                         r = r600_cs_packet_next_reloc(p, &reloc);
1293                         if (r) {
1294                                 DRM_ERROR("bad SURFACE_SYNC\n");
1295                                 return -EINVAL;
1296                         }
1297                         ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1298                 }
1299                 break;
1300         case PACKET3_EVENT_WRITE:
1301                 if (pkt->count != 2 && pkt->count != 0) {
1302                         DRM_ERROR("bad EVENT_WRITE\n");
1303                         return -EINVAL;
1304                 }
1305                 if (pkt->count) {
1306                         r = r600_cs_packet_next_reloc(p, &reloc);
1307                         if (r) {
1308                                 DRM_ERROR("bad EVENT_WRITE\n");
1309                                 return -EINVAL;
1310                         }
1311                         ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1312                         ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1313                 }
1314                 break;
1315         case PACKET3_EVENT_WRITE_EOP:
1316                 if (pkt->count != 4) {
1317                         DRM_ERROR("bad EVENT_WRITE_EOP\n");
1318                         return -EINVAL;
1319                 }
1320                 r = r600_cs_packet_next_reloc(p, &reloc);
1321                 if (r) {
1322                         DRM_ERROR("bad EVENT_WRITE\n");
1323                         return -EINVAL;
1324                 }
1325                 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1326                 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1327                 break;
1328         case PACKET3_SET_CONFIG_REG:
1329                 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
1330                 end_reg = 4 * pkt->count + start_reg - 4;
1331                 if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) ||
1332                     (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
1333                     (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
1334                         DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
1335                         return -EINVAL;
1336                 }
1337                 for (i = 0; i < pkt->count; i++) {
1338                         reg = start_reg + (4 * i);
1339                         r = r600_cs_check_reg(p, reg, idx+1+i);
1340                         if (r)
1341                                 return r;
1342                 }
1343                 break;
1344         case PACKET3_SET_CONTEXT_REG:
1345                 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET;
1346                 end_reg = 4 * pkt->count + start_reg - 4;
1347                 if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) ||
1348                     (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
1349                     (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
1350                         DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
1351                         return -EINVAL;
1352                 }
1353                 for (i = 0; i < pkt->count; i++) {
1354                         reg = start_reg + (4 * i);
1355                         r = r600_cs_check_reg(p, reg, idx+1+i);
1356                         if (r)
1357                                 return r;
1358                 }
1359                 break;
1360         case PACKET3_SET_RESOURCE:
1361                 if (pkt->count % 7) {
1362                         DRM_ERROR("bad SET_RESOURCE\n");
1363                         return -EINVAL;
1364                 }
1365                 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET;
1366                 end_reg = 4 * pkt->count + start_reg - 4;
1367                 if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) ||
1368                     (start_reg >= PACKET3_SET_RESOURCE_END) ||
1369                     (end_reg >= PACKET3_SET_RESOURCE_END)) {
1370                         DRM_ERROR("bad SET_RESOURCE\n");
1371                         return -EINVAL;
1372                 }
1373                 for (i = 0; i < (pkt->count / 7); i++) {
1374                         struct radeon_bo *texture, *mipmap;
1375                         u32 size, offset, base_offset, mip_offset;
1376
1377                         switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) {
1378                         case SQ_TEX_VTX_VALID_TEXTURE:
1379                                 /* tex base */
1380                                 r = r600_cs_packet_next_reloc(p, &reloc);
1381                                 if (r) {
1382                                         DRM_ERROR("bad SET_RESOURCE\n");
1383                                         return -EINVAL;
1384                                 }
1385                                 base_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1386                                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1387                                         ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1388                                 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1389                                         ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1390                                 texture = reloc->robj;
1391                                 /* tex mip base */
1392                                 r = r600_cs_packet_next_reloc(p, &reloc);
1393                                 if (r) {
1394                                         DRM_ERROR("bad SET_RESOURCE\n");
1395                                         return -EINVAL;
1396                                 }
1397                                 mip_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1398                                 mipmap = reloc->robj;
1399                                 r = r600_check_texture_resource(p,  idx+(i*7)+1,
1400                                                                 texture, mipmap, reloc->lobj.tiling_flags);
1401                                 if (r)
1402                                         return r;
1403                                 ib[idx+1+(i*7)+2] += base_offset;
1404                                 ib[idx+1+(i*7)+3] += mip_offset;
1405                                 break;
1406                         case SQ_TEX_VTX_VALID_BUFFER:
1407                                 /* vtx base */
1408                                 r = r600_cs_packet_next_reloc(p, &reloc);
1409                                 if (r) {
1410                                         DRM_ERROR("bad SET_RESOURCE\n");
1411                                         return -EINVAL;
1412                                 }
1413                                 offset = radeon_get_ib_value(p, idx+1+(i*7)+0);
1414                                 size = radeon_get_ib_value(p, idx+1+(i*7)+1) + 1;
1415                                 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
1416                                         /* force size to size of the buffer */
1417                                         dev_warn(p->dev, "vbo resource seems too big (%d) for the bo (%ld)\n",
1418                                                  size + offset, radeon_bo_size(reloc->robj));
1419                                         ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj);
1420                                 }
1421                                 ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff);
1422                                 ib[idx+1+(i*7)+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1423                                 break;
1424                         case SQ_TEX_VTX_INVALID_TEXTURE:
1425                         case SQ_TEX_VTX_INVALID_BUFFER:
1426                         default:
1427                                 DRM_ERROR("bad SET_RESOURCE\n");
1428                                 return -EINVAL;
1429                         }
1430                 }
1431                 break;
1432         case PACKET3_SET_ALU_CONST:
1433                 if (track->sq_config & DX9_CONSTS) {
1434                         start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;
1435                         end_reg = 4 * pkt->count + start_reg - 4;
1436                         if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||
1437                             (start_reg >= PACKET3_SET_ALU_CONST_END) ||
1438                             (end_reg >= PACKET3_SET_ALU_CONST_END)) {
1439                                 DRM_ERROR("bad SET_ALU_CONST\n");
1440                                 return -EINVAL;
1441                         }
1442                 }
1443                 break;
1444         case PACKET3_SET_BOOL_CONST:
1445                 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET;
1446                 end_reg = 4 * pkt->count + start_reg - 4;
1447                 if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) ||
1448                     (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
1449                     (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
1450                         DRM_ERROR("bad SET_BOOL_CONST\n");
1451                         return -EINVAL;
1452                 }
1453                 break;
1454         case PACKET3_SET_LOOP_CONST:
1455                 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET;
1456                 end_reg = 4 * pkt->count + start_reg - 4;
1457                 if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) ||
1458                     (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
1459                     (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
1460                         DRM_ERROR("bad SET_LOOP_CONST\n");
1461                         return -EINVAL;
1462                 }
1463                 break;
1464         case PACKET3_SET_CTL_CONST:
1465                 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET;
1466                 end_reg = 4 * pkt->count + start_reg - 4;
1467                 if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) ||
1468                     (start_reg >= PACKET3_SET_CTL_CONST_END) ||
1469                     (end_reg >= PACKET3_SET_CTL_CONST_END)) {
1470                         DRM_ERROR("bad SET_CTL_CONST\n");
1471                         return -EINVAL;
1472                 }
1473                 break;
1474         case PACKET3_SET_SAMPLER:
1475                 if (pkt->count % 3) {
1476                         DRM_ERROR("bad SET_SAMPLER\n");
1477                         return -EINVAL;
1478                 }
1479                 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET;
1480                 end_reg = 4 * pkt->count + start_reg - 4;
1481                 if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) ||
1482                     (start_reg >= PACKET3_SET_SAMPLER_END) ||
1483                     (end_reg >= PACKET3_SET_SAMPLER_END)) {
1484                         DRM_ERROR("bad SET_SAMPLER\n");
1485                         return -EINVAL;
1486                 }
1487                 break;
1488         case PACKET3_SURFACE_BASE_UPDATE:
1489                 if (p->family >= CHIP_RV770 || p->family == CHIP_R600) {
1490                         DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
1491                         return -EINVAL;
1492                 }
1493                 if (pkt->count) {
1494                         DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
1495                         return -EINVAL;
1496                 }
1497                 break;
1498         case PACKET3_NOP:
1499                 break;
1500         default:
1501                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1502                 return -EINVAL;
1503         }
1504         return 0;
1505 }
1506
1507 int r600_cs_parse(struct radeon_cs_parser *p)
1508 {
1509         struct radeon_cs_packet pkt;
1510         struct r600_cs_track *track;
1511         int r;
1512
1513         if (p->track == NULL) {
1514                 /* initialize tracker, we are in kms */
1515                 track = kzalloc(sizeof(*track), GFP_KERNEL);
1516                 if (track == NULL)
1517                         return -ENOMEM;
1518                 r600_cs_track_init(track);
1519                 if (p->rdev->family < CHIP_RV770) {
1520                         track->npipes = p->rdev->config.r600.tiling_npipes;
1521                         track->nbanks = p->rdev->config.r600.tiling_nbanks;
1522                         track->group_size = p->rdev->config.r600.tiling_group_size;
1523                 } else if (p->rdev->family <= CHIP_RV740) {
1524                         track->npipes = p->rdev->config.rv770.tiling_npipes;
1525                         track->nbanks = p->rdev->config.rv770.tiling_nbanks;
1526                         track->group_size = p->rdev->config.rv770.tiling_group_size;
1527                 }
1528                 p->track = track;
1529         }
1530         do {
1531                 r = r600_cs_packet_parse(p, &pkt, p->idx);
1532                 if (r) {
1533                         kfree(p->track);
1534                         p->track = NULL;
1535                         return r;
1536                 }
1537                 p->idx += pkt.count + 2;
1538                 switch (pkt.type) {
1539                 case PACKET_TYPE0:
1540                         r = r600_cs_parse_packet0(p, &pkt);
1541                         break;
1542                 case PACKET_TYPE2:
1543                         break;
1544                 case PACKET_TYPE3:
1545                         r = r600_packet3_check(p, &pkt);
1546                         break;
1547                 default:
1548                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1549                         kfree(p->track);
1550                         p->track = NULL;
1551                         return -EINVAL;
1552                 }
1553                 if (r) {
1554                         kfree(p->track);
1555                         p->track = NULL;
1556                         return r;
1557                 }
1558         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1559 #if 0
1560         for (r = 0; r < p->ib->length_dw; r++) {
1561                 printk(KERN_INFO "%05d  0x%08X\n", r, p->ib->ptr[r]);
1562                 mdelay(1);
1563         }
1564 #endif
1565         kfree(p->track);
1566         p->track = NULL;
1567         return 0;
1568 }
1569
1570 static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p)
1571 {
1572         if (p->chunk_relocs_idx == -1) {
1573                 return 0;
1574         }
1575         p->relocs = kzalloc(sizeof(struct radeon_cs_reloc), GFP_KERNEL);
1576         if (p->relocs == NULL) {
1577                 return -ENOMEM;
1578         }
1579         return 0;
1580 }
1581
1582 /**
1583  * cs_parser_fini() - clean parser states
1584  * @parser:     parser structure holding parsing context.
1585  * @error:      error number
1586  *
1587  * If error is set than unvalidate buffer, otherwise just free memory
1588  * used by parsing context.
1589  **/
1590 static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error)
1591 {
1592         unsigned i;
1593
1594         kfree(parser->relocs);
1595         for (i = 0; i < parser->nchunks; i++) {
1596                 kfree(parser->chunks[i].kdata);
1597                 kfree(parser->chunks[i].kpage[0]);
1598                 kfree(parser->chunks[i].kpage[1]);
1599         }
1600         kfree(parser->chunks);
1601         kfree(parser->chunks_array);
1602 }
1603
1604 int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
1605                         unsigned family, u32 *ib, int *l)
1606 {
1607         struct radeon_cs_parser parser;
1608         struct radeon_cs_chunk *ib_chunk;
1609         struct radeon_ib fake_ib;
1610         struct r600_cs_track *track;
1611         int r;
1612
1613         /* initialize tracker */
1614         track = kzalloc(sizeof(*track), GFP_KERNEL);
1615         if (track == NULL)
1616                 return -ENOMEM;
1617         r600_cs_track_init(track);
1618         r600_cs_legacy_get_tiling_conf(dev, &track->npipes, &track->nbanks, &track->group_size);
1619         /* initialize parser */
1620         memset(&parser, 0, sizeof(struct radeon_cs_parser));
1621         parser.filp = filp;
1622         parser.dev = &dev->pdev->dev;
1623         parser.rdev = NULL;
1624         parser.family = family;
1625         parser.ib = &fake_ib;
1626         parser.track = track;
1627         fake_ib.ptr = ib;
1628         r = radeon_cs_parser_init(&parser, data);
1629         if (r) {
1630                 DRM_ERROR("Failed to initialize parser !\n");
1631                 r600_cs_parser_fini(&parser, r);
1632                 return r;
1633         }
1634         r = r600_cs_parser_relocs_legacy(&parser);
1635         if (r) {
1636                 DRM_ERROR("Failed to parse relocation !\n");
1637                 r600_cs_parser_fini(&parser, r);
1638                 return r;
1639         }
1640         /* Copy the packet into the IB, the parser will read from the
1641          * input memory (cached) and write to the IB (which can be
1642          * uncached). */
1643         ib_chunk = &parser.chunks[parser.chunk_ib_idx];
1644         parser.ib->length_dw = ib_chunk->length_dw;
1645         *l = parser.ib->length_dw;
1646         r = r600_cs_parse(&parser);
1647         if (r) {
1648                 DRM_ERROR("Invalid command stream !\n");
1649                 r600_cs_parser_fini(&parser, r);
1650                 return r;
1651         }
1652         r = radeon_cs_finish_pages(&parser);
1653         if (r) {
1654                 DRM_ERROR("Invalid command stream !\n");
1655                 r600_cs_parser_fini(&parser, r);
1656                 return r;
1657         }
1658         r600_cs_parser_fini(&parser, r);
1659         return r;
1660 }
1661
1662 void r600_cs_legacy_init(void)
1663 {
1664         r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_nomm;
1665 }