drm/radeon: allow CMASK and FMASK in the CS checker on r600-r700
[linux-3.10.git] / drivers / gpu / drm / radeon / r600_cs.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <linux/kernel.h>
29 #include "drmP.h"
30 #include "radeon.h"
31 #include "r600d.h"
32 #include "r600_reg_safe.h"
33
34 static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
35                                         struct radeon_cs_reloc **cs_reloc);
36 static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
37                                         struct radeon_cs_reloc **cs_reloc);
38 typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**);
39 static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm;
40 extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size);
41
42
43 struct r600_cs_track {
44         /* configuration we miror so that we use same code btw kms/ums */
45         u32                     group_size;
46         u32                     nbanks;
47         u32                     npipes;
48         /* value we track */
49         u32                     sq_config;
50         u32                     log_nsamples;
51         u32                     nsamples;
52         u32                     cb_color_base_last[8];
53         struct radeon_bo        *cb_color_bo[8];
54         u64                     cb_color_bo_mc[8];
55         u64                     cb_color_bo_offset[8];
56         struct radeon_bo        *cb_color_frag_bo[8];
57         u64                     cb_color_frag_offset[8];
58         struct radeon_bo        *cb_color_tile_bo[8];
59         u64                     cb_color_tile_offset[8];
60         u32                     cb_color_mask[8];
61         u32                     cb_color_info[8];
62         u32                     cb_color_view[8];
63         u32                     cb_color_size_idx[8]; /* unused */
64         u32                     cb_target_mask;
65         u32                     cb_shader_mask;  /* unused */
66         u32                     cb_color_size[8];
67         u32                     vgt_strmout_en;
68         u32                     vgt_strmout_buffer_en;
69         struct radeon_bo        *vgt_strmout_bo[4];
70         u64                     vgt_strmout_bo_mc[4]; /* unused */
71         u32                     vgt_strmout_bo_offset[4];
72         u32                     vgt_strmout_size[4];
73         u32                     db_depth_control;
74         u32                     db_depth_info;
75         u32                     db_depth_size_idx;
76         u32                     db_depth_view;
77         u32                     db_depth_size;
78         u32                     db_offset;
79         struct radeon_bo        *db_bo;
80         u64                     db_bo_mc;
81         bool                    sx_misc_kill_all_prims;
82         bool                    cb_dirty;
83         bool                    db_dirty;
84         bool                    streamout_dirty;
85         struct radeon_bo        *htile_bo;
86         u64                     htile_offset;
87         u32                     htile_surface;
88 };
89
90 #define FMT_8_BIT(fmt, vc)   [fmt] = { 1, 1, 1, vc, CHIP_R600 }
91 #define FMT_16_BIT(fmt, vc)  [fmt] = { 1, 1, 2, vc, CHIP_R600 }
92 #define FMT_24_BIT(fmt)      [fmt] = { 1, 1, 4,  0, CHIP_R600 }
93 #define FMT_32_BIT(fmt, vc)  [fmt] = { 1, 1, 4, vc, CHIP_R600 }
94 #define FMT_48_BIT(fmt)      [fmt] = { 1, 1, 8,  0, CHIP_R600 }
95 #define FMT_64_BIT(fmt, vc)  [fmt] = { 1, 1, 8, vc, CHIP_R600 }
96 #define FMT_96_BIT(fmt)      [fmt] = { 1, 1, 12, 0, CHIP_R600 }
97 #define FMT_128_BIT(fmt, vc) [fmt] = { 1, 1, 16,vc, CHIP_R600 }
98
99 struct gpu_formats {
100         unsigned blockwidth;
101         unsigned blockheight;
102         unsigned blocksize;
103         unsigned valid_color;
104         enum radeon_family min_family;
105 };
106
107 static const struct gpu_formats color_formats_table[] = {
108         /* 8 bit */
109         FMT_8_BIT(V_038004_COLOR_8, 1),
110         FMT_8_BIT(V_038004_COLOR_4_4, 1),
111         FMT_8_BIT(V_038004_COLOR_3_3_2, 1),
112         FMT_8_BIT(V_038004_FMT_1, 0),
113
114         /* 16-bit */
115         FMT_16_BIT(V_038004_COLOR_16, 1),
116         FMT_16_BIT(V_038004_COLOR_16_FLOAT, 1),
117         FMT_16_BIT(V_038004_COLOR_8_8, 1),
118         FMT_16_BIT(V_038004_COLOR_5_6_5, 1),
119         FMT_16_BIT(V_038004_COLOR_6_5_5, 1),
120         FMT_16_BIT(V_038004_COLOR_1_5_5_5, 1),
121         FMT_16_BIT(V_038004_COLOR_4_4_4_4, 1),
122         FMT_16_BIT(V_038004_COLOR_5_5_5_1, 1),
123
124         /* 24-bit */
125         FMT_24_BIT(V_038004_FMT_8_8_8),
126
127         /* 32-bit */
128         FMT_32_BIT(V_038004_COLOR_32, 1),
129         FMT_32_BIT(V_038004_COLOR_32_FLOAT, 1),
130         FMT_32_BIT(V_038004_COLOR_16_16, 1),
131         FMT_32_BIT(V_038004_COLOR_16_16_FLOAT, 1),
132         FMT_32_BIT(V_038004_COLOR_8_24, 1),
133         FMT_32_BIT(V_038004_COLOR_8_24_FLOAT, 1),
134         FMT_32_BIT(V_038004_COLOR_24_8, 1),
135         FMT_32_BIT(V_038004_COLOR_24_8_FLOAT, 1),
136         FMT_32_BIT(V_038004_COLOR_10_11_11, 1),
137         FMT_32_BIT(V_038004_COLOR_10_11_11_FLOAT, 1),
138         FMT_32_BIT(V_038004_COLOR_11_11_10, 1),
139         FMT_32_BIT(V_038004_COLOR_11_11_10_FLOAT, 1),
140         FMT_32_BIT(V_038004_COLOR_2_10_10_10, 1),
141         FMT_32_BIT(V_038004_COLOR_8_8_8_8, 1),
142         FMT_32_BIT(V_038004_COLOR_10_10_10_2, 1),
143         FMT_32_BIT(V_038004_FMT_5_9_9_9_SHAREDEXP, 0),
144         FMT_32_BIT(V_038004_FMT_32_AS_8, 0),
145         FMT_32_BIT(V_038004_FMT_32_AS_8_8, 0),
146
147         /* 48-bit */
148         FMT_48_BIT(V_038004_FMT_16_16_16),
149         FMT_48_BIT(V_038004_FMT_16_16_16_FLOAT),
150
151         /* 64-bit */
152         FMT_64_BIT(V_038004_COLOR_X24_8_32_FLOAT, 1),
153         FMT_64_BIT(V_038004_COLOR_32_32, 1),
154         FMT_64_BIT(V_038004_COLOR_32_32_FLOAT, 1),
155         FMT_64_BIT(V_038004_COLOR_16_16_16_16, 1),
156         FMT_64_BIT(V_038004_COLOR_16_16_16_16_FLOAT, 1),
157
158         FMT_96_BIT(V_038004_FMT_32_32_32),
159         FMT_96_BIT(V_038004_FMT_32_32_32_FLOAT),
160
161         /* 128-bit */
162         FMT_128_BIT(V_038004_COLOR_32_32_32_32, 1),
163         FMT_128_BIT(V_038004_COLOR_32_32_32_32_FLOAT, 1),
164
165         [V_038004_FMT_GB_GR] = { 2, 1, 4, 0 },
166         [V_038004_FMT_BG_RG] = { 2, 1, 4, 0 },
167
168         /* block compressed formats */
169         [V_038004_FMT_BC1] = { 4, 4, 8, 0 },
170         [V_038004_FMT_BC2] = { 4, 4, 16, 0 },
171         [V_038004_FMT_BC3] = { 4, 4, 16, 0 },
172         [V_038004_FMT_BC4] = { 4, 4, 8, 0 },
173         [V_038004_FMT_BC5] = { 4, 4, 16, 0},
174         [V_038004_FMT_BC6] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */
175         [V_038004_FMT_BC7] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */
176
177         /* The other Evergreen formats */
178         [V_038004_FMT_32_AS_32_32_32_32] = { 1, 1, 4, 0, CHIP_CEDAR},
179 };
180
181 bool r600_fmt_is_valid_color(u32 format)
182 {
183         if (format >= ARRAY_SIZE(color_formats_table))
184                 return false;
185
186         if (color_formats_table[format].valid_color)
187                 return true;
188
189         return false;
190 }
191
192 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family)
193 {
194         if (format >= ARRAY_SIZE(color_formats_table))
195                 return false;
196
197         if (family < color_formats_table[format].min_family)
198                 return false;
199
200         if (color_formats_table[format].blockwidth > 0)
201                 return true;
202
203         return false;
204 }
205
206 int r600_fmt_get_blocksize(u32 format)
207 {
208         if (format >= ARRAY_SIZE(color_formats_table))
209                 return 0;
210
211         return color_formats_table[format].blocksize;
212 }
213
214 int r600_fmt_get_nblocksx(u32 format, u32 w)
215 {
216         unsigned bw;
217
218         if (format >= ARRAY_SIZE(color_formats_table))
219                 return 0;
220
221         bw = color_formats_table[format].blockwidth;
222         if (bw == 0)
223                 return 0;
224
225         return (w + bw - 1) / bw;
226 }
227
228 int r600_fmt_get_nblocksy(u32 format, u32 h)
229 {
230         unsigned bh;
231
232         if (format >= ARRAY_SIZE(color_formats_table))
233                 return 0;
234
235         bh = color_formats_table[format].blockheight;
236         if (bh == 0)
237                 return 0;
238
239         return (h + bh - 1) / bh;
240 }
241
242 struct array_mode_checker {
243         int array_mode;
244         u32 group_size;
245         u32 nbanks;
246         u32 npipes;
247         u32 nsamples;
248         u32 blocksize;
249 };
250
251 /* returns alignment in pixels for pitch/height/depth and bytes for base */
252 static int r600_get_array_mode_alignment(struct array_mode_checker *values,
253                                                 u32 *pitch_align,
254                                                 u32 *height_align,
255                                                 u32 *depth_align,
256                                                 u64 *base_align)
257 {
258         u32 tile_width = 8;
259         u32 tile_height = 8;
260         u32 macro_tile_width = values->nbanks;
261         u32 macro_tile_height = values->npipes;
262         u32 tile_bytes = tile_width * tile_height * values->blocksize * values->nsamples;
263         u32 macro_tile_bytes = macro_tile_width * macro_tile_height * tile_bytes;
264
265         switch (values->array_mode) {
266         case ARRAY_LINEAR_GENERAL:
267                 /* technically tile_width/_height for pitch/height */
268                 *pitch_align = 1; /* tile_width */
269                 *height_align = 1; /* tile_height */
270                 *depth_align = 1;
271                 *base_align = 1;
272                 break;
273         case ARRAY_LINEAR_ALIGNED:
274                 *pitch_align = max((u32)64, (u32)(values->group_size / values->blocksize));
275                 *height_align = 1;
276                 *depth_align = 1;
277                 *base_align = values->group_size;
278                 break;
279         case ARRAY_1D_TILED_THIN1:
280                 *pitch_align = max((u32)tile_width,
281                                    (u32)(values->group_size /
282                                          (tile_height * values->blocksize * values->nsamples)));
283                 *height_align = tile_height;
284                 *depth_align = 1;
285                 *base_align = values->group_size;
286                 break;
287         case ARRAY_2D_TILED_THIN1:
288                 *pitch_align = max((u32)macro_tile_width * tile_width,
289                                 (u32)((values->group_size * values->nbanks) /
290                                 (values->blocksize * values->nsamples * tile_width)));
291                 *height_align = macro_tile_height * tile_height;
292                 *depth_align = 1;
293                 *base_align = max(macro_tile_bytes,
294                                   (*pitch_align) * values->blocksize * (*height_align) * values->nsamples);
295                 break;
296         default:
297                 return -EINVAL;
298         }
299
300         return 0;
301 }
302
303 static void r600_cs_track_init(struct r600_cs_track *track)
304 {
305         int i;
306
307         /* assume DX9 mode */
308         track->sq_config = DX9_CONSTS;
309         for (i = 0; i < 8; i++) {
310                 track->cb_color_base_last[i] = 0;
311                 track->cb_color_size[i] = 0;
312                 track->cb_color_size_idx[i] = 0;
313                 track->cb_color_info[i] = 0;
314                 track->cb_color_view[i] = 0xFFFFFFFF;
315                 track->cb_color_bo[i] = NULL;
316                 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
317                 track->cb_color_bo_mc[i] = 0xFFFFFFFF;
318         }
319         track->cb_target_mask = 0xFFFFFFFF;
320         track->cb_shader_mask = 0xFFFFFFFF;
321         track->cb_dirty = true;
322         track->db_bo = NULL;
323         track->db_bo_mc = 0xFFFFFFFF;
324         /* assume the biggest format and that htile is enabled */
325         track->db_depth_info = 7 | (1 << 25);
326         track->db_depth_view = 0xFFFFC000;
327         track->db_depth_size = 0xFFFFFFFF;
328         track->db_depth_size_idx = 0;
329         track->db_depth_control = 0xFFFFFFFF;
330         track->db_dirty = true;
331         track->htile_bo = NULL;
332         track->htile_offset = 0xFFFFFFFF;
333         track->htile_surface = 0;
334
335         for (i = 0; i < 4; i++) {
336                 track->vgt_strmout_size[i] = 0;
337                 track->vgt_strmout_bo[i] = NULL;
338                 track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF;
339                 track->vgt_strmout_bo_mc[i] = 0xFFFFFFFF;
340         }
341         track->streamout_dirty = true;
342         track->sx_misc_kill_all_prims = false;
343 }
344
345 static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
346 {
347         struct r600_cs_track *track = p->track;
348         u32 slice_tile_max, size, tmp;
349         u32 height, height_align, pitch, pitch_align, depth_align;
350         u64 base_offset, base_align;
351         struct array_mode_checker array_check;
352         volatile u32 *ib = p->ib.ptr;
353         unsigned array_mode;
354         u32 format;
355
356         size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i];
357         format = G_0280A0_FORMAT(track->cb_color_info[i]);
358         if (!r600_fmt_is_valid_color(format)) {
359                 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n",
360                          __func__, __LINE__, format,
361                         i, track->cb_color_info[i]);
362                 return -EINVAL;
363         }
364         /* pitch in pixels */
365         pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) * 8;
366         slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1;
367         slice_tile_max *= 64;
368         height = slice_tile_max / pitch;
369         if (height > 8192)
370                 height = 8192;
371         array_mode = G_0280A0_ARRAY_MODE(track->cb_color_info[i]);
372
373         base_offset = track->cb_color_bo_mc[i] + track->cb_color_bo_offset[i];
374         array_check.array_mode = array_mode;
375         array_check.group_size = track->group_size;
376         array_check.nbanks = track->nbanks;
377         array_check.npipes = track->npipes;
378         array_check.nsamples = track->nsamples;
379         array_check.blocksize = r600_fmt_get_blocksize(format);
380         if (r600_get_array_mode_alignment(&array_check,
381                                           &pitch_align, &height_align, &depth_align, &base_align)) {
382                 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
383                          G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
384                          track->cb_color_info[i]);
385                 return -EINVAL;
386         }
387         switch (array_mode) {
388         case V_0280A0_ARRAY_LINEAR_GENERAL:
389                 break;
390         case V_0280A0_ARRAY_LINEAR_ALIGNED:
391                 break;
392         case V_0280A0_ARRAY_1D_TILED_THIN1:
393                 /* avoid breaking userspace */
394                 if (height > 7)
395                         height &= ~0x7;
396                 break;
397         case V_0280A0_ARRAY_2D_TILED_THIN1:
398                 break;
399         default:
400                 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
401                         G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
402                         track->cb_color_info[i]);
403                 return -EINVAL;
404         }
405
406         if (!IS_ALIGNED(pitch, pitch_align)) {
407                 dev_warn(p->dev, "%s:%d cb pitch (%d, 0x%x, %d) invalid\n",
408                          __func__, __LINE__, pitch, pitch_align, array_mode);
409                 return -EINVAL;
410         }
411         if (!IS_ALIGNED(height, height_align)) {
412                 dev_warn(p->dev, "%s:%d cb height (%d, 0x%x, %d) invalid\n",
413                          __func__, __LINE__, height, height_align, array_mode);
414                 return -EINVAL;
415         }
416         if (!IS_ALIGNED(base_offset, base_align)) {
417                 dev_warn(p->dev, "%s offset[%d] 0x%llx 0x%llx, %d not aligned\n", __func__, i,
418                          base_offset, base_align, array_mode);
419                 return -EINVAL;
420         }
421
422         /* check offset */
423         tmp = r600_fmt_get_nblocksy(format, height) * r600_fmt_get_nblocksx(format, pitch) * r600_fmt_get_blocksize(format);
424         switch (array_mode) {
425         default:
426         case V_0280A0_ARRAY_LINEAR_GENERAL:
427         case V_0280A0_ARRAY_LINEAR_ALIGNED:
428                 tmp += track->cb_color_view[i] & 0xFF;
429                 break;
430         case V_0280A0_ARRAY_1D_TILED_THIN1:
431         case V_0280A0_ARRAY_2D_TILED_THIN1:
432                 tmp += G_028080_SLICE_MAX(track->cb_color_view[i]) * tmp;
433                 break;
434         }
435         if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
436                 if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) {
437                         /* the initial DDX does bad things with the CB size occasionally */
438                         /* it rounds up height too far for slice tile max but the BO is smaller */
439                         /* r600c,g also seem to flush at bad times in some apps resulting in
440                          * bogus values here. So for linear just allow anything to avoid breaking
441                          * broken userspace.
442                          */
443                 } else {
444                         dev_warn(p->dev, "%s offset[%d] %d %llu %d %lu too big (%d %d) (%d %d %d)\n",
445                                  __func__, i, array_mode,
446                                  track->cb_color_bo_offset[i], tmp,
447                                  radeon_bo_size(track->cb_color_bo[i]),
448                                  pitch, height, r600_fmt_get_nblocksx(format, pitch),
449                                  r600_fmt_get_nblocksy(format, height),
450                                  r600_fmt_get_blocksize(format));
451                         return -EINVAL;
452                 }
453         }
454         /* limit max tile */
455         tmp = (height * pitch) >> 6;
456         if (tmp < slice_tile_max)
457                 slice_tile_max = tmp;
458         tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) |
459                 S_028060_SLICE_TILE_MAX(slice_tile_max - 1);
460         ib[track->cb_color_size_idx[i]] = tmp;
461
462         /* FMASK/CMASK */
463         switch (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
464         case V_0280A0_TILE_DISABLE:
465                 break;
466         case V_0280A0_FRAG_ENABLE:
467                 if (track->nsamples > 1) {
468                         uint32_t tile_max = G_028100_FMASK_TILE_MAX(track->cb_color_mask[i]);
469                         /* the tile size is 8x8, but the size is in units of bits.
470                          * for bytes, do just * 8. */
471                         uint32_t bytes = track->nsamples * track->log_nsamples * 8 * (tile_max + 1);
472
473                         if (bytes + track->cb_color_frag_offset[i] >
474                             radeon_bo_size(track->cb_color_frag_bo[i])) {
475                                 dev_warn(p->dev, "%s FMASK_TILE_MAX too large "
476                                          "(tile_max=%u, bytes=%u, offset=%llu, bo_size=%lu)\n",
477                                          __func__, tile_max, bytes,
478                                          track->cb_color_frag_offset[i],
479                                          radeon_bo_size(track->cb_color_frag_bo[i]));
480                                 return -EINVAL;
481                         }
482                 }
483                 /* fall through */
484         case V_0280A0_CLEAR_ENABLE:
485         {
486                 uint32_t block_max = G_028100_CMASK_BLOCK_MAX(track->cb_color_mask[i]);
487                 /* One block = 128x128 pixels, one 8x8 tile has 4 bits..
488                  * (128*128) / (8*8) / 2 = 128 bytes per block. */
489                 uint32_t bytes = (block_max + 1) * 128;
490
491                 if (bytes + track->cb_color_tile_offset[i] >
492                     radeon_bo_size(track->cb_color_tile_bo[i])) {
493                         dev_warn(p->dev, "%s CMASK_BLOCK_MAX too large "
494                                  "(block_max=%u, bytes=%u, offset=%llu, bo_size=%lu)\n",
495                                  __func__, block_max, bytes,
496                                  track->cb_color_tile_offset[i],
497                                  radeon_bo_size(track->cb_color_tile_bo[i]));
498                         return -EINVAL;
499                 }
500                 break;
501         }
502         default:
503                 dev_warn(p->dev, "%s invalid tile mode\n", __func__);
504                 return -EINVAL;
505         }
506         return 0;
507 }
508
509 static int r600_cs_track_validate_db(struct radeon_cs_parser *p)
510 {
511         struct r600_cs_track *track = p->track;
512         u32 nviews, bpe, ntiles, size, slice_tile_max, tmp;
513         u32 height_align, pitch_align, depth_align;
514         u32 pitch = 8192;
515         u32 height = 8192;
516         u64 base_offset, base_align;
517         struct array_mode_checker array_check;
518         int array_mode;
519         volatile u32 *ib = p->ib.ptr;
520
521
522         if (track->db_bo == NULL) {
523                 dev_warn(p->dev, "z/stencil with no depth buffer\n");
524                 return -EINVAL;
525         }
526         switch (G_028010_FORMAT(track->db_depth_info)) {
527         case V_028010_DEPTH_16:
528                 bpe = 2;
529                 break;
530         case V_028010_DEPTH_X8_24:
531         case V_028010_DEPTH_8_24:
532         case V_028010_DEPTH_X8_24_FLOAT:
533         case V_028010_DEPTH_8_24_FLOAT:
534         case V_028010_DEPTH_32_FLOAT:
535                 bpe = 4;
536                 break;
537         case V_028010_DEPTH_X24_8_32_FLOAT:
538                 bpe = 8;
539                 break;
540         default:
541                 dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info));
542                 return -EINVAL;
543         }
544         if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
545                 if (!track->db_depth_size_idx) {
546                         dev_warn(p->dev, "z/stencil buffer size not set\n");
547                         return -EINVAL;
548                 }
549                 tmp = radeon_bo_size(track->db_bo) - track->db_offset;
550                 tmp = (tmp / bpe) >> 6;
551                 if (!tmp) {
552                         dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n",
553                                         track->db_depth_size, bpe, track->db_offset,
554                                         radeon_bo_size(track->db_bo));
555                         return -EINVAL;
556                 }
557                 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
558         } else {
559                 size = radeon_bo_size(track->db_bo);
560                 /* pitch in pixels */
561                 pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8;
562                 slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
563                 slice_tile_max *= 64;
564                 height = slice_tile_max / pitch;
565                 if (height > 8192)
566                         height = 8192;
567                 base_offset = track->db_bo_mc + track->db_offset;
568                 array_mode = G_028010_ARRAY_MODE(track->db_depth_info);
569                 array_check.array_mode = array_mode;
570                 array_check.group_size = track->group_size;
571                 array_check.nbanks = track->nbanks;
572                 array_check.npipes = track->npipes;
573                 array_check.nsamples = track->nsamples;
574                 array_check.blocksize = bpe;
575                 if (r600_get_array_mode_alignment(&array_check,
576                                         &pitch_align, &height_align, &depth_align, &base_align)) {
577                         dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
578                                         G_028010_ARRAY_MODE(track->db_depth_info),
579                                         track->db_depth_info);
580                         return -EINVAL;
581                 }
582                 switch (array_mode) {
583                 case V_028010_ARRAY_1D_TILED_THIN1:
584                         /* don't break userspace */
585                         height &= ~0x7;
586                         break;
587                 case V_028010_ARRAY_2D_TILED_THIN1:
588                         break;
589                 default:
590                         dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
591                                         G_028010_ARRAY_MODE(track->db_depth_info),
592                                         track->db_depth_info);
593                         return -EINVAL;
594                 }
595
596                 if (!IS_ALIGNED(pitch, pitch_align)) {
597                         dev_warn(p->dev, "%s:%d db pitch (%d, 0x%x, %d) invalid\n",
598                                         __func__, __LINE__, pitch, pitch_align, array_mode);
599                         return -EINVAL;
600                 }
601                 if (!IS_ALIGNED(height, height_align)) {
602                         dev_warn(p->dev, "%s:%d db height (%d, 0x%x, %d) invalid\n",
603                                         __func__, __LINE__, height, height_align, array_mode);
604                         return -EINVAL;
605                 }
606                 if (!IS_ALIGNED(base_offset, base_align)) {
607                         dev_warn(p->dev, "%s offset 0x%llx, 0x%llx, %d not aligned\n", __func__,
608                                         base_offset, base_align, array_mode);
609                         return -EINVAL;
610                 }
611
612                 ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
613                 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
614                 tmp = ntiles * bpe * 64 * nviews;
615                 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
616                         dev_warn(p->dev, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n",
617                                         array_mode,
618                                         track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
619                                         radeon_bo_size(track->db_bo));
620                         return -EINVAL;
621                 }
622         }
623
624         /* hyperz */
625         if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) {
626                 unsigned long size;
627                 unsigned nbx, nby;
628
629                 if (track->htile_bo == NULL) {
630                         dev_warn(p->dev, "%s:%d htile enabled without htile surface 0x%08x\n",
631                                  __func__, __LINE__, track->db_depth_info);
632                         return -EINVAL;
633                 }
634                 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
635                         dev_warn(p->dev, "%s:%d htile can't be enabled with bogus db_depth_size 0x%08x\n",
636                                  __func__, __LINE__, track->db_depth_size);
637                         return -EINVAL;
638                 }
639
640                 nbx = pitch;
641                 nby = height;
642                 if (G_028D24_LINEAR(track->htile_surface)) {
643                         /* nbx must be 16 htiles aligned == 16 * 8 pixel aligned */
644                         nbx = round_up(nbx, 16 * 8);
645                         /* nby is npipes htiles aligned == npipes * 8 pixel aligned */
646                         nby = round_up(nby, track->npipes * 8);
647                 } else {
648                         /* htile widht & nby (8 or 4) make 2 bits number */
649                         tmp = track->htile_surface & 3;
650                         /* align is htile align * 8, htile align vary according to
651                          * number of pipe and tile width and nby
652                          */
653                         switch (track->npipes) {
654                         case 8:
655                                 switch (tmp) {
656                                 case 3: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
657                                         nbx = round_up(nbx, 64 * 8);
658                                         nby = round_up(nby, 64 * 8);
659                                         break;
660                                 case 2: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 8*/
661                                 case 1: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 4*/
662                                         nbx = round_up(nbx, 64 * 8);
663                                         nby = round_up(nby, 32 * 8);
664                                         break;
665                                 case 0: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 4*/
666                                         nbx = round_up(nbx, 32 * 8);
667                                         nby = round_up(nby, 32 * 8);
668                                         break;
669                                 default:
670                                         return -EINVAL;
671                                 }
672                                 break;
673                         case 4:
674                                 switch (tmp) {
675                                 case 3: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
676                                         nbx = round_up(nbx, 64 * 8);
677                                         nby = round_up(nby, 32 * 8);
678                                         break;
679                                 case 2: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 8*/
680                                 case 1: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 4*/
681                                         nbx = round_up(nbx, 32 * 8);
682                                         nby = round_up(nby, 32 * 8);
683                                         break;
684                                 case 0: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 4*/
685                                         nbx = round_up(nbx, 32 * 8);
686                                         nby = round_up(nby, 16 * 8);
687                                         break;
688                                 default:
689                                         return -EINVAL;
690                                 }
691                                 break;
692                         case 2:
693                                 switch (tmp) {
694                                 case 3: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
695                                         nbx = round_up(nbx, 32 * 8);
696                                         nby = round_up(nby, 32 * 8);
697                                         break;
698                                 case 2: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 8*/
699                                 case 1: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 4*/
700                                         nbx = round_up(nbx, 32 * 8);
701                                         nby = round_up(nby, 16 * 8);
702                                         break;
703                                 case 0: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 4*/
704                                         nbx = round_up(nbx, 16 * 8);
705                                         nby = round_up(nby, 16 * 8);
706                                         break;
707                                 default:
708                                         return -EINVAL;
709                                 }
710                                 break;
711                         case 1:
712                                 switch (tmp) {
713                                 case 3: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
714                                         nbx = round_up(nbx, 32 * 8);
715                                         nby = round_up(nby, 16 * 8);
716                                         break;
717                                 case 2: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 8*/
718                                 case 1: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 4*/
719                                         nbx = round_up(nbx, 16 * 8);
720                                         nby = round_up(nby, 16 * 8);
721                                         break;
722                                 case 0: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 4*/
723                                         nbx = round_up(nbx, 16 * 8);
724                                         nby = round_up(nby, 8 * 8);
725                                         break;
726                                 default:
727                                         return -EINVAL;
728                                 }
729                                 break;
730                         default:
731                                 dev_warn(p->dev, "%s:%d invalid num pipes %d\n",
732                                          __func__, __LINE__, track->npipes);
733                                 return -EINVAL;
734                         }
735                 }
736                 /* compute number of htile */
737                 nbx = G_028D24_HTILE_WIDTH(track->htile_surface) ? nbx / 8 : nbx / 4;
738                 nby = G_028D24_HTILE_HEIGHT(track->htile_surface) ? nby / 8 : nby / 4;
739                 size = nbx * nby * 4;
740                 size += track->htile_offset;
741
742                 if (size > radeon_bo_size(track->htile_bo)) {
743                         dev_warn(p->dev, "%s:%d htile surface too small %ld for %ld (%d %d)\n",
744                                  __func__, __LINE__, radeon_bo_size(track->htile_bo),
745                                  size, nbx, nby);
746                         return -EINVAL;
747                 }
748         }
749
750         track->db_dirty = false;
751         return 0;
752 }
753
754 static int r600_cs_track_check(struct radeon_cs_parser *p)
755 {
756         struct r600_cs_track *track = p->track;
757         u32 tmp;
758         int r, i;
759
760         /* on legacy kernel we don't perform advanced check */
761         if (p->rdev == NULL)
762                 return 0;
763
764         /* check streamout */
765         if (track->streamout_dirty && track->vgt_strmout_en) {
766                 for (i = 0; i < 4; i++) {
767                         if (track->vgt_strmout_buffer_en & (1 << i)) {
768                                 if (track->vgt_strmout_bo[i]) {
769                                         u64 offset = (u64)track->vgt_strmout_bo_offset[i] +
770                                                 (u64)track->vgt_strmout_size[i];
771                                         if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) {
772                                                 DRM_ERROR("streamout %d bo too small: 0x%llx, 0x%lx\n",
773                                                           i, offset,
774                                                           radeon_bo_size(track->vgt_strmout_bo[i]));
775                                                 return -EINVAL;
776                                         }
777                                 } else {
778                                         dev_warn(p->dev, "No buffer for streamout %d\n", i);
779                                         return -EINVAL;
780                                 }
781                         }
782                 }
783                 track->streamout_dirty = false;
784         }
785
786         if (track->sx_misc_kill_all_prims)
787                 return 0;
788
789         /* check that we have a cb for each enabled target, we don't check
790          * shader_mask because it seems mesa isn't always setting it :(
791          */
792         if (track->cb_dirty) {
793                 tmp = track->cb_target_mask;
794                 for (i = 0; i < 8; i++) {
795                         if ((tmp >> (i * 4)) & 0xF) {
796                                 /* at least one component is enabled */
797                                 if (track->cb_color_bo[i] == NULL) {
798                                         dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
799                                                 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
800                                         return -EINVAL;
801                                 }
802                                 /* perform rewrite of CB_COLOR[0-7]_SIZE */
803                                 r = r600_cs_track_validate_cb(p, i);
804                                 if (r)
805                                         return r;
806                         }
807                 }
808                 track->cb_dirty = false;
809         }
810
811         /* Check depth buffer */
812         if (track->db_dirty &&
813             G_028010_FORMAT(track->db_depth_info) != V_028010_DEPTH_INVALID &&
814             (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
815              G_028800_Z_ENABLE(track->db_depth_control))) {
816                 r = r600_cs_track_validate_db(p);
817                 if (r)
818                         return r;
819         }
820
821         return 0;
822 }
823
824 /**
825  * r600_cs_packet_parse() - parse cp packet and point ib index to next packet
826  * @parser:     parser structure holding parsing context.
827  * @pkt:        where to store packet informations
828  *
829  * Assume that chunk_ib_index is properly set. Will return -EINVAL
830  * if packet is bigger than remaining ib size. or if packets is unknown.
831  **/
832 int r600_cs_packet_parse(struct radeon_cs_parser *p,
833                         struct radeon_cs_packet *pkt,
834                         unsigned idx)
835 {
836         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
837         uint32_t header;
838
839         if (idx >= ib_chunk->length_dw) {
840                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
841                           idx, ib_chunk->length_dw);
842                 return -EINVAL;
843         }
844         header = radeon_get_ib_value(p, idx);
845         pkt->idx = idx;
846         pkt->type = CP_PACKET_GET_TYPE(header);
847         pkt->count = CP_PACKET_GET_COUNT(header);
848         pkt->one_reg_wr = 0;
849         switch (pkt->type) {
850         case PACKET_TYPE0:
851                 pkt->reg = CP_PACKET0_GET_REG(header);
852                 break;
853         case PACKET_TYPE3:
854                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
855                 break;
856         case PACKET_TYPE2:
857                 pkt->count = -1;
858                 break;
859         default:
860                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
861                 return -EINVAL;
862         }
863         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
864                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
865                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
866                 return -EINVAL;
867         }
868         return 0;
869 }
870
871 /**
872  * r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3
873  * @parser:             parser structure holding parsing context.
874  * @data:               pointer to relocation data
875  * @offset_start:       starting offset
876  * @offset_mask:        offset mask (to align start offset on)
877  * @reloc:              reloc informations
878  *
879  * Check next packet is relocation packet3, do bo validation and compute
880  * GPU offset using the provided start.
881  **/
882 static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
883                                         struct radeon_cs_reloc **cs_reloc)
884 {
885         struct radeon_cs_chunk *relocs_chunk;
886         struct radeon_cs_packet p3reloc;
887         unsigned idx;
888         int r;
889
890         if (p->chunk_relocs_idx == -1) {
891                 DRM_ERROR("No relocation chunk !\n");
892                 return -EINVAL;
893         }
894         *cs_reloc = NULL;
895         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
896         r = r600_cs_packet_parse(p, &p3reloc, p->idx);
897         if (r) {
898                 return r;
899         }
900         p->idx += p3reloc.count + 2;
901         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
902                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
903                           p3reloc.idx);
904                 return -EINVAL;
905         }
906         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
907         if (idx >= relocs_chunk->length_dw) {
908                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
909                           idx, relocs_chunk->length_dw);
910                 return -EINVAL;
911         }
912         /* FIXME: we assume reloc size is 4 dwords */
913         *cs_reloc = p->relocs_ptr[(idx / 4)];
914         return 0;
915 }
916
917 /**
918  * r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3
919  * @parser:             parser structure holding parsing context.
920  * @data:               pointer to relocation data
921  * @offset_start:       starting offset
922  * @offset_mask:        offset mask (to align start offset on)
923  * @reloc:              reloc informations
924  *
925  * Check next packet is relocation packet3, do bo validation and compute
926  * GPU offset using the provided start.
927  **/
928 static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
929                                         struct radeon_cs_reloc **cs_reloc)
930 {
931         struct radeon_cs_chunk *relocs_chunk;
932         struct radeon_cs_packet p3reloc;
933         unsigned idx;
934         int r;
935
936         if (p->chunk_relocs_idx == -1) {
937                 DRM_ERROR("No relocation chunk !\n");
938                 return -EINVAL;
939         }
940         *cs_reloc = NULL;
941         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
942         r = r600_cs_packet_parse(p, &p3reloc, p->idx);
943         if (r) {
944                 return r;
945         }
946         p->idx += p3reloc.count + 2;
947         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
948                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
949                           p3reloc.idx);
950                 return -EINVAL;
951         }
952         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
953         if (idx >= relocs_chunk->length_dw) {
954                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
955                           idx, relocs_chunk->length_dw);
956                 return -EINVAL;
957         }
958         *cs_reloc = p->relocs;
959         (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32;
960         (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
961         return 0;
962 }
963
964 /**
965  * r600_cs_packet_next_is_pkt3_nop() - test if next packet is packet3 nop for reloc
966  * @parser:             parser structure holding parsing context.
967  *
968  * Check next packet is relocation packet3, do bo validation and compute
969  * GPU offset using the provided start.
970  **/
971 static int r600_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
972 {
973         struct radeon_cs_packet p3reloc;
974         int r;
975
976         r = r600_cs_packet_parse(p, &p3reloc, p->idx);
977         if (r) {
978                 return 0;
979         }
980         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
981                 return 0;
982         }
983         return 1;
984 }
985
986 /**
987  * r600_cs_packet_next_vline() - parse userspace VLINE packet
988  * @parser:             parser structure holding parsing context.
989  *
990  * Userspace sends a special sequence for VLINE waits.
991  * PACKET0 - VLINE_START_END + value
992  * PACKET3 - WAIT_REG_MEM poll vline status reg
993  * RELOC (P3) - crtc_id in reloc.
994  *
995  * This function parses this and relocates the VLINE START END
996  * and WAIT_REG_MEM packets to the correct crtc.
997  * It also detects a switched off crtc and nulls out the
998  * wait in that case.
999  */
1000 static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
1001 {
1002         struct drm_mode_object *obj;
1003         struct drm_crtc *crtc;
1004         struct radeon_crtc *radeon_crtc;
1005         struct radeon_cs_packet p3reloc, wait_reg_mem;
1006         int crtc_id;
1007         int r;
1008         uint32_t header, h_idx, reg, wait_reg_mem_info;
1009         volatile uint32_t *ib;
1010
1011         ib = p->ib.ptr;
1012
1013         /* parse the WAIT_REG_MEM */
1014         r = r600_cs_packet_parse(p, &wait_reg_mem, p->idx);
1015         if (r)
1016                 return r;
1017
1018         /* check its a WAIT_REG_MEM */
1019         if (wait_reg_mem.type != PACKET_TYPE3 ||
1020             wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
1021                 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
1022                 return -EINVAL;
1023         }
1024
1025         wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
1026         /* bit 4 is reg (0) or mem (1) */
1027         if (wait_reg_mem_info & 0x10) {
1028                 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n");
1029                 return -EINVAL;
1030         }
1031         /* waiting for value to be equal */
1032         if ((wait_reg_mem_info & 0x7) != 0x3) {
1033                 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
1034                 return -EINVAL;
1035         }
1036         if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != AVIVO_D1MODE_VLINE_STATUS) {
1037                 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
1038                 return -EINVAL;
1039         }
1040
1041         if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != AVIVO_D1MODE_VLINE_STAT) {
1042                 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
1043                 return -EINVAL;
1044         }
1045
1046         /* jump over the NOP */
1047         r = r600_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);
1048         if (r)
1049                 return r;
1050
1051         h_idx = p->idx - 2;
1052         p->idx += wait_reg_mem.count + 2;
1053         p->idx += p3reloc.count + 2;
1054
1055         header = radeon_get_ib_value(p, h_idx);
1056         crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
1057         reg = CP_PACKET0_GET_REG(header);
1058
1059         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1060         if (!obj) {
1061                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1062                 return -EINVAL;
1063         }
1064         crtc = obj_to_crtc(obj);
1065         radeon_crtc = to_radeon_crtc(crtc);
1066         crtc_id = radeon_crtc->crtc_id;
1067
1068         if (!crtc->enabled) {
1069                 /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
1070                 ib[h_idx + 2] = PACKET2(0);
1071                 ib[h_idx + 3] = PACKET2(0);
1072                 ib[h_idx + 4] = PACKET2(0);
1073                 ib[h_idx + 5] = PACKET2(0);
1074                 ib[h_idx + 6] = PACKET2(0);
1075                 ib[h_idx + 7] = PACKET2(0);
1076                 ib[h_idx + 8] = PACKET2(0);
1077         } else if (crtc_id == 1) {
1078                 switch (reg) {
1079                 case AVIVO_D1MODE_VLINE_START_END:
1080                         header &= ~R600_CP_PACKET0_REG_MASK;
1081                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1082                         break;
1083                 default:
1084                         DRM_ERROR("unknown crtc reloc\n");
1085                         return -EINVAL;
1086                 }
1087                 ib[h_idx] = header;
1088                 ib[h_idx + 4] = AVIVO_D2MODE_VLINE_STATUS >> 2;
1089         }
1090
1091         return 0;
1092 }
1093
1094 static int r600_packet0_check(struct radeon_cs_parser *p,
1095                                 struct radeon_cs_packet *pkt,
1096                                 unsigned idx, unsigned reg)
1097 {
1098         int r;
1099
1100         switch (reg) {
1101         case AVIVO_D1MODE_VLINE_START_END:
1102                 r = r600_cs_packet_parse_vline(p);
1103                 if (r) {
1104                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1105                                         idx, reg);
1106                         return r;
1107                 }
1108                 break;
1109         default:
1110                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1111                        reg, idx);
1112                 return -EINVAL;
1113         }
1114         return 0;
1115 }
1116
1117 static int r600_cs_parse_packet0(struct radeon_cs_parser *p,
1118                                 struct radeon_cs_packet *pkt)
1119 {
1120         unsigned reg, i;
1121         unsigned idx;
1122         int r;
1123
1124         idx = pkt->idx + 1;
1125         reg = pkt->reg;
1126         for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
1127                 r = r600_packet0_check(p, pkt, idx, reg);
1128                 if (r) {
1129                         return r;
1130                 }
1131         }
1132         return 0;
1133 }
1134
1135 /**
1136  * r600_cs_check_reg() - check if register is authorized or not
1137  * @parser: parser structure holding parsing context
1138  * @reg: register we are testing
1139  * @idx: index into the cs buffer
1140  *
1141  * This function will test against r600_reg_safe_bm and return 0
1142  * if register is safe. If register is not flag as safe this function
1143  * will test it against a list of register needind special handling.
1144  */
1145 static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1146 {
1147         struct r600_cs_track *track = (struct r600_cs_track *)p->track;
1148         struct radeon_cs_reloc *reloc;
1149         u32 m, i, tmp, *ib;
1150         int r;
1151
1152         i = (reg >> 7);
1153         if (i >= ARRAY_SIZE(r600_reg_safe_bm)) {
1154                 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1155                 return -EINVAL;
1156         }
1157         m = 1 << ((reg >> 2) & 31);
1158         if (!(r600_reg_safe_bm[i] & m))
1159                 return 0;
1160         ib = p->ib.ptr;
1161         switch (reg) {
1162         /* force following reg to 0 in an attempt to disable out buffer
1163          * which will need us to better understand how it works to perform
1164          * security check on it (Jerome)
1165          */
1166         case R_0288A8_SQ_ESGS_RING_ITEMSIZE:
1167         case R_008C44_SQ_ESGS_RING_SIZE:
1168         case R_0288B0_SQ_ESTMP_RING_ITEMSIZE:
1169         case R_008C54_SQ_ESTMP_RING_SIZE:
1170         case R_0288C0_SQ_FBUF_RING_ITEMSIZE:
1171         case R_008C74_SQ_FBUF_RING_SIZE:
1172         case R_0288B4_SQ_GSTMP_RING_ITEMSIZE:
1173         case R_008C5C_SQ_GSTMP_RING_SIZE:
1174         case R_0288AC_SQ_GSVS_RING_ITEMSIZE:
1175         case R_008C4C_SQ_GSVS_RING_SIZE:
1176         case R_0288BC_SQ_PSTMP_RING_ITEMSIZE:
1177         case R_008C6C_SQ_PSTMP_RING_SIZE:
1178         case R_0288C4_SQ_REDUC_RING_ITEMSIZE:
1179         case R_008C7C_SQ_REDUC_RING_SIZE:
1180         case R_0288B8_SQ_VSTMP_RING_ITEMSIZE:
1181         case R_008C64_SQ_VSTMP_RING_SIZE:
1182         case R_0288C8_SQ_GS_VERT_ITEMSIZE:
1183                 /* get value to populate the IB don't remove */
1184                 tmp =radeon_get_ib_value(p, idx);
1185                 ib[idx] = 0;
1186                 break;
1187         case SQ_CONFIG:
1188                 track->sq_config = radeon_get_ib_value(p, idx);
1189                 break;
1190         case R_028800_DB_DEPTH_CONTROL:
1191                 track->db_depth_control = radeon_get_ib_value(p, idx);
1192                 track->db_dirty = true;
1193                 break;
1194         case R_028010_DB_DEPTH_INFO:
1195                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) &&
1196                     r600_cs_packet_next_is_pkt3_nop(p)) {
1197                         r = r600_cs_packet_next_reloc(p, &reloc);
1198                         if (r) {
1199                                 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1200                                          "0x%04X\n", reg);
1201                                 return -EINVAL;
1202                         }
1203                         track->db_depth_info = radeon_get_ib_value(p, idx);
1204                         ib[idx] &= C_028010_ARRAY_MODE;
1205                         track->db_depth_info &= C_028010_ARRAY_MODE;
1206                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1207                                 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
1208                                 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
1209                         } else {
1210                                 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
1211                                 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
1212                         }
1213                 } else {
1214                         track->db_depth_info = radeon_get_ib_value(p, idx);
1215                 }
1216                 track->db_dirty = true;
1217                 break;
1218         case R_028004_DB_DEPTH_VIEW:
1219                 track->db_depth_view = radeon_get_ib_value(p, idx);
1220                 track->db_dirty = true;
1221                 break;
1222         case R_028000_DB_DEPTH_SIZE:
1223                 track->db_depth_size = radeon_get_ib_value(p, idx);
1224                 track->db_depth_size_idx = idx;
1225                 track->db_dirty = true;
1226                 break;
1227         case R_028AB0_VGT_STRMOUT_EN:
1228                 track->vgt_strmout_en = radeon_get_ib_value(p, idx);
1229                 track->streamout_dirty = true;
1230                 break;
1231         case R_028B20_VGT_STRMOUT_BUFFER_EN:
1232                 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx);
1233                 track->streamout_dirty = true;
1234                 break;
1235         case VGT_STRMOUT_BUFFER_BASE_0:
1236         case VGT_STRMOUT_BUFFER_BASE_1:
1237         case VGT_STRMOUT_BUFFER_BASE_2:
1238         case VGT_STRMOUT_BUFFER_BASE_3:
1239                 r = r600_cs_packet_next_reloc(p, &reloc);
1240                 if (r) {
1241                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1242                                         "0x%04X\n", reg);
1243                         return -EINVAL;
1244                 }
1245                 tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16;
1246                 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1247                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1248                 track->vgt_strmout_bo[tmp] = reloc->robj;
1249                 track->vgt_strmout_bo_mc[tmp] = reloc->lobj.gpu_offset;
1250                 track->streamout_dirty = true;
1251                 break;
1252         case VGT_STRMOUT_BUFFER_SIZE_0:
1253         case VGT_STRMOUT_BUFFER_SIZE_1:
1254         case VGT_STRMOUT_BUFFER_SIZE_2:
1255         case VGT_STRMOUT_BUFFER_SIZE_3:
1256                 tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16;
1257                 /* size in register is DWs, convert to bytes */
1258                 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;
1259                 track->streamout_dirty = true;
1260                 break;
1261         case CP_COHER_BASE:
1262                 r = r600_cs_packet_next_reloc(p, &reloc);
1263                 if (r) {
1264                         dev_warn(p->dev, "missing reloc for CP_COHER_BASE "
1265                                         "0x%04X\n", reg);
1266                         return -EINVAL;
1267                 }
1268                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1269                 break;
1270         case R_028238_CB_TARGET_MASK:
1271                 track->cb_target_mask = radeon_get_ib_value(p, idx);
1272                 track->cb_dirty = true;
1273                 break;
1274         case R_02823C_CB_SHADER_MASK:
1275                 track->cb_shader_mask = radeon_get_ib_value(p, idx);
1276                 break;
1277         case R_028C04_PA_SC_AA_CONFIG:
1278                 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));
1279                 track->log_nsamples = tmp;
1280                 track->nsamples = 1 << tmp;
1281                 track->cb_dirty = true;
1282                 break;
1283         case R_0280A0_CB_COLOR0_INFO:
1284         case R_0280A4_CB_COLOR1_INFO:
1285         case R_0280A8_CB_COLOR2_INFO:
1286         case R_0280AC_CB_COLOR3_INFO:
1287         case R_0280B0_CB_COLOR4_INFO:
1288         case R_0280B4_CB_COLOR5_INFO:
1289         case R_0280B8_CB_COLOR6_INFO:
1290         case R_0280BC_CB_COLOR7_INFO:
1291                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) &&
1292                      r600_cs_packet_next_is_pkt3_nop(p)) {
1293                         r = r600_cs_packet_next_reloc(p, &reloc);
1294                         if (r) {
1295                                 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1296                                 return -EINVAL;
1297                         }
1298                         tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
1299                         track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1300                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1301                                 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
1302                                 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
1303                         } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
1304                                 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
1305                                 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
1306                         }
1307                 } else {
1308                         tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
1309                         track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1310                 }
1311                 track->cb_dirty = true;
1312                 break;
1313         case R_028080_CB_COLOR0_VIEW:
1314         case R_028084_CB_COLOR1_VIEW:
1315         case R_028088_CB_COLOR2_VIEW:
1316         case R_02808C_CB_COLOR3_VIEW:
1317         case R_028090_CB_COLOR4_VIEW:
1318         case R_028094_CB_COLOR5_VIEW:
1319         case R_028098_CB_COLOR6_VIEW:
1320         case R_02809C_CB_COLOR7_VIEW:
1321                 tmp = (reg - R_028080_CB_COLOR0_VIEW) / 4;
1322                 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
1323                 track->cb_dirty = true;
1324                 break;
1325         case R_028060_CB_COLOR0_SIZE:
1326         case R_028064_CB_COLOR1_SIZE:
1327         case R_028068_CB_COLOR2_SIZE:
1328         case R_02806C_CB_COLOR3_SIZE:
1329         case R_028070_CB_COLOR4_SIZE:
1330         case R_028074_CB_COLOR5_SIZE:
1331         case R_028078_CB_COLOR6_SIZE:
1332         case R_02807C_CB_COLOR7_SIZE:
1333                 tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4;
1334                 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx);
1335                 track->cb_color_size_idx[tmp] = idx;
1336                 track->cb_dirty = true;
1337                 break;
1338                 /* This register were added late, there is userspace
1339                  * which does provide relocation for those but set
1340                  * 0 offset. In order to avoid breaking old userspace
1341                  * we detect this and set address to point to last
1342                  * CB_COLOR0_BASE, note that if userspace doesn't set
1343                  * CB_COLOR0_BASE before this register we will report
1344                  * error. Old userspace always set CB_COLOR0_BASE
1345                  * before any of this.
1346                  */
1347         case R_0280E0_CB_COLOR0_FRAG:
1348         case R_0280E4_CB_COLOR1_FRAG:
1349         case R_0280E8_CB_COLOR2_FRAG:
1350         case R_0280EC_CB_COLOR3_FRAG:
1351         case R_0280F0_CB_COLOR4_FRAG:
1352         case R_0280F4_CB_COLOR5_FRAG:
1353         case R_0280F8_CB_COLOR6_FRAG:
1354         case R_0280FC_CB_COLOR7_FRAG:
1355                 tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4;
1356                 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
1357                         if (!track->cb_color_base_last[tmp]) {
1358                                 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1359                                 return -EINVAL;
1360                         }
1361                         track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];
1362                         track->cb_color_frag_offset[tmp] = track->cb_color_bo_offset[tmp];
1363                         ib[idx] = track->cb_color_base_last[tmp];
1364                 } else {
1365                         r = r600_cs_packet_next_reloc(p, &reloc);
1366                         if (r) {
1367                                 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1368                                 return -EINVAL;
1369                         }
1370                         track->cb_color_frag_bo[tmp] = reloc->robj;
1371                         track->cb_color_frag_offset[tmp] = (u64)ib[idx] << 8;
1372                         ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1373                 }
1374                 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1375                         track->cb_dirty = true;
1376                 }
1377                 break;
1378         case R_0280C0_CB_COLOR0_TILE:
1379         case R_0280C4_CB_COLOR1_TILE:
1380         case R_0280C8_CB_COLOR2_TILE:
1381         case R_0280CC_CB_COLOR3_TILE:
1382         case R_0280D0_CB_COLOR4_TILE:
1383         case R_0280D4_CB_COLOR5_TILE:
1384         case R_0280D8_CB_COLOR6_TILE:
1385         case R_0280DC_CB_COLOR7_TILE:
1386                 tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4;
1387                 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
1388                         if (!track->cb_color_base_last[tmp]) {
1389                                 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1390                                 return -EINVAL;
1391                         }
1392                         track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];
1393                         track->cb_color_tile_offset[tmp] = track->cb_color_bo_offset[tmp];
1394                         ib[idx] = track->cb_color_base_last[tmp];
1395                 } else {
1396                         r = r600_cs_packet_next_reloc(p, &reloc);
1397                         if (r) {
1398                                 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1399                                 return -EINVAL;
1400                         }
1401                         track->cb_color_tile_bo[tmp] = reloc->robj;
1402                         track->cb_color_tile_offset[tmp] = (u64)ib[idx] << 8;
1403                         ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1404                 }
1405                 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1406                         track->cb_dirty = true;
1407                 }
1408                 break;
1409         case R_028100_CB_COLOR0_MASK:
1410         case R_028104_CB_COLOR1_MASK:
1411         case R_028108_CB_COLOR2_MASK:
1412         case R_02810C_CB_COLOR3_MASK:
1413         case R_028110_CB_COLOR4_MASK:
1414         case R_028114_CB_COLOR5_MASK:
1415         case R_028118_CB_COLOR6_MASK:
1416         case R_02811C_CB_COLOR7_MASK:
1417                 tmp = (reg - R_028100_CB_COLOR0_MASK) / 4;
1418                 track->cb_color_mask[tmp] = ib[idx];
1419                 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1420                         track->cb_dirty = true;
1421                 }
1422                 break;
1423         case CB_COLOR0_BASE:
1424         case CB_COLOR1_BASE:
1425         case CB_COLOR2_BASE:
1426         case CB_COLOR3_BASE:
1427         case CB_COLOR4_BASE:
1428         case CB_COLOR5_BASE:
1429         case CB_COLOR6_BASE:
1430         case CB_COLOR7_BASE:
1431                 r = r600_cs_packet_next_reloc(p, &reloc);
1432                 if (r) {
1433                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1434                                         "0x%04X\n", reg);
1435                         return -EINVAL;
1436                 }
1437                 tmp = (reg - CB_COLOR0_BASE) / 4;
1438                 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1439                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1440                 track->cb_color_base_last[tmp] = ib[idx];
1441                 track->cb_color_bo[tmp] = reloc->robj;
1442                 track->cb_color_bo_mc[tmp] = reloc->lobj.gpu_offset;
1443                 track->cb_dirty = true;
1444                 break;
1445         case DB_DEPTH_BASE:
1446                 r = r600_cs_packet_next_reloc(p, &reloc);
1447                 if (r) {
1448                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1449                                         "0x%04X\n", reg);
1450                         return -EINVAL;
1451                 }
1452                 track->db_offset = radeon_get_ib_value(p, idx) << 8;
1453                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1454                 track->db_bo = reloc->robj;
1455                 track->db_bo_mc = reloc->lobj.gpu_offset;
1456                 track->db_dirty = true;
1457                 break;
1458         case DB_HTILE_DATA_BASE:
1459                 r = r600_cs_packet_next_reloc(p, &reloc);
1460                 if (r) {
1461                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1462                                         "0x%04X\n", reg);
1463                         return -EINVAL;
1464                 }
1465                 track->htile_offset = radeon_get_ib_value(p, idx) << 8;
1466                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1467                 track->htile_bo = reloc->robj;
1468                 track->db_dirty = true;
1469                 break;
1470         case DB_HTILE_SURFACE:
1471                 track->htile_surface = radeon_get_ib_value(p, idx);
1472                 track->db_dirty = true;
1473                 break;
1474         case SQ_PGM_START_FS:
1475         case SQ_PGM_START_ES:
1476         case SQ_PGM_START_VS:
1477         case SQ_PGM_START_GS:
1478         case SQ_PGM_START_PS:
1479         case SQ_ALU_CONST_CACHE_GS_0:
1480         case SQ_ALU_CONST_CACHE_GS_1:
1481         case SQ_ALU_CONST_CACHE_GS_2:
1482         case SQ_ALU_CONST_CACHE_GS_3:
1483         case SQ_ALU_CONST_CACHE_GS_4:
1484         case SQ_ALU_CONST_CACHE_GS_5:
1485         case SQ_ALU_CONST_CACHE_GS_6:
1486         case SQ_ALU_CONST_CACHE_GS_7:
1487         case SQ_ALU_CONST_CACHE_GS_8:
1488         case SQ_ALU_CONST_CACHE_GS_9:
1489         case SQ_ALU_CONST_CACHE_GS_10:
1490         case SQ_ALU_CONST_CACHE_GS_11:
1491         case SQ_ALU_CONST_CACHE_GS_12:
1492         case SQ_ALU_CONST_CACHE_GS_13:
1493         case SQ_ALU_CONST_CACHE_GS_14:
1494         case SQ_ALU_CONST_CACHE_GS_15:
1495         case SQ_ALU_CONST_CACHE_PS_0:
1496         case SQ_ALU_CONST_CACHE_PS_1:
1497         case SQ_ALU_CONST_CACHE_PS_2:
1498         case SQ_ALU_CONST_CACHE_PS_3:
1499         case SQ_ALU_CONST_CACHE_PS_4:
1500         case SQ_ALU_CONST_CACHE_PS_5:
1501         case SQ_ALU_CONST_CACHE_PS_6:
1502         case SQ_ALU_CONST_CACHE_PS_7:
1503         case SQ_ALU_CONST_CACHE_PS_8:
1504         case SQ_ALU_CONST_CACHE_PS_9:
1505         case SQ_ALU_CONST_CACHE_PS_10:
1506         case SQ_ALU_CONST_CACHE_PS_11:
1507         case SQ_ALU_CONST_CACHE_PS_12:
1508         case SQ_ALU_CONST_CACHE_PS_13:
1509         case SQ_ALU_CONST_CACHE_PS_14:
1510         case SQ_ALU_CONST_CACHE_PS_15:
1511         case SQ_ALU_CONST_CACHE_VS_0:
1512         case SQ_ALU_CONST_CACHE_VS_1:
1513         case SQ_ALU_CONST_CACHE_VS_2:
1514         case SQ_ALU_CONST_CACHE_VS_3:
1515         case SQ_ALU_CONST_CACHE_VS_4:
1516         case SQ_ALU_CONST_CACHE_VS_5:
1517         case SQ_ALU_CONST_CACHE_VS_6:
1518         case SQ_ALU_CONST_CACHE_VS_7:
1519         case SQ_ALU_CONST_CACHE_VS_8:
1520         case SQ_ALU_CONST_CACHE_VS_9:
1521         case SQ_ALU_CONST_CACHE_VS_10:
1522         case SQ_ALU_CONST_CACHE_VS_11:
1523         case SQ_ALU_CONST_CACHE_VS_12:
1524         case SQ_ALU_CONST_CACHE_VS_13:
1525         case SQ_ALU_CONST_CACHE_VS_14:
1526         case SQ_ALU_CONST_CACHE_VS_15:
1527                 r = r600_cs_packet_next_reloc(p, &reloc);
1528                 if (r) {
1529                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1530                                         "0x%04X\n", reg);
1531                         return -EINVAL;
1532                 }
1533                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1534                 break;
1535         case SX_MEMORY_EXPORT_BASE:
1536                 r = r600_cs_packet_next_reloc(p, &reloc);
1537                 if (r) {
1538                         dev_warn(p->dev, "bad SET_CONFIG_REG "
1539                                         "0x%04X\n", reg);
1540                         return -EINVAL;
1541                 }
1542                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1543                 break;
1544         case SX_MISC:
1545                 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0;
1546                 break;
1547         default:
1548                 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1549                 return -EINVAL;
1550         }
1551         return 0;
1552 }
1553
1554 unsigned r600_mip_minify(unsigned size, unsigned level)
1555 {
1556         unsigned val;
1557
1558         val = max(1U, size >> level);
1559         if (level > 0)
1560                 val = roundup_pow_of_two(val);
1561         return val;
1562 }
1563
1564 static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel,
1565                               unsigned w0, unsigned h0, unsigned d0, unsigned format,
1566                               unsigned block_align, unsigned height_align, unsigned base_align,
1567                               unsigned *l0_size, unsigned *mipmap_size)
1568 {
1569         unsigned offset, i, level;
1570         unsigned width, height, depth, size;
1571         unsigned blocksize;
1572         unsigned nbx, nby;
1573         unsigned nlevels = llevel - blevel + 1;
1574
1575         *l0_size = -1;
1576         blocksize = r600_fmt_get_blocksize(format);
1577
1578         w0 = r600_mip_minify(w0, 0);
1579         h0 = r600_mip_minify(h0, 0);
1580         d0 = r600_mip_minify(d0, 0);
1581         for(i = 0, offset = 0, level = blevel; i < nlevels; i++, level++) {
1582                 width = r600_mip_minify(w0, i);
1583                 nbx = r600_fmt_get_nblocksx(format, width);
1584
1585                 nbx = round_up(nbx, block_align);
1586
1587                 height = r600_mip_minify(h0, i);
1588                 nby = r600_fmt_get_nblocksy(format, height);
1589                 nby = round_up(nby, height_align);
1590
1591                 depth = r600_mip_minify(d0, i);
1592
1593                 size = nbx * nby * blocksize;
1594                 if (nfaces)
1595                         size *= nfaces;
1596                 else
1597                         size *= depth;
1598
1599                 if (i == 0)
1600                         *l0_size = size;
1601
1602                 if (i == 0 || i == 1)
1603                         offset = round_up(offset, base_align);
1604
1605                 offset += size;
1606         }
1607         *mipmap_size = offset;
1608         if (llevel == 0)
1609                 *mipmap_size = *l0_size;
1610         if (!blevel)
1611                 *mipmap_size -= *l0_size;
1612 }
1613
1614 /**
1615  * r600_check_texture_resource() - check if register is authorized or not
1616  * @p: parser structure holding parsing context
1617  * @idx: index into the cs buffer
1618  * @texture: texture's bo structure
1619  * @mipmap: mipmap's bo structure
1620  *
1621  * This function will check that the resource has valid field and that
1622  * the texture and mipmap bo object are big enough to cover this resource.
1623  */
1624 static int r600_check_texture_resource(struct radeon_cs_parser *p,  u32 idx,
1625                                               struct radeon_bo *texture,
1626                                               struct radeon_bo *mipmap,
1627                                               u64 base_offset,
1628                                               u64 mip_offset,
1629                                               u32 tiling_flags)
1630 {
1631         struct r600_cs_track *track = p->track;
1632         u32 dim, nfaces, llevel, blevel, w0, h0, d0;
1633         u32 word0, word1, l0_size, mipmap_size, word2, word3, word4, word5;
1634         u32 height_align, pitch, pitch_align, depth_align;
1635         u32 barray, larray;
1636         u64 base_align;
1637         struct array_mode_checker array_check;
1638         u32 format;
1639         bool is_array;
1640
1641         /* on legacy kernel we don't perform advanced check */
1642         if (p->rdev == NULL)
1643                 return 0;
1644
1645         /* convert to bytes */
1646         base_offset <<= 8;
1647         mip_offset <<= 8;
1648
1649         word0 = radeon_get_ib_value(p, idx + 0);
1650         if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1651                 if (tiling_flags & RADEON_TILING_MACRO)
1652                         word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1653                 else if (tiling_flags & RADEON_TILING_MICRO)
1654                         word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1655         }
1656         word1 = radeon_get_ib_value(p, idx + 1);
1657         word2 = radeon_get_ib_value(p, idx + 2) << 8;
1658         word3 = radeon_get_ib_value(p, idx + 3) << 8;
1659         word4 = radeon_get_ib_value(p, idx + 4);
1660         word5 = radeon_get_ib_value(p, idx + 5);
1661         dim = G_038000_DIM(word0);
1662         w0 = G_038000_TEX_WIDTH(word0) + 1;
1663         pitch = (G_038000_PITCH(word0) + 1) * 8;
1664         h0 = G_038004_TEX_HEIGHT(word1) + 1;
1665         d0 = G_038004_TEX_DEPTH(word1);
1666         format = G_038004_DATA_FORMAT(word1);
1667         blevel = G_038010_BASE_LEVEL(word4);
1668         llevel = G_038014_LAST_LEVEL(word5);
1669         /* pitch in texels */
1670         array_check.array_mode = G_038000_TILE_MODE(word0);
1671         array_check.group_size = track->group_size;
1672         array_check.nbanks = track->nbanks;
1673         array_check.npipes = track->npipes;
1674         array_check.nsamples = 1;
1675         array_check.blocksize = r600_fmt_get_blocksize(format);
1676         nfaces = 1;
1677         is_array = false;
1678         switch (dim) {
1679         case V_038000_SQ_TEX_DIM_1D:
1680         case V_038000_SQ_TEX_DIM_2D:
1681         case V_038000_SQ_TEX_DIM_3D:
1682                 break;
1683         case V_038000_SQ_TEX_DIM_CUBEMAP:
1684                 if (p->family >= CHIP_RV770)
1685                         nfaces = 8;
1686                 else
1687                         nfaces = 6;
1688                 break;
1689         case V_038000_SQ_TEX_DIM_1D_ARRAY:
1690         case V_038000_SQ_TEX_DIM_2D_ARRAY:
1691                 is_array = true;
1692                 break;
1693         case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA:
1694                 is_array = true;
1695                 /* fall through */
1696         case V_038000_SQ_TEX_DIM_2D_MSAA:
1697                 array_check.nsamples = 1 << llevel;
1698                 llevel = 0;
1699                 break;
1700         default:
1701                 dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0));
1702                 return -EINVAL;
1703         }
1704         if (!r600_fmt_is_valid_texture(format, p->family)) {
1705                 dev_warn(p->dev, "%s:%d texture invalid format %d\n",
1706                          __func__, __LINE__, format);
1707                 return -EINVAL;
1708         }
1709
1710         if (r600_get_array_mode_alignment(&array_check,
1711                                           &pitch_align, &height_align, &depth_align, &base_align)) {
1712                 dev_warn(p->dev, "%s:%d tex array mode (%d) invalid\n",
1713                          __func__, __LINE__, G_038000_TILE_MODE(word0));
1714                 return -EINVAL;
1715         }
1716
1717         /* XXX check height as well... */
1718
1719         if (!IS_ALIGNED(pitch, pitch_align)) {
1720                 dev_warn(p->dev, "%s:%d tex pitch (%d, 0x%x, %d) invalid\n",
1721                          __func__, __LINE__, pitch, pitch_align, G_038000_TILE_MODE(word0));
1722                 return -EINVAL;
1723         }
1724         if (!IS_ALIGNED(base_offset, base_align)) {
1725                 dev_warn(p->dev, "%s:%d tex base offset (0x%llx, 0x%llx, %d) invalid\n",
1726                          __func__, __LINE__, base_offset, base_align, G_038000_TILE_MODE(word0));
1727                 return -EINVAL;
1728         }
1729         if (!IS_ALIGNED(mip_offset, base_align)) {
1730                 dev_warn(p->dev, "%s:%d tex mip offset (0x%llx, 0x%llx, %d) invalid\n",
1731                          __func__, __LINE__, mip_offset, base_align, G_038000_TILE_MODE(word0));
1732                 return -EINVAL;
1733         }
1734
1735         if (blevel > llevel) {
1736                 dev_warn(p->dev, "texture blevel %d > llevel %d\n",
1737                          blevel, llevel);
1738         }
1739         if (is_array) {
1740                 barray = G_038014_BASE_ARRAY(word5);
1741                 larray = G_038014_LAST_ARRAY(word5);
1742
1743                 nfaces = larray - barray + 1;
1744         }
1745         r600_texture_size(nfaces, blevel, llevel, w0, h0, d0, format,
1746                           pitch_align, height_align, base_align,
1747                           &l0_size, &mipmap_size);
1748         /* using get ib will give us the offset into the texture bo */
1749         if ((l0_size + word2) > radeon_bo_size(texture)) {
1750                 dev_warn(p->dev, "texture bo too small ((%d %d) (%d %d) %d %d %d -> %d have %ld)\n",
1751                          w0, h0, pitch_align, height_align,
1752                          array_check.array_mode, format, word2,
1753                          l0_size, radeon_bo_size(texture));
1754                 dev_warn(p->dev, "alignments %d %d %d %lld\n", pitch, pitch_align, height_align, base_align);
1755                 return -EINVAL;
1756         }
1757         /* using get ib will give us the offset into the mipmap bo */
1758         if ((mipmap_size + word3) > radeon_bo_size(mipmap)) {
1759                 /*dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n",
1760                   w0, h0, format, blevel, nlevels, word3, mipmap_size, radeon_bo_size(texture));*/
1761         }
1762         return 0;
1763 }
1764
1765 static bool r600_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1766 {
1767         u32 m, i;
1768
1769         i = (reg >> 7);
1770         if (i >= ARRAY_SIZE(r600_reg_safe_bm)) {
1771                 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1772                 return false;
1773         }
1774         m = 1 << ((reg >> 2) & 31);
1775         if (!(r600_reg_safe_bm[i] & m))
1776                 return true;
1777         dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1778         return false;
1779 }
1780
1781 static int r600_packet3_check(struct radeon_cs_parser *p,
1782                                 struct radeon_cs_packet *pkt)
1783 {
1784         struct radeon_cs_reloc *reloc;
1785         struct r600_cs_track *track;
1786         volatile u32 *ib;
1787         unsigned idx;
1788         unsigned i;
1789         unsigned start_reg, end_reg, reg;
1790         int r;
1791         u32 idx_value;
1792
1793         track = (struct r600_cs_track *)p->track;
1794         ib = p->ib.ptr;
1795         idx = pkt->idx + 1;
1796         idx_value = radeon_get_ib_value(p, idx);
1797
1798         switch (pkt->opcode) {
1799         case PACKET3_SET_PREDICATION:
1800         {
1801                 int pred_op;
1802                 int tmp;
1803                 uint64_t offset;
1804
1805                 if (pkt->count != 1) {
1806                         DRM_ERROR("bad SET PREDICATION\n");
1807                         return -EINVAL;
1808                 }
1809
1810                 tmp = radeon_get_ib_value(p, idx + 1);
1811                 pred_op = (tmp >> 16) & 0x7;
1812
1813                 /* for the clear predicate operation */
1814                 if (pred_op == 0)
1815                         return 0;
1816
1817                 if (pred_op > 2) {
1818                         DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op);
1819                         return -EINVAL;
1820                 }
1821
1822                 r = r600_cs_packet_next_reloc(p, &reloc);
1823                 if (r) {
1824                         DRM_ERROR("bad SET PREDICATION\n");
1825                         return -EINVAL;
1826                 }
1827
1828                 offset = reloc->lobj.gpu_offset +
1829                          (idx_value & 0xfffffff0) +
1830                          ((u64)(tmp & 0xff) << 32);
1831
1832                 ib[idx + 0] = offset;
1833                 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff);
1834         }
1835         break;
1836
1837         case PACKET3_START_3D_CMDBUF:
1838                 if (p->family >= CHIP_RV770 || pkt->count) {
1839                         DRM_ERROR("bad START_3D\n");
1840                         return -EINVAL;
1841                 }
1842                 break;
1843         case PACKET3_CONTEXT_CONTROL:
1844                 if (pkt->count != 1) {
1845                         DRM_ERROR("bad CONTEXT_CONTROL\n");
1846                         return -EINVAL;
1847                 }
1848                 break;
1849         case PACKET3_INDEX_TYPE:
1850         case PACKET3_NUM_INSTANCES:
1851                 if (pkt->count) {
1852                         DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n");
1853                         return -EINVAL;
1854                 }
1855                 break;
1856         case PACKET3_DRAW_INDEX:
1857         {
1858                 uint64_t offset;
1859                 if (pkt->count != 3) {
1860                         DRM_ERROR("bad DRAW_INDEX\n");
1861                         return -EINVAL;
1862                 }
1863                 r = r600_cs_packet_next_reloc(p, &reloc);
1864                 if (r) {
1865                         DRM_ERROR("bad DRAW_INDEX\n");
1866                         return -EINVAL;
1867                 }
1868
1869                 offset = reloc->lobj.gpu_offset +
1870                          idx_value +
1871                          ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
1872
1873                 ib[idx+0] = offset;
1874                 ib[idx+1] = upper_32_bits(offset) & 0xff;
1875
1876                 r = r600_cs_track_check(p);
1877                 if (r) {
1878                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1879                         return r;
1880                 }
1881                 break;
1882         }
1883         case PACKET3_DRAW_INDEX_AUTO:
1884                 if (pkt->count != 1) {
1885                         DRM_ERROR("bad DRAW_INDEX_AUTO\n");
1886                         return -EINVAL;
1887                 }
1888                 r = r600_cs_track_check(p);
1889                 if (r) {
1890                         dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
1891                         return r;
1892                 }
1893                 break;
1894         case PACKET3_DRAW_INDEX_IMMD_BE:
1895         case PACKET3_DRAW_INDEX_IMMD:
1896                 if (pkt->count < 2) {
1897                         DRM_ERROR("bad DRAW_INDEX_IMMD\n");
1898                         return -EINVAL;
1899                 }
1900                 r = r600_cs_track_check(p);
1901                 if (r) {
1902                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1903                         return r;
1904                 }
1905                 break;
1906         case PACKET3_WAIT_REG_MEM:
1907                 if (pkt->count != 5) {
1908                         DRM_ERROR("bad WAIT_REG_MEM\n");
1909                         return -EINVAL;
1910                 }
1911                 /* bit 4 is reg (0) or mem (1) */
1912                 if (idx_value & 0x10) {
1913                         uint64_t offset;
1914
1915                         r = r600_cs_packet_next_reloc(p, &reloc);
1916                         if (r) {
1917                                 DRM_ERROR("bad WAIT_REG_MEM\n");
1918                                 return -EINVAL;
1919                         }
1920
1921                         offset = reloc->lobj.gpu_offset +
1922                                  (radeon_get_ib_value(p, idx+1) & 0xfffffff0) +
1923                                  ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
1924
1925                         ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffff0);
1926                         ib[idx+2] = upper_32_bits(offset) & 0xff;
1927                 }
1928                 break;
1929         case PACKET3_SURFACE_SYNC:
1930                 if (pkt->count != 3) {
1931                         DRM_ERROR("bad SURFACE_SYNC\n");
1932                         return -EINVAL;
1933                 }
1934                 /* 0xffffffff/0x0 is flush all cache flag */
1935                 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
1936                     radeon_get_ib_value(p, idx + 2) != 0) {
1937                         r = r600_cs_packet_next_reloc(p, &reloc);
1938                         if (r) {
1939                                 DRM_ERROR("bad SURFACE_SYNC\n");
1940                                 return -EINVAL;
1941                         }
1942                         ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1943                 }
1944                 break;
1945         case PACKET3_EVENT_WRITE:
1946                 if (pkt->count != 2 && pkt->count != 0) {
1947                         DRM_ERROR("bad EVENT_WRITE\n");
1948                         return -EINVAL;
1949                 }
1950                 if (pkt->count) {
1951                         uint64_t offset;
1952
1953                         r = r600_cs_packet_next_reloc(p, &reloc);
1954                         if (r) {
1955                                 DRM_ERROR("bad EVENT_WRITE\n");
1956                                 return -EINVAL;
1957                         }
1958                         offset = reloc->lobj.gpu_offset +
1959                                  (radeon_get_ib_value(p, idx+1) & 0xfffffff8) +
1960                                  ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
1961
1962                         ib[idx+1] = offset & 0xfffffff8;
1963                         ib[idx+2] = upper_32_bits(offset) & 0xff;
1964                 }
1965                 break;
1966         case PACKET3_EVENT_WRITE_EOP:
1967         {
1968                 uint64_t offset;
1969
1970                 if (pkt->count != 4) {
1971                         DRM_ERROR("bad EVENT_WRITE_EOP\n");
1972                         return -EINVAL;
1973                 }
1974                 r = r600_cs_packet_next_reloc(p, &reloc);
1975                 if (r) {
1976                         DRM_ERROR("bad EVENT_WRITE\n");
1977                         return -EINVAL;
1978                 }
1979
1980                 offset = reloc->lobj.gpu_offset +
1981                          (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
1982                          ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
1983
1984                 ib[idx+1] = offset & 0xfffffffc;
1985                 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
1986                 break;
1987         }
1988         case PACKET3_SET_CONFIG_REG:
1989                 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
1990                 end_reg = 4 * pkt->count + start_reg - 4;
1991                 if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) ||
1992                     (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
1993                     (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
1994                         DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
1995                         return -EINVAL;
1996                 }
1997                 for (i = 0; i < pkt->count; i++) {
1998                         reg = start_reg + (4 * i);
1999                         r = r600_cs_check_reg(p, reg, idx+1+i);
2000                         if (r)
2001                                 return r;
2002                 }
2003                 break;
2004         case PACKET3_SET_CONTEXT_REG:
2005                 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET;
2006                 end_reg = 4 * pkt->count + start_reg - 4;
2007                 if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) ||
2008                     (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
2009                     (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
2010                         DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
2011                         return -EINVAL;
2012                 }
2013                 for (i = 0; i < pkt->count; i++) {
2014                         reg = start_reg + (4 * i);
2015                         r = r600_cs_check_reg(p, reg, idx+1+i);
2016                         if (r)
2017                                 return r;
2018                 }
2019                 break;
2020         case PACKET3_SET_RESOURCE:
2021                 if (pkt->count % 7) {
2022                         DRM_ERROR("bad SET_RESOURCE\n");
2023                         return -EINVAL;
2024                 }
2025                 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET;
2026                 end_reg = 4 * pkt->count + start_reg - 4;
2027                 if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) ||
2028                     (start_reg >= PACKET3_SET_RESOURCE_END) ||
2029                     (end_reg >= PACKET3_SET_RESOURCE_END)) {
2030                         DRM_ERROR("bad SET_RESOURCE\n");
2031                         return -EINVAL;
2032                 }
2033                 for (i = 0; i < (pkt->count / 7); i++) {
2034                         struct radeon_bo *texture, *mipmap;
2035                         u32 size, offset, base_offset, mip_offset;
2036
2037                         switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) {
2038                         case SQ_TEX_VTX_VALID_TEXTURE:
2039                                 /* tex base */
2040                                 r = r600_cs_packet_next_reloc(p, &reloc);
2041                                 if (r) {
2042                                         DRM_ERROR("bad SET_RESOURCE\n");
2043                                         return -EINVAL;
2044                                 }
2045                                 base_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2046                                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
2047                                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
2048                                                 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
2049                                         else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
2050                                                 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
2051                                 }
2052                                 texture = reloc->robj;
2053                                 /* tex mip base */
2054                                 r = r600_cs_packet_next_reloc(p, &reloc);
2055                                 if (r) {
2056                                         DRM_ERROR("bad SET_RESOURCE\n");
2057                                         return -EINVAL;
2058                                 }
2059                                 mip_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2060                                 mipmap = reloc->robj;
2061                                 r = r600_check_texture_resource(p,  idx+(i*7)+1,
2062                                                                 texture, mipmap,
2063                                                                 base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2),
2064                                                                 mip_offset + radeon_get_ib_value(p, idx+1+(i*7)+3),
2065                                                                 reloc->lobj.tiling_flags);
2066                                 if (r)
2067                                         return r;
2068                                 ib[idx+1+(i*7)+2] += base_offset;
2069                                 ib[idx+1+(i*7)+3] += mip_offset;
2070                                 break;
2071                         case SQ_TEX_VTX_VALID_BUFFER:
2072                         {
2073                                 uint64_t offset64;
2074                                 /* vtx base */
2075                                 r = r600_cs_packet_next_reloc(p, &reloc);
2076                                 if (r) {
2077                                         DRM_ERROR("bad SET_RESOURCE\n");
2078                                         return -EINVAL;
2079                                 }
2080                                 offset = radeon_get_ib_value(p, idx+1+(i*7)+0);
2081                                 size = radeon_get_ib_value(p, idx+1+(i*7)+1) + 1;
2082                                 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
2083                                         /* force size to size of the buffer */
2084                                         dev_warn(p->dev, "vbo resource seems too big (%d) for the bo (%ld)\n",
2085                                                  size + offset, radeon_bo_size(reloc->robj));
2086                                         ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj) - offset;
2087                                 }
2088
2089                                 offset64 = reloc->lobj.gpu_offset + offset;
2090                                 ib[idx+1+(i*8)+0] = offset64;
2091                                 ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) |
2092                                                     (upper_32_bits(offset64) & 0xff);
2093                                 break;
2094                         }
2095                         case SQ_TEX_VTX_INVALID_TEXTURE:
2096                         case SQ_TEX_VTX_INVALID_BUFFER:
2097                         default:
2098                                 DRM_ERROR("bad SET_RESOURCE\n");
2099                                 return -EINVAL;
2100                         }
2101                 }
2102                 break;
2103         case PACKET3_SET_ALU_CONST:
2104                 if (track->sq_config & DX9_CONSTS) {
2105                         start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;
2106                         end_reg = 4 * pkt->count + start_reg - 4;
2107                         if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||
2108                             (start_reg >= PACKET3_SET_ALU_CONST_END) ||
2109                             (end_reg >= PACKET3_SET_ALU_CONST_END)) {
2110                                 DRM_ERROR("bad SET_ALU_CONST\n");
2111                                 return -EINVAL;
2112                         }
2113                 }
2114                 break;
2115         case PACKET3_SET_BOOL_CONST:
2116                 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET;
2117                 end_reg = 4 * pkt->count + start_reg - 4;
2118                 if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) ||
2119                     (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
2120                     (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
2121                         DRM_ERROR("bad SET_BOOL_CONST\n");
2122                         return -EINVAL;
2123                 }
2124                 break;
2125         case PACKET3_SET_LOOP_CONST:
2126                 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET;
2127                 end_reg = 4 * pkt->count + start_reg - 4;
2128                 if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) ||
2129                     (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
2130                     (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
2131                         DRM_ERROR("bad SET_LOOP_CONST\n");
2132                         return -EINVAL;
2133                 }
2134                 break;
2135         case PACKET3_SET_CTL_CONST:
2136                 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET;
2137                 end_reg = 4 * pkt->count + start_reg - 4;
2138                 if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) ||
2139                     (start_reg >= PACKET3_SET_CTL_CONST_END) ||
2140                     (end_reg >= PACKET3_SET_CTL_CONST_END)) {
2141                         DRM_ERROR("bad SET_CTL_CONST\n");
2142                         return -EINVAL;
2143                 }
2144                 break;
2145         case PACKET3_SET_SAMPLER:
2146                 if (pkt->count % 3) {
2147                         DRM_ERROR("bad SET_SAMPLER\n");
2148                         return -EINVAL;
2149                 }
2150                 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET;
2151                 end_reg = 4 * pkt->count + start_reg - 4;
2152                 if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) ||
2153                     (start_reg >= PACKET3_SET_SAMPLER_END) ||
2154                     (end_reg >= PACKET3_SET_SAMPLER_END)) {
2155                         DRM_ERROR("bad SET_SAMPLER\n");
2156                         return -EINVAL;
2157                 }
2158                 break;
2159         case PACKET3_STRMOUT_BASE_UPDATE:
2160                 if (p->family < CHIP_RV770) {
2161                         DRM_ERROR("STRMOUT_BASE_UPDATE only supported on 7xx\n");
2162                         return -EINVAL;
2163                 }
2164                 if (pkt->count != 1) {
2165                         DRM_ERROR("bad STRMOUT_BASE_UPDATE packet count\n");
2166                         return -EINVAL;
2167                 }
2168                 if (idx_value > 3) {
2169                         DRM_ERROR("bad STRMOUT_BASE_UPDATE index\n");
2170                         return -EINVAL;
2171                 }
2172                 {
2173                         u64 offset;
2174
2175                         r = r600_cs_packet_next_reloc(p, &reloc);
2176                         if (r) {
2177                                 DRM_ERROR("bad STRMOUT_BASE_UPDATE reloc\n");
2178                                 return -EINVAL;
2179                         }
2180
2181                         if (reloc->robj != track->vgt_strmout_bo[idx_value]) {
2182                                 DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo does not match\n");
2183                                 return -EINVAL;
2184                         }
2185
2186                         offset = radeon_get_ib_value(p, idx+1) << 8;
2187                         if (offset != track->vgt_strmout_bo_offset[idx_value]) {
2188                                 DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo offset does not match: 0x%llx, 0x%x\n",
2189                                           offset, track->vgt_strmout_bo_offset[idx_value]);
2190                                 return -EINVAL;
2191                         }
2192
2193                         if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2194                                 DRM_ERROR("bad STRMOUT_BASE_UPDATE bo too small: 0x%llx, 0x%lx\n",
2195                                           offset + 4, radeon_bo_size(reloc->robj));
2196                                 return -EINVAL;
2197                         }
2198                         ib[idx+1] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2199                 }
2200                 break;
2201         case PACKET3_SURFACE_BASE_UPDATE:
2202                 if (p->family >= CHIP_RV770 || p->family == CHIP_R600) {
2203                         DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
2204                         return -EINVAL;
2205                 }
2206                 if (pkt->count) {
2207                         DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
2208                         return -EINVAL;
2209                 }
2210                 break;
2211         case PACKET3_STRMOUT_BUFFER_UPDATE:
2212                 if (pkt->count != 4) {
2213                         DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (invalid count)\n");
2214                         return -EINVAL;
2215                 }
2216                 /* Updating memory at DST_ADDRESS. */
2217                 if (idx_value & 0x1) {
2218                         u64 offset;
2219                         r = r600_cs_packet_next_reloc(p, &reloc);
2220                         if (r) {
2221                                 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n");
2222                                 return -EINVAL;
2223                         }
2224                         offset = radeon_get_ib_value(p, idx+1);
2225                         offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2226                         if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2227                                 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE dst bo too small: 0x%llx, 0x%lx\n",
2228                                           offset + 4, radeon_bo_size(reloc->robj));
2229                                 return -EINVAL;
2230                         }
2231                         offset += reloc->lobj.gpu_offset;
2232                         ib[idx+1] = offset;
2233                         ib[idx+2] = upper_32_bits(offset) & 0xff;
2234                 }
2235                 /* Reading data from SRC_ADDRESS. */
2236                 if (((idx_value >> 1) & 0x3) == 2) {
2237                         u64 offset;
2238                         r = r600_cs_packet_next_reloc(p, &reloc);
2239                         if (r) {
2240                                 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n");
2241                                 return -EINVAL;
2242                         }
2243                         offset = radeon_get_ib_value(p, idx+3);
2244                         offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2245                         if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2246                                 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE src bo too small: 0x%llx, 0x%lx\n",
2247                                           offset + 4, radeon_bo_size(reloc->robj));
2248                                 return -EINVAL;
2249                         }
2250                         offset += reloc->lobj.gpu_offset;
2251                         ib[idx+3] = offset;
2252                         ib[idx+4] = upper_32_bits(offset) & 0xff;
2253                 }
2254                 break;
2255         case PACKET3_COPY_DW:
2256                 if (pkt->count != 4) {
2257                         DRM_ERROR("bad COPY_DW (invalid count)\n");
2258                         return -EINVAL;
2259                 }
2260                 if (idx_value & 0x1) {
2261                         u64 offset;
2262                         /* SRC is memory. */
2263                         r = r600_cs_packet_next_reloc(p, &reloc);
2264                         if (r) {
2265                                 DRM_ERROR("bad COPY_DW (missing src reloc)\n");
2266                                 return -EINVAL;
2267                         }
2268                         offset = radeon_get_ib_value(p, idx+1);
2269                         offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2270                         if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2271                                 DRM_ERROR("bad COPY_DW src bo too small: 0x%llx, 0x%lx\n",
2272                                           offset + 4, radeon_bo_size(reloc->robj));
2273                                 return -EINVAL;
2274                         }
2275                         offset += reloc->lobj.gpu_offset;
2276                         ib[idx+1] = offset;
2277                         ib[idx+2] = upper_32_bits(offset) & 0xff;
2278                 } else {
2279                         /* SRC is a reg. */
2280                         reg = radeon_get_ib_value(p, idx+1) << 2;
2281                         if (!r600_is_safe_reg(p, reg, idx+1))
2282                                 return -EINVAL;
2283                 }
2284                 if (idx_value & 0x2) {
2285                         u64 offset;
2286                         /* DST is memory. */
2287                         r = r600_cs_packet_next_reloc(p, &reloc);
2288                         if (r) {
2289                                 DRM_ERROR("bad COPY_DW (missing dst reloc)\n");
2290                                 return -EINVAL;
2291                         }
2292                         offset = radeon_get_ib_value(p, idx+3);
2293                         offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2294                         if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2295                                 DRM_ERROR("bad COPY_DW dst bo too small: 0x%llx, 0x%lx\n",
2296                                           offset + 4, radeon_bo_size(reloc->robj));
2297                                 return -EINVAL;
2298                         }
2299                         offset += reloc->lobj.gpu_offset;
2300                         ib[idx+3] = offset;
2301                         ib[idx+4] = upper_32_bits(offset) & 0xff;
2302                 } else {
2303                         /* DST is a reg. */
2304                         reg = radeon_get_ib_value(p, idx+3) << 2;
2305                         if (!r600_is_safe_reg(p, reg, idx+3))
2306                                 return -EINVAL;
2307                 }
2308                 break;
2309         case PACKET3_NOP:
2310                 break;
2311         default:
2312                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2313                 return -EINVAL;
2314         }
2315         return 0;
2316 }
2317
2318 int r600_cs_parse(struct radeon_cs_parser *p)
2319 {
2320         struct radeon_cs_packet pkt;
2321         struct r600_cs_track *track;
2322         int r;
2323
2324         if (p->track == NULL) {
2325                 /* initialize tracker, we are in kms */
2326                 track = kzalloc(sizeof(*track), GFP_KERNEL);
2327                 if (track == NULL)
2328                         return -ENOMEM;
2329                 r600_cs_track_init(track);
2330                 if (p->rdev->family < CHIP_RV770) {
2331                         track->npipes = p->rdev->config.r600.tiling_npipes;
2332                         track->nbanks = p->rdev->config.r600.tiling_nbanks;
2333                         track->group_size = p->rdev->config.r600.tiling_group_size;
2334                 } else if (p->rdev->family <= CHIP_RV740) {
2335                         track->npipes = p->rdev->config.rv770.tiling_npipes;
2336                         track->nbanks = p->rdev->config.rv770.tiling_nbanks;
2337                         track->group_size = p->rdev->config.rv770.tiling_group_size;
2338                 }
2339                 p->track = track;
2340         }
2341         do {
2342                 r = r600_cs_packet_parse(p, &pkt, p->idx);
2343                 if (r) {
2344                         kfree(p->track);
2345                         p->track = NULL;
2346                         return r;
2347                 }
2348                 p->idx += pkt.count + 2;
2349                 switch (pkt.type) {
2350                 case PACKET_TYPE0:
2351                         r = r600_cs_parse_packet0(p, &pkt);
2352                         break;
2353                 case PACKET_TYPE2:
2354                         break;
2355                 case PACKET_TYPE3:
2356                         r = r600_packet3_check(p, &pkt);
2357                         break;
2358                 default:
2359                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
2360                         kfree(p->track);
2361                         p->track = NULL;
2362                         return -EINVAL;
2363                 }
2364                 if (r) {
2365                         kfree(p->track);
2366                         p->track = NULL;
2367                         return r;
2368                 }
2369         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2370 #if 0
2371         for (r = 0; r < p->ib.length_dw; r++) {
2372                 printk(KERN_INFO "%05d  0x%08X\n", r, p->ib.ptr[r]);
2373                 mdelay(1);
2374         }
2375 #endif
2376         kfree(p->track);
2377         p->track = NULL;
2378         return 0;
2379 }
2380
2381 static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p)
2382 {
2383         if (p->chunk_relocs_idx == -1) {
2384                 return 0;
2385         }
2386         p->relocs = kzalloc(sizeof(struct radeon_cs_reloc), GFP_KERNEL);
2387         if (p->relocs == NULL) {
2388                 return -ENOMEM;
2389         }
2390         return 0;
2391 }
2392
2393 /**
2394  * cs_parser_fini() - clean parser states
2395  * @parser:     parser structure holding parsing context.
2396  * @error:      error number
2397  *
2398  * If error is set than unvalidate buffer, otherwise just free memory
2399  * used by parsing context.
2400  **/
2401 static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error)
2402 {
2403         unsigned i;
2404
2405         kfree(parser->relocs);
2406         for (i = 0; i < parser->nchunks; i++) {
2407                 kfree(parser->chunks[i].kdata);
2408                 kfree(parser->chunks[i].kpage[0]);
2409                 kfree(parser->chunks[i].kpage[1]);
2410         }
2411         kfree(parser->chunks);
2412         kfree(parser->chunks_array);
2413 }
2414
2415 int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
2416                         unsigned family, u32 *ib, int *l)
2417 {
2418         struct radeon_cs_parser parser;
2419         struct radeon_cs_chunk *ib_chunk;
2420         struct r600_cs_track *track;
2421         int r;
2422
2423         /* initialize tracker */
2424         track = kzalloc(sizeof(*track), GFP_KERNEL);
2425         if (track == NULL)
2426                 return -ENOMEM;
2427         r600_cs_track_init(track);
2428         r600_cs_legacy_get_tiling_conf(dev, &track->npipes, &track->nbanks, &track->group_size);
2429         /* initialize parser */
2430         memset(&parser, 0, sizeof(struct radeon_cs_parser));
2431         parser.filp = filp;
2432         parser.dev = &dev->pdev->dev;
2433         parser.rdev = NULL;
2434         parser.family = family;
2435         parser.track = track;
2436         parser.ib.ptr = ib;
2437         r = radeon_cs_parser_init(&parser, data);
2438         if (r) {
2439                 DRM_ERROR("Failed to initialize parser !\n");
2440                 r600_cs_parser_fini(&parser, r);
2441                 return r;
2442         }
2443         r = r600_cs_parser_relocs_legacy(&parser);
2444         if (r) {
2445                 DRM_ERROR("Failed to parse relocation !\n");
2446                 r600_cs_parser_fini(&parser, r);
2447                 return r;
2448         }
2449         /* Copy the packet into the IB, the parser will read from the
2450          * input memory (cached) and write to the IB (which can be
2451          * uncached). */
2452         ib_chunk = &parser.chunks[parser.chunk_ib_idx];
2453         parser.ib.length_dw = ib_chunk->length_dw;
2454         *l = parser.ib.length_dw;
2455         r = r600_cs_parse(&parser);
2456         if (r) {
2457                 DRM_ERROR("Invalid command stream !\n");
2458                 r600_cs_parser_fini(&parser, r);
2459                 return r;
2460         }
2461         r = radeon_cs_finish_pages(&parser);
2462         if (r) {
2463                 DRM_ERROR("Invalid command stream !\n");
2464                 r600_cs_parser_fini(&parser, r);
2465                 return r;
2466         }
2467         r600_cs_parser_fini(&parser, r);
2468         return r;
2469 }
2470
2471 void r600_cs_legacy_init(void)
2472 {
2473         r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_nomm;
2474 }