drm/radeon/r600: fix warnings in CS checker
[linux-3.10.git] / drivers / gpu / drm / radeon / r600_cs.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include "drmP.h"
29 #include "radeon.h"
30 #include "r600d.h"
31 #include "r600_reg_safe.h"
32
33 static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
34                                         struct radeon_cs_reloc **cs_reloc);
35 static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
36                                         struct radeon_cs_reloc **cs_reloc);
37 typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**);
38 static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm;
39 extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size);
40
41
42 struct r600_cs_track {
43         /* configuration we miror so that we use same code btw kms/ums */
44         u32                     group_size;
45         u32                     nbanks;
46         u32                     npipes;
47         /* value we track */
48         u32                     nsamples;
49         u32                     cb_color_base_last[8];
50         struct radeon_bo        *cb_color_bo[8];
51         u32                     cb_color_bo_offset[8];
52         struct radeon_bo        *cb_color_frag_bo[8];
53         struct radeon_bo        *cb_color_tile_bo[8];
54         u32                     cb_color_info[8];
55         u32                     cb_color_size_idx[8];
56         u32                     cb_target_mask;
57         u32                     cb_shader_mask;
58         u32                     cb_color_size[8];
59         u32                     vgt_strmout_en;
60         u32                     vgt_strmout_buffer_en;
61         u32                     db_depth_control;
62         u32                     db_depth_info;
63         u32                     db_depth_size_idx;
64         u32                     db_depth_view;
65         u32                     db_depth_size;
66         u32                     db_offset;
67         struct radeon_bo        *db_bo;
68 };
69
70 static inline int r600_bpe_from_format(u32 *bpe, u32 format)
71 {
72         switch (format) {
73         case V_038004_COLOR_8:
74         case V_038004_COLOR_4_4:
75         case V_038004_COLOR_3_3_2:
76         case V_038004_FMT_1:
77                 *bpe = 1;
78                 break;
79         case V_038004_COLOR_16:
80         case V_038004_COLOR_16_FLOAT:
81         case V_038004_COLOR_8_8:
82         case V_038004_COLOR_5_6_5:
83         case V_038004_COLOR_6_5_5:
84         case V_038004_COLOR_1_5_5_5:
85         case V_038004_COLOR_4_4_4_4:
86         case V_038004_COLOR_5_5_5_1:
87                 *bpe = 2;
88                 break;
89         case V_038004_FMT_8_8_8:
90                 *bpe = 3;
91                 break;
92         case V_038004_COLOR_32:
93         case V_038004_COLOR_32_FLOAT:
94         case V_038004_COLOR_16_16:
95         case V_038004_COLOR_16_16_FLOAT:
96         case V_038004_COLOR_8_24:
97         case V_038004_COLOR_8_24_FLOAT:
98         case V_038004_COLOR_24_8:
99         case V_038004_COLOR_24_8_FLOAT:
100         case V_038004_COLOR_10_11_11:
101         case V_038004_COLOR_10_11_11_FLOAT:
102         case V_038004_COLOR_11_11_10:
103         case V_038004_COLOR_11_11_10_FLOAT:
104         case V_038004_COLOR_2_10_10_10:
105         case V_038004_COLOR_8_8_8_8:
106         case V_038004_COLOR_10_10_10_2:
107         case V_038004_FMT_5_9_9_9_SHAREDEXP:
108         case V_038004_FMT_32_AS_8:
109         case V_038004_FMT_32_AS_8_8:
110                 *bpe = 4;
111                 break;
112         case V_038004_COLOR_X24_8_32_FLOAT:
113         case V_038004_COLOR_32_32:
114         case V_038004_COLOR_32_32_FLOAT:
115         case V_038004_COLOR_16_16_16_16:
116         case V_038004_COLOR_16_16_16_16_FLOAT:
117                 *bpe = 8;
118                 break;
119         case V_038004_FMT_16_16_16:
120         case V_038004_FMT_16_16_16_FLOAT:
121                 *bpe = 6;
122                 break;
123         case V_038004_FMT_32_32_32:
124         case V_038004_FMT_32_32_32_FLOAT:
125                 *bpe = 12;
126                 break;
127         case V_038004_COLOR_32_32_32_32:
128         case V_038004_COLOR_32_32_32_32_FLOAT:
129                 *bpe = 16;
130                 break;
131         case V_038004_FMT_GB_GR:
132         case V_038004_FMT_BG_RG:
133         case V_038004_COLOR_INVALID:
134                 *bpe = 16;
135                 return -EINVAL;
136         }
137         return 0;
138 }
139
140 static void r600_cs_track_init(struct r600_cs_track *track)
141 {
142         int i;
143
144         for (i = 0; i < 8; i++) {
145                 track->cb_color_base_last[i] = 0;
146                 track->cb_color_size[i] = 0;
147                 track->cb_color_size_idx[i] = 0;
148                 track->cb_color_info[i] = 0;
149                 track->cb_color_bo[i] = NULL;
150                 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
151         }
152         track->cb_target_mask = 0xFFFFFFFF;
153         track->cb_shader_mask = 0xFFFFFFFF;
154         track->db_bo = NULL;
155         /* assume the biggest format and that htile is enabled */
156         track->db_depth_info = 7 | (1 << 25);
157         track->db_depth_view = 0xFFFFC000;
158         track->db_depth_size = 0xFFFFFFFF;
159         track->db_depth_size_idx = 0;
160         track->db_depth_control = 0xFFFFFFFF;
161 }
162
163 static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
164 {
165         struct r600_cs_track *track = p->track;
166         u32 bpe = 0, pitch, slice_tile_max, size, tmp, height;
167         volatile u32 *ib = p->ib->ptr;
168
169         if (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
170                 dev_warn(p->dev, "FMASK or CMASK buffer are not supported by this kernel\n");
171                 return -EINVAL;
172         }
173         size = radeon_bo_size(track->cb_color_bo[i]);
174         if (r600_bpe_from_format(&bpe, G_0280A0_FORMAT(track->cb_color_info[i]))) {
175                 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n",
176                          __func__, __LINE__, G_0280A0_FORMAT(track->cb_color_info[i]),
177                         i, track->cb_color_info[i]);
178                 return -EINVAL;
179         }
180         pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) << 3;
181         slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1;
182         if (!pitch) {
183                 dev_warn(p->dev, "%s:%d cb pitch (%d) for %d invalid (0x%08X)\n",
184                         __func__, __LINE__, pitch, i, track->cb_color_size[i]);
185                 return -EINVAL;
186         }
187         height = size / (pitch * bpe);
188         if (height > 8192)
189                 height = 8192;
190         switch (G_0280A0_ARRAY_MODE(track->cb_color_info[i])) {
191         case V_0280A0_ARRAY_LINEAR_GENERAL:
192         case V_0280A0_ARRAY_LINEAR_ALIGNED:
193                 if (pitch & 0x3f) {
194                         dev_warn(p->dev, "%s:%d cb pitch (%d x %d = %d) invalid\n",
195                                 __func__, __LINE__, pitch, bpe, pitch * bpe);
196                         return -EINVAL;
197                 }
198                 if ((pitch * bpe) & (track->group_size - 1)) {
199                         dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
200                                 __func__, __LINE__, pitch);
201                         return -EINVAL;
202                 }
203                 break;
204         case V_0280A0_ARRAY_1D_TILED_THIN1:
205                 if ((pitch * 8 * bpe * track->nsamples) & (track->group_size - 1)) {
206                         dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
207                                 __func__, __LINE__, pitch);
208                         return -EINVAL;
209                 }
210                 height &= ~0x7;
211                 if (!height)
212                         height = 8;
213                 break;
214         case V_0280A0_ARRAY_2D_TILED_THIN1:
215                 if (pitch & ((8 * track->nbanks) - 1)) {
216                         dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
217                                 __func__, __LINE__, pitch);
218                         return -EINVAL;
219                 }
220                 tmp = pitch * 8 * bpe * track->nsamples;
221                 tmp = tmp / track->nbanks;
222                 if (tmp & (track->group_size - 1)) {
223                         dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
224                                 __func__, __LINE__, pitch);
225                         return -EINVAL;
226                 }
227                 height &= ~((16 * track->npipes) - 1);
228                 if (!height)
229                         height = 16 * track->npipes;
230                 break;
231         default:
232                 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
233                         G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
234                         track->cb_color_info[i]);
235                 return -EINVAL;
236         }
237         /* check offset */
238         tmp = height * pitch;
239         if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
240                 dev_warn(p->dev, "%s offset[%d] %d to big\n", __func__, i, track->cb_color_bo_offset[i]);
241                 return -EINVAL;
242         }
243         /* limit max tile */
244         tmp = (height * pitch) >> 6;
245         if (tmp < slice_tile_max)
246                 slice_tile_max = tmp;
247         tmp = S_028060_PITCH_TILE_MAX((pitch >> 3) - 1) |
248                 S_028060_SLICE_TILE_MAX(slice_tile_max - 1);
249         ib[track->cb_color_size_idx[i]] = tmp;
250         return 0;
251 }
252
253 static int r600_cs_track_check(struct radeon_cs_parser *p)
254 {
255         struct r600_cs_track *track = p->track;
256         u32 tmp;
257         int r, i;
258         volatile u32 *ib = p->ib->ptr;
259
260         /* on legacy kernel we don't perform advanced check */
261         if (p->rdev == NULL)
262                 return 0;
263         /* we don't support out buffer yet */
264         if (track->vgt_strmout_en || track->vgt_strmout_buffer_en) {
265                 dev_warn(p->dev, "this kernel doesn't support SMX output buffer\n");
266                 return -EINVAL;
267         }
268         /* check that we have a cb for each enabled target, we don't check
269          * shader_mask because it seems mesa isn't always setting it :(
270          */
271         tmp = track->cb_target_mask;
272         for (i = 0; i < 8; i++) {
273                 if ((tmp >> (i * 4)) & 0xF) {
274                         /* at least one component is enabled */
275                         if (track->cb_color_bo[i] == NULL) {
276                                 dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
277                                         __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
278                                 return -EINVAL;
279                         }
280                         /* perform rewrite of CB_COLOR[0-7]_SIZE */
281                         r = r600_cs_track_validate_cb(p, i);
282                         if (r)
283                                 return r;
284                 }
285         }
286         /* Check depth buffer */
287         if (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
288                 G_028800_Z_ENABLE(track->db_depth_control)) {
289                 u32 nviews, bpe, ntiles;
290                 if (track->db_bo == NULL) {
291                         dev_warn(p->dev, "z/stencil with no depth buffer\n");
292                         return -EINVAL;
293                 }
294                 if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) {
295                         dev_warn(p->dev, "this kernel doesn't support z/stencil htile\n");
296                         return -EINVAL;
297                 }
298                 switch (G_028010_FORMAT(track->db_depth_info)) {
299                 case V_028010_DEPTH_16:
300                         bpe = 2;
301                         break;
302                 case V_028010_DEPTH_X8_24:
303                 case V_028010_DEPTH_8_24:
304                 case V_028010_DEPTH_X8_24_FLOAT:
305                 case V_028010_DEPTH_8_24_FLOAT:
306                 case V_028010_DEPTH_32_FLOAT:
307                         bpe = 4;
308                         break;
309                 case V_028010_DEPTH_X24_8_32_FLOAT:
310                         bpe = 8;
311                         break;
312                 default:
313                         dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info));
314                         return -EINVAL;
315                 }
316                 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
317                         if (!track->db_depth_size_idx) {
318                                 dev_warn(p->dev, "z/stencil buffer size not set\n");
319                                 return -EINVAL;
320                         }
321                         printk_once(KERN_WARNING "You have old & broken userspace please consider updating mesa\n");
322                         tmp = radeon_bo_size(track->db_bo) - track->db_offset;
323                         tmp = (tmp / bpe) >> 6;
324                         if (!tmp) {
325                                 dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n",
326                                                 track->db_depth_size, bpe, track->db_offset,
327                                                 radeon_bo_size(track->db_bo));
328                                 return -EINVAL;
329                         }
330                         ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
331                 } else {
332                         ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
333                         nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
334                         tmp = ntiles * bpe * 64 * nviews;
335                         if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
336                                 dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %d -> %d have %ld)\n",
337                                                 track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
338                                                 radeon_bo_size(track->db_bo));
339                                 return -EINVAL;
340                         }
341                 }
342         }
343         return 0;
344 }
345
346 /**
347  * r600_cs_packet_parse() - parse cp packet and point ib index to next packet
348  * @parser:     parser structure holding parsing context.
349  * @pkt:        where to store packet informations
350  *
351  * Assume that chunk_ib_index is properly set. Will return -EINVAL
352  * if packet is bigger than remaining ib size. or if packets is unknown.
353  **/
354 int r600_cs_packet_parse(struct radeon_cs_parser *p,
355                         struct radeon_cs_packet *pkt,
356                         unsigned idx)
357 {
358         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
359         uint32_t header;
360
361         if (idx >= ib_chunk->length_dw) {
362                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
363                           idx, ib_chunk->length_dw);
364                 return -EINVAL;
365         }
366         header = radeon_get_ib_value(p, idx);
367         pkt->idx = idx;
368         pkt->type = CP_PACKET_GET_TYPE(header);
369         pkt->count = CP_PACKET_GET_COUNT(header);
370         pkt->one_reg_wr = 0;
371         switch (pkt->type) {
372         case PACKET_TYPE0:
373                 pkt->reg = CP_PACKET0_GET_REG(header);
374                 break;
375         case PACKET_TYPE3:
376                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
377                 break;
378         case PACKET_TYPE2:
379                 pkt->count = -1;
380                 break;
381         default:
382                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
383                 return -EINVAL;
384         }
385         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
386                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
387                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
388                 return -EINVAL;
389         }
390         return 0;
391 }
392
393 /**
394  * r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3
395  * @parser:             parser structure holding parsing context.
396  * @data:               pointer to relocation data
397  * @offset_start:       starting offset
398  * @offset_mask:        offset mask (to align start offset on)
399  * @reloc:              reloc informations
400  *
401  * Check next packet is relocation packet3, do bo validation and compute
402  * GPU offset using the provided start.
403  **/
404 static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
405                                         struct radeon_cs_reloc **cs_reloc)
406 {
407         struct radeon_cs_chunk *relocs_chunk;
408         struct radeon_cs_packet p3reloc;
409         unsigned idx;
410         int r;
411
412         if (p->chunk_relocs_idx == -1) {
413                 DRM_ERROR("No relocation chunk !\n");
414                 return -EINVAL;
415         }
416         *cs_reloc = NULL;
417         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
418         r = r600_cs_packet_parse(p, &p3reloc, p->idx);
419         if (r) {
420                 return r;
421         }
422         p->idx += p3reloc.count + 2;
423         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
424                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
425                           p3reloc.idx);
426                 return -EINVAL;
427         }
428         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
429         if (idx >= relocs_chunk->length_dw) {
430                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
431                           idx, relocs_chunk->length_dw);
432                 return -EINVAL;
433         }
434         /* FIXME: we assume reloc size is 4 dwords */
435         *cs_reloc = p->relocs_ptr[(idx / 4)];
436         return 0;
437 }
438
439 /**
440  * r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3
441  * @parser:             parser structure holding parsing context.
442  * @data:               pointer to relocation data
443  * @offset_start:       starting offset
444  * @offset_mask:        offset mask (to align start offset on)
445  * @reloc:              reloc informations
446  *
447  * Check next packet is relocation packet3, do bo validation and compute
448  * GPU offset using the provided start.
449  **/
450 static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
451                                         struct radeon_cs_reloc **cs_reloc)
452 {
453         struct radeon_cs_chunk *relocs_chunk;
454         struct radeon_cs_packet p3reloc;
455         unsigned idx;
456         int r;
457
458         if (p->chunk_relocs_idx == -1) {
459                 DRM_ERROR("No relocation chunk !\n");
460                 return -EINVAL;
461         }
462         *cs_reloc = NULL;
463         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
464         r = r600_cs_packet_parse(p, &p3reloc, p->idx);
465         if (r) {
466                 return r;
467         }
468         p->idx += p3reloc.count + 2;
469         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
470                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
471                           p3reloc.idx);
472                 return -EINVAL;
473         }
474         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
475         if (idx >= relocs_chunk->length_dw) {
476                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
477                           idx, relocs_chunk->length_dw);
478                 return -EINVAL;
479         }
480         *cs_reloc = p->relocs;
481         (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32;
482         (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
483         return 0;
484 }
485
486 /**
487  * r600_cs_packet_next_is_pkt3_nop() - test if next packet is packet3 nop for reloc
488  * @parser:             parser structure holding parsing context.
489  *
490  * Check next packet is relocation packet3, do bo validation and compute
491  * GPU offset using the provided start.
492  **/
493 static inline int r600_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
494 {
495         struct radeon_cs_packet p3reloc;
496         int r;
497
498         r = r600_cs_packet_parse(p, &p3reloc, p->idx);
499         if (r) {
500                 return 0;
501         }
502         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
503                 return 0;
504         }
505         return 1;
506 }
507
508 /**
509  * r600_cs_packet_next_vline() - parse userspace VLINE packet
510  * @parser:             parser structure holding parsing context.
511  *
512  * Userspace sends a special sequence for VLINE waits.
513  * PACKET0 - VLINE_START_END + value
514  * PACKET3 - WAIT_REG_MEM poll vline status reg
515  * RELOC (P3) - crtc_id in reloc.
516  *
517  * This function parses this and relocates the VLINE START END
518  * and WAIT_REG_MEM packets to the correct crtc.
519  * It also detects a switched off crtc and nulls out the
520  * wait in that case.
521  */
522 static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
523 {
524         struct drm_mode_object *obj;
525         struct drm_crtc *crtc;
526         struct radeon_crtc *radeon_crtc;
527         struct radeon_cs_packet p3reloc, wait_reg_mem;
528         int crtc_id;
529         int r;
530         uint32_t header, h_idx, reg, wait_reg_mem_info;
531         volatile uint32_t *ib;
532
533         ib = p->ib->ptr;
534
535         /* parse the WAIT_REG_MEM */
536         r = r600_cs_packet_parse(p, &wait_reg_mem, p->idx);
537         if (r)
538                 return r;
539
540         /* check its a WAIT_REG_MEM */
541         if (wait_reg_mem.type != PACKET_TYPE3 ||
542             wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
543                 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
544                 r = -EINVAL;
545                 return r;
546         }
547
548         wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
549         /* bit 4 is reg (0) or mem (1) */
550         if (wait_reg_mem_info & 0x10) {
551                 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n");
552                 r = -EINVAL;
553                 return r;
554         }
555         /* waiting for value to be equal */
556         if ((wait_reg_mem_info & 0x7) != 0x3) {
557                 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
558                 r = -EINVAL;
559                 return r;
560         }
561         if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != AVIVO_D1MODE_VLINE_STATUS) {
562                 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
563                 r = -EINVAL;
564                 return r;
565         }
566
567         if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != AVIVO_D1MODE_VLINE_STAT) {
568                 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
569                 r = -EINVAL;
570                 return r;
571         }
572
573         /* jump over the NOP */
574         r = r600_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);
575         if (r)
576                 return r;
577
578         h_idx = p->idx - 2;
579         p->idx += wait_reg_mem.count + 2;
580         p->idx += p3reloc.count + 2;
581
582         header = radeon_get_ib_value(p, h_idx);
583         crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
584         reg = CP_PACKET0_GET_REG(header);
585         mutex_lock(&p->rdev->ddev->mode_config.mutex);
586         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
587         if (!obj) {
588                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
589                 r = -EINVAL;
590                 goto out;
591         }
592         crtc = obj_to_crtc(obj);
593         radeon_crtc = to_radeon_crtc(crtc);
594         crtc_id = radeon_crtc->crtc_id;
595
596         if (!crtc->enabled) {
597                 /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
598                 ib[h_idx + 2] = PACKET2(0);
599                 ib[h_idx + 3] = PACKET2(0);
600                 ib[h_idx + 4] = PACKET2(0);
601                 ib[h_idx + 5] = PACKET2(0);
602                 ib[h_idx + 6] = PACKET2(0);
603                 ib[h_idx + 7] = PACKET2(0);
604                 ib[h_idx + 8] = PACKET2(0);
605         } else if (crtc_id == 1) {
606                 switch (reg) {
607                 case AVIVO_D1MODE_VLINE_START_END:
608                         header &= ~R600_CP_PACKET0_REG_MASK;
609                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
610                         break;
611                 default:
612                         DRM_ERROR("unknown crtc reloc\n");
613                         r = -EINVAL;
614                         goto out;
615                 }
616                 ib[h_idx] = header;
617                 ib[h_idx + 4] = AVIVO_D2MODE_VLINE_STATUS >> 2;
618         }
619 out:
620         mutex_unlock(&p->rdev->ddev->mode_config.mutex);
621         return r;
622 }
623
624 static int r600_packet0_check(struct radeon_cs_parser *p,
625                                 struct radeon_cs_packet *pkt,
626                                 unsigned idx, unsigned reg)
627 {
628         int r;
629
630         switch (reg) {
631         case AVIVO_D1MODE_VLINE_START_END:
632                 r = r600_cs_packet_parse_vline(p);
633                 if (r) {
634                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
635                                         idx, reg);
636                         return r;
637                 }
638                 break;
639         default:
640                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
641                        reg, idx);
642                 return -EINVAL;
643         }
644         return 0;
645 }
646
647 static int r600_cs_parse_packet0(struct radeon_cs_parser *p,
648                                 struct radeon_cs_packet *pkt)
649 {
650         unsigned reg, i;
651         unsigned idx;
652         int r;
653
654         idx = pkt->idx + 1;
655         reg = pkt->reg;
656         for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
657                 r = r600_packet0_check(p, pkt, idx, reg);
658                 if (r) {
659                         return r;
660                 }
661         }
662         return 0;
663 }
664
665 /**
666  * r600_cs_check_reg() - check if register is authorized or not
667  * @parser: parser structure holding parsing context
668  * @reg: register we are testing
669  * @idx: index into the cs buffer
670  *
671  * This function will test against r600_reg_safe_bm and return 0
672  * if register is safe. If register is not flag as safe this function
673  * will test it against a list of register needind special handling.
674  */
675 static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
676 {
677         struct r600_cs_track *track = (struct r600_cs_track *)p->track;
678         struct radeon_cs_reloc *reloc;
679         u32 last_reg = ARRAY_SIZE(r600_reg_safe_bm);
680         u32 m, i, tmp, *ib;
681         int r;
682
683         i = (reg >> 7);
684         if (i > last_reg) {
685                 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
686                 return -EINVAL;
687         }
688         m = 1 << ((reg >> 2) & 31);
689         if (!(r600_reg_safe_bm[i] & m))
690                 return 0;
691         ib = p->ib->ptr;
692         switch (reg) {
693         /* force following reg to 0 in an attemp to disable out buffer
694          * which will need us to better understand how it works to perform
695          * security check on it (Jerome)
696          */
697         case R_0288A8_SQ_ESGS_RING_ITEMSIZE:
698         case R_008C44_SQ_ESGS_RING_SIZE:
699         case R_0288B0_SQ_ESTMP_RING_ITEMSIZE:
700         case R_008C54_SQ_ESTMP_RING_SIZE:
701         case R_0288C0_SQ_FBUF_RING_ITEMSIZE:
702         case R_008C74_SQ_FBUF_RING_SIZE:
703         case R_0288B4_SQ_GSTMP_RING_ITEMSIZE:
704         case R_008C5C_SQ_GSTMP_RING_SIZE:
705         case R_0288AC_SQ_GSVS_RING_ITEMSIZE:
706         case R_008C4C_SQ_GSVS_RING_SIZE:
707         case R_0288BC_SQ_PSTMP_RING_ITEMSIZE:
708         case R_008C6C_SQ_PSTMP_RING_SIZE:
709         case R_0288C4_SQ_REDUC_RING_ITEMSIZE:
710         case R_008C7C_SQ_REDUC_RING_SIZE:
711         case R_0288B8_SQ_VSTMP_RING_ITEMSIZE:
712         case R_008C64_SQ_VSTMP_RING_SIZE:
713         case R_0288C8_SQ_GS_VERT_ITEMSIZE:
714                 /* get value to populate the IB don't remove */
715                 tmp =radeon_get_ib_value(p, idx);
716                 ib[idx] = 0;
717                 break;
718         case R_028800_DB_DEPTH_CONTROL:
719                 track->db_depth_control = radeon_get_ib_value(p, idx);
720                 break;
721         case R_028010_DB_DEPTH_INFO:
722                 track->db_depth_info = radeon_get_ib_value(p, idx);
723                 break;
724         case R_028004_DB_DEPTH_VIEW:
725                 track->db_depth_view = radeon_get_ib_value(p, idx);
726                 break;
727         case R_028000_DB_DEPTH_SIZE:
728                 track->db_depth_size = radeon_get_ib_value(p, idx);
729                 track->db_depth_size_idx = idx;
730                 break;
731         case R_028AB0_VGT_STRMOUT_EN:
732                 track->vgt_strmout_en = radeon_get_ib_value(p, idx);
733                 break;
734         case R_028B20_VGT_STRMOUT_BUFFER_EN:
735                 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx);
736                 break;
737         case R_028238_CB_TARGET_MASK:
738                 track->cb_target_mask = radeon_get_ib_value(p, idx);
739                 break;
740         case R_02823C_CB_SHADER_MASK:
741                 track->cb_shader_mask = radeon_get_ib_value(p, idx);
742                 break;
743         case R_028C04_PA_SC_AA_CONFIG:
744                 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));
745                 track->nsamples = 1 << tmp;
746                 break;
747         case R_0280A0_CB_COLOR0_INFO:
748         case R_0280A4_CB_COLOR1_INFO:
749         case R_0280A8_CB_COLOR2_INFO:
750         case R_0280AC_CB_COLOR3_INFO:
751         case R_0280B0_CB_COLOR4_INFO:
752         case R_0280B4_CB_COLOR5_INFO:
753         case R_0280B8_CB_COLOR6_INFO:
754         case R_0280BC_CB_COLOR7_INFO:
755                 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
756                 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
757                 break;
758         case R_028060_CB_COLOR0_SIZE:
759         case R_028064_CB_COLOR1_SIZE:
760         case R_028068_CB_COLOR2_SIZE:
761         case R_02806C_CB_COLOR3_SIZE:
762         case R_028070_CB_COLOR4_SIZE:
763         case R_028074_CB_COLOR5_SIZE:
764         case R_028078_CB_COLOR6_SIZE:
765         case R_02807C_CB_COLOR7_SIZE:
766                 tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4;
767                 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx);
768                 track->cb_color_size_idx[tmp] = idx;
769                 break;
770                 /* This register were added late, there is userspace
771                  * which does provide relocation for those but set
772                  * 0 offset. In order to avoid breaking old userspace
773                  * we detect this and set address to point to last
774                  * CB_COLOR0_BASE, note that if userspace doesn't set
775                  * CB_COLOR0_BASE before this register we will report
776                  * error. Old userspace always set CB_COLOR0_BASE
777                  * before any of this.
778                  */
779         case R_0280E0_CB_COLOR0_FRAG:
780         case R_0280E4_CB_COLOR1_FRAG:
781         case R_0280E8_CB_COLOR2_FRAG:
782         case R_0280EC_CB_COLOR3_FRAG:
783         case R_0280F0_CB_COLOR4_FRAG:
784         case R_0280F4_CB_COLOR5_FRAG:
785         case R_0280F8_CB_COLOR6_FRAG:
786         case R_0280FC_CB_COLOR7_FRAG:
787                 tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4;
788                 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
789                         if (!track->cb_color_base_last[tmp]) {
790                                 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
791                                 return -EINVAL;
792                         }
793                         ib[idx] = track->cb_color_base_last[tmp];
794                         printk_once(KERN_WARNING "You have old & broken userspace "
795                                         "please consider updating mesa & xf86-video-ati\n");
796                         track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];
797                 } else {
798                         r = r600_cs_packet_next_reloc(p, &reloc);
799                         if (r) {
800                                 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
801                                 return -EINVAL;
802                         }
803                         ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
804                         track->cb_color_frag_bo[tmp] = reloc->robj;
805                 }
806                 break;
807         case R_0280C0_CB_COLOR0_TILE:
808         case R_0280C4_CB_COLOR1_TILE:
809         case R_0280C8_CB_COLOR2_TILE:
810         case R_0280CC_CB_COLOR3_TILE:
811         case R_0280D0_CB_COLOR4_TILE:
812         case R_0280D4_CB_COLOR5_TILE:
813         case R_0280D8_CB_COLOR6_TILE:
814         case R_0280DC_CB_COLOR7_TILE:
815                 tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4;
816                 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
817                         if (!track->cb_color_base_last[tmp]) {
818                                 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
819                                 return -EINVAL;
820                         }
821                         ib[idx] = track->cb_color_base_last[tmp];
822                         printk_once(KERN_WARNING "You have old & broken userspace "
823                                         "please consider updating mesa & xf86-video-ati\n");
824                         track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];
825                 } else {
826                         r = r600_cs_packet_next_reloc(p, &reloc);
827                         if (r) {
828                                 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
829                                 return -EINVAL;
830                         }
831                         ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
832                         track->cb_color_tile_bo[tmp] = reloc->robj;
833                 }
834                 break;
835         case CB_COLOR0_BASE:
836         case CB_COLOR1_BASE:
837         case CB_COLOR2_BASE:
838         case CB_COLOR3_BASE:
839         case CB_COLOR4_BASE:
840         case CB_COLOR5_BASE:
841         case CB_COLOR6_BASE:
842         case CB_COLOR7_BASE:
843                 r = r600_cs_packet_next_reloc(p, &reloc);
844                 if (r) {
845                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
846                                         "0x%04X\n", reg);
847                         return -EINVAL;
848                 }
849                 tmp = (reg - CB_COLOR0_BASE) / 4;
850                 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
851                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
852                 track->cb_color_base_last[tmp] = ib[idx];
853                 track->cb_color_bo[tmp] = reloc->robj;
854                 break;
855         case DB_DEPTH_BASE:
856                 r = r600_cs_packet_next_reloc(p, &reloc);
857                 if (r) {
858                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
859                                         "0x%04X\n", reg);
860                         return -EINVAL;
861                 }
862                 track->db_offset = radeon_get_ib_value(p, idx);
863                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
864                 track->db_bo = reloc->robj;
865                 break;
866         case DB_HTILE_DATA_BASE:
867         case SQ_PGM_START_FS:
868         case SQ_PGM_START_ES:
869         case SQ_PGM_START_VS:
870         case SQ_PGM_START_GS:
871         case SQ_PGM_START_PS:
872                 r = r600_cs_packet_next_reloc(p, &reloc);
873                 if (r) {
874                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
875                                         "0x%04X\n", reg);
876                         return -EINVAL;
877                 }
878                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
879                 break;
880         default:
881                 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
882                 return -EINVAL;
883         }
884         return 0;
885 }
886
887 static inline unsigned minify(unsigned size, unsigned levels)
888 {
889         size = size >> levels;
890         if (size < 1)
891                 size = 1;
892         return size;
893 }
894
895 static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned nlevels,
896                                 unsigned w0, unsigned h0, unsigned d0, unsigned bpe,
897                                 unsigned *l0_size, unsigned *mipmap_size)
898 {
899         unsigned offset, i, level, face;
900         unsigned width, height, depth, rowstride, size;
901
902         w0 = minify(w0, 0);
903         h0 = minify(h0, 0);
904         d0 = minify(d0, 0);
905         for(i = 0, offset = 0, level = blevel; i < nlevels; i++, level++) {
906                 width = minify(w0, i);
907                 height = minify(h0, i);
908                 depth = minify(d0, i);
909                 for(face = 0; face < nfaces; face++) {
910                         rowstride = ((width * bpe) + 255) & ~255;
911                         size = height * rowstride * depth;
912                         offset += size;
913                         offset = (offset + 0x1f) & ~0x1f;
914                 }
915         }
916         *l0_size = (((w0 * bpe) + 255) & ~255) * h0 * d0;
917         *mipmap_size = offset;
918         if (!blevel)
919                 *mipmap_size -= *l0_size;
920         if (!nlevels)
921                 *mipmap_size = *l0_size;
922 }
923
924 /**
925  * r600_check_texture_resource() - check if register is authorized or not
926  * @p: parser structure holding parsing context
927  * @idx: index into the cs buffer
928  * @texture: texture's bo structure
929  * @mipmap: mipmap's bo structure
930  *
931  * This function will check that the resource has valid field and that
932  * the texture and mipmap bo object are big enough to cover this resource.
933  */
934 static inline int r600_check_texture_resource(struct radeon_cs_parser *p,  u32 idx,
935                                                 struct radeon_bo *texture,
936                                                 struct radeon_bo *mipmap)
937 {
938         u32 nfaces, nlevels, blevel, w0, h0, d0, bpe = 0;
939         u32 word0, word1, l0_size, mipmap_size;
940
941         /* on legacy kernel we don't perform advanced check */
942         if (p->rdev == NULL)
943                 return 0;
944         word0 = radeon_get_ib_value(p, idx + 0);
945         word1 = radeon_get_ib_value(p, idx + 1);
946         w0 = G_038000_TEX_WIDTH(word0) + 1;
947         h0 = G_038004_TEX_HEIGHT(word1) + 1;
948         d0 = G_038004_TEX_DEPTH(word1);
949         nfaces = 1;
950         switch (G_038000_DIM(word0)) {
951         case V_038000_SQ_TEX_DIM_1D:
952         case V_038000_SQ_TEX_DIM_2D:
953         case V_038000_SQ_TEX_DIM_3D:
954                 break;
955         case V_038000_SQ_TEX_DIM_CUBEMAP:
956                 nfaces = 6;
957                 break;
958         case V_038000_SQ_TEX_DIM_1D_ARRAY:
959         case V_038000_SQ_TEX_DIM_2D_ARRAY:
960         case V_038000_SQ_TEX_DIM_2D_MSAA:
961         case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA:
962         default:
963                 dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0));
964                 return -EINVAL;
965         }
966         if (r600_bpe_from_format(&bpe,  G_038004_DATA_FORMAT(word1))) {
967                 dev_warn(p->dev, "%s:%d texture invalid format %d\n",
968                          __func__, __LINE__, G_038004_DATA_FORMAT(word1));
969                 return -EINVAL;
970         }
971         word0 = radeon_get_ib_value(p, idx + 4);
972         word1 = radeon_get_ib_value(p, idx + 5);
973         blevel = G_038010_BASE_LEVEL(word0);
974         nlevels = G_038014_LAST_LEVEL(word1);
975         r600_texture_size(nfaces, blevel, nlevels, w0, h0, d0, bpe, &l0_size, &mipmap_size);
976         /* using get ib will give us the offset into the texture bo */
977         word0 = radeon_get_ib_value(p, idx + 2);
978         if ((l0_size + word0) > radeon_bo_size(texture)) {
979                 dev_warn(p->dev, "texture bo too small (%d %d %d %d -> %d have %ld)\n",
980                         w0, h0, bpe, word0, l0_size, radeon_bo_size(texture));
981                 return -EINVAL;
982         }
983         /* using get ib will give us the offset into the mipmap bo */
984         word0 = radeon_get_ib_value(p, idx + 3);
985         if ((mipmap_size + word0) > radeon_bo_size(mipmap)) {
986                 dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n",
987                         w0, h0, bpe, blevel, nlevels, word0, mipmap_size, radeon_bo_size(texture));
988                 return -EINVAL;
989         }
990         return 0;
991 }
992
993 static int r600_packet3_check(struct radeon_cs_parser *p,
994                                 struct radeon_cs_packet *pkt)
995 {
996         struct radeon_cs_reloc *reloc;
997         struct r600_cs_track *track;
998         volatile u32 *ib;
999         unsigned idx;
1000         unsigned i;
1001         unsigned start_reg, end_reg, reg;
1002         int r;
1003         u32 idx_value;
1004
1005         track = (struct r600_cs_track *)p->track;
1006         ib = p->ib->ptr;
1007         idx = pkt->idx + 1;
1008         idx_value = radeon_get_ib_value(p, idx);
1009
1010         switch (pkt->opcode) {
1011         case PACKET3_START_3D_CMDBUF:
1012                 if (p->family >= CHIP_RV770 || pkt->count) {
1013                         DRM_ERROR("bad START_3D\n");
1014                         return -EINVAL;
1015                 }
1016                 break;
1017         case PACKET3_CONTEXT_CONTROL:
1018                 if (pkt->count != 1) {
1019                         DRM_ERROR("bad CONTEXT_CONTROL\n");
1020                         return -EINVAL;
1021                 }
1022                 break;
1023         case PACKET3_INDEX_TYPE:
1024         case PACKET3_NUM_INSTANCES:
1025                 if (pkt->count) {
1026                         DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n");
1027                         return -EINVAL;
1028                 }
1029                 break;
1030         case PACKET3_DRAW_INDEX:
1031                 if (pkt->count != 3) {
1032                         DRM_ERROR("bad DRAW_INDEX\n");
1033                         return -EINVAL;
1034                 }
1035                 r = r600_cs_packet_next_reloc(p, &reloc);
1036                 if (r) {
1037                         DRM_ERROR("bad DRAW_INDEX\n");
1038                         return -EINVAL;
1039                 }
1040                 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1041                 ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1042                 r = r600_cs_track_check(p);
1043                 if (r) {
1044                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1045                         return r;
1046                 }
1047                 break;
1048         case PACKET3_DRAW_INDEX_AUTO:
1049                 if (pkt->count != 1) {
1050                         DRM_ERROR("bad DRAW_INDEX_AUTO\n");
1051                         return -EINVAL;
1052                 }
1053                 r = r600_cs_track_check(p);
1054                 if (r) {
1055                         dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
1056                         return r;
1057                 }
1058                 break;
1059         case PACKET3_DRAW_INDEX_IMMD_BE:
1060         case PACKET3_DRAW_INDEX_IMMD:
1061                 if (pkt->count < 2) {
1062                         DRM_ERROR("bad DRAW_INDEX_IMMD\n");
1063                         return -EINVAL;
1064                 }
1065                 r = r600_cs_track_check(p);
1066                 if (r) {
1067                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1068                         return r;
1069                 }
1070                 break;
1071         case PACKET3_WAIT_REG_MEM:
1072                 if (pkt->count != 5) {
1073                         DRM_ERROR("bad WAIT_REG_MEM\n");
1074                         return -EINVAL;
1075                 }
1076                 /* bit 4 is reg (0) or mem (1) */
1077                 if (idx_value & 0x10) {
1078                         r = r600_cs_packet_next_reloc(p, &reloc);
1079                         if (r) {
1080                                 DRM_ERROR("bad WAIT_REG_MEM\n");
1081                                 return -EINVAL;
1082                         }
1083                         ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1084                         ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1085                 }
1086                 break;
1087         case PACKET3_SURFACE_SYNC:
1088                 if (pkt->count != 3) {
1089                         DRM_ERROR("bad SURFACE_SYNC\n");
1090                         return -EINVAL;
1091                 }
1092                 /* 0xffffffff/0x0 is flush all cache flag */
1093                 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
1094                     radeon_get_ib_value(p, idx + 2) != 0) {
1095                         r = r600_cs_packet_next_reloc(p, &reloc);
1096                         if (r) {
1097                                 DRM_ERROR("bad SURFACE_SYNC\n");
1098                                 return -EINVAL;
1099                         }
1100                         ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1101                 }
1102                 break;
1103         case PACKET3_EVENT_WRITE:
1104                 if (pkt->count != 2 && pkt->count != 0) {
1105                         DRM_ERROR("bad EVENT_WRITE\n");
1106                         return -EINVAL;
1107                 }
1108                 if (pkt->count) {
1109                         r = r600_cs_packet_next_reloc(p, &reloc);
1110                         if (r) {
1111                                 DRM_ERROR("bad EVENT_WRITE\n");
1112                                 return -EINVAL;
1113                         }
1114                         ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1115                         ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1116                 }
1117                 break;
1118         case PACKET3_EVENT_WRITE_EOP:
1119                 if (pkt->count != 4) {
1120                         DRM_ERROR("bad EVENT_WRITE_EOP\n");
1121                         return -EINVAL;
1122                 }
1123                 r = r600_cs_packet_next_reloc(p, &reloc);
1124                 if (r) {
1125                         DRM_ERROR("bad EVENT_WRITE\n");
1126                         return -EINVAL;
1127                 }
1128                 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1129                 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1130                 break;
1131         case PACKET3_SET_CONFIG_REG:
1132                 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
1133                 end_reg = 4 * pkt->count + start_reg - 4;
1134                 if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) ||
1135                     (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
1136                     (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
1137                         DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
1138                         return -EINVAL;
1139                 }
1140                 for (i = 0; i < pkt->count; i++) {
1141                         reg = start_reg + (4 * i);
1142                         r = r600_cs_check_reg(p, reg, idx+1+i);
1143                         if (r)
1144                                 return r;
1145                 }
1146                 break;
1147         case PACKET3_SET_CONTEXT_REG:
1148                 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET;
1149                 end_reg = 4 * pkt->count + start_reg - 4;
1150                 if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) ||
1151                     (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
1152                     (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
1153                         DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
1154                         return -EINVAL;
1155                 }
1156                 for (i = 0; i < pkt->count; i++) {
1157                         reg = start_reg + (4 * i);
1158                         r = r600_cs_check_reg(p, reg, idx+1+i);
1159                         if (r)
1160                                 return r;
1161                 }
1162                 break;
1163         case PACKET3_SET_RESOURCE:
1164                 if (pkt->count % 7) {
1165                         DRM_ERROR("bad SET_RESOURCE\n");
1166                         return -EINVAL;
1167                 }
1168                 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET;
1169                 end_reg = 4 * pkt->count + start_reg - 4;
1170                 if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) ||
1171                     (start_reg >= PACKET3_SET_RESOURCE_END) ||
1172                     (end_reg >= PACKET3_SET_RESOURCE_END)) {
1173                         DRM_ERROR("bad SET_RESOURCE\n");
1174                         return -EINVAL;
1175                 }
1176                 for (i = 0; i < (pkt->count / 7); i++) {
1177                         struct radeon_bo *texture, *mipmap;
1178                         u32 size, offset;
1179
1180                         switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) {
1181                         case SQ_TEX_VTX_VALID_TEXTURE:
1182                                 /* tex base */
1183                                 r = r600_cs_packet_next_reloc(p, &reloc);
1184                                 if (r) {
1185                                         DRM_ERROR("bad SET_RESOURCE\n");
1186                                         return -EINVAL;
1187                                 }
1188                                 ib[idx+1+(i*7)+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1189                                 texture = reloc->robj;
1190                                 /* tex mip base */
1191                                 r = r600_cs_packet_next_reloc(p, &reloc);
1192                                 if (r) {
1193                                         DRM_ERROR("bad SET_RESOURCE\n");
1194                                         return -EINVAL;
1195                                 }
1196                                 ib[idx+1+(i*7)+3] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1197                                 mipmap = reloc->robj;
1198                                 r = r600_check_texture_resource(p,  idx+(i*7)+1,
1199                                                 texture, mipmap);
1200                                 if (r)
1201                                         return r;
1202                                 break;
1203                         case SQ_TEX_VTX_VALID_BUFFER:
1204                                 /* vtx base */
1205                                 r = r600_cs_packet_next_reloc(p, &reloc);
1206                                 if (r) {
1207                                         DRM_ERROR("bad SET_RESOURCE\n");
1208                                         return -EINVAL;
1209                                 }
1210                                 offset = radeon_get_ib_value(p, idx+1+(i*7)+0);
1211                                 size = radeon_get_ib_value(p, idx+1+(i*7)+1);
1212                                 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
1213                                         /* force size to size of the buffer */
1214                                         dev_warn(p->dev, "vbo resource seems too big for the bo\n");
1215                                         ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj);
1216                                 }
1217                                 ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff);
1218                                 ib[idx+1+(i*7)+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1219                                 break;
1220                         case SQ_TEX_VTX_INVALID_TEXTURE:
1221                         case SQ_TEX_VTX_INVALID_BUFFER:
1222                         default:
1223                                 DRM_ERROR("bad SET_RESOURCE\n");
1224                                 return -EINVAL;
1225                         }
1226                 }
1227                 break;
1228         case PACKET3_SET_ALU_CONST:
1229                 start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;
1230                 end_reg = 4 * pkt->count + start_reg - 4;
1231                 if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||
1232                     (start_reg >= PACKET3_SET_ALU_CONST_END) ||
1233                     (end_reg >= PACKET3_SET_ALU_CONST_END)) {
1234                         DRM_ERROR("bad SET_ALU_CONST\n");
1235                         return -EINVAL;
1236                 }
1237                 break;
1238         case PACKET3_SET_BOOL_CONST:
1239                 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET;
1240                 end_reg = 4 * pkt->count + start_reg - 4;
1241                 if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) ||
1242                     (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
1243                     (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
1244                         DRM_ERROR("bad SET_BOOL_CONST\n");
1245                         return -EINVAL;
1246                 }
1247                 break;
1248         case PACKET3_SET_LOOP_CONST:
1249                 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET;
1250                 end_reg = 4 * pkt->count + start_reg - 4;
1251                 if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) ||
1252                     (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
1253                     (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
1254                         DRM_ERROR("bad SET_LOOP_CONST\n");
1255                         return -EINVAL;
1256                 }
1257                 break;
1258         case PACKET3_SET_CTL_CONST:
1259                 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET;
1260                 end_reg = 4 * pkt->count + start_reg - 4;
1261                 if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) ||
1262                     (start_reg >= PACKET3_SET_CTL_CONST_END) ||
1263                     (end_reg >= PACKET3_SET_CTL_CONST_END)) {
1264                         DRM_ERROR("bad SET_CTL_CONST\n");
1265                         return -EINVAL;
1266                 }
1267                 break;
1268         case PACKET3_SET_SAMPLER:
1269                 if (pkt->count % 3) {
1270                         DRM_ERROR("bad SET_SAMPLER\n");
1271                         return -EINVAL;
1272                 }
1273                 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET;
1274                 end_reg = 4 * pkt->count + start_reg - 4;
1275                 if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) ||
1276                     (start_reg >= PACKET3_SET_SAMPLER_END) ||
1277                     (end_reg >= PACKET3_SET_SAMPLER_END)) {
1278                         DRM_ERROR("bad SET_SAMPLER\n");
1279                         return -EINVAL;
1280                 }
1281                 break;
1282         case PACKET3_SURFACE_BASE_UPDATE:
1283                 if (p->family >= CHIP_RV770 || p->family == CHIP_R600) {
1284                         DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
1285                         return -EINVAL;
1286                 }
1287                 if (pkt->count) {
1288                         DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
1289                         return -EINVAL;
1290                 }
1291                 break;
1292         case PACKET3_NOP:
1293                 break;
1294         default:
1295                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1296                 return -EINVAL;
1297         }
1298         return 0;
1299 }
1300
1301 int r600_cs_parse(struct radeon_cs_parser *p)
1302 {
1303         struct radeon_cs_packet pkt;
1304         struct r600_cs_track *track;
1305         int r;
1306
1307         if (p->track == NULL) {
1308                 /* initialize tracker, we are in kms */
1309                 track = kzalloc(sizeof(*track), GFP_KERNEL);
1310                 if (track == NULL)
1311                         return -ENOMEM;
1312                 r600_cs_track_init(track);
1313                 if (p->rdev->family < CHIP_RV770) {
1314                         track->npipes = p->rdev->config.r600.tiling_npipes;
1315                         track->nbanks = p->rdev->config.r600.tiling_nbanks;
1316                         track->group_size = p->rdev->config.r600.tiling_group_size;
1317                 } else if (p->rdev->family <= CHIP_RV740) {
1318                         track->npipes = p->rdev->config.rv770.tiling_npipes;
1319                         track->nbanks = p->rdev->config.rv770.tiling_nbanks;
1320                         track->group_size = p->rdev->config.rv770.tiling_group_size;
1321                 }
1322                 p->track = track;
1323         }
1324         do {
1325                 r = r600_cs_packet_parse(p, &pkt, p->idx);
1326                 if (r) {
1327                         kfree(p->track);
1328                         p->track = NULL;
1329                         return r;
1330                 }
1331                 p->idx += pkt.count + 2;
1332                 switch (pkt.type) {
1333                 case PACKET_TYPE0:
1334                         r = r600_cs_parse_packet0(p, &pkt);
1335                         break;
1336                 case PACKET_TYPE2:
1337                         break;
1338                 case PACKET_TYPE3:
1339                         r = r600_packet3_check(p, &pkt);
1340                         break;
1341                 default:
1342                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1343                         kfree(p->track);
1344                         p->track = NULL;
1345                         return -EINVAL;
1346                 }
1347                 if (r) {
1348                         kfree(p->track);
1349                         p->track = NULL;
1350                         return r;
1351                 }
1352         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1353 #if 0
1354         for (r = 0; r < p->ib->length_dw; r++) {
1355                 printk(KERN_INFO "%05d  0x%08X\n", r, p->ib->ptr[r]);
1356                 mdelay(1);
1357         }
1358 #endif
1359         kfree(p->track);
1360         p->track = NULL;
1361         return 0;
1362 }
1363
1364 static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p)
1365 {
1366         if (p->chunk_relocs_idx == -1) {
1367                 return 0;
1368         }
1369         p->relocs = kzalloc(sizeof(struct radeon_cs_reloc), GFP_KERNEL);
1370         if (p->relocs == NULL) {
1371                 return -ENOMEM;
1372         }
1373         return 0;
1374 }
1375
1376 /**
1377  * cs_parser_fini() - clean parser states
1378  * @parser:     parser structure holding parsing context.
1379  * @error:      error number
1380  *
1381  * If error is set than unvalidate buffer, otherwise just free memory
1382  * used by parsing context.
1383  **/
1384 static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error)
1385 {
1386         unsigned i;
1387
1388         kfree(parser->relocs);
1389         for (i = 0; i < parser->nchunks; i++) {
1390                 kfree(parser->chunks[i].kdata);
1391                 kfree(parser->chunks[i].kpage[0]);
1392                 kfree(parser->chunks[i].kpage[1]);
1393         }
1394         kfree(parser->chunks);
1395         kfree(parser->chunks_array);
1396 }
1397
1398 int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
1399                         unsigned family, u32 *ib, int *l)
1400 {
1401         struct radeon_cs_parser parser;
1402         struct radeon_cs_chunk *ib_chunk;
1403         struct radeon_ib fake_ib;
1404         struct r600_cs_track *track;
1405         int r;
1406
1407         /* initialize tracker */
1408         track = kzalloc(sizeof(*track), GFP_KERNEL);
1409         if (track == NULL)
1410                 return -ENOMEM;
1411         r600_cs_track_init(track);
1412         r600_cs_legacy_get_tiling_conf(dev, &track->npipes, &track->nbanks, &track->group_size);
1413         /* initialize parser */
1414         memset(&parser, 0, sizeof(struct radeon_cs_parser));
1415         parser.filp = filp;
1416         parser.dev = &dev->pdev->dev;
1417         parser.rdev = NULL;
1418         parser.family = family;
1419         parser.ib = &fake_ib;
1420         parser.track = track;
1421         fake_ib.ptr = ib;
1422         r = radeon_cs_parser_init(&parser, data);
1423         if (r) {
1424                 DRM_ERROR("Failed to initialize parser !\n");
1425                 r600_cs_parser_fini(&parser, r);
1426                 return r;
1427         }
1428         r = r600_cs_parser_relocs_legacy(&parser);
1429         if (r) {
1430                 DRM_ERROR("Failed to parse relocation !\n");
1431                 r600_cs_parser_fini(&parser, r);
1432                 return r;
1433         }
1434         /* Copy the packet into the IB, the parser will read from the
1435          * input memory (cached) and write to the IB (which can be
1436          * uncached). */
1437         ib_chunk = &parser.chunks[parser.chunk_ib_idx];
1438         parser.ib->length_dw = ib_chunk->length_dw;
1439         *l = parser.ib->length_dw;
1440         r = r600_cs_parse(&parser);
1441         if (r) {
1442                 DRM_ERROR("Invalid command stream !\n");
1443                 r600_cs_parser_fini(&parser, r);
1444                 return r;
1445         }
1446         r = radeon_cs_finish_pages(&parser);
1447         if (r) {
1448                 DRM_ERROR("Invalid command stream !\n");
1449                 r600_cs_parser_fini(&parser, r);
1450                 return r;
1451         }
1452         r600_cs_parser_fini(&parser, r);
1453         return r;
1454 }
1455
1456 void r600_cs_legacy_init(void)
1457 {
1458         r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_nomm;
1459 }