drm/radeon/kms: don't require up to 64k allocations. (v2)
[linux-3.10.git] / drivers / gpu / drm / radeon / r600_cs.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include "drmP.h"
29 #include "radeon.h"
30 #include "r600d.h"
31 #include "avivod.h"
32
33 static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
34                                         struct radeon_cs_reloc **cs_reloc);
35 static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
36                                         struct radeon_cs_reloc **cs_reloc);
37 typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**);
38 static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm;
39
40 /**
41  * r600_cs_packet_parse() - parse cp packet and point ib index to next packet
42  * @parser:     parser structure holding parsing context.
43  * @pkt:        where to store packet informations
44  *
45  * Assume that chunk_ib_index is properly set. Will return -EINVAL
46  * if packet is bigger than remaining ib size. or if packets is unknown.
47  **/
48 int r600_cs_packet_parse(struct radeon_cs_parser *p,
49                         struct radeon_cs_packet *pkt,
50                         unsigned idx)
51 {
52         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
53         uint32_t header;
54
55         if (idx >= ib_chunk->length_dw) {
56                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
57                           idx, ib_chunk->length_dw);
58                 return -EINVAL;
59         }
60         header = radeon_get_ib_value(p, idx);
61         pkt->idx = idx;
62         pkt->type = CP_PACKET_GET_TYPE(header);
63         pkt->count = CP_PACKET_GET_COUNT(header);
64         pkt->one_reg_wr = 0;
65         switch (pkt->type) {
66         case PACKET_TYPE0:
67                 pkt->reg = CP_PACKET0_GET_REG(header);
68                 break;
69         case PACKET_TYPE3:
70                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
71                 break;
72         case PACKET_TYPE2:
73                 pkt->count = -1;
74                 break;
75         default:
76                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
77                 return -EINVAL;
78         }
79         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
80                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
81                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
82                 return -EINVAL;
83         }
84         return 0;
85 }
86
87 /**
88  * r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3
89  * @parser:             parser structure holding parsing context.
90  * @data:               pointer to relocation data
91  * @offset_start:       starting offset
92  * @offset_mask:        offset mask (to align start offset on)
93  * @reloc:              reloc informations
94  *
95  * Check next packet is relocation packet3, do bo validation and compute
96  * GPU offset using the provided start.
97  **/
98 static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
99                                         struct radeon_cs_reloc **cs_reloc)
100 {
101         struct radeon_cs_chunk *relocs_chunk;
102         struct radeon_cs_packet p3reloc;
103         unsigned idx;
104         int r;
105
106         if (p->chunk_relocs_idx == -1) {
107                 DRM_ERROR("No relocation chunk !\n");
108                 return -EINVAL;
109         }
110         *cs_reloc = NULL;
111         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
112         r = r600_cs_packet_parse(p, &p3reloc, p->idx);
113         if (r) {
114                 return r;
115         }
116         p->idx += p3reloc.count + 2;
117         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
118                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
119                           p3reloc.idx);
120                 return -EINVAL;
121         }
122         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
123         if (idx >= relocs_chunk->length_dw) {
124                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
125                           idx, relocs_chunk->length_dw);
126                 return -EINVAL;
127         }
128         /* FIXME: we assume reloc size is 4 dwords */
129         *cs_reloc = p->relocs_ptr[(idx / 4)];
130         return 0;
131 }
132
133 /**
134  * r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3
135  * @parser:             parser structure holding parsing context.
136  * @data:               pointer to relocation data
137  * @offset_start:       starting offset
138  * @offset_mask:        offset mask (to align start offset on)
139  * @reloc:              reloc informations
140  *
141  * Check next packet is relocation packet3, do bo validation and compute
142  * GPU offset using the provided start.
143  **/
144 static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
145                                         struct radeon_cs_reloc **cs_reloc)
146 {
147         struct radeon_cs_chunk *relocs_chunk;
148         struct radeon_cs_packet p3reloc;
149         unsigned idx;
150         int r;
151
152         if (p->chunk_relocs_idx == -1) {
153                 DRM_ERROR("No relocation chunk !\n");
154                 return -EINVAL;
155         }
156         *cs_reloc = NULL;
157         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
158         r = r600_cs_packet_parse(p, &p3reloc, p->idx);
159         if (r) {
160                 return r;
161         }
162         p->idx += p3reloc.count + 2;
163         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
164                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
165                           p3reloc.idx);
166                 return -EINVAL;
167         }
168         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
169         if (idx >= relocs_chunk->length_dw) {
170                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
171                           idx, relocs_chunk->length_dw);
172                 return -EINVAL;
173         }
174         *cs_reloc = &p->relocs[0];
175         (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32;
176         (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
177         return 0;
178 }
179
180 static int r600_packet0_check(struct radeon_cs_parser *p,
181                                 struct radeon_cs_packet *pkt,
182                                 unsigned idx, unsigned reg)
183 {
184         switch (reg) {
185         case AVIVO_D1MODE_VLINE_START_END:
186         case AVIVO_D2MODE_VLINE_START_END:
187                 break;
188         default:
189                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
190                        reg, idx);
191                 return -EINVAL;
192         }
193         return 0;
194 }
195
196 static int r600_cs_parse_packet0(struct radeon_cs_parser *p,
197                                 struct radeon_cs_packet *pkt)
198 {
199         unsigned reg, i;
200         unsigned idx;
201         int r;
202
203         idx = pkt->idx + 1;
204         reg = pkt->reg;
205         for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
206                 r = r600_packet0_check(p, pkt, idx, reg);
207                 if (r) {
208                         return r;
209                 }
210         }
211         return 0;
212 }
213
214 static int r600_packet3_check(struct radeon_cs_parser *p,
215                                 struct radeon_cs_packet *pkt)
216 {
217         struct radeon_cs_reloc *reloc;
218         volatile u32 *ib;
219         unsigned idx;
220         unsigned i;
221         unsigned start_reg, end_reg, reg;
222         int r;
223
224         ib = p->ib->ptr;
225         idx = pkt->idx + 1;
226
227         switch (pkt->opcode) {
228         case PACKET3_START_3D_CMDBUF:
229                 if (p->family >= CHIP_RV770 || pkt->count) {
230                         DRM_ERROR("bad START_3D\n");
231                         return -EINVAL;
232                 }
233                 break;
234         case PACKET3_CONTEXT_CONTROL:
235                 if (pkt->count != 1) {
236                         DRM_ERROR("bad CONTEXT_CONTROL\n");
237                         return -EINVAL;
238                 }
239                 break;
240         case PACKET3_INDEX_TYPE:
241         case PACKET3_NUM_INSTANCES:
242                 if (pkt->count) {
243                         DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n");
244                         return -EINVAL;
245                 }
246                 break;
247         case PACKET3_DRAW_INDEX:
248                 if (pkt->count != 3) {
249                         DRM_ERROR("bad DRAW_INDEX\n");
250                         return -EINVAL;
251                 }
252                 r = r600_cs_packet_next_reloc(p, &reloc);
253                 if (r) {
254                         DRM_ERROR("bad DRAW_INDEX\n");
255                         return -EINVAL;
256                 }
257                 ib[idx+0] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
258                 ib[idx+1] = upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
259                 break;
260         case PACKET3_DRAW_INDEX_AUTO:
261                 if (pkt->count != 1) {
262                         DRM_ERROR("bad DRAW_INDEX_AUTO\n");
263                         return -EINVAL;
264                 }
265                 break;
266         case PACKET3_DRAW_INDEX_IMMD_BE:
267         case PACKET3_DRAW_INDEX_IMMD:
268                 if (pkt->count < 2) {
269                         DRM_ERROR("bad DRAW_INDEX_IMMD\n");
270                         return -EINVAL;
271                 }
272                 break;
273         case PACKET3_WAIT_REG_MEM:
274                 if (pkt->count != 5) {
275                         DRM_ERROR("bad WAIT_REG_MEM\n");
276                         return -EINVAL;
277                 }
278                 /* bit 4 is reg (0) or mem (1) */
279                 if (radeon_get_ib_value(p, idx) & 0x10) {
280                         r = r600_cs_packet_next_reloc(p, &reloc);
281                         if (r) {
282                                 DRM_ERROR("bad WAIT_REG_MEM\n");
283                                 return -EINVAL;
284                         }
285                         ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
286                         ib[idx+2] = upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
287                 }
288                 break;
289         case PACKET3_SURFACE_SYNC:
290                 if (pkt->count != 3) {
291                         DRM_ERROR("bad SURFACE_SYNC\n");
292                         return -EINVAL;
293                 }
294                 /* 0xffffffff/0x0 is flush all cache flag */
295                 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
296                     radeon_get_ib_value(p, idx + 2) != 0) {
297                         r = r600_cs_packet_next_reloc(p, &reloc);
298                         if (r) {
299                                 DRM_ERROR("bad SURFACE_SYNC\n");
300                                 return -EINVAL;
301                         }
302                         ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
303                 }
304                 break;
305         case PACKET3_EVENT_WRITE:
306                 if (pkt->count != 2 && pkt->count != 0) {
307                         DRM_ERROR("bad EVENT_WRITE\n");
308                         return -EINVAL;
309                 }
310                 if (pkt->count) {
311                         r = r600_cs_packet_next_reloc(p, &reloc);
312                         if (r) {
313                                 DRM_ERROR("bad EVENT_WRITE\n");
314                                 return -EINVAL;
315                         }
316                         ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
317                         ib[idx+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
318                 }
319                 break;
320         case PACKET3_EVENT_WRITE_EOP:
321                 if (pkt->count != 4) {
322                         DRM_ERROR("bad EVENT_WRITE_EOP\n");
323                         return -EINVAL;
324                 }
325                 r = r600_cs_packet_next_reloc(p, &reloc);
326                 if (r) {
327                         DRM_ERROR("bad EVENT_WRITE\n");
328                         return -EINVAL;
329                 }
330                 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
331                 ib[idx+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
332                 break;
333         case PACKET3_SET_CONFIG_REG:
334                 start_reg = (ib[idx+0] << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
335                 end_reg = 4 * pkt->count + start_reg - 4;
336                 if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) ||
337                     (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
338                     (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
339                         DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
340                         return -EINVAL;
341                 }
342                 for (i = 0; i < pkt->count; i++) {
343                         reg = start_reg + (4 * i);
344                         switch (reg) {
345                         case CP_COHER_BASE:
346                                 /* use PACKET3_SURFACE_SYNC */
347                                 return -EINVAL;
348                         default:
349                                 break;
350                         }
351                 }
352                 break;
353         case PACKET3_SET_CONTEXT_REG:
354                 start_reg = (ib[idx+0] << 2) + PACKET3_SET_CONTEXT_REG_OFFSET;
355                 end_reg = 4 * pkt->count + start_reg - 4;
356                 if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) ||
357                     (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
358                     (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
359                         DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
360                         return -EINVAL;
361                 }
362                 for (i = 0; i < pkt->count; i++) {
363                         reg = start_reg + (4 * i);
364                         switch (reg) {
365                         case DB_DEPTH_BASE:
366                         case CB_COLOR0_BASE:
367                         case CB_COLOR1_BASE:
368                         case CB_COLOR2_BASE:
369                         case CB_COLOR3_BASE:
370                         case CB_COLOR4_BASE:
371                         case CB_COLOR5_BASE:
372                         case CB_COLOR6_BASE:
373                         case CB_COLOR7_BASE:
374                         case SQ_PGM_START_FS:
375                         case SQ_PGM_START_ES:
376                         case SQ_PGM_START_VS:
377                         case SQ_PGM_START_GS:
378                         case SQ_PGM_START_PS:
379                                 r = r600_cs_packet_next_reloc(p, &reloc);
380                                 if (r) {
381                                         DRM_ERROR("bad SET_CONTEXT_REG "
382                                                         "0x%04X\n", reg);
383                                         return -EINVAL;
384                                 }
385                                 ib[idx+1+i] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
386                                 break;
387                         case VGT_DMA_BASE:
388                         case VGT_DMA_BASE_HI:
389                                 /* These should be handled by DRAW_INDEX packet 3 */
390                         case VGT_STRMOUT_BASE_OFFSET_0:
391                         case VGT_STRMOUT_BASE_OFFSET_1:
392                         case VGT_STRMOUT_BASE_OFFSET_2:
393                         case VGT_STRMOUT_BASE_OFFSET_3:
394                         case VGT_STRMOUT_BASE_OFFSET_HI_0:
395                         case VGT_STRMOUT_BASE_OFFSET_HI_1:
396                         case VGT_STRMOUT_BASE_OFFSET_HI_2:
397                         case VGT_STRMOUT_BASE_OFFSET_HI_3:
398                         case VGT_STRMOUT_BUFFER_BASE_0:
399                         case VGT_STRMOUT_BUFFER_BASE_1:
400                         case VGT_STRMOUT_BUFFER_BASE_2:
401                         case VGT_STRMOUT_BUFFER_BASE_3:
402                         case VGT_STRMOUT_BUFFER_OFFSET_0:
403                         case VGT_STRMOUT_BUFFER_OFFSET_1:
404                         case VGT_STRMOUT_BUFFER_OFFSET_2:
405                         case VGT_STRMOUT_BUFFER_OFFSET_3:
406                                 /* These should be handled by STRMOUT_BUFFER packet 3 */
407                                 DRM_ERROR("bad context reg: 0x%08x\n", reg);
408                                 return -EINVAL;
409                         default:
410                                 break;
411                         }
412                 }
413                 break;
414         case PACKET3_SET_RESOURCE:
415                 if (pkt->count % 7) {
416                         DRM_ERROR("bad SET_RESOURCE\n");
417                         return -EINVAL;
418                 }
419                 start_reg = (ib[idx+0] << 2) + PACKET3_SET_RESOURCE_OFFSET;
420                 end_reg = 4 * pkt->count + start_reg - 4;
421                 if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) ||
422                     (start_reg >= PACKET3_SET_RESOURCE_END) ||
423                     (end_reg >= PACKET3_SET_RESOURCE_END)) {
424                         DRM_ERROR("bad SET_RESOURCE\n");
425                         return -EINVAL;
426                 }
427                 for (i = 0; i < (pkt->count / 7); i++) {
428                         switch (G__SQ_VTX_CONSTANT_TYPE(ib[idx+(i*7)+6+1])) {
429                         case SQ_TEX_VTX_VALID_TEXTURE:
430                                 /* tex base */
431                                 r = r600_cs_packet_next_reloc(p, &reloc);
432                                 if (r) {
433                                         DRM_ERROR("bad SET_RESOURCE\n");
434                                         return -EINVAL;
435                                 }
436                                 ib[idx+1+(i*7)+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
437                                 /* tex mip base */
438                                 r = r600_cs_packet_next_reloc(p, &reloc);
439                                 if (r) {
440                                         DRM_ERROR("bad SET_RESOURCE\n");
441                                         return -EINVAL;
442                                 }
443                                 ib[idx+1+(i*7)+3] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
444                                 break;
445                         case SQ_TEX_VTX_VALID_BUFFER:
446                                 /* vtx base */
447                                 r = r600_cs_packet_next_reloc(p, &reloc);
448                                 if (r) {
449                                         DRM_ERROR("bad SET_RESOURCE\n");
450                                         return -EINVAL;
451                                 }
452                                 ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff);
453                                 ib[idx+1+(i*7)+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
454                                 break;
455                         case SQ_TEX_VTX_INVALID_TEXTURE:
456                         case SQ_TEX_VTX_INVALID_BUFFER:
457                         default:
458                                 DRM_ERROR("bad SET_RESOURCE\n");
459                                 return -EINVAL;
460                         }
461                 }
462                 break;
463         case PACKET3_SET_ALU_CONST:
464                 start_reg = (ib[idx+0] << 2) + PACKET3_SET_ALU_CONST_OFFSET;
465                 end_reg = 4 * pkt->count + start_reg - 4;
466                 if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||
467                     (start_reg >= PACKET3_SET_ALU_CONST_END) ||
468                     (end_reg >= PACKET3_SET_ALU_CONST_END)) {
469                         DRM_ERROR("bad SET_ALU_CONST\n");
470                         return -EINVAL;
471                 }
472                 break;
473         case PACKET3_SET_BOOL_CONST:
474                 start_reg = (ib[idx+0] << 2) + PACKET3_SET_BOOL_CONST_OFFSET;
475                 end_reg = 4 * pkt->count + start_reg - 4;
476                 if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) ||
477                     (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
478                     (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
479                         DRM_ERROR("bad SET_BOOL_CONST\n");
480                         return -EINVAL;
481                 }
482                 break;
483         case PACKET3_SET_LOOP_CONST:
484                 start_reg = (ib[idx+0] << 2) + PACKET3_SET_LOOP_CONST_OFFSET;
485                 end_reg = 4 * pkt->count + start_reg - 4;
486                 if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) ||
487                     (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
488                     (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
489                         DRM_ERROR("bad SET_LOOP_CONST\n");
490                         return -EINVAL;
491                 }
492                 break;
493         case PACKET3_SET_CTL_CONST:
494                 start_reg = (ib[idx+0] << 2) + PACKET3_SET_CTL_CONST_OFFSET;
495                 end_reg = 4 * pkt->count + start_reg - 4;
496                 if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) ||
497                     (start_reg >= PACKET3_SET_CTL_CONST_END) ||
498                     (end_reg >= PACKET3_SET_CTL_CONST_END)) {
499                         DRM_ERROR("bad SET_CTL_CONST\n");
500                         return -EINVAL;
501                 }
502                 break;
503         case PACKET3_SET_SAMPLER:
504                 if (pkt->count % 3) {
505                         DRM_ERROR("bad SET_SAMPLER\n");
506                         return -EINVAL;
507                 }
508                 start_reg = (ib[idx+0] << 2) + PACKET3_SET_SAMPLER_OFFSET;
509                 end_reg = 4 * pkt->count + start_reg - 4;
510                 if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) ||
511                     (start_reg >= PACKET3_SET_SAMPLER_END) ||
512                     (end_reg >= PACKET3_SET_SAMPLER_END)) {
513                         DRM_ERROR("bad SET_SAMPLER\n");
514                         return -EINVAL;
515                 }
516                 break;
517         case PACKET3_SURFACE_BASE_UPDATE:
518                 if (p->family >= CHIP_RV770 || p->family == CHIP_R600) {
519                         DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
520                         return -EINVAL;
521                 }
522                 if (pkt->count) {
523                         DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
524                         return -EINVAL;
525                 }
526                 break;
527         case PACKET3_NOP:
528                 break;
529         default:
530                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
531                 return -EINVAL;
532         }
533         return 0;
534 }
535
536 int r600_cs_parse(struct radeon_cs_parser *p)
537 {
538         struct radeon_cs_packet pkt;
539         int r;
540
541         do {
542                 r = r600_cs_packet_parse(p, &pkt, p->idx);
543                 if (r) {
544                         return r;
545                 }
546                 p->idx += pkt.count + 2;
547                 switch (pkt.type) {
548                 case PACKET_TYPE0:
549                         r = r600_cs_parse_packet0(p, &pkt);
550                         break;
551                 case PACKET_TYPE2:
552                         break;
553                 case PACKET_TYPE3:
554                         r = r600_packet3_check(p, &pkt);
555                         break;
556                 default:
557                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
558                         return -EINVAL;
559                 }
560                 if (r) {
561                         return r;
562                 }
563         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
564 #if 0
565         for (r = 0; r < p->ib->length_dw; r++) {
566                 printk(KERN_INFO "%05d  0x%08X\n", r, p->ib->ptr[r]);
567                 mdelay(1);
568         }
569 #endif
570         return 0;
571 }
572
573 static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p)
574 {
575         if (p->chunk_relocs_idx == -1) {
576                 return 0;
577         }
578         p->relocs = kcalloc(1, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
579         if (p->relocs == NULL) {
580                 return -ENOMEM;
581         }
582         return 0;
583 }
584
585 /**
586  * cs_parser_fini() - clean parser states
587  * @parser:     parser structure holding parsing context.
588  * @error:      error number
589  *
590  * If error is set than unvalidate buffer, otherwise just free memory
591  * used by parsing context.
592  **/
593 static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error)
594 {
595         unsigned i;
596
597         kfree(parser->relocs);
598         for (i = 0; i < parser->nchunks; i++) {
599                 kfree(parser->chunks[i].kdata);
600         }
601         kfree(parser->chunks);
602         kfree(parser->chunks_array);
603 }
604
605 int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
606                         unsigned family, u32 *ib, int *l)
607 {
608         struct radeon_cs_parser parser;
609         struct radeon_cs_chunk *ib_chunk;
610         struct radeon_ib        fake_ib;
611         int r;
612
613         /* initialize parser */
614         memset(&parser, 0, sizeof(struct radeon_cs_parser));
615         parser.filp = filp;
616         parser.rdev = NULL;
617         parser.family = family;
618         parser.ib = &fake_ib;
619         fake_ib.ptr = ib;
620         r = radeon_cs_parser_init(&parser, data);
621         if (r) {
622                 DRM_ERROR("Failed to initialize parser !\n");
623                 r600_cs_parser_fini(&parser, r);
624                 return r;
625         }
626         r = r600_cs_parser_relocs_legacy(&parser);
627         if (r) {
628                 DRM_ERROR("Failed to parse relocation !\n");
629                 r600_cs_parser_fini(&parser, r);
630                 return r;
631         }
632         /* Copy the packet into the IB, the parser will read from the
633          * input memory (cached) and write to the IB (which can be
634          * uncached). */
635         ib_chunk = &parser.chunks[parser.chunk_ib_idx];
636         parser.ib->length_dw = ib_chunk->length_dw;
637         *l = parser.ib->length_dw;
638         r = r600_cs_parse(&parser);
639         if (r) {
640                 DRM_ERROR("Invalid command stream !\n");
641                 r600_cs_parser_fini(&parser, r);
642                 return r;
643         }
644         r = radeon_cs_finish_pages(&parser);
645         if (r) {
646                 DRM_ERROR("Invalid command stream !\n");
647                 r600_cs_parser_fini(&parser, r);
648                 return r;
649         }
650         r600_cs_parser_fini(&parser, r);
651         return r;
652 }
653
654 void r600_cs_legacy_init(void)
655 {
656         r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_nomm;
657 }