Merge remote branch 'intel/drm-intel-next' of ../drm-next into drm-core-next
[linux-3.10.git] / drivers / gpu / drm / radeon / r600_cs.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <linux/kernel.h>
29 #include "drmP.h"
30 #include "radeon.h"
31 #include "r600d.h"
32 #include "r600_reg_safe.h"
33
34 static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
35                                         struct radeon_cs_reloc **cs_reloc);
36 static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
37                                         struct radeon_cs_reloc **cs_reloc);
38 typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**);
39 static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm;
40 extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size);
41
42
43 struct r600_cs_track {
44         /* configuration we miror so that we use same code btw kms/ums */
45         u32                     group_size;
46         u32                     nbanks;
47         u32                     npipes;
48         /* value we track */
49         u32                     sq_config;
50         u32                     nsamples;
51         u32                     cb_color_base_last[8];
52         struct radeon_bo        *cb_color_bo[8];
53         u64                     cb_color_bo_mc[8];
54         u32                     cb_color_bo_offset[8];
55         struct radeon_bo        *cb_color_frag_bo[8];
56         struct radeon_bo        *cb_color_tile_bo[8];
57         u32                     cb_color_info[8];
58         u32                     cb_color_size_idx[8];
59         u32                     cb_target_mask;
60         u32                     cb_shader_mask;
61         u32                     cb_color_size[8];
62         u32                     vgt_strmout_en;
63         u32                     vgt_strmout_buffer_en;
64         u32                     db_depth_control;
65         u32                     db_depth_info;
66         u32                     db_depth_size_idx;
67         u32                     db_depth_view;
68         u32                     db_depth_size;
69         u32                     db_offset;
70         struct radeon_bo        *db_bo;
71         u64                     db_bo_mc;
72 };
73
74 #define FMT_8_BIT(fmt, vc) [fmt] = { 1, 1, 1, vc }
75 #define FMT_16_BIT(fmt, vc) [fmt] = { 1, 1, 2, vc }
76 #define FMT_24_BIT(fmt) [fmt] = { 1, 1, 3, 0 }
77 #define FMT_32_BIT(fmt, vc) [fmt] = { 1, 1, 4, vc }
78 #define FMT_48_BIT(fmt) [fmt] = { 1, 1, 6, 0 }
79 #define FMT_64_BIT(fmt, vc) [fmt] = { 1, 1, 8, vc }
80 #define FMT_96_BIT(fmt) [fmt] = { 1, 1, 12, 0 }
81 #define FMT_128_BIT(fmt, vc) [fmt] = { 1, 1, 16, vc }
82
83 struct gpu_formats {
84         unsigned blockwidth;
85         unsigned blockheight;
86         unsigned blocksize;
87         unsigned valid_color;
88 };
89
90 static const struct gpu_formats color_formats_table[] = {
91         /* 8 bit */
92         FMT_8_BIT(V_038004_COLOR_8, 1),
93         FMT_8_BIT(V_038004_COLOR_4_4, 1),
94         FMT_8_BIT(V_038004_COLOR_3_3_2, 1),
95         FMT_8_BIT(V_038004_FMT_1, 0),
96
97         /* 16-bit */
98         FMT_16_BIT(V_038004_COLOR_16, 1),
99         FMT_16_BIT(V_038004_COLOR_16_FLOAT, 1),
100         FMT_16_BIT(V_038004_COLOR_8_8, 1),
101         FMT_16_BIT(V_038004_COLOR_5_6_5, 1),
102         FMT_16_BIT(V_038004_COLOR_6_5_5, 1),
103         FMT_16_BIT(V_038004_COLOR_1_5_5_5, 1),
104         FMT_16_BIT(V_038004_COLOR_4_4_4_4, 1),
105         FMT_16_BIT(V_038004_COLOR_5_5_5_1, 1),
106
107         /* 24-bit */
108         FMT_24_BIT(V_038004_FMT_8_8_8),
109                                                
110         /* 32-bit */
111         FMT_32_BIT(V_038004_COLOR_32, 1),
112         FMT_32_BIT(V_038004_COLOR_32_FLOAT, 1),
113         FMT_32_BIT(V_038004_COLOR_16_16, 1),
114         FMT_32_BIT(V_038004_COLOR_16_16_FLOAT, 1),
115         FMT_32_BIT(V_038004_COLOR_8_24, 1),
116         FMT_32_BIT(V_038004_COLOR_8_24_FLOAT, 1),
117         FMT_32_BIT(V_038004_COLOR_24_8, 1),
118         FMT_32_BIT(V_038004_COLOR_24_8_FLOAT, 1),
119         FMT_32_BIT(V_038004_COLOR_10_11_11, 1),
120         FMT_32_BIT(V_038004_COLOR_10_11_11_FLOAT, 1),
121         FMT_32_BIT(V_038004_COLOR_11_11_10, 1),
122         FMT_32_BIT(V_038004_COLOR_11_11_10_FLOAT, 1),
123         FMT_32_BIT(V_038004_COLOR_2_10_10_10, 1),
124         FMT_32_BIT(V_038004_COLOR_8_8_8_8, 1),
125         FMT_32_BIT(V_038004_COLOR_10_10_10_2, 1),
126         FMT_32_BIT(V_038004_FMT_5_9_9_9_SHAREDEXP, 0),
127         FMT_32_BIT(V_038004_FMT_32_AS_8, 0),
128         FMT_32_BIT(V_038004_FMT_32_AS_8_8, 0),
129
130         /* 48-bit */
131         FMT_48_BIT(V_038004_FMT_16_16_16),
132         FMT_48_BIT(V_038004_FMT_16_16_16_FLOAT),
133
134         /* 64-bit */
135         FMT_64_BIT(V_038004_COLOR_X24_8_32_FLOAT, 1),
136         FMT_64_BIT(V_038004_COLOR_32_32, 1),
137         FMT_64_BIT(V_038004_COLOR_32_32_FLOAT, 1),
138         FMT_64_BIT(V_038004_COLOR_16_16_16_16, 1),
139         FMT_64_BIT(V_038004_COLOR_16_16_16_16_FLOAT, 1),
140
141         FMT_96_BIT(V_038004_FMT_32_32_32),
142         FMT_96_BIT(V_038004_FMT_32_32_32_FLOAT),
143
144         /* 128-bit */
145         FMT_128_BIT(V_038004_COLOR_32_32_32_32, 1),
146         FMT_128_BIT(V_038004_COLOR_32_32_32_32_FLOAT, 1),
147
148         [V_038004_FMT_GB_GR] = { 2, 1, 4, 0 },
149         [V_038004_FMT_BG_RG] = { 2, 1, 4, 0 },
150
151         /* block compressed formats */
152         [V_038004_FMT_BC1] = { 4, 4, 8, 0 },
153         [V_038004_FMT_BC2] = { 4, 4, 16, 0 },
154         [V_038004_FMT_BC3] = { 4, 4, 16, 0 },
155         [V_038004_FMT_BC4] = { 4, 4, 8, 0 },
156         [V_038004_FMT_BC5] = { 4, 4, 16, 0},
157
158 };
159
160 static inline bool fmt_is_valid_color(u32 format)
161 {
162         if (format >= ARRAY_SIZE(color_formats_table))
163                 return false;
164         
165         if (color_formats_table[format].valid_color)
166                 return true;
167
168         return false;
169 }
170
171 static inline bool fmt_is_valid_texture(u32 format)
172 {
173         if (format >= ARRAY_SIZE(color_formats_table))
174                 return false;
175         
176         if (color_formats_table[format].blockwidth > 0)
177                 return true;
178
179         return false;
180 }
181
182 static inline int fmt_get_blocksize(u32 format)
183 {
184         if (format >= ARRAY_SIZE(color_formats_table))
185                 return 0;
186
187         return color_formats_table[format].blocksize;
188 }
189
190 static inline int fmt_get_nblocksx(u32 format, u32 w)
191 {
192         unsigned bw;
193
194         if (format >= ARRAY_SIZE(color_formats_table))
195                 return 0;
196
197         bw = color_formats_table[format].blockwidth;
198         if (bw == 0)
199                 return 0;
200
201         return (w + bw - 1) / bw;
202 }
203
204 static inline int fmt_get_nblocksy(u32 format, u32 h)
205 {
206         unsigned bh;
207
208         if (format >= ARRAY_SIZE(color_formats_table))
209                 return 0;
210
211         bh = color_formats_table[format].blockheight;
212         if (bh == 0)
213                 return 0;
214
215         return (h + bh - 1) / bh;
216 }
217
218 static inline int r600_bpe_from_format(u32 *bpe, u32 format)
219 {
220         unsigned res;
221
222         if (format >= ARRAY_SIZE(color_formats_table))
223                 goto fail;
224
225         res = color_formats_table[format].blocksize;
226         if (res == 0)
227                 goto fail;
228
229         *bpe = res;
230         return 0;
231
232 fail:
233         *bpe = 16;
234         return -EINVAL;
235 }
236
237 struct array_mode_checker {
238         int array_mode;
239         u32 group_size;
240         u32 nbanks;
241         u32 npipes;
242         u32 nsamples;
243         u32 blocksize;
244 };
245
246 /* returns alignment in pixels for pitch/height/depth and bytes for base */
247 static inline int r600_get_array_mode_alignment(struct array_mode_checker *values,
248                                                 u32 *pitch_align,
249                                                 u32 *height_align,
250                                                 u32 *depth_align,
251                                                 u64 *base_align)
252 {
253         u32 tile_width = 8;
254         u32 tile_height = 8;
255         u32 macro_tile_width = values->nbanks;
256         u32 macro_tile_height = values->npipes;
257         u32 tile_bytes = tile_width * tile_height * values->blocksize * values->nsamples;
258         u32 macro_tile_bytes = macro_tile_width * macro_tile_height * tile_bytes;
259
260         switch (values->array_mode) {
261         case ARRAY_LINEAR_GENERAL:
262                 /* technically tile_width/_height for pitch/height */
263                 *pitch_align = 1; /* tile_width */
264                 *height_align = 1; /* tile_height */
265                 *depth_align = 1;
266                 *base_align = 1;
267                 break;
268         case ARRAY_LINEAR_ALIGNED:
269                 *pitch_align = max((u32)64, (u32)(values->group_size / values->blocksize));
270                 *height_align = tile_height;
271                 *depth_align = 1;
272                 *base_align = values->group_size;
273                 break;
274         case ARRAY_1D_TILED_THIN1:
275                 *pitch_align = max((u32)tile_width,
276                                    (u32)(values->group_size /
277                                          (tile_height * values->blocksize * values->nsamples)));
278                 *height_align = tile_height;
279                 *depth_align = 1;
280                 *base_align = values->group_size;
281                 break;
282         case ARRAY_2D_TILED_THIN1:
283                 *pitch_align = max((u32)macro_tile_width,
284                                   (u32)(((values->group_size / tile_height) /
285                                          (values->blocksize * values->nsamples)) *
286                                         values->nbanks)) * tile_width;
287                 *height_align = macro_tile_height * tile_height;
288                 *depth_align = 1;
289                 *base_align = max(macro_tile_bytes,
290                                   (*pitch_align) * values->blocksize * (*height_align) * values->nsamples);
291                 break;
292         default:
293                 return -EINVAL;
294         }
295
296         return 0;
297 }
298
299 static void r600_cs_track_init(struct r600_cs_track *track)
300 {
301         int i;
302
303         /* assume DX9 mode */
304         track->sq_config = DX9_CONSTS;
305         for (i = 0; i < 8; i++) {
306                 track->cb_color_base_last[i] = 0;
307                 track->cb_color_size[i] = 0;
308                 track->cb_color_size_idx[i] = 0;
309                 track->cb_color_info[i] = 0;
310                 track->cb_color_bo[i] = NULL;
311                 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
312                 track->cb_color_bo_mc[i] = 0xFFFFFFFF;
313         }
314         track->cb_target_mask = 0xFFFFFFFF;
315         track->cb_shader_mask = 0xFFFFFFFF;
316         track->db_bo = NULL;
317         track->db_bo_mc = 0xFFFFFFFF;
318         /* assume the biggest format and that htile is enabled */
319         track->db_depth_info = 7 | (1 << 25);
320         track->db_depth_view = 0xFFFFC000;
321         track->db_depth_size = 0xFFFFFFFF;
322         track->db_depth_size_idx = 0;
323         track->db_depth_control = 0xFFFFFFFF;
324 }
325
326 static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
327 {
328         struct r600_cs_track *track = p->track;
329         u32 slice_tile_max, size, tmp;
330         u32 height, height_align, pitch, pitch_align, depth_align;
331         u64 base_offset, base_align;
332         struct array_mode_checker array_check;
333         volatile u32 *ib = p->ib->ptr;
334         unsigned array_mode;
335         u32 format;
336         if (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
337                 dev_warn(p->dev, "FMASK or CMASK buffer are not supported by this kernel\n");
338                 return -EINVAL;
339         }
340         size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i];
341         format = G_0280A0_FORMAT(track->cb_color_info[i]);
342         if (!fmt_is_valid_color(format)) {
343                 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n",
344                          __func__, __LINE__, format,
345                         i, track->cb_color_info[i]);
346                 return -EINVAL;
347         }
348         /* pitch in pixels */
349         pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) * 8;
350         slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1;
351         slice_tile_max *= 64;
352         height = slice_tile_max / pitch;
353         if (height > 8192)
354                 height = 8192;
355         array_mode = G_0280A0_ARRAY_MODE(track->cb_color_info[i]);
356
357         base_offset = track->cb_color_bo_mc[i] + track->cb_color_bo_offset[i];
358         array_check.array_mode = array_mode;
359         array_check.group_size = track->group_size;
360         array_check.nbanks = track->nbanks;
361         array_check.npipes = track->npipes;
362         array_check.nsamples = track->nsamples;
363         array_check.blocksize = fmt_get_blocksize(format);
364         if (r600_get_array_mode_alignment(&array_check,
365                                           &pitch_align, &height_align, &depth_align, &base_align)) {
366                 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
367                          G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
368                          track->cb_color_info[i]);
369                 return -EINVAL;
370         }
371         switch (array_mode) {
372         case V_0280A0_ARRAY_LINEAR_GENERAL:
373                 break;
374         case V_0280A0_ARRAY_LINEAR_ALIGNED:
375                 break;
376         case V_0280A0_ARRAY_1D_TILED_THIN1:
377                 /* avoid breaking userspace */
378                 if (height > 7)
379                         height &= ~0x7;
380                 break;
381         case V_0280A0_ARRAY_2D_TILED_THIN1:
382                 break;
383         default:
384                 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
385                         G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
386                         track->cb_color_info[i]);
387                 return -EINVAL;
388         }
389
390         if (!IS_ALIGNED(pitch, pitch_align)) {
391                 dev_warn(p->dev, "%s:%d cb pitch (%d, 0x%x, %d) invalid\n",
392                          __func__, __LINE__, pitch, pitch_align, array_mode);
393                 return -EINVAL;
394         }
395         if (!IS_ALIGNED(height, height_align)) {
396                 dev_warn(p->dev, "%s:%d cb height (%d, 0x%x, %d) invalid\n",
397                          __func__, __LINE__, height, height_align, array_mode);
398                 return -EINVAL;
399         }
400         if (!IS_ALIGNED(base_offset, base_align)) {
401                 dev_warn(p->dev, "%s offset[%d] 0x%llx 0x%llx, %d not aligned\n", __func__, i,
402                          base_offset, base_align, array_mode);
403                 return -EINVAL;
404         }
405
406         /* check offset */
407         tmp = fmt_get_nblocksy(format, height) * fmt_get_nblocksx(format, pitch) * fmt_get_blocksize(format);
408         if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
409                 if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) {
410                         /* the initial DDX does bad things with the CB size occasionally */
411                         /* it rounds up height too far for slice tile max but the BO is smaller */
412                         /* r600c,g also seem to flush at bad times in some apps resulting in
413                          * bogus values here. So for linear just allow anything to avoid breaking
414                          * broken userspace.
415                          */
416                 } else {
417                         dev_warn(p->dev, "%s offset[%d] %d %d %d %lu too big\n", __func__, i,
418                                  array_mode,
419                                  track->cb_color_bo_offset[i], tmp,
420                                  radeon_bo_size(track->cb_color_bo[i]));
421                         return -EINVAL;
422                 }
423         }
424         /* limit max tile */
425         tmp = (height * pitch) >> 6;
426         if (tmp < slice_tile_max)
427                 slice_tile_max = tmp;
428         tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) |
429                 S_028060_SLICE_TILE_MAX(slice_tile_max - 1);
430         ib[track->cb_color_size_idx[i]] = tmp;
431         return 0;
432 }
433
434 static int r600_cs_track_check(struct radeon_cs_parser *p)
435 {
436         struct r600_cs_track *track = p->track;
437         u32 tmp;
438         int r, i;
439         volatile u32 *ib = p->ib->ptr;
440
441         /* on legacy kernel we don't perform advanced check */
442         if (p->rdev == NULL)
443                 return 0;
444         /* we don't support out buffer yet */
445         if (track->vgt_strmout_en || track->vgt_strmout_buffer_en) {
446                 dev_warn(p->dev, "this kernel doesn't support SMX output buffer\n");
447                 return -EINVAL;
448         }
449         /* check that we have a cb for each enabled target, we don't check
450          * shader_mask because it seems mesa isn't always setting it :(
451          */
452         tmp = track->cb_target_mask;
453         for (i = 0; i < 8; i++) {
454                 if ((tmp >> (i * 4)) & 0xF) {
455                         /* at least one component is enabled */
456                         if (track->cb_color_bo[i] == NULL) {
457                                 dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
458                                         __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
459                                 return -EINVAL;
460                         }
461                         /* perform rewrite of CB_COLOR[0-7]_SIZE */
462                         r = r600_cs_track_validate_cb(p, i);
463                         if (r)
464                                 return r;
465                 }
466         }
467         /* Check depth buffer */
468         if (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
469                 G_028800_Z_ENABLE(track->db_depth_control)) {
470                 u32 nviews, bpe, ntiles, size, slice_tile_max;
471                 u32 height, height_align, pitch, pitch_align, depth_align;
472                 u64 base_offset, base_align;
473                 struct array_mode_checker array_check;
474                 int array_mode;
475
476                 if (track->db_bo == NULL) {
477                         dev_warn(p->dev, "z/stencil with no depth buffer\n");
478                         return -EINVAL;
479                 }
480                 if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) {
481                         dev_warn(p->dev, "this kernel doesn't support z/stencil htile\n");
482                         return -EINVAL;
483                 }
484                 switch (G_028010_FORMAT(track->db_depth_info)) {
485                 case V_028010_DEPTH_16:
486                         bpe = 2;
487                         break;
488                 case V_028010_DEPTH_X8_24:
489                 case V_028010_DEPTH_8_24:
490                 case V_028010_DEPTH_X8_24_FLOAT:
491                 case V_028010_DEPTH_8_24_FLOAT:
492                 case V_028010_DEPTH_32_FLOAT:
493                         bpe = 4;
494                         break;
495                 case V_028010_DEPTH_X24_8_32_FLOAT:
496                         bpe = 8;
497                         break;
498                 default:
499                         dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info));
500                         return -EINVAL;
501                 }
502                 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
503                         if (!track->db_depth_size_idx) {
504                                 dev_warn(p->dev, "z/stencil buffer size not set\n");
505                                 return -EINVAL;
506                         }
507                         tmp = radeon_bo_size(track->db_bo) - track->db_offset;
508                         tmp = (tmp / bpe) >> 6;
509                         if (!tmp) {
510                                 dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n",
511                                                 track->db_depth_size, bpe, track->db_offset,
512                                                 radeon_bo_size(track->db_bo));
513                                 return -EINVAL;
514                         }
515                         ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
516                 } else {
517                         size = radeon_bo_size(track->db_bo);
518                         /* pitch in pixels */
519                         pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8;
520                         slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
521                         slice_tile_max *= 64;
522                         height = slice_tile_max / pitch;
523                         if (height > 8192)
524                                 height = 8192;
525                         base_offset = track->db_bo_mc + track->db_offset;
526                         array_mode = G_028010_ARRAY_MODE(track->db_depth_info);
527                         array_check.array_mode = array_mode;
528                         array_check.group_size = track->group_size;
529                         array_check.nbanks = track->nbanks;
530                         array_check.npipes = track->npipes;
531                         array_check.nsamples = track->nsamples;
532                         array_check.blocksize = bpe;
533                         if (r600_get_array_mode_alignment(&array_check,
534                                                           &pitch_align, &height_align, &depth_align, &base_align)) {
535                                 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
536                                          G_028010_ARRAY_MODE(track->db_depth_info),
537                                          track->db_depth_info);
538                                 return -EINVAL;
539                         }
540                         switch (array_mode) {
541                         case V_028010_ARRAY_1D_TILED_THIN1:
542                                 /* don't break userspace */
543                                 height &= ~0x7;
544                                 break;
545                         case V_028010_ARRAY_2D_TILED_THIN1:
546                                 break;
547                         default:
548                                 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
549                                          G_028010_ARRAY_MODE(track->db_depth_info),
550                                          track->db_depth_info);
551                                 return -EINVAL;
552                         }
553
554                         if (!IS_ALIGNED(pitch, pitch_align)) {
555                                 dev_warn(p->dev, "%s:%d db pitch (%d, 0x%x, %d) invalid\n",
556                                          __func__, __LINE__, pitch, pitch_align, array_mode);
557                                 return -EINVAL;
558                         }
559                         if (!IS_ALIGNED(height, height_align)) {
560                                 dev_warn(p->dev, "%s:%d db height (%d, 0x%x, %d) invalid\n",
561                                          __func__, __LINE__, height, height_align, array_mode);
562                                 return -EINVAL;
563                         }
564                         if (!IS_ALIGNED(base_offset, base_align)) {
565                                 dev_warn(p->dev, "%s offset[%d] 0x%llx, 0x%llx, %d not aligned\n", __func__, i,
566                                          base_offset, base_align, array_mode);
567                                 return -EINVAL;
568                         }
569
570                         ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
571                         nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
572                         tmp = ntiles * bpe * 64 * nviews;
573                         if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
574                                 dev_warn(p->dev, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n",
575                                          array_mode,
576                                          track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
577                                          radeon_bo_size(track->db_bo));
578                                 return -EINVAL;
579                         }
580                 }
581         }
582         return 0;
583 }
584
585 /**
586  * r600_cs_packet_parse() - parse cp packet and point ib index to next packet
587  * @parser:     parser structure holding parsing context.
588  * @pkt:        where to store packet informations
589  *
590  * Assume that chunk_ib_index is properly set. Will return -EINVAL
591  * if packet is bigger than remaining ib size. or if packets is unknown.
592  **/
593 int r600_cs_packet_parse(struct radeon_cs_parser *p,
594                         struct radeon_cs_packet *pkt,
595                         unsigned idx)
596 {
597         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
598         uint32_t header;
599
600         if (idx >= ib_chunk->length_dw) {
601                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
602                           idx, ib_chunk->length_dw);
603                 return -EINVAL;
604         }
605         header = radeon_get_ib_value(p, idx);
606         pkt->idx = idx;
607         pkt->type = CP_PACKET_GET_TYPE(header);
608         pkt->count = CP_PACKET_GET_COUNT(header);
609         pkt->one_reg_wr = 0;
610         switch (pkt->type) {
611         case PACKET_TYPE0:
612                 pkt->reg = CP_PACKET0_GET_REG(header);
613                 break;
614         case PACKET_TYPE3:
615                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
616                 break;
617         case PACKET_TYPE2:
618                 pkt->count = -1;
619                 break;
620         default:
621                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
622                 return -EINVAL;
623         }
624         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
625                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
626                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
627                 return -EINVAL;
628         }
629         return 0;
630 }
631
632 /**
633  * r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3
634  * @parser:             parser structure holding parsing context.
635  * @data:               pointer to relocation data
636  * @offset_start:       starting offset
637  * @offset_mask:        offset mask (to align start offset on)
638  * @reloc:              reloc informations
639  *
640  * Check next packet is relocation packet3, do bo validation and compute
641  * GPU offset using the provided start.
642  **/
643 static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
644                                         struct radeon_cs_reloc **cs_reloc)
645 {
646         struct radeon_cs_chunk *relocs_chunk;
647         struct radeon_cs_packet p3reloc;
648         unsigned idx;
649         int r;
650
651         if (p->chunk_relocs_idx == -1) {
652                 DRM_ERROR("No relocation chunk !\n");
653                 return -EINVAL;
654         }
655         *cs_reloc = NULL;
656         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
657         r = r600_cs_packet_parse(p, &p3reloc, p->idx);
658         if (r) {
659                 return r;
660         }
661         p->idx += p3reloc.count + 2;
662         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
663                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
664                           p3reloc.idx);
665                 return -EINVAL;
666         }
667         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
668         if (idx >= relocs_chunk->length_dw) {
669                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
670                           idx, relocs_chunk->length_dw);
671                 return -EINVAL;
672         }
673         /* FIXME: we assume reloc size is 4 dwords */
674         *cs_reloc = p->relocs_ptr[(idx / 4)];
675         return 0;
676 }
677
678 /**
679  * r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3
680  * @parser:             parser structure holding parsing context.
681  * @data:               pointer to relocation data
682  * @offset_start:       starting offset
683  * @offset_mask:        offset mask (to align start offset on)
684  * @reloc:              reloc informations
685  *
686  * Check next packet is relocation packet3, do bo validation and compute
687  * GPU offset using the provided start.
688  **/
689 static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
690                                         struct radeon_cs_reloc **cs_reloc)
691 {
692         struct radeon_cs_chunk *relocs_chunk;
693         struct radeon_cs_packet p3reloc;
694         unsigned idx;
695         int r;
696
697         if (p->chunk_relocs_idx == -1) {
698                 DRM_ERROR("No relocation chunk !\n");
699                 return -EINVAL;
700         }
701         *cs_reloc = NULL;
702         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
703         r = r600_cs_packet_parse(p, &p3reloc, p->idx);
704         if (r) {
705                 return r;
706         }
707         p->idx += p3reloc.count + 2;
708         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
709                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
710                           p3reloc.idx);
711                 return -EINVAL;
712         }
713         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
714         if (idx >= relocs_chunk->length_dw) {
715                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
716                           idx, relocs_chunk->length_dw);
717                 return -EINVAL;
718         }
719         *cs_reloc = p->relocs;
720         (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32;
721         (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
722         return 0;
723 }
724
725 /**
726  * r600_cs_packet_next_is_pkt3_nop() - test if next packet is packet3 nop for reloc
727  * @parser:             parser structure holding parsing context.
728  *
729  * Check next packet is relocation packet3, do bo validation and compute
730  * GPU offset using the provided start.
731  **/
732 static inline int r600_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
733 {
734         struct radeon_cs_packet p3reloc;
735         int r;
736
737         r = r600_cs_packet_parse(p, &p3reloc, p->idx);
738         if (r) {
739                 return 0;
740         }
741         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
742                 return 0;
743         }
744         return 1;
745 }
746
747 /**
748  * r600_cs_packet_next_vline() - parse userspace VLINE packet
749  * @parser:             parser structure holding parsing context.
750  *
751  * Userspace sends a special sequence for VLINE waits.
752  * PACKET0 - VLINE_START_END + value
753  * PACKET3 - WAIT_REG_MEM poll vline status reg
754  * RELOC (P3) - crtc_id in reloc.
755  *
756  * This function parses this and relocates the VLINE START END
757  * and WAIT_REG_MEM packets to the correct crtc.
758  * It also detects a switched off crtc and nulls out the
759  * wait in that case.
760  */
761 static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
762 {
763         struct drm_mode_object *obj;
764         struct drm_crtc *crtc;
765         struct radeon_crtc *radeon_crtc;
766         struct radeon_cs_packet p3reloc, wait_reg_mem;
767         int crtc_id;
768         int r;
769         uint32_t header, h_idx, reg, wait_reg_mem_info;
770         volatile uint32_t *ib;
771
772         ib = p->ib->ptr;
773
774         /* parse the WAIT_REG_MEM */
775         r = r600_cs_packet_parse(p, &wait_reg_mem, p->idx);
776         if (r)
777                 return r;
778
779         /* check its a WAIT_REG_MEM */
780         if (wait_reg_mem.type != PACKET_TYPE3 ||
781             wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
782                 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
783                 r = -EINVAL;
784                 return r;
785         }
786
787         wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
788         /* bit 4 is reg (0) or mem (1) */
789         if (wait_reg_mem_info & 0x10) {
790                 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n");
791                 r = -EINVAL;
792                 return r;
793         }
794         /* waiting for value to be equal */
795         if ((wait_reg_mem_info & 0x7) != 0x3) {
796                 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
797                 r = -EINVAL;
798                 return r;
799         }
800         if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != AVIVO_D1MODE_VLINE_STATUS) {
801                 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
802                 r = -EINVAL;
803                 return r;
804         }
805
806         if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != AVIVO_D1MODE_VLINE_STAT) {
807                 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
808                 r = -EINVAL;
809                 return r;
810         }
811
812         /* jump over the NOP */
813         r = r600_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);
814         if (r)
815                 return r;
816
817         h_idx = p->idx - 2;
818         p->idx += wait_reg_mem.count + 2;
819         p->idx += p3reloc.count + 2;
820
821         header = radeon_get_ib_value(p, h_idx);
822         crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
823         reg = CP_PACKET0_GET_REG(header);
824
825         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
826         if (!obj) {
827                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
828                 r = -EINVAL;
829                 goto out;
830         }
831         crtc = obj_to_crtc(obj);
832         radeon_crtc = to_radeon_crtc(crtc);
833         crtc_id = radeon_crtc->crtc_id;
834
835         if (!crtc->enabled) {
836                 /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
837                 ib[h_idx + 2] = PACKET2(0);
838                 ib[h_idx + 3] = PACKET2(0);
839                 ib[h_idx + 4] = PACKET2(0);
840                 ib[h_idx + 5] = PACKET2(0);
841                 ib[h_idx + 6] = PACKET2(0);
842                 ib[h_idx + 7] = PACKET2(0);
843                 ib[h_idx + 8] = PACKET2(0);
844         } else if (crtc_id == 1) {
845                 switch (reg) {
846                 case AVIVO_D1MODE_VLINE_START_END:
847                         header &= ~R600_CP_PACKET0_REG_MASK;
848                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
849                         break;
850                 default:
851                         DRM_ERROR("unknown crtc reloc\n");
852                         r = -EINVAL;
853                         goto out;
854                 }
855                 ib[h_idx] = header;
856                 ib[h_idx + 4] = AVIVO_D2MODE_VLINE_STATUS >> 2;
857         }
858 out:
859         return r;
860 }
861
862 static int r600_packet0_check(struct radeon_cs_parser *p,
863                                 struct radeon_cs_packet *pkt,
864                                 unsigned idx, unsigned reg)
865 {
866         int r;
867
868         switch (reg) {
869         case AVIVO_D1MODE_VLINE_START_END:
870                 r = r600_cs_packet_parse_vline(p);
871                 if (r) {
872                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
873                                         idx, reg);
874                         return r;
875                 }
876                 break;
877         default:
878                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
879                        reg, idx);
880                 return -EINVAL;
881         }
882         return 0;
883 }
884
885 static int r600_cs_parse_packet0(struct radeon_cs_parser *p,
886                                 struct radeon_cs_packet *pkt)
887 {
888         unsigned reg, i;
889         unsigned idx;
890         int r;
891
892         idx = pkt->idx + 1;
893         reg = pkt->reg;
894         for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
895                 r = r600_packet0_check(p, pkt, idx, reg);
896                 if (r) {
897                         return r;
898                 }
899         }
900         return 0;
901 }
902
903 /**
904  * r600_cs_check_reg() - check if register is authorized or not
905  * @parser: parser structure holding parsing context
906  * @reg: register we are testing
907  * @idx: index into the cs buffer
908  *
909  * This function will test against r600_reg_safe_bm and return 0
910  * if register is safe. If register is not flag as safe this function
911  * will test it against a list of register needind special handling.
912  */
913 static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
914 {
915         struct r600_cs_track *track = (struct r600_cs_track *)p->track;
916         struct radeon_cs_reloc *reloc;
917         u32 last_reg = ARRAY_SIZE(r600_reg_safe_bm);
918         u32 m, i, tmp, *ib;
919         int r;
920
921         i = (reg >> 7);
922         if (i > last_reg) {
923                 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
924                 return -EINVAL;
925         }
926         m = 1 << ((reg >> 2) & 31);
927         if (!(r600_reg_safe_bm[i] & m))
928                 return 0;
929         ib = p->ib->ptr;
930         switch (reg) {
931         /* force following reg to 0 in an attemp to disable out buffer
932          * which will need us to better understand how it works to perform
933          * security check on it (Jerome)
934          */
935         case R_0288A8_SQ_ESGS_RING_ITEMSIZE:
936         case R_008C44_SQ_ESGS_RING_SIZE:
937         case R_0288B0_SQ_ESTMP_RING_ITEMSIZE:
938         case R_008C54_SQ_ESTMP_RING_SIZE:
939         case R_0288C0_SQ_FBUF_RING_ITEMSIZE:
940         case R_008C74_SQ_FBUF_RING_SIZE:
941         case R_0288B4_SQ_GSTMP_RING_ITEMSIZE:
942         case R_008C5C_SQ_GSTMP_RING_SIZE:
943         case R_0288AC_SQ_GSVS_RING_ITEMSIZE:
944         case R_008C4C_SQ_GSVS_RING_SIZE:
945         case R_0288BC_SQ_PSTMP_RING_ITEMSIZE:
946         case R_008C6C_SQ_PSTMP_RING_SIZE:
947         case R_0288C4_SQ_REDUC_RING_ITEMSIZE:
948         case R_008C7C_SQ_REDUC_RING_SIZE:
949         case R_0288B8_SQ_VSTMP_RING_ITEMSIZE:
950         case R_008C64_SQ_VSTMP_RING_SIZE:
951         case R_0288C8_SQ_GS_VERT_ITEMSIZE:
952                 /* get value to populate the IB don't remove */
953                 tmp =radeon_get_ib_value(p, idx);
954                 ib[idx] = 0;
955                 break;
956         case SQ_CONFIG:
957                 track->sq_config = radeon_get_ib_value(p, idx);
958                 break;
959         case R_028800_DB_DEPTH_CONTROL:
960                 track->db_depth_control = radeon_get_ib_value(p, idx);
961                 break;
962         case R_028010_DB_DEPTH_INFO:
963                 if (r600_cs_packet_next_is_pkt3_nop(p)) {
964                         r = r600_cs_packet_next_reloc(p, &reloc);
965                         if (r) {
966                                 dev_warn(p->dev, "bad SET_CONTEXT_REG "
967                                          "0x%04X\n", reg);
968                                 return -EINVAL;
969                         }
970                         track->db_depth_info = radeon_get_ib_value(p, idx);
971                         ib[idx] &= C_028010_ARRAY_MODE;
972                         track->db_depth_info &= C_028010_ARRAY_MODE;
973                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
974                                 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
975                                 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
976                         } else {
977                                 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
978                                 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
979                         }
980                 } else
981                         track->db_depth_info = radeon_get_ib_value(p, idx);
982                 break;
983         case R_028004_DB_DEPTH_VIEW:
984                 track->db_depth_view = radeon_get_ib_value(p, idx);
985                 break;
986         case R_028000_DB_DEPTH_SIZE:
987                 track->db_depth_size = radeon_get_ib_value(p, idx);
988                 track->db_depth_size_idx = idx;
989                 break;
990         case R_028AB0_VGT_STRMOUT_EN:
991                 track->vgt_strmout_en = radeon_get_ib_value(p, idx);
992                 break;
993         case R_028B20_VGT_STRMOUT_BUFFER_EN:
994                 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx);
995                 break;
996         case R_028238_CB_TARGET_MASK:
997                 track->cb_target_mask = radeon_get_ib_value(p, idx);
998                 break;
999         case R_02823C_CB_SHADER_MASK:
1000                 track->cb_shader_mask = radeon_get_ib_value(p, idx);
1001                 break;
1002         case R_028C04_PA_SC_AA_CONFIG:
1003                 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));
1004                 track->nsamples = 1 << tmp;
1005                 break;
1006         case R_0280A0_CB_COLOR0_INFO:
1007         case R_0280A4_CB_COLOR1_INFO:
1008         case R_0280A8_CB_COLOR2_INFO:
1009         case R_0280AC_CB_COLOR3_INFO:
1010         case R_0280B0_CB_COLOR4_INFO:
1011         case R_0280B4_CB_COLOR5_INFO:
1012         case R_0280B8_CB_COLOR6_INFO:
1013         case R_0280BC_CB_COLOR7_INFO:
1014                 if (r600_cs_packet_next_is_pkt3_nop(p)) {
1015                         r = r600_cs_packet_next_reloc(p, &reloc);
1016                         if (r) {
1017                                 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1018                                 return -EINVAL;
1019                         }
1020                         tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
1021                         track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1022                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1023                                 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
1024                                 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
1025                         } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
1026                                 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
1027                                 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
1028                         }
1029                 } else {
1030                         tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
1031                         track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1032                 }
1033                 break;
1034         case R_028060_CB_COLOR0_SIZE:
1035         case R_028064_CB_COLOR1_SIZE:
1036         case R_028068_CB_COLOR2_SIZE:
1037         case R_02806C_CB_COLOR3_SIZE:
1038         case R_028070_CB_COLOR4_SIZE:
1039         case R_028074_CB_COLOR5_SIZE:
1040         case R_028078_CB_COLOR6_SIZE:
1041         case R_02807C_CB_COLOR7_SIZE:
1042                 tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4;
1043                 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx);
1044                 track->cb_color_size_idx[tmp] = idx;
1045                 break;
1046                 /* This register were added late, there is userspace
1047                  * which does provide relocation for those but set
1048                  * 0 offset. In order to avoid breaking old userspace
1049                  * we detect this and set address to point to last
1050                  * CB_COLOR0_BASE, note that if userspace doesn't set
1051                  * CB_COLOR0_BASE before this register we will report
1052                  * error. Old userspace always set CB_COLOR0_BASE
1053                  * before any of this.
1054                  */
1055         case R_0280E0_CB_COLOR0_FRAG:
1056         case R_0280E4_CB_COLOR1_FRAG:
1057         case R_0280E8_CB_COLOR2_FRAG:
1058         case R_0280EC_CB_COLOR3_FRAG:
1059         case R_0280F0_CB_COLOR4_FRAG:
1060         case R_0280F4_CB_COLOR5_FRAG:
1061         case R_0280F8_CB_COLOR6_FRAG:
1062         case R_0280FC_CB_COLOR7_FRAG:
1063                 tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4;
1064                 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
1065                         if (!track->cb_color_base_last[tmp]) {
1066                                 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1067                                 return -EINVAL;
1068                         }
1069                         ib[idx] = track->cb_color_base_last[tmp];
1070                         track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];
1071                 } else {
1072                         r = r600_cs_packet_next_reloc(p, &reloc);
1073                         if (r) {
1074                                 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1075                                 return -EINVAL;
1076                         }
1077                         ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1078                         track->cb_color_frag_bo[tmp] = reloc->robj;
1079                 }
1080                 break;
1081         case R_0280C0_CB_COLOR0_TILE:
1082         case R_0280C4_CB_COLOR1_TILE:
1083         case R_0280C8_CB_COLOR2_TILE:
1084         case R_0280CC_CB_COLOR3_TILE:
1085         case R_0280D0_CB_COLOR4_TILE:
1086         case R_0280D4_CB_COLOR5_TILE:
1087         case R_0280D8_CB_COLOR6_TILE:
1088         case R_0280DC_CB_COLOR7_TILE:
1089                 tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4;
1090                 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
1091                         if (!track->cb_color_base_last[tmp]) {
1092                                 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1093                                 return -EINVAL;
1094                         }
1095                         ib[idx] = track->cb_color_base_last[tmp];
1096                         track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];
1097                 } else {
1098                         r = r600_cs_packet_next_reloc(p, &reloc);
1099                         if (r) {
1100                                 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1101                                 return -EINVAL;
1102                         }
1103                         ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1104                         track->cb_color_tile_bo[tmp] = reloc->robj;
1105                 }
1106                 break;
1107         case CB_COLOR0_BASE:
1108         case CB_COLOR1_BASE:
1109         case CB_COLOR2_BASE:
1110         case CB_COLOR3_BASE:
1111         case CB_COLOR4_BASE:
1112         case CB_COLOR5_BASE:
1113         case CB_COLOR6_BASE:
1114         case CB_COLOR7_BASE:
1115                 r = r600_cs_packet_next_reloc(p, &reloc);
1116                 if (r) {
1117                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1118                                         "0x%04X\n", reg);
1119                         return -EINVAL;
1120                 }
1121                 tmp = (reg - CB_COLOR0_BASE) / 4;
1122                 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1123                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1124                 track->cb_color_base_last[tmp] = ib[idx];
1125                 track->cb_color_bo[tmp] = reloc->robj;
1126                 track->cb_color_bo_mc[tmp] = reloc->lobj.gpu_offset;
1127                 break;
1128         case DB_DEPTH_BASE:
1129                 r = r600_cs_packet_next_reloc(p, &reloc);
1130                 if (r) {
1131                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1132                                         "0x%04X\n", reg);
1133                         return -EINVAL;
1134                 }
1135                 track->db_offset = radeon_get_ib_value(p, idx) << 8;
1136                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1137                 track->db_bo = reloc->robj;
1138                 track->db_bo_mc = reloc->lobj.gpu_offset;
1139                 break;
1140         case DB_HTILE_DATA_BASE:
1141         case SQ_PGM_START_FS:
1142         case SQ_PGM_START_ES:
1143         case SQ_PGM_START_VS:
1144         case SQ_PGM_START_GS:
1145         case SQ_PGM_START_PS:
1146         case SQ_ALU_CONST_CACHE_GS_0:
1147         case SQ_ALU_CONST_CACHE_GS_1:
1148         case SQ_ALU_CONST_CACHE_GS_2:
1149         case SQ_ALU_CONST_CACHE_GS_3:
1150         case SQ_ALU_CONST_CACHE_GS_4:
1151         case SQ_ALU_CONST_CACHE_GS_5:
1152         case SQ_ALU_CONST_CACHE_GS_6:
1153         case SQ_ALU_CONST_CACHE_GS_7:
1154         case SQ_ALU_CONST_CACHE_GS_8:
1155         case SQ_ALU_CONST_CACHE_GS_9:
1156         case SQ_ALU_CONST_CACHE_GS_10:
1157         case SQ_ALU_CONST_CACHE_GS_11:
1158         case SQ_ALU_CONST_CACHE_GS_12:
1159         case SQ_ALU_CONST_CACHE_GS_13:
1160         case SQ_ALU_CONST_CACHE_GS_14:
1161         case SQ_ALU_CONST_CACHE_GS_15:
1162         case SQ_ALU_CONST_CACHE_PS_0:
1163         case SQ_ALU_CONST_CACHE_PS_1:
1164         case SQ_ALU_CONST_CACHE_PS_2:
1165         case SQ_ALU_CONST_CACHE_PS_3:
1166         case SQ_ALU_CONST_CACHE_PS_4:
1167         case SQ_ALU_CONST_CACHE_PS_5:
1168         case SQ_ALU_CONST_CACHE_PS_6:
1169         case SQ_ALU_CONST_CACHE_PS_7:
1170         case SQ_ALU_CONST_CACHE_PS_8:
1171         case SQ_ALU_CONST_CACHE_PS_9:
1172         case SQ_ALU_CONST_CACHE_PS_10:
1173         case SQ_ALU_CONST_CACHE_PS_11:
1174         case SQ_ALU_CONST_CACHE_PS_12:
1175         case SQ_ALU_CONST_CACHE_PS_13:
1176         case SQ_ALU_CONST_CACHE_PS_14:
1177         case SQ_ALU_CONST_CACHE_PS_15:
1178         case SQ_ALU_CONST_CACHE_VS_0:
1179         case SQ_ALU_CONST_CACHE_VS_1:
1180         case SQ_ALU_CONST_CACHE_VS_2:
1181         case SQ_ALU_CONST_CACHE_VS_3:
1182         case SQ_ALU_CONST_CACHE_VS_4:
1183         case SQ_ALU_CONST_CACHE_VS_5:
1184         case SQ_ALU_CONST_CACHE_VS_6:
1185         case SQ_ALU_CONST_CACHE_VS_7:
1186         case SQ_ALU_CONST_CACHE_VS_8:
1187         case SQ_ALU_CONST_CACHE_VS_9:
1188         case SQ_ALU_CONST_CACHE_VS_10:
1189         case SQ_ALU_CONST_CACHE_VS_11:
1190         case SQ_ALU_CONST_CACHE_VS_12:
1191         case SQ_ALU_CONST_CACHE_VS_13:
1192         case SQ_ALU_CONST_CACHE_VS_14:
1193         case SQ_ALU_CONST_CACHE_VS_15:
1194                 r = r600_cs_packet_next_reloc(p, &reloc);
1195                 if (r) {
1196                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1197                                         "0x%04X\n", reg);
1198                         return -EINVAL;
1199                 }
1200                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1201                 break;
1202         default:
1203                 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1204                 return -EINVAL;
1205         }
1206         return 0;
1207 }
1208
1209 static inline unsigned mip_minify(unsigned size, unsigned level)
1210 {
1211         unsigned val;
1212
1213         val = max(1U, size >> level);
1214         if (level > 0)
1215                 val = roundup_pow_of_two(val);
1216         return val;
1217 }
1218
1219 static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel,
1220                               unsigned w0, unsigned h0, unsigned d0, unsigned format,
1221                               unsigned block_align, unsigned height_align, unsigned base_align,
1222                               unsigned *l0_size, unsigned *mipmap_size)
1223 {
1224         unsigned offset, i, level;
1225         unsigned width, height, depth, size;
1226         unsigned blocksize;
1227         unsigned nbx, nby;
1228         unsigned nlevels = llevel - blevel + 1;
1229
1230         *l0_size = -1;
1231         blocksize = fmt_get_blocksize(format);
1232
1233         w0 = mip_minify(w0, 0);
1234         h0 = mip_minify(h0, 0);
1235         d0 = mip_minify(d0, 0);
1236         for(i = 0, offset = 0, level = blevel; i < nlevels; i++, level++) {
1237                 width = mip_minify(w0, i);
1238                 nbx = fmt_get_nblocksx(format, width);
1239
1240                 nbx = round_up(nbx, block_align);
1241
1242                 height = mip_minify(h0, i);
1243                 nby = fmt_get_nblocksy(format, height);
1244                 nby = round_up(nby, height_align);
1245
1246                 depth = mip_minify(d0, i);
1247
1248                 size = nbx * nby * blocksize;
1249                 if (nfaces)
1250                         size *= nfaces;
1251                 else
1252                         size *= depth;
1253
1254                 if (i == 0)
1255                         *l0_size = size;
1256
1257                 if (i == 0 || i == 1)
1258                         offset = round_up(offset, base_align);
1259
1260                 offset += size;
1261         }
1262         *mipmap_size = offset;
1263         if (llevel == 0)
1264                 *mipmap_size = *l0_size;
1265         if (!blevel)
1266                 *mipmap_size -= *l0_size;
1267 }
1268
1269 /**
1270  * r600_check_texture_resource() - check if register is authorized or not
1271  * @p: parser structure holding parsing context
1272  * @idx: index into the cs buffer
1273  * @texture: texture's bo structure
1274  * @mipmap: mipmap's bo structure
1275  *
1276  * This function will check that the resource has valid field and that
1277  * the texture and mipmap bo object are big enough to cover this resource.
1278  */
1279 static inline int r600_check_texture_resource(struct radeon_cs_parser *p,  u32 idx,
1280                                               struct radeon_bo *texture,
1281                                               struct radeon_bo *mipmap,
1282                                               u64 base_offset,
1283                                               u64 mip_offset,
1284                                               u32 tiling_flags)
1285 {
1286         struct r600_cs_track *track = p->track;
1287         u32 nfaces, llevel, blevel, w0, h0, d0;
1288         u32 word0, word1, l0_size, mipmap_size, word2, word3;
1289         u32 height_align, pitch, pitch_align, depth_align;
1290         u32 array, barray, larray;
1291         u64 base_align;
1292         struct array_mode_checker array_check;
1293         u32 format;
1294
1295         /* on legacy kernel we don't perform advanced check */
1296         if (p->rdev == NULL)
1297                 return 0;
1298
1299         /* convert to bytes */
1300         base_offset <<= 8;
1301         mip_offset <<= 8;
1302
1303         word0 = radeon_get_ib_value(p, idx + 0);
1304         if (tiling_flags & RADEON_TILING_MACRO)
1305                 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1306         else if (tiling_flags & RADEON_TILING_MICRO)
1307                 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1308         word1 = radeon_get_ib_value(p, idx + 1);
1309         w0 = G_038000_TEX_WIDTH(word0) + 1;
1310         h0 = G_038004_TEX_HEIGHT(word1) + 1;
1311         d0 = G_038004_TEX_DEPTH(word1);
1312         nfaces = 1;
1313         switch (G_038000_DIM(word0)) {
1314         case V_038000_SQ_TEX_DIM_1D:
1315         case V_038000_SQ_TEX_DIM_2D:
1316         case V_038000_SQ_TEX_DIM_3D:
1317                 break;
1318         case V_038000_SQ_TEX_DIM_CUBEMAP:
1319                 if (p->family >= CHIP_RV770)
1320                         nfaces = 8;
1321                 else
1322                         nfaces = 6;
1323                 break;
1324         case V_038000_SQ_TEX_DIM_1D_ARRAY:
1325         case V_038000_SQ_TEX_DIM_2D_ARRAY:
1326                 array = 1;
1327                 break;
1328         case V_038000_SQ_TEX_DIM_2D_MSAA:
1329         case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA:
1330         default:
1331                 dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0));
1332                 return -EINVAL;
1333         }
1334         format = G_038004_DATA_FORMAT(word1);
1335         if (!fmt_is_valid_texture(format)) {
1336                 dev_warn(p->dev, "%s:%d texture invalid format %d\n",
1337                          __func__, __LINE__, format);
1338                 return -EINVAL;
1339         }
1340
1341         /* pitch in texels */
1342         pitch = (G_038000_PITCH(word0) + 1) * 8;
1343         array_check.array_mode = G_038000_TILE_MODE(word0);
1344         array_check.group_size = track->group_size;
1345         array_check.nbanks = track->nbanks;
1346         array_check.npipes = track->npipes;
1347         array_check.nsamples = 1;
1348         array_check.blocksize = fmt_get_blocksize(format);
1349         if (r600_get_array_mode_alignment(&array_check,
1350                                           &pitch_align, &height_align, &depth_align, &base_align)) {
1351                 dev_warn(p->dev, "%s:%d tex array mode (%d) invalid\n",
1352                          __func__, __LINE__, G_038000_TILE_MODE(word0));
1353                 return -EINVAL;
1354         }
1355
1356         /* XXX check height as well... */
1357
1358         if (!IS_ALIGNED(pitch, pitch_align)) {
1359                 dev_warn(p->dev, "%s:%d tex pitch (%d, 0x%x, %d) invalid\n",
1360                          __func__, __LINE__, pitch, pitch_align, G_038000_TILE_MODE(word0));
1361                 return -EINVAL;
1362         }
1363         if (!IS_ALIGNED(base_offset, base_align)) {
1364                 dev_warn(p->dev, "%s:%d tex base offset (0x%llx, 0x%llx, %d) invalid\n",
1365                          __func__, __LINE__, base_offset, base_align, G_038000_TILE_MODE(word0));
1366                 return -EINVAL;
1367         }
1368         if (!IS_ALIGNED(mip_offset, base_align)) {
1369                 dev_warn(p->dev, "%s:%d tex mip offset (0x%llx, 0x%llx, %d) invalid\n",
1370                          __func__, __LINE__, mip_offset, base_align, G_038000_TILE_MODE(word0));
1371                 return -EINVAL;
1372         }
1373
1374         word2 = radeon_get_ib_value(p, idx + 2) << 8;
1375         word3 = radeon_get_ib_value(p, idx + 3) << 8;
1376
1377         word0 = radeon_get_ib_value(p, idx + 4);
1378         word1 = radeon_get_ib_value(p, idx + 5);
1379         blevel = G_038010_BASE_LEVEL(word0);
1380         llevel = G_038014_LAST_LEVEL(word1);
1381         if (array == 1) {
1382                 barray = G_038014_BASE_ARRAY(word1);
1383                 larray = G_038014_LAST_ARRAY(word1);
1384
1385                 nfaces = larray - barray + 1;
1386         }
1387         r600_texture_size(nfaces, blevel, llevel, w0, h0, d0, format,
1388                           pitch_align, height_align, base_align,
1389                           &l0_size, &mipmap_size);
1390         /* using get ib will give us the offset into the texture bo */
1391         if ((l0_size + word2) > radeon_bo_size(texture)) {
1392                 dev_warn(p->dev, "texture bo too small (%d %d %d %d -> %d have %ld)\n",
1393                         w0, h0, format, word2, l0_size, radeon_bo_size(texture));
1394                 dev_warn(p->dev, "alignments %d %d %d %lld\n", pitch, pitch_align, height_align, base_align);
1395                 return -EINVAL;
1396         }
1397         /* using get ib will give us the offset into the mipmap bo */
1398         word3 = radeon_get_ib_value(p, idx + 3) << 8;
1399         if ((mipmap_size + word3) > radeon_bo_size(mipmap)) {
1400                 /*dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n",
1401                   w0, h0, format, blevel, nlevels, word3, mipmap_size, radeon_bo_size(texture));*/
1402         }
1403         return 0;
1404 }
1405
1406 static int r600_packet3_check(struct radeon_cs_parser *p,
1407                                 struct radeon_cs_packet *pkt)
1408 {
1409         struct radeon_cs_reloc *reloc;
1410         struct r600_cs_track *track;
1411         volatile u32 *ib;
1412         unsigned idx;
1413         unsigned i;
1414         unsigned start_reg, end_reg, reg;
1415         int r;
1416         u32 idx_value;
1417
1418         track = (struct r600_cs_track *)p->track;
1419         ib = p->ib->ptr;
1420         idx = pkt->idx + 1;
1421         idx_value = radeon_get_ib_value(p, idx);
1422
1423         switch (pkt->opcode) {
1424         case PACKET3_SET_PREDICATION:
1425         {
1426                 int pred_op;
1427                 int tmp;
1428                 if (pkt->count != 1) {
1429                         DRM_ERROR("bad SET PREDICATION\n");
1430                         return -EINVAL;
1431                 }
1432
1433                 tmp = radeon_get_ib_value(p, idx + 1);
1434                 pred_op = (tmp >> 16) & 0x7;
1435
1436                 /* for the clear predicate operation */
1437                 if (pred_op == 0)
1438                         return 0;
1439
1440                 if (pred_op > 2) {
1441                         DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op);
1442                         return -EINVAL;
1443                 }
1444
1445                 r = r600_cs_packet_next_reloc(p, &reloc);
1446                 if (r) {
1447                         DRM_ERROR("bad SET PREDICATION\n");
1448                         return -EINVAL;
1449                 }
1450
1451                 ib[idx + 0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1452                 ib[idx + 1] = tmp + (upper_32_bits(reloc->lobj.gpu_offset) & 0xff);
1453         }
1454         break;
1455
1456         case PACKET3_START_3D_CMDBUF:
1457                 if (p->family >= CHIP_RV770 || pkt->count) {
1458                         DRM_ERROR("bad START_3D\n");
1459                         return -EINVAL;
1460                 }
1461                 break;
1462         case PACKET3_CONTEXT_CONTROL:
1463                 if (pkt->count != 1) {
1464                         DRM_ERROR("bad CONTEXT_CONTROL\n");
1465                         return -EINVAL;
1466                 }
1467                 break;
1468         case PACKET3_INDEX_TYPE:
1469         case PACKET3_NUM_INSTANCES:
1470                 if (pkt->count) {
1471                         DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n");
1472                         return -EINVAL;
1473                 }
1474                 break;
1475         case PACKET3_DRAW_INDEX:
1476                 if (pkt->count != 3) {
1477                         DRM_ERROR("bad DRAW_INDEX\n");
1478                         return -EINVAL;
1479                 }
1480                 r = r600_cs_packet_next_reloc(p, &reloc);
1481                 if (r) {
1482                         DRM_ERROR("bad DRAW_INDEX\n");
1483                         return -EINVAL;
1484                 }
1485                 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1486                 ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1487                 r = r600_cs_track_check(p);
1488                 if (r) {
1489                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1490                         return r;
1491                 }
1492                 break;
1493         case PACKET3_DRAW_INDEX_AUTO:
1494                 if (pkt->count != 1) {
1495                         DRM_ERROR("bad DRAW_INDEX_AUTO\n");
1496                         return -EINVAL;
1497                 }
1498                 r = r600_cs_track_check(p);
1499                 if (r) {
1500                         dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
1501                         return r;
1502                 }
1503                 break;
1504         case PACKET3_DRAW_INDEX_IMMD_BE:
1505         case PACKET3_DRAW_INDEX_IMMD:
1506                 if (pkt->count < 2) {
1507                         DRM_ERROR("bad DRAW_INDEX_IMMD\n");
1508                         return -EINVAL;
1509                 }
1510                 r = r600_cs_track_check(p);
1511                 if (r) {
1512                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1513                         return r;
1514                 }
1515                 break;
1516         case PACKET3_WAIT_REG_MEM:
1517                 if (pkt->count != 5) {
1518                         DRM_ERROR("bad WAIT_REG_MEM\n");
1519                         return -EINVAL;
1520                 }
1521                 /* bit 4 is reg (0) or mem (1) */
1522                 if (idx_value & 0x10) {
1523                         r = r600_cs_packet_next_reloc(p, &reloc);
1524                         if (r) {
1525                                 DRM_ERROR("bad WAIT_REG_MEM\n");
1526                                 return -EINVAL;
1527                         }
1528                         ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1529                         ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1530                 }
1531                 break;
1532         case PACKET3_SURFACE_SYNC:
1533                 if (pkt->count != 3) {
1534                         DRM_ERROR("bad SURFACE_SYNC\n");
1535                         return -EINVAL;
1536                 }
1537                 /* 0xffffffff/0x0 is flush all cache flag */
1538                 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
1539                     radeon_get_ib_value(p, idx + 2) != 0) {
1540                         r = r600_cs_packet_next_reloc(p, &reloc);
1541                         if (r) {
1542                                 DRM_ERROR("bad SURFACE_SYNC\n");
1543                                 return -EINVAL;
1544                         }
1545                         ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1546                 }
1547                 break;
1548         case PACKET3_EVENT_WRITE:
1549                 if (pkt->count != 2 && pkt->count != 0) {
1550                         DRM_ERROR("bad EVENT_WRITE\n");
1551                         return -EINVAL;
1552                 }
1553                 if (pkt->count) {
1554                         r = r600_cs_packet_next_reloc(p, &reloc);
1555                         if (r) {
1556                                 DRM_ERROR("bad EVENT_WRITE\n");
1557                                 return -EINVAL;
1558                         }
1559                         ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1560                         ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1561                 }
1562                 break;
1563         case PACKET3_EVENT_WRITE_EOP:
1564                 if (pkt->count != 4) {
1565                         DRM_ERROR("bad EVENT_WRITE_EOP\n");
1566                         return -EINVAL;
1567                 }
1568                 r = r600_cs_packet_next_reloc(p, &reloc);
1569                 if (r) {
1570                         DRM_ERROR("bad EVENT_WRITE\n");
1571                         return -EINVAL;
1572                 }
1573                 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1574                 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1575                 break;
1576         case PACKET3_SET_CONFIG_REG:
1577                 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
1578                 end_reg = 4 * pkt->count + start_reg - 4;
1579                 if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) ||
1580                     (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
1581                     (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
1582                         DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
1583                         return -EINVAL;
1584                 }
1585                 for (i = 0; i < pkt->count; i++) {
1586                         reg = start_reg + (4 * i);
1587                         r = r600_cs_check_reg(p, reg, idx+1+i);
1588                         if (r)
1589                                 return r;
1590                 }
1591                 break;
1592         case PACKET3_SET_CONTEXT_REG:
1593                 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET;
1594                 end_reg = 4 * pkt->count + start_reg - 4;
1595                 if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) ||
1596                     (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
1597                     (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
1598                         DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
1599                         return -EINVAL;
1600                 }
1601                 for (i = 0; i < pkt->count; i++) {
1602                         reg = start_reg + (4 * i);
1603                         r = r600_cs_check_reg(p, reg, idx+1+i);
1604                         if (r)
1605                                 return r;
1606                 }
1607                 break;
1608         case PACKET3_SET_RESOURCE:
1609                 if (pkt->count % 7) {
1610                         DRM_ERROR("bad SET_RESOURCE\n");
1611                         return -EINVAL;
1612                 }
1613                 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET;
1614                 end_reg = 4 * pkt->count + start_reg - 4;
1615                 if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) ||
1616                     (start_reg >= PACKET3_SET_RESOURCE_END) ||
1617                     (end_reg >= PACKET3_SET_RESOURCE_END)) {
1618                         DRM_ERROR("bad SET_RESOURCE\n");
1619                         return -EINVAL;
1620                 }
1621                 for (i = 0; i < (pkt->count / 7); i++) {
1622                         struct radeon_bo *texture, *mipmap;
1623                         u32 size, offset, base_offset, mip_offset;
1624
1625                         switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) {
1626                         case SQ_TEX_VTX_VALID_TEXTURE:
1627                                 /* tex base */
1628                                 r = r600_cs_packet_next_reloc(p, &reloc);
1629                                 if (r) {
1630                                         DRM_ERROR("bad SET_RESOURCE\n");
1631                                         return -EINVAL;
1632                                 }
1633                                 base_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1634                                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1635                                         ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1636                                 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1637                                         ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1638                                 texture = reloc->robj;
1639                                 /* tex mip base */
1640                                 r = r600_cs_packet_next_reloc(p, &reloc);
1641                                 if (r) {
1642                                         DRM_ERROR("bad SET_RESOURCE\n");
1643                                         return -EINVAL;
1644                                 }
1645                                 mip_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1646                                 mipmap = reloc->robj;
1647                                 r = r600_check_texture_resource(p,  idx+(i*7)+1,
1648                                                                 texture, mipmap,
1649                                                                 base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2),
1650                                                                 mip_offset + radeon_get_ib_value(p, idx+1+(i*7)+3),
1651                                                                 reloc->lobj.tiling_flags);
1652                                 if (r)
1653                                         return r;
1654                                 ib[idx+1+(i*7)+2] += base_offset;
1655                                 ib[idx+1+(i*7)+3] += mip_offset;
1656                                 break;
1657                         case SQ_TEX_VTX_VALID_BUFFER:
1658                                 /* vtx base */
1659                                 r = r600_cs_packet_next_reloc(p, &reloc);
1660                                 if (r) {
1661                                         DRM_ERROR("bad SET_RESOURCE\n");
1662                                         return -EINVAL;
1663                                 }
1664                                 offset = radeon_get_ib_value(p, idx+1+(i*7)+0);
1665                                 size = radeon_get_ib_value(p, idx+1+(i*7)+1) + 1;
1666                                 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
1667                                         /* force size to size of the buffer */
1668                                         dev_warn(p->dev, "vbo resource seems too big (%d) for the bo (%ld)\n",
1669                                                  size + offset, radeon_bo_size(reloc->robj));
1670                                         ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj);
1671                                 }
1672                                 ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff);
1673                                 ib[idx+1+(i*7)+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1674                                 break;
1675                         case SQ_TEX_VTX_INVALID_TEXTURE:
1676                         case SQ_TEX_VTX_INVALID_BUFFER:
1677                         default:
1678                                 DRM_ERROR("bad SET_RESOURCE\n");
1679                                 return -EINVAL;
1680                         }
1681                 }
1682                 break;
1683         case PACKET3_SET_ALU_CONST:
1684                 if (track->sq_config & DX9_CONSTS) {
1685                         start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;
1686                         end_reg = 4 * pkt->count + start_reg - 4;
1687                         if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||
1688                             (start_reg >= PACKET3_SET_ALU_CONST_END) ||
1689                             (end_reg >= PACKET3_SET_ALU_CONST_END)) {
1690                                 DRM_ERROR("bad SET_ALU_CONST\n");
1691                                 return -EINVAL;
1692                         }
1693                 }
1694                 break;
1695         case PACKET3_SET_BOOL_CONST:
1696                 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET;
1697                 end_reg = 4 * pkt->count + start_reg - 4;
1698                 if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) ||
1699                     (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
1700                     (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
1701                         DRM_ERROR("bad SET_BOOL_CONST\n");
1702                         return -EINVAL;
1703                 }
1704                 break;
1705         case PACKET3_SET_LOOP_CONST:
1706                 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET;
1707                 end_reg = 4 * pkt->count + start_reg - 4;
1708                 if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) ||
1709                     (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
1710                     (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
1711                         DRM_ERROR("bad SET_LOOP_CONST\n");
1712                         return -EINVAL;
1713                 }
1714                 break;
1715         case PACKET3_SET_CTL_CONST:
1716                 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET;
1717                 end_reg = 4 * pkt->count + start_reg - 4;
1718                 if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) ||
1719                     (start_reg >= PACKET3_SET_CTL_CONST_END) ||
1720                     (end_reg >= PACKET3_SET_CTL_CONST_END)) {
1721                         DRM_ERROR("bad SET_CTL_CONST\n");
1722                         return -EINVAL;
1723                 }
1724                 break;
1725         case PACKET3_SET_SAMPLER:
1726                 if (pkt->count % 3) {
1727                         DRM_ERROR("bad SET_SAMPLER\n");
1728                         return -EINVAL;
1729                 }
1730                 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET;
1731                 end_reg = 4 * pkt->count + start_reg - 4;
1732                 if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) ||
1733                     (start_reg >= PACKET3_SET_SAMPLER_END) ||
1734                     (end_reg >= PACKET3_SET_SAMPLER_END)) {
1735                         DRM_ERROR("bad SET_SAMPLER\n");
1736                         return -EINVAL;
1737                 }
1738                 break;
1739         case PACKET3_SURFACE_BASE_UPDATE:
1740                 if (p->family >= CHIP_RV770 || p->family == CHIP_R600) {
1741                         DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
1742                         return -EINVAL;
1743                 }
1744                 if (pkt->count) {
1745                         DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
1746                         return -EINVAL;
1747                 }
1748                 break;
1749         case PACKET3_NOP:
1750                 break;
1751         default:
1752                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1753                 return -EINVAL;
1754         }
1755         return 0;
1756 }
1757
1758 int r600_cs_parse(struct radeon_cs_parser *p)
1759 {
1760         struct radeon_cs_packet pkt;
1761         struct r600_cs_track *track;
1762         int r;
1763
1764         if (p->track == NULL) {
1765                 /* initialize tracker, we are in kms */
1766                 track = kzalloc(sizeof(*track), GFP_KERNEL);
1767                 if (track == NULL)
1768                         return -ENOMEM;
1769                 r600_cs_track_init(track);
1770                 if (p->rdev->family < CHIP_RV770) {
1771                         track->npipes = p->rdev->config.r600.tiling_npipes;
1772                         track->nbanks = p->rdev->config.r600.tiling_nbanks;
1773                         track->group_size = p->rdev->config.r600.tiling_group_size;
1774                 } else if (p->rdev->family <= CHIP_RV740) {
1775                         track->npipes = p->rdev->config.rv770.tiling_npipes;
1776                         track->nbanks = p->rdev->config.rv770.tiling_nbanks;
1777                         track->group_size = p->rdev->config.rv770.tiling_group_size;
1778                 }
1779                 p->track = track;
1780         }
1781         do {
1782                 r = r600_cs_packet_parse(p, &pkt, p->idx);
1783                 if (r) {
1784                         kfree(p->track);
1785                         p->track = NULL;
1786                         return r;
1787                 }
1788                 p->idx += pkt.count + 2;
1789                 switch (pkt.type) {
1790                 case PACKET_TYPE0:
1791                         r = r600_cs_parse_packet0(p, &pkt);
1792                         break;
1793                 case PACKET_TYPE2:
1794                         break;
1795                 case PACKET_TYPE3:
1796                         r = r600_packet3_check(p, &pkt);
1797                         break;
1798                 default:
1799                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1800                         kfree(p->track);
1801                         p->track = NULL;
1802                         return -EINVAL;
1803                 }
1804                 if (r) {
1805                         kfree(p->track);
1806                         p->track = NULL;
1807                         return r;
1808                 }
1809         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1810 #if 0
1811         for (r = 0; r < p->ib->length_dw; r++) {
1812                 printk(KERN_INFO "%05d  0x%08X\n", r, p->ib->ptr[r]);
1813                 mdelay(1);
1814         }
1815 #endif
1816         kfree(p->track);
1817         p->track = NULL;
1818         return 0;
1819 }
1820
1821 static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p)
1822 {
1823         if (p->chunk_relocs_idx == -1) {
1824                 return 0;
1825         }
1826         p->relocs = kzalloc(sizeof(struct radeon_cs_reloc), GFP_KERNEL);
1827         if (p->relocs == NULL) {
1828                 return -ENOMEM;
1829         }
1830         return 0;
1831 }
1832
1833 /**
1834  * cs_parser_fini() - clean parser states
1835  * @parser:     parser structure holding parsing context.
1836  * @error:      error number
1837  *
1838  * If error is set than unvalidate buffer, otherwise just free memory
1839  * used by parsing context.
1840  **/
1841 static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error)
1842 {
1843         unsigned i;
1844
1845         kfree(parser->relocs);
1846         for (i = 0; i < parser->nchunks; i++) {
1847                 kfree(parser->chunks[i].kdata);
1848                 kfree(parser->chunks[i].kpage[0]);
1849                 kfree(parser->chunks[i].kpage[1]);
1850         }
1851         kfree(parser->chunks);
1852         kfree(parser->chunks_array);
1853 }
1854
1855 int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
1856                         unsigned family, u32 *ib, int *l)
1857 {
1858         struct radeon_cs_parser parser;
1859         struct radeon_cs_chunk *ib_chunk;
1860         struct radeon_ib fake_ib;
1861         struct r600_cs_track *track;
1862         int r;
1863
1864         /* initialize tracker */
1865         track = kzalloc(sizeof(*track), GFP_KERNEL);
1866         if (track == NULL)
1867                 return -ENOMEM;
1868         r600_cs_track_init(track);
1869         r600_cs_legacy_get_tiling_conf(dev, &track->npipes, &track->nbanks, &track->group_size);
1870         /* initialize parser */
1871         memset(&parser, 0, sizeof(struct radeon_cs_parser));
1872         parser.filp = filp;
1873         parser.dev = &dev->pdev->dev;
1874         parser.rdev = NULL;
1875         parser.family = family;
1876         parser.ib = &fake_ib;
1877         parser.track = track;
1878         fake_ib.ptr = ib;
1879         r = radeon_cs_parser_init(&parser, data);
1880         if (r) {
1881                 DRM_ERROR("Failed to initialize parser !\n");
1882                 r600_cs_parser_fini(&parser, r);
1883                 return r;
1884         }
1885         r = r600_cs_parser_relocs_legacy(&parser);
1886         if (r) {
1887                 DRM_ERROR("Failed to parse relocation !\n");
1888                 r600_cs_parser_fini(&parser, r);
1889                 return r;
1890         }
1891         /* Copy the packet into the IB, the parser will read from the
1892          * input memory (cached) and write to the IB (which can be
1893          * uncached). */
1894         ib_chunk = &parser.chunks[parser.chunk_ib_idx];
1895         parser.ib->length_dw = ib_chunk->length_dw;
1896         *l = parser.ib->length_dw;
1897         r = r600_cs_parse(&parser);
1898         if (r) {
1899                 DRM_ERROR("Invalid command stream !\n");
1900                 r600_cs_parser_fini(&parser, r);
1901                 return r;
1902         }
1903         r = radeon_cs_finish_pages(&parser);
1904         if (r) {
1905                 DRM_ERROR("Invalid command stream !\n");
1906                 r600_cs_parser_fini(&parser, r);
1907                 return r;
1908         }
1909         r600_cs_parser_fini(&parser, r);
1910         return r;
1911 }
1912
1913 void r600_cs_legacy_init(void)
1914 {
1915         r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_nomm;
1916 }