dd009da0e7a0c1c47b50f290a868a8e50d730072
[linux-3.10.git] / drivers / gpu / drm / radeon / r600_cs.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include "drmP.h"
29 #include "radeon.h"
30 #include "r600d.h"
31 #include "avivod.h"
32
33 static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
34                                         struct radeon_cs_reloc **cs_reloc);
35 static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
36                                         struct radeon_cs_reloc **cs_reloc);
37 typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**);
38 static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm;
39
40 /**
41  * r600_cs_packet_parse() - parse cp packet and point ib index to next packet
42  * @parser:     parser structure holding parsing context.
43  * @pkt:        where to store packet informations
44  *
45  * Assume that chunk_ib_index is properly set. Will return -EINVAL
46  * if packet is bigger than remaining ib size. or if packets is unknown.
47  **/
48 int r600_cs_packet_parse(struct radeon_cs_parser *p,
49                         struct radeon_cs_packet *pkt,
50                         unsigned idx)
51 {
52         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
53         uint32_t header;
54
55         if (idx >= ib_chunk->length_dw) {
56                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
57                           idx, ib_chunk->length_dw);
58                 return -EINVAL;
59         }
60         header = radeon_get_ib_value(p, idx);
61         pkt->idx = idx;
62         pkt->type = CP_PACKET_GET_TYPE(header);
63         pkt->count = CP_PACKET_GET_COUNT(header);
64         pkt->one_reg_wr = 0;
65         switch (pkt->type) {
66         case PACKET_TYPE0:
67                 pkt->reg = CP_PACKET0_GET_REG(header);
68                 break;
69         case PACKET_TYPE3:
70                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
71                 break;
72         case PACKET_TYPE2:
73                 pkt->count = -1;
74                 break;
75         default:
76                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
77                 return -EINVAL;
78         }
79         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
80                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
81                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
82                 return -EINVAL;
83         }
84         return 0;
85 }
86
87 /**
88  * r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3
89  * @parser:             parser structure holding parsing context.
90  * @data:               pointer to relocation data
91  * @offset_start:       starting offset
92  * @offset_mask:        offset mask (to align start offset on)
93  * @reloc:              reloc informations
94  *
95  * Check next packet is relocation packet3, do bo validation and compute
96  * GPU offset using the provided start.
97  **/
98 static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
99                                         struct radeon_cs_reloc **cs_reloc)
100 {
101         struct radeon_cs_chunk *relocs_chunk;
102         struct radeon_cs_packet p3reloc;
103         unsigned idx;
104         int r;
105
106         if (p->chunk_relocs_idx == -1) {
107                 DRM_ERROR("No relocation chunk !\n");
108                 return -EINVAL;
109         }
110         *cs_reloc = NULL;
111         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
112         r = r600_cs_packet_parse(p, &p3reloc, p->idx);
113         if (r) {
114                 return r;
115         }
116         p->idx += p3reloc.count + 2;
117         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
118                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
119                           p3reloc.idx);
120                 return -EINVAL;
121         }
122         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
123         if (idx >= relocs_chunk->length_dw) {
124                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
125                           idx, relocs_chunk->length_dw);
126                 return -EINVAL;
127         }
128         /* FIXME: we assume reloc size is 4 dwords */
129         *cs_reloc = p->relocs_ptr[(idx / 4)];
130         return 0;
131 }
132
133 /**
134  * r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3
135  * @parser:             parser structure holding parsing context.
136  * @data:               pointer to relocation data
137  * @offset_start:       starting offset
138  * @offset_mask:        offset mask (to align start offset on)
139  * @reloc:              reloc informations
140  *
141  * Check next packet is relocation packet3, do bo validation and compute
142  * GPU offset using the provided start.
143  **/
144 static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
145                                         struct radeon_cs_reloc **cs_reloc)
146 {
147         struct radeon_cs_chunk *relocs_chunk;
148         struct radeon_cs_packet p3reloc;
149         unsigned idx;
150         int r;
151
152         if (p->chunk_relocs_idx == -1) {
153                 DRM_ERROR("No relocation chunk !\n");
154                 return -EINVAL;
155         }
156         *cs_reloc = NULL;
157         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
158         r = r600_cs_packet_parse(p, &p3reloc, p->idx);
159         if (r) {
160                 return r;
161         }
162         p->idx += p3reloc.count + 2;
163         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
164                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
165                           p3reloc.idx);
166                 return -EINVAL;
167         }
168         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
169         if (idx >= relocs_chunk->length_dw) {
170                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
171                           idx, relocs_chunk->length_dw);
172                 return -EINVAL;
173         }
174         *cs_reloc = &p->relocs[0];
175         (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32;
176         (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
177         return 0;
178 }
179
180 static int r600_packet0_check(struct radeon_cs_parser *p,
181                                 struct radeon_cs_packet *pkt,
182                                 unsigned idx, unsigned reg)
183 {
184         switch (reg) {
185         case AVIVO_D1MODE_VLINE_START_END:
186         case AVIVO_D2MODE_VLINE_START_END:
187                 break;
188         default:
189                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
190                        reg, idx);
191                 return -EINVAL;
192         }
193         return 0;
194 }
195
196 static int r600_cs_parse_packet0(struct radeon_cs_parser *p,
197                                 struct radeon_cs_packet *pkt)
198 {
199         unsigned reg, i;
200         unsigned idx;
201         int r;
202
203         idx = pkt->idx + 1;
204         reg = pkt->reg;
205         for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
206                 r = r600_packet0_check(p, pkt, idx, reg);
207                 if (r) {
208                         return r;
209                 }
210         }
211         return 0;
212 }
213
214 static int r600_packet3_check(struct radeon_cs_parser *p,
215                                 struct radeon_cs_packet *pkt)
216 {
217         struct radeon_cs_reloc *reloc;
218         volatile u32 *ib;
219         unsigned idx;
220         unsigned i;
221         unsigned start_reg, end_reg, reg;
222         int r;
223         u32 idx_value;
224
225         ib = p->ib->ptr;
226         idx = pkt->idx + 1;
227         idx_value = radeon_get_ib_value(p, idx);
228
229         switch (pkt->opcode) {
230         case PACKET3_START_3D_CMDBUF:
231                 if (p->family >= CHIP_RV770 || pkt->count) {
232                         DRM_ERROR("bad START_3D\n");
233                         return -EINVAL;
234                 }
235                 break;
236         case PACKET3_CONTEXT_CONTROL:
237                 if (pkt->count != 1) {
238                         DRM_ERROR("bad CONTEXT_CONTROL\n");
239                         return -EINVAL;
240                 }
241                 break;
242         case PACKET3_INDEX_TYPE:
243         case PACKET3_NUM_INSTANCES:
244                 if (pkt->count) {
245                         DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n");
246                         return -EINVAL;
247                 }
248                 break;
249         case PACKET3_DRAW_INDEX:
250                 if (pkt->count != 3) {
251                         DRM_ERROR("bad DRAW_INDEX\n");
252                         return -EINVAL;
253                 }
254                 r = r600_cs_packet_next_reloc(p, &reloc);
255                 if (r) {
256                         DRM_ERROR("bad DRAW_INDEX\n");
257                         return -EINVAL;
258                 }
259                 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
260                 ib[idx+1] = upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
261                 break;
262         case PACKET3_DRAW_INDEX_AUTO:
263                 if (pkt->count != 1) {
264                         DRM_ERROR("bad DRAW_INDEX_AUTO\n");
265                         return -EINVAL;
266                 }
267                 break;
268         case PACKET3_DRAW_INDEX_IMMD_BE:
269         case PACKET3_DRAW_INDEX_IMMD:
270                 if (pkt->count < 2) {
271                         DRM_ERROR("bad DRAW_INDEX_IMMD\n");
272                         return -EINVAL;
273                 }
274                 break;
275         case PACKET3_WAIT_REG_MEM:
276                 if (pkt->count != 5) {
277                         DRM_ERROR("bad WAIT_REG_MEM\n");
278                         return -EINVAL;
279                 }
280                 /* bit 4 is reg (0) or mem (1) */
281                 if (idx_value & 0x10) {
282                         r = r600_cs_packet_next_reloc(p, &reloc);
283                         if (r) {
284                                 DRM_ERROR("bad WAIT_REG_MEM\n");
285                                 return -EINVAL;
286                         }
287                         ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
288                         ib[idx+2] = upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
289                 }
290                 break;
291         case PACKET3_SURFACE_SYNC:
292                 if (pkt->count != 3) {
293                         DRM_ERROR("bad SURFACE_SYNC\n");
294                         return -EINVAL;
295                 }
296                 /* 0xffffffff/0x0 is flush all cache flag */
297                 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
298                     radeon_get_ib_value(p, idx + 2) != 0) {
299                         r = r600_cs_packet_next_reloc(p, &reloc);
300                         if (r) {
301                                 DRM_ERROR("bad SURFACE_SYNC\n");
302                                 return -EINVAL;
303                         }
304                         ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
305                 }
306                 break;
307         case PACKET3_EVENT_WRITE:
308                 if (pkt->count != 2 && pkt->count != 0) {
309                         DRM_ERROR("bad EVENT_WRITE\n");
310                         return -EINVAL;
311                 }
312                 if (pkt->count) {
313                         r = r600_cs_packet_next_reloc(p, &reloc);
314                         if (r) {
315                                 DRM_ERROR("bad EVENT_WRITE\n");
316                                 return -EINVAL;
317                         }
318                         ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
319                         ib[idx+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
320                 }
321                 break;
322         case PACKET3_EVENT_WRITE_EOP:
323                 if (pkt->count != 4) {
324                         DRM_ERROR("bad EVENT_WRITE_EOP\n");
325                         return -EINVAL;
326                 }
327                 r = r600_cs_packet_next_reloc(p, &reloc);
328                 if (r) {
329                         DRM_ERROR("bad EVENT_WRITE\n");
330                         return -EINVAL;
331                 }
332                 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
333                 ib[idx+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
334                 break;
335         case PACKET3_SET_CONFIG_REG:
336                 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
337                 end_reg = 4 * pkt->count + start_reg - 4;
338                 if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) ||
339                     (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
340                     (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
341                         DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
342                         return -EINVAL;
343                 }
344                 for (i = 0; i < pkt->count; i++) {
345                         reg = start_reg + (4 * i);
346                         switch (reg) {
347                         case CP_COHER_BASE:
348                                 /* use PACKET3_SURFACE_SYNC */
349                                 return -EINVAL;
350                         default:
351                                 break;
352                         }
353                 }
354                 break;
355         case PACKET3_SET_CONTEXT_REG:
356                 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET;
357                 end_reg = 4 * pkt->count + start_reg - 4;
358                 if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) ||
359                     (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
360                     (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
361                         DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
362                         return -EINVAL;
363                 }
364                 for (i = 0; i < pkt->count; i++) {
365                         reg = start_reg + (4 * i);
366                         switch (reg) {
367                         case DB_DEPTH_BASE:
368                         case CB_COLOR0_BASE:
369                         case CB_COLOR1_BASE:
370                         case CB_COLOR2_BASE:
371                         case CB_COLOR3_BASE:
372                         case CB_COLOR4_BASE:
373                         case CB_COLOR5_BASE:
374                         case CB_COLOR6_BASE:
375                         case CB_COLOR7_BASE:
376                         case SQ_PGM_START_FS:
377                         case SQ_PGM_START_ES:
378                         case SQ_PGM_START_VS:
379                         case SQ_PGM_START_GS:
380                         case SQ_PGM_START_PS:
381                                 r = r600_cs_packet_next_reloc(p, &reloc);
382                                 if (r) {
383                                         DRM_ERROR("bad SET_CONTEXT_REG "
384                                                         "0x%04X\n", reg);
385                                         return -EINVAL;
386                                 }
387                                 ib[idx+1+i] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
388                                 break;
389                         case VGT_DMA_BASE:
390                         case VGT_DMA_BASE_HI:
391                                 /* These should be handled by DRAW_INDEX packet 3 */
392                         case VGT_STRMOUT_BASE_OFFSET_0:
393                         case VGT_STRMOUT_BASE_OFFSET_1:
394                         case VGT_STRMOUT_BASE_OFFSET_2:
395                         case VGT_STRMOUT_BASE_OFFSET_3:
396                         case VGT_STRMOUT_BASE_OFFSET_HI_0:
397                         case VGT_STRMOUT_BASE_OFFSET_HI_1:
398                         case VGT_STRMOUT_BASE_OFFSET_HI_2:
399                         case VGT_STRMOUT_BASE_OFFSET_HI_3:
400                         case VGT_STRMOUT_BUFFER_BASE_0:
401                         case VGT_STRMOUT_BUFFER_BASE_1:
402                         case VGT_STRMOUT_BUFFER_BASE_2:
403                         case VGT_STRMOUT_BUFFER_BASE_3:
404                         case VGT_STRMOUT_BUFFER_OFFSET_0:
405                         case VGT_STRMOUT_BUFFER_OFFSET_1:
406                         case VGT_STRMOUT_BUFFER_OFFSET_2:
407                         case VGT_STRMOUT_BUFFER_OFFSET_3:
408                                 /* These should be handled by STRMOUT_BUFFER packet 3 */
409                                 DRM_ERROR("bad context reg: 0x%08x\n", reg);
410                                 return -EINVAL;
411                         default:
412                                 break;
413                         }
414                 }
415                 break;
416         case PACKET3_SET_RESOURCE:
417                 if (pkt->count % 7) {
418                         DRM_ERROR("bad SET_RESOURCE\n");
419                         return -EINVAL;
420                 }
421                 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET;
422                 end_reg = 4 * pkt->count + start_reg - 4;
423                 if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) ||
424                     (start_reg >= PACKET3_SET_RESOURCE_END) ||
425                     (end_reg >= PACKET3_SET_RESOURCE_END)) {
426                         DRM_ERROR("bad SET_RESOURCE\n");
427                         return -EINVAL;
428                 }
429                 for (i = 0; i < (pkt->count / 7); i++) {
430                         switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) {
431                         case SQ_TEX_VTX_VALID_TEXTURE:
432                                 /* tex base */
433                                 r = r600_cs_packet_next_reloc(p, &reloc);
434                                 if (r) {
435                                         DRM_ERROR("bad SET_RESOURCE\n");
436                                         return -EINVAL;
437                                 }
438                                 ib[idx+1+(i*7)+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
439                                 /* tex mip base */
440                                 r = r600_cs_packet_next_reloc(p, &reloc);
441                                 if (r) {
442                                         DRM_ERROR("bad SET_RESOURCE\n");
443                                         return -EINVAL;
444                                 }
445                                 ib[idx+1+(i*7)+3] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
446                                 break;
447                         case SQ_TEX_VTX_VALID_BUFFER:
448                                 /* vtx base */
449                                 r = r600_cs_packet_next_reloc(p, &reloc);
450                                 if (r) {
451                                         DRM_ERROR("bad SET_RESOURCE\n");
452                                         return -EINVAL;
453                                 }
454                                 ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff);
455                                 ib[idx+1+(i*7)+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
456                                 break;
457                         case SQ_TEX_VTX_INVALID_TEXTURE:
458                         case SQ_TEX_VTX_INVALID_BUFFER:
459                         default:
460                                 DRM_ERROR("bad SET_RESOURCE\n");
461                                 return -EINVAL;
462                         }
463                 }
464                 break;
465         case PACKET3_SET_ALU_CONST:
466                 start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;
467                 end_reg = 4 * pkt->count + start_reg - 4;
468                 if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||
469                     (start_reg >= PACKET3_SET_ALU_CONST_END) ||
470                     (end_reg >= PACKET3_SET_ALU_CONST_END)) {
471                         DRM_ERROR("bad SET_ALU_CONST\n");
472                         return -EINVAL;
473                 }
474                 break;
475         case PACKET3_SET_BOOL_CONST:
476                 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET;
477                 end_reg = 4 * pkt->count + start_reg - 4;
478                 if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) ||
479                     (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
480                     (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
481                         DRM_ERROR("bad SET_BOOL_CONST\n");
482                         return -EINVAL;
483                 }
484                 break;
485         case PACKET3_SET_LOOP_CONST:
486                 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET;
487                 end_reg = 4 * pkt->count + start_reg - 4;
488                 if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) ||
489                     (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
490                     (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
491                         DRM_ERROR("bad SET_LOOP_CONST\n");
492                         return -EINVAL;
493                 }
494                 break;
495         case PACKET3_SET_CTL_CONST:
496                 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET;
497                 end_reg = 4 * pkt->count + start_reg - 4;
498                 if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) ||
499                     (start_reg >= PACKET3_SET_CTL_CONST_END) ||
500                     (end_reg >= PACKET3_SET_CTL_CONST_END)) {
501                         DRM_ERROR("bad SET_CTL_CONST\n");
502                         return -EINVAL;
503                 }
504                 break;
505         case PACKET3_SET_SAMPLER:
506                 if (pkt->count % 3) {
507                         DRM_ERROR("bad SET_SAMPLER\n");
508                         return -EINVAL;
509                 }
510                 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET;
511                 end_reg = 4 * pkt->count + start_reg - 4;
512                 if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) ||
513                     (start_reg >= PACKET3_SET_SAMPLER_END) ||
514                     (end_reg >= PACKET3_SET_SAMPLER_END)) {
515                         DRM_ERROR("bad SET_SAMPLER\n");
516                         return -EINVAL;
517                 }
518                 break;
519         case PACKET3_SURFACE_BASE_UPDATE:
520                 if (p->family >= CHIP_RV770 || p->family == CHIP_R600) {
521                         DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
522                         return -EINVAL;
523                 }
524                 if (pkt->count) {
525                         DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
526                         return -EINVAL;
527                 }
528                 break;
529         case PACKET3_NOP:
530                 break;
531         default:
532                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
533                 return -EINVAL;
534         }
535         return 0;
536 }
537
538 int r600_cs_parse(struct radeon_cs_parser *p)
539 {
540         struct radeon_cs_packet pkt;
541         int r;
542
543         do {
544                 r = r600_cs_packet_parse(p, &pkt, p->idx);
545                 if (r) {
546                         return r;
547                 }
548                 p->idx += pkt.count + 2;
549                 switch (pkt.type) {
550                 case PACKET_TYPE0:
551                         r = r600_cs_parse_packet0(p, &pkt);
552                         break;
553                 case PACKET_TYPE2:
554                         break;
555                 case PACKET_TYPE3:
556                         r = r600_packet3_check(p, &pkt);
557                         break;
558                 default:
559                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
560                         return -EINVAL;
561                 }
562                 if (r) {
563                         return r;
564                 }
565         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
566 #if 0
567         for (r = 0; r < p->ib->length_dw; r++) {
568                 printk(KERN_INFO "%05d  0x%08X\n", r, p->ib->ptr[r]);
569                 mdelay(1);
570         }
571 #endif
572         return 0;
573 }
574
575 static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p)
576 {
577         if (p->chunk_relocs_idx == -1) {
578                 return 0;
579         }
580         p->relocs = kcalloc(1, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
581         if (p->relocs == NULL) {
582                 return -ENOMEM;
583         }
584         return 0;
585 }
586
587 /**
588  * cs_parser_fini() - clean parser states
589  * @parser:     parser structure holding parsing context.
590  * @error:      error number
591  *
592  * If error is set than unvalidate buffer, otherwise just free memory
593  * used by parsing context.
594  **/
595 static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error)
596 {
597         unsigned i;
598
599         kfree(parser->relocs);
600         for (i = 0; i < parser->nchunks; i++) {
601                 kfree(parser->chunks[i].kdata);
602         }
603         kfree(parser->chunks);
604         kfree(parser->chunks_array);
605 }
606
607 int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
608                         unsigned family, u32 *ib, int *l)
609 {
610         struct radeon_cs_parser parser;
611         struct radeon_cs_chunk *ib_chunk;
612         struct radeon_ib        fake_ib;
613         int r;
614
615         /* initialize parser */
616         memset(&parser, 0, sizeof(struct radeon_cs_parser));
617         parser.filp = filp;
618         parser.rdev = NULL;
619         parser.family = family;
620         parser.ib = &fake_ib;
621         fake_ib.ptr = ib;
622         r = radeon_cs_parser_init(&parser, data);
623         if (r) {
624                 DRM_ERROR("Failed to initialize parser !\n");
625                 r600_cs_parser_fini(&parser, r);
626                 return r;
627         }
628         r = r600_cs_parser_relocs_legacy(&parser);
629         if (r) {
630                 DRM_ERROR("Failed to parse relocation !\n");
631                 r600_cs_parser_fini(&parser, r);
632                 return r;
633         }
634         /* Copy the packet into the IB, the parser will read from the
635          * input memory (cached) and write to the IB (which can be
636          * uncached). */
637         ib_chunk = &parser.chunks[parser.chunk_ib_idx];
638         parser.ib->length_dw = ib_chunk->length_dw;
639         *l = parser.ib->length_dw;
640         r = r600_cs_parse(&parser);
641         if (r) {
642                 DRM_ERROR("Invalid command stream !\n");
643                 r600_cs_parser_fini(&parser, r);
644                 return r;
645         }
646         r = radeon_cs_finish_pages(&parser);
647         if (r) {
648                 DRM_ERROR("Invalid command stream !\n");
649                 r600_cs_parser_fini(&parser, r);
650                 return r;
651         }
652         r600_cs_parser_fini(&parser, r);
653         return r;
654 }
655
656 void r600_cs_legacy_init(void)
657 {
658         r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_nomm;
659 }