Merge branch 'drm-core-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied...
[linux-3.10.git] / drivers / gpu / drm / radeon / evergreend.h
1 /*
2  * Copyright 2010 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Alex Deucher
23  */
24 #ifndef EVERGREEND_H
25 #define EVERGREEND_H
26
27 #define EVERGREEN_MAX_SH_GPRS           256
28 #define EVERGREEN_MAX_TEMP_GPRS         16
29 #define EVERGREEN_MAX_SH_THREADS        256
30 #define EVERGREEN_MAX_SH_STACK_ENTRIES  4096
31 #define EVERGREEN_MAX_FRC_EOV_CNT       16384
32 #define EVERGREEN_MAX_BACKENDS          8
33 #define EVERGREEN_MAX_BACKENDS_MASK     0xFF
34 #define EVERGREEN_MAX_SIMDS             16
35 #define EVERGREEN_MAX_SIMDS_MASK        0xFFFF
36 #define EVERGREEN_MAX_PIPES             8
37 #define EVERGREEN_MAX_PIPES_MASK        0xFF
38 #define EVERGREEN_MAX_LDS_NUM           0xFFFF
39
40 /* Registers */
41
42 #define RCU_IND_INDEX                                   0x100
43 #define RCU_IND_DATA                                    0x104
44
45 #define GRBM_GFX_INDEX                                  0x802C
46 #define         INSTANCE_INDEX(x)                       ((x) << 0)
47 #define         SE_INDEX(x)                             ((x) << 16)
48 #define         INSTANCE_BROADCAST_WRITES               (1 << 30)
49 #define         SE_BROADCAST_WRITES                     (1 << 31)
50 #define RLC_GFX_INDEX                                   0x3fC4
51 #define CC_GC_SHADER_PIPE_CONFIG                        0x8950
52 #define         WRITE_DIS                               (1 << 0)
53 #define CC_RB_BACKEND_DISABLE                           0x98F4
54 #define         BACKEND_DISABLE(x)                      ((x) << 16)
55 #define GB_ADDR_CONFIG                                  0x98F8
56 #define         NUM_PIPES(x)                            ((x) << 0)
57 #define         PIPE_INTERLEAVE_SIZE(x)                 ((x) << 4)
58 #define         BANK_INTERLEAVE_SIZE(x)                 ((x) << 8)
59 #define         NUM_SHADER_ENGINES(x)                   ((x) << 12)
60 #define         SHADER_ENGINE_TILE_SIZE(x)              ((x) << 16)
61 #define         NUM_GPUS(x)                             ((x) << 20)
62 #define         MULTI_GPU_TILE_SIZE(x)                  ((x) << 24)
63 #define         ROW_SIZE(x)                             ((x) << 28)
64 #define GB_BACKEND_MAP                                  0x98FC
65 #define DMIF_ADDR_CONFIG                                0xBD4
66 #define HDP_ADDR_CONFIG                                 0x2F48
67 #define HDP_MISC_CNTL                                   0x2F4C
68 #define         HDP_FLUSH_INVALIDATE_CACHE              (1 << 0)
69
70 #define CC_SYS_RB_BACKEND_DISABLE                       0x3F88
71 #define GC_USER_RB_BACKEND_DISABLE                      0x9B7C
72
73 #define CGTS_SYS_TCC_DISABLE                            0x3F90
74 #define CGTS_TCC_DISABLE                                0x9148
75 #define CGTS_USER_SYS_TCC_DISABLE                       0x3F94
76 #define CGTS_USER_TCC_DISABLE                           0x914C
77
78 #define CONFIG_MEMSIZE                                  0x5428
79
80 #define CP_ME_CNTL                                      0x86D8
81 #define         CP_ME_HALT                                      (1 << 28)
82 #define         CP_PFP_HALT                                     (1 << 26)
83 #define CP_ME_RAM_DATA                                  0xC160
84 #define CP_ME_RAM_RADDR                                 0xC158
85 #define CP_ME_RAM_WADDR                                 0xC15C
86 #define CP_MEQ_THRESHOLDS                               0x8764
87 #define         STQ_SPLIT(x)                                    ((x) << 0)
88 #define CP_PERFMON_CNTL                                 0x87FC
89 #define CP_PFP_UCODE_ADDR                               0xC150
90 #define CP_PFP_UCODE_DATA                               0xC154
91 #define CP_QUEUE_THRESHOLDS                             0x8760
92 #define         ROQ_IB1_START(x)                                ((x) << 0)
93 #define         ROQ_IB2_START(x)                                ((x) << 8)
94 #define CP_RB_BASE                                      0xC100
95 #define CP_RB_CNTL                                      0xC104
96 #define         RB_BUFSZ(x)                                     ((x) << 0)
97 #define         RB_BLKSZ(x)                                     ((x) << 8)
98 #define         RB_NO_UPDATE                                    (1 << 27)
99 #define         RB_RPTR_WR_ENA                                  (1 << 31)
100 #define         BUF_SWAP_32BIT                                  (2 << 16)
101 #define CP_RB_RPTR                                      0x8700
102 #define CP_RB_RPTR_ADDR                                 0xC10C
103 #define         RB_RPTR_SWAP(x)                                 ((x) << 0)
104 #define CP_RB_RPTR_ADDR_HI                              0xC110
105 #define CP_RB_RPTR_WR                                   0xC108
106 #define CP_RB_WPTR                                      0xC114
107 #define CP_RB_WPTR_ADDR                                 0xC118
108 #define CP_RB_WPTR_ADDR_HI                              0xC11C
109 #define CP_RB_WPTR_DELAY                                0x8704
110 #define CP_SEM_WAIT_TIMER                               0x85BC
111 #define CP_DEBUG                                        0xC1FC
112
113
114 #define GC_USER_SHADER_PIPE_CONFIG                      0x8954
115 #define         INACTIVE_QD_PIPES(x)                            ((x) << 8)
116 #define         INACTIVE_QD_PIPES_MASK                          0x0000FF00
117 #define         INACTIVE_SIMDS(x)                               ((x) << 16)
118 #define         INACTIVE_SIMDS_MASK                             0x00FF0000
119
120 #define GRBM_CNTL                                       0x8000
121 #define         GRBM_READ_TIMEOUT(x)                            ((x) << 0)
122 #define GRBM_SOFT_RESET                                 0x8020
123 #define         SOFT_RESET_CP                                   (1 << 0)
124 #define         SOFT_RESET_CB                                   (1 << 1)
125 #define         SOFT_RESET_DB                                   (1 << 3)
126 #define         SOFT_RESET_PA                                   (1 << 5)
127 #define         SOFT_RESET_SC                                   (1 << 6)
128 #define         SOFT_RESET_SPI                                  (1 << 8)
129 #define         SOFT_RESET_SH                                   (1 << 9)
130 #define         SOFT_RESET_SX                                   (1 << 10)
131 #define         SOFT_RESET_TC                                   (1 << 11)
132 #define         SOFT_RESET_TA                                   (1 << 12)
133 #define         SOFT_RESET_VC                                   (1 << 13)
134 #define         SOFT_RESET_VGT                                  (1 << 14)
135
136 #define GRBM_STATUS                                     0x8010
137 #define         CMDFIFO_AVAIL_MASK                              0x0000000F
138 #define         SRBM_RQ_PENDING                                 (1 << 5)
139 #define         CF_RQ_PENDING                                   (1 << 7)
140 #define         PF_RQ_PENDING                                   (1 << 8)
141 #define         GRBM_EE_BUSY                                    (1 << 10)
142 #define         SX_CLEAN                                        (1 << 11)
143 #define         DB_CLEAN                                        (1 << 12)
144 #define         CB_CLEAN                                        (1 << 13)
145 #define         TA_BUSY                                         (1 << 14)
146 #define         VGT_BUSY_NO_DMA                                 (1 << 16)
147 #define         VGT_BUSY                                        (1 << 17)
148 #define         SX_BUSY                                         (1 << 20)
149 #define         SH_BUSY                                         (1 << 21)
150 #define         SPI_BUSY                                        (1 << 22)
151 #define         SC_BUSY                                         (1 << 24)
152 #define         PA_BUSY                                         (1 << 25)
153 #define         DB_BUSY                                         (1 << 26)
154 #define         CP_COHERENCY_BUSY                               (1 << 28)
155 #define         CP_BUSY                                         (1 << 29)
156 #define         CB_BUSY                                         (1 << 30)
157 #define         GUI_ACTIVE                                      (1 << 31)
158 #define GRBM_STATUS_SE0                                 0x8014
159 #define GRBM_STATUS_SE1                                 0x8018
160 #define         SE_SX_CLEAN                                     (1 << 0)
161 #define         SE_DB_CLEAN                                     (1 << 1)
162 #define         SE_CB_CLEAN                                     (1 << 2)
163 #define         SE_TA_BUSY                                      (1 << 25)
164 #define         SE_SX_BUSY                                      (1 << 26)
165 #define         SE_SPI_BUSY                                     (1 << 27)
166 #define         SE_SH_BUSY                                      (1 << 28)
167 #define         SE_SC_BUSY                                      (1 << 29)
168 #define         SE_DB_BUSY                                      (1 << 30)
169 #define         SE_CB_BUSY                                      (1 << 31)
170 /* evergreen */
171 #define CG_MULT_THERMAL_STATUS                          0x740
172 #define         ASIC_T(x)                               ((x) << 16)
173 #define         ASIC_T_MASK                             0x7FF0000
174 #define         ASIC_T_SHIFT                            16
175 /* APU */
176 #define CG_THERMAL_STATUS                               0x678
177
178 #define HDP_HOST_PATH_CNTL                              0x2C00
179 #define HDP_NONSURFACE_BASE                             0x2C04
180 #define HDP_NONSURFACE_INFO                             0x2C08
181 #define HDP_NONSURFACE_SIZE                             0x2C0C
182 #define HDP_MEM_COHERENCY_FLUSH_CNTL                    0x5480
183 #define HDP_REG_COHERENCY_FLUSH_CNTL                    0x54A0
184 #define HDP_TILING_CONFIG                               0x2F3C
185
186 #define MC_SHARED_CHMAP                                         0x2004
187 #define         NOOFCHAN_SHIFT                                  12
188 #define         NOOFCHAN_MASK                                   0x00003000
189 #define MC_SHARED_CHREMAP                                       0x2008
190
191 #define MC_ARB_RAMCFG                                   0x2760
192 #define         NOOFBANK_SHIFT                                  0
193 #define         NOOFBANK_MASK                                   0x00000003
194 #define         NOOFRANK_SHIFT                                  2
195 #define         NOOFRANK_MASK                                   0x00000004
196 #define         NOOFROWS_SHIFT                                  3
197 #define         NOOFROWS_MASK                                   0x00000038
198 #define         NOOFCOLS_SHIFT                                  6
199 #define         NOOFCOLS_MASK                                   0x000000C0
200 #define         CHANSIZE_SHIFT                                  8
201 #define         CHANSIZE_MASK                                   0x00000100
202 #define         BURSTLENGTH_SHIFT                               9
203 #define         BURSTLENGTH_MASK                                0x00000200
204 #define         CHANSIZE_OVERRIDE                               (1 << 11)
205 #define FUS_MC_ARB_RAMCFG                               0x2768
206 #define MC_VM_AGP_TOP                                   0x2028
207 #define MC_VM_AGP_BOT                                   0x202C
208 #define MC_VM_AGP_BASE                                  0x2030
209 #define MC_VM_FB_LOCATION                               0x2024
210 #define MC_FUS_VM_FB_OFFSET                             0x2898
211 #define MC_VM_MB_L1_TLB0_CNTL                           0x2234
212 #define MC_VM_MB_L1_TLB1_CNTL                           0x2238
213 #define MC_VM_MB_L1_TLB2_CNTL                           0x223C
214 #define MC_VM_MB_L1_TLB3_CNTL                           0x2240
215 #define         ENABLE_L1_TLB                                   (1 << 0)
216 #define         ENABLE_L1_FRAGMENT_PROCESSING                   (1 << 1)
217 #define         SYSTEM_ACCESS_MODE_PA_ONLY                      (0 << 3)
218 #define         SYSTEM_ACCESS_MODE_USE_SYS_MAP                  (1 << 3)
219 #define         SYSTEM_ACCESS_MODE_IN_SYS                       (2 << 3)
220 #define         SYSTEM_ACCESS_MODE_NOT_IN_SYS                   (3 << 3)
221 #define         SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU       (0 << 5)
222 #define         EFFECTIVE_L1_TLB_SIZE(x)                        ((x)<<15)
223 #define         EFFECTIVE_L1_QUEUE_SIZE(x)                      ((x)<<18)
224 #define MC_VM_MD_L1_TLB0_CNTL                           0x2654
225 #define MC_VM_MD_L1_TLB1_CNTL                           0x2658
226 #define MC_VM_MD_L1_TLB2_CNTL                           0x265C
227
228 #define FUS_MC_VM_MD_L1_TLB0_CNTL                       0x265C
229 #define FUS_MC_VM_MD_L1_TLB1_CNTL                       0x2660
230 #define FUS_MC_VM_MD_L1_TLB2_CNTL                       0x2664
231
232 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR              0x203C
233 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR                 0x2038
234 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR                  0x2034
235
236 #define PA_CL_ENHANCE                                   0x8A14
237 #define         CLIP_VTX_REORDER_ENA                            (1 << 0)
238 #define         NUM_CLIP_SEQ(x)                                 ((x) << 1)
239 #define PA_SC_AA_CONFIG                                 0x28C04
240 #define         MSAA_NUM_SAMPLES_SHIFT                  0
241 #define         MSAA_NUM_SAMPLES_MASK                   0x3
242 #define PA_SC_CLIPRECT_RULE                             0x2820C
243 #define PA_SC_EDGERULE                                  0x28230
244 #define PA_SC_FIFO_SIZE                                 0x8BCC
245 #define         SC_PRIM_FIFO_SIZE(x)                            ((x) << 0)
246 #define         SC_HIZ_TILE_FIFO_SIZE(x)                        ((x) << 12)
247 #define         SC_EARLYZ_TILE_FIFO_SIZE(x)                     ((x) << 20)
248 #define PA_SC_FORCE_EOV_MAX_CNTS                        0x8B24
249 #define         FORCE_EOV_MAX_CLK_CNT(x)                        ((x) << 0)
250 #define         FORCE_EOV_MAX_REZ_CNT(x)                        ((x) << 16)
251 #define PA_SC_LINE_STIPPLE                              0x28A0C
252 #define PA_SU_LINE_STIPPLE_VALUE                        0x8A60
253 #define PA_SC_LINE_STIPPLE_STATE                        0x8B10
254
255 #define SCRATCH_REG0                                    0x8500
256 #define SCRATCH_REG1                                    0x8504
257 #define SCRATCH_REG2                                    0x8508
258 #define SCRATCH_REG3                                    0x850C
259 #define SCRATCH_REG4                                    0x8510
260 #define SCRATCH_REG5                                    0x8514
261 #define SCRATCH_REG6                                    0x8518
262 #define SCRATCH_REG7                                    0x851C
263 #define SCRATCH_UMSK                                    0x8540
264 #define SCRATCH_ADDR                                    0x8544
265
266 #define SMX_DC_CTL0                                     0xA020
267 #define         USE_HASH_FUNCTION                               (1 << 0)
268 #define         NUMBER_OF_SETS(x)                               ((x) << 1)
269 #define         FLUSH_ALL_ON_EVENT                              (1 << 10)
270 #define         STALL_ON_EVENT                                  (1 << 11)
271 #define SMX_EVENT_CTL                                   0xA02C
272 #define         ES_FLUSH_CTL(x)                                 ((x) << 0)
273 #define         GS_FLUSH_CTL(x)                                 ((x) << 3)
274 #define         ACK_FLUSH_CTL(x)                                ((x) << 6)
275 #define         SYNC_FLUSH_CTL                                  (1 << 8)
276
277 #define SPI_CONFIG_CNTL                                 0x9100
278 #define         GPR_WRITE_PRIORITY(x)                           ((x) << 0)
279 #define SPI_CONFIG_CNTL_1                               0x913C
280 #define         VTX_DONE_DELAY(x)                               ((x) << 0)
281 #define         INTERP_ONE_PRIM_PER_ROW                         (1 << 4)
282 #define SPI_INPUT_Z                                     0x286D8
283 #define SPI_PS_IN_CONTROL_0                             0x286CC
284 #define         NUM_INTERP(x)                                   ((x)<<0)
285 #define         POSITION_ENA                                    (1<<8)
286 #define         POSITION_CENTROID                               (1<<9)
287 #define         POSITION_ADDR(x)                                ((x)<<10)
288 #define         PARAM_GEN(x)                                    ((x)<<15)
289 #define         PARAM_GEN_ADDR(x)                               ((x)<<19)
290 #define         BARYC_SAMPLE_CNTL(x)                            ((x)<<26)
291 #define         PERSP_GRADIENT_ENA                              (1<<28)
292 #define         LINEAR_GRADIENT_ENA                             (1<<29)
293 #define         POSITION_SAMPLE                                 (1<<30)
294 #define         BARYC_AT_SAMPLE_ENA                             (1<<31)
295
296 #define SQ_CONFIG                                       0x8C00
297 #define         VC_ENABLE                                       (1 << 0)
298 #define         EXPORT_SRC_C                                    (1 << 1)
299 #define         CS_PRIO(x)                                      ((x) << 18)
300 #define         LS_PRIO(x)                                      ((x) << 20)
301 #define         HS_PRIO(x)                                      ((x) << 22)
302 #define         PS_PRIO(x)                                      ((x) << 24)
303 #define         VS_PRIO(x)                                      ((x) << 26)
304 #define         GS_PRIO(x)                                      ((x) << 28)
305 #define         ES_PRIO(x)                                      ((x) << 30)
306 #define SQ_GPR_RESOURCE_MGMT_1                          0x8C04
307 #define         NUM_PS_GPRS(x)                                  ((x) << 0)
308 #define         NUM_VS_GPRS(x)                                  ((x) << 16)
309 #define         NUM_CLAUSE_TEMP_GPRS(x)                         ((x) << 28)
310 #define SQ_GPR_RESOURCE_MGMT_2                          0x8C08
311 #define         NUM_GS_GPRS(x)                                  ((x) << 0)
312 #define         NUM_ES_GPRS(x)                                  ((x) << 16)
313 #define SQ_GPR_RESOURCE_MGMT_3                          0x8C0C
314 #define         NUM_HS_GPRS(x)                                  ((x) << 0)
315 #define         NUM_LS_GPRS(x)                                  ((x) << 16)
316 #define SQ_THREAD_RESOURCE_MGMT                         0x8C18
317 #define         NUM_PS_THREADS(x)                               ((x) << 0)
318 #define         NUM_VS_THREADS(x)                               ((x) << 8)
319 #define         NUM_GS_THREADS(x)                               ((x) << 16)
320 #define         NUM_ES_THREADS(x)                               ((x) << 24)
321 #define SQ_THREAD_RESOURCE_MGMT_2                       0x8C1C
322 #define         NUM_HS_THREADS(x)                               ((x) << 0)
323 #define         NUM_LS_THREADS(x)                               ((x) << 8)
324 #define SQ_STACK_RESOURCE_MGMT_1                        0x8C20
325 #define         NUM_PS_STACK_ENTRIES(x)                         ((x) << 0)
326 #define         NUM_VS_STACK_ENTRIES(x)                         ((x) << 16)
327 #define SQ_STACK_RESOURCE_MGMT_2                        0x8C24
328 #define         NUM_GS_STACK_ENTRIES(x)                         ((x) << 0)
329 #define         NUM_ES_STACK_ENTRIES(x)                         ((x) << 16)
330 #define SQ_STACK_RESOURCE_MGMT_3                        0x8C28
331 #define         NUM_HS_STACK_ENTRIES(x)                         ((x) << 0)
332 #define         NUM_LS_STACK_ENTRIES(x)                         ((x) << 16)
333 #define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ                    0x8D8C
334 #define SQ_LDS_RESOURCE_MGMT                            0x8E2C
335
336 #define SQ_MS_FIFO_SIZES                                0x8CF0
337 #define         CACHE_FIFO_SIZE(x)                              ((x) << 0)
338 #define         FETCH_FIFO_HIWATER(x)                           ((x) << 8)
339 #define         DONE_FIFO_HIWATER(x)                            ((x) << 16)
340 #define         ALU_UPDATE_FIFO_HIWATER(x)                      ((x) << 24)
341
342 #define SX_DEBUG_1                                      0x9058
343 #define         ENABLE_NEW_SMX_ADDRESS                          (1 << 16)
344 #define SX_EXPORT_BUFFER_SIZES                          0x900C
345 #define         COLOR_BUFFER_SIZE(x)                            ((x) << 0)
346 #define         POSITION_BUFFER_SIZE(x)                         ((x) << 8)
347 #define         SMX_BUFFER_SIZE(x)                              ((x) << 16)
348 #define SX_MISC                                         0x28350
349
350 #define CB_PERF_CTR0_SEL_0                              0x9A20
351 #define CB_PERF_CTR0_SEL_1                              0x9A24
352 #define CB_PERF_CTR1_SEL_0                              0x9A28
353 #define CB_PERF_CTR1_SEL_1                              0x9A2C
354 #define CB_PERF_CTR2_SEL_0                              0x9A30
355 #define CB_PERF_CTR2_SEL_1                              0x9A34
356 #define CB_PERF_CTR3_SEL_0                              0x9A38
357 #define CB_PERF_CTR3_SEL_1                              0x9A3C
358
359 #define TA_CNTL_AUX                                     0x9508
360 #define         DISABLE_CUBE_WRAP                               (1 << 0)
361 #define         DISABLE_CUBE_ANISO                              (1 << 1)
362 #define         SYNC_GRADIENT                                   (1 << 24)
363 #define         SYNC_WALKER                                     (1 << 25)
364 #define         SYNC_ALIGNER                                    (1 << 26)
365
366 #define TCP_CHAN_STEER_LO                               0x960c
367 #define TCP_CHAN_STEER_HI                               0x9610
368
369 #define VGT_CACHE_INVALIDATION                          0x88C4
370 #define         CACHE_INVALIDATION(x)                           ((x) << 0)
371 #define                 VC_ONLY                                         0
372 #define                 TC_ONLY                                         1
373 #define                 VC_AND_TC                                       2
374 #define         AUTO_INVLD_EN(x)                                ((x) << 6)
375 #define                 NO_AUTO                                         0
376 #define                 ES_AUTO                                         1
377 #define                 GS_AUTO                                         2
378 #define                 ES_AND_GS_AUTO                                  3
379 #define VGT_GS_VERTEX_REUSE                             0x88D4
380 #define VGT_NUM_INSTANCES                               0x8974
381 #define VGT_OUT_DEALLOC_CNTL                            0x28C5C
382 #define         DEALLOC_DIST_MASK                               0x0000007F
383 #define VGT_VERTEX_REUSE_BLOCK_CNTL                     0x28C58
384 #define         VTX_REUSE_DEPTH_MASK                            0x000000FF
385
386 #define VM_CONTEXT0_CNTL                                0x1410
387 #define         ENABLE_CONTEXT                                  (1 << 0)
388 #define         PAGE_TABLE_DEPTH(x)                             (((x) & 3) << 1)
389 #define         RANGE_PROTECTION_FAULT_ENABLE_DEFAULT           (1 << 4)
390 #define VM_CONTEXT1_CNTL                                0x1414
391 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR                0x153C
392 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR                 0x157C
393 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR               0x155C
394 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR       0x1518
395 #define VM_CONTEXT0_REQUEST_RESPONSE                    0x1470
396 #define         REQUEST_TYPE(x)                                 (((x) & 0xf) << 0)
397 #define         RESPONSE_TYPE_MASK                              0x000000F0
398 #define         RESPONSE_TYPE_SHIFT                             4
399 #define VM_L2_CNTL                                      0x1400
400 #define         ENABLE_L2_CACHE                                 (1 << 0)
401 #define         ENABLE_L2_FRAGMENT_PROCESSING                   (1 << 1)
402 #define         ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE         (1 << 9)
403 #define         EFFECTIVE_L2_QUEUE_SIZE(x)                      (((x) & 7) << 14)
404 #define VM_L2_CNTL2                                     0x1404
405 #define         INVALIDATE_ALL_L1_TLBS                          (1 << 0)
406 #define         INVALIDATE_L2_CACHE                             (1 << 1)
407 #define VM_L2_CNTL3                                     0x1408
408 #define         BANK_SELECT(x)                                  ((x) << 0)
409 #define         CACHE_UPDATE_MODE(x)                            ((x) << 6)
410 #define VM_L2_STATUS                                    0x140C
411 #define         L2_BUSY                                         (1 << 0)
412
413 #define WAIT_UNTIL                                      0x8040
414
415 #define SRBM_STATUS                                     0x0E50
416 #define SRBM_SOFT_RESET                                 0x0E60
417 #define         SRBM_SOFT_RESET_ALL_MASK                0x00FEEFA6
418 #define         SOFT_RESET_BIF                          (1 << 1)
419 #define         SOFT_RESET_CG                           (1 << 2)
420 #define         SOFT_RESET_DC                           (1 << 5)
421 #define         SOFT_RESET_GRBM                         (1 << 8)
422 #define         SOFT_RESET_HDP                          (1 << 9)
423 #define         SOFT_RESET_IH                           (1 << 10)
424 #define         SOFT_RESET_MC                           (1 << 11)
425 #define         SOFT_RESET_RLC                          (1 << 13)
426 #define         SOFT_RESET_ROM                          (1 << 14)
427 #define         SOFT_RESET_SEM                          (1 << 15)
428 #define         SOFT_RESET_VMC                          (1 << 17)
429 #define         SOFT_RESET_TST                          (1 << 21)
430 #define         SOFT_RESET_REGBB                        (1 << 22)
431 #define         SOFT_RESET_ORB                          (1 << 23)
432
433 /* display watermarks */
434 #define DC_LB_MEMORY_SPLIT                                0x6b0c
435 #define PRIORITY_A_CNT                                    0x6b18
436 #define         PRIORITY_MARK_MASK                        0x7fff
437 #define         PRIORITY_OFF                              (1 << 16)
438 #define         PRIORITY_ALWAYS_ON                        (1 << 20)
439 #define PRIORITY_B_CNT                                    0x6b1c
440 #define PIPE0_ARBITRATION_CONTROL3                        0x0bf0
441 #       define LATENCY_WATERMARK_MASK(x)                  ((x) << 16)
442 #define PIPE0_LATENCY_CONTROL                             0x0bf4
443 #       define LATENCY_LOW_WATERMARK(x)                   ((x) << 0)
444 #       define LATENCY_HIGH_WATERMARK(x)                  ((x) << 16)
445
446 #define IH_RB_CNTL                                        0x3e00
447 #       define IH_RB_ENABLE                               (1 << 0)
448 #       define IH_IB_SIZE(x)                              ((x) << 1) /* log2 */
449 #       define IH_RB_FULL_DRAIN_ENABLE                    (1 << 6)
450 #       define IH_WPTR_WRITEBACK_ENABLE                   (1 << 8)
451 #       define IH_WPTR_WRITEBACK_TIMER(x)                 ((x) << 9) /* log2 */
452 #       define IH_WPTR_OVERFLOW_ENABLE                    (1 << 16)
453 #       define IH_WPTR_OVERFLOW_CLEAR                     (1 << 31)
454 #define IH_RB_BASE                                        0x3e04
455 #define IH_RB_RPTR                                        0x3e08
456 #define IH_RB_WPTR                                        0x3e0c
457 #       define RB_OVERFLOW                                (1 << 0)
458 #       define WPTR_OFFSET_MASK                           0x3fffc
459 #define IH_RB_WPTR_ADDR_HI                                0x3e10
460 #define IH_RB_WPTR_ADDR_LO                                0x3e14
461 #define IH_CNTL                                           0x3e18
462 #       define ENABLE_INTR                                (1 << 0)
463 #       define IH_MC_SWAP(x)                              ((x) << 2)
464 #       define IH_MC_SWAP_NONE                            0
465 #       define IH_MC_SWAP_16BIT                           1
466 #       define IH_MC_SWAP_32BIT                           2
467 #       define IH_MC_SWAP_64BIT                           3
468 #       define RPTR_REARM                                 (1 << 4)
469 #       define MC_WRREQ_CREDIT(x)                         ((x) << 15)
470 #       define MC_WR_CLEAN_CNT(x)                         ((x) << 20)
471
472 #define CP_INT_CNTL                                     0xc124
473 #       define CNTX_BUSY_INT_ENABLE                     (1 << 19)
474 #       define CNTX_EMPTY_INT_ENABLE                    (1 << 20)
475 #       define SCRATCH_INT_ENABLE                       (1 << 25)
476 #       define TIME_STAMP_INT_ENABLE                    (1 << 26)
477 #       define IB2_INT_ENABLE                           (1 << 29)
478 #       define IB1_INT_ENABLE                           (1 << 30)
479 #       define RB_INT_ENABLE                            (1 << 31)
480 #define CP_INT_STATUS                                   0xc128
481 #       define SCRATCH_INT_STAT                         (1 << 25)
482 #       define TIME_STAMP_INT_STAT                      (1 << 26)
483 #       define IB2_INT_STAT                             (1 << 29)
484 #       define IB1_INT_STAT                             (1 << 30)
485 #       define RB_INT_STAT                              (1 << 31)
486
487 #define GRBM_INT_CNTL                                   0x8060
488 #       define RDERR_INT_ENABLE                         (1 << 0)
489 #       define GUI_IDLE_INT_ENABLE                      (1 << 19)
490
491 /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */
492 #define CRTC_STATUS_FRAME_COUNT                         0x6e98
493
494 /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */
495 #define VLINE_STATUS                                    0x6bb8
496 #       define VLINE_OCCURRED                           (1 << 0)
497 #       define VLINE_ACK                                (1 << 4)
498 #       define VLINE_STAT                               (1 << 12)
499 #       define VLINE_INTERRUPT                          (1 << 16)
500 #       define VLINE_INTERRUPT_TYPE                     (1 << 17)
501 /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */
502 #define VBLANK_STATUS                                   0x6bbc
503 #       define VBLANK_OCCURRED                          (1 << 0)
504 #       define VBLANK_ACK                               (1 << 4)
505 #       define VBLANK_STAT                              (1 << 12)
506 #       define VBLANK_INTERRUPT                         (1 << 16)
507 #       define VBLANK_INTERRUPT_TYPE                    (1 << 17)
508
509 /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */
510 #define INT_MASK                                        0x6b40
511 #       define VBLANK_INT_MASK                          (1 << 0)
512 #       define VLINE_INT_MASK                           (1 << 4)
513
514 #define DISP_INTERRUPT_STATUS                           0x60f4
515 #       define LB_D1_VLINE_INTERRUPT                    (1 << 2)
516 #       define LB_D1_VBLANK_INTERRUPT                   (1 << 3)
517 #       define DC_HPD1_INTERRUPT                        (1 << 17)
518 #       define DC_HPD1_RX_INTERRUPT                     (1 << 18)
519 #       define DACA_AUTODETECT_INTERRUPT                (1 << 22)
520 #       define DACB_AUTODETECT_INTERRUPT                (1 << 23)
521 #       define DC_I2C_SW_DONE_INTERRUPT                 (1 << 24)
522 #       define DC_I2C_HW_DONE_INTERRUPT                 (1 << 25)
523 #define DISP_INTERRUPT_STATUS_CONTINUE                  0x60f8
524 #       define LB_D2_VLINE_INTERRUPT                    (1 << 2)
525 #       define LB_D2_VBLANK_INTERRUPT                   (1 << 3)
526 #       define DC_HPD2_INTERRUPT                        (1 << 17)
527 #       define DC_HPD2_RX_INTERRUPT                     (1 << 18)
528 #       define DISP_TIMER_INTERRUPT                     (1 << 24)
529 #define DISP_INTERRUPT_STATUS_CONTINUE2                 0x60fc
530 #       define LB_D3_VLINE_INTERRUPT                    (1 << 2)
531 #       define LB_D3_VBLANK_INTERRUPT                   (1 << 3)
532 #       define DC_HPD3_INTERRUPT                        (1 << 17)
533 #       define DC_HPD3_RX_INTERRUPT                     (1 << 18)
534 #define DISP_INTERRUPT_STATUS_CONTINUE3                 0x6100
535 #       define LB_D4_VLINE_INTERRUPT                    (1 << 2)
536 #       define LB_D4_VBLANK_INTERRUPT                   (1 << 3)
537 #       define DC_HPD4_INTERRUPT                        (1 << 17)
538 #       define DC_HPD4_RX_INTERRUPT                     (1 << 18)
539 #define DISP_INTERRUPT_STATUS_CONTINUE4                 0x614c
540 #       define LB_D5_VLINE_INTERRUPT                    (1 << 2)
541 #       define LB_D5_VBLANK_INTERRUPT                   (1 << 3)
542 #       define DC_HPD5_INTERRUPT                        (1 << 17)
543 #       define DC_HPD5_RX_INTERRUPT                     (1 << 18)
544 #define DISP_INTERRUPT_STATUS_CONTINUE5                 0x6050
545 #       define LB_D6_VLINE_INTERRUPT                    (1 << 2)
546 #       define LB_D6_VBLANK_INTERRUPT                   (1 << 3)
547 #       define DC_HPD6_INTERRUPT                        (1 << 17)
548 #       define DC_HPD6_RX_INTERRUPT                     (1 << 18)
549
550 /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
551 #define GRPH_INT_STATUS                                 0x6858
552 #       define GRPH_PFLIP_INT_OCCURRED                  (1 << 0)
553 #       define GRPH_PFLIP_INT_CLEAR                     (1 << 8)
554 /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
555 #define GRPH_INT_CONTROL                                0x685c
556 #       define GRPH_PFLIP_INT_MASK                      (1 << 0)
557 #       define GRPH_PFLIP_INT_TYPE                      (1 << 8)
558
559 #define DACA_AUTODETECT_INT_CONTROL                     0x66c8
560 #define DACB_AUTODETECT_INT_CONTROL                     0x67c8
561
562 #define DC_HPD1_INT_STATUS                              0x601c
563 #define DC_HPD2_INT_STATUS                              0x6028
564 #define DC_HPD3_INT_STATUS                              0x6034
565 #define DC_HPD4_INT_STATUS                              0x6040
566 #define DC_HPD5_INT_STATUS                              0x604c
567 #define DC_HPD6_INT_STATUS                              0x6058
568 #       define DC_HPDx_INT_STATUS                       (1 << 0)
569 #       define DC_HPDx_SENSE                            (1 << 1)
570 #       define DC_HPDx_RX_INT_STATUS                    (1 << 8)
571
572 #define DC_HPD1_INT_CONTROL                             0x6020
573 #define DC_HPD2_INT_CONTROL                             0x602c
574 #define DC_HPD3_INT_CONTROL                             0x6038
575 #define DC_HPD4_INT_CONTROL                             0x6044
576 #define DC_HPD5_INT_CONTROL                             0x6050
577 #define DC_HPD6_INT_CONTROL                             0x605c
578 #       define DC_HPDx_INT_ACK                          (1 << 0)
579 #       define DC_HPDx_INT_POLARITY                     (1 << 8)
580 #       define DC_HPDx_INT_EN                           (1 << 16)
581 #       define DC_HPDx_RX_INT_ACK                       (1 << 20)
582 #       define DC_HPDx_RX_INT_EN                        (1 << 24)
583
584 #define DC_HPD1_CONTROL                                   0x6024
585 #define DC_HPD2_CONTROL                                   0x6030
586 #define DC_HPD3_CONTROL                                   0x603c
587 #define DC_HPD4_CONTROL                                   0x6048
588 #define DC_HPD5_CONTROL                                   0x6054
589 #define DC_HPD6_CONTROL                                   0x6060
590 #       define DC_HPDx_CONNECTION_TIMER(x)                ((x) << 0)
591 #       define DC_HPDx_RX_INT_TIMER(x)                    ((x) << 16)
592 #       define DC_HPDx_EN                                 (1 << 28)
593
594 /* PCIE link stuff */
595 #define PCIE_LC_TRAINING_CNTL                             0xa1 /* PCIE_P */
596 #define PCIE_LC_LINK_WIDTH_CNTL                           0xa2 /* PCIE_P */
597 #       define LC_LINK_WIDTH_SHIFT                        0
598 #       define LC_LINK_WIDTH_MASK                         0x7
599 #       define LC_LINK_WIDTH_X0                           0
600 #       define LC_LINK_WIDTH_X1                           1
601 #       define LC_LINK_WIDTH_X2                           2
602 #       define LC_LINK_WIDTH_X4                           3
603 #       define LC_LINK_WIDTH_X8                           4
604 #       define LC_LINK_WIDTH_X16                          6
605 #       define LC_LINK_WIDTH_RD_SHIFT                     4
606 #       define LC_LINK_WIDTH_RD_MASK                      0x70
607 #       define LC_RECONFIG_ARC_MISSING_ESCAPE             (1 << 7)
608 #       define LC_RECONFIG_NOW                            (1 << 8)
609 #       define LC_RENEGOTIATION_SUPPORT                   (1 << 9)
610 #       define LC_RENEGOTIATE_EN                          (1 << 10)
611 #       define LC_SHORT_RECONFIG_EN                       (1 << 11)
612 #       define LC_UPCONFIGURE_SUPPORT                     (1 << 12)
613 #       define LC_UPCONFIGURE_DIS                         (1 << 13)
614 #define PCIE_LC_SPEED_CNTL                                0xa4 /* PCIE_P */
615 #       define LC_GEN2_EN_STRAP                           (1 << 0)
616 #       define LC_TARGET_LINK_SPEED_OVERRIDE_EN           (1 << 1)
617 #       define LC_FORCE_EN_HW_SPEED_CHANGE                (1 << 5)
618 #       define LC_FORCE_DIS_HW_SPEED_CHANGE               (1 << 6)
619 #       define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK      (0x3 << 8)
620 #       define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT     3
621 #       define LC_CURRENT_DATA_RATE                       (1 << 11)
622 #       define LC_VOLTAGE_TIMER_SEL_MASK                  (0xf << 14)
623 #       define LC_CLR_FAILED_SPD_CHANGE_CNT               (1 << 21)
624 #       define LC_OTHER_SIDE_EVER_SENT_GEN2               (1 << 23)
625 #       define LC_OTHER_SIDE_SUPPORTS_GEN2                (1 << 24)
626 #define MM_CFGREGS_CNTL                                   0x544c
627 #       define MM_WR_TO_CFG_EN                            (1 << 3)
628 #define LINK_CNTL2                                        0x88 /* F0 */
629 #       define TARGET_LINK_SPEED_MASK                     (0xf << 0)
630 #       define SELECTABLE_DEEMPHASIS                      (1 << 6)
631
632 /*
633  * PM4
634  */
635 #define PACKET_TYPE0    0
636 #define PACKET_TYPE1    1
637 #define PACKET_TYPE2    2
638 #define PACKET_TYPE3    3
639
640 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
641 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
642 #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
643 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
644 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) |                         \
645                          (((reg) >> 2) & 0xFFFF) |                      \
646                          ((n) & 0x3FFF) << 16)
647 #define CP_PACKET2                      0x80000000
648 #define         PACKET2_PAD_SHIFT               0
649 #define         PACKET2_PAD_MASK                (0x3fffffff << 0)
650
651 #define PACKET2(v)      (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
652
653 #define PACKET3(op, n)  ((PACKET_TYPE3 << 30) |                         \
654                          (((op) & 0xFF) << 8) |                         \
655                          ((n) & 0x3FFF) << 16)
656
657 /* Packet 3 types */
658 #define PACKET3_NOP                                     0x10
659 #define PACKET3_SET_BASE                                0x11
660 #define PACKET3_CLEAR_STATE                             0x12
661 #define PACKET3_INDEX_BUFFER_SIZE                       0x13
662 #define PACKET3_DISPATCH_DIRECT                         0x15
663 #define PACKET3_DISPATCH_INDIRECT                       0x16
664 #define PACKET3_INDIRECT_BUFFER_END                     0x17
665 #define PACKET3_MODE_CONTROL                            0x18
666 #define PACKET3_SET_PREDICATION                         0x20
667 #define PACKET3_REG_RMW                                 0x21
668 #define PACKET3_COND_EXEC                               0x22
669 #define PACKET3_PRED_EXEC                               0x23
670 #define PACKET3_DRAW_INDIRECT                           0x24
671 #define PACKET3_DRAW_INDEX_INDIRECT                     0x25
672 #define PACKET3_INDEX_BASE                              0x26
673 #define PACKET3_DRAW_INDEX_2                            0x27
674 #define PACKET3_CONTEXT_CONTROL                         0x28
675 #define PACKET3_DRAW_INDEX_OFFSET                       0x29
676 #define PACKET3_INDEX_TYPE                              0x2A
677 #define PACKET3_DRAW_INDEX                              0x2B
678 #define PACKET3_DRAW_INDEX_AUTO                         0x2D
679 #define PACKET3_DRAW_INDEX_IMMD                         0x2E
680 #define PACKET3_NUM_INSTANCES                           0x2F
681 #define PACKET3_DRAW_INDEX_MULTI_AUTO                   0x30
682 #define PACKET3_STRMOUT_BUFFER_UPDATE                   0x34
683 #define PACKET3_DRAW_INDEX_OFFSET_2                     0x35
684 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT                0x36
685 #define PACKET3_MEM_SEMAPHORE                           0x39
686 #define PACKET3_MPEG_INDEX                              0x3A
687 #define PACKET3_WAIT_REG_MEM                            0x3C
688 #define PACKET3_MEM_WRITE                               0x3D
689 #define PACKET3_INDIRECT_BUFFER                         0x32
690 #define PACKET3_SURFACE_SYNC                            0x43
691 #              define PACKET3_CB0_DEST_BASE_ENA    (1 << 6)
692 #              define PACKET3_CB1_DEST_BASE_ENA    (1 << 7)
693 #              define PACKET3_CB2_DEST_BASE_ENA    (1 << 8)
694 #              define PACKET3_CB3_DEST_BASE_ENA    (1 << 9)
695 #              define PACKET3_CB4_DEST_BASE_ENA    (1 << 10)
696 #              define PACKET3_CB5_DEST_BASE_ENA    (1 << 11)
697 #              define PACKET3_CB6_DEST_BASE_ENA    (1 << 12)
698 #              define PACKET3_CB7_DEST_BASE_ENA    (1 << 13)
699 #              define PACKET3_DB_DEST_BASE_ENA     (1 << 14)
700 #              define PACKET3_CB8_DEST_BASE_ENA    (1 << 15)
701 #              define PACKET3_CB9_DEST_BASE_ENA    (1 << 16)
702 #              define PACKET3_CB10_DEST_BASE_ENA   (1 << 17)
703 #              define PACKET3_CB11_DEST_BASE_ENA   (1 << 18)
704 #              define PACKET3_FULL_CACHE_ENA       (1 << 20)
705 #              define PACKET3_TC_ACTION_ENA        (1 << 23)
706 #              define PACKET3_VC_ACTION_ENA        (1 << 24)
707 #              define PACKET3_CB_ACTION_ENA        (1 << 25)
708 #              define PACKET3_DB_ACTION_ENA        (1 << 26)
709 #              define PACKET3_SH_ACTION_ENA        (1 << 27)
710 #              define PACKET3_SX_ACTION_ENA        (1 << 28)
711 #define PACKET3_ME_INITIALIZE                           0x44
712 #define         PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
713 #define PACKET3_COND_WRITE                              0x45
714 #define PACKET3_EVENT_WRITE                             0x46
715 #define PACKET3_EVENT_WRITE_EOP                         0x47
716 #define PACKET3_EVENT_WRITE_EOS                         0x48
717 #define PACKET3_PREAMBLE_CNTL                           0x4A
718 #              define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE     (2 << 28)
719 #              define PACKET3_PREAMBLE_END_CLEAR_STATE       (3 << 28)
720 #define PACKET3_RB_OFFSET                               0x4B
721 #define PACKET3_ALU_PS_CONST_BUFFER_COPY                0x4C
722 #define PACKET3_ALU_VS_CONST_BUFFER_COPY                0x4D
723 #define PACKET3_ALU_PS_CONST_UPDATE                     0x4E
724 #define PACKET3_ALU_VS_CONST_UPDATE                     0x4F
725 #define PACKET3_ONE_REG_WRITE                           0x57
726 #define PACKET3_SET_CONFIG_REG                          0x68
727 #define         PACKET3_SET_CONFIG_REG_START                    0x00008000
728 #define         PACKET3_SET_CONFIG_REG_END                      0x0000ac00
729 #define PACKET3_SET_CONTEXT_REG                         0x69
730 #define         PACKET3_SET_CONTEXT_REG_START                   0x00028000
731 #define         PACKET3_SET_CONTEXT_REG_END                     0x00029000
732 #define PACKET3_SET_ALU_CONST                           0x6A
733 /* alu const buffers only; no reg file */
734 #define PACKET3_SET_BOOL_CONST                          0x6B
735 #define         PACKET3_SET_BOOL_CONST_START                    0x0003a500
736 #define         PACKET3_SET_BOOL_CONST_END                      0x0003a518
737 #define PACKET3_SET_LOOP_CONST                          0x6C
738 #define         PACKET3_SET_LOOP_CONST_START                    0x0003a200
739 #define         PACKET3_SET_LOOP_CONST_END                      0x0003a500
740 #define PACKET3_SET_RESOURCE                            0x6D
741 #define         PACKET3_SET_RESOURCE_START                      0x00030000
742 #define         PACKET3_SET_RESOURCE_END                        0x00038000
743 #define PACKET3_SET_SAMPLER                             0x6E
744 #define         PACKET3_SET_SAMPLER_START                       0x0003c000
745 #define         PACKET3_SET_SAMPLER_END                         0x0003c600
746 #define PACKET3_SET_CTL_CONST                           0x6F
747 #define         PACKET3_SET_CTL_CONST_START                     0x0003cff0
748 #define         PACKET3_SET_CTL_CONST_END                       0x0003ff0c
749 #define PACKET3_SET_RESOURCE_OFFSET                     0x70
750 #define PACKET3_SET_ALU_CONST_VS                        0x71
751 #define PACKET3_SET_ALU_CONST_DI                        0x72
752 #define PACKET3_SET_CONTEXT_REG_INDIRECT                0x73
753 #define PACKET3_SET_RESOURCE_INDIRECT                   0x74
754 #define PACKET3_SET_APPEND_CNT                          0x75
755
756 #define SQ_RESOURCE_CONSTANT_WORD7_0                            0x3001c
757 #define         S__SQ_CONSTANT_TYPE(x)                  (((x) & 3) << 30)
758 #define         G__SQ_CONSTANT_TYPE(x)                  (((x) >> 30) & 3)
759 #define                 SQ_TEX_VTX_INVALID_TEXTURE                      0x0
760 #define                 SQ_TEX_VTX_INVALID_BUFFER                       0x1
761 #define                 SQ_TEX_VTX_VALID_TEXTURE                        0x2
762 #define                 SQ_TEX_VTX_VALID_BUFFER                         0x3
763
764 #define SQ_CONST_MEM_BASE                               0x8df8
765
766 #define SQ_ESGS_RING_BASE                               0x8c40
767 #define SQ_ESGS_RING_SIZE                               0x8c44
768 #define SQ_GSVS_RING_BASE                               0x8c48
769 #define SQ_GSVS_RING_SIZE                               0x8c4c
770 #define SQ_ESTMP_RING_BASE                              0x8c50
771 #define SQ_ESTMP_RING_SIZE                              0x8c54
772 #define SQ_GSTMP_RING_BASE                              0x8c58
773 #define SQ_GSTMP_RING_SIZE                              0x8c5c
774 #define SQ_VSTMP_RING_BASE                              0x8c60
775 #define SQ_VSTMP_RING_SIZE                              0x8c64
776 #define SQ_PSTMP_RING_BASE                              0x8c68
777 #define SQ_PSTMP_RING_SIZE                              0x8c6c
778 #define SQ_LSTMP_RING_BASE                              0x8e10
779 #define SQ_LSTMP_RING_SIZE                              0x8e14
780 #define SQ_HSTMP_RING_BASE                              0x8e18
781 #define SQ_HSTMP_RING_SIZE                              0x8e1c
782 #define VGT_TF_RING_SIZE                                0x8988
783
784 #define SQ_ESGS_RING_ITEMSIZE                           0x28900
785 #define SQ_GSVS_RING_ITEMSIZE                           0x28904
786 #define SQ_ESTMP_RING_ITEMSIZE                          0x28908
787 #define SQ_GSTMP_RING_ITEMSIZE                          0x2890c
788 #define SQ_VSTMP_RING_ITEMSIZE                          0x28910
789 #define SQ_PSTMP_RING_ITEMSIZE                          0x28914
790 #define SQ_LSTMP_RING_ITEMSIZE                          0x28830
791 #define SQ_HSTMP_RING_ITEMSIZE                          0x28834
792
793 #define SQ_GS_VERT_ITEMSIZE                             0x2891c
794 #define SQ_GS_VERT_ITEMSIZE_1                           0x28920
795 #define SQ_GS_VERT_ITEMSIZE_2                           0x28924
796 #define SQ_GS_VERT_ITEMSIZE_3                           0x28928
797 #define SQ_GSVS_RING_OFFSET_1                           0x2892c
798 #define SQ_GSVS_RING_OFFSET_2                           0x28930
799 #define SQ_GSVS_RING_OFFSET_3                           0x28934
800
801 #define SQ_ALU_CONST_BUFFER_SIZE_PS_0                   0x28140
802 #define SQ_ALU_CONST_BUFFER_SIZE_HS_0                   0x28f80
803
804 #define SQ_ALU_CONST_CACHE_PS_0                         0x28940
805 #define SQ_ALU_CONST_CACHE_PS_1                         0x28944
806 #define SQ_ALU_CONST_CACHE_PS_2                         0x28948
807 #define SQ_ALU_CONST_CACHE_PS_3                         0x2894c
808 #define SQ_ALU_CONST_CACHE_PS_4                         0x28950
809 #define SQ_ALU_CONST_CACHE_PS_5                         0x28954
810 #define SQ_ALU_CONST_CACHE_PS_6                         0x28958
811 #define SQ_ALU_CONST_CACHE_PS_7                         0x2895c
812 #define SQ_ALU_CONST_CACHE_PS_8                         0x28960
813 #define SQ_ALU_CONST_CACHE_PS_9                         0x28964
814 #define SQ_ALU_CONST_CACHE_PS_10                        0x28968
815 #define SQ_ALU_CONST_CACHE_PS_11                        0x2896c
816 #define SQ_ALU_CONST_CACHE_PS_12                        0x28970
817 #define SQ_ALU_CONST_CACHE_PS_13                        0x28974
818 #define SQ_ALU_CONST_CACHE_PS_14                        0x28978
819 #define SQ_ALU_CONST_CACHE_PS_15                        0x2897c
820 #define SQ_ALU_CONST_CACHE_VS_0                         0x28980
821 #define SQ_ALU_CONST_CACHE_VS_1                         0x28984
822 #define SQ_ALU_CONST_CACHE_VS_2                         0x28988
823 #define SQ_ALU_CONST_CACHE_VS_3                         0x2898c
824 #define SQ_ALU_CONST_CACHE_VS_4                         0x28990
825 #define SQ_ALU_CONST_CACHE_VS_5                         0x28994
826 #define SQ_ALU_CONST_CACHE_VS_6                         0x28998
827 #define SQ_ALU_CONST_CACHE_VS_7                         0x2899c
828 #define SQ_ALU_CONST_CACHE_VS_8                         0x289a0
829 #define SQ_ALU_CONST_CACHE_VS_9                         0x289a4
830 #define SQ_ALU_CONST_CACHE_VS_10                        0x289a8
831 #define SQ_ALU_CONST_CACHE_VS_11                        0x289ac
832 #define SQ_ALU_CONST_CACHE_VS_12                        0x289b0
833 #define SQ_ALU_CONST_CACHE_VS_13                        0x289b4
834 #define SQ_ALU_CONST_CACHE_VS_14                        0x289b8
835 #define SQ_ALU_CONST_CACHE_VS_15                        0x289bc
836 #define SQ_ALU_CONST_CACHE_GS_0                         0x289c0
837 #define SQ_ALU_CONST_CACHE_GS_1                         0x289c4
838 #define SQ_ALU_CONST_CACHE_GS_2                         0x289c8
839 #define SQ_ALU_CONST_CACHE_GS_3                         0x289cc
840 #define SQ_ALU_CONST_CACHE_GS_4                         0x289d0
841 #define SQ_ALU_CONST_CACHE_GS_5                         0x289d4
842 #define SQ_ALU_CONST_CACHE_GS_6                         0x289d8
843 #define SQ_ALU_CONST_CACHE_GS_7                         0x289dc
844 #define SQ_ALU_CONST_CACHE_GS_8                         0x289e0
845 #define SQ_ALU_CONST_CACHE_GS_9                         0x289e4
846 #define SQ_ALU_CONST_CACHE_GS_10                        0x289e8
847 #define SQ_ALU_CONST_CACHE_GS_11                        0x289ec
848 #define SQ_ALU_CONST_CACHE_GS_12                        0x289f0
849 #define SQ_ALU_CONST_CACHE_GS_13                        0x289f4
850 #define SQ_ALU_CONST_CACHE_GS_14                        0x289f8
851 #define SQ_ALU_CONST_CACHE_GS_15                        0x289fc
852 #define SQ_ALU_CONST_CACHE_HS_0                         0x28f00
853 #define SQ_ALU_CONST_CACHE_HS_1                         0x28f04
854 #define SQ_ALU_CONST_CACHE_HS_2                         0x28f08
855 #define SQ_ALU_CONST_CACHE_HS_3                         0x28f0c
856 #define SQ_ALU_CONST_CACHE_HS_4                         0x28f10
857 #define SQ_ALU_CONST_CACHE_HS_5                         0x28f14
858 #define SQ_ALU_CONST_CACHE_HS_6                         0x28f18
859 #define SQ_ALU_CONST_CACHE_HS_7                         0x28f1c
860 #define SQ_ALU_CONST_CACHE_HS_8                         0x28f20
861 #define SQ_ALU_CONST_CACHE_HS_9                         0x28f24
862 #define SQ_ALU_CONST_CACHE_HS_10                        0x28f28
863 #define SQ_ALU_CONST_CACHE_HS_11                        0x28f2c
864 #define SQ_ALU_CONST_CACHE_HS_12                        0x28f30
865 #define SQ_ALU_CONST_CACHE_HS_13                        0x28f34
866 #define SQ_ALU_CONST_CACHE_HS_14                        0x28f38
867 #define SQ_ALU_CONST_CACHE_HS_15                        0x28f3c
868 #define SQ_ALU_CONST_CACHE_LS_0                         0x28f40
869 #define SQ_ALU_CONST_CACHE_LS_1                         0x28f44
870 #define SQ_ALU_CONST_CACHE_LS_2                         0x28f48
871 #define SQ_ALU_CONST_CACHE_LS_3                         0x28f4c
872 #define SQ_ALU_CONST_CACHE_LS_4                         0x28f50
873 #define SQ_ALU_CONST_CACHE_LS_5                         0x28f54
874 #define SQ_ALU_CONST_CACHE_LS_6                         0x28f58
875 #define SQ_ALU_CONST_CACHE_LS_7                         0x28f5c
876 #define SQ_ALU_CONST_CACHE_LS_8                         0x28f60
877 #define SQ_ALU_CONST_CACHE_LS_9                         0x28f64
878 #define SQ_ALU_CONST_CACHE_LS_10                        0x28f68
879 #define SQ_ALU_CONST_CACHE_LS_11                        0x28f6c
880 #define SQ_ALU_CONST_CACHE_LS_12                        0x28f70
881 #define SQ_ALU_CONST_CACHE_LS_13                        0x28f74
882 #define SQ_ALU_CONST_CACHE_LS_14                        0x28f78
883 #define SQ_ALU_CONST_CACHE_LS_15                        0x28f7c
884
885 #define PA_SC_SCREEN_SCISSOR_TL                         0x28030
886 #define PA_SC_GENERIC_SCISSOR_TL                        0x28240
887 #define PA_SC_WINDOW_SCISSOR_TL                         0x28204
888 #define VGT_PRIMITIVE_TYPE                              0x8958
889
890 #define DB_DEPTH_CONTROL                                0x28800
891 #define DB_DEPTH_VIEW                                   0x28008
892 #define DB_HTILE_DATA_BASE                              0x28014
893 #define DB_Z_INFO                                       0x28040
894 #       define Z_ARRAY_MODE(x)                          ((x) << 4)
895 #define DB_STENCIL_INFO                                 0x28044
896 #define DB_Z_READ_BASE                                  0x28048
897 #define DB_STENCIL_READ_BASE                            0x2804c
898 #define DB_Z_WRITE_BASE                                 0x28050
899 #define DB_STENCIL_WRITE_BASE                           0x28054
900 #define DB_DEPTH_SIZE                                   0x28058
901
902 #define SQ_PGM_START_PS                                 0x28840
903 #define SQ_PGM_START_VS                                 0x2885c
904 #define SQ_PGM_START_GS                                 0x28874
905 #define SQ_PGM_START_ES                                 0x2888c
906 #define SQ_PGM_START_FS                                 0x288a4
907 #define SQ_PGM_START_HS                                 0x288b8
908 #define SQ_PGM_START_LS                                 0x288d0
909
910 #define VGT_STRMOUT_CONFIG                              0x28b94
911 #define VGT_STRMOUT_BUFFER_CONFIG                       0x28b98
912
913 #define CB_TARGET_MASK                                  0x28238
914 #define CB_SHADER_MASK                                  0x2823c
915
916 #define GDS_ADDR_BASE                                   0x28720
917
918 #define CB_IMMED0_BASE                                  0x28b9c
919 #define CB_IMMED1_BASE                                  0x28ba0
920 #define CB_IMMED2_BASE                                  0x28ba4
921 #define CB_IMMED3_BASE                                  0x28ba8
922 #define CB_IMMED4_BASE                                  0x28bac
923 #define CB_IMMED5_BASE                                  0x28bb0
924 #define CB_IMMED6_BASE                                  0x28bb4
925 #define CB_IMMED7_BASE                                  0x28bb8
926 #define CB_IMMED8_BASE                                  0x28bbc
927 #define CB_IMMED9_BASE                                  0x28bc0
928 #define CB_IMMED10_BASE                                 0x28bc4
929 #define CB_IMMED11_BASE                                 0x28bc8
930
931 /* all 12 CB blocks have these regs */
932 #define CB_COLOR0_BASE                                  0x28c60
933 #define CB_COLOR0_PITCH                                 0x28c64
934 #define CB_COLOR0_SLICE                                 0x28c68
935 #define CB_COLOR0_VIEW                                  0x28c6c
936 #define CB_COLOR0_INFO                                  0x28c70
937 #       define CB_ARRAY_MODE(x)                         ((x) << 8)
938 #       define ARRAY_LINEAR_GENERAL                     0
939 #       define ARRAY_LINEAR_ALIGNED                     1
940 #       define ARRAY_1D_TILED_THIN1                     2
941 #       define ARRAY_2D_TILED_THIN1                     4
942 #define CB_COLOR0_ATTRIB                                0x28c74
943 #define CB_COLOR0_DIM                                   0x28c78
944 /* only CB0-7 blocks have these regs */
945 #define CB_COLOR0_CMASK                                 0x28c7c
946 #define CB_COLOR0_CMASK_SLICE                           0x28c80
947 #define CB_COLOR0_FMASK                                 0x28c84
948 #define CB_COLOR0_FMASK_SLICE                           0x28c88
949 #define CB_COLOR0_CLEAR_WORD0                           0x28c8c
950 #define CB_COLOR0_CLEAR_WORD1                           0x28c90
951 #define CB_COLOR0_CLEAR_WORD2                           0x28c94
952 #define CB_COLOR0_CLEAR_WORD3                           0x28c98
953
954 #define CB_COLOR1_BASE                                  0x28c9c
955 #define CB_COLOR2_BASE                                  0x28cd8
956 #define CB_COLOR3_BASE                                  0x28d14
957 #define CB_COLOR4_BASE                                  0x28d50
958 #define CB_COLOR5_BASE                                  0x28d8c
959 #define CB_COLOR6_BASE                                  0x28dc8
960 #define CB_COLOR7_BASE                                  0x28e04
961 #define CB_COLOR8_BASE                                  0x28e40
962 #define CB_COLOR9_BASE                                  0x28e5c
963 #define CB_COLOR10_BASE                                 0x28e78
964 #define CB_COLOR11_BASE                                 0x28e94
965
966 #define CB_COLOR1_PITCH                                 0x28ca0
967 #define CB_COLOR2_PITCH                                 0x28cdc
968 #define CB_COLOR3_PITCH                                 0x28d18
969 #define CB_COLOR4_PITCH                                 0x28d54
970 #define CB_COLOR5_PITCH                                 0x28d90
971 #define CB_COLOR6_PITCH                                 0x28dcc
972 #define CB_COLOR7_PITCH                                 0x28e08
973 #define CB_COLOR8_PITCH                                 0x28e44
974 #define CB_COLOR9_PITCH                                 0x28e60
975 #define CB_COLOR10_PITCH                                0x28e7c
976 #define CB_COLOR11_PITCH                                0x28e98
977
978 #define CB_COLOR1_SLICE                                 0x28ca4
979 #define CB_COLOR2_SLICE                                 0x28ce0
980 #define CB_COLOR3_SLICE                                 0x28d1c
981 #define CB_COLOR4_SLICE                                 0x28d58
982 #define CB_COLOR5_SLICE                                 0x28d94
983 #define CB_COLOR6_SLICE                                 0x28dd0
984 #define CB_COLOR7_SLICE                                 0x28e0c
985 #define CB_COLOR8_SLICE                                 0x28e48
986 #define CB_COLOR9_SLICE                                 0x28e64
987 #define CB_COLOR10_SLICE                                0x28e80
988 #define CB_COLOR11_SLICE                                0x28e9c
989
990 #define CB_COLOR1_VIEW                                  0x28ca8
991 #define CB_COLOR2_VIEW                                  0x28ce4
992 #define CB_COLOR3_VIEW                                  0x28d20
993 #define CB_COLOR4_VIEW                                  0x28d5c
994 #define CB_COLOR5_VIEW                                  0x28d98
995 #define CB_COLOR6_VIEW                                  0x28dd4
996 #define CB_COLOR7_VIEW                                  0x28e10
997 #define CB_COLOR8_VIEW                                  0x28e4c
998 #define CB_COLOR9_VIEW                                  0x28e68
999 #define CB_COLOR10_VIEW                                 0x28e84
1000 #define CB_COLOR11_VIEW                                 0x28ea0
1001
1002 #define CB_COLOR1_INFO                                  0x28cac
1003 #define CB_COLOR2_INFO                                  0x28ce8
1004 #define CB_COLOR3_INFO                                  0x28d24
1005 #define CB_COLOR4_INFO                                  0x28d60
1006 #define CB_COLOR5_INFO                                  0x28d9c
1007 #define CB_COLOR6_INFO                                  0x28dd8
1008 #define CB_COLOR7_INFO                                  0x28e14
1009 #define CB_COLOR8_INFO                                  0x28e50
1010 #define CB_COLOR9_INFO                                  0x28e6c
1011 #define CB_COLOR10_INFO                                 0x28e88
1012 #define CB_COLOR11_INFO                                 0x28ea4
1013
1014 #define CB_COLOR1_ATTRIB                                0x28cb0
1015 #define CB_COLOR2_ATTRIB                                0x28cec
1016 #define CB_COLOR3_ATTRIB                                0x28d28
1017 #define CB_COLOR4_ATTRIB                                0x28d64
1018 #define CB_COLOR5_ATTRIB                                0x28da0
1019 #define CB_COLOR6_ATTRIB                                0x28ddc
1020 #define CB_COLOR7_ATTRIB                                0x28e18
1021 #define CB_COLOR8_ATTRIB                                0x28e54
1022 #define CB_COLOR9_ATTRIB                                0x28e70
1023 #define CB_COLOR10_ATTRIB                               0x28e8c
1024 #define CB_COLOR11_ATTRIB                               0x28ea8
1025
1026 #define CB_COLOR1_DIM                                   0x28cb4
1027 #define CB_COLOR2_DIM                                   0x28cf0
1028 #define CB_COLOR3_DIM                                   0x28d2c
1029 #define CB_COLOR4_DIM                                   0x28d68
1030 #define CB_COLOR5_DIM                                   0x28da4
1031 #define CB_COLOR6_DIM                                   0x28de0
1032 #define CB_COLOR7_DIM                                   0x28e1c
1033 #define CB_COLOR8_DIM                                   0x28e58
1034 #define CB_COLOR9_DIM                                   0x28e74
1035 #define CB_COLOR10_DIM                                  0x28e90
1036 #define CB_COLOR11_DIM                                  0x28eac
1037
1038 #define CB_COLOR1_CMASK                                 0x28cb8
1039 #define CB_COLOR2_CMASK                                 0x28cf4
1040 #define CB_COLOR3_CMASK                                 0x28d30
1041 #define CB_COLOR4_CMASK                                 0x28d6c
1042 #define CB_COLOR5_CMASK                                 0x28da8
1043 #define CB_COLOR6_CMASK                                 0x28de4
1044 #define CB_COLOR7_CMASK                                 0x28e20
1045
1046 #define CB_COLOR1_CMASK_SLICE                           0x28cbc
1047 #define CB_COLOR2_CMASK_SLICE                           0x28cf8
1048 #define CB_COLOR3_CMASK_SLICE                           0x28d34
1049 #define CB_COLOR4_CMASK_SLICE                           0x28d70
1050 #define CB_COLOR5_CMASK_SLICE                           0x28dac
1051 #define CB_COLOR6_CMASK_SLICE                           0x28de8
1052 #define CB_COLOR7_CMASK_SLICE                           0x28e24
1053
1054 #define CB_COLOR1_FMASK                                 0x28cc0
1055 #define CB_COLOR2_FMASK                                 0x28cfc
1056 #define CB_COLOR3_FMASK                                 0x28d38
1057 #define CB_COLOR4_FMASK                                 0x28d74
1058 #define CB_COLOR5_FMASK                                 0x28db0
1059 #define CB_COLOR6_FMASK                                 0x28dec
1060 #define CB_COLOR7_FMASK                                 0x28e28
1061
1062 #define CB_COLOR1_FMASK_SLICE                           0x28cc4
1063 #define CB_COLOR2_FMASK_SLICE                           0x28d00
1064 #define CB_COLOR3_FMASK_SLICE                           0x28d3c
1065 #define CB_COLOR4_FMASK_SLICE                           0x28d78
1066 #define CB_COLOR5_FMASK_SLICE                           0x28db4
1067 #define CB_COLOR6_FMASK_SLICE                           0x28df0
1068 #define CB_COLOR7_FMASK_SLICE                           0x28e2c
1069
1070 #define CB_COLOR1_CLEAR_WORD0                           0x28cc8
1071 #define CB_COLOR2_CLEAR_WORD0                           0x28d04
1072 #define CB_COLOR3_CLEAR_WORD0                           0x28d40
1073 #define CB_COLOR4_CLEAR_WORD0                           0x28d7c
1074 #define CB_COLOR5_CLEAR_WORD0                           0x28db8
1075 #define CB_COLOR6_CLEAR_WORD0                           0x28df4
1076 #define CB_COLOR7_CLEAR_WORD0                           0x28e30
1077
1078 #define CB_COLOR1_CLEAR_WORD1                           0x28ccc
1079 #define CB_COLOR2_CLEAR_WORD1                           0x28d08
1080 #define CB_COLOR3_CLEAR_WORD1                           0x28d44
1081 #define CB_COLOR4_CLEAR_WORD1                           0x28d80
1082 #define CB_COLOR5_CLEAR_WORD1                           0x28dbc
1083 #define CB_COLOR6_CLEAR_WORD1                           0x28df8
1084 #define CB_COLOR7_CLEAR_WORD1                           0x28e34
1085
1086 #define CB_COLOR1_CLEAR_WORD2                           0x28cd0
1087 #define CB_COLOR2_CLEAR_WORD2                           0x28d0c
1088 #define CB_COLOR3_CLEAR_WORD2                           0x28d48
1089 #define CB_COLOR4_CLEAR_WORD2                           0x28d84
1090 #define CB_COLOR5_CLEAR_WORD2                           0x28dc0
1091 #define CB_COLOR6_CLEAR_WORD2                           0x28dfc
1092 #define CB_COLOR7_CLEAR_WORD2                           0x28e38
1093
1094 #define CB_COLOR1_CLEAR_WORD3                           0x28cd4
1095 #define CB_COLOR2_CLEAR_WORD3                           0x28d10
1096 #define CB_COLOR3_CLEAR_WORD3                           0x28d4c
1097 #define CB_COLOR4_CLEAR_WORD3                           0x28d88
1098 #define CB_COLOR5_CLEAR_WORD3                           0x28dc4
1099 #define CB_COLOR6_CLEAR_WORD3                           0x28e00
1100 #define CB_COLOR7_CLEAR_WORD3                           0x28e3c
1101
1102 #define SQ_TEX_RESOURCE_WORD0_0                         0x30000
1103 #define SQ_TEX_RESOURCE_WORD1_0                         0x30004
1104 #       define TEX_ARRAY_MODE(x)                        ((x) << 28)
1105 #define SQ_TEX_RESOURCE_WORD2_0                         0x30008
1106 #define SQ_TEX_RESOURCE_WORD3_0                         0x3000C
1107 #define SQ_TEX_RESOURCE_WORD4_0                         0x30010
1108 #define SQ_TEX_RESOURCE_WORD5_0                         0x30014
1109 #define SQ_TEX_RESOURCE_WORD6_0                         0x30018
1110 #define SQ_TEX_RESOURCE_WORD7_0                         0x3001c
1111
1112 /* cayman 3D regs */
1113 #define CAYMAN_VGT_OFFCHIP_LDS_BASE                     0x89B0
1114 #define CAYMAN_DB_EQAA                                  0x28804
1115 #define CAYMAN_DB_DEPTH_INFO                            0x2803C
1116 #define CAYMAN_PA_SC_AA_CONFIG                          0x28BE0
1117 #define         CAYMAN_MSAA_NUM_SAMPLES_SHIFT           0
1118 #define         CAYMAN_MSAA_NUM_SAMPLES_MASK            0x7
1119 /* cayman packet3 addition */
1120 #define CAYMAN_PACKET3_DEALLOC_STATE                    0x14
1121
1122 #endif