drm/nv50-nvc0: disp channels have fixed purposes, don't "allocate" them
[linux-3.10.git] / drivers / gpu / drm / nouveau / nv50_evo.c
1 /*
2  * Copyright 2010 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24
25 #include "drmP.h"
26
27 #include "nouveau_drv.h"
28 #include "nouveau_dma.h"
29 #include "nouveau_ramht.h"
30 #include "nv50_display.h"
31
32 static void
33 nv50_evo_channel_del(struct nouveau_channel **pevo)
34 {
35         struct nouveau_channel *evo = *pevo;
36
37         if (!evo)
38                 return;
39         *pevo = NULL;
40
41         nouveau_gpuobj_channel_takedown(evo);
42         nouveau_bo_unmap(evo->pushbuf_bo);
43         nouveau_bo_ref(NULL, &evo->pushbuf_bo);
44
45         if (evo->user)
46                 iounmap(evo->user);
47
48         kfree(evo);
49 }
50
51 int
52 nv50_evo_dmaobj_new(struct nouveau_channel *evo, u32 class, u32 name,
53                     u32 tile_flags, u32 magic_flags, u32 offset, u32 limit,
54                     u32 flags5)
55 {
56         struct drm_nouveau_private *dev_priv = evo->dev->dev_private;
57         struct nv50_display *disp = nv50_display(evo->dev);
58         struct nouveau_gpuobj *obj = NULL;
59         int ret;
60
61         ret = nouveau_gpuobj_new(evo->dev, disp->master, 6*4, 32, 0, &obj);
62         if (ret)
63                 return ret;
64         obj->engine = NVOBJ_ENGINE_DISPLAY;
65
66         nv_wo32(obj,  0, (tile_flags << 22) | (magic_flags << 16) | class);
67         nv_wo32(obj,  4, limit);
68         nv_wo32(obj,  8, offset);
69         nv_wo32(obj, 12, 0x00000000);
70         nv_wo32(obj, 16, 0x00000000);
71         nv_wo32(obj, 20, flags5);
72         dev_priv->engine.instmem.flush(evo->dev);
73
74         ret = nouveau_ramht_insert(evo, name, obj);
75         nouveau_gpuobj_ref(NULL, &obj);
76         if (ret) {
77                 return ret;
78         }
79
80         return 0;
81 }
82
83 static int
84 nv50_evo_channel_new(struct drm_device *dev, int chid,
85                      struct nouveau_channel **pevo)
86 {
87         struct nv50_display *disp = nv50_display(dev);
88         struct nouveau_channel *evo;
89         int ret;
90
91         evo = kzalloc(sizeof(struct nouveau_channel), GFP_KERNEL);
92         if (!evo)
93                 return -ENOMEM;
94         *pevo = evo;
95
96         evo->id = chid;
97         evo->dev = dev;
98         evo->user_get = 4;
99         evo->user_put = 0;
100
101         ret = nouveau_bo_new(dev, NULL, 4096, 0, TTM_PL_FLAG_VRAM, 0, 0,
102                              false, true, &evo->pushbuf_bo);
103         if (ret == 0)
104                 ret = nouveau_bo_pin(evo->pushbuf_bo, TTM_PL_FLAG_VRAM);
105         if (ret) {
106                 NV_ERROR(dev, "Error creating EVO DMA push buffer: %d\n", ret);
107                 nv50_evo_channel_del(pevo);
108                 return ret;
109         }
110
111         ret = nouveau_bo_map(evo->pushbuf_bo);
112         if (ret) {
113                 NV_ERROR(dev, "Error mapping EVO DMA push buffer: %d\n", ret);
114                 nv50_evo_channel_del(pevo);
115                 return ret;
116         }
117
118         evo->user = ioremap(pci_resource_start(dev->pdev, 0) +
119                             NV50_PDISPLAY_USER(evo->id), PAGE_SIZE);
120         if (!evo->user) {
121                 NV_ERROR(dev, "Error mapping EVO control regs.\n");
122                 nv50_evo_channel_del(pevo);
123                 return -ENOMEM;
124         }
125
126         /* bind primary evo channel's ramht to the channel */
127         if (disp->master && evo != disp->master)
128                 nouveau_ramht_ref(disp->master->ramht, &evo->ramht, NULL);
129
130         return 0;
131 }
132
133 static int
134 nv50_evo_channel_init(struct nouveau_channel *evo)
135 {
136         struct drm_device *dev = evo->dev;
137         int id = evo->id, ret, i;
138         u64 pushbuf = evo->pushbuf_bo->bo.mem.start << PAGE_SHIFT;
139         u32 tmp;
140
141         tmp = nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id));
142         if ((tmp & 0x009f0000) == 0x00020000)
143                 nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), tmp | 0x00800000);
144
145         tmp = nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id));
146         if ((tmp & 0x003f0000) == 0x00030000)
147                 nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), tmp | 0x00600000);
148
149         /* initialise fifo */
150         nv_wr32(dev, NV50_PDISPLAY_EVO_DMA_CB(id), pushbuf >> 8 |
151                      NV50_PDISPLAY_EVO_DMA_CB_LOCATION_VRAM |
152                      NV50_PDISPLAY_EVO_DMA_CB_VALID);
153         nv_wr32(dev, NV50_PDISPLAY_EVO_UNK2(id), 0x00010000);
154         nv_wr32(dev, NV50_PDISPLAY_EVO_HASH_TAG(id), id);
155         nv_mask(dev, NV50_PDISPLAY_EVO_CTRL(id), NV50_PDISPLAY_EVO_CTRL_DMA,
156                      NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED);
157
158         nv_wr32(dev, NV50_PDISPLAY_USER_PUT(id), 0x00000000);
159         nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x01000003 |
160                      NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED);
161         if (!nv_wait(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x80000000, 0x00000000)) {
162                 NV_ERROR(dev, "EvoCh %d init timeout: 0x%08x\n", id,
163                          nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id)));
164                 return -EBUSY;
165         }
166
167         /* enable error reporting on the channel */
168         nv_mask(dev, 0x610028, 0x00000000, 0x00010001 << id);
169
170         evo->dma.max = (4096/4) - 2;
171         evo->dma.put = 0;
172         evo->dma.cur = evo->dma.put;
173         evo->dma.free = evo->dma.max - evo->dma.cur;
174
175         ret = RING_SPACE(evo, NOUVEAU_DMA_SKIPS);
176         if (ret)
177                 return ret;
178
179         for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
180                 OUT_RING(evo, 0);
181
182         return 0;
183 }
184
185 static void
186 nv50_evo_channel_fini(struct nouveau_channel *evo)
187 {
188         struct drm_device *dev = evo->dev;
189         int id = evo->id;
190
191         nv_mask(dev, 0x610028, 0x00010001 << id, 0x00000000);
192         nv_mask(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x00001010, 0x00001000);
193         nv_wr32(dev, NV50_PDISPLAY_INTR_0, (1 << id));
194         nv_mask(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x00000003, 0x00000000);
195         if (!nv_wait(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x001e0000, 0x00000000)) {
196                 NV_ERROR(dev, "EvoCh %d takedown timeout: 0x%08x\n", id,
197                          nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id)));
198         }
199 }
200
201 static int
202 nv50_evo_create(struct drm_device *dev)
203 {
204         struct drm_nouveau_private *dev_priv = dev->dev_private;
205         struct nv50_display *disp = nv50_display(dev);
206         struct nouveau_gpuobj *ramht = NULL;
207         struct nouveau_channel *evo;
208         int ret;
209
210         /* create primary evo channel, the one we use for modesetting
211          * purporses
212          */
213         ret = nv50_evo_channel_new(dev, 0, &disp->master);
214         if (ret)
215                 return ret;
216         evo = disp->master;
217
218         /* setup object management on it, any other evo channel will
219          * use this also as there's no per-channel support on the
220          * hardware
221          */
222         ret = nouveau_gpuobj_new(dev, NULL, 32768, 65536,
223                                  NVOBJ_FLAG_ZERO_ALLOC, &evo->ramin);
224         if (ret) {
225                 NV_ERROR(dev, "Error allocating EVO channel memory: %d\n", ret);
226                 nv50_evo_channel_del(&disp->master);
227                 return ret;
228         }
229
230         ret = drm_mm_init(&evo->ramin_heap, 0, 32768);
231         if (ret) {
232                 NV_ERROR(dev, "Error initialising EVO PRAMIN heap: %d\n", ret);
233                 nv50_evo_channel_del(&disp->master);
234                 return ret;
235         }
236
237         ret = nouveau_gpuobj_new(dev, evo, 4096, 16, 0, &ramht);
238         if (ret) {
239                 NV_ERROR(dev, "Unable to allocate EVO RAMHT: %d\n", ret);
240                 nv50_evo_channel_del(&disp->master);
241                 return ret;
242         }
243
244         ret = nouveau_ramht_new(dev, ramht, &evo->ramht);
245         nouveau_gpuobj_ref(NULL, &ramht);
246         if (ret) {
247                 nv50_evo_channel_del(&disp->master);
248                 return ret;
249         }
250
251         /* create some default objects for the scanout memtypes we support */
252         if (dev_priv->card_type >= NV_C0) {
253                 ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoFB32, 0xfe, 0x19,
254                                           0, 0xffffffff, 0x00000000);
255                 if (ret) {
256                         nv50_evo_channel_del(&disp->master);
257                         return ret;
258                 }
259
260                 ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoVRAM, 0, 0x19,
261                                           0, dev_priv->vram_size, 0x00020000);
262                 if (ret) {
263                         nv50_evo_channel_del(&disp->master);
264                         return ret;
265                 }
266
267                 ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoVRAM_LP, 0, 0x19,
268                                           0, dev_priv->vram_size, 0x00000000);
269                 if (ret) {
270                         nv50_evo_channel_del(&disp->master);
271                         return ret;
272                 }
273         } else {
274                 ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoFB16, 0x70, 0x19,
275                                           0, 0xffffffff, 0x00010000);
276                 if (ret) {
277                         nv50_evo_channel_del(&disp->master);
278                         return ret;
279                 }
280
281
282                 ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoFB32, 0x7a, 0x19,
283                                           0, 0xffffffff, 0x00010000);
284                 if (ret) {
285                         nv50_evo_channel_del(&disp->master);
286                         return ret;
287                 }
288
289                 ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoVRAM, 0, 0x19,
290                                           0, dev_priv->vram_size, 0x00010000);
291                 if (ret) {
292                         nv50_evo_channel_del(&disp->master);
293                         return ret;
294                 }
295
296                 ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoVRAM_LP, 0, 0x19,
297                                           0, dev_priv->vram_size, 0x00010000);
298                 if (ret) {
299                         nv50_evo_channel_del(&disp->master);
300                         return ret;
301                 }
302         }
303
304         return 0;
305 }
306
307 int
308 nv50_evo_init(struct drm_device *dev)
309 {
310         struct nv50_display *disp = nv50_display(dev);
311         int ret;
312
313         if (!disp->master) {
314                 ret = nv50_evo_create(dev);
315                 if (ret)
316                         return ret;
317         }
318
319         return nv50_evo_channel_init(disp->master);
320 }
321
322 void
323 nv50_evo_fini(struct drm_device *dev)
324 {
325         struct nv50_display *disp = nv50_display(dev);
326
327         if (disp->master) {
328                 nv50_evo_channel_fini(disp->master);
329                 nv50_evo_channel_del(&disp->master);
330         }
331 }