drm/nouveau: port all engines to new engine module format
[linux-3.10.git] / drivers / gpu / drm / nouveau / nv10_fence.c
1 /*
2  * Copyright 2012 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs <bskeggs@redhat.com>
23  */
24
25 #include <core/object.h>
26 #include <core/class.h>
27
28 #include "nouveau_drm.h"
29 #include "nouveau_dma.h"
30 #include "nouveau_fence.h"
31
32 struct nv10_fence_chan {
33         struct nouveau_fence_chan base;
34 };
35
36 struct nv10_fence_priv {
37         struct nouveau_fence_priv base;
38         struct nouveau_bo *bo;
39         spinlock_t lock;
40         u32 sequence;
41 };
42
43 int
44 nv10_fence_emit(struct nouveau_fence *fence)
45 {
46         struct nouveau_channel *chan = fence->channel;
47         int ret = RING_SPACE(chan, 2);
48         if (ret == 0) {
49                 BEGIN_NV04(chan, 0, NV10_SUBCHAN_REF_CNT, 1);
50                 OUT_RING  (chan, fence->sequence);
51                 FIRE_RING (chan);
52         }
53         return ret;
54 }
55
56
57 static int
58 nv10_fence_sync(struct nouveau_fence *fence,
59                 struct nouveau_channel *prev, struct nouveau_channel *chan)
60 {
61         return -ENODEV;
62 }
63
64 int
65 nv17_fence_sync(struct nouveau_fence *fence,
66                 struct nouveau_channel *prev, struct nouveau_channel *chan)
67 {
68         struct nv10_fence_priv *priv = chan->drm->fence;
69         u32 value;
70         int ret;
71
72         if (!mutex_trylock(&prev->cli->mutex))
73                 return -EBUSY;
74
75         spin_lock(&priv->lock);
76         value = priv->sequence;
77         priv->sequence += 2;
78         spin_unlock(&priv->lock);
79
80         ret = RING_SPACE(prev, 5);
81         if (!ret) {
82                 BEGIN_NV04(prev, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 4);
83                 OUT_RING  (prev, NvSema);
84                 OUT_RING  (prev, 0);
85                 OUT_RING  (prev, value + 0);
86                 OUT_RING  (prev, value + 1);
87                 FIRE_RING (prev);
88         }
89
90         if (!ret && !(ret = RING_SPACE(chan, 5))) {
91                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 4);
92                 OUT_RING  (chan, NvSema);
93                 OUT_RING  (chan, 0);
94                 OUT_RING  (chan, value + 1);
95                 OUT_RING  (chan, value + 2);
96                 FIRE_RING (chan);
97         }
98
99         mutex_unlock(&prev->cli->mutex);
100         return 0;
101 }
102
103 u32
104 nv10_fence_read(struct nouveau_channel *chan)
105 {
106         return nv_ro32(chan->object, 0x0048);
107 }
108
109 void
110 nv10_fence_context_del(struct nouveau_channel *chan)
111 {
112         struct nv10_fence_chan *fctx = chan->fence;
113         nouveau_fence_context_del(&fctx->base);
114         chan->fence = NULL;
115         kfree(fctx);
116 }
117
118 static int
119 nv10_fence_context_new(struct nouveau_channel *chan)
120 {
121         struct nv10_fence_priv *priv = chan->drm->fence;
122         struct nv10_fence_chan *fctx;
123         int ret = 0;
124
125         fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
126         if (!fctx)
127                 return -ENOMEM;
128
129         nouveau_fence_context_new(&fctx->base);
130
131         if (priv->bo) {
132                 struct ttm_mem_reg *mem = &priv->bo->bo.mem;
133                 struct nouveau_object *object;
134                 u32 start = mem->start * PAGE_SIZE;
135                 u32 limit = mem->start + mem->size - 1;
136
137                 ret = nouveau_object_new(nv_object(chan->cli), chan->handle,
138                                          NvSema, 0x0002,
139                                          &(struct nv_dma_class) {
140                                                 .flags = NV_DMA_TARGET_VRAM |
141                                                          NV_DMA_ACCESS_RDWR,
142                                                 .start = start,
143                                                 .limit = limit,
144                                          }, sizeof(struct nv_dma_class),
145                                          &object);
146         }
147
148         if (ret)
149                 nv10_fence_context_del(chan);
150         return ret;
151 }
152
153 void
154 nv10_fence_destroy(struct nouveau_drm *drm)
155 {
156         struct nv10_fence_priv *priv = drm->fence;
157         nouveau_bo_unmap(priv->bo);
158         nouveau_bo_ref(NULL, &priv->bo);
159         drm->fence = NULL;
160         kfree(priv);
161 }
162
163 int
164 nv10_fence_create(struct nouveau_drm *drm)
165 {
166         struct nv10_fence_priv *priv;
167         int ret = 0;
168
169         priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
170         if (!priv)
171                 return -ENOMEM;
172
173         priv->base.dtor = nv10_fence_destroy;
174         priv->base.context_new = nv10_fence_context_new;
175         priv->base.context_del = nv10_fence_context_del;
176         priv->base.emit = nv10_fence_emit;
177         priv->base.read = nv10_fence_read;
178         priv->base.sync = nv10_fence_sync;
179         spin_lock_init(&priv->lock);
180
181         if (nv_device(drm->device)->chipset >= 0x17) {
182                 ret = nouveau_bo_new(drm->dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
183                                      0, 0x0000, NULL, &priv->bo);
184                 if (!ret) {
185                         ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM);
186                         if (!ret)
187                                 ret = nouveau_bo_map(priv->bo);
188                         if (ret)
189                                 nouveau_bo_ref(NULL, &priv->bo);
190                 }
191
192                 if (ret == 0) {
193                         nouveau_bo_wr32(priv->bo, 0x000, 0x00000000);
194                         priv->base.sync = nv17_fence_sync;
195                 }
196         }
197
198         if (ret)
199                 nv10_fence_destroy(drm);
200         return ret;
201 }