drm/nouveau: port all engines to new engine module format
[linux-3.10.git] / drivers / gpu / drm / nouveau / core / engine / fifo / nv17.c
1 /*
2  * Copyright 2012 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24
25 #include <core/os.h>
26 #include <core/class.h>
27 #include <core/engctx.h>
28 #include <core/ramht.h>
29
30 #include <subdev/instmem.h>
31 #include <subdev/instmem/nv04.h>
32 #include <subdev/fb.h>
33
34 #include <engine/fifo.h>
35
36 #include "nv04.h"
37
38 static struct ramfc_desc
39 nv17_ramfc[] = {
40         { 32,  0, 0x00,  0, NV04_PFIFO_CACHE1_DMA_PUT },
41         { 32,  0, 0x04,  0, NV04_PFIFO_CACHE1_DMA_GET },
42         { 32,  0, 0x08,  0, NV10_PFIFO_CACHE1_REF_CNT },
43         { 16,  0, 0x0c,  0, NV04_PFIFO_CACHE1_DMA_INSTANCE },
44         { 16, 16, 0x0c,  0, NV04_PFIFO_CACHE1_DMA_DCOUNT },
45         { 32,  0, 0x10,  0, NV04_PFIFO_CACHE1_DMA_STATE },
46         { 32,  0, 0x14,  0, NV04_PFIFO_CACHE1_DMA_FETCH },
47         { 32,  0, 0x18,  0, NV04_PFIFO_CACHE1_ENGINE },
48         { 32,  0, 0x1c,  0, NV04_PFIFO_CACHE1_PULL1 },
49         { 32,  0, 0x20,  0, NV10_PFIFO_CACHE1_ACQUIRE_VALUE },
50         { 32,  0, 0x24,  0, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP },
51         { 32,  0, 0x28,  0, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT },
52         { 32,  0, 0x2c,  0, NV10_PFIFO_CACHE1_SEMAPHORE },
53         { 32,  0, 0x30,  0, NV10_PFIFO_CACHE1_DMA_SUBROUTINE },
54         {}
55 };
56
57 /*******************************************************************************
58  * FIFO channel objects
59  ******************************************************************************/
60
61 static int
62 nv17_fifo_chan_ctor(struct nouveau_object *parent,
63                     struct nouveau_object *engine,
64                     struct nouveau_oclass *oclass, void *data, u32 size,
65                     struct nouveau_object **pobject)
66 {
67         struct nv04_fifo_priv *priv = (void *)engine;
68         struct nv04_fifo_chan *chan;
69         struct nv_channel_dma_class *args = data;
70         int ret;
71
72         if (size < sizeof(*args))
73                 return -EINVAL;
74
75         ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0x800000,
76                                           0x10000, args->pushbuf,
77                                           (1 << NVDEV_ENGINE_DMAOBJ) |
78                                           (1 << NVDEV_ENGINE_SW) |
79                                           (1 << NVDEV_ENGINE_GR) |
80                                           (1 << NVDEV_ENGINE_MPEG), /* NV31- */
81                                           &chan);
82         *pobject = nv_object(chan);
83         if (ret)
84                 return ret;
85
86         nv_parent(chan)->object_attach = nv04_fifo_object_attach;
87         nv_parent(chan)->object_detach = nv04_fifo_object_detach;
88         chan->ramfc = chan->base.chid * 64;
89
90         nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->offset);
91         nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->offset);
92         nv_wo32(priv->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4);
93         nv_wo32(priv->ramfc, chan->ramfc + 0x14,
94                              NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
95                              NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
96 #ifdef __BIG_ENDIAN
97                              NV_PFIFO_CACHE1_BIG_ENDIAN |
98 #endif
99                              NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8);
100         return 0;
101 }
102
103 static struct nouveau_ofuncs
104 nv17_fifo_ofuncs = {
105         .ctor = nv17_fifo_chan_ctor,
106         .dtor = nv04_fifo_chan_dtor,
107         .init = nv04_fifo_chan_init,
108         .fini = nv04_fifo_chan_fini,
109         .rd32 = _nouveau_fifo_channel_rd32,
110         .wr32 = _nouveau_fifo_channel_wr32,
111 };
112
113 static struct nouveau_oclass
114 nv17_fifo_sclass[] = {
115         { 0x006e, &nv17_fifo_ofuncs },
116         {}
117 };
118
119 /*******************************************************************************
120  * FIFO context - basically just the instmem reserved for the channel
121  ******************************************************************************/
122
123 static struct nouveau_oclass
124 nv17_fifo_cclass = {
125         .handle = NV_ENGCTX(FIFO, 0x17),
126         .ofuncs = &(struct nouveau_ofuncs) {
127                 .ctor = nv04_fifo_context_ctor,
128                 .dtor = _nouveau_fifo_context_dtor,
129                 .init = _nouveau_fifo_context_init,
130                 .fini = _nouveau_fifo_context_fini,
131                 .rd32 = _nouveau_fifo_context_rd32,
132                 .wr32 = _nouveau_fifo_context_wr32,
133         },
134 };
135
136 /*******************************************************************************
137  * PFIFO engine
138  ******************************************************************************/
139
140 static int
141 nv17_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
142                struct nouveau_oclass *oclass, void *data, u32 size,
143                struct nouveau_object **pobject)
144 {
145         struct nv04_instmem_priv *imem = nv04_instmem(parent);
146         struct nv04_fifo_priv *priv;
147         int ret;
148
149         ret = nouveau_fifo_create(parent, engine, oclass, 0, 31, &priv);
150         *pobject = nv_object(priv);
151         if (ret)
152                 return ret;
153
154         nouveau_ramht_ref(imem->ramht, &priv->ramht);
155         nouveau_gpuobj_ref(imem->ramro, &priv->ramro);
156         nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc);
157
158         nv_subdev(priv)->unit = 0x00000100;
159         nv_subdev(priv)->intr = nv04_fifo_intr;
160         nv_engine(priv)->cclass = &nv17_fifo_cclass;
161         nv_engine(priv)->sclass = nv17_fifo_sclass;
162         priv->base.pause = nv04_fifo_pause;
163         priv->base.start = nv04_fifo_start;
164         priv->ramfc_desc = nv17_ramfc;
165         return 0;
166 }
167
168 static int
169 nv17_fifo_init(struct nouveau_object *object)
170 {
171         struct nv04_fifo_priv *priv = (void *)object;
172         int ret;
173
174         ret = nouveau_fifo_init(&priv->base);
175         if (ret)
176                 return ret;
177
178         nv_wr32(priv, NV04_PFIFO_DELAY_0, 0x000000ff);
179         nv_wr32(priv, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff);
180
181         nv_wr32(priv, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
182                                        ((priv->ramht->bits - 9) << 16) |
183                                         (priv->ramht->base.addr >> 8));
184         nv_wr32(priv, NV03_PFIFO_RAMRO, priv->ramro->addr >> 8);
185         nv_wr32(priv, NV03_PFIFO_RAMFC, priv->ramfc->addr >> 8 | 0x00010000);
186
187         nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH1, priv->base.max);
188
189         nv_wr32(priv, NV03_PFIFO_INTR_0, 0xffffffff);
190         nv_wr32(priv, NV03_PFIFO_INTR_EN_0, 0xffffffff);
191
192         nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, 1);
193         nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1);
194         nv_wr32(priv, NV03_PFIFO_CACHES, 1);
195         return 0;
196 }
197
198 struct nouveau_oclass
199 nv17_fifo_oclass = {
200         .handle = NV_ENGINE(FIFO, 0x17),
201         .ofuncs = &(struct nouveau_ofuncs) {
202                 .ctor = nv17_fifo_ctor,
203                 .dtor = nv04_fifo_dtor,
204                 .init = nv17_fifo_init,
205                 .fini = _nouveau_fifo_fini,
206         },
207 };