e2c93f7be8edea400941a30926acbe36fd50bcaa
[linux-3.10.git] / drivers / gpu / drm / i915 / i915_gem.c
1 /*
2  * Copyright © 2008 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Authors:
24  *    Eric Anholt <eric@anholt.net>
25  *
26  */
27
28 #include <drm/drmP.h>
29 #include <drm/i915_drm.h>
30 #include "i915_drv.h"
31 #include "i915_trace.h"
32 #include "intel_drv.h"
33 #include <linux/shmem_fs.h>
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/dma-buf.h>
38
39 static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj);
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
42 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
43                                                     unsigned alignment,
44                                                     bool map_and_fenceable);
45 static int i915_gem_phys_pwrite(struct drm_device *dev,
46                                 struct drm_i915_gem_object *obj,
47                                 struct drm_i915_gem_pwrite *args,
48                                 struct drm_file *file);
49
50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
51                                  struct drm_i915_gem_object *obj);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
53                                          struct drm_i915_fence_reg *fence,
54                                          bool enable);
55
56 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
57                                     struct shrink_control *sc);
58 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
59
60 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
61 {
62         if (obj->tiling_mode)
63                 i915_gem_release_mmap(obj);
64
65         /* As we do not have an associated fence register, we will force
66          * a tiling change if we ever need to acquire one.
67          */
68         obj->fence_dirty = false;
69         obj->fence_reg = I915_FENCE_REG_NONE;
70 }
71
72 /* some bookkeeping */
73 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
74                                   size_t size)
75 {
76         dev_priv->mm.object_count++;
77         dev_priv->mm.object_memory += size;
78 }
79
80 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
81                                      size_t size)
82 {
83         dev_priv->mm.object_count--;
84         dev_priv->mm.object_memory -= size;
85 }
86
87 static int
88 i915_gem_wait_for_error(struct drm_device *dev)
89 {
90         struct drm_i915_private *dev_priv = dev->dev_private;
91         struct completion *x = &dev_priv->error_completion;
92         unsigned long flags;
93         int ret;
94
95         if (!atomic_read(&dev_priv->mm.wedged))
96                 return 0;
97
98         /*
99          * Only wait 10 seconds for the gpu reset to complete to avoid hanging
100          * userspace. If it takes that long something really bad is going on and
101          * we should simply try to bail out and fail as gracefully as possible.
102          */
103         ret = wait_for_completion_interruptible_timeout(x, 10*HZ);
104         if (ret == 0) {
105                 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
106                 return -EIO;
107         } else if (ret < 0) {
108                 return ret;
109         }
110
111         if (atomic_read(&dev_priv->mm.wedged)) {
112                 /* GPU is hung, bump the completion count to account for
113                  * the token we just consumed so that we never hit zero and
114                  * end up waiting upon a subsequent completion event that
115                  * will never happen.
116                  */
117                 spin_lock_irqsave(&x->wait.lock, flags);
118                 x->done++;
119                 spin_unlock_irqrestore(&x->wait.lock, flags);
120         }
121         return 0;
122 }
123
124 int i915_mutex_lock_interruptible(struct drm_device *dev)
125 {
126         int ret;
127
128         ret = i915_gem_wait_for_error(dev);
129         if (ret)
130                 return ret;
131
132         ret = mutex_lock_interruptible(&dev->struct_mutex);
133         if (ret)
134                 return ret;
135
136         WARN_ON(i915_verify_lists(dev));
137         return 0;
138 }
139
140 static inline bool
141 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
142 {
143         return !obj->active;
144 }
145
146 int
147 i915_gem_init_ioctl(struct drm_device *dev, void *data,
148                     struct drm_file *file)
149 {
150         struct drm_i915_gem_init *args = data;
151
152         if (drm_core_check_feature(dev, DRIVER_MODESET))
153                 return -ENODEV;
154
155         if (args->gtt_start >= args->gtt_end ||
156             (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
157                 return -EINVAL;
158
159         /* GEM with user mode setting was never supported on ilk and later. */
160         if (INTEL_INFO(dev)->gen >= 5)
161                 return -ENODEV;
162
163         mutex_lock(&dev->struct_mutex);
164         i915_gem_init_global_gtt(dev, args->gtt_start,
165                                  args->gtt_end, args->gtt_end);
166         mutex_unlock(&dev->struct_mutex);
167
168         return 0;
169 }
170
171 int
172 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
173                             struct drm_file *file)
174 {
175         struct drm_i915_private *dev_priv = dev->dev_private;
176         struct drm_i915_gem_get_aperture *args = data;
177         struct drm_i915_gem_object *obj;
178         size_t pinned;
179
180         pinned = 0;
181         mutex_lock(&dev->struct_mutex);
182         list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list)
183                 if (obj->pin_count)
184                         pinned += obj->gtt_space->size;
185         mutex_unlock(&dev->struct_mutex);
186
187         args->aper_size = dev_priv->mm.gtt_total;
188         args->aper_available_size = args->aper_size - pinned;
189
190         return 0;
191 }
192
193 static int
194 i915_gem_create(struct drm_file *file,
195                 struct drm_device *dev,
196                 uint64_t size,
197                 uint32_t *handle_p)
198 {
199         struct drm_i915_gem_object *obj;
200         int ret;
201         u32 handle;
202
203         size = roundup(size, PAGE_SIZE);
204         if (size == 0)
205                 return -EINVAL;
206
207         /* Allocate the new object */
208         obj = i915_gem_alloc_object(dev, size);
209         if (obj == NULL)
210                 return -ENOMEM;
211
212         ret = drm_gem_handle_create(file, &obj->base, &handle);
213         if (ret) {
214                 drm_gem_object_release(&obj->base);
215                 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
216                 kfree(obj);
217                 return ret;
218         }
219
220         /* drop reference from allocate - handle holds it now */
221         drm_gem_object_unreference(&obj->base);
222         trace_i915_gem_object_create(obj);
223
224         *handle_p = handle;
225         return 0;
226 }
227
228 int
229 i915_gem_dumb_create(struct drm_file *file,
230                      struct drm_device *dev,
231                      struct drm_mode_create_dumb *args)
232 {
233         /* have to work out size/pitch and return them */
234         args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
235         args->size = args->pitch * args->height;
236         return i915_gem_create(file, dev,
237                                args->size, &args->handle);
238 }
239
240 int i915_gem_dumb_destroy(struct drm_file *file,
241                           struct drm_device *dev,
242                           uint32_t handle)
243 {
244         return drm_gem_handle_delete(file, handle);
245 }
246
247 /**
248  * Creates a new mm object and returns a handle to it.
249  */
250 int
251 i915_gem_create_ioctl(struct drm_device *dev, void *data,
252                       struct drm_file *file)
253 {
254         struct drm_i915_gem_create *args = data;
255
256         return i915_gem_create(file, dev,
257                                args->size, &args->handle);
258 }
259
260 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
261 {
262         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
263
264         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
265                 obj->tiling_mode != I915_TILING_NONE;
266 }
267
268 static inline int
269 __copy_to_user_swizzled(char __user *cpu_vaddr,
270                         const char *gpu_vaddr, int gpu_offset,
271                         int length)
272 {
273         int ret, cpu_offset = 0;
274
275         while (length > 0) {
276                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
277                 int this_length = min(cacheline_end - gpu_offset, length);
278                 int swizzled_gpu_offset = gpu_offset ^ 64;
279
280                 ret = __copy_to_user(cpu_vaddr + cpu_offset,
281                                      gpu_vaddr + swizzled_gpu_offset,
282                                      this_length);
283                 if (ret)
284                         return ret + length;
285
286                 cpu_offset += this_length;
287                 gpu_offset += this_length;
288                 length -= this_length;
289         }
290
291         return 0;
292 }
293
294 static inline int
295 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
296                           const char __user *cpu_vaddr,
297                           int length)
298 {
299         int ret, cpu_offset = 0;
300
301         while (length > 0) {
302                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
303                 int this_length = min(cacheline_end - gpu_offset, length);
304                 int swizzled_gpu_offset = gpu_offset ^ 64;
305
306                 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
307                                        cpu_vaddr + cpu_offset,
308                                        this_length);
309                 if (ret)
310                         return ret + length;
311
312                 cpu_offset += this_length;
313                 gpu_offset += this_length;
314                 length -= this_length;
315         }
316
317         return 0;
318 }
319
320 /* Per-page copy function for the shmem pread fastpath.
321  * Flushes invalid cachelines before reading the target if
322  * needs_clflush is set. */
323 static int
324 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
325                  char __user *user_data,
326                  bool page_do_bit17_swizzling, bool needs_clflush)
327 {
328         char *vaddr;
329         int ret;
330
331         if (unlikely(page_do_bit17_swizzling))
332                 return -EINVAL;
333
334         vaddr = kmap_atomic(page);
335         if (needs_clflush)
336                 drm_clflush_virt_range(vaddr + shmem_page_offset,
337                                        page_length);
338         ret = __copy_to_user_inatomic(user_data,
339                                       vaddr + shmem_page_offset,
340                                       page_length);
341         kunmap_atomic(vaddr);
342
343         return ret;
344 }
345
346 static void
347 shmem_clflush_swizzled_range(char *addr, unsigned long length,
348                              bool swizzled)
349 {
350         if (unlikely(swizzled)) {
351                 unsigned long start = (unsigned long) addr;
352                 unsigned long end = (unsigned long) addr + length;
353
354                 /* For swizzling simply ensure that we always flush both
355                  * channels. Lame, but simple and it works. Swizzled
356                  * pwrite/pread is far from a hotpath - current userspace
357                  * doesn't use it at all. */
358                 start = round_down(start, 128);
359                 end = round_up(end, 128);
360
361                 drm_clflush_virt_range((void *)start, end - start);
362         } else {
363                 drm_clflush_virt_range(addr, length);
364         }
365
366 }
367
368 /* Only difference to the fast-path function is that this can handle bit17
369  * and uses non-atomic copy and kmap functions. */
370 static int
371 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
372                  char __user *user_data,
373                  bool page_do_bit17_swizzling, bool needs_clflush)
374 {
375         char *vaddr;
376         int ret;
377
378         vaddr = kmap(page);
379         if (needs_clflush)
380                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
381                                              page_length,
382                                              page_do_bit17_swizzling);
383
384         if (page_do_bit17_swizzling)
385                 ret = __copy_to_user_swizzled(user_data,
386                                               vaddr, shmem_page_offset,
387                                               page_length);
388         else
389                 ret = __copy_to_user(user_data,
390                                      vaddr + shmem_page_offset,
391                                      page_length);
392         kunmap(page);
393
394         return ret;
395 }
396
397 static int
398 i915_gem_shmem_pread(struct drm_device *dev,
399                      struct drm_i915_gem_object *obj,
400                      struct drm_i915_gem_pread *args,
401                      struct drm_file *file)
402 {
403         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
404         char __user *user_data;
405         ssize_t remain;
406         loff_t offset;
407         int shmem_page_offset, page_length, ret = 0;
408         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
409         int hit_slowpath = 0;
410         int prefaulted = 0;
411         int needs_clflush = 0;
412         int release_page;
413
414         user_data = (char __user *) (uintptr_t) args->data_ptr;
415         remain = args->size;
416
417         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
418
419         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
420                 /* If we're not in the cpu read domain, set ourself into the gtt
421                  * read domain and manually flush cachelines (if required). This
422                  * optimizes for the case when the gpu will dirty the data
423                  * anyway again before the next pread happens. */
424                 if (obj->cache_level == I915_CACHE_NONE)
425                         needs_clflush = 1;
426                 ret = i915_gem_object_set_to_gtt_domain(obj, false);
427                 if (ret)
428                         return ret;
429         }
430
431         offset = args->offset;
432
433         while (remain > 0) {
434                 struct page *page;
435
436                 /* Operation in this page
437                  *
438                  * shmem_page_offset = offset within page in shmem file
439                  * page_length = bytes to copy for this page
440                  */
441                 shmem_page_offset = offset_in_page(offset);
442                 page_length = remain;
443                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
444                         page_length = PAGE_SIZE - shmem_page_offset;
445
446                 if (obj->pages) {
447                         page = obj->pages[offset >> PAGE_SHIFT];
448                         release_page = 0;
449                 } else {
450                         page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
451                         if (IS_ERR(page)) {
452                                 ret = PTR_ERR(page);
453                                 goto out;
454                         }
455                         release_page = 1;
456                 }
457
458                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
459                         (page_to_phys(page) & (1 << 17)) != 0;
460
461                 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
462                                        user_data, page_do_bit17_swizzling,
463                                        needs_clflush);
464                 if (ret == 0)
465                         goto next_page;
466
467                 hit_slowpath = 1;
468                 page_cache_get(page);
469                 mutex_unlock(&dev->struct_mutex);
470
471                 if (!prefaulted) {
472                         ret = fault_in_multipages_writeable(user_data, remain);
473                         /* Userspace is tricking us, but we've already clobbered
474                          * its pages with the prefault and promised to write the
475                          * data up to the first fault. Hence ignore any errors
476                          * and just continue. */
477                         (void)ret;
478                         prefaulted = 1;
479                 }
480
481                 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
482                                        user_data, page_do_bit17_swizzling,
483                                        needs_clflush);
484
485                 mutex_lock(&dev->struct_mutex);
486                 page_cache_release(page);
487 next_page:
488                 mark_page_accessed(page);
489                 if (release_page)
490                         page_cache_release(page);
491
492                 if (ret) {
493                         ret = -EFAULT;
494                         goto out;
495                 }
496
497                 remain -= page_length;
498                 user_data += page_length;
499                 offset += page_length;
500         }
501
502 out:
503         if (hit_slowpath) {
504                 /* Fixup: Kill any reinstated backing storage pages */
505                 if (obj->madv == __I915_MADV_PURGED)
506                         i915_gem_object_truncate(obj);
507         }
508
509         return ret;
510 }
511
512 /**
513  * Reads data from the object referenced by handle.
514  *
515  * On error, the contents of *data are undefined.
516  */
517 int
518 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
519                      struct drm_file *file)
520 {
521         struct drm_i915_gem_pread *args = data;
522         struct drm_i915_gem_object *obj;
523         int ret = 0;
524
525         if (args->size == 0)
526                 return 0;
527
528         if (!access_ok(VERIFY_WRITE,
529                        (char __user *)(uintptr_t)args->data_ptr,
530                        args->size))
531                 return -EFAULT;
532
533         ret = i915_mutex_lock_interruptible(dev);
534         if (ret)
535                 return ret;
536
537         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
538         if (&obj->base == NULL) {
539                 ret = -ENOENT;
540                 goto unlock;
541         }
542
543         /* Bounds check source.  */
544         if (args->offset > obj->base.size ||
545             args->size > obj->base.size - args->offset) {
546                 ret = -EINVAL;
547                 goto out;
548         }
549
550         /* prime objects have no backing filp to GEM pread/pwrite
551          * pages from.
552          */
553         if (!obj->base.filp) {
554                 ret = -EINVAL;
555                 goto out;
556         }
557
558         trace_i915_gem_object_pread(obj, args->offset, args->size);
559
560         ret = i915_gem_shmem_pread(dev, obj, args, file);
561
562 out:
563         drm_gem_object_unreference(&obj->base);
564 unlock:
565         mutex_unlock(&dev->struct_mutex);
566         return ret;
567 }
568
569 /* This is the fast write path which cannot handle
570  * page faults in the source data
571  */
572
573 static inline int
574 fast_user_write(struct io_mapping *mapping,
575                 loff_t page_base, int page_offset,
576                 char __user *user_data,
577                 int length)
578 {
579         void __iomem *vaddr_atomic;
580         void *vaddr;
581         unsigned long unwritten;
582
583         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
584         /* We can use the cpu mem copy function because this is X86. */
585         vaddr = (void __force*)vaddr_atomic + page_offset;
586         unwritten = __copy_from_user_inatomic_nocache(vaddr,
587                                                       user_data, length);
588         io_mapping_unmap_atomic(vaddr_atomic);
589         return unwritten;
590 }
591
592 /**
593  * This is the fast pwrite path, where we copy the data directly from the
594  * user into the GTT, uncached.
595  */
596 static int
597 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
598                          struct drm_i915_gem_object *obj,
599                          struct drm_i915_gem_pwrite *args,
600                          struct drm_file *file)
601 {
602         drm_i915_private_t *dev_priv = dev->dev_private;
603         ssize_t remain;
604         loff_t offset, page_base;
605         char __user *user_data;
606         int page_offset, page_length, ret;
607
608         ret = i915_gem_object_pin(obj, 0, true);
609         if (ret)
610                 goto out;
611
612         ret = i915_gem_object_set_to_gtt_domain(obj, true);
613         if (ret)
614                 goto out_unpin;
615
616         ret = i915_gem_object_put_fence(obj);
617         if (ret)
618                 goto out_unpin;
619
620         user_data = (char __user *) (uintptr_t) args->data_ptr;
621         remain = args->size;
622
623         offset = obj->gtt_offset + args->offset;
624
625         while (remain > 0) {
626                 /* Operation in this page
627                  *
628                  * page_base = page offset within aperture
629                  * page_offset = offset within page
630                  * page_length = bytes to copy for this page
631                  */
632                 page_base = offset & PAGE_MASK;
633                 page_offset = offset_in_page(offset);
634                 page_length = remain;
635                 if ((page_offset + remain) > PAGE_SIZE)
636                         page_length = PAGE_SIZE - page_offset;
637
638                 /* If we get a fault while copying data, then (presumably) our
639                  * source page isn't available.  Return the error and we'll
640                  * retry in the slow path.
641                  */
642                 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
643                                     page_offset, user_data, page_length)) {
644                         ret = -EFAULT;
645                         goto out_unpin;
646                 }
647
648                 remain -= page_length;
649                 user_data += page_length;
650                 offset += page_length;
651         }
652
653 out_unpin:
654         i915_gem_object_unpin(obj);
655 out:
656         return ret;
657 }
658
659 /* Per-page copy function for the shmem pwrite fastpath.
660  * Flushes invalid cachelines before writing to the target if
661  * needs_clflush_before is set and flushes out any written cachelines after
662  * writing if needs_clflush is set. */
663 static int
664 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
665                   char __user *user_data,
666                   bool page_do_bit17_swizzling,
667                   bool needs_clflush_before,
668                   bool needs_clflush_after)
669 {
670         char *vaddr;
671         int ret;
672
673         if (unlikely(page_do_bit17_swizzling))
674                 return -EINVAL;
675
676         vaddr = kmap_atomic(page);
677         if (needs_clflush_before)
678                 drm_clflush_virt_range(vaddr + shmem_page_offset,
679                                        page_length);
680         ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
681                                                 user_data,
682                                                 page_length);
683         if (needs_clflush_after)
684                 drm_clflush_virt_range(vaddr + shmem_page_offset,
685                                        page_length);
686         kunmap_atomic(vaddr);
687
688         return ret;
689 }
690
691 /* Only difference to the fast-path function is that this can handle bit17
692  * and uses non-atomic copy and kmap functions. */
693 static int
694 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
695                   char __user *user_data,
696                   bool page_do_bit17_swizzling,
697                   bool needs_clflush_before,
698                   bool needs_clflush_after)
699 {
700         char *vaddr;
701         int ret;
702
703         vaddr = kmap(page);
704         if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
705                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
706                                              page_length,
707                                              page_do_bit17_swizzling);
708         if (page_do_bit17_swizzling)
709                 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
710                                                 user_data,
711                                                 page_length);
712         else
713                 ret = __copy_from_user(vaddr + shmem_page_offset,
714                                        user_data,
715                                        page_length);
716         if (needs_clflush_after)
717                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
718                                              page_length,
719                                              page_do_bit17_swizzling);
720         kunmap(page);
721
722         return ret;
723 }
724
725 static int
726 i915_gem_shmem_pwrite(struct drm_device *dev,
727                       struct drm_i915_gem_object *obj,
728                       struct drm_i915_gem_pwrite *args,
729                       struct drm_file *file)
730 {
731         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
732         ssize_t remain;
733         loff_t offset;
734         char __user *user_data;
735         int shmem_page_offset, page_length, ret = 0;
736         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
737         int hit_slowpath = 0;
738         int needs_clflush_after = 0;
739         int needs_clflush_before = 0;
740         int release_page;
741
742         user_data = (char __user *) (uintptr_t) args->data_ptr;
743         remain = args->size;
744
745         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
746
747         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
748                 /* If we're not in the cpu write domain, set ourself into the gtt
749                  * write domain and manually flush cachelines (if required). This
750                  * optimizes for the case when the gpu will use the data
751                  * right away and we therefore have to clflush anyway. */
752                 if (obj->cache_level == I915_CACHE_NONE)
753                         needs_clflush_after = 1;
754                 ret = i915_gem_object_set_to_gtt_domain(obj, true);
755                 if (ret)
756                         return ret;
757         }
758         /* Same trick applies for invalidate partially written cachelines before
759          * writing.  */
760         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
761             && obj->cache_level == I915_CACHE_NONE)
762                 needs_clflush_before = 1;
763
764         offset = args->offset;
765         obj->dirty = 1;
766
767         while (remain > 0) {
768                 struct page *page;
769                 int partial_cacheline_write;
770
771                 /* Operation in this page
772                  *
773                  * shmem_page_offset = offset within page in shmem file
774                  * page_length = bytes to copy for this page
775                  */
776                 shmem_page_offset = offset_in_page(offset);
777
778                 page_length = remain;
779                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
780                         page_length = PAGE_SIZE - shmem_page_offset;
781
782                 /* If we don't overwrite a cacheline completely we need to be
783                  * careful to have up-to-date data by first clflushing. Don't
784                  * overcomplicate things and flush the entire patch. */
785                 partial_cacheline_write = needs_clflush_before &&
786                         ((shmem_page_offset | page_length)
787                                 & (boot_cpu_data.x86_clflush_size - 1));
788
789                 if (obj->pages) {
790                         page = obj->pages[offset >> PAGE_SHIFT];
791                         release_page = 0;
792                 } else {
793                         page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
794                         if (IS_ERR(page)) {
795                                 ret = PTR_ERR(page);
796                                 goto out;
797                         }
798                         release_page = 1;
799                 }
800
801                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
802                         (page_to_phys(page) & (1 << 17)) != 0;
803
804                 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
805                                         user_data, page_do_bit17_swizzling,
806                                         partial_cacheline_write,
807                                         needs_clflush_after);
808                 if (ret == 0)
809                         goto next_page;
810
811                 hit_slowpath = 1;
812                 page_cache_get(page);
813                 mutex_unlock(&dev->struct_mutex);
814
815                 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
816                                         user_data, page_do_bit17_swizzling,
817                                         partial_cacheline_write,
818                                         needs_clflush_after);
819
820                 mutex_lock(&dev->struct_mutex);
821                 page_cache_release(page);
822 next_page:
823                 set_page_dirty(page);
824                 mark_page_accessed(page);
825                 if (release_page)
826                         page_cache_release(page);
827
828                 if (ret) {
829                         ret = -EFAULT;
830                         goto out;
831                 }
832
833                 remain -= page_length;
834                 user_data += page_length;
835                 offset += page_length;
836         }
837
838 out:
839         if (hit_slowpath) {
840                 /* Fixup: Kill any reinstated backing storage pages */
841                 if (obj->madv == __I915_MADV_PURGED)
842                         i915_gem_object_truncate(obj);
843                 /* and flush dirty cachelines in case the object isn't in the cpu write
844                  * domain anymore. */
845                 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
846                         i915_gem_clflush_object(obj);
847                         intel_gtt_chipset_flush();
848                 }
849         }
850
851         if (needs_clflush_after)
852                 intel_gtt_chipset_flush();
853
854         return ret;
855 }
856
857 /**
858  * Writes data to the object referenced by handle.
859  *
860  * On error, the contents of the buffer that were to be modified are undefined.
861  */
862 int
863 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
864                       struct drm_file *file)
865 {
866         struct drm_i915_gem_pwrite *args = data;
867         struct drm_i915_gem_object *obj;
868         int ret;
869
870         if (args->size == 0)
871                 return 0;
872
873         if (!access_ok(VERIFY_READ,
874                        (char __user *)(uintptr_t)args->data_ptr,
875                        args->size))
876                 return -EFAULT;
877
878         ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr,
879                                            args->size);
880         if (ret)
881                 return -EFAULT;
882
883         ret = i915_mutex_lock_interruptible(dev);
884         if (ret)
885                 return ret;
886
887         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
888         if (&obj->base == NULL) {
889                 ret = -ENOENT;
890                 goto unlock;
891         }
892
893         /* Bounds check destination. */
894         if (args->offset > obj->base.size ||
895             args->size > obj->base.size - args->offset) {
896                 ret = -EINVAL;
897                 goto out;
898         }
899
900         /* prime objects have no backing filp to GEM pread/pwrite
901          * pages from.
902          */
903         if (!obj->base.filp) {
904                 ret = -EINVAL;
905                 goto out;
906         }
907
908         trace_i915_gem_object_pwrite(obj, args->offset, args->size);
909
910         ret = -EFAULT;
911         /* We can only do the GTT pwrite on untiled buffers, as otherwise
912          * it would end up going through the fenced access, and we'll get
913          * different detiling behavior between reading and writing.
914          * pread/pwrite currently are reading and writing from the CPU
915          * perspective, requiring manual detiling by the client.
916          */
917         if (obj->phys_obj) {
918                 ret = i915_gem_phys_pwrite(dev, obj, args, file);
919                 goto out;
920         }
921
922         if (obj->gtt_space &&
923             obj->cache_level == I915_CACHE_NONE &&
924             obj->tiling_mode == I915_TILING_NONE &&
925             obj->map_and_fenceable &&
926             obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
927                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
928                 /* Note that the gtt paths might fail with non-page-backed user
929                  * pointers (e.g. gtt mappings when moving data between
930                  * textures). Fallback to the shmem path in that case. */
931         }
932
933         if (ret == -EFAULT)
934                 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
935
936 out:
937         drm_gem_object_unreference(&obj->base);
938 unlock:
939         mutex_unlock(&dev->struct_mutex);
940         return ret;
941 }
942
943 /**
944  * Called when user space prepares to use an object with the CPU, either
945  * through the mmap ioctl's mapping or a GTT mapping.
946  */
947 int
948 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
949                           struct drm_file *file)
950 {
951         struct drm_i915_gem_set_domain *args = data;
952         struct drm_i915_gem_object *obj;
953         uint32_t read_domains = args->read_domains;
954         uint32_t write_domain = args->write_domain;
955         int ret;
956
957         /* Only handle setting domains to types used by the CPU. */
958         if (write_domain & I915_GEM_GPU_DOMAINS)
959                 return -EINVAL;
960
961         if (read_domains & I915_GEM_GPU_DOMAINS)
962                 return -EINVAL;
963
964         /* Having something in the write domain implies it's in the read
965          * domain, and only that read domain.  Enforce that in the request.
966          */
967         if (write_domain != 0 && read_domains != write_domain)
968                 return -EINVAL;
969
970         ret = i915_mutex_lock_interruptible(dev);
971         if (ret)
972                 return ret;
973
974         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
975         if (&obj->base == NULL) {
976                 ret = -ENOENT;
977                 goto unlock;
978         }
979
980         if (read_domains & I915_GEM_DOMAIN_GTT) {
981                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
982
983                 /* Silently promote "you're not bound, there was nothing to do"
984                  * to success, since the client was just asking us to
985                  * make sure everything was done.
986                  */
987                 if (ret == -EINVAL)
988                         ret = 0;
989         } else {
990                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
991         }
992
993         drm_gem_object_unreference(&obj->base);
994 unlock:
995         mutex_unlock(&dev->struct_mutex);
996         return ret;
997 }
998
999 /**
1000  * Called when user space has done writes to this buffer
1001  */
1002 int
1003 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1004                          struct drm_file *file)
1005 {
1006         struct drm_i915_gem_sw_finish *args = data;
1007         struct drm_i915_gem_object *obj;
1008         int ret = 0;
1009
1010         ret = i915_mutex_lock_interruptible(dev);
1011         if (ret)
1012                 return ret;
1013
1014         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1015         if (&obj->base == NULL) {
1016                 ret = -ENOENT;
1017                 goto unlock;
1018         }
1019
1020         /* Pinned buffers may be scanout, so flush the cache */
1021         if (obj->pin_count)
1022                 i915_gem_object_flush_cpu_write_domain(obj);
1023
1024         drm_gem_object_unreference(&obj->base);
1025 unlock:
1026         mutex_unlock(&dev->struct_mutex);
1027         return ret;
1028 }
1029
1030 /**
1031  * Maps the contents of an object, returning the address it is mapped
1032  * into.
1033  *
1034  * While the mapping holds a reference on the contents of the object, it doesn't
1035  * imply a ref on the object itself.
1036  */
1037 int
1038 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1039                     struct drm_file *file)
1040 {
1041         struct drm_i915_gem_mmap *args = data;
1042         struct drm_gem_object *obj;
1043         unsigned long addr;
1044
1045         obj = drm_gem_object_lookup(dev, file, args->handle);
1046         if (obj == NULL)
1047                 return -ENOENT;
1048
1049         /* prime objects have no backing filp to GEM mmap
1050          * pages from.
1051          */
1052         if (!obj->filp) {
1053                 drm_gem_object_unreference_unlocked(obj);
1054                 return -EINVAL;
1055         }
1056
1057         addr = vm_mmap(obj->filp, 0, args->size,
1058                        PROT_READ | PROT_WRITE, MAP_SHARED,
1059                        args->offset);
1060         drm_gem_object_unreference_unlocked(obj);
1061         if (IS_ERR((void *)addr))
1062                 return addr;
1063
1064         args->addr_ptr = (uint64_t) addr;
1065
1066         return 0;
1067 }
1068
1069 /**
1070  * i915_gem_fault - fault a page into the GTT
1071  * vma: VMA in question
1072  * vmf: fault info
1073  *
1074  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1075  * from userspace.  The fault handler takes care of binding the object to
1076  * the GTT (if needed), allocating and programming a fence register (again,
1077  * only if needed based on whether the old reg is still valid or the object
1078  * is tiled) and inserting a new PTE into the faulting process.
1079  *
1080  * Note that the faulting process may involve evicting existing objects
1081  * from the GTT and/or fence registers to make room.  So performance may
1082  * suffer if the GTT working set is large or there are few fence registers
1083  * left.
1084  */
1085 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1086 {
1087         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1088         struct drm_device *dev = obj->base.dev;
1089         drm_i915_private_t *dev_priv = dev->dev_private;
1090         pgoff_t page_offset;
1091         unsigned long pfn;
1092         int ret = 0;
1093         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1094
1095         /* We don't use vmf->pgoff since that has the fake offset */
1096         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1097                 PAGE_SHIFT;
1098
1099         ret = i915_mutex_lock_interruptible(dev);
1100         if (ret)
1101                 goto out;
1102
1103         trace_i915_gem_object_fault(obj, page_offset, true, write);
1104
1105         /* Now bind it into the GTT if needed */
1106         if (!obj->map_and_fenceable) {
1107                 ret = i915_gem_object_unbind(obj);
1108                 if (ret)
1109                         goto unlock;
1110         }
1111         if (!obj->gtt_space) {
1112                 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
1113                 if (ret)
1114                         goto unlock;
1115
1116                 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1117                 if (ret)
1118                         goto unlock;
1119         }
1120
1121         if (!obj->has_global_gtt_mapping)
1122                 i915_gem_gtt_bind_object(obj, obj->cache_level);
1123
1124         ret = i915_gem_object_get_fence(obj);
1125         if (ret)
1126                 goto unlock;
1127
1128         if (i915_gem_object_is_inactive(obj))
1129                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1130
1131         obj->fault_mappable = true;
1132
1133         pfn = ((dev_priv->mm.gtt_base_addr + obj->gtt_offset) >> PAGE_SHIFT) +
1134                 page_offset;
1135
1136         /* Finally, remap it using the new GTT offset */
1137         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1138 unlock:
1139         mutex_unlock(&dev->struct_mutex);
1140 out:
1141         switch (ret) {
1142         case -EIO:
1143                 /* If this -EIO is due to a gpu hang, give the reset code a
1144                  * chance to clean up the mess. Otherwise return the proper
1145                  * SIGBUS. */
1146                 if (!atomic_read(&dev_priv->mm.wedged))
1147                         return VM_FAULT_SIGBUS;
1148         case -EAGAIN:
1149                 /* Give the error handler a chance to run and move the
1150                  * objects off the GPU active list. Next time we service the
1151                  * fault, we should be able to transition the page into the
1152                  * GTT without touching the GPU (and so avoid further
1153                  * EIO/EGAIN). If the GPU is wedged, then there is no issue
1154                  * with coherency, just lost writes.
1155                  */
1156                 set_need_resched();
1157         case 0:
1158         case -ERESTARTSYS:
1159         case -EINTR:
1160                 return VM_FAULT_NOPAGE;
1161         case -ENOMEM:
1162                 return VM_FAULT_OOM;
1163         default:
1164                 return VM_FAULT_SIGBUS;
1165         }
1166 }
1167
1168 /**
1169  * i915_gem_release_mmap - remove physical page mappings
1170  * @obj: obj in question
1171  *
1172  * Preserve the reservation of the mmapping with the DRM core code, but
1173  * relinquish ownership of the pages back to the system.
1174  *
1175  * It is vital that we remove the page mapping if we have mapped a tiled
1176  * object through the GTT and then lose the fence register due to
1177  * resource pressure. Similarly if the object has been moved out of the
1178  * aperture, than pages mapped into userspace must be revoked. Removing the
1179  * mapping will then trigger a page fault on the next user access, allowing
1180  * fixup by i915_gem_fault().
1181  */
1182 void
1183 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1184 {
1185         if (!obj->fault_mappable)
1186                 return;
1187
1188         if (obj->base.dev->dev_mapping)
1189                 unmap_mapping_range(obj->base.dev->dev_mapping,
1190                                     (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1191                                     obj->base.size, 1);
1192
1193         obj->fault_mappable = false;
1194 }
1195
1196 static uint32_t
1197 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1198 {
1199         uint32_t gtt_size;
1200
1201         if (INTEL_INFO(dev)->gen >= 4 ||
1202             tiling_mode == I915_TILING_NONE)
1203                 return size;
1204
1205         /* Previous chips need a power-of-two fence region when tiling */
1206         if (INTEL_INFO(dev)->gen == 3)
1207                 gtt_size = 1024*1024;
1208         else
1209                 gtt_size = 512*1024;
1210
1211         while (gtt_size < size)
1212                 gtt_size <<= 1;
1213
1214         return gtt_size;
1215 }
1216
1217 /**
1218  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1219  * @obj: object to check
1220  *
1221  * Return the required GTT alignment for an object, taking into account
1222  * potential fence register mapping.
1223  */
1224 static uint32_t
1225 i915_gem_get_gtt_alignment(struct drm_device *dev,
1226                            uint32_t size,
1227                            int tiling_mode)
1228 {
1229         /*
1230          * Minimum alignment is 4k (GTT page size), but might be greater
1231          * if a fence register is needed for the object.
1232          */
1233         if (INTEL_INFO(dev)->gen >= 4 ||
1234             tiling_mode == I915_TILING_NONE)
1235                 return 4096;
1236
1237         /*
1238          * Previous chips need to be aligned to the size of the smallest
1239          * fence register that can contain the object.
1240          */
1241         return i915_gem_get_gtt_size(dev, size, tiling_mode);
1242 }
1243
1244 /**
1245  * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1246  *                                       unfenced object
1247  * @dev: the device
1248  * @size: size of the object
1249  * @tiling_mode: tiling mode of the object
1250  *
1251  * Return the required GTT alignment for an object, only taking into account
1252  * unfenced tiled surface requirements.
1253  */
1254 uint32_t
1255 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1256                                     uint32_t size,
1257                                     int tiling_mode)
1258 {
1259         /*
1260          * Minimum alignment is 4k (GTT page size) for sane hw.
1261          */
1262         if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1263             tiling_mode == I915_TILING_NONE)
1264                 return 4096;
1265
1266         /* Previous hardware however needs to be aligned to a power-of-two
1267          * tile height. The simplest method for determining this is to reuse
1268          * the power-of-tile object size.
1269          */
1270         return i915_gem_get_gtt_size(dev, size, tiling_mode);
1271 }
1272
1273 int
1274 i915_gem_mmap_gtt(struct drm_file *file,
1275                   struct drm_device *dev,
1276                   uint32_t handle,
1277                   uint64_t *offset)
1278 {
1279         struct drm_i915_private *dev_priv = dev->dev_private;
1280         struct drm_i915_gem_object *obj;
1281         int ret;
1282
1283         ret = i915_mutex_lock_interruptible(dev);
1284         if (ret)
1285                 return ret;
1286
1287         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1288         if (&obj->base == NULL) {
1289                 ret = -ENOENT;
1290                 goto unlock;
1291         }
1292
1293         if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1294                 ret = -E2BIG;
1295                 goto out;
1296         }
1297
1298         if (obj->madv != I915_MADV_WILLNEED) {
1299                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1300                 ret = -EINVAL;
1301                 goto out;
1302         }
1303
1304         if (!obj->base.map_list.map) {
1305                 ret = drm_gem_create_mmap_offset(&obj->base);
1306                 if (ret)
1307                         goto out;
1308         }
1309
1310         *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1311
1312 out:
1313         drm_gem_object_unreference(&obj->base);
1314 unlock:
1315         mutex_unlock(&dev->struct_mutex);
1316         return ret;
1317 }
1318
1319 /**
1320  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1321  * @dev: DRM device
1322  * @data: GTT mapping ioctl data
1323  * @file: GEM object info
1324  *
1325  * Simply returns the fake offset to userspace so it can mmap it.
1326  * The mmap call will end up in drm_gem_mmap(), which will set things
1327  * up so we can get faults in the handler above.
1328  *
1329  * The fault handler will take care of binding the object into the GTT
1330  * (since it may have been evicted to make room for something), allocating
1331  * a fence register, and mapping the appropriate aperture address into
1332  * userspace.
1333  */
1334 int
1335 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1336                         struct drm_file *file)
1337 {
1338         struct drm_i915_gem_mmap_gtt *args = data;
1339
1340         return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1341 }
1342
1343 int
1344 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
1345                               gfp_t gfpmask)
1346 {
1347         int page_count, i;
1348         struct address_space *mapping;
1349         struct inode *inode;
1350         struct page *page;
1351
1352         if (obj->pages || obj->sg_table)
1353                 return 0;
1354
1355         /* Get the list of pages out of our struct file.  They'll be pinned
1356          * at this point until we release them.
1357          */
1358         page_count = obj->base.size / PAGE_SIZE;
1359         BUG_ON(obj->pages != NULL);
1360         obj->pages = drm_malloc_ab(page_count, sizeof(struct page *));
1361         if (obj->pages == NULL)
1362                 return -ENOMEM;
1363
1364         inode = obj->base.filp->f_path.dentry->d_inode;
1365         mapping = inode->i_mapping;
1366         gfpmask |= mapping_gfp_mask(mapping);
1367
1368         for (i = 0; i < page_count; i++) {
1369                 page = shmem_read_mapping_page_gfp(mapping, i, gfpmask);
1370                 if (IS_ERR(page))
1371                         goto err_pages;
1372
1373                 obj->pages[i] = page;
1374         }
1375
1376         if (i915_gem_object_needs_bit17_swizzle(obj))
1377                 i915_gem_object_do_bit_17_swizzle(obj);
1378
1379         return 0;
1380
1381 err_pages:
1382         while (i--)
1383                 page_cache_release(obj->pages[i]);
1384
1385         drm_free_large(obj->pages);
1386         obj->pages = NULL;
1387         return PTR_ERR(page);
1388 }
1389
1390 static void
1391 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1392 {
1393         int page_count = obj->base.size / PAGE_SIZE;
1394         int i;
1395
1396         if (!obj->pages)
1397                 return;
1398
1399         BUG_ON(obj->madv == __I915_MADV_PURGED);
1400
1401         if (i915_gem_object_needs_bit17_swizzle(obj))
1402                 i915_gem_object_save_bit_17_swizzle(obj);
1403
1404         if (obj->madv == I915_MADV_DONTNEED)
1405                 obj->dirty = 0;
1406
1407         for (i = 0; i < page_count; i++) {
1408                 if (obj->dirty)
1409                         set_page_dirty(obj->pages[i]);
1410
1411                 if (obj->madv == I915_MADV_WILLNEED)
1412                         mark_page_accessed(obj->pages[i]);
1413
1414                 page_cache_release(obj->pages[i]);
1415         }
1416         obj->dirty = 0;
1417
1418         drm_free_large(obj->pages);
1419         obj->pages = NULL;
1420 }
1421
1422 void
1423 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1424                                struct intel_ring_buffer *ring,
1425                                u32 seqno)
1426 {
1427         struct drm_device *dev = obj->base.dev;
1428         struct drm_i915_private *dev_priv = dev->dev_private;
1429
1430         BUG_ON(ring == NULL);
1431         obj->ring = ring;
1432
1433         /* Add a reference if we're newly entering the active list. */
1434         if (!obj->active) {
1435                 drm_gem_object_reference(&obj->base);
1436                 obj->active = 1;
1437         }
1438
1439         /* Move from whatever list we were on to the tail of execution. */
1440         list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1441         list_move_tail(&obj->ring_list, &ring->active_list);
1442
1443         obj->last_rendering_seqno = seqno;
1444
1445         if (obj->fenced_gpu_access) {
1446                 obj->last_fenced_seqno = seqno;
1447
1448                 /* Bump MRU to take account of the delayed flush */
1449                 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1450                         struct drm_i915_fence_reg *reg;
1451
1452                         reg = &dev_priv->fence_regs[obj->fence_reg];
1453                         list_move_tail(&reg->lru_list,
1454                                        &dev_priv->mm.fence_list);
1455                 }
1456         }
1457 }
1458
1459 static void
1460 i915_gem_object_move_off_active(struct drm_i915_gem_object *obj)
1461 {
1462         list_del_init(&obj->ring_list);
1463         obj->last_rendering_seqno = 0;
1464         obj->last_fenced_seqno = 0;
1465 }
1466
1467 static void
1468 i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj)
1469 {
1470         struct drm_device *dev = obj->base.dev;
1471         drm_i915_private_t *dev_priv = dev->dev_private;
1472
1473         BUG_ON(!obj->active);
1474         list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list);
1475
1476         i915_gem_object_move_off_active(obj);
1477 }
1478
1479 static void
1480 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1481 {
1482         struct drm_device *dev = obj->base.dev;
1483         struct drm_i915_private *dev_priv = dev->dev_private;
1484
1485         list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1486
1487         BUG_ON(!list_empty(&obj->gpu_write_list));
1488         BUG_ON(!obj->active);
1489         obj->ring = NULL;
1490
1491         i915_gem_object_move_off_active(obj);
1492         obj->fenced_gpu_access = false;
1493
1494         obj->active = 0;
1495         obj->pending_gpu_write = false;
1496         drm_gem_object_unreference(&obj->base);
1497
1498         WARN_ON(i915_verify_lists(dev));
1499 }
1500
1501 /* Immediately discard the backing storage */
1502 static void
1503 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1504 {
1505         struct inode *inode;
1506
1507         /* Our goal here is to return as much of the memory as
1508          * is possible back to the system as we are called from OOM.
1509          * To do this we must instruct the shmfs to drop all of its
1510          * backing pages, *now*.
1511          */
1512         inode = obj->base.filp->f_path.dentry->d_inode;
1513         shmem_truncate_range(inode, 0, (loff_t)-1);
1514
1515         if (obj->base.map_list.map)
1516                 drm_gem_free_mmap_offset(&obj->base);
1517
1518         obj->madv = __I915_MADV_PURGED;
1519 }
1520
1521 static inline int
1522 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1523 {
1524         return obj->madv == I915_MADV_DONTNEED;
1525 }
1526
1527 static void
1528 i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
1529                                uint32_t flush_domains)
1530 {
1531         struct drm_i915_gem_object *obj, *next;
1532
1533         list_for_each_entry_safe(obj, next,
1534                                  &ring->gpu_write_list,
1535                                  gpu_write_list) {
1536                 if (obj->base.write_domain & flush_domains) {
1537                         uint32_t old_write_domain = obj->base.write_domain;
1538
1539                         obj->base.write_domain = 0;
1540                         list_del_init(&obj->gpu_write_list);
1541                         i915_gem_object_move_to_active(obj, ring,
1542                                                        i915_gem_next_request_seqno(ring));
1543
1544                         trace_i915_gem_object_change_domain(obj,
1545                                                             obj->base.read_domains,
1546                                                             old_write_domain);
1547                 }
1548         }
1549 }
1550
1551 static u32
1552 i915_gem_get_seqno(struct drm_device *dev)
1553 {
1554         drm_i915_private_t *dev_priv = dev->dev_private;
1555         u32 seqno = dev_priv->next_seqno;
1556
1557         /* reserve 0 for non-seqno */
1558         if (++dev_priv->next_seqno == 0)
1559                 dev_priv->next_seqno = 1;
1560
1561         return seqno;
1562 }
1563
1564 u32
1565 i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
1566 {
1567         if (ring->outstanding_lazy_request == 0)
1568                 ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev);
1569
1570         return ring->outstanding_lazy_request;
1571 }
1572
1573 int
1574 i915_add_request(struct intel_ring_buffer *ring,
1575                  struct drm_file *file,
1576                  struct drm_i915_gem_request *request)
1577 {
1578         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1579         uint32_t seqno;
1580         u32 request_ring_position;
1581         int was_empty;
1582         int ret;
1583
1584         /*
1585          * Emit any outstanding flushes - execbuf can fail to emit the flush
1586          * after having emitted the batchbuffer command. Hence we need to fix
1587          * things up similar to emitting the lazy request. The difference here
1588          * is that the flush _must_ happen before the next request, no matter
1589          * what.
1590          */
1591         if (ring->gpu_caches_dirty) {
1592                 ret = i915_gem_flush_ring(ring, 0, I915_GEM_GPU_DOMAINS);
1593                 if (ret)
1594                         return ret;
1595
1596                 ring->gpu_caches_dirty = false;
1597         }
1598
1599         BUG_ON(request == NULL);
1600         seqno = i915_gem_next_request_seqno(ring);
1601
1602         /* Record the position of the start of the request so that
1603          * should we detect the updated seqno part-way through the
1604          * GPU processing the request, we never over-estimate the
1605          * position of the head.
1606          */
1607         request_ring_position = intel_ring_get_tail(ring);
1608
1609         ret = ring->add_request(ring, &seqno);
1610         if (ret)
1611             return ret;
1612
1613         trace_i915_gem_request_add(ring, seqno);
1614
1615         request->seqno = seqno;
1616         request->ring = ring;
1617         request->tail = request_ring_position;
1618         request->emitted_jiffies = jiffies;
1619         was_empty = list_empty(&ring->request_list);
1620         list_add_tail(&request->list, &ring->request_list);
1621
1622         if (file) {
1623                 struct drm_i915_file_private *file_priv = file->driver_priv;
1624
1625                 spin_lock(&file_priv->mm.lock);
1626                 request->file_priv = file_priv;
1627                 list_add_tail(&request->client_list,
1628                               &file_priv->mm.request_list);
1629                 spin_unlock(&file_priv->mm.lock);
1630         }
1631
1632         ring->outstanding_lazy_request = 0;
1633
1634         if (!dev_priv->mm.suspended) {
1635                 if (i915_enable_hangcheck) {
1636                         mod_timer(&dev_priv->hangcheck_timer,
1637                                   jiffies +
1638                                   msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1639                 }
1640                 if (was_empty)
1641                         queue_delayed_work(dev_priv->wq,
1642                                            &dev_priv->mm.retire_work, HZ);
1643         }
1644
1645         WARN_ON(!list_empty(&ring->gpu_write_list));
1646
1647         return 0;
1648 }
1649
1650 static inline void
1651 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1652 {
1653         struct drm_i915_file_private *file_priv = request->file_priv;
1654
1655         if (!file_priv)
1656                 return;
1657
1658         spin_lock(&file_priv->mm.lock);
1659         if (request->file_priv) {
1660                 list_del(&request->client_list);
1661                 request->file_priv = NULL;
1662         }
1663         spin_unlock(&file_priv->mm.lock);
1664 }
1665
1666 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1667                                       struct intel_ring_buffer *ring)
1668 {
1669         while (!list_empty(&ring->request_list)) {
1670                 struct drm_i915_gem_request *request;
1671
1672                 request = list_first_entry(&ring->request_list,
1673                                            struct drm_i915_gem_request,
1674                                            list);
1675
1676                 list_del(&request->list);
1677                 i915_gem_request_remove_from_client(request);
1678                 kfree(request);
1679         }
1680
1681         while (!list_empty(&ring->active_list)) {
1682                 struct drm_i915_gem_object *obj;
1683
1684                 obj = list_first_entry(&ring->active_list,
1685                                        struct drm_i915_gem_object,
1686                                        ring_list);
1687
1688                 obj->base.write_domain = 0;
1689                 list_del_init(&obj->gpu_write_list);
1690                 i915_gem_object_move_to_inactive(obj);
1691         }
1692 }
1693
1694 static void i915_gem_reset_fences(struct drm_device *dev)
1695 {
1696         struct drm_i915_private *dev_priv = dev->dev_private;
1697         int i;
1698
1699         for (i = 0; i < dev_priv->num_fence_regs; i++) {
1700                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
1701
1702                 i915_gem_write_fence(dev, i, NULL);
1703
1704                 if (reg->obj)
1705                         i915_gem_object_fence_lost(reg->obj);
1706
1707                 reg->pin_count = 0;
1708                 reg->obj = NULL;
1709                 INIT_LIST_HEAD(&reg->lru_list);
1710         }
1711
1712         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
1713 }
1714
1715 void i915_gem_reset(struct drm_device *dev)
1716 {
1717         struct drm_i915_private *dev_priv = dev->dev_private;
1718         struct drm_i915_gem_object *obj;
1719         struct intel_ring_buffer *ring;
1720         int i;
1721
1722         for_each_ring(ring, dev_priv, i)
1723                 i915_gem_reset_ring_lists(dev_priv, ring);
1724
1725         /* Remove anything from the flushing lists. The GPU cache is likely
1726          * to be lost on reset along with the data, so simply move the
1727          * lost bo to the inactive list.
1728          */
1729         while (!list_empty(&dev_priv->mm.flushing_list)) {
1730                 obj = list_first_entry(&dev_priv->mm.flushing_list,
1731                                       struct drm_i915_gem_object,
1732                                       mm_list);
1733
1734                 obj->base.write_domain = 0;
1735                 list_del_init(&obj->gpu_write_list);
1736                 i915_gem_object_move_to_inactive(obj);
1737         }
1738
1739         /* Move everything out of the GPU domains to ensure we do any
1740          * necessary invalidation upon reuse.
1741          */
1742         list_for_each_entry(obj,
1743                             &dev_priv->mm.inactive_list,
1744                             mm_list)
1745         {
1746                 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1747         }
1748
1749         /* The fence registers are invalidated so clear them out */
1750         i915_gem_reset_fences(dev);
1751 }
1752
1753 /**
1754  * This function clears the request list as sequence numbers are passed.
1755  */
1756 void
1757 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
1758 {
1759         uint32_t seqno;
1760         int i;
1761
1762         if (list_empty(&ring->request_list))
1763                 return;
1764
1765         WARN_ON(i915_verify_lists(ring->dev));
1766
1767         seqno = ring->get_seqno(ring);
1768
1769         for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++)
1770                 if (seqno >= ring->sync_seqno[i])
1771                         ring->sync_seqno[i] = 0;
1772
1773         while (!list_empty(&ring->request_list)) {
1774                 struct drm_i915_gem_request *request;
1775
1776                 request = list_first_entry(&ring->request_list,
1777                                            struct drm_i915_gem_request,
1778                                            list);
1779
1780                 if (!i915_seqno_passed(seqno, request->seqno))
1781                         break;
1782
1783                 trace_i915_gem_request_retire(ring, request->seqno);
1784                 /* We know the GPU must have read the request to have
1785                  * sent us the seqno + interrupt, so use the position
1786                  * of tail of the request to update the last known position
1787                  * of the GPU head.
1788                  */
1789                 ring->last_retired_head = request->tail;
1790
1791                 list_del(&request->list);
1792                 i915_gem_request_remove_from_client(request);
1793                 kfree(request);
1794         }
1795
1796         /* Move any buffers on the active list that are no longer referenced
1797          * by the ringbuffer to the flushing/inactive lists as appropriate.
1798          */
1799         while (!list_empty(&ring->active_list)) {
1800                 struct drm_i915_gem_object *obj;
1801
1802                 obj = list_first_entry(&ring->active_list,
1803                                       struct drm_i915_gem_object,
1804                                       ring_list);
1805
1806                 if (!i915_seqno_passed(seqno, obj->last_rendering_seqno))
1807                         break;
1808
1809                 if (obj->base.write_domain != 0)
1810                         i915_gem_object_move_to_flushing(obj);
1811                 else
1812                         i915_gem_object_move_to_inactive(obj);
1813         }
1814
1815         if (unlikely(ring->trace_irq_seqno &&
1816                      i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
1817                 ring->irq_put(ring);
1818                 ring->trace_irq_seqno = 0;
1819         }
1820
1821         WARN_ON(i915_verify_lists(ring->dev));
1822 }
1823
1824 void
1825 i915_gem_retire_requests(struct drm_device *dev)
1826 {
1827         drm_i915_private_t *dev_priv = dev->dev_private;
1828         struct intel_ring_buffer *ring;
1829         int i;
1830
1831         for_each_ring(ring, dev_priv, i)
1832                 i915_gem_retire_requests_ring(ring);
1833 }
1834
1835 static void
1836 i915_gem_retire_work_handler(struct work_struct *work)
1837 {
1838         drm_i915_private_t *dev_priv;
1839         struct drm_device *dev;
1840         struct intel_ring_buffer *ring;
1841         bool idle;
1842         int i;
1843
1844         dev_priv = container_of(work, drm_i915_private_t,
1845                                 mm.retire_work.work);
1846         dev = dev_priv->dev;
1847
1848         /* Come back later if the device is busy... */
1849         if (!mutex_trylock(&dev->struct_mutex)) {
1850                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1851                 return;
1852         }
1853
1854         i915_gem_retire_requests(dev);
1855
1856         /* Send a periodic flush down the ring so we don't hold onto GEM
1857          * objects indefinitely.
1858          */
1859         idle = true;
1860         for_each_ring(ring, dev_priv, i) {
1861                 if (ring->gpu_caches_dirty) {
1862                         struct drm_i915_gem_request *request;
1863
1864                         request = kzalloc(sizeof(*request), GFP_KERNEL);
1865                         if (request == NULL ||
1866                             i915_add_request(ring, NULL, request))
1867                             kfree(request);
1868                 }
1869
1870                 idle &= list_empty(&ring->request_list);
1871         }
1872
1873         if (!dev_priv->mm.suspended && !idle)
1874                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1875
1876         mutex_unlock(&dev->struct_mutex);
1877 }
1878
1879 int
1880 i915_gem_check_wedge(struct drm_i915_private *dev_priv,
1881                      bool interruptible)
1882 {
1883         if (atomic_read(&dev_priv->mm.wedged)) {
1884                 struct completion *x = &dev_priv->error_completion;
1885                 bool recovery_complete;
1886                 unsigned long flags;
1887
1888                 /* Give the error handler a chance to run. */
1889                 spin_lock_irqsave(&x->wait.lock, flags);
1890                 recovery_complete = x->done > 0;
1891                 spin_unlock_irqrestore(&x->wait.lock, flags);
1892
1893                 /* Non-interruptible callers can't handle -EAGAIN, hence return
1894                  * -EIO unconditionally for these. */
1895                 if (!interruptible)
1896                         return -EIO;
1897
1898                 /* Recovery complete, but still wedged means reset failure. */
1899                 if (recovery_complete)
1900                         return -EIO;
1901
1902                 return -EAGAIN;
1903         }
1904
1905         return 0;
1906 }
1907
1908 /*
1909  * Compare seqno against outstanding lazy request. Emit a request if they are
1910  * equal.
1911  */
1912 static int
1913 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
1914 {
1915         int ret = 0;
1916
1917         BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1918
1919         if (seqno == ring->outstanding_lazy_request) {
1920                 struct drm_i915_gem_request *request;
1921
1922                 request = kzalloc(sizeof(*request), GFP_KERNEL);
1923                 if (request == NULL)
1924                         return -ENOMEM;
1925
1926                 ret = i915_add_request(ring, NULL, request);
1927                 if (ret) {
1928                         kfree(request);
1929                         return ret;
1930                 }
1931
1932                 BUG_ON(seqno != request->seqno);
1933         }
1934
1935         return ret;
1936 }
1937
1938 /**
1939  * __wait_seqno - wait until execution of seqno has finished
1940  * @ring: the ring expected to report seqno
1941  * @seqno: duh!
1942  * @interruptible: do an interruptible wait (normally yes)
1943  * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1944  *
1945  * Returns 0 if the seqno was found within the alloted time. Else returns the
1946  * errno with remaining time filled in timeout argument.
1947  */
1948 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
1949                         bool interruptible, struct timespec *timeout)
1950 {
1951         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1952         struct timespec before, now, wait_time={1,0};
1953         unsigned long timeout_jiffies;
1954         long end;
1955         bool wait_forever = true;
1956         int ret;
1957
1958         if (i915_seqno_passed(ring->get_seqno(ring), seqno))
1959                 return 0;
1960
1961         trace_i915_gem_request_wait_begin(ring, seqno);
1962
1963         if (timeout != NULL) {
1964                 wait_time = *timeout;
1965                 wait_forever = false;
1966         }
1967
1968         timeout_jiffies = timespec_to_jiffies(&wait_time);
1969
1970         if (WARN_ON(!ring->irq_get(ring)))
1971                 return -ENODEV;
1972
1973         /* Record current time in case interrupted by signal, or wedged * */
1974         getrawmonotonic(&before);
1975
1976 #define EXIT_COND \
1977         (i915_seqno_passed(ring->get_seqno(ring), seqno) || \
1978         atomic_read(&dev_priv->mm.wedged))
1979         do {
1980                 if (interruptible)
1981                         end = wait_event_interruptible_timeout(ring->irq_queue,
1982                                                                EXIT_COND,
1983                                                                timeout_jiffies);
1984                 else
1985                         end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1986                                                  timeout_jiffies);
1987
1988                 ret = i915_gem_check_wedge(dev_priv, interruptible);
1989                 if (ret)
1990                         end = ret;
1991         } while (end == 0 && wait_forever);
1992
1993         getrawmonotonic(&now);
1994
1995         ring->irq_put(ring);
1996         trace_i915_gem_request_wait_end(ring, seqno);
1997 #undef EXIT_COND
1998
1999         if (timeout) {
2000                 struct timespec sleep_time = timespec_sub(now, before);
2001                 *timeout = timespec_sub(*timeout, sleep_time);
2002         }
2003
2004         switch (end) {
2005         case -EIO:
2006         case -EAGAIN: /* Wedged */
2007         case -ERESTARTSYS: /* Signal */
2008                 return (int)end;
2009         case 0: /* Timeout */
2010                 if (timeout)
2011                         set_normalized_timespec(timeout, 0, 0);
2012                 return -ETIME;
2013         default: /* Completed */
2014                 WARN_ON(end < 0); /* We're not aware of other errors */
2015                 return 0;
2016         }
2017 }
2018
2019 /**
2020  * Waits for a sequence number to be signaled, and cleans up the
2021  * request and object lists appropriately for that event.
2022  */
2023 int
2024 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
2025 {
2026         drm_i915_private_t *dev_priv = ring->dev->dev_private;
2027         int ret = 0;
2028
2029         BUG_ON(seqno == 0);
2030
2031         ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
2032         if (ret)
2033                 return ret;
2034
2035         ret = i915_gem_check_olr(ring, seqno);
2036         if (ret)
2037                 return ret;
2038
2039         ret = __wait_seqno(ring, seqno, dev_priv->mm.interruptible, NULL);
2040
2041         return ret;
2042 }
2043
2044 /**
2045  * Ensures that all rendering to the object has completed and the object is
2046  * safe to unbind from the GTT or access from the CPU.
2047  */
2048 int
2049 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj)
2050 {
2051         int ret;
2052
2053         /* This function only exists to support waiting for existing rendering,
2054          * not for emitting required flushes.
2055          */
2056         BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0);
2057
2058         /* If there is rendering queued on the buffer being evicted, wait for
2059          * it.
2060          */
2061         if (obj->active) {
2062                 ret = i915_wait_seqno(obj->ring, obj->last_rendering_seqno);
2063                 if (ret)
2064                         return ret;
2065                 i915_gem_retire_requests_ring(obj->ring);
2066         }
2067
2068         return 0;
2069 }
2070
2071 /**
2072  * Ensures that an object will eventually get non-busy by flushing any required
2073  * write domains, emitting any outstanding lazy request and retiring and
2074  * completed requests.
2075  */
2076 static int
2077 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2078 {
2079         int ret;
2080
2081         if (obj->active) {
2082                 ret = i915_gem_object_flush_gpu_write_domain(obj);
2083                 if (ret)
2084                         return ret;
2085
2086                 ret = i915_gem_check_olr(obj->ring,
2087                                          obj->last_rendering_seqno);
2088                 if (ret)
2089                         return ret;
2090                 i915_gem_retire_requests_ring(obj->ring);
2091         }
2092
2093         return 0;
2094 }
2095
2096 /**
2097  * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2098  * @DRM_IOCTL_ARGS: standard ioctl arguments
2099  *
2100  * Returns 0 if successful, else an error is returned with the remaining time in
2101  * the timeout parameter.
2102  *  -ETIME: object is still busy after timeout
2103  *  -ERESTARTSYS: signal interrupted the wait
2104  *  -ENONENT: object doesn't exist
2105  * Also possible, but rare:
2106  *  -EAGAIN: GPU wedged
2107  *  -ENOMEM: damn
2108  *  -ENODEV: Internal IRQ fail
2109  *  -E?: The add request failed
2110  *
2111  * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2112  * non-zero timeout parameter the wait ioctl will wait for the given number of
2113  * nanoseconds on an object becoming unbusy. Since the wait itself does so
2114  * without holding struct_mutex the object may become re-busied before this
2115  * function completes. A similar but shorter * race condition exists in the busy
2116  * ioctl
2117  */
2118 int
2119 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2120 {
2121         struct drm_i915_gem_wait *args = data;
2122         struct drm_i915_gem_object *obj;
2123         struct intel_ring_buffer *ring = NULL;
2124         struct timespec timeout_stack, *timeout = NULL;
2125         u32 seqno = 0;
2126         int ret = 0;
2127
2128         if (args->timeout_ns >= 0) {
2129                 timeout_stack = ns_to_timespec(args->timeout_ns);
2130                 timeout = &timeout_stack;
2131         }
2132
2133         ret = i915_mutex_lock_interruptible(dev);
2134         if (ret)
2135                 return ret;
2136
2137         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2138         if (&obj->base == NULL) {
2139                 mutex_unlock(&dev->struct_mutex);
2140                 return -ENOENT;
2141         }
2142
2143         /* Need to make sure the object gets inactive eventually. */
2144         ret = i915_gem_object_flush_active(obj);
2145         if (ret)
2146                 goto out;
2147
2148         if (obj->active) {
2149                 seqno = obj->last_rendering_seqno;
2150                 ring = obj->ring;
2151         }
2152
2153         if (seqno == 0)
2154                  goto out;
2155
2156         /* Do this after OLR check to make sure we make forward progress polling
2157          * on this IOCTL with a 0 timeout (like busy ioctl)
2158          */
2159         if (!args->timeout_ns) {
2160                 ret = -ETIME;
2161                 goto out;
2162         }
2163
2164         drm_gem_object_unreference(&obj->base);
2165         mutex_unlock(&dev->struct_mutex);
2166
2167         ret = __wait_seqno(ring, seqno, true, timeout);
2168         if (timeout) {
2169                 WARN_ON(!timespec_valid(timeout));
2170                 args->timeout_ns = timespec_to_ns(timeout);
2171         }
2172         return ret;
2173
2174 out:
2175         drm_gem_object_unreference(&obj->base);
2176         mutex_unlock(&dev->struct_mutex);
2177         return ret;
2178 }
2179
2180 /**
2181  * i915_gem_object_sync - sync an object to a ring.
2182  *
2183  * @obj: object which may be in use on another ring.
2184  * @to: ring we wish to use the object on. May be NULL.
2185  *
2186  * This code is meant to abstract object synchronization with the GPU.
2187  * Calling with NULL implies synchronizing the object with the CPU
2188  * rather than a particular GPU ring.
2189  *
2190  * Returns 0 if successful, else propagates up the lower layer error.
2191  */
2192 int
2193 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2194                      struct intel_ring_buffer *to)
2195 {
2196         struct intel_ring_buffer *from = obj->ring;
2197         u32 seqno;
2198         int ret, idx;
2199
2200         if (from == NULL || to == from)
2201                 return 0;
2202
2203         if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2204                 return i915_gem_object_wait_rendering(obj);
2205
2206         idx = intel_ring_sync_index(from, to);
2207
2208         seqno = obj->last_rendering_seqno;
2209         if (seqno <= from->sync_seqno[idx])
2210                 return 0;
2211
2212         ret = i915_gem_check_olr(obj->ring, seqno);
2213         if (ret)
2214                 return ret;
2215
2216         ret = to->sync_to(to, from, seqno);
2217         if (!ret)
2218                 from->sync_seqno[idx] = seqno;
2219
2220         return ret;
2221 }
2222
2223 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2224 {
2225         u32 old_write_domain, old_read_domains;
2226
2227         /* Act a barrier for all accesses through the GTT */
2228         mb();
2229
2230         /* Force a pagefault for domain tracking on next user access */
2231         i915_gem_release_mmap(obj);
2232
2233         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2234                 return;
2235
2236         old_read_domains = obj->base.read_domains;
2237         old_write_domain = obj->base.write_domain;
2238
2239         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2240         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2241
2242         trace_i915_gem_object_change_domain(obj,
2243                                             old_read_domains,
2244                                             old_write_domain);
2245 }
2246
2247 /**
2248  * Unbinds an object from the GTT aperture.
2249  */
2250 int
2251 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2252 {
2253         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2254         int ret = 0;
2255
2256         if (obj->gtt_space == NULL)
2257                 return 0;
2258
2259         if (obj->pin_count)
2260                 return -EBUSY;
2261
2262         ret = i915_gem_object_finish_gpu(obj);
2263         if (ret)
2264                 return ret;
2265         /* Continue on if we fail due to EIO, the GPU is hung so we
2266          * should be safe and we need to cleanup or else we might
2267          * cause memory corruption through use-after-free.
2268          */
2269
2270         i915_gem_object_finish_gtt(obj);
2271
2272         /* Move the object to the CPU domain to ensure that
2273          * any possible CPU writes while it's not in the GTT
2274          * are flushed when we go to remap it.
2275          */
2276         if (ret == 0)
2277                 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2278         if (ret == -ERESTARTSYS)
2279                 return ret;
2280         if (ret) {
2281                 /* In the event of a disaster, abandon all caches and
2282                  * hope for the best.
2283                  */
2284                 i915_gem_clflush_object(obj);
2285                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2286         }
2287
2288         /* release the fence reg _after_ flushing */
2289         ret = i915_gem_object_put_fence(obj);
2290         if (ret)
2291                 return ret;
2292
2293         trace_i915_gem_object_unbind(obj);
2294
2295         if (obj->has_global_gtt_mapping)
2296                 i915_gem_gtt_unbind_object(obj);
2297         if (obj->has_aliasing_ppgtt_mapping) {
2298                 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2299                 obj->has_aliasing_ppgtt_mapping = 0;
2300         }
2301         i915_gem_gtt_finish_object(obj);
2302
2303         i915_gem_object_put_pages_gtt(obj);
2304
2305         list_del_init(&obj->gtt_list);
2306         list_del_init(&obj->mm_list);
2307         /* Avoid an unnecessary call to unbind on rebind. */
2308         obj->map_and_fenceable = true;
2309
2310         drm_mm_put_block(obj->gtt_space);
2311         obj->gtt_space = NULL;
2312         obj->gtt_offset = 0;
2313
2314         if (i915_gem_object_is_purgeable(obj))
2315                 i915_gem_object_truncate(obj);
2316
2317         return ret;
2318 }
2319
2320 int
2321 i915_gem_flush_ring(struct intel_ring_buffer *ring,
2322                     uint32_t invalidate_domains,
2323                     uint32_t flush_domains)
2324 {
2325         int ret;
2326
2327         if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0)
2328                 return 0;
2329
2330         trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains);
2331
2332         ret = ring->flush(ring, invalidate_domains, flush_domains);
2333         if (ret)
2334                 return ret;
2335
2336         if (flush_domains & I915_GEM_GPU_DOMAINS)
2337                 i915_gem_process_flushing_list(ring, flush_domains);
2338
2339         return 0;
2340 }
2341
2342 static int i915_ring_idle(struct intel_ring_buffer *ring)
2343 {
2344         int ret;
2345
2346         if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list))
2347                 return 0;
2348
2349         if (!list_empty(&ring->gpu_write_list)) {
2350                 ret = i915_gem_flush_ring(ring,
2351                                     I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2352                 if (ret)
2353                         return ret;
2354         }
2355
2356         return i915_wait_seqno(ring, i915_gem_next_request_seqno(ring));
2357 }
2358
2359 int i915_gpu_idle(struct drm_device *dev)
2360 {
2361         drm_i915_private_t *dev_priv = dev->dev_private;
2362         struct intel_ring_buffer *ring;
2363         int ret, i;
2364
2365         /* Flush everything onto the inactive list. */
2366         for_each_ring(ring, dev_priv, i) {
2367                 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2368                 if (ret)
2369                         return ret;
2370
2371                 ret = i915_ring_idle(ring);
2372                 if (ret)
2373                         return ret;
2374
2375                 /* Is the device fubar? */
2376                 if (WARN_ON(!list_empty(&ring->gpu_write_list)))
2377                         return -EBUSY;
2378         }
2379
2380         return 0;
2381 }
2382
2383 static void sandybridge_write_fence_reg(struct drm_device *dev, int reg,
2384                                         struct drm_i915_gem_object *obj)
2385 {
2386         drm_i915_private_t *dev_priv = dev->dev_private;
2387         uint64_t val;
2388
2389         if (obj) {
2390                 u32 size = obj->gtt_space->size;
2391
2392                 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2393                                  0xfffff000) << 32;
2394                 val |= obj->gtt_offset & 0xfffff000;
2395                 val |= (uint64_t)((obj->stride / 128) - 1) <<
2396                         SANDYBRIDGE_FENCE_PITCH_SHIFT;
2397
2398                 if (obj->tiling_mode == I915_TILING_Y)
2399                         val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2400                 val |= I965_FENCE_REG_VALID;
2401         } else
2402                 val = 0;
2403
2404         I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val);
2405         POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8);
2406 }
2407
2408 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2409                                  struct drm_i915_gem_object *obj)
2410 {
2411         drm_i915_private_t *dev_priv = dev->dev_private;
2412         uint64_t val;
2413
2414         if (obj) {
2415                 u32 size = obj->gtt_space->size;
2416
2417                 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2418                                  0xfffff000) << 32;
2419                 val |= obj->gtt_offset & 0xfffff000;
2420                 val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2421                 if (obj->tiling_mode == I915_TILING_Y)
2422                         val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2423                 val |= I965_FENCE_REG_VALID;
2424         } else
2425                 val = 0;
2426
2427         I915_WRITE64(FENCE_REG_965_0 + reg * 8, val);
2428         POSTING_READ(FENCE_REG_965_0 + reg * 8);
2429 }
2430
2431 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2432                                  struct drm_i915_gem_object *obj)
2433 {
2434         drm_i915_private_t *dev_priv = dev->dev_private;
2435         u32 val;
2436
2437         if (obj) {
2438                 u32 size = obj->gtt_space->size;
2439                 int pitch_val;
2440                 int tile_width;
2441
2442                 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2443                      (size & -size) != size ||
2444                      (obj->gtt_offset & (size - 1)),
2445                      "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2446                      obj->gtt_offset, obj->map_and_fenceable, size);
2447
2448                 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2449                         tile_width = 128;
2450                 else
2451                         tile_width = 512;
2452
2453                 /* Note: pitch better be a power of two tile widths */
2454                 pitch_val = obj->stride / tile_width;
2455                 pitch_val = ffs(pitch_val) - 1;
2456
2457                 val = obj->gtt_offset;
2458                 if (obj->tiling_mode == I915_TILING_Y)
2459                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2460                 val |= I915_FENCE_SIZE_BITS(size);
2461                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2462                 val |= I830_FENCE_REG_VALID;
2463         } else
2464                 val = 0;
2465
2466         if (reg < 8)
2467                 reg = FENCE_REG_830_0 + reg * 4;
2468         else
2469                 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2470
2471         I915_WRITE(reg, val);
2472         POSTING_READ(reg);
2473 }
2474
2475 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2476                                 struct drm_i915_gem_object *obj)
2477 {
2478         drm_i915_private_t *dev_priv = dev->dev_private;
2479         uint32_t val;
2480
2481         if (obj) {
2482                 u32 size = obj->gtt_space->size;
2483                 uint32_t pitch_val;
2484
2485                 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2486                      (size & -size) != size ||
2487                      (obj->gtt_offset & (size - 1)),
2488                      "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2489                      obj->gtt_offset, size);
2490
2491                 pitch_val = obj->stride / 128;
2492                 pitch_val = ffs(pitch_val) - 1;
2493
2494                 val = obj->gtt_offset;
2495                 if (obj->tiling_mode == I915_TILING_Y)
2496                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2497                 val |= I830_FENCE_SIZE_BITS(size);
2498                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2499                 val |= I830_FENCE_REG_VALID;
2500         } else
2501                 val = 0;
2502
2503         I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2504         POSTING_READ(FENCE_REG_830_0 + reg * 4);
2505 }
2506
2507 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2508                                  struct drm_i915_gem_object *obj)
2509 {
2510         switch (INTEL_INFO(dev)->gen) {
2511         case 7:
2512         case 6: sandybridge_write_fence_reg(dev, reg, obj); break;
2513         case 5:
2514         case 4: i965_write_fence_reg(dev, reg, obj); break;
2515         case 3: i915_write_fence_reg(dev, reg, obj); break;
2516         case 2: i830_write_fence_reg(dev, reg, obj); break;
2517         default: break;
2518         }
2519 }
2520
2521 static inline int fence_number(struct drm_i915_private *dev_priv,
2522                                struct drm_i915_fence_reg *fence)
2523 {
2524         return fence - dev_priv->fence_regs;
2525 }
2526
2527 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2528                                          struct drm_i915_fence_reg *fence,
2529                                          bool enable)
2530 {
2531         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2532         int reg = fence_number(dev_priv, fence);
2533
2534         i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2535
2536         if (enable) {
2537                 obj->fence_reg = reg;
2538                 fence->obj = obj;
2539                 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2540         } else {
2541                 obj->fence_reg = I915_FENCE_REG_NONE;
2542                 fence->obj = NULL;
2543                 list_del_init(&fence->lru_list);
2544         }
2545 }
2546
2547 static int
2548 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj)
2549 {
2550         int ret;
2551
2552         if (obj->fenced_gpu_access) {
2553                 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
2554                         ret = i915_gem_flush_ring(obj->ring,
2555                                                   0, obj->base.write_domain);
2556                         if (ret)
2557                                 return ret;
2558                 }
2559
2560                 obj->fenced_gpu_access = false;
2561         }
2562
2563         if (obj->last_fenced_seqno) {
2564                 ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2565                 if (ret)
2566                         return ret;
2567
2568                 obj->last_fenced_seqno = 0;
2569         }
2570
2571         /* Ensure that all CPU reads are completed before installing a fence
2572          * and all writes before removing the fence.
2573          */
2574         if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
2575                 mb();
2576
2577         return 0;
2578 }
2579
2580 int
2581 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2582 {
2583         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2584         int ret;
2585
2586         ret = i915_gem_object_flush_fence(obj);
2587         if (ret)
2588                 return ret;
2589
2590         if (obj->fence_reg == I915_FENCE_REG_NONE)
2591                 return 0;
2592
2593         i915_gem_object_update_fence(obj,
2594                                      &dev_priv->fence_regs[obj->fence_reg],
2595                                      false);
2596         i915_gem_object_fence_lost(obj);
2597
2598         return 0;
2599 }
2600
2601 static struct drm_i915_fence_reg *
2602 i915_find_fence_reg(struct drm_device *dev)
2603 {
2604         struct drm_i915_private *dev_priv = dev->dev_private;
2605         struct drm_i915_fence_reg *reg, *avail;
2606         int i;
2607
2608         /* First try to find a free reg */
2609         avail = NULL;
2610         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2611                 reg = &dev_priv->fence_regs[i];
2612                 if (!reg->obj)
2613                         return reg;
2614
2615                 if (!reg->pin_count)
2616                         avail = reg;
2617         }
2618
2619         if (avail == NULL)
2620                 return NULL;
2621
2622         /* None available, try to steal one or wait for a user to finish */
2623         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2624                 if (reg->pin_count)
2625                         continue;
2626
2627                 return reg;
2628         }
2629
2630         return NULL;
2631 }
2632
2633 /**
2634  * i915_gem_object_get_fence - set up fencing for an object
2635  * @obj: object to map through a fence reg
2636  *
2637  * When mapping objects through the GTT, userspace wants to be able to write
2638  * to them without having to worry about swizzling if the object is tiled.
2639  * This function walks the fence regs looking for a free one for @obj,
2640  * stealing one if it can't find any.
2641  *
2642  * It then sets up the reg based on the object's properties: address, pitch
2643  * and tiling format.
2644  *
2645  * For an untiled surface, this removes any existing fence.
2646  */
2647 int
2648 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2649 {
2650         struct drm_device *dev = obj->base.dev;
2651         struct drm_i915_private *dev_priv = dev->dev_private;
2652         bool enable = obj->tiling_mode != I915_TILING_NONE;
2653         struct drm_i915_fence_reg *reg;
2654         int ret;
2655
2656         /* Have we updated the tiling parameters upon the object and so
2657          * will need to serialise the write to the associated fence register?
2658          */
2659         if (obj->fence_dirty) {
2660                 ret = i915_gem_object_flush_fence(obj);
2661                 if (ret)
2662                         return ret;
2663         }
2664
2665         /* Just update our place in the LRU if our fence is getting reused. */
2666         if (obj->fence_reg != I915_FENCE_REG_NONE) {
2667                 reg = &dev_priv->fence_regs[obj->fence_reg];
2668                 if (!obj->fence_dirty) {
2669                         list_move_tail(&reg->lru_list,
2670                                        &dev_priv->mm.fence_list);
2671                         return 0;
2672                 }
2673         } else if (enable) {
2674                 reg = i915_find_fence_reg(dev);
2675                 if (reg == NULL)
2676                         return -EDEADLK;
2677
2678                 if (reg->obj) {
2679                         struct drm_i915_gem_object *old = reg->obj;
2680
2681                         ret = i915_gem_object_flush_fence(old);
2682                         if (ret)
2683                                 return ret;
2684
2685                         i915_gem_object_fence_lost(old);
2686                 }
2687         } else
2688                 return 0;
2689
2690         i915_gem_object_update_fence(obj, reg, enable);
2691         obj->fence_dirty = false;
2692
2693         return 0;
2694 }
2695
2696 /**
2697  * Finds free space in the GTT aperture and binds the object there.
2698  */
2699 static int
2700 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2701                             unsigned alignment,
2702                             bool map_and_fenceable)
2703 {
2704         struct drm_device *dev = obj->base.dev;
2705         drm_i915_private_t *dev_priv = dev->dev_private;
2706         struct drm_mm_node *free_space;
2707         gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2708         u32 size, fence_size, fence_alignment, unfenced_alignment;
2709         bool mappable, fenceable;
2710         int ret;
2711
2712         if (obj->madv != I915_MADV_WILLNEED) {
2713                 DRM_ERROR("Attempting to bind a purgeable object\n");
2714                 return -EINVAL;
2715         }
2716
2717         fence_size = i915_gem_get_gtt_size(dev,
2718                                            obj->base.size,
2719                                            obj->tiling_mode);
2720         fence_alignment = i915_gem_get_gtt_alignment(dev,
2721                                                      obj->base.size,
2722                                                      obj->tiling_mode);
2723         unfenced_alignment =
2724                 i915_gem_get_unfenced_gtt_alignment(dev,
2725                                                     obj->base.size,
2726                                                     obj->tiling_mode);
2727
2728         if (alignment == 0)
2729                 alignment = map_and_fenceable ? fence_alignment :
2730                                                 unfenced_alignment;
2731         if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2732                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2733                 return -EINVAL;
2734         }
2735
2736         size = map_and_fenceable ? fence_size : obj->base.size;
2737
2738         /* If the object is bigger than the entire aperture, reject it early
2739          * before evicting everything in a vain attempt to find space.
2740          */
2741         if (obj->base.size >
2742             (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2743                 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2744                 return -E2BIG;
2745         }
2746
2747  search_free:
2748         if (map_and_fenceable)
2749                 free_space =
2750                         drm_mm_search_free_in_range(&dev_priv->mm.gtt_space,
2751                                                     size, alignment,
2752                                                     0, dev_priv->mm.gtt_mappable_end,
2753                                                     0);
2754         else
2755                 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2756                                                 size, alignment, 0);
2757
2758         if (free_space != NULL) {
2759                 if (map_and_fenceable)
2760                         obj->gtt_space =
2761                                 drm_mm_get_block_range_generic(free_space,
2762                                                                size, alignment, 0,
2763                                                                0, dev_priv->mm.gtt_mappable_end,
2764                                                                0);
2765                 else
2766                         obj->gtt_space =
2767                                 drm_mm_get_block(free_space, size, alignment);
2768         }
2769         if (obj->gtt_space == NULL) {
2770                 /* If the gtt is empty and we're still having trouble
2771                  * fitting our object in, we're out of memory.
2772                  */
2773                 ret = i915_gem_evict_something(dev, size, alignment,
2774                                                map_and_fenceable);
2775                 if (ret)
2776                         return ret;
2777
2778                 goto search_free;
2779         }
2780
2781         ret = i915_gem_object_get_pages_gtt(obj, gfpmask);
2782         if (ret) {
2783                 drm_mm_put_block(obj->gtt_space);
2784                 obj->gtt_space = NULL;
2785
2786                 if (ret == -ENOMEM) {
2787                         /* first try to reclaim some memory by clearing the GTT */
2788                         ret = i915_gem_evict_everything(dev, false);
2789                         if (ret) {
2790                                 /* now try to shrink everyone else */
2791                                 if (gfpmask) {
2792                                         gfpmask = 0;
2793                                         goto search_free;
2794                                 }
2795
2796                                 return -ENOMEM;
2797                         }
2798
2799                         goto search_free;
2800                 }
2801
2802                 return ret;
2803         }
2804
2805         ret = i915_gem_gtt_prepare_object(obj);
2806         if (ret) {
2807                 i915_gem_object_put_pages_gtt(obj);
2808                 drm_mm_put_block(obj->gtt_space);
2809                 obj->gtt_space = NULL;
2810
2811                 if (i915_gem_evict_everything(dev, false))
2812                         return ret;
2813
2814                 goto search_free;
2815         }
2816
2817         if (!dev_priv->mm.aliasing_ppgtt)
2818                 i915_gem_gtt_bind_object(obj, obj->cache_level);
2819
2820         list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
2821         list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2822
2823         /* Assert that the object is not currently in any GPU domain. As it
2824          * wasn't in the GTT, there shouldn't be any way it could have been in
2825          * a GPU cache
2826          */
2827         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2828         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2829
2830         obj->gtt_offset = obj->gtt_space->start;
2831
2832         fenceable =
2833                 obj->gtt_space->size == fence_size &&
2834                 (obj->gtt_space->start & (fence_alignment - 1)) == 0;
2835
2836         mappable =
2837                 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2838
2839         obj->map_and_fenceable = mappable && fenceable;
2840
2841         trace_i915_gem_object_bind(obj, map_and_fenceable);
2842         return 0;
2843 }
2844
2845 void
2846 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
2847 {
2848         /* If we don't have a page list set up, then we're not pinned
2849          * to GPU, and we can ignore the cache flush because it'll happen
2850          * again at bind time.
2851          */
2852         if (obj->pages == NULL)
2853                 return;
2854
2855         /* If the GPU is snooping the contents of the CPU cache,
2856          * we do not need to manually clear the CPU cache lines.  However,
2857          * the caches are only snooped when the render cache is
2858          * flushed/invalidated.  As we always have to emit invalidations
2859          * and flushes when moving into and out of the RENDER domain, correct
2860          * snooping behaviour occurs naturally as the result of our domain
2861          * tracking.
2862          */
2863         if (obj->cache_level != I915_CACHE_NONE)
2864                 return;
2865
2866         trace_i915_gem_object_clflush(obj);
2867
2868         drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
2869 }
2870
2871 /** Flushes any GPU write domain for the object if it's dirty. */
2872 static int
2873 i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
2874 {
2875         if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
2876                 return 0;
2877
2878         /* Queue the GPU write cache flushing we need. */
2879         return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
2880 }
2881
2882 /** Flushes the GTT write domain for the object if it's dirty. */
2883 static void
2884 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
2885 {
2886         uint32_t old_write_domain;
2887
2888         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
2889                 return;
2890
2891         /* No actual flushing is required for the GTT write domain.  Writes
2892          * to it immediately go to main memory as far as we know, so there's
2893          * no chipset flush.  It also doesn't land in render cache.
2894          *
2895          * However, we do have to enforce the order so that all writes through
2896          * the GTT land before any writes to the device, such as updates to
2897          * the GATT itself.
2898          */
2899         wmb();
2900
2901         old_write_domain = obj->base.write_domain;
2902         obj->base.write_domain = 0;
2903
2904         trace_i915_gem_object_change_domain(obj,
2905                                             obj->base.read_domains,
2906                                             old_write_domain);
2907 }
2908
2909 /** Flushes the CPU write domain for the object if it's dirty. */
2910 static void
2911 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
2912 {
2913         uint32_t old_write_domain;
2914
2915         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
2916                 return;
2917
2918         i915_gem_clflush_object(obj);
2919         intel_gtt_chipset_flush();
2920         old_write_domain = obj->base.write_domain;
2921         obj->base.write_domain = 0;
2922
2923         trace_i915_gem_object_change_domain(obj,
2924                                             obj->base.read_domains,
2925                                             old_write_domain);
2926 }
2927
2928 /**
2929  * Moves a single object to the GTT read, and possibly write domain.
2930  *
2931  * This function returns when the move is complete, including waiting on
2932  * flushes to occur.
2933  */
2934 int
2935 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
2936 {
2937         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2938         uint32_t old_write_domain, old_read_domains;
2939         int ret;
2940
2941         /* Not valid to be called on unbound objects. */
2942         if (obj->gtt_space == NULL)
2943                 return -EINVAL;
2944
2945         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
2946                 return 0;
2947
2948         ret = i915_gem_object_flush_gpu_write_domain(obj);
2949         if (ret)
2950                 return ret;
2951
2952         if (obj->pending_gpu_write || write) {
2953                 ret = i915_gem_object_wait_rendering(obj);
2954                 if (ret)
2955                         return ret;
2956         }
2957
2958         i915_gem_object_flush_cpu_write_domain(obj);
2959
2960         old_write_domain = obj->base.write_domain;
2961         old_read_domains = obj->base.read_domains;
2962
2963         /* It should now be out of any other write domains, and we can update
2964          * the domain values for our changes.
2965          */
2966         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2967         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2968         if (write) {
2969                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
2970                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
2971                 obj->dirty = 1;
2972         }
2973
2974         trace_i915_gem_object_change_domain(obj,
2975                                             old_read_domains,
2976                                             old_write_domain);
2977
2978         /* And bump the LRU for this access */
2979         if (i915_gem_object_is_inactive(obj))
2980                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2981
2982         return 0;
2983 }
2984
2985 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2986                                     enum i915_cache_level cache_level)
2987 {
2988         struct drm_device *dev = obj->base.dev;
2989         drm_i915_private_t *dev_priv = dev->dev_private;
2990         int ret;
2991
2992         if (obj->cache_level == cache_level)
2993                 return 0;
2994
2995         if (obj->pin_count) {
2996                 DRM_DEBUG("can not change the cache level of pinned objects\n");
2997                 return -EBUSY;
2998         }
2999
3000         if (obj->gtt_space) {
3001                 ret = i915_gem_object_finish_gpu(obj);
3002                 if (ret)
3003                         return ret;
3004
3005                 i915_gem_object_finish_gtt(obj);
3006
3007                 /* Before SandyBridge, you could not use tiling or fence
3008                  * registers with snooped memory, so relinquish any fences
3009                  * currently pointing to our region in the aperture.
3010                  */
3011                 if (INTEL_INFO(obj->base.dev)->gen < 6) {
3012                         ret = i915_gem_object_put_fence(obj);
3013                         if (ret)
3014                                 return ret;
3015                 }
3016
3017                 if (obj->has_global_gtt_mapping)
3018                         i915_gem_gtt_bind_object(obj, cache_level);
3019                 if (obj->has_aliasing_ppgtt_mapping)
3020                         i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3021                                                obj, cache_level);
3022         }
3023
3024         if (cache_level == I915_CACHE_NONE) {
3025                 u32 old_read_domains, old_write_domain;
3026
3027                 /* If we're coming from LLC cached, then we haven't
3028                  * actually been tracking whether the data is in the
3029                  * CPU cache or not, since we only allow one bit set
3030                  * in obj->write_domain and have been skipping the clflushes.
3031                  * Just set it to the CPU cache for now.
3032                  */
3033                 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3034                 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3035
3036                 old_read_domains = obj->base.read_domains;
3037                 old_write_domain = obj->base.write_domain;
3038
3039                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3040                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3041
3042                 trace_i915_gem_object_change_domain(obj,
3043                                                     old_read_domains,
3044                                                     old_write_domain);
3045         }
3046
3047         obj->cache_level = cache_level;
3048         return 0;
3049 }
3050
3051 /*
3052  * Prepare buffer for display plane (scanout, cursors, etc).
3053  * Can be called from an uninterruptible phase (modesetting) and allows
3054  * any flushes to be pipelined (for pageflips).
3055  */
3056 int
3057 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3058                                      u32 alignment,
3059                                      struct intel_ring_buffer *pipelined)
3060 {
3061         u32 old_read_domains, old_write_domain;
3062         int ret;
3063
3064         ret = i915_gem_object_flush_gpu_write_domain(obj);
3065         if (ret)
3066                 return ret;
3067
3068         if (pipelined != obj->ring) {
3069                 ret = i915_gem_object_sync(obj, pipelined);
3070                 if (ret)
3071                         return ret;
3072         }
3073
3074         /* The display engine is not coherent with the LLC cache on gen6.  As
3075          * a result, we make sure that the pinning that is about to occur is
3076          * done with uncached PTEs. This is lowest common denominator for all
3077          * chipsets.
3078          *
3079          * However for gen6+, we could do better by using the GFDT bit instead
3080          * of uncaching, which would allow us to flush all the LLC-cached data
3081          * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3082          */
3083         ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3084         if (ret)
3085                 return ret;
3086
3087         /* As the user may map the buffer once pinned in the display plane
3088          * (e.g. libkms for the bootup splash), we have to ensure that we
3089          * always use map_and_fenceable for all scanout buffers.
3090          */
3091         ret = i915_gem_object_pin(obj, alignment, true);
3092         if (ret)
3093                 return ret;
3094
3095         i915_gem_object_flush_cpu_write_domain(obj);
3096
3097         old_write_domain = obj->base.write_domain;
3098         old_read_domains = obj->base.read_domains;
3099
3100         /* It should now be out of any other write domains, and we can update
3101          * the domain values for our changes.
3102          */
3103         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3104         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3105
3106         trace_i915_gem_object_change_domain(obj,
3107                                             old_read_domains,
3108                                             old_write_domain);
3109
3110         return 0;
3111 }
3112
3113 int
3114 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3115 {
3116         int ret;
3117
3118         if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3119                 return 0;
3120
3121         if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3122                 ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
3123                 if (ret)
3124                         return ret;
3125         }
3126
3127         ret = i915_gem_object_wait_rendering(obj);
3128         if (ret)
3129                 return ret;
3130
3131         /* Ensure that we invalidate the GPU's caches and TLBs. */
3132         obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3133         return 0;
3134 }
3135
3136 /**
3137  * Moves a single object to the CPU read, and possibly write domain.
3138  *
3139  * This function returns when the move is complete, including waiting on
3140  * flushes to occur.
3141  */
3142 int
3143 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3144 {
3145         uint32_t old_write_domain, old_read_domains;
3146         int ret;
3147
3148         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3149                 return 0;
3150
3151         ret = i915_gem_object_flush_gpu_write_domain(obj);
3152         if (ret)
3153                 return ret;
3154
3155         if (write || obj->pending_gpu_write) {
3156                 ret = i915_gem_object_wait_rendering(obj);
3157                 if (ret)
3158                         return ret;
3159         }
3160
3161         i915_gem_object_flush_gtt_write_domain(obj);
3162
3163         old_write_domain = obj->base.write_domain;
3164         old_read_domains = obj->base.read_domains;
3165
3166         /* Flush the CPU cache if it's still invalid. */
3167         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3168                 i915_gem_clflush_object(obj);
3169
3170                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3171         }
3172
3173         /* It should now be out of any other write domains, and we can update
3174          * the domain values for our changes.
3175          */
3176         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3177
3178         /* If we're writing through the CPU, then the GPU read domains will
3179          * need to be invalidated at next use.
3180          */
3181         if (write) {
3182                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3183                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3184         }
3185
3186         trace_i915_gem_object_change_domain(obj,
3187                                             old_read_domains,
3188                                             old_write_domain);
3189
3190         return 0;
3191 }
3192
3193 /* Throttle our rendering by waiting until the ring has completed our requests
3194  * emitted over 20 msec ago.
3195  *
3196  * Note that if we were to use the current jiffies each time around the loop,
3197  * we wouldn't escape the function with any frames outstanding if the time to
3198  * render a frame was over 20ms.
3199  *
3200  * This should get us reasonable parallelism between CPU and GPU but also
3201  * relatively low latency when blocking on a particular request to finish.
3202  */
3203 static int
3204 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3205 {
3206         struct drm_i915_private *dev_priv = dev->dev_private;
3207         struct drm_i915_file_private *file_priv = file->driver_priv;
3208         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3209         struct drm_i915_gem_request *request;
3210         struct intel_ring_buffer *ring = NULL;
3211         u32 seqno = 0;
3212         int ret;
3213
3214         if (atomic_read(&dev_priv->mm.wedged))
3215                 return -EIO;
3216
3217         spin_lock(&file_priv->mm.lock);
3218         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3219                 if (time_after_eq(request->emitted_jiffies, recent_enough))
3220                         break;
3221
3222                 ring = request->ring;
3223                 seqno = request->seqno;
3224         }
3225         spin_unlock(&file_priv->mm.lock);
3226
3227         if (seqno == 0)
3228                 return 0;
3229
3230         ret = __wait_seqno(ring, seqno, true, NULL);
3231         if (ret == 0)
3232                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3233
3234         return ret;
3235 }
3236
3237 int
3238 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3239                     uint32_t alignment,
3240                     bool map_and_fenceable)
3241 {
3242         int ret;
3243
3244         if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3245                 return -EBUSY;
3246
3247         if (obj->gtt_space != NULL) {
3248                 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3249                     (map_and_fenceable && !obj->map_and_fenceable)) {
3250                         WARN(obj->pin_count,
3251                              "bo is already pinned with incorrect alignment:"
3252                              " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3253                              " obj->map_and_fenceable=%d\n",
3254                              obj->gtt_offset, alignment,
3255                              map_and_fenceable,
3256                              obj->map_and_fenceable);
3257                         ret = i915_gem_object_unbind(obj);
3258                         if (ret)
3259                                 return ret;
3260                 }
3261         }
3262
3263         if (obj->gtt_space == NULL) {
3264                 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3265                                                   map_and_fenceable);
3266                 if (ret)
3267                         return ret;
3268         }
3269
3270         if (!obj->has_global_gtt_mapping && map_and_fenceable)
3271                 i915_gem_gtt_bind_object(obj, obj->cache_level);
3272
3273         obj->pin_count++;
3274         obj->pin_mappable |= map_and_fenceable;
3275
3276         return 0;
3277 }
3278
3279 void
3280 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3281 {
3282         BUG_ON(obj->pin_count == 0);
3283         BUG_ON(obj->gtt_space == NULL);
3284
3285         if (--obj->pin_count == 0)
3286                 obj->pin_mappable = false;
3287 }
3288
3289 int
3290 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3291                    struct drm_file *file)
3292 {
3293         struct drm_i915_gem_pin *args = data;
3294         struct drm_i915_gem_object *obj;
3295         int ret;
3296
3297         ret = i915_mutex_lock_interruptible(dev);
3298         if (ret)
3299                 return ret;
3300
3301         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3302         if (&obj->base == NULL) {
3303                 ret = -ENOENT;
3304                 goto unlock;
3305         }
3306
3307         if (obj->madv != I915_MADV_WILLNEED) {
3308                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3309                 ret = -EINVAL;
3310                 goto out;
3311         }
3312
3313         if (obj->pin_filp != NULL && obj->pin_filp != file) {
3314                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3315                           args->handle);
3316                 ret = -EINVAL;
3317                 goto out;
3318         }
3319
3320         obj->user_pin_count++;
3321         obj->pin_filp = file;
3322         if (obj->user_pin_count == 1) {
3323                 ret = i915_gem_object_pin(obj, args->alignment, true);
3324                 if (ret)
3325                         goto out;
3326         }
3327
3328         /* XXX - flush the CPU caches for pinned objects
3329          * as the X server doesn't manage domains yet
3330          */
3331         i915_gem_object_flush_cpu_write_domain(obj);
3332         args->offset = obj->gtt_offset;
3333 out:
3334         drm_gem_object_unreference(&obj->base);
3335 unlock:
3336         mutex_unlock(&dev->struct_mutex);
3337         return ret;
3338 }
3339
3340 int
3341 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3342                      struct drm_file *file)
3343 {
3344         struct drm_i915_gem_pin *args = data;
3345         struct drm_i915_gem_object *obj;
3346         int ret;
3347
3348         ret = i915_mutex_lock_interruptible(dev);
3349         if (ret)
3350                 return ret;
3351
3352         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3353         if (&obj->base == NULL) {
3354                 ret = -ENOENT;
3355                 goto unlock;
3356         }
3357
3358         if (obj->pin_filp != file) {
3359                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3360                           args->handle);
3361                 ret = -EINVAL;
3362                 goto out;
3363         }
3364         obj->user_pin_count--;
3365         if (obj->user_pin_count == 0) {
3366                 obj->pin_filp = NULL;
3367                 i915_gem_object_unpin(obj);
3368         }
3369
3370 out:
3371         drm_gem_object_unreference(&obj->base);
3372 unlock:
3373         mutex_unlock(&dev->struct_mutex);
3374         return ret;
3375 }
3376
3377 int
3378 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3379                     struct drm_file *file)
3380 {
3381         struct drm_i915_gem_busy *args = data;
3382         struct drm_i915_gem_object *obj;
3383         int ret;
3384
3385         ret = i915_mutex_lock_interruptible(dev);
3386         if (ret)
3387                 return ret;
3388
3389         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3390         if (&obj->base == NULL) {
3391                 ret = -ENOENT;
3392                 goto unlock;
3393         }
3394
3395         /* Count all active objects as busy, even if they are currently not used
3396          * by the gpu. Users of this interface expect objects to eventually
3397          * become non-busy without any further actions, therefore emit any
3398          * necessary flushes here.
3399          */
3400         ret = i915_gem_object_flush_active(obj);
3401
3402         args->busy = obj->active;
3403
3404         drm_gem_object_unreference(&obj->base);
3405 unlock:
3406         mutex_unlock(&dev->struct_mutex);
3407         return ret;
3408 }
3409
3410 int
3411 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3412                         struct drm_file *file_priv)
3413 {
3414         return i915_gem_ring_throttle(dev, file_priv);
3415 }
3416
3417 int
3418 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3419                        struct drm_file *file_priv)
3420 {
3421         struct drm_i915_gem_madvise *args = data;
3422         struct drm_i915_gem_object *obj;
3423         int ret;
3424
3425         switch (args->madv) {
3426         case I915_MADV_DONTNEED:
3427         case I915_MADV_WILLNEED:
3428             break;
3429         default:
3430             return -EINVAL;
3431         }
3432
3433         ret = i915_mutex_lock_interruptible(dev);
3434         if (ret)
3435                 return ret;
3436
3437         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3438         if (&obj->base == NULL) {
3439                 ret = -ENOENT;
3440                 goto unlock;
3441         }
3442
3443         if (obj->pin_count) {
3444                 ret = -EINVAL;
3445                 goto out;
3446         }
3447
3448         if (obj->madv != __I915_MADV_PURGED)
3449                 obj->madv = args->madv;
3450
3451         /* if the object is no longer bound, discard its backing storage */
3452         if (i915_gem_object_is_purgeable(obj) &&
3453             obj->gtt_space == NULL)
3454                 i915_gem_object_truncate(obj);
3455
3456         args->retained = obj->madv != __I915_MADV_PURGED;
3457
3458 out:
3459         drm_gem_object_unreference(&obj->base);
3460 unlock:
3461         mutex_unlock(&dev->struct_mutex);
3462         return ret;
3463 }
3464
3465 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3466                                                   size_t size)
3467 {
3468         struct drm_i915_private *dev_priv = dev->dev_private;
3469         struct drm_i915_gem_object *obj;
3470         struct address_space *mapping;
3471         u32 mask;
3472
3473         obj = kzalloc(sizeof(*obj), GFP_KERNEL);
3474         if (obj == NULL)
3475                 return NULL;
3476
3477         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3478                 kfree(obj);
3479                 return NULL;
3480         }
3481
3482         mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3483         if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
3484                 /* 965gm cannot relocate objects above 4GiB. */
3485                 mask &= ~__GFP_HIGHMEM;
3486                 mask |= __GFP_DMA32;
3487         }
3488
3489         mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3490         mapping_set_gfp_mask(mapping, mask);
3491
3492         i915_gem_info_add_obj(dev_priv, size);
3493
3494         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3495         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3496
3497         if (HAS_LLC(dev)) {
3498                 /* On some devices, we can have the GPU use the LLC (the CPU
3499                  * cache) for about a 10% performance improvement
3500                  * compared to uncached.  Graphics requests other than
3501                  * display scanout are coherent with the CPU in
3502                  * accessing this cache.  This means in this mode we
3503                  * don't need to clflush on the CPU side, and on the
3504                  * GPU side we only need to flush internal caches to
3505                  * get data visible to the CPU.
3506                  *
3507                  * However, we maintain the display planes as UC, and so
3508                  * need to rebind when first used as such.
3509                  */
3510                 obj->cache_level = I915_CACHE_LLC;
3511         } else
3512                 obj->cache_level = I915_CACHE_NONE;
3513
3514         obj->base.driver_private = NULL;
3515         obj->fence_reg = I915_FENCE_REG_NONE;
3516         INIT_LIST_HEAD(&obj->mm_list);
3517         INIT_LIST_HEAD(&obj->gtt_list);
3518         INIT_LIST_HEAD(&obj->ring_list);
3519         INIT_LIST_HEAD(&obj->exec_list);
3520         INIT_LIST_HEAD(&obj->gpu_write_list);
3521         obj->madv = I915_MADV_WILLNEED;
3522         /* Avoid an unnecessary call to unbind on the first bind. */
3523         obj->map_and_fenceable = true;
3524
3525         return obj;
3526 }
3527
3528 int i915_gem_init_object(struct drm_gem_object *obj)
3529 {
3530         BUG();
3531
3532         return 0;
3533 }
3534
3535 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3536 {
3537         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3538         struct drm_device *dev = obj->base.dev;
3539         drm_i915_private_t *dev_priv = dev->dev_private;
3540
3541         trace_i915_gem_object_destroy(obj);
3542
3543         if (gem_obj->import_attach)
3544                 drm_prime_gem_destroy(gem_obj, obj->sg_table);
3545
3546         if (obj->phys_obj)
3547                 i915_gem_detach_phys_object(dev, obj);
3548
3549         obj->pin_count = 0;
3550         if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
3551                 bool was_interruptible;
3552
3553                 was_interruptible = dev_priv->mm.interruptible;
3554                 dev_priv->mm.interruptible = false;
3555
3556                 WARN_ON(i915_gem_object_unbind(obj));
3557
3558                 dev_priv->mm.interruptible = was_interruptible;
3559         }
3560
3561         if (obj->base.map_list.map)
3562                 drm_gem_free_mmap_offset(&obj->base);
3563
3564         drm_gem_object_release(&obj->base);
3565         i915_gem_info_remove_obj(dev_priv, obj->base.size);
3566
3567         kfree(obj->bit_17);
3568         kfree(obj);
3569 }
3570
3571 int
3572 i915_gem_idle(struct drm_device *dev)
3573 {
3574         drm_i915_private_t *dev_priv = dev->dev_private;
3575         int ret;
3576
3577         mutex_lock(&dev->struct_mutex);
3578
3579         if (dev_priv->mm.suspended) {
3580                 mutex_unlock(&dev->struct_mutex);
3581                 return 0;
3582         }
3583
3584         ret = i915_gpu_idle(dev);
3585         if (ret) {
3586                 mutex_unlock(&dev->struct_mutex);
3587                 return ret;
3588         }
3589         i915_gem_retire_requests(dev);
3590
3591         /* Under UMS, be paranoid and evict. */
3592         if (!drm_core_check_feature(dev, DRIVER_MODESET))
3593                 i915_gem_evict_everything(dev, false);
3594
3595         i915_gem_reset_fences(dev);
3596
3597         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
3598          * We need to replace this with a semaphore, or something.
3599          * And not confound mm.suspended!
3600          */
3601         dev_priv->mm.suspended = 1;
3602         del_timer_sync(&dev_priv->hangcheck_timer);
3603
3604         i915_kernel_lost_context(dev);
3605         i915_gem_cleanup_ringbuffer(dev);
3606
3607         mutex_unlock(&dev->struct_mutex);
3608
3609         /* Cancel the retire work handler, which should be idle now. */
3610         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3611
3612         return 0;
3613 }
3614
3615 void i915_gem_l3_remap(struct drm_device *dev)
3616 {
3617         drm_i915_private_t *dev_priv = dev->dev_private;
3618         u32 misccpctl;
3619         int i;
3620
3621         if (!IS_IVYBRIDGE(dev))
3622                 return;
3623
3624         if (!dev_priv->mm.l3_remap_info)
3625                 return;
3626
3627         misccpctl = I915_READ(GEN7_MISCCPCTL);
3628         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
3629         POSTING_READ(GEN7_MISCCPCTL);
3630
3631         for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
3632                 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
3633                 if (remap && remap != dev_priv->mm.l3_remap_info[i/4])
3634                         DRM_DEBUG("0x%x was already programmed to %x\n",
3635                                   GEN7_L3LOG_BASE + i, remap);
3636                 if (remap && !dev_priv->mm.l3_remap_info[i/4])
3637                         DRM_DEBUG_DRIVER("Clearing remapped register\n");
3638                 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->mm.l3_remap_info[i/4]);
3639         }
3640
3641         /* Make sure all the writes land before disabling dop clock gating */
3642         POSTING_READ(GEN7_L3LOG_BASE);
3643
3644         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
3645 }
3646
3647 void i915_gem_init_swizzling(struct drm_device *dev)
3648 {
3649         drm_i915_private_t *dev_priv = dev->dev_private;
3650
3651         if (INTEL_INFO(dev)->gen < 5 ||
3652             dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
3653                 return;
3654
3655         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
3656                                  DISP_TILE_SURFACE_SWIZZLING);
3657
3658         if (IS_GEN5(dev))
3659                 return;
3660
3661         I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
3662         if (IS_GEN6(dev))
3663                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
3664         else
3665                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
3666 }
3667
3668 void i915_gem_init_ppgtt(struct drm_device *dev)
3669 {
3670         drm_i915_private_t *dev_priv = dev->dev_private;
3671         uint32_t pd_offset;
3672         struct intel_ring_buffer *ring;
3673         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
3674         uint32_t __iomem *pd_addr;
3675         uint32_t pd_entry;
3676         int i;
3677
3678         if (!dev_priv->mm.aliasing_ppgtt)
3679                 return;
3680
3681
3682         pd_addr = dev_priv->mm.gtt->gtt + ppgtt->pd_offset/sizeof(uint32_t);
3683         for (i = 0; i < ppgtt->num_pd_entries; i++) {
3684                 dma_addr_t pt_addr;
3685
3686                 if (dev_priv->mm.gtt->needs_dmar)
3687                         pt_addr = ppgtt->pt_dma_addr[i];
3688                 else
3689                         pt_addr = page_to_phys(ppgtt->pt_pages[i]);
3690
3691                 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
3692                 pd_entry |= GEN6_PDE_VALID;
3693
3694                 writel(pd_entry, pd_addr + i);
3695         }
3696         readl(pd_addr);
3697
3698         pd_offset = ppgtt->pd_offset;
3699         pd_offset /= 64; /* in cachelines, */
3700         pd_offset <<= 16;
3701
3702         if (INTEL_INFO(dev)->gen == 6) {
3703                 uint32_t ecochk, gab_ctl, ecobits;
3704
3705                 ecobits = I915_READ(GAC_ECO_BITS); 
3706                 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
3707
3708                 gab_ctl = I915_READ(GAB_CTL);
3709                 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
3710
3711                 ecochk = I915_READ(GAM_ECOCHK);
3712                 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
3713                                        ECOCHK_PPGTT_CACHE64B);
3714                 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
3715         } else if (INTEL_INFO(dev)->gen >= 7) {
3716                 I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
3717                 /* GFX_MODE is per-ring on gen7+ */
3718         }
3719
3720         for_each_ring(ring, dev_priv, i) {
3721                 if (INTEL_INFO(dev)->gen >= 7)
3722                         I915_WRITE(RING_MODE_GEN7(ring),
3723                                    _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
3724
3725                 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
3726                 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
3727         }
3728 }
3729
3730 static bool
3731 intel_enable_blt(struct drm_device *dev)
3732 {
3733         if (!HAS_BLT(dev))
3734                 return false;
3735
3736         /* The blitter was dysfunctional on early prototypes */
3737         if (IS_GEN6(dev) && dev->pdev->revision < 8) {
3738                 DRM_INFO("BLT not supported on this pre-production hardware;"
3739                          " graphics performance will be degraded.\n");
3740                 return false;
3741         }
3742
3743         return true;
3744 }
3745
3746 int
3747 i915_gem_init_hw(struct drm_device *dev)
3748 {
3749         drm_i915_private_t *dev_priv = dev->dev_private;
3750         int ret;
3751
3752         if (!intel_enable_gtt())
3753                 return -EIO;
3754
3755         i915_gem_l3_remap(dev);
3756
3757         i915_gem_init_swizzling(dev);
3758
3759         ret = intel_init_render_ring_buffer(dev);
3760         if (ret)
3761                 return ret;
3762
3763         if (HAS_BSD(dev)) {
3764                 ret = intel_init_bsd_ring_buffer(dev);
3765                 if (ret)
3766                         goto cleanup_render_ring;
3767         }
3768
3769         if (intel_enable_blt(dev)) {
3770                 ret = intel_init_blt_ring_buffer(dev);
3771                 if (ret)
3772                         goto cleanup_bsd_ring;
3773         }
3774
3775         dev_priv->next_seqno = 1;
3776
3777         /*
3778          * XXX: There was some w/a described somewhere suggesting loading
3779          * contexts before PPGTT.
3780          */
3781         i915_gem_context_init(dev);
3782         i915_gem_init_ppgtt(dev);
3783
3784         return 0;
3785
3786 cleanup_bsd_ring:
3787         intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
3788 cleanup_render_ring:
3789         intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
3790         return ret;
3791 }
3792
3793 static bool
3794 intel_enable_ppgtt(struct drm_device *dev)
3795 {
3796         if (i915_enable_ppgtt >= 0)
3797                 return i915_enable_ppgtt;
3798
3799 #ifdef CONFIG_INTEL_IOMMU
3800         /* Disable ppgtt on SNB if VT-d is on. */
3801         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
3802                 return false;
3803 #endif
3804
3805         return true;
3806 }
3807
3808 int i915_gem_init(struct drm_device *dev)
3809 {
3810         struct drm_i915_private *dev_priv = dev->dev_private;
3811         unsigned long gtt_size, mappable_size;
3812         int ret;
3813
3814         gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
3815         mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
3816
3817         mutex_lock(&dev->struct_mutex);
3818         if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
3819                 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
3820                  * aperture accordingly when using aliasing ppgtt. */
3821                 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
3822
3823                 i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size);
3824
3825                 ret = i915_gem_init_aliasing_ppgtt(dev);
3826                 if (ret) {
3827                         mutex_unlock(&dev->struct_mutex);
3828                         return ret;
3829                 }
3830         } else {
3831                 /* Let GEM Manage all of the aperture.
3832                  *
3833                  * However, leave one page at the end still bound to the scratch
3834                  * page.  There are a number of places where the hardware
3835                  * apparently prefetches past the end of the object, and we've
3836                  * seen multiple hangs with the GPU head pointer stuck in a
3837                  * batchbuffer bound at the last page of the aperture.  One page
3838                  * should be enough to keep any prefetching inside of the
3839                  * aperture.
3840                  */
3841                 i915_gem_init_global_gtt(dev, 0, mappable_size,
3842                                          gtt_size);
3843         }
3844
3845         ret = i915_gem_init_hw(dev);
3846         mutex_unlock(&dev->struct_mutex);
3847         if (ret) {
3848                 i915_gem_cleanup_aliasing_ppgtt(dev);
3849                 return ret;
3850         }
3851
3852         /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
3853         if (!drm_core_check_feature(dev, DRIVER_MODESET))
3854                 dev_priv->dri1.allow_batchbuffer = 1;
3855         return 0;
3856 }
3857
3858 void
3859 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
3860 {
3861         drm_i915_private_t *dev_priv = dev->dev_private;
3862         struct intel_ring_buffer *ring;
3863         int i;
3864
3865         for_each_ring(ring, dev_priv, i)
3866                 intel_cleanup_ring_buffer(ring);
3867 }
3868
3869 int
3870 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
3871                        struct drm_file *file_priv)
3872 {
3873         drm_i915_private_t *dev_priv = dev->dev_private;
3874         int ret;
3875
3876         if (drm_core_check_feature(dev, DRIVER_MODESET))
3877                 return 0;
3878
3879         if (atomic_read(&dev_priv->mm.wedged)) {
3880                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3881                 atomic_set(&dev_priv->mm.wedged, 0);
3882         }
3883
3884         mutex_lock(&dev->struct_mutex);
3885         dev_priv->mm.suspended = 0;
3886
3887         ret = i915_gem_init_hw(dev);
3888         if (ret != 0) {
3889                 mutex_unlock(&dev->struct_mutex);
3890                 return ret;
3891         }
3892
3893         BUG_ON(!list_empty(&dev_priv->mm.active_list));
3894         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
3895         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
3896         mutex_unlock(&dev->struct_mutex);
3897
3898         ret = drm_irq_install(dev);
3899         if (ret)
3900                 goto cleanup_ringbuffer;
3901
3902         return 0;
3903
3904 cleanup_ringbuffer:
3905         mutex_lock(&dev->struct_mutex);
3906         i915_gem_cleanup_ringbuffer(dev);
3907         dev_priv->mm.suspended = 1;
3908         mutex_unlock(&dev->struct_mutex);
3909
3910         return ret;
3911 }
3912
3913 int
3914 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
3915                        struct drm_file *file_priv)
3916 {
3917         if (drm_core_check_feature(dev, DRIVER_MODESET))
3918                 return 0;
3919
3920         drm_irq_uninstall(dev);
3921         return i915_gem_idle(dev);
3922 }
3923
3924 void
3925 i915_gem_lastclose(struct drm_device *dev)
3926 {
3927         int ret;
3928
3929         if (drm_core_check_feature(dev, DRIVER_MODESET))
3930                 return;
3931
3932         ret = i915_gem_idle(dev);
3933         if (ret)
3934                 DRM_ERROR("failed to idle hardware: %d\n", ret);
3935 }
3936
3937 static void
3938 init_ring_lists(struct intel_ring_buffer *ring)
3939 {
3940         INIT_LIST_HEAD(&ring->active_list);
3941         INIT_LIST_HEAD(&ring->request_list);
3942         INIT_LIST_HEAD(&ring->gpu_write_list);
3943 }
3944
3945 void
3946 i915_gem_load(struct drm_device *dev)
3947 {
3948         int i;
3949         drm_i915_private_t *dev_priv = dev->dev_private;
3950
3951         INIT_LIST_HEAD(&dev_priv->mm.active_list);
3952         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
3953         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
3954         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
3955         INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
3956         for (i = 0; i < I915_NUM_RINGS; i++)
3957                 init_ring_lists(&dev_priv->ring[i]);
3958         for (i = 0; i < I915_MAX_NUM_FENCES; i++)
3959                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
3960         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
3961                           i915_gem_retire_work_handler);
3962         init_completion(&dev_priv->error_completion);
3963
3964         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3965         if (IS_GEN3(dev)) {
3966                 I915_WRITE(MI_ARB_STATE,
3967                            _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
3968         }
3969
3970         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
3971
3972         /* Old X drivers will take 0-2 for front, back, depth buffers */
3973         if (!drm_core_check_feature(dev, DRIVER_MODESET))
3974                 dev_priv->fence_reg_start = 3;
3975
3976         if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3977                 dev_priv->num_fence_regs = 16;
3978         else
3979                 dev_priv->num_fence_regs = 8;
3980
3981         /* Initialize fence registers to zero */
3982         i915_gem_reset_fences(dev);
3983
3984         i915_gem_detect_bit_6_swizzle(dev);
3985         init_waitqueue_head(&dev_priv->pending_flip_queue);
3986
3987         dev_priv->mm.interruptible = true;
3988
3989         dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
3990         dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
3991         register_shrinker(&dev_priv->mm.inactive_shrinker);
3992 }
3993
3994 /*
3995  * Create a physically contiguous memory object for this object
3996  * e.g. for cursor + overlay regs
3997  */
3998 static int i915_gem_init_phys_object(struct drm_device *dev,
3999                                      int id, int size, int align)
4000 {
4001         drm_i915_private_t *dev_priv = dev->dev_private;
4002         struct drm_i915_gem_phys_object *phys_obj;
4003         int ret;
4004
4005         if (dev_priv->mm.phys_objs[id - 1] || !size)
4006                 return 0;
4007
4008         phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4009         if (!phys_obj)
4010                 return -ENOMEM;
4011
4012         phys_obj->id = id;
4013
4014         phys_obj->handle = drm_pci_alloc(dev, size, align);
4015         if (!phys_obj->handle) {
4016                 ret = -ENOMEM;
4017                 goto kfree_obj;
4018         }
4019 #ifdef CONFIG_X86
4020         set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4021 #endif
4022
4023         dev_priv->mm.phys_objs[id - 1] = phys_obj;
4024
4025         return 0;
4026 kfree_obj:
4027         kfree(phys_obj);
4028         return ret;
4029 }
4030
4031 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4032 {
4033         drm_i915_private_t *dev_priv = dev->dev_private;
4034         struct drm_i915_gem_phys_object *phys_obj;
4035
4036         if (!dev_priv->mm.phys_objs[id - 1])
4037                 return;
4038
4039         phys_obj = dev_priv->mm.phys_objs[id - 1];
4040         if (phys_obj->cur_obj) {
4041                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4042         }
4043
4044 #ifdef CONFIG_X86
4045         set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4046 #endif
4047         drm_pci_free(dev, phys_obj->handle);
4048         kfree(phys_obj);
4049         dev_priv->mm.phys_objs[id - 1] = NULL;
4050 }
4051
4052 void i915_gem_free_all_phys_object(struct drm_device *dev)
4053 {
4054         int i;
4055
4056         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4057                 i915_gem_free_phys_object(dev, i);
4058 }
4059
4060 void i915_gem_detach_phys_object(struct drm_device *dev,
4061                                  struct drm_i915_gem_object *obj)
4062 {
4063         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4064         char *vaddr;
4065         int i;
4066         int page_count;
4067
4068         if (!obj->phys_obj)
4069                 return;
4070         vaddr = obj->phys_obj->handle->vaddr;
4071
4072         page_count = obj->base.size / PAGE_SIZE;
4073         for (i = 0; i < page_count; i++) {
4074                 struct page *page = shmem_read_mapping_page(mapping, i);
4075                 if (!IS_ERR(page)) {
4076                         char *dst = kmap_atomic(page);
4077                         memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4078                         kunmap_atomic(dst);
4079
4080                         drm_clflush_pages(&page, 1);
4081
4082                         set_page_dirty(page);
4083                         mark_page_accessed(page);
4084                         page_cache_release(page);
4085                 }
4086         }
4087         intel_gtt_chipset_flush();
4088
4089         obj->phys_obj->cur_obj = NULL;
4090         obj->phys_obj = NULL;
4091 }
4092
4093 int
4094 i915_gem_attach_phys_object(struct drm_device *dev,
4095                             struct drm_i915_gem_object *obj,
4096                             int id,
4097                             int align)
4098 {
4099         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4100         drm_i915_private_t *dev_priv = dev->dev_private;
4101         int ret = 0;
4102         int page_count;
4103         int i;
4104
4105         if (id > I915_MAX_PHYS_OBJECT)
4106                 return -EINVAL;
4107
4108         if (obj->phys_obj) {
4109                 if (obj->phys_obj->id == id)
4110                         return 0;
4111                 i915_gem_detach_phys_object(dev, obj);
4112         }
4113
4114         /* create a new object */
4115         if (!dev_priv->mm.phys_objs[id - 1]) {
4116                 ret = i915_gem_init_phys_object(dev, id,
4117                                                 obj->base.size, align);
4118                 if (ret) {
4119                         DRM_ERROR("failed to init phys object %d size: %zu\n",
4120                                   id, obj->base.size);
4121                         return ret;
4122                 }
4123         }
4124
4125         /* bind to the object */
4126         obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4127         obj->phys_obj->cur_obj = obj;
4128
4129         page_count = obj->base.size / PAGE_SIZE;
4130
4131         for (i = 0; i < page_count; i++) {
4132                 struct page *page;
4133                 char *dst, *src;
4134
4135                 page = shmem_read_mapping_page(mapping, i);
4136                 if (IS_ERR(page))
4137                         return PTR_ERR(page);
4138
4139                 src = kmap_atomic(page);
4140                 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4141                 memcpy(dst, src, PAGE_SIZE);
4142                 kunmap_atomic(src);
4143
4144                 mark_page_accessed(page);
4145                 page_cache_release(page);
4146         }
4147
4148         return 0;
4149 }
4150
4151 static int
4152 i915_gem_phys_pwrite(struct drm_device *dev,
4153                      struct drm_i915_gem_object *obj,
4154                      struct drm_i915_gem_pwrite *args,
4155                      struct drm_file *file_priv)
4156 {
4157         void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4158         char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
4159
4160         if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4161                 unsigned long unwritten;
4162
4163                 /* The physical object once assigned is fixed for the lifetime
4164                  * of the obj, so we can safely drop the lock and continue
4165                  * to access vaddr.
4166                  */
4167                 mutex_unlock(&dev->struct_mutex);
4168                 unwritten = copy_from_user(vaddr, user_data, args->size);
4169                 mutex_lock(&dev->struct_mutex);
4170                 if (unwritten)
4171                         return -EFAULT;
4172         }
4173
4174         intel_gtt_chipset_flush();
4175         return 0;
4176 }
4177
4178 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4179 {
4180         struct drm_i915_file_private *file_priv = file->driver_priv;
4181
4182         /* Clean up our request list when the client is going away, so that
4183          * later retire_requests won't dereference our soon-to-be-gone
4184          * file_priv.
4185          */
4186         spin_lock(&file_priv->mm.lock);
4187         while (!list_empty(&file_priv->mm.request_list)) {
4188                 struct drm_i915_gem_request *request;
4189
4190                 request = list_first_entry(&file_priv->mm.request_list,
4191                                            struct drm_i915_gem_request,
4192                                            client_list);
4193                 list_del(&request->client_list);
4194                 request->file_priv = NULL;
4195         }
4196         spin_unlock(&file_priv->mm.lock);
4197 }
4198
4199 static int
4200 i915_gpu_is_active(struct drm_device *dev)
4201 {
4202         drm_i915_private_t *dev_priv = dev->dev_private;
4203         int lists_empty;
4204
4205         lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
4206                       list_empty(&dev_priv->mm.active_list);
4207
4208         return !lists_empty;
4209 }
4210
4211 static int
4212 i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4213 {
4214         struct drm_i915_private *dev_priv =
4215                 container_of(shrinker,
4216                              struct drm_i915_private,
4217                              mm.inactive_shrinker);
4218         struct drm_device *dev = dev_priv->dev;
4219         struct drm_i915_gem_object *obj, *next;
4220         int nr_to_scan = sc->nr_to_scan;
4221         int cnt;
4222
4223         if (!mutex_trylock(&dev->struct_mutex))
4224                 return 0;
4225
4226         /* "fast-path" to count number of available objects */
4227         if (nr_to_scan == 0) {
4228                 cnt = 0;
4229                 list_for_each_entry(obj,
4230                                     &dev_priv->mm.inactive_list,
4231                                     mm_list)
4232                         cnt++;
4233                 mutex_unlock(&dev->struct_mutex);
4234                 return cnt / 100 * sysctl_vfs_cache_pressure;
4235         }
4236
4237 rescan:
4238         /* first scan for clean buffers */
4239         i915_gem_retire_requests(dev);
4240
4241         list_for_each_entry_safe(obj, next,
4242                                  &dev_priv->mm.inactive_list,
4243                                  mm_list) {
4244                 if (i915_gem_object_is_purgeable(obj)) {
4245                         if (i915_gem_object_unbind(obj) == 0 &&
4246                             --nr_to_scan == 0)
4247                                 break;
4248                 }
4249         }
4250
4251         /* second pass, evict/count anything still on the inactive list */
4252         cnt = 0;
4253         list_for_each_entry_safe(obj, next,
4254                                  &dev_priv->mm.inactive_list,
4255                                  mm_list) {
4256                 if (nr_to_scan &&
4257                     i915_gem_object_unbind(obj) == 0)
4258                         nr_to_scan--;
4259                 else
4260                         cnt++;
4261         }
4262
4263         if (nr_to_scan && i915_gpu_is_active(dev)) {
4264                 /*
4265                  * We are desperate for pages, so as a last resort, wait
4266                  * for the GPU to finish and discard whatever we can.
4267                  * This has a dramatic impact to reduce the number of
4268                  * OOM-killer events whilst running the GPU aggressively.
4269                  */
4270                 if (i915_gpu_idle(dev) == 0)
4271                         goto rescan;
4272         }
4273         mutex_unlock(&dev->struct_mutex);
4274         return cnt / 100 * sysctl_vfs_cache_pressure;
4275 }