24fe8c10b4b22c6bac1cfa17d79d55f02dd59179
[linux-3.10.git] / drivers / gpu / drm / i915 / i915_gem.c
1 /*
2  * Copyright © 2008 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Authors:
24  *    Eric Anholt <eric@anholt.net>
25  *
26  */
27
28 #include "drmP.h"
29 #include "drm.h"
30 #include "i915_drm.h"
31 #include "i915_drv.h"
32 #include <linux/swap.h>
33
34 #define I915_GEM_GPU_DOMAINS    (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
35
36 static void
37 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj,
38                                   uint32_t read_domains,
39                                   uint32_t write_domain);
40 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
41 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
42 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
43 static int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
44                                              int write);
45 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
46                                              int write);
47 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
48                                                      uint64_t offset,
49                                                      uint64_t size);
50 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
51 static int i915_gem_object_get_page_list(struct drm_gem_object *obj);
52 static void i915_gem_object_free_page_list(struct drm_gem_object *obj);
53 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
54
55 static void
56 i915_gem_cleanup_ringbuffer(struct drm_device *dev);
57
58 int
59 i915_gem_init_ioctl(struct drm_device *dev, void *data,
60                     struct drm_file *file_priv)
61 {
62         drm_i915_private_t *dev_priv = dev->dev_private;
63         struct drm_i915_gem_init *args = data;
64
65         mutex_lock(&dev->struct_mutex);
66
67         if (args->gtt_start >= args->gtt_end ||
68             (args->gtt_start & (PAGE_SIZE - 1)) != 0 ||
69             (args->gtt_end & (PAGE_SIZE - 1)) != 0) {
70                 mutex_unlock(&dev->struct_mutex);
71                 return -EINVAL;
72         }
73
74         drm_mm_init(&dev_priv->mm.gtt_space, args->gtt_start,
75             args->gtt_end - args->gtt_start);
76
77         dev->gtt_total = (uint32_t) (args->gtt_end - args->gtt_start);
78
79         mutex_unlock(&dev->struct_mutex);
80
81         return 0;
82 }
83
84 int
85 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
86                             struct drm_file *file_priv)
87 {
88         struct drm_i915_gem_get_aperture *args = data;
89
90         if (!(dev->driver->driver_features & DRIVER_GEM))
91                 return -ENODEV;
92
93         args->aper_size = dev->gtt_total;
94         args->aper_available_size = (args->aper_size -
95                                      atomic_read(&dev->pin_memory));
96
97         return 0;
98 }
99
100
101 /**
102  * Creates a new mm object and returns a handle to it.
103  */
104 int
105 i915_gem_create_ioctl(struct drm_device *dev, void *data,
106                       struct drm_file *file_priv)
107 {
108         struct drm_i915_gem_create *args = data;
109         struct drm_gem_object *obj;
110         int handle, ret;
111
112         args->size = roundup(args->size, PAGE_SIZE);
113
114         /* Allocate the new object */
115         obj = drm_gem_object_alloc(dev, args->size);
116         if (obj == NULL)
117                 return -ENOMEM;
118
119         ret = drm_gem_handle_create(file_priv, obj, &handle);
120         mutex_lock(&dev->struct_mutex);
121         drm_gem_object_handle_unreference(obj);
122         mutex_unlock(&dev->struct_mutex);
123
124         if (ret)
125                 return ret;
126
127         args->handle = handle;
128
129         return 0;
130 }
131
132 /**
133  * Reads data from the object referenced by handle.
134  *
135  * On error, the contents of *data are undefined.
136  */
137 int
138 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
139                      struct drm_file *file_priv)
140 {
141         struct drm_i915_gem_pread *args = data;
142         struct drm_gem_object *obj;
143         struct drm_i915_gem_object *obj_priv;
144         ssize_t read;
145         loff_t offset;
146         int ret;
147
148         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
149         if (obj == NULL)
150                 return -EBADF;
151         obj_priv = obj->driver_private;
152
153         /* Bounds check source.
154          *
155          * XXX: This could use review for overflow issues...
156          */
157         if (args->offset > obj->size || args->size > obj->size ||
158             args->offset + args->size > obj->size) {
159                 drm_gem_object_unreference(obj);
160                 return -EINVAL;
161         }
162
163         mutex_lock(&dev->struct_mutex);
164
165         ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
166                                                         args->size);
167         if (ret != 0) {
168                 drm_gem_object_unreference(obj);
169                 mutex_unlock(&dev->struct_mutex);
170                 return ret;
171         }
172
173         offset = args->offset;
174
175         read = vfs_read(obj->filp, (char __user *)(uintptr_t)args->data_ptr,
176                         args->size, &offset);
177         if (read != args->size) {
178                 drm_gem_object_unreference(obj);
179                 mutex_unlock(&dev->struct_mutex);
180                 if (read < 0)
181                         return read;
182                 else
183                         return -EINVAL;
184         }
185
186         drm_gem_object_unreference(obj);
187         mutex_unlock(&dev->struct_mutex);
188
189         return 0;
190 }
191
192 /* This is the fast write path which cannot handle
193  * page faults in the source data
194  */
195
196 static inline int
197 fast_user_write(struct io_mapping *mapping,
198                 loff_t page_base, int page_offset,
199                 char __user *user_data,
200                 int length)
201 {
202         char *vaddr_atomic;
203         unsigned long unwritten;
204
205         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
206         unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
207                                                       user_data, length);
208         io_mapping_unmap_atomic(vaddr_atomic);
209         if (unwritten)
210                 return -EFAULT;
211         return 0;
212 }
213
214 /* Here's the write path which can sleep for
215  * page faults
216  */
217
218 static inline int
219 slow_user_write(struct io_mapping *mapping,
220                 loff_t page_base, int page_offset,
221                 char __user *user_data,
222                 int length)
223 {
224         char __iomem *vaddr;
225         unsigned long unwritten;
226
227         vaddr = io_mapping_map_wc(mapping, page_base);
228         if (vaddr == NULL)
229                 return -EFAULT;
230         unwritten = __copy_from_user(vaddr + page_offset,
231                                      user_data, length);
232         io_mapping_unmap(vaddr);
233         if (unwritten)
234                 return -EFAULT;
235         return 0;
236 }
237
238 static int
239 i915_gem_gtt_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
240                     struct drm_i915_gem_pwrite *args,
241                     struct drm_file *file_priv)
242 {
243         struct drm_i915_gem_object *obj_priv = obj->driver_private;
244         drm_i915_private_t *dev_priv = dev->dev_private;
245         ssize_t remain;
246         loff_t offset, page_base;
247         char __user *user_data;
248         int page_offset, page_length;
249         int ret;
250
251         user_data = (char __user *) (uintptr_t) args->data_ptr;
252         remain = args->size;
253         if (!access_ok(VERIFY_READ, user_data, remain))
254                 return -EFAULT;
255
256
257         mutex_lock(&dev->struct_mutex);
258         ret = i915_gem_object_pin(obj, 0);
259         if (ret) {
260                 mutex_unlock(&dev->struct_mutex);
261                 return ret;
262         }
263         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
264         if (ret)
265                 goto fail;
266
267         obj_priv = obj->driver_private;
268         offset = obj_priv->gtt_offset + args->offset;
269         obj_priv->dirty = 1;
270
271         while (remain > 0) {
272                 /* Operation in this page
273                  *
274                  * page_base = page offset within aperture
275                  * page_offset = offset within page
276                  * page_length = bytes to copy for this page
277                  */
278                 page_base = (offset & ~(PAGE_SIZE-1));
279                 page_offset = offset & (PAGE_SIZE-1);
280                 page_length = remain;
281                 if ((page_offset + remain) > PAGE_SIZE)
282                         page_length = PAGE_SIZE - page_offset;
283
284                 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
285                                        page_offset, user_data, page_length);
286
287                 /* If we get a fault while copying data, then (presumably) our
288                  * source page isn't available. In this case, use the
289                  * non-atomic function
290                  */
291                 if (ret) {
292                         ret = slow_user_write (dev_priv->mm.gtt_mapping,
293                                                page_base, page_offset,
294                                                user_data, page_length);
295                         if (ret)
296                                 goto fail;
297                 }
298
299                 remain -= page_length;
300                 user_data += page_length;
301                 offset += page_length;
302         }
303
304 fail:
305         i915_gem_object_unpin(obj);
306         mutex_unlock(&dev->struct_mutex);
307
308         return ret;
309 }
310
311 static int
312 i915_gem_shmem_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
313                       struct drm_i915_gem_pwrite *args,
314                       struct drm_file *file_priv)
315 {
316         int ret;
317         loff_t offset;
318         ssize_t written;
319
320         mutex_lock(&dev->struct_mutex);
321
322         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
323         if (ret) {
324                 mutex_unlock(&dev->struct_mutex);
325                 return ret;
326         }
327
328         offset = args->offset;
329
330         written = vfs_write(obj->filp,
331                             (char __user *)(uintptr_t) args->data_ptr,
332                             args->size, &offset);
333         if (written != args->size) {
334                 mutex_unlock(&dev->struct_mutex);
335                 if (written < 0)
336                         return written;
337                 else
338                         return -EINVAL;
339         }
340
341         mutex_unlock(&dev->struct_mutex);
342
343         return 0;
344 }
345
346 /**
347  * Writes data to the object referenced by handle.
348  *
349  * On error, the contents of the buffer that were to be modified are undefined.
350  */
351 int
352 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
353                       struct drm_file *file_priv)
354 {
355         struct drm_i915_gem_pwrite *args = data;
356         struct drm_gem_object *obj;
357         struct drm_i915_gem_object *obj_priv;
358         int ret = 0;
359
360         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
361         if (obj == NULL)
362                 return -EBADF;
363         obj_priv = obj->driver_private;
364
365         /* Bounds check destination.
366          *
367          * XXX: This could use review for overflow issues...
368          */
369         if (args->offset > obj->size || args->size > obj->size ||
370             args->offset + args->size > obj->size) {
371                 drm_gem_object_unreference(obj);
372                 return -EINVAL;
373         }
374
375         /* We can only do the GTT pwrite on untiled buffers, as otherwise
376          * it would end up going through the fenced access, and we'll get
377          * different detiling behavior between reading and writing.
378          * pread/pwrite currently are reading and writing from the CPU
379          * perspective, requiring manual detiling by the client.
380          */
381         if (obj_priv->tiling_mode == I915_TILING_NONE &&
382             dev->gtt_total != 0)
383                 ret = i915_gem_gtt_pwrite(dev, obj, args, file_priv);
384         else
385                 ret = i915_gem_shmem_pwrite(dev, obj, args, file_priv);
386
387 #if WATCH_PWRITE
388         if (ret)
389                 DRM_INFO("pwrite failed %d\n", ret);
390 #endif
391
392         drm_gem_object_unreference(obj);
393
394         return ret;
395 }
396
397 /**
398  * Called when user space prepares to use an object with the CPU, either
399  * through the mmap ioctl's mapping or a GTT mapping.
400  */
401 int
402 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
403                           struct drm_file *file_priv)
404 {
405         struct drm_i915_gem_set_domain *args = data;
406         struct drm_gem_object *obj;
407         uint32_t read_domains = args->read_domains;
408         uint32_t write_domain = args->write_domain;
409         int ret;
410
411         if (!(dev->driver->driver_features & DRIVER_GEM))
412                 return -ENODEV;
413
414         /* Only handle setting domains to types used by the CPU. */
415         if (write_domain & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
416                 return -EINVAL;
417
418         if (read_domains & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
419                 return -EINVAL;
420
421         /* Having something in the write domain implies it's in the read
422          * domain, and only that read domain.  Enforce that in the request.
423          */
424         if (write_domain != 0 && read_domains != write_domain)
425                 return -EINVAL;
426
427         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
428         if (obj == NULL)
429                 return -EBADF;
430
431         mutex_lock(&dev->struct_mutex);
432 #if WATCH_BUF
433         DRM_INFO("set_domain_ioctl %p(%d), %08x %08x\n",
434                  obj, obj->size, read_domains, write_domain);
435 #endif
436         if (read_domains & I915_GEM_DOMAIN_GTT) {
437                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
438
439                 /* Silently promote "you're not bound, there was nothing to do"
440                  * to success, since the client was just asking us to
441                  * make sure everything was done.
442                  */
443                 if (ret == -EINVAL)
444                         ret = 0;
445         } else {
446                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
447         }
448
449         drm_gem_object_unreference(obj);
450         mutex_unlock(&dev->struct_mutex);
451         return ret;
452 }
453
454 /**
455  * Called when user space has done writes to this buffer
456  */
457 int
458 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
459                       struct drm_file *file_priv)
460 {
461         struct drm_i915_gem_sw_finish *args = data;
462         struct drm_gem_object *obj;
463         struct drm_i915_gem_object *obj_priv;
464         int ret = 0;
465
466         if (!(dev->driver->driver_features & DRIVER_GEM))
467                 return -ENODEV;
468
469         mutex_lock(&dev->struct_mutex);
470         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
471         if (obj == NULL) {
472                 mutex_unlock(&dev->struct_mutex);
473                 return -EBADF;
474         }
475
476 #if WATCH_BUF
477         DRM_INFO("%s: sw_finish %d (%p %d)\n",
478                  __func__, args->handle, obj, obj->size);
479 #endif
480         obj_priv = obj->driver_private;
481
482         /* Pinned buffers may be scanout, so flush the cache */
483         if (obj_priv->pin_count)
484                 i915_gem_object_flush_cpu_write_domain(obj);
485
486         drm_gem_object_unreference(obj);
487         mutex_unlock(&dev->struct_mutex);
488         return ret;
489 }
490
491 /**
492  * Maps the contents of an object, returning the address it is mapped
493  * into.
494  *
495  * While the mapping holds a reference on the contents of the object, it doesn't
496  * imply a ref on the object itself.
497  */
498 int
499 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
500                    struct drm_file *file_priv)
501 {
502         struct drm_i915_gem_mmap *args = data;
503         struct drm_gem_object *obj;
504         loff_t offset;
505         unsigned long addr;
506
507         if (!(dev->driver->driver_features & DRIVER_GEM))
508                 return -ENODEV;
509
510         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
511         if (obj == NULL)
512                 return -EBADF;
513
514         offset = args->offset;
515
516         down_write(&current->mm->mmap_sem);
517         addr = do_mmap(obj->filp, 0, args->size,
518                        PROT_READ | PROT_WRITE, MAP_SHARED,
519                        args->offset);
520         up_write(&current->mm->mmap_sem);
521         mutex_lock(&dev->struct_mutex);
522         drm_gem_object_unreference(obj);
523         mutex_unlock(&dev->struct_mutex);
524         if (IS_ERR((void *)addr))
525                 return addr;
526
527         args->addr_ptr = (uint64_t) addr;
528
529         return 0;
530 }
531
532 static void
533 i915_gem_object_free_page_list(struct drm_gem_object *obj)
534 {
535         struct drm_i915_gem_object *obj_priv = obj->driver_private;
536         int page_count = obj->size / PAGE_SIZE;
537         int i;
538
539         if (obj_priv->page_list == NULL)
540                 return;
541
542
543         for (i = 0; i < page_count; i++)
544                 if (obj_priv->page_list[i] != NULL) {
545                         if (obj_priv->dirty)
546                                 set_page_dirty(obj_priv->page_list[i]);
547                         mark_page_accessed(obj_priv->page_list[i]);
548                         page_cache_release(obj_priv->page_list[i]);
549                 }
550         obj_priv->dirty = 0;
551
552         drm_free(obj_priv->page_list,
553                  page_count * sizeof(struct page *),
554                  DRM_MEM_DRIVER);
555         obj_priv->page_list = NULL;
556 }
557
558 static void
559 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
560 {
561         struct drm_device *dev = obj->dev;
562         drm_i915_private_t *dev_priv = dev->dev_private;
563         struct drm_i915_gem_object *obj_priv = obj->driver_private;
564
565         /* Add a reference if we're newly entering the active list. */
566         if (!obj_priv->active) {
567                 drm_gem_object_reference(obj);
568                 obj_priv->active = 1;
569         }
570         /* Move from whatever list we were on to the tail of execution. */
571         list_move_tail(&obj_priv->list,
572                        &dev_priv->mm.active_list);
573         obj_priv->last_rendering_seqno = seqno;
574 }
575
576 static void
577 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
578 {
579         struct drm_device *dev = obj->dev;
580         drm_i915_private_t *dev_priv = dev->dev_private;
581         struct drm_i915_gem_object *obj_priv = obj->driver_private;
582
583         BUG_ON(!obj_priv->active);
584         list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
585         obj_priv->last_rendering_seqno = 0;
586 }
587
588 static void
589 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
590 {
591         struct drm_device *dev = obj->dev;
592         drm_i915_private_t *dev_priv = dev->dev_private;
593         struct drm_i915_gem_object *obj_priv = obj->driver_private;
594
595         i915_verify_inactive(dev, __FILE__, __LINE__);
596         if (obj_priv->pin_count != 0)
597                 list_del_init(&obj_priv->list);
598         else
599                 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
600
601         obj_priv->last_rendering_seqno = 0;
602         if (obj_priv->active) {
603                 obj_priv->active = 0;
604                 drm_gem_object_unreference(obj);
605         }
606         i915_verify_inactive(dev, __FILE__, __LINE__);
607 }
608
609 /**
610  * Creates a new sequence number, emitting a write of it to the status page
611  * plus an interrupt, which will trigger i915_user_interrupt_handler.
612  *
613  * Must be called with struct_lock held.
614  *
615  * Returned sequence numbers are nonzero on success.
616  */
617 static uint32_t
618 i915_add_request(struct drm_device *dev, uint32_t flush_domains)
619 {
620         drm_i915_private_t *dev_priv = dev->dev_private;
621         struct drm_i915_gem_request *request;
622         uint32_t seqno;
623         int was_empty;
624         RING_LOCALS;
625
626         request = drm_calloc(1, sizeof(*request), DRM_MEM_DRIVER);
627         if (request == NULL)
628                 return 0;
629
630         /* Grab the seqno we're going to make this request be, and bump the
631          * next (skipping 0 so it can be the reserved no-seqno value).
632          */
633         seqno = dev_priv->mm.next_gem_seqno;
634         dev_priv->mm.next_gem_seqno++;
635         if (dev_priv->mm.next_gem_seqno == 0)
636                 dev_priv->mm.next_gem_seqno++;
637
638         BEGIN_LP_RING(4);
639         OUT_RING(MI_STORE_DWORD_INDEX);
640         OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
641         OUT_RING(seqno);
642
643         OUT_RING(MI_USER_INTERRUPT);
644         ADVANCE_LP_RING();
645
646         DRM_DEBUG("%d\n", seqno);
647
648         request->seqno = seqno;
649         request->emitted_jiffies = jiffies;
650         was_empty = list_empty(&dev_priv->mm.request_list);
651         list_add_tail(&request->list, &dev_priv->mm.request_list);
652
653         /* Associate any objects on the flushing list matching the write
654          * domain we're flushing with our flush.
655          */
656         if (flush_domains != 0) {
657                 struct drm_i915_gem_object *obj_priv, *next;
658
659                 list_for_each_entry_safe(obj_priv, next,
660                                          &dev_priv->mm.flushing_list, list) {
661                         struct drm_gem_object *obj = obj_priv->obj;
662
663                         if ((obj->write_domain & flush_domains) ==
664                             obj->write_domain) {
665                                 obj->write_domain = 0;
666                                 i915_gem_object_move_to_active(obj, seqno);
667                         }
668                 }
669
670         }
671
672         if (was_empty && !dev_priv->mm.suspended)
673                 schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
674         return seqno;
675 }
676
677 /**
678  * Command execution barrier
679  *
680  * Ensures that all commands in the ring are finished
681  * before signalling the CPU
682  */
683 static uint32_t
684 i915_retire_commands(struct drm_device *dev)
685 {
686         drm_i915_private_t *dev_priv = dev->dev_private;
687         uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
688         uint32_t flush_domains = 0;
689         RING_LOCALS;
690
691         /* The sampler always gets flushed on i965 (sigh) */
692         if (IS_I965G(dev))
693                 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
694         BEGIN_LP_RING(2);
695         OUT_RING(cmd);
696         OUT_RING(0); /* noop */
697         ADVANCE_LP_RING();
698         return flush_domains;
699 }
700
701 /**
702  * Moves buffers associated only with the given active seqno from the active
703  * to inactive list, potentially freeing them.
704  */
705 static void
706 i915_gem_retire_request(struct drm_device *dev,
707                         struct drm_i915_gem_request *request)
708 {
709         drm_i915_private_t *dev_priv = dev->dev_private;
710
711         /* Move any buffers on the active list that are no longer referenced
712          * by the ringbuffer to the flushing/inactive lists as appropriate.
713          */
714         while (!list_empty(&dev_priv->mm.active_list)) {
715                 struct drm_gem_object *obj;
716                 struct drm_i915_gem_object *obj_priv;
717
718                 obj_priv = list_first_entry(&dev_priv->mm.active_list,
719                                             struct drm_i915_gem_object,
720                                             list);
721                 obj = obj_priv->obj;
722
723                 /* If the seqno being retired doesn't match the oldest in the
724                  * list, then the oldest in the list must still be newer than
725                  * this seqno.
726                  */
727                 if (obj_priv->last_rendering_seqno != request->seqno)
728                         return;
729 #if WATCH_LRU
730                 DRM_INFO("%s: retire %d moves to inactive list %p\n",
731                          __func__, request->seqno, obj);
732 #endif
733
734                 if (obj->write_domain != 0)
735                         i915_gem_object_move_to_flushing(obj);
736                 else
737                         i915_gem_object_move_to_inactive(obj);
738         }
739 }
740
741 /**
742  * Returns true if seq1 is later than seq2.
743  */
744 static int
745 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
746 {
747         return (int32_t)(seq1 - seq2) >= 0;
748 }
749
750 uint32_t
751 i915_get_gem_seqno(struct drm_device *dev)
752 {
753         drm_i915_private_t *dev_priv = dev->dev_private;
754
755         return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
756 }
757
758 /**
759  * This function clears the request list as sequence numbers are passed.
760  */
761 void
762 i915_gem_retire_requests(struct drm_device *dev)
763 {
764         drm_i915_private_t *dev_priv = dev->dev_private;
765         uint32_t seqno;
766
767         seqno = i915_get_gem_seqno(dev);
768
769         while (!list_empty(&dev_priv->mm.request_list)) {
770                 struct drm_i915_gem_request *request;
771                 uint32_t retiring_seqno;
772
773                 request = list_first_entry(&dev_priv->mm.request_list,
774                                            struct drm_i915_gem_request,
775                                            list);
776                 retiring_seqno = request->seqno;
777
778                 if (i915_seqno_passed(seqno, retiring_seqno) ||
779                     dev_priv->mm.wedged) {
780                         i915_gem_retire_request(dev, request);
781
782                         list_del(&request->list);
783                         drm_free(request, sizeof(*request), DRM_MEM_DRIVER);
784                 } else
785                         break;
786         }
787 }
788
789 void
790 i915_gem_retire_work_handler(struct work_struct *work)
791 {
792         drm_i915_private_t *dev_priv;
793         struct drm_device *dev;
794
795         dev_priv = container_of(work, drm_i915_private_t,
796                                 mm.retire_work.work);
797         dev = dev_priv->dev;
798
799         mutex_lock(&dev->struct_mutex);
800         i915_gem_retire_requests(dev);
801         if (!dev_priv->mm.suspended &&
802             !list_empty(&dev_priv->mm.request_list))
803                 schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
804         mutex_unlock(&dev->struct_mutex);
805 }
806
807 /**
808  * Waits for a sequence number to be signaled, and cleans up the
809  * request and object lists appropriately for that event.
810  */
811 static int
812 i915_wait_request(struct drm_device *dev, uint32_t seqno)
813 {
814         drm_i915_private_t *dev_priv = dev->dev_private;
815         int ret = 0;
816
817         BUG_ON(seqno == 0);
818
819         if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
820                 dev_priv->mm.waiting_gem_seqno = seqno;
821                 i915_user_irq_get(dev);
822                 ret = wait_event_interruptible(dev_priv->irq_queue,
823                                                i915_seqno_passed(i915_get_gem_seqno(dev),
824                                                                  seqno) ||
825                                                dev_priv->mm.wedged);
826                 i915_user_irq_put(dev);
827                 dev_priv->mm.waiting_gem_seqno = 0;
828         }
829         if (dev_priv->mm.wedged)
830                 ret = -EIO;
831
832         if (ret && ret != -ERESTARTSYS)
833                 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
834                           __func__, ret, seqno, i915_get_gem_seqno(dev));
835
836         /* Directly dispatch request retiring.  While we have the work queue
837          * to handle this, the waiter on a request often wants an associated
838          * buffer to have made it to the inactive list, and we would need
839          * a separate wait queue to handle that.
840          */
841         if (ret == 0)
842                 i915_gem_retire_requests(dev);
843
844         return ret;
845 }
846
847 static void
848 i915_gem_flush(struct drm_device *dev,
849                uint32_t invalidate_domains,
850                uint32_t flush_domains)
851 {
852         drm_i915_private_t *dev_priv = dev->dev_private;
853         uint32_t cmd;
854         RING_LOCALS;
855
856 #if WATCH_EXEC
857         DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
858                   invalidate_domains, flush_domains);
859 #endif
860
861         if (flush_domains & I915_GEM_DOMAIN_CPU)
862                 drm_agp_chipset_flush(dev);
863
864         if ((invalidate_domains | flush_domains) & ~(I915_GEM_DOMAIN_CPU |
865                                                      I915_GEM_DOMAIN_GTT)) {
866                 /*
867                  * read/write caches:
868                  *
869                  * I915_GEM_DOMAIN_RENDER is always invalidated, but is
870                  * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
871                  * also flushed at 2d versus 3d pipeline switches.
872                  *
873                  * read-only caches:
874                  *
875                  * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
876                  * MI_READ_FLUSH is set, and is always flushed on 965.
877                  *
878                  * I915_GEM_DOMAIN_COMMAND may not exist?
879                  *
880                  * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
881                  * invalidated when MI_EXE_FLUSH is set.
882                  *
883                  * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
884                  * invalidated with every MI_FLUSH.
885                  *
886                  * TLBs:
887                  *
888                  * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
889                  * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
890                  * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
891                  * are flushed at any MI_FLUSH.
892                  */
893
894                 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
895                 if ((invalidate_domains|flush_domains) &
896                     I915_GEM_DOMAIN_RENDER)
897                         cmd &= ~MI_NO_WRITE_FLUSH;
898                 if (!IS_I965G(dev)) {
899                         /*
900                          * On the 965, the sampler cache always gets flushed
901                          * and this bit is reserved.
902                          */
903                         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
904                                 cmd |= MI_READ_FLUSH;
905                 }
906                 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
907                         cmd |= MI_EXE_FLUSH;
908
909 #if WATCH_EXEC
910                 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
911 #endif
912                 BEGIN_LP_RING(2);
913                 OUT_RING(cmd);
914                 OUT_RING(0); /* noop */
915                 ADVANCE_LP_RING();
916         }
917 }
918
919 /**
920  * Ensures that all rendering to the object has completed and the object is
921  * safe to unbind from the GTT or access from the CPU.
922  */
923 static int
924 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
925 {
926         struct drm_device *dev = obj->dev;
927         struct drm_i915_gem_object *obj_priv = obj->driver_private;
928         int ret;
929
930         /* This function only exists to support waiting for existing rendering,
931          * not for emitting required flushes.
932          */
933         BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
934
935         /* If there is rendering queued on the buffer being evicted, wait for
936          * it.
937          */
938         if (obj_priv->active) {
939 #if WATCH_BUF
940                 DRM_INFO("%s: object %p wait for seqno %08x\n",
941                           __func__, obj, obj_priv->last_rendering_seqno);
942 #endif
943                 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
944                 if (ret != 0)
945                         return ret;
946         }
947
948         return 0;
949 }
950
951 /**
952  * Unbinds an object from the GTT aperture.
953  */
954 static int
955 i915_gem_object_unbind(struct drm_gem_object *obj)
956 {
957         struct drm_device *dev = obj->dev;
958         struct drm_i915_gem_object *obj_priv = obj->driver_private;
959         int ret = 0;
960
961 #if WATCH_BUF
962         DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
963         DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
964 #endif
965         if (obj_priv->gtt_space == NULL)
966                 return 0;
967
968         if (obj_priv->pin_count != 0) {
969                 DRM_ERROR("Attempting to unbind pinned buffer\n");
970                 return -EINVAL;
971         }
972
973         /* Move the object to the CPU domain to ensure that
974          * any possible CPU writes while it's not in the GTT
975          * are flushed when we go to remap it. This will
976          * also ensure that all pending GPU writes are finished
977          * before we unbind.
978          */
979         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
980         if (ret) {
981                 if (ret != -ERESTARTSYS)
982                         DRM_ERROR("set_domain failed: %d\n", ret);
983                 return ret;
984         }
985
986         if (obj_priv->agp_mem != NULL) {
987                 drm_unbind_agp(obj_priv->agp_mem);
988                 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
989                 obj_priv->agp_mem = NULL;
990         }
991
992         BUG_ON(obj_priv->active);
993
994         i915_gem_object_free_page_list(obj);
995
996         if (obj_priv->gtt_space) {
997                 atomic_dec(&dev->gtt_count);
998                 atomic_sub(obj->size, &dev->gtt_memory);
999
1000                 drm_mm_put_block(obj_priv->gtt_space);
1001                 obj_priv->gtt_space = NULL;
1002         }
1003
1004         /* Remove ourselves from the LRU list if present. */
1005         if (!list_empty(&obj_priv->list))
1006                 list_del_init(&obj_priv->list);
1007
1008         return 0;
1009 }
1010
1011 static int
1012 i915_gem_evict_something(struct drm_device *dev)
1013 {
1014         drm_i915_private_t *dev_priv = dev->dev_private;
1015         struct drm_gem_object *obj;
1016         struct drm_i915_gem_object *obj_priv;
1017         int ret = 0;
1018
1019         for (;;) {
1020                 /* If there's an inactive buffer available now, grab it
1021                  * and be done.
1022                  */
1023                 if (!list_empty(&dev_priv->mm.inactive_list)) {
1024                         obj_priv = list_first_entry(&dev_priv->mm.inactive_list,
1025                                                     struct drm_i915_gem_object,
1026                                                     list);
1027                         obj = obj_priv->obj;
1028                         BUG_ON(obj_priv->pin_count != 0);
1029 #if WATCH_LRU
1030                         DRM_INFO("%s: evicting %p\n", __func__, obj);
1031 #endif
1032                         BUG_ON(obj_priv->active);
1033
1034                         /* Wait on the rendering and unbind the buffer. */
1035                         ret = i915_gem_object_unbind(obj);
1036                         break;
1037                 }
1038
1039                 /* If we didn't get anything, but the ring is still processing
1040                  * things, wait for one of those things to finish and hopefully
1041                  * leave us a buffer to evict.
1042                  */
1043                 if (!list_empty(&dev_priv->mm.request_list)) {
1044                         struct drm_i915_gem_request *request;
1045
1046                         request = list_first_entry(&dev_priv->mm.request_list,
1047                                                    struct drm_i915_gem_request,
1048                                                    list);
1049
1050                         ret = i915_wait_request(dev, request->seqno);
1051                         if (ret)
1052                                 break;
1053
1054                         /* if waiting caused an object to become inactive,
1055                          * then loop around and wait for it. Otherwise, we
1056                          * assume that waiting freed and unbound something,
1057                          * so there should now be some space in the GTT
1058                          */
1059                         if (!list_empty(&dev_priv->mm.inactive_list))
1060                                 continue;
1061                         break;
1062                 }
1063
1064                 /* If we didn't have anything on the request list but there
1065                  * are buffers awaiting a flush, emit one and try again.
1066                  * When we wait on it, those buffers waiting for that flush
1067                  * will get moved to inactive.
1068                  */
1069                 if (!list_empty(&dev_priv->mm.flushing_list)) {
1070                         obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
1071                                                     struct drm_i915_gem_object,
1072                                                     list);
1073                         obj = obj_priv->obj;
1074
1075                         i915_gem_flush(dev,
1076                                        obj->write_domain,
1077                                        obj->write_domain);
1078                         i915_add_request(dev, obj->write_domain);
1079
1080                         obj = NULL;
1081                         continue;
1082                 }
1083
1084                 DRM_ERROR("inactive empty %d request empty %d "
1085                           "flushing empty %d\n",
1086                           list_empty(&dev_priv->mm.inactive_list),
1087                           list_empty(&dev_priv->mm.request_list),
1088                           list_empty(&dev_priv->mm.flushing_list));
1089                 /* If we didn't do any of the above, there's nothing to be done
1090                  * and we just can't fit it in.
1091                  */
1092                 return -ENOMEM;
1093         }
1094         return ret;
1095 }
1096
1097 static int
1098 i915_gem_evict_everything(struct drm_device *dev)
1099 {
1100         int ret;
1101
1102         for (;;) {
1103                 ret = i915_gem_evict_something(dev);
1104                 if (ret != 0)
1105                         break;
1106         }
1107         if (ret == -ENOMEM)
1108                 return 0;
1109         return ret;
1110 }
1111
1112 static int
1113 i915_gem_object_get_page_list(struct drm_gem_object *obj)
1114 {
1115         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1116         int page_count, i;
1117         struct address_space *mapping;
1118         struct inode *inode;
1119         struct page *page;
1120         int ret;
1121
1122         if (obj_priv->page_list)
1123                 return 0;
1124
1125         /* Get the list of pages out of our struct file.  They'll be pinned
1126          * at this point until we release them.
1127          */
1128         page_count = obj->size / PAGE_SIZE;
1129         BUG_ON(obj_priv->page_list != NULL);
1130         obj_priv->page_list = drm_calloc(page_count, sizeof(struct page *),
1131                                          DRM_MEM_DRIVER);
1132         if (obj_priv->page_list == NULL) {
1133                 DRM_ERROR("Faled to allocate page list\n");
1134                 return -ENOMEM;
1135         }
1136
1137         inode = obj->filp->f_path.dentry->d_inode;
1138         mapping = inode->i_mapping;
1139         for (i = 0; i < page_count; i++) {
1140                 page = read_mapping_page(mapping, i, NULL);
1141                 if (IS_ERR(page)) {
1142                         ret = PTR_ERR(page);
1143                         DRM_ERROR("read_mapping_page failed: %d\n", ret);
1144                         i915_gem_object_free_page_list(obj);
1145                         return ret;
1146                 }
1147                 obj_priv->page_list[i] = page;
1148         }
1149         return 0;
1150 }
1151
1152 /**
1153  * Finds free space in the GTT aperture and binds the object there.
1154  */
1155 static int
1156 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
1157 {
1158         struct drm_device *dev = obj->dev;
1159         drm_i915_private_t *dev_priv = dev->dev_private;
1160         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1161         struct drm_mm_node *free_space;
1162         int page_count, ret;
1163
1164         if (alignment == 0)
1165                 alignment = PAGE_SIZE;
1166         if (alignment & (PAGE_SIZE - 1)) {
1167                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
1168                 return -EINVAL;
1169         }
1170
1171  search_free:
1172         free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
1173                                         obj->size, alignment, 0);
1174         if (free_space != NULL) {
1175                 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
1176                                                        alignment);
1177                 if (obj_priv->gtt_space != NULL) {
1178                         obj_priv->gtt_space->private = obj;
1179                         obj_priv->gtt_offset = obj_priv->gtt_space->start;
1180                 }
1181         }
1182         if (obj_priv->gtt_space == NULL) {
1183                 /* If the gtt is empty and we're still having trouble
1184                  * fitting our object in, we're out of memory.
1185                  */
1186 #if WATCH_LRU
1187                 DRM_INFO("%s: GTT full, evicting something\n", __func__);
1188 #endif
1189                 if (list_empty(&dev_priv->mm.inactive_list) &&
1190                     list_empty(&dev_priv->mm.flushing_list) &&
1191                     list_empty(&dev_priv->mm.active_list)) {
1192                         DRM_ERROR("GTT full, but LRU list empty\n");
1193                         return -ENOMEM;
1194                 }
1195
1196                 ret = i915_gem_evict_something(dev);
1197                 if (ret != 0) {
1198                         if (ret != -ERESTARTSYS)
1199                                 DRM_ERROR("Failed to evict a buffer %d\n", ret);
1200                         return ret;
1201                 }
1202                 goto search_free;
1203         }
1204
1205 #if WATCH_BUF
1206         DRM_INFO("Binding object of size %d at 0x%08x\n",
1207                  obj->size, obj_priv->gtt_offset);
1208 #endif
1209         ret = i915_gem_object_get_page_list(obj);
1210         if (ret) {
1211                 drm_mm_put_block(obj_priv->gtt_space);
1212                 obj_priv->gtt_space = NULL;
1213                 return ret;
1214         }
1215
1216         page_count = obj->size / PAGE_SIZE;
1217         /* Create an AGP memory structure pointing at our pages, and bind it
1218          * into the GTT.
1219          */
1220         obj_priv->agp_mem = drm_agp_bind_pages(dev,
1221                                                obj_priv->page_list,
1222                                                page_count,
1223                                                obj_priv->gtt_offset,
1224                                                obj_priv->agp_type);
1225         if (obj_priv->agp_mem == NULL) {
1226                 i915_gem_object_free_page_list(obj);
1227                 drm_mm_put_block(obj_priv->gtt_space);
1228                 obj_priv->gtt_space = NULL;
1229                 return -ENOMEM;
1230         }
1231         atomic_inc(&dev->gtt_count);
1232         atomic_add(obj->size, &dev->gtt_memory);
1233
1234         /* Assert that the object is not currently in any GPU domain. As it
1235          * wasn't in the GTT, there shouldn't be any way it could have been in
1236          * a GPU cache
1237          */
1238         BUG_ON(obj->read_domains & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
1239         BUG_ON(obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
1240
1241         return 0;
1242 }
1243
1244 void
1245 i915_gem_clflush_object(struct drm_gem_object *obj)
1246 {
1247         struct drm_i915_gem_object      *obj_priv = obj->driver_private;
1248
1249         /* If we don't have a page list set up, then we're not pinned
1250          * to GPU, and we can ignore the cache flush because it'll happen
1251          * again at bind time.
1252          */
1253         if (obj_priv->page_list == NULL)
1254                 return;
1255
1256         drm_clflush_pages(obj_priv->page_list, obj->size / PAGE_SIZE);
1257 }
1258
1259 /** Flushes any GPU write domain for the object if it's dirty. */
1260 static void
1261 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
1262 {
1263         struct drm_device *dev = obj->dev;
1264         uint32_t seqno;
1265
1266         if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
1267                 return;
1268
1269         /* Queue the GPU write cache flushing we need. */
1270         i915_gem_flush(dev, 0, obj->write_domain);
1271         seqno = i915_add_request(dev, obj->write_domain);
1272         obj->write_domain = 0;
1273         i915_gem_object_move_to_active(obj, seqno);
1274 }
1275
1276 /** Flushes the GTT write domain for the object if it's dirty. */
1277 static void
1278 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
1279 {
1280         if (obj->write_domain != I915_GEM_DOMAIN_GTT)
1281                 return;
1282
1283         /* No actual flushing is required for the GTT write domain.   Writes
1284          * to it immediately go to main memory as far as we know, so there's
1285          * no chipset flush.  It also doesn't land in render cache.
1286          */
1287         obj->write_domain = 0;
1288 }
1289
1290 /** Flushes the CPU write domain for the object if it's dirty. */
1291 static void
1292 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
1293 {
1294         struct drm_device *dev = obj->dev;
1295
1296         if (obj->write_domain != I915_GEM_DOMAIN_CPU)
1297                 return;
1298
1299         i915_gem_clflush_object(obj);
1300         drm_agp_chipset_flush(dev);
1301         obj->write_domain = 0;
1302 }
1303
1304 /**
1305  * Moves a single object to the GTT read, and possibly write domain.
1306  *
1307  * This function returns when the move is complete, including waiting on
1308  * flushes to occur.
1309  */
1310 static int
1311 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
1312 {
1313         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1314         int ret;
1315
1316         /* Not valid to be called on unbound objects. */
1317         if (obj_priv->gtt_space == NULL)
1318                 return -EINVAL;
1319
1320         i915_gem_object_flush_gpu_write_domain(obj);
1321         /* Wait on any GPU rendering and flushing to occur. */
1322         ret = i915_gem_object_wait_rendering(obj);
1323         if (ret != 0)
1324                 return ret;
1325
1326         /* If we're writing through the GTT domain, then CPU and GPU caches
1327          * will need to be invalidated at next use.
1328          */
1329         if (write)
1330                 obj->read_domains &= I915_GEM_DOMAIN_GTT;
1331
1332         i915_gem_object_flush_cpu_write_domain(obj);
1333
1334         /* It should now be out of any other write domains, and we can update
1335          * the domain values for our changes.
1336          */
1337         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
1338         obj->read_domains |= I915_GEM_DOMAIN_GTT;
1339         if (write) {
1340                 obj->write_domain = I915_GEM_DOMAIN_GTT;
1341                 obj_priv->dirty = 1;
1342         }
1343
1344         return 0;
1345 }
1346
1347 /**
1348  * Moves a single object to the CPU read, and possibly write domain.
1349  *
1350  * This function returns when the move is complete, including waiting on
1351  * flushes to occur.
1352  */
1353 static int
1354 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
1355 {
1356         struct drm_device *dev = obj->dev;
1357         int ret;
1358
1359         i915_gem_object_flush_gpu_write_domain(obj);
1360         /* Wait on any GPU rendering and flushing to occur. */
1361         ret = i915_gem_object_wait_rendering(obj);
1362         if (ret != 0)
1363                 return ret;
1364
1365         i915_gem_object_flush_gtt_write_domain(obj);
1366
1367         /* If we have a partially-valid cache of the object in the CPU,
1368          * finish invalidating it and free the per-page flags.
1369          */
1370         i915_gem_object_set_to_full_cpu_read_domain(obj);
1371
1372         /* Flush the CPU cache if it's still invalid. */
1373         if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
1374                 i915_gem_clflush_object(obj);
1375                 drm_agp_chipset_flush(dev);
1376
1377                 obj->read_domains |= I915_GEM_DOMAIN_CPU;
1378         }
1379
1380         /* It should now be out of any other write domains, and we can update
1381          * the domain values for our changes.
1382          */
1383         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
1384
1385         /* If we're writing through the CPU, then the GPU read domains will
1386          * need to be invalidated at next use.
1387          */
1388         if (write) {
1389                 obj->read_domains &= I915_GEM_DOMAIN_CPU;
1390                 obj->write_domain = I915_GEM_DOMAIN_CPU;
1391         }
1392
1393         return 0;
1394 }
1395
1396 /*
1397  * Set the next domain for the specified object. This
1398  * may not actually perform the necessary flushing/invaliding though,
1399  * as that may want to be batched with other set_domain operations
1400  *
1401  * This is (we hope) the only really tricky part of gem. The goal
1402  * is fairly simple -- track which caches hold bits of the object
1403  * and make sure they remain coherent. A few concrete examples may
1404  * help to explain how it works. For shorthand, we use the notation
1405  * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
1406  * a pair of read and write domain masks.
1407  *
1408  * Case 1: the batch buffer
1409  *
1410  *      1. Allocated
1411  *      2. Written by CPU
1412  *      3. Mapped to GTT
1413  *      4. Read by GPU
1414  *      5. Unmapped from GTT
1415  *      6. Freed
1416  *
1417  *      Let's take these a step at a time
1418  *
1419  *      1. Allocated
1420  *              Pages allocated from the kernel may still have
1421  *              cache contents, so we set them to (CPU, CPU) always.
1422  *      2. Written by CPU (using pwrite)
1423  *              The pwrite function calls set_domain (CPU, CPU) and
1424  *              this function does nothing (as nothing changes)
1425  *      3. Mapped by GTT
1426  *              This function asserts that the object is not
1427  *              currently in any GPU-based read or write domains
1428  *      4. Read by GPU
1429  *              i915_gem_execbuffer calls set_domain (COMMAND, 0).
1430  *              As write_domain is zero, this function adds in the
1431  *              current read domains (CPU+COMMAND, 0).
1432  *              flush_domains is set to CPU.
1433  *              invalidate_domains is set to COMMAND
1434  *              clflush is run to get data out of the CPU caches
1435  *              then i915_dev_set_domain calls i915_gem_flush to
1436  *              emit an MI_FLUSH and drm_agp_chipset_flush
1437  *      5. Unmapped from GTT
1438  *              i915_gem_object_unbind calls set_domain (CPU, CPU)
1439  *              flush_domains and invalidate_domains end up both zero
1440  *              so no flushing/invalidating happens
1441  *      6. Freed
1442  *              yay, done
1443  *
1444  * Case 2: The shared render buffer
1445  *
1446  *      1. Allocated
1447  *      2. Mapped to GTT
1448  *      3. Read/written by GPU
1449  *      4. set_domain to (CPU,CPU)
1450  *      5. Read/written by CPU
1451  *      6. Read/written by GPU
1452  *
1453  *      1. Allocated
1454  *              Same as last example, (CPU, CPU)
1455  *      2. Mapped to GTT
1456  *              Nothing changes (assertions find that it is not in the GPU)
1457  *      3. Read/written by GPU
1458  *              execbuffer calls set_domain (RENDER, RENDER)
1459  *              flush_domains gets CPU
1460  *              invalidate_domains gets GPU
1461  *              clflush (obj)
1462  *              MI_FLUSH and drm_agp_chipset_flush
1463  *      4. set_domain (CPU, CPU)
1464  *              flush_domains gets GPU
1465  *              invalidate_domains gets CPU
1466  *              wait_rendering (obj) to make sure all drawing is complete.
1467  *              This will include an MI_FLUSH to get the data from GPU
1468  *              to memory
1469  *              clflush (obj) to invalidate the CPU cache
1470  *              Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
1471  *      5. Read/written by CPU
1472  *              cache lines are loaded and dirtied
1473  *      6. Read written by GPU
1474  *              Same as last GPU access
1475  *
1476  * Case 3: The constant buffer
1477  *
1478  *      1. Allocated
1479  *      2. Written by CPU
1480  *      3. Read by GPU
1481  *      4. Updated (written) by CPU again
1482  *      5. Read by GPU
1483  *
1484  *      1. Allocated
1485  *              (CPU, CPU)
1486  *      2. Written by CPU
1487  *              (CPU, CPU)
1488  *      3. Read by GPU
1489  *              (CPU+RENDER, 0)
1490  *              flush_domains = CPU
1491  *              invalidate_domains = RENDER
1492  *              clflush (obj)
1493  *              MI_FLUSH
1494  *              drm_agp_chipset_flush
1495  *      4. Updated (written) by CPU again
1496  *              (CPU, CPU)
1497  *              flush_domains = 0 (no previous write domain)
1498  *              invalidate_domains = 0 (no new read domains)
1499  *      5. Read by GPU
1500  *              (CPU+RENDER, 0)
1501  *              flush_domains = CPU
1502  *              invalidate_domains = RENDER
1503  *              clflush (obj)
1504  *              MI_FLUSH
1505  *              drm_agp_chipset_flush
1506  */
1507 static void
1508 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj,
1509                                   uint32_t read_domains,
1510                                   uint32_t write_domain)
1511 {
1512         struct drm_device               *dev = obj->dev;
1513         struct drm_i915_gem_object      *obj_priv = obj->driver_private;
1514         uint32_t                        invalidate_domains = 0;
1515         uint32_t                        flush_domains = 0;
1516
1517         BUG_ON(read_domains & I915_GEM_DOMAIN_CPU);
1518         BUG_ON(write_domain == I915_GEM_DOMAIN_CPU);
1519
1520 #if WATCH_BUF
1521         DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
1522                  __func__, obj,
1523                  obj->read_domains, read_domains,
1524                  obj->write_domain, write_domain);
1525 #endif
1526         /*
1527          * If the object isn't moving to a new write domain,
1528          * let the object stay in multiple read domains
1529          */
1530         if (write_domain == 0)
1531                 read_domains |= obj->read_domains;
1532         else
1533                 obj_priv->dirty = 1;
1534
1535         /*
1536          * Flush the current write domain if
1537          * the new read domains don't match. Invalidate
1538          * any read domains which differ from the old
1539          * write domain
1540          */
1541         if (obj->write_domain && obj->write_domain != read_domains) {
1542                 flush_domains |= obj->write_domain;
1543                 invalidate_domains |= read_domains & ~obj->write_domain;
1544         }
1545         /*
1546          * Invalidate any read caches which may have
1547          * stale data. That is, any new read domains.
1548          */
1549         invalidate_domains |= read_domains & ~obj->read_domains;
1550         if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
1551 #if WATCH_BUF
1552                 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
1553                          __func__, flush_domains, invalidate_domains);
1554 #endif
1555                 i915_gem_clflush_object(obj);
1556         }
1557
1558         if ((write_domain | flush_domains) != 0)
1559                 obj->write_domain = write_domain;
1560         obj->read_domains = read_domains;
1561
1562         dev->invalidate_domains |= invalidate_domains;
1563         dev->flush_domains |= flush_domains;
1564 #if WATCH_BUF
1565         DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
1566                  __func__,
1567                  obj->read_domains, obj->write_domain,
1568                  dev->invalidate_domains, dev->flush_domains);
1569 #endif
1570 }
1571
1572 /**
1573  * Moves the object from a partially CPU read to a full one.
1574  *
1575  * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
1576  * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
1577  */
1578 static void
1579 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
1580 {
1581         struct drm_device *dev = obj->dev;
1582         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1583
1584         if (!obj_priv->page_cpu_valid)
1585                 return;
1586
1587         /* If we're partially in the CPU read domain, finish moving it in.
1588          */
1589         if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
1590                 int i;
1591
1592                 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
1593                         if (obj_priv->page_cpu_valid[i])
1594                                 continue;
1595                         drm_clflush_pages(obj_priv->page_list + i, 1);
1596                 }
1597                 drm_agp_chipset_flush(dev);
1598         }
1599
1600         /* Free the page_cpu_valid mappings which are now stale, whether
1601          * or not we've got I915_GEM_DOMAIN_CPU.
1602          */
1603         drm_free(obj_priv->page_cpu_valid, obj->size / PAGE_SIZE,
1604                  DRM_MEM_DRIVER);
1605         obj_priv->page_cpu_valid = NULL;
1606 }
1607
1608 /**
1609  * Set the CPU read domain on a range of the object.
1610  *
1611  * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
1612  * not entirely valid.  The page_cpu_valid member of the object flags which
1613  * pages have been flushed, and will be respected by
1614  * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
1615  * of the whole object.
1616  *
1617  * This function returns when the move is complete, including waiting on
1618  * flushes to occur.
1619  */
1620 static int
1621 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
1622                                           uint64_t offset, uint64_t size)
1623 {
1624         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1625         int i, ret;
1626
1627         if (offset == 0 && size == obj->size)
1628                 return i915_gem_object_set_to_cpu_domain(obj, 0);
1629
1630         i915_gem_object_flush_gpu_write_domain(obj);
1631         /* Wait on any GPU rendering and flushing to occur. */
1632         ret = i915_gem_object_wait_rendering(obj);
1633         if (ret != 0)
1634                 return ret;
1635         i915_gem_object_flush_gtt_write_domain(obj);
1636
1637         /* If we're already fully in the CPU read domain, we're done. */
1638         if (obj_priv->page_cpu_valid == NULL &&
1639             (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
1640                 return 0;
1641
1642         /* Otherwise, create/clear the per-page CPU read domain flag if we're
1643          * newly adding I915_GEM_DOMAIN_CPU
1644          */
1645         if (obj_priv->page_cpu_valid == NULL) {
1646                 obj_priv->page_cpu_valid = drm_calloc(1, obj->size / PAGE_SIZE,
1647                                                       DRM_MEM_DRIVER);
1648                 if (obj_priv->page_cpu_valid == NULL)
1649                         return -ENOMEM;
1650         } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
1651                 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
1652
1653         /* Flush the cache on any pages that are still invalid from the CPU's
1654          * perspective.
1655          */
1656         for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
1657              i++) {
1658                 if (obj_priv->page_cpu_valid[i])
1659                         continue;
1660
1661                 drm_clflush_pages(obj_priv->page_list + i, 1);
1662
1663                 obj_priv->page_cpu_valid[i] = 1;
1664         }
1665
1666         /* It should now be out of any other write domains, and we can update
1667          * the domain values for our changes.
1668          */
1669         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
1670
1671         obj->read_domains |= I915_GEM_DOMAIN_CPU;
1672
1673         return 0;
1674 }
1675
1676 /**
1677  * Pin an object to the GTT and evaluate the relocations landing in it.
1678  */
1679 static int
1680 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
1681                                  struct drm_file *file_priv,
1682                                  struct drm_i915_gem_exec_object *entry)
1683 {
1684         struct drm_device *dev = obj->dev;
1685         drm_i915_private_t *dev_priv = dev->dev_private;
1686         struct drm_i915_gem_relocation_entry reloc;
1687         struct drm_i915_gem_relocation_entry __user *relocs;
1688         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1689         int i, ret;
1690         void __iomem *reloc_page;
1691
1692         /* Choose the GTT offset for our buffer and put it there. */
1693         ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
1694         if (ret)
1695                 return ret;
1696
1697         entry->offset = obj_priv->gtt_offset;
1698
1699         relocs = (struct drm_i915_gem_relocation_entry __user *)
1700                  (uintptr_t) entry->relocs_ptr;
1701         /* Apply the relocations, using the GTT aperture to avoid cache
1702          * flushing requirements.
1703          */
1704         for (i = 0; i < entry->relocation_count; i++) {
1705                 struct drm_gem_object *target_obj;
1706                 struct drm_i915_gem_object *target_obj_priv;
1707                 uint32_t reloc_val, reloc_offset;
1708                 uint32_t __iomem *reloc_entry;
1709
1710                 ret = copy_from_user(&reloc, relocs + i, sizeof(reloc));
1711                 if (ret != 0) {
1712                         i915_gem_object_unpin(obj);
1713                         return ret;
1714                 }
1715
1716                 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
1717                                                    reloc.target_handle);
1718                 if (target_obj == NULL) {
1719                         i915_gem_object_unpin(obj);
1720                         return -EBADF;
1721                 }
1722                 target_obj_priv = target_obj->driver_private;
1723
1724                 /* The target buffer should have appeared before us in the
1725                  * exec_object list, so it should have a GTT space bound by now.
1726                  */
1727                 if (target_obj_priv->gtt_space == NULL) {
1728                         DRM_ERROR("No GTT space found for object %d\n",
1729                                   reloc.target_handle);
1730                         drm_gem_object_unreference(target_obj);
1731                         i915_gem_object_unpin(obj);
1732                         return -EINVAL;
1733                 }
1734
1735                 if (reloc.offset > obj->size - 4) {
1736                         DRM_ERROR("Relocation beyond object bounds: "
1737                                   "obj %p target %d offset %d size %d.\n",
1738                                   obj, reloc.target_handle,
1739                                   (int) reloc.offset, (int) obj->size);
1740                         drm_gem_object_unreference(target_obj);
1741                         i915_gem_object_unpin(obj);
1742                         return -EINVAL;
1743                 }
1744                 if (reloc.offset & 3) {
1745                         DRM_ERROR("Relocation not 4-byte aligned: "
1746                                   "obj %p target %d offset %d.\n",
1747                                   obj, reloc.target_handle,
1748                                   (int) reloc.offset);
1749                         drm_gem_object_unreference(target_obj);
1750                         i915_gem_object_unpin(obj);
1751                         return -EINVAL;
1752                 }
1753
1754                 if (reloc.write_domain & I915_GEM_DOMAIN_CPU ||
1755                     reloc.read_domains & I915_GEM_DOMAIN_CPU) {
1756                         DRM_ERROR("reloc with read/write CPU domains: "
1757                                   "obj %p target %d offset %d "
1758                                   "read %08x write %08x",
1759                                   obj, reloc.target_handle,
1760                                   (int) reloc.offset,
1761                                   reloc.read_domains,
1762                                   reloc.write_domain);
1763                         return -EINVAL;
1764                 }
1765
1766                 if (reloc.write_domain && target_obj->pending_write_domain &&
1767                     reloc.write_domain != target_obj->pending_write_domain) {
1768                         DRM_ERROR("Write domain conflict: "
1769                                   "obj %p target %d offset %d "
1770                                   "new %08x old %08x\n",
1771                                   obj, reloc.target_handle,
1772                                   (int) reloc.offset,
1773                                   reloc.write_domain,
1774                                   target_obj->pending_write_domain);
1775                         drm_gem_object_unreference(target_obj);
1776                         i915_gem_object_unpin(obj);
1777                         return -EINVAL;
1778                 }
1779
1780 #if WATCH_RELOC
1781                 DRM_INFO("%s: obj %p offset %08x target %d "
1782                          "read %08x write %08x gtt %08x "
1783                          "presumed %08x delta %08x\n",
1784                          __func__,
1785                          obj,
1786                          (int) reloc.offset,
1787                          (int) reloc.target_handle,
1788                          (int) reloc.read_domains,
1789                          (int) reloc.write_domain,
1790                          (int) target_obj_priv->gtt_offset,
1791                          (int) reloc.presumed_offset,
1792                          reloc.delta);
1793 #endif
1794
1795                 target_obj->pending_read_domains |= reloc.read_domains;
1796                 target_obj->pending_write_domain |= reloc.write_domain;
1797
1798                 /* If the relocation already has the right value in it, no
1799                  * more work needs to be done.
1800                  */
1801                 if (target_obj_priv->gtt_offset == reloc.presumed_offset) {
1802                         drm_gem_object_unreference(target_obj);
1803                         continue;
1804                 }
1805
1806                 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
1807                 if (ret != 0) {
1808                         drm_gem_object_unreference(target_obj);
1809                         i915_gem_object_unpin(obj);
1810                         return -EINVAL;
1811                 }
1812
1813                 /* Map the page containing the relocation we're going to
1814                  * perform.
1815                  */
1816                 reloc_offset = obj_priv->gtt_offset + reloc.offset;
1817                 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
1818                                                       (reloc_offset &
1819                                                        ~(PAGE_SIZE - 1)));
1820                 reloc_entry = (uint32_t __iomem *)(reloc_page +
1821                                                    (reloc_offset & (PAGE_SIZE - 1)));
1822                 reloc_val = target_obj_priv->gtt_offset + reloc.delta;
1823
1824 #if WATCH_BUF
1825                 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
1826                           obj, (unsigned int) reloc.offset,
1827                           readl(reloc_entry), reloc_val);
1828 #endif
1829                 writel(reloc_val, reloc_entry);
1830                 io_mapping_unmap_atomic(reloc_page);
1831
1832                 /* Write the updated presumed offset for this entry back out
1833                  * to the user.
1834                  */
1835                 reloc.presumed_offset = target_obj_priv->gtt_offset;
1836                 ret = copy_to_user(relocs + i, &reloc, sizeof(reloc));
1837                 if (ret != 0) {
1838                         drm_gem_object_unreference(target_obj);
1839                         i915_gem_object_unpin(obj);
1840                         return ret;
1841                 }
1842
1843                 drm_gem_object_unreference(target_obj);
1844         }
1845
1846 #if WATCH_BUF
1847         if (0)
1848                 i915_gem_dump_object(obj, 128, __func__, ~0);
1849 #endif
1850         return 0;
1851 }
1852
1853 /** Dispatch a batchbuffer to the ring
1854  */
1855 static int
1856 i915_dispatch_gem_execbuffer(struct drm_device *dev,
1857                               struct drm_i915_gem_execbuffer *exec,
1858                               uint64_t exec_offset)
1859 {
1860         drm_i915_private_t *dev_priv = dev->dev_private;
1861         struct drm_clip_rect __user *boxes = (struct drm_clip_rect __user *)
1862                                              (uintptr_t) exec->cliprects_ptr;
1863         int nbox = exec->num_cliprects;
1864         int i = 0, count;
1865         uint32_t        exec_start, exec_len;
1866         RING_LOCALS;
1867
1868         exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
1869         exec_len = (uint32_t) exec->batch_len;
1870
1871         if ((exec_start | exec_len) & 0x7) {
1872                 DRM_ERROR("alignment\n");
1873                 return -EINVAL;
1874         }
1875
1876         if (!exec_start)
1877                 return -EINVAL;
1878
1879         count = nbox ? nbox : 1;
1880
1881         for (i = 0; i < count; i++) {
1882                 if (i < nbox) {
1883                         int ret = i915_emit_box(dev, boxes, i,
1884                                                 exec->DR1, exec->DR4);
1885                         if (ret)
1886                                 return ret;
1887                 }
1888
1889                 if (IS_I830(dev) || IS_845G(dev)) {
1890                         BEGIN_LP_RING(4);
1891                         OUT_RING(MI_BATCH_BUFFER);
1892                         OUT_RING(exec_start | MI_BATCH_NON_SECURE);
1893                         OUT_RING(exec_start + exec_len - 4);
1894                         OUT_RING(0);
1895                         ADVANCE_LP_RING();
1896                 } else {
1897                         BEGIN_LP_RING(2);
1898                         if (IS_I965G(dev)) {
1899                                 OUT_RING(MI_BATCH_BUFFER_START |
1900                                          (2 << 6) |
1901                                          MI_BATCH_NON_SECURE_I965);
1902                                 OUT_RING(exec_start);
1903                         } else {
1904                                 OUT_RING(MI_BATCH_BUFFER_START |
1905                                          (2 << 6));
1906                                 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
1907                         }
1908                         ADVANCE_LP_RING();
1909                 }
1910         }
1911
1912         /* XXX breadcrumb */
1913         return 0;
1914 }
1915
1916 /* Throttle our rendering by waiting until the ring has completed our requests
1917  * emitted over 20 msec ago.
1918  *
1919  * This should get us reasonable parallelism between CPU and GPU but also
1920  * relatively low latency when blocking on a particular request to finish.
1921  */
1922 static int
1923 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
1924 {
1925         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1926         int ret = 0;
1927         uint32_t seqno;
1928
1929         mutex_lock(&dev->struct_mutex);
1930         seqno = i915_file_priv->mm.last_gem_throttle_seqno;
1931         i915_file_priv->mm.last_gem_throttle_seqno =
1932                 i915_file_priv->mm.last_gem_seqno;
1933         if (seqno)
1934                 ret = i915_wait_request(dev, seqno);
1935         mutex_unlock(&dev->struct_mutex);
1936         return ret;
1937 }
1938
1939 int
1940 i915_gem_execbuffer(struct drm_device *dev, void *data,
1941                     struct drm_file *file_priv)
1942 {
1943         drm_i915_private_t *dev_priv = dev->dev_private;
1944         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1945         struct drm_i915_gem_execbuffer *args = data;
1946         struct drm_i915_gem_exec_object *exec_list = NULL;
1947         struct drm_gem_object **object_list = NULL;
1948         struct drm_gem_object *batch_obj;
1949         int ret, i, pinned = 0;
1950         uint64_t exec_offset;
1951         uint32_t seqno, flush_domains;
1952         int pin_tries;
1953
1954 #if WATCH_EXEC
1955         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
1956                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
1957 #endif
1958
1959         if (args->buffer_count < 1) {
1960                 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
1961                 return -EINVAL;
1962         }
1963         /* Copy in the exec list from userland */
1964         exec_list = drm_calloc(sizeof(*exec_list), args->buffer_count,
1965                                DRM_MEM_DRIVER);
1966         object_list = drm_calloc(sizeof(*object_list), args->buffer_count,
1967                                  DRM_MEM_DRIVER);
1968         if (exec_list == NULL || object_list == NULL) {
1969                 DRM_ERROR("Failed to allocate exec or object list "
1970                           "for %d buffers\n",
1971                           args->buffer_count);
1972                 ret = -ENOMEM;
1973                 goto pre_mutex_err;
1974         }
1975         ret = copy_from_user(exec_list,
1976                              (struct drm_i915_relocation_entry __user *)
1977                              (uintptr_t) args->buffers_ptr,
1978                              sizeof(*exec_list) * args->buffer_count);
1979         if (ret != 0) {
1980                 DRM_ERROR("copy %d exec entries failed %d\n",
1981                           args->buffer_count, ret);
1982                 goto pre_mutex_err;
1983         }
1984
1985         mutex_lock(&dev->struct_mutex);
1986
1987         i915_verify_inactive(dev, __FILE__, __LINE__);
1988
1989         if (dev_priv->mm.wedged) {
1990                 DRM_ERROR("Execbuf while wedged\n");
1991                 mutex_unlock(&dev->struct_mutex);
1992                 return -EIO;
1993         }
1994
1995         if (dev_priv->mm.suspended) {
1996                 DRM_ERROR("Execbuf while VT-switched.\n");
1997                 mutex_unlock(&dev->struct_mutex);
1998                 return -EBUSY;
1999         }
2000
2001         /* Look up object handles */
2002         for (i = 0; i < args->buffer_count; i++) {
2003                 object_list[i] = drm_gem_object_lookup(dev, file_priv,
2004                                                        exec_list[i].handle);
2005                 if (object_list[i] == NULL) {
2006                         DRM_ERROR("Invalid object handle %d at index %d\n",
2007                                    exec_list[i].handle, i);
2008                         ret = -EBADF;
2009                         goto err;
2010                 }
2011         }
2012
2013         /* Pin and relocate */
2014         for (pin_tries = 0; ; pin_tries++) {
2015                 ret = 0;
2016                 for (i = 0; i < args->buffer_count; i++) {
2017                         object_list[i]->pending_read_domains = 0;
2018                         object_list[i]->pending_write_domain = 0;
2019                         ret = i915_gem_object_pin_and_relocate(object_list[i],
2020                                                                file_priv,
2021                                                                &exec_list[i]);
2022                         if (ret)
2023                                 break;
2024                         pinned = i + 1;
2025                 }
2026                 /* success */
2027                 if (ret == 0)
2028                         break;
2029
2030                 /* error other than GTT full, or we've already tried again */
2031                 if (ret != -ENOMEM || pin_tries >= 1) {
2032                         DRM_ERROR("Failed to pin buffers %d\n", ret);
2033                         goto err;
2034                 }
2035
2036                 /* unpin all of our buffers */
2037                 for (i = 0; i < pinned; i++)
2038                         i915_gem_object_unpin(object_list[i]);
2039
2040                 /* evict everyone we can from the aperture */
2041                 ret = i915_gem_evict_everything(dev);
2042                 if (ret)
2043                         goto err;
2044         }
2045
2046         /* Set the pending read domains for the batch buffer to COMMAND */
2047         batch_obj = object_list[args->buffer_count-1];
2048         batch_obj->pending_read_domains = I915_GEM_DOMAIN_COMMAND;
2049         batch_obj->pending_write_domain = 0;
2050
2051         i915_verify_inactive(dev, __FILE__, __LINE__);
2052
2053         /* Zero the global flush/invalidate flags. These
2054          * will be modified as new domains are computed
2055          * for each object
2056          */
2057         dev->invalidate_domains = 0;
2058         dev->flush_domains = 0;
2059
2060         for (i = 0; i < args->buffer_count; i++) {
2061                 struct drm_gem_object *obj = object_list[i];
2062
2063                 /* Compute new gpu domains and update invalidate/flush */
2064                 i915_gem_object_set_to_gpu_domain(obj,
2065                                                   obj->pending_read_domains,
2066                                                   obj->pending_write_domain);
2067         }
2068
2069         i915_verify_inactive(dev, __FILE__, __LINE__);
2070
2071         if (dev->invalidate_domains | dev->flush_domains) {
2072 #if WATCH_EXEC
2073                 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
2074                           __func__,
2075                          dev->invalidate_domains,
2076                          dev->flush_domains);
2077 #endif
2078                 i915_gem_flush(dev,
2079                                dev->invalidate_domains,
2080                                dev->flush_domains);
2081                 if (dev->flush_domains)
2082                         (void)i915_add_request(dev, dev->flush_domains);
2083         }
2084
2085         i915_verify_inactive(dev, __FILE__, __LINE__);
2086
2087 #if WATCH_COHERENCY
2088         for (i = 0; i < args->buffer_count; i++) {
2089                 i915_gem_object_check_coherency(object_list[i],
2090                                                 exec_list[i].handle);
2091         }
2092 #endif
2093
2094         exec_offset = exec_list[args->buffer_count - 1].offset;
2095
2096 #if WATCH_EXEC
2097         i915_gem_dump_object(object_list[args->buffer_count - 1],
2098                               args->batch_len,
2099                               __func__,
2100                               ~0);
2101 #endif
2102
2103         /* Exec the batchbuffer */
2104         ret = i915_dispatch_gem_execbuffer(dev, args, exec_offset);
2105         if (ret) {
2106                 DRM_ERROR("dispatch failed %d\n", ret);
2107                 goto err;
2108         }
2109
2110         /*
2111          * Ensure that the commands in the batch buffer are
2112          * finished before the interrupt fires
2113          */
2114         flush_domains = i915_retire_commands(dev);
2115
2116         i915_verify_inactive(dev, __FILE__, __LINE__);
2117
2118         /*
2119          * Get a seqno representing the execution of the current buffer,
2120          * which we can wait on.  We would like to mitigate these interrupts,
2121          * likely by only creating seqnos occasionally (so that we have
2122          * *some* interrupts representing completion of buffers that we can
2123          * wait on when trying to clear up gtt space).
2124          */
2125         seqno = i915_add_request(dev, flush_domains);
2126         BUG_ON(seqno == 0);
2127         i915_file_priv->mm.last_gem_seqno = seqno;
2128         for (i = 0; i < args->buffer_count; i++) {
2129                 struct drm_gem_object *obj = object_list[i];
2130
2131                 i915_gem_object_move_to_active(obj, seqno);
2132 #if WATCH_LRU
2133                 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
2134 #endif
2135         }
2136 #if WATCH_LRU
2137         i915_dump_lru(dev, __func__);
2138 #endif
2139
2140         i915_verify_inactive(dev, __FILE__, __LINE__);
2141
2142         /* Copy the new buffer offsets back to the user's exec list. */
2143         ret = copy_to_user((struct drm_i915_relocation_entry __user *)
2144                            (uintptr_t) args->buffers_ptr,
2145                            exec_list,
2146                            sizeof(*exec_list) * args->buffer_count);
2147         if (ret)
2148                 DRM_ERROR("failed to copy %d exec entries "
2149                           "back to user (%d)\n",
2150                            args->buffer_count, ret);
2151 err:
2152         if (object_list != NULL) {
2153                 for (i = 0; i < pinned; i++)
2154                         i915_gem_object_unpin(object_list[i]);
2155
2156                 for (i = 0; i < args->buffer_count; i++)
2157                         drm_gem_object_unreference(object_list[i]);
2158         }
2159         mutex_unlock(&dev->struct_mutex);
2160
2161 pre_mutex_err:
2162         drm_free(object_list, sizeof(*object_list) * args->buffer_count,
2163                  DRM_MEM_DRIVER);
2164         drm_free(exec_list, sizeof(*exec_list) * args->buffer_count,
2165                  DRM_MEM_DRIVER);
2166
2167         return ret;
2168 }
2169
2170 int
2171 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
2172 {
2173         struct drm_device *dev = obj->dev;
2174         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2175         int ret;
2176
2177         i915_verify_inactive(dev, __FILE__, __LINE__);
2178         if (obj_priv->gtt_space == NULL) {
2179                 ret = i915_gem_object_bind_to_gtt(obj, alignment);
2180                 if (ret != 0) {
2181                         DRM_ERROR("Failure to bind: %d", ret);
2182                         return ret;
2183                 }
2184         }
2185         obj_priv->pin_count++;
2186
2187         /* If the object is not active and not pending a flush,
2188          * remove it from the inactive list
2189          */
2190         if (obj_priv->pin_count == 1) {
2191                 atomic_inc(&dev->pin_count);
2192                 atomic_add(obj->size, &dev->pin_memory);
2193                 if (!obj_priv->active &&
2194                     (obj->write_domain & ~(I915_GEM_DOMAIN_CPU |
2195                                            I915_GEM_DOMAIN_GTT)) == 0 &&
2196                     !list_empty(&obj_priv->list))
2197                         list_del_init(&obj_priv->list);
2198         }
2199         i915_verify_inactive(dev, __FILE__, __LINE__);
2200
2201         return 0;
2202 }
2203
2204 void
2205 i915_gem_object_unpin(struct drm_gem_object *obj)
2206 {
2207         struct drm_device *dev = obj->dev;
2208         drm_i915_private_t *dev_priv = dev->dev_private;
2209         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2210
2211         i915_verify_inactive(dev, __FILE__, __LINE__);
2212         obj_priv->pin_count--;
2213         BUG_ON(obj_priv->pin_count < 0);
2214         BUG_ON(obj_priv->gtt_space == NULL);
2215
2216         /* If the object is no longer pinned, and is
2217          * neither active nor being flushed, then stick it on
2218          * the inactive list
2219          */
2220         if (obj_priv->pin_count == 0) {
2221                 if (!obj_priv->active &&
2222                     (obj->write_domain & ~(I915_GEM_DOMAIN_CPU |
2223                                            I915_GEM_DOMAIN_GTT)) == 0)
2224                         list_move_tail(&obj_priv->list,
2225                                        &dev_priv->mm.inactive_list);
2226                 atomic_dec(&dev->pin_count);
2227                 atomic_sub(obj->size, &dev->pin_memory);
2228         }
2229         i915_verify_inactive(dev, __FILE__, __LINE__);
2230 }
2231
2232 int
2233 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2234                    struct drm_file *file_priv)
2235 {
2236         struct drm_i915_gem_pin *args = data;
2237         struct drm_gem_object *obj;
2238         struct drm_i915_gem_object *obj_priv;
2239         int ret;
2240
2241         mutex_lock(&dev->struct_mutex);
2242
2243         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2244         if (obj == NULL) {
2245                 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
2246                           args->handle);
2247                 mutex_unlock(&dev->struct_mutex);
2248                 return -EBADF;
2249         }
2250         obj_priv = obj->driver_private;
2251
2252         ret = i915_gem_object_pin(obj, args->alignment);
2253         if (ret != 0) {
2254                 drm_gem_object_unreference(obj);
2255                 mutex_unlock(&dev->struct_mutex);
2256                 return ret;
2257         }
2258
2259         /* XXX - flush the CPU caches for pinned objects
2260          * as the X server doesn't manage domains yet
2261          */
2262         i915_gem_object_flush_cpu_write_domain(obj);
2263         args->offset = obj_priv->gtt_offset;
2264         drm_gem_object_unreference(obj);
2265         mutex_unlock(&dev->struct_mutex);
2266
2267         return 0;
2268 }
2269
2270 int
2271 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2272                      struct drm_file *file_priv)
2273 {
2274         struct drm_i915_gem_pin *args = data;
2275         struct drm_gem_object *obj;
2276
2277         mutex_lock(&dev->struct_mutex);
2278
2279         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2280         if (obj == NULL) {
2281                 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
2282                           args->handle);
2283                 mutex_unlock(&dev->struct_mutex);
2284                 return -EBADF;
2285         }
2286
2287         i915_gem_object_unpin(obj);
2288
2289         drm_gem_object_unreference(obj);
2290         mutex_unlock(&dev->struct_mutex);
2291         return 0;
2292 }
2293
2294 int
2295 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2296                     struct drm_file *file_priv)
2297 {
2298         struct drm_i915_gem_busy *args = data;
2299         struct drm_gem_object *obj;
2300         struct drm_i915_gem_object *obj_priv;
2301
2302         mutex_lock(&dev->struct_mutex);
2303         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2304         if (obj == NULL) {
2305                 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
2306                           args->handle);
2307                 mutex_unlock(&dev->struct_mutex);
2308                 return -EBADF;
2309         }
2310
2311         obj_priv = obj->driver_private;
2312         /* Don't count being on the flushing list against the object being
2313          * done.  Otherwise, a buffer left on the flushing list but not getting
2314          * flushed (because nobody's flushing that domain) won't ever return
2315          * unbusy and get reused by libdrm's bo cache.  The other expected
2316          * consumer of this interface, OpenGL's occlusion queries, also specs
2317          * that the objects get unbusy "eventually" without any interference.
2318          */
2319         args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
2320
2321         drm_gem_object_unreference(obj);
2322         mutex_unlock(&dev->struct_mutex);
2323         return 0;
2324 }
2325
2326 int
2327 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2328                         struct drm_file *file_priv)
2329 {
2330     return i915_gem_ring_throttle(dev, file_priv);
2331 }
2332
2333 int i915_gem_init_object(struct drm_gem_object *obj)
2334 {
2335         struct drm_i915_gem_object *obj_priv;
2336
2337         obj_priv = drm_calloc(1, sizeof(*obj_priv), DRM_MEM_DRIVER);
2338         if (obj_priv == NULL)
2339                 return -ENOMEM;
2340
2341         /*
2342          * We've just allocated pages from the kernel,
2343          * so they've just been written by the CPU with
2344          * zeros. They'll need to be clflushed before we
2345          * use them with the GPU.
2346          */
2347         obj->write_domain = I915_GEM_DOMAIN_CPU;
2348         obj->read_domains = I915_GEM_DOMAIN_CPU;
2349
2350         obj_priv->agp_type = AGP_USER_MEMORY;
2351
2352         obj->driver_private = obj_priv;
2353         obj_priv->obj = obj;
2354         INIT_LIST_HEAD(&obj_priv->list);
2355         return 0;
2356 }
2357
2358 void i915_gem_free_object(struct drm_gem_object *obj)
2359 {
2360         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2361
2362         while (obj_priv->pin_count > 0)
2363                 i915_gem_object_unpin(obj);
2364
2365         i915_gem_object_unbind(obj);
2366
2367         drm_free(obj_priv->page_cpu_valid, 1, DRM_MEM_DRIVER);
2368         drm_free(obj->driver_private, 1, DRM_MEM_DRIVER);
2369 }
2370
2371 /** Unbinds all objects that are on the given buffer list. */
2372 static int
2373 i915_gem_evict_from_list(struct drm_device *dev, struct list_head *head)
2374 {
2375         struct drm_gem_object *obj;
2376         struct drm_i915_gem_object *obj_priv;
2377         int ret;
2378
2379         while (!list_empty(head)) {
2380                 obj_priv = list_first_entry(head,
2381                                             struct drm_i915_gem_object,
2382                                             list);
2383                 obj = obj_priv->obj;
2384
2385                 if (obj_priv->pin_count != 0) {
2386                         DRM_ERROR("Pinned object in unbind list\n");
2387                         mutex_unlock(&dev->struct_mutex);
2388                         return -EINVAL;
2389                 }
2390
2391                 ret = i915_gem_object_unbind(obj);
2392                 if (ret != 0) {
2393                         DRM_ERROR("Error unbinding object in LeaveVT: %d\n",
2394                                   ret);
2395                         mutex_unlock(&dev->struct_mutex);
2396                         return ret;
2397                 }
2398         }
2399
2400
2401         return 0;
2402 }
2403
2404 static int
2405 i915_gem_idle(struct drm_device *dev)
2406 {
2407         drm_i915_private_t *dev_priv = dev->dev_private;
2408         uint32_t seqno, cur_seqno, last_seqno;
2409         int stuck, ret;
2410
2411         mutex_lock(&dev->struct_mutex);
2412
2413         if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
2414                 mutex_unlock(&dev->struct_mutex);
2415                 return 0;
2416         }
2417
2418         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
2419          * We need to replace this with a semaphore, or something.
2420          */
2421         dev_priv->mm.suspended = 1;
2422
2423         /* Cancel the retire work handler, wait for it to finish if running
2424          */
2425         mutex_unlock(&dev->struct_mutex);
2426         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
2427         mutex_lock(&dev->struct_mutex);
2428
2429         i915_kernel_lost_context(dev);
2430
2431         /* Flush the GPU along with all non-CPU write domains
2432          */
2433         i915_gem_flush(dev, ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT),
2434                        ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
2435         seqno = i915_add_request(dev, ~(I915_GEM_DOMAIN_CPU |
2436                                         I915_GEM_DOMAIN_GTT));
2437
2438         if (seqno == 0) {
2439                 mutex_unlock(&dev->struct_mutex);
2440                 return -ENOMEM;
2441         }
2442
2443         dev_priv->mm.waiting_gem_seqno = seqno;
2444         last_seqno = 0;
2445         stuck = 0;
2446         for (;;) {
2447                 cur_seqno = i915_get_gem_seqno(dev);
2448                 if (i915_seqno_passed(cur_seqno, seqno))
2449                         break;
2450                 if (last_seqno == cur_seqno) {
2451                         if (stuck++ > 100) {
2452                                 DRM_ERROR("hardware wedged\n");
2453                                 dev_priv->mm.wedged = 1;
2454                                 DRM_WAKEUP(&dev_priv->irq_queue);
2455                                 break;
2456                         }
2457                 }
2458                 msleep(10);
2459                 last_seqno = cur_seqno;
2460         }
2461         dev_priv->mm.waiting_gem_seqno = 0;
2462
2463         i915_gem_retire_requests(dev);
2464
2465         if (!dev_priv->mm.wedged) {
2466                 /* Active and flushing should now be empty as we've
2467                  * waited for a sequence higher than any pending execbuffer
2468                  */
2469                 WARN_ON(!list_empty(&dev_priv->mm.active_list));
2470                 WARN_ON(!list_empty(&dev_priv->mm.flushing_list));
2471                 /* Request should now be empty as we've also waited
2472                  * for the last request in the list
2473                  */
2474                 WARN_ON(!list_empty(&dev_priv->mm.request_list));
2475         }
2476
2477         /* Empty the active and flushing lists to inactive.  If there's
2478          * anything left at this point, it means that we're wedged and
2479          * nothing good's going to happen by leaving them there.  So strip
2480          * the GPU domains and just stuff them onto inactive.
2481          */
2482         while (!list_empty(&dev_priv->mm.active_list)) {
2483                 struct drm_i915_gem_object *obj_priv;
2484
2485                 obj_priv = list_first_entry(&dev_priv->mm.active_list,
2486                                             struct drm_i915_gem_object,
2487                                             list);
2488                 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
2489                 i915_gem_object_move_to_inactive(obj_priv->obj);
2490         }
2491
2492         while (!list_empty(&dev_priv->mm.flushing_list)) {
2493                 struct drm_i915_gem_object *obj_priv;
2494
2495                 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
2496                                             struct drm_i915_gem_object,
2497                                             list);
2498                 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
2499                 i915_gem_object_move_to_inactive(obj_priv->obj);
2500         }
2501
2502
2503         /* Move all inactive buffers out of the GTT. */
2504         ret = i915_gem_evict_from_list(dev, &dev_priv->mm.inactive_list);
2505         WARN_ON(!list_empty(&dev_priv->mm.inactive_list));
2506         if (ret) {
2507                 mutex_unlock(&dev->struct_mutex);
2508                 return ret;
2509         }
2510
2511         i915_gem_cleanup_ringbuffer(dev);
2512         mutex_unlock(&dev->struct_mutex);
2513
2514         return 0;
2515 }
2516
2517 static int
2518 i915_gem_init_hws(struct drm_device *dev)
2519 {
2520         drm_i915_private_t *dev_priv = dev->dev_private;
2521         struct drm_gem_object *obj;
2522         struct drm_i915_gem_object *obj_priv;
2523         int ret;
2524
2525         /* If we need a physical address for the status page, it's already
2526          * initialized at driver load time.
2527          */
2528         if (!I915_NEED_GFX_HWS(dev))
2529                 return 0;
2530
2531         obj = drm_gem_object_alloc(dev, 4096);
2532         if (obj == NULL) {
2533                 DRM_ERROR("Failed to allocate status page\n");
2534                 return -ENOMEM;
2535         }
2536         obj_priv = obj->driver_private;
2537         obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
2538
2539         ret = i915_gem_object_pin(obj, 4096);
2540         if (ret != 0) {
2541                 drm_gem_object_unreference(obj);
2542                 return ret;
2543         }
2544
2545         dev_priv->status_gfx_addr = obj_priv->gtt_offset;
2546
2547         dev_priv->hw_status_page = kmap(obj_priv->page_list[0]);
2548         if (dev_priv->hw_status_page == NULL) {
2549                 DRM_ERROR("Failed to map status page.\n");
2550                 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
2551                 drm_gem_object_unreference(obj);
2552                 return -EINVAL;
2553         }
2554         dev_priv->hws_obj = obj;
2555         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
2556         I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
2557         I915_READ(HWS_PGA); /* posting read */
2558         DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
2559
2560         return 0;
2561 }
2562
2563 static int
2564 i915_gem_init_ringbuffer(struct drm_device *dev)
2565 {
2566         drm_i915_private_t *dev_priv = dev->dev_private;
2567         struct drm_gem_object *obj;
2568         struct drm_i915_gem_object *obj_priv;
2569         int ret;
2570         u32 head;
2571
2572         ret = i915_gem_init_hws(dev);
2573         if (ret != 0)
2574                 return ret;
2575
2576         obj = drm_gem_object_alloc(dev, 128 * 1024);
2577         if (obj == NULL) {
2578                 DRM_ERROR("Failed to allocate ringbuffer\n");
2579                 return -ENOMEM;
2580         }
2581         obj_priv = obj->driver_private;
2582
2583         ret = i915_gem_object_pin(obj, 4096);
2584         if (ret != 0) {
2585                 drm_gem_object_unreference(obj);
2586                 return ret;
2587         }
2588
2589         /* Set up the kernel mapping for the ring. */
2590         dev_priv->ring.Size = obj->size;
2591         dev_priv->ring.tail_mask = obj->size - 1;
2592
2593         dev_priv->ring.map.offset = dev->agp->base + obj_priv->gtt_offset;
2594         dev_priv->ring.map.size = obj->size;
2595         dev_priv->ring.map.type = 0;
2596         dev_priv->ring.map.flags = 0;
2597         dev_priv->ring.map.mtrr = 0;
2598
2599         drm_core_ioremap_wc(&dev_priv->ring.map, dev);
2600         if (dev_priv->ring.map.handle == NULL) {
2601                 DRM_ERROR("Failed to map ringbuffer.\n");
2602                 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
2603                 drm_gem_object_unreference(obj);
2604                 return -EINVAL;
2605         }
2606         dev_priv->ring.ring_obj = obj;
2607         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
2608
2609         /* Stop the ring if it's running. */
2610         I915_WRITE(PRB0_CTL, 0);
2611         I915_WRITE(PRB0_TAIL, 0);
2612         I915_WRITE(PRB0_HEAD, 0);
2613
2614         /* Initialize the ring. */
2615         I915_WRITE(PRB0_START, obj_priv->gtt_offset);
2616         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
2617
2618         /* G45 ring initialization fails to reset head to zero */
2619         if (head != 0) {
2620                 DRM_ERROR("Ring head not reset to zero "
2621                           "ctl %08x head %08x tail %08x start %08x\n",
2622                           I915_READ(PRB0_CTL),
2623                           I915_READ(PRB0_HEAD),
2624                           I915_READ(PRB0_TAIL),
2625                           I915_READ(PRB0_START));
2626                 I915_WRITE(PRB0_HEAD, 0);
2627
2628                 DRM_ERROR("Ring head forced to zero "
2629                           "ctl %08x head %08x tail %08x start %08x\n",
2630                           I915_READ(PRB0_CTL),
2631                           I915_READ(PRB0_HEAD),
2632                           I915_READ(PRB0_TAIL),
2633                           I915_READ(PRB0_START));
2634         }
2635
2636         I915_WRITE(PRB0_CTL,
2637                    ((obj->size - 4096) & RING_NR_PAGES) |
2638                    RING_NO_REPORT |
2639                    RING_VALID);
2640
2641         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
2642
2643         /* If the head is still not zero, the ring is dead */
2644         if (head != 0) {
2645                 DRM_ERROR("Ring initialization failed "
2646                           "ctl %08x head %08x tail %08x start %08x\n",
2647                           I915_READ(PRB0_CTL),
2648                           I915_READ(PRB0_HEAD),
2649                           I915_READ(PRB0_TAIL),
2650                           I915_READ(PRB0_START));
2651                 return -EIO;
2652         }
2653
2654         /* Update our cache of the ring state */
2655         i915_kernel_lost_context(dev);
2656
2657         return 0;
2658 }
2659
2660 static void
2661 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
2662 {
2663         drm_i915_private_t *dev_priv = dev->dev_private;
2664
2665         if (dev_priv->ring.ring_obj == NULL)
2666                 return;
2667
2668         drm_core_ioremapfree(&dev_priv->ring.map, dev);
2669
2670         i915_gem_object_unpin(dev_priv->ring.ring_obj);
2671         drm_gem_object_unreference(dev_priv->ring.ring_obj);
2672         dev_priv->ring.ring_obj = NULL;
2673         memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
2674
2675         if (dev_priv->hws_obj != NULL) {
2676                 struct drm_gem_object *obj = dev_priv->hws_obj;
2677                 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2678
2679                 kunmap(obj_priv->page_list[0]);
2680                 i915_gem_object_unpin(obj);
2681                 drm_gem_object_unreference(obj);
2682                 dev_priv->hws_obj = NULL;
2683                 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
2684                 dev_priv->hw_status_page = NULL;
2685
2686                 /* Write high address into HWS_PGA when disabling. */
2687                 I915_WRITE(HWS_PGA, 0x1ffff000);
2688         }
2689 }
2690
2691 int
2692 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
2693                        struct drm_file *file_priv)
2694 {
2695         drm_i915_private_t *dev_priv = dev->dev_private;
2696         int ret;
2697
2698         if (dev_priv->mm.wedged) {
2699                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
2700                 dev_priv->mm.wedged = 0;
2701         }
2702
2703         ret = i915_gem_init_ringbuffer(dev);
2704         if (ret != 0)
2705                 return ret;
2706
2707         dev_priv->mm.gtt_mapping = io_mapping_create_wc(dev->agp->base,
2708                                                         dev->agp->agp_info.aper_size
2709                                                         * 1024 * 1024);
2710
2711         mutex_lock(&dev->struct_mutex);
2712         BUG_ON(!list_empty(&dev_priv->mm.active_list));
2713         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2714         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
2715         BUG_ON(!list_empty(&dev_priv->mm.request_list));
2716         dev_priv->mm.suspended = 0;
2717         mutex_unlock(&dev->struct_mutex);
2718
2719         drm_irq_install(dev);
2720
2721         return 0;
2722 }
2723
2724 int
2725 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
2726                        struct drm_file *file_priv)
2727 {
2728         drm_i915_private_t *dev_priv = dev->dev_private;
2729         int ret;
2730
2731         ret = i915_gem_idle(dev);
2732         drm_irq_uninstall(dev);
2733
2734         io_mapping_free(dev_priv->mm.gtt_mapping);
2735         return ret;
2736 }
2737
2738 void
2739 i915_gem_lastclose(struct drm_device *dev)
2740 {
2741         int ret;
2742
2743         ret = i915_gem_idle(dev);
2744         if (ret)
2745                 DRM_ERROR("failed to idle hardware: %d\n", ret);
2746 }
2747
2748 void
2749 i915_gem_load(struct drm_device *dev)
2750 {
2751         drm_i915_private_t *dev_priv = dev->dev_private;
2752
2753         INIT_LIST_HEAD(&dev_priv->mm.active_list);
2754         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
2755         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
2756         INIT_LIST_HEAD(&dev_priv->mm.request_list);
2757         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
2758                           i915_gem_retire_work_handler);
2759         dev_priv->mm.next_gem_seqno = 1;
2760
2761         i915_gem_detect_bit_6_swizzle(dev);
2762 }