i915: Use more consistent names for regs, and store them in a separate file.
[linux-3.10.git] / drivers / gpu / drm / i915 / i915_drv.h
1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2  */
3 /*
4  *
5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6  * All Rights Reserved.
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a
9  * copy of this software and associated documentation files (the
10  * "Software"), to deal in the Software without restriction, including
11  * without limitation the rights to use, copy, modify, merge, publish,
12  * distribute, sub license, and/or sell copies of the Software, and to
13  * permit persons to whom the Software is furnished to do so, subject to
14  * the following conditions:
15  *
16  * The above copyright notice and this permission notice (including the
17  * next paragraph) shall be included in all copies or substantial portions
18  * of the Software.
19  *
20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27  *
28  */
29
30 #ifndef _I915_DRV_H_
31 #define _I915_DRV_H_
32
33 #include "i915_reg.h"
34
35 /* General customization:
36  */
37
38 #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
39
40 #define DRIVER_NAME             "i915"
41 #define DRIVER_DESC             "Intel Graphics"
42 #define DRIVER_DATE             "20060119"
43
44 /* Interface history:
45  *
46  * 1.1: Original.
47  * 1.2: Add Power Management
48  * 1.3: Add vblank support
49  * 1.4: Fix cmdbuffer path, add heap destroy
50  * 1.5: Add vblank pipe configuration
51  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
52  *      - Support vertical blank on secondary display pipe
53  */
54 #define DRIVER_MAJOR            1
55 #define DRIVER_MINOR            6
56 #define DRIVER_PATCHLEVEL       0
57
58 typedef struct _drm_i915_ring_buffer {
59         int tail_mask;
60         unsigned long Start;
61         unsigned long End;
62         unsigned long Size;
63         u8 *virtual_start;
64         int head;
65         int tail;
66         int space;
67         drm_local_map_t map;
68 } drm_i915_ring_buffer_t;
69
70 struct mem_block {
71         struct mem_block *next;
72         struct mem_block *prev;
73         int start;
74         int size;
75         struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
76 };
77
78 typedef struct _drm_i915_vbl_swap {
79         struct list_head head;
80         drm_drawable_t drw_id;
81         unsigned int pipe;
82         unsigned int sequence;
83 } drm_i915_vbl_swap_t;
84
85 typedef struct drm_i915_private {
86         drm_local_map_t *sarea;
87         drm_local_map_t *mmio_map;
88
89         drm_i915_sarea_t *sarea_priv;
90         drm_i915_ring_buffer_t ring;
91
92         drm_dma_handle_t *status_page_dmah;
93         void *hw_status_page;
94         dma_addr_t dma_status_page;
95         unsigned long counter;
96         unsigned int status_gfx_addr;
97         drm_local_map_t hws_map;
98
99         unsigned int cpp;
100         int back_offset;
101         int front_offset;
102         int current_page;
103         int page_flipping;
104
105         wait_queue_head_t irq_queue;
106         atomic_t irq_received;
107         atomic_t irq_emitted;
108
109         int tex_lru_log_granularity;
110         int allow_batchbuffer;
111         struct mem_block *agp_heap;
112         unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
113         int vblank_pipe;
114
115         spinlock_t swaps_lock;
116         drm_i915_vbl_swap_t vbl_swaps;
117         unsigned int swaps_pending;
118
119         /* Register state */
120         u8 saveLBB;
121         u32 saveDSPACNTR;
122         u32 saveDSPBCNTR;
123         u32 saveDSPARB;
124         u32 savePIPEACONF;
125         u32 savePIPEBCONF;
126         u32 savePIPEASRC;
127         u32 savePIPEBSRC;
128         u32 saveFPA0;
129         u32 saveFPA1;
130         u32 saveDPLL_A;
131         u32 saveDPLL_A_MD;
132         u32 saveHTOTAL_A;
133         u32 saveHBLANK_A;
134         u32 saveHSYNC_A;
135         u32 saveVTOTAL_A;
136         u32 saveVBLANK_A;
137         u32 saveVSYNC_A;
138         u32 saveBCLRPAT_A;
139         u32 savePIPEASTAT;
140         u32 saveDSPASTRIDE;
141         u32 saveDSPASIZE;
142         u32 saveDSPAPOS;
143         u32 saveDSPAADDR;
144         u32 saveDSPASURF;
145         u32 saveDSPATILEOFF;
146         u32 savePFIT_PGM_RATIOS;
147         u32 saveBLC_PWM_CTL;
148         u32 saveBLC_PWM_CTL2;
149         u32 saveFPB0;
150         u32 saveFPB1;
151         u32 saveDPLL_B;
152         u32 saveDPLL_B_MD;
153         u32 saveHTOTAL_B;
154         u32 saveHBLANK_B;
155         u32 saveHSYNC_B;
156         u32 saveVTOTAL_B;
157         u32 saveVBLANK_B;
158         u32 saveVSYNC_B;
159         u32 saveBCLRPAT_B;
160         u32 savePIPEBSTAT;
161         u32 saveDSPBSTRIDE;
162         u32 saveDSPBSIZE;
163         u32 saveDSPBPOS;
164         u32 saveDSPBADDR;
165         u32 saveDSPBSURF;
166         u32 saveDSPBTILEOFF;
167         u32 saveVGA0;
168         u32 saveVGA1;
169         u32 saveVGA_PD;
170         u32 saveVGACNTRL;
171         u32 saveADPA;
172         u32 saveLVDS;
173         u32 savePP_ON_DELAYS;
174         u32 savePP_OFF_DELAYS;
175         u32 saveDVOA;
176         u32 saveDVOB;
177         u32 saveDVOC;
178         u32 savePP_ON;
179         u32 savePP_OFF;
180         u32 savePP_CONTROL;
181         u32 savePP_DIVISOR;
182         u32 savePFIT_CONTROL;
183         u32 save_palette_a[256];
184         u32 save_palette_b[256];
185         u32 saveFBC_CFB_BASE;
186         u32 saveFBC_LL_BASE;
187         u32 saveFBC_CONTROL;
188         u32 saveFBC_CONTROL2;
189         u32 saveIER;
190         u32 saveIIR;
191         u32 saveIMR;
192         u32 saveCACHE_MODE_0;
193         u32 saveD_STATE;
194         u32 saveCG_2D_DIS;
195         u32 saveMI_ARB_STATE;
196         u32 saveSWF0[16];
197         u32 saveSWF1[16];
198         u32 saveSWF2[3];
199         u8 saveMSR;
200         u8 saveSR[8];
201         u8 saveGR[25];
202         u8 saveAR_INDEX;
203         u8 saveAR[21];
204         u8 saveDACMASK;
205         u8 saveDACDATA[256*3]; /* 256 3-byte colors */
206         u8 saveCR[37];
207 } drm_i915_private_t;
208
209 extern struct drm_ioctl_desc i915_ioctls[];
210 extern int i915_max_ioctl;
211
212                                 /* i915_dma.c */
213 extern void i915_kernel_lost_context(struct drm_device * dev);
214 extern int i915_driver_load(struct drm_device *, unsigned long flags);
215 extern int i915_driver_unload(struct drm_device *);
216 extern void i915_driver_lastclose(struct drm_device * dev);
217 extern void i915_driver_preclose(struct drm_device *dev,
218                                  struct drm_file *file_priv);
219 extern int i915_driver_device_is_agp(struct drm_device * dev);
220 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
221                               unsigned long arg);
222
223 /* i915_irq.c */
224 extern int i915_irq_emit(struct drm_device *dev, void *data,
225                          struct drm_file *file_priv);
226 extern int i915_irq_wait(struct drm_device *dev, void *data,
227                          struct drm_file *file_priv);
228
229 extern int i915_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence);
230 extern int i915_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
231 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
232 extern void i915_driver_irq_preinstall(struct drm_device * dev);
233 extern void i915_driver_irq_postinstall(struct drm_device * dev);
234 extern void i915_driver_irq_uninstall(struct drm_device * dev);
235 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
236                                 struct drm_file *file_priv);
237 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
238                                 struct drm_file *file_priv);
239 extern int i915_vblank_swap(struct drm_device *dev, void *data,
240                             struct drm_file *file_priv);
241
242 /* i915_mem.c */
243 extern int i915_mem_alloc(struct drm_device *dev, void *data,
244                           struct drm_file *file_priv);
245 extern int i915_mem_free(struct drm_device *dev, void *data,
246                          struct drm_file *file_priv);
247 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
248                               struct drm_file *file_priv);
249 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
250                                  struct drm_file *file_priv);
251 extern void i915_mem_takedown(struct mem_block **heap);
252 extern void i915_mem_release(struct drm_device * dev,
253                              struct drm_file *file_priv, struct mem_block *heap);
254
255 #define I915_READ(reg)          DRM_READ32(dev_priv->mmio_map, (reg))
256 #define I915_WRITE(reg,val)     DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
257 #define I915_READ16(reg)        DRM_READ16(dev_priv->mmio_map, (reg))
258 #define I915_WRITE16(reg,val)   DRM_WRITE16(dev_priv->mmio_map, (reg), (val))
259
260 #define I915_VERBOSE 0
261
262 #define RING_LOCALS     unsigned int outring, ringmask, outcount; \
263                         volatile char *virt;
264
265 #define BEGIN_LP_RING(n) do {                           \
266         if (I915_VERBOSE)                               \
267                 DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n));  \
268         if (dev_priv->ring.space < (n)*4)               \
269                 i915_wait_ring(dev, (n)*4, __func__);           \
270         outcount = 0;                                   \
271         outring = dev_priv->ring.tail;                  \
272         ringmask = dev_priv->ring.tail_mask;            \
273         virt = dev_priv->ring.virtual_start;            \
274 } while (0)
275
276 #define OUT_RING(n) do {                                        \
277         if (I915_VERBOSE) DRM_DEBUG("   OUT_RING %x\n", (int)(n));      \
278         *(volatile unsigned int *)(virt + outring) = (n);       \
279         outcount++;                                             \
280         outring += 4;                                           \
281         outring &= ringmask;                                    \
282 } while (0)
283
284 #define ADVANCE_LP_RING() do {                                          \
285         if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring);   \
286         dev_priv->ring.tail = outring;                                  \
287         dev_priv->ring.space -= outcount * 4;                           \
288         I915_WRITE(PRB0_TAIL, outring);                 \
289 } while(0)
290
291 /**
292  * Reads a dword out of the status page, which is written to from the command
293  * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
294  * MI_STORE_DATA_IMM.
295  *
296  * The following dwords have a reserved meaning:
297  * 0: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
298  * 4: ring 0 head pointer
299  * 5: ring 1 head pointer (915-class)
300  * 6: ring 2 head pointer (915-class)
301  *
302  * The area from dword 0x10 to 0x3ff is available for driver usage.
303  */
304 #define READ_HWSP(dev_priv, reg)  (((volatile u32*)(dev_priv->hw_status_page))[reg])
305 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, 5)
306
307 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
308
309 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
310 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
311 #define IS_I85X(dev) ((dev)->pci_device == 0x3582)
312 #define IS_I855(dev) ((dev)->pci_device == 0x3582)
313 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
314
315 #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
316 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
317 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
318 #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
319                         (dev)->pci_device == 0x27AE)
320 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
321                        (dev)->pci_device == 0x2982 || \
322                        (dev)->pci_device == 0x2992 || \
323                        (dev)->pci_device == 0x29A2 || \
324                        (dev)->pci_device == 0x2A02 || \
325                        (dev)->pci_device == 0x2A12 || \
326                        (dev)->pci_device == 0x2A42 || \
327                        (dev)->pci_device == 0x2E02 || \
328                        (dev)->pci_device == 0x2E12 || \
329                        (dev)->pci_device == 0x2E22)
330
331 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
332
333 #define IS_IGD_GM(dev) ((dev)->pci_device == 0x2A42)
334
335 #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
336                      (dev)->pci_device == 0x2E12 || \
337                      (dev)->pci_device == 0x2E22)
338
339 #define IS_G33(dev)    ((dev)->pci_device == 0x29C2 ||  \
340                         (dev)->pci_device == 0x29B2 ||  \
341                         (dev)->pci_device == 0x29D2)
342
343 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
344                       IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev))
345
346 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
347                         IS_I945GM(dev) || IS_I965GM(dev) || IS_IGD_GM(dev))
348
349 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_IGD_GM(dev) || IS_G4X(dev))
350
351 #define PRIMARY_RINGBUFFER_SIZE         (128*1024)
352
353 #endif