edac: mpc85xx fix pci ofdev 2nd pass
[linux-3.10.git] / drivers / edac / r82600_edac.c
1 /*
2  * Radisys 82600 Embedded chipset Memory Controller kernel module
3  * (C) 2005 EADS Astrium
4  * This file may be distributed under the terms of the
5  * GNU General Public License.
6  *
7  * Written by Tim Small <tim@buttersideup.com>, based on work by Thayne
8  * Harbaugh, Dan Hollis <goemon at anime dot net> and others.
9  *
10  * $Id: edac_r82600.c,v 1.1.2.6 2005/10/05 00:43:44 dsp_llnl Exp $
11  *
12  * Written with reference to 82600 High Integration Dual PCI System
13  * Controller Data Book:
14  * www.radisys.com/files/support_downloads/007-01277-0002.82600DataBook.pdf
15  * references to this document given in []
16  */
17
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/pci.h>
21 #include <linux/pci_ids.h>
22 #include <linux/slab.h>
23 #include <linux/edac.h>
24 #include "edac_core.h"
25
26 #define R82600_REVISION " Ver: 2.0.2 " __DATE__
27 #define EDAC_MOD_STR    "r82600_edac"
28
29 #define r82600_printk(level, fmt, arg...) \
30         edac_printk(level, "r82600", fmt, ##arg)
31
32 #define r82600_mc_printk(mci, level, fmt, arg...) \
33         edac_mc_chipset_printk(mci, level, "r82600", fmt, ##arg)
34
35 /* Radisys say "The 82600 integrates a main memory SDRAM controller that
36  * supports up to four banks of memory. The four banks can support a mix of
37  * sizes of 64 bit wide (72 bits with ECC) Synchronous DRAM (SDRAM) DIMMs,
38  * each of which can be any size from 16MB to 512MB. Both registered (control
39  * signals buffered) and unbuffered DIMM types are supported. Mixing of
40  * registered and unbuffered DIMMs as well as mixing of ECC and non-ECC DIMMs
41  * is not allowed. The 82600 SDRAM interface operates at the same frequency as
42  * the CPU bus, 66MHz, 100MHz or 133MHz."
43  */
44
45 #define R82600_NR_CSROWS 4
46 #define R82600_NR_CHANS  1
47 #define R82600_NR_DIMMS  4
48
49 #define R82600_BRIDGE_ID  0x8200
50
51 /* Radisys 82600 register addresses - device 0 function 0 - PCI bridge */
52 #define R82600_DRAMC    0x57    /* Various SDRAM related control bits
53                                  * all bits are R/W
54                                  *
55                                  * 7    SDRAM ISA Hole Enable
56                                  * 6    Flash Page Mode Enable
57                                  * 5    ECC Enable: 1=ECC 0=noECC
58                                  * 4    DRAM DIMM Type: 1=
59                                  * 3    BIOS Alias Disable
60                                  * 2    SDRAM BIOS Flash Write Enable
61                                  * 1:0  SDRAM Refresh Rate: 00=Disabled
62                                  *          01=7.8usec (256Mbit SDRAMs)
63                                  *          10=15.6us 11=125usec
64                                  */
65
66 #define R82600_SDRAMC   0x76    /* "SDRAM Control Register"
67                                  * More SDRAM related control bits
68                                  * all bits are R/W
69                                  *
70                                  * 15:8 Reserved.
71                                  *
72                                  * 7:5  Special SDRAM Mode Select
73                                  *
74                                  * 4    Force ECC
75                                  *
76                                  *        1=Drive ECC bits to 0 during
77                                  *          write cycles (i.e. ECC test mode)
78                                  *
79                                  *        0=Normal ECC functioning
80                                  *
81                                  * 3    Enhanced Paging Enable
82                                  *
83                                  * 2    CAS# Latency 0=3clks 1=2clks
84                                  *
85                                  * 1    RAS# to CAS# Delay 0=3 1=2
86                                  *
87                                  * 0    RAS# Precharge     0=3 1=2
88                                  */
89
90 #define R82600_EAP      0x80    /* ECC Error Address Pointer Register
91                                  *
92                                  * 31    Disable Hardware Scrubbing (RW)
93                                  *        0=Scrub on corrected read
94                                  *        1=Don't scrub on corrected read
95                                  *
96                                  * 30:12 Error Address Pointer (RO)
97                                  *        Upper 19 bits of error address
98                                  *
99                                  * 11:4  Syndrome Bits (RO)
100                                  *
101                                  * 3     BSERR# on multibit error (RW)
102                                  *        1=enable 0=disable
103                                  *
104                                  * 2     NMI on Single Bit Eror (RW)
105                                  *        1=NMI triggered by SBE n.b. other
106                                  *          prerequeists
107                                  *        0=NMI not triggered
108                                  *
109                                  * 1     MBE (R/WC)
110                                  *        read 1=MBE at EAP (see above)
111                                  *        read 0=no MBE, or SBE occurred first
112                                  *        write 1=Clear MBE status (must also
113                                  *          clear SBE)
114                                  *        write 0=NOP
115                                  *
116                                  * 1     SBE (R/WC)
117                                  *        read 1=SBE at EAP (see above)
118                                  *        read 0=no SBE, or MBE occurred first
119                                  *        write 1=Clear SBE status (must also
120                                  *          clear MBE)
121                                  *        write 0=NOP
122                                  */
123
124 #define R82600_DRBA     0x60    /* + 0x60..0x63 SDRAM Row Boundry Address
125                                  *  Registers
126                                  *
127                                  * 7:0  Address lines 30:24 - upper limit of
128                                  * each row [p57]
129                                  */
130
131 struct r82600_error_info {
132         u32 eapr;
133 };
134
135 static unsigned int disable_hardware_scrub;
136
137 static struct edac_pci_ctl_info *r82600_pci;
138
139 static void r82600_get_error_info(struct mem_ctl_info *mci,
140                                 struct r82600_error_info *info)
141 {
142         struct pci_dev *pdev;
143
144         pdev = to_pci_dev(mci->dev);
145         pci_read_config_dword(pdev, R82600_EAP, &info->eapr);
146
147         if (info->eapr & BIT(0))
148                 /* Clear error to allow next error to be reported [p.62] */
149                 pci_write_bits32(pdev, R82600_EAP,
150                                  ((u32) BIT(0) & (u32) BIT(1)),
151                                  ((u32) BIT(0) & (u32) BIT(1)));
152
153         if (info->eapr & BIT(1))
154                 /* Clear error to allow next error to be reported [p.62] */
155                 pci_write_bits32(pdev, R82600_EAP,
156                                  ((u32) BIT(0) & (u32) BIT(1)),
157                                  ((u32) BIT(0) & (u32) BIT(1)));
158 }
159
160 static int r82600_process_error_info(struct mem_ctl_info *mci,
161                                 struct r82600_error_info *info,
162                                 int handle_errors)
163 {
164         int error_found;
165         u32 eapaddr, page;
166         u32 syndrome;
167
168         error_found = 0;
169
170         /* bits 30:12 store the upper 19 bits of the 32 bit error address */
171         eapaddr = ((info->eapr >> 12) & 0x7FFF) << 13;
172         /* Syndrome in bits 11:4 [p.62]       */
173         syndrome = (info->eapr >> 4) & 0xFF;
174
175         /* the R82600 reports at less than page *
176          * granularity (upper 19 bits only)     */
177         page = eapaddr >> PAGE_SHIFT;
178
179         if (info->eapr & BIT(0)) {      /* CE? */
180                 error_found = 1;
181
182                 if (handle_errors)
183                         edac_mc_handle_ce(mci, page, 0, /* not avail */
184                                         syndrome,
185                                         edac_mc_find_csrow_by_page(mci, page),
186                                         0, mci->ctl_name);
187         }
188
189         if (info->eapr & BIT(1)) {      /* UE? */
190                 error_found = 1;
191
192                 if (handle_errors)
193                         /* 82600 doesn't give enough info */
194                         edac_mc_handle_ue(mci, page, 0,
195                                         edac_mc_find_csrow_by_page(mci, page),
196                                         mci->ctl_name);
197         }
198
199         return error_found;
200 }
201
202 static void r82600_check(struct mem_ctl_info *mci)
203 {
204         struct r82600_error_info info;
205
206         debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
207         r82600_get_error_info(mci, &info);
208         r82600_process_error_info(mci, &info, 1);
209 }
210
211 static inline int ecc_enabled(u8 dramcr)
212 {
213         return dramcr & BIT(5);
214 }
215
216 static void r82600_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
217                         u8 dramcr)
218 {
219         struct csrow_info *csrow;
220         int index;
221         u8 drbar;               /* SDRAM Row Boundry Address Register */
222         u32 row_high_limit, row_high_limit_last;
223         u32 reg_sdram, ecc_on, row_base;
224
225         ecc_on = ecc_enabled(dramcr);
226         reg_sdram = dramcr & BIT(4);
227         row_high_limit_last = 0;
228
229         for (index = 0; index < mci->nr_csrows; index++) {
230                 csrow = &mci->csrows[index];
231
232                 /* find the DRAM Chip Select Base address and mask */
233                 pci_read_config_byte(pdev, R82600_DRBA + index, &drbar);
234
235                 debugf1("%s() Row=%d DRBA = %#0x\n", __func__, index, drbar);
236
237                 row_high_limit = ((u32) drbar << 24);
238 /*              row_high_limit = ((u32)drbar << 24) | 0xffffffUL; */
239
240                 debugf1("%s() Row=%d, Boundry Address=%#0x, Last = %#0x\n",
241                         __func__, index, row_high_limit, row_high_limit_last);
242
243                 /* Empty row [p.57] */
244                 if (row_high_limit == row_high_limit_last)
245                         continue;
246
247                 row_base = row_high_limit_last;
248
249                 csrow->first_page = row_base >> PAGE_SHIFT;
250                 csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1;
251                 csrow->nr_pages = csrow->last_page - csrow->first_page + 1;
252                 /* Error address is top 19 bits - so granularity is      *
253                  * 14 bits                                               */
254                 csrow->grain = 1 << 14;
255                 csrow->mtype = reg_sdram ? MEM_RDDR : MEM_DDR;
256                 /* FIXME - check that this is unknowable with this chipset */
257                 csrow->dtype = DEV_UNKNOWN;
258
259                 /* Mode is global on 82600 */
260                 csrow->edac_mode = ecc_on ? EDAC_SECDED : EDAC_NONE;
261                 row_high_limit_last = row_high_limit;
262         }
263 }
264
265 static int r82600_probe1(struct pci_dev *pdev, int dev_idx)
266 {
267         struct mem_ctl_info *mci;
268         u8 dramcr;
269         u32 eapr;
270         u32 scrub_disabled;
271         u32 sdram_refresh_rate;
272         struct r82600_error_info discard;
273
274         debugf0("%s()\n", __func__);
275         pci_read_config_byte(pdev, R82600_DRAMC, &dramcr);
276         pci_read_config_dword(pdev, R82600_EAP, &eapr);
277         scrub_disabled = eapr & BIT(31);
278         sdram_refresh_rate = dramcr & (BIT(0) | BIT(1));
279         debugf2("%s(): sdram refresh rate = %#0x\n", __func__,
280                 sdram_refresh_rate);
281         debugf2("%s(): DRAMC register = %#0x\n", __func__, dramcr);
282         mci = edac_mc_alloc(0, R82600_NR_CSROWS, R82600_NR_CHANS, 0);
283
284         if (mci == NULL)
285                 return -ENOMEM;
286
287         debugf0("%s(): mci = %p\n", __func__, mci);
288         mci->dev = &pdev->dev;
289         mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR;
290         mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
291         /* FIXME try to work out if the chip leads have been used for COM2
292          * instead on this board? [MA6?] MAYBE:
293          */
294
295         /* On the R82600, the pins for memory bits 72:65 - i.e. the   *
296          * EC bits are shared with the pins for COM2 (!), so if COM2  *
297          * is enabled, we assume COM2 is wired up, and thus no EDAC   *
298          * is possible.                                               */
299         mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
300
301         if (ecc_enabled(dramcr)) {
302                 if (scrub_disabled)
303                         debugf3("%s(): mci = %p - Scrubbing disabled! EAP: "
304                                 "%#0x\n", __func__, mci, eapr);
305         } else
306                 mci->edac_cap = EDAC_FLAG_NONE;
307
308         mci->mod_name = EDAC_MOD_STR;
309         mci->mod_ver = R82600_REVISION;
310         mci->ctl_name = "R82600";
311         mci->dev_name = pci_name(pdev);
312         mci->edac_check = r82600_check;
313         mci->ctl_page_to_phys = NULL;
314         r82600_init_csrows(mci, pdev, dramcr);
315         r82600_get_error_info(mci, &discard);   /* clear counters */
316
317         /* Here we assume that we will never see multiple instances of this
318          * type of memory controller.  The ID is therefore hardcoded to 0.
319          */
320         if (edac_mc_add_mc(mci)) {
321                 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
322                 goto fail;
323         }
324
325         /* get this far and it's successful */
326
327         if (disable_hardware_scrub) {
328                 debugf3("%s(): Disabling Hardware Scrub (scrub on error)\n",
329                         __func__);
330                 pci_write_bits32(pdev, R82600_EAP, BIT(31), BIT(31));
331         }
332
333         /* allocating generic PCI control info */
334         r82600_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
335         if (!r82600_pci) {
336                 printk(KERN_WARNING
337                         "%s(): Unable to create PCI control\n",
338                         __func__);
339                 printk(KERN_WARNING
340                         "%s(): PCI error report via EDAC not setup\n",
341                         __func__);
342         }
343
344         debugf3("%s(): success\n", __func__);
345         return 0;
346
347 fail:
348         edac_mc_free(mci);
349         return -ENODEV;
350 }
351
352 /* returns count (>= 0), or negative on error */
353 static int __devinit r82600_init_one(struct pci_dev *pdev,
354                                 const struct pci_device_id *ent)
355 {
356         debugf0("%s()\n", __func__);
357
358         /* don't need to call pci_device_enable() */
359         return r82600_probe1(pdev, ent->driver_data);
360 }
361
362 static void __devexit r82600_remove_one(struct pci_dev *pdev)
363 {
364         struct mem_ctl_info *mci;
365
366         debugf0("%s()\n", __func__);
367
368         if (r82600_pci)
369                 edac_pci_release_generic_ctl(r82600_pci);
370
371         if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
372                 return;
373
374         edac_mc_free(mci);
375 }
376
377 static const struct pci_device_id r82600_pci_tbl[] __devinitdata = {
378         {
379          PCI_DEVICE(PCI_VENDOR_ID_RADISYS, R82600_BRIDGE_ID)
380          },
381         {
382          0,
383          }                      /* 0 terminated list. */
384 };
385
386 MODULE_DEVICE_TABLE(pci, r82600_pci_tbl);
387
388 static struct pci_driver r82600_driver = {
389         .name = EDAC_MOD_STR,
390         .probe = r82600_init_one,
391         .remove = __devexit_p(r82600_remove_one),
392         .id_table = r82600_pci_tbl,
393 };
394
395 static int __init r82600_init(void)
396 {
397        /* Ensure that the OPSTATE is set correctly for POLL or NMI */
398        opstate_init();
399
400         return pci_register_driver(&r82600_driver);
401 }
402
403 static void __exit r82600_exit(void)
404 {
405         pci_unregister_driver(&r82600_driver);
406 }
407
408 module_init(r82600_init);
409 module_exit(r82600_exit);
410
411 MODULE_LICENSE("GPL");
412 MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD Ltd. "
413                 "on behalf of EADS Astrium");
414 MODULE_DESCRIPTION("MC support for Radisys 82600 memory controllers");
415
416 module_param(disable_hardware_scrub, bool, 0644);
417 MODULE_PARM_DESC(disable_hardware_scrub,
418                  "If set, disable the chipset's automatic scrub for CEs");
419
420 module_param(edac_op_state, int, 0444);
421 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");