edac mpc85xx: add support for mpc8572
[linux-3.10.git] / drivers / edac / mpc85xx_edac.c
1 /*
2  * Freescale MPC85xx Memory Controller kenel module
3  *
4  * Author: Dave Jiang <djiang@mvista.com>
5  *
6  * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
7  * the terms of the GNU General Public License version 2. This program
8  * is licensed "as is" without any warranty of any kind, whether express
9  * or implied.
10  *
11  */
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/slab.h>
15 #include <linux/interrupt.h>
16 #include <linux/ctype.h>
17 #include <linux/io.h>
18 #include <linux/mod_devicetable.h>
19 #include <linux/edac.h>
20 #include <linux/smp.h>
21
22 #include <linux/of_platform.h>
23 #include <linux/of_device.h>
24 #include "edac_module.h"
25 #include "edac_core.h"
26 #include "mpc85xx_edac.h"
27
28 static int edac_dev_idx;
29 static int edac_pci_idx;
30 static int edac_mc_idx;
31
32 static u32 orig_ddr_err_disable;
33 static u32 orig_ddr_err_sbe;
34
35 /*
36  * PCI Err defines
37  */
38 #ifdef CONFIG_PCI
39 static u32 orig_pci_err_cap_dr;
40 static u32 orig_pci_err_en;
41 #endif
42
43 static u32 orig_l2_err_disable;
44 static u32 orig_hid1[2];
45
46 /************************ MC SYSFS parts ***********************************/
47
48 static ssize_t mpc85xx_mc_inject_data_hi_show(struct mem_ctl_info *mci,
49                                               char *data)
50 {
51         struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
52         return sprintf(data, "0x%08x",
53                        in_be32(pdata->mc_vbase +
54                                MPC85XX_MC_DATA_ERR_INJECT_HI));
55 }
56
57 static ssize_t mpc85xx_mc_inject_data_lo_show(struct mem_ctl_info *mci,
58                                               char *data)
59 {
60         struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
61         return sprintf(data, "0x%08x",
62                        in_be32(pdata->mc_vbase +
63                                MPC85XX_MC_DATA_ERR_INJECT_LO));
64 }
65
66 static ssize_t mpc85xx_mc_inject_ctrl_show(struct mem_ctl_info *mci, char *data)
67 {
68         struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
69         return sprintf(data, "0x%08x",
70                        in_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT));
71 }
72
73 static ssize_t mpc85xx_mc_inject_data_hi_store(struct mem_ctl_info *mci,
74                                                const char *data, size_t count)
75 {
76         struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
77         if (isdigit(*data)) {
78                 out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_HI,
79                          simple_strtoul(data, NULL, 0));
80                 return count;
81         }
82         return 0;
83 }
84
85 static ssize_t mpc85xx_mc_inject_data_lo_store(struct mem_ctl_info *mci,
86                                                const char *data, size_t count)
87 {
88         struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
89         if (isdigit(*data)) {
90                 out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_LO,
91                          simple_strtoul(data, NULL, 0));
92                 return count;
93         }
94         return 0;
95 }
96
97 static ssize_t mpc85xx_mc_inject_ctrl_store(struct mem_ctl_info *mci,
98                                             const char *data, size_t count)
99 {
100         struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
101         if (isdigit(*data)) {
102                 out_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT,
103                          simple_strtoul(data, NULL, 0));
104                 return count;
105         }
106         return 0;
107 }
108
109 static struct mcidev_sysfs_attribute mpc85xx_mc_sysfs_attributes[] = {
110         {
111          .attr = {
112                   .name = "inject_data_hi",
113                   .mode = (S_IRUGO | S_IWUSR)
114                   },
115          .show = mpc85xx_mc_inject_data_hi_show,
116          .store = mpc85xx_mc_inject_data_hi_store},
117         {
118          .attr = {
119                   .name = "inject_data_lo",
120                   .mode = (S_IRUGO | S_IWUSR)
121                   },
122          .show = mpc85xx_mc_inject_data_lo_show,
123          .store = mpc85xx_mc_inject_data_lo_store},
124         {
125          .attr = {
126                   .name = "inject_ctrl",
127                   .mode = (S_IRUGO | S_IWUSR)
128                   },
129          .show = mpc85xx_mc_inject_ctrl_show,
130          .store = mpc85xx_mc_inject_ctrl_store},
131
132         /* End of list */
133         {
134          .attr = {.name = NULL}
135          }
136 };
137
138 static void mpc85xx_set_mc_sysfs_attributes(struct mem_ctl_info *mci)
139 {
140         mci->mc_driver_sysfs_attributes = mpc85xx_mc_sysfs_attributes;
141 }
142
143 /**************************** PCI Err device ***************************/
144 #ifdef CONFIG_PCI
145
146 static void mpc85xx_pci_check(struct edac_pci_ctl_info *pci)
147 {
148         struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
149         u32 err_detect;
150
151         err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
152
153         /* master aborts can happen during PCI config cycles */
154         if (!(err_detect & ~(PCI_EDE_MULTI_ERR | PCI_EDE_MST_ABRT))) {
155                 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
156                 return;
157         }
158
159         printk(KERN_ERR "PCI error(s) detected\n");
160         printk(KERN_ERR "PCI/X ERR_DR register: %#08x\n", err_detect);
161
162         printk(KERN_ERR "PCI/X ERR_ATTRIB register: %#08x\n",
163                in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB));
164         printk(KERN_ERR "PCI/X ERR_ADDR register: %#08x\n",
165                in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR));
166         printk(KERN_ERR "PCI/X ERR_EXT_ADDR register: %#08x\n",
167                in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR));
168         printk(KERN_ERR "PCI/X ERR_DL register: %#08x\n",
169                in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL));
170         printk(KERN_ERR "PCI/X ERR_DH register: %#08x\n",
171                in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH));
172
173         /* clear error bits */
174         out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
175
176         if (err_detect & PCI_EDE_PERR_MASK)
177                 edac_pci_handle_pe(pci, pci->ctl_name);
178
179         if ((err_detect & ~PCI_EDE_MULTI_ERR) & ~PCI_EDE_PERR_MASK)
180                 edac_pci_handle_npe(pci, pci->ctl_name);
181 }
182
183 static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id)
184 {
185         struct edac_pci_ctl_info *pci = dev_id;
186         struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
187         u32 err_detect;
188
189         err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
190
191         if (!err_detect)
192                 return IRQ_NONE;
193
194         mpc85xx_pci_check(pci);
195
196         return IRQ_HANDLED;
197 }
198
199 static int __devinit mpc85xx_pci_err_probe(struct of_device *op,
200                                            const struct of_device_id *match)
201 {
202         struct edac_pci_ctl_info *pci;
203         struct mpc85xx_pci_pdata *pdata;
204         struct resource r;
205         int res = 0;
206
207         if (!devres_open_group(&op->dev, mpc85xx_pci_err_probe, GFP_KERNEL))
208                 return -ENOMEM;
209
210         pci = edac_pci_alloc_ctl_info(sizeof(*pdata), "mpc85xx_pci_err");
211         if (!pci)
212                 return -ENOMEM;
213
214         pdata = pci->pvt_info;
215         pdata->name = "mpc85xx_pci_err";
216         pdata->irq = NO_IRQ;
217         dev_set_drvdata(&op->dev, pci);
218         pci->dev = &op->dev;
219         pci->mod_name = EDAC_MOD_STR;
220         pci->ctl_name = pdata->name;
221         pci->dev_name = op->dev.bus_id;
222
223         if (edac_op_state == EDAC_OPSTATE_POLL)
224                 pci->edac_check = mpc85xx_pci_check;
225
226         pdata->edac_idx = edac_pci_idx++;
227
228         res = of_address_to_resource(op->node, 0, &r);
229         if (res) {
230                 printk(KERN_ERR "%s: Unable to get resource for "
231                        "PCI err regs\n", __func__);
232                 goto err;
233         }
234
235         /* we only need the error registers */
236         r.start += 0xe00;
237
238         if (!devm_request_mem_region(&op->dev, r.start,
239                                         r.end - r.start + 1, pdata->name)) {
240                 printk(KERN_ERR "%s: Error while requesting mem region\n",
241                        __func__);
242                 res = -EBUSY;
243                 goto err;
244         }
245
246         pdata->pci_vbase = devm_ioremap(&op->dev, r.start,
247                                         r.end - r.start + 1);
248         if (!pdata->pci_vbase) {
249                 printk(KERN_ERR "%s: Unable to setup PCI err regs\n", __func__);
250                 res = -ENOMEM;
251                 goto err;
252         }
253
254         orig_pci_err_cap_dr =
255             in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR);
256
257         /* PCI master abort is expected during config cycles */
258         out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, 0x40);
259
260         orig_pci_err_en = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN);
261
262         /* disable master abort reporting */
263         out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0x40);
264
265         /* clear error bits */
266         out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, ~0);
267
268         if (edac_pci_add_device(pci, pdata->edac_idx) > 0) {
269                 debugf3("%s(): failed edac_pci_add_device()\n", __func__);
270                 goto err;
271         }
272
273         if (edac_op_state == EDAC_OPSTATE_INT) {
274                 pdata->irq = irq_of_parse_and_map(op->node, 0);
275                 res = devm_request_irq(&op->dev, pdata->irq,
276                                        mpc85xx_pci_isr, IRQF_DISABLED,
277                                        "[EDAC] PCI err", pci);
278                 if (res < 0) {
279                         printk(KERN_ERR
280                                "%s: Unable to requiest irq %d for "
281                                "MPC85xx PCI err\n", __func__, pdata->irq);
282                         irq_dispose_mapping(pdata->irq);
283                         res = -ENODEV;
284                         goto err2;
285                 }
286
287                 printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for PCI Err\n",
288                        pdata->irq);
289         }
290
291         devres_remove_group(&op->dev, mpc85xx_pci_err_probe);
292         debugf3("%s(): success\n", __func__);
293         printk(KERN_INFO EDAC_MOD_STR " PCI err registered\n");
294
295         return 0;
296
297 err2:
298         edac_pci_del_device(&op->dev);
299 err:
300         edac_pci_free_ctl_info(pci);
301         devres_release_group(&op->dev, mpc85xx_pci_err_probe);
302         return res;
303 }
304
305 static int mpc85xx_pci_err_remove(struct of_device *op)
306 {
307         struct edac_pci_ctl_info *pci = dev_get_drvdata(&op->dev);
308         struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
309
310         debugf0("%s()\n", __func__);
311
312         out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR,
313                  orig_pci_err_cap_dr);
314
315         out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, orig_pci_err_en);
316
317         edac_pci_del_device(pci->dev);
318
319         if (edac_op_state == EDAC_OPSTATE_INT)
320                 irq_dispose_mapping(pdata->irq);
321
322         edac_pci_free_ctl_info(pci);
323
324         return 0;
325 }
326
327 static struct of_device_id mpc85xx_pci_err_of_match[] = {
328         {
329          .compatible = "fsl,mpc8540-pcix",
330          },
331         {
332          .compatible = "fsl,mpc8540-pci",
333         },
334         {},
335 };
336
337 static struct of_platform_driver mpc85xx_pci_err_driver = {
338         .owner = THIS_MODULE,
339         .name = "mpc85xx_pci_err",
340         .match_table = mpc85xx_pci_err_of_match,
341         .probe = mpc85xx_pci_err_probe,
342         .remove = __devexit_p(mpc85xx_pci_err_remove),
343         .driver = {
344                    .name = "mpc85xx_pci_err",
345                    .owner = THIS_MODULE,
346                    },
347 };
348
349 #endif                          /* CONFIG_PCI */
350
351 /**************************** L2 Err device ***************************/
352
353 /************************ L2 SYSFS parts ***********************************/
354
355 static ssize_t mpc85xx_l2_inject_data_hi_show(struct edac_device_ctl_info
356                                               *edac_dev, char *data)
357 {
358         struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
359         return sprintf(data, "0x%08x",
360                        in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI));
361 }
362
363 static ssize_t mpc85xx_l2_inject_data_lo_show(struct edac_device_ctl_info
364                                               *edac_dev, char *data)
365 {
366         struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
367         return sprintf(data, "0x%08x",
368                        in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO));
369 }
370
371 static ssize_t mpc85xx_l2_inject_ctrl_show(struct edac_device_ctl_info
372                                            *edac_dev, char *data)
373 {
374         struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
375         return sprintf(data, "0x%08x",
376                        in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL));
377 }
378
379 static ssize_t mpc85xx_l2_inject_data_hi_store(struct edac_device_ctl_info
380                                                *edac_dev, const char *data,
381                                                size_t count)
382 {
383         struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
384         if (isdigit(*data)) {
385                 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI,
386                          simple_strtoul(data, NULL, 0));
387                 return count;
388         }
389         return 0;
390 }
391
392 static ssize_t mpc85xx_l2_inject_data_lo_store(struct edac_device_ctl_info
393                                                *edac_dev, const char *data,
394                                                size_t count)
395 {
396         struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
397         if (isdigit(*data)) {
398                 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO,
399                          simple_strtoul(data, NULL, 0));
400                 return count;
401         }
402         return 0;
403 }
404
405 static ssize_t mpc85xx_l2_inject_ctrl_store(struct edac_device_ctl_info
406                                             *edac_dev, const char *data,
407                                             size_t count)
408 {
409         struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
410         if (isdigit(*data)) {
411                 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL,
412                          simple_strtoul(data, NULL, 0));
413                 return count;
414         }
415         return 0;
416 }
417
418 static struct edac_dev_sysfs_attribute mpc85xx_l2_sysfs_attributes[] = {
419         {
420          .attr = {
421                   .name = "inject_data_hi",
422                   .mode = (S_IRUGO | S_IWUSR)
423                   },
424          .show = mpc85xx_l2_inject_data_hi_show,
425          .store = mpc85xx_l2_inject_data_hi_store},
426         {
427          .attr = {
428                   .name = "inject_data_lo",
429                   .mode = (S_IRUGO | S_IWUSR)
430                   },
431          .show = mpc85xx_l2_inject_data_lo_show,
432          .store = mpc85xx_l2_inject_data_lo_store},
433         {
434          .attr = {
435                   .name = "inject_ctrl",
436                   .mode = (S_IRUGO | S_IWUSR)
437                   },
438          .show = mpc85xx_l2_inject_ctrl_show,
439          .store = mpc85xx_l2_inject_ctrl_store},
440
441         /* End of list */
442         {
443          .attr = {.name = NULL}
444          }
445 };
446
447 static void mpc85xx_set_l2_sysfs_attributes(struct edac_device_ctl_info
448                                             *edac_dev)
449 {
450         edac_dev->sysfs_attributes = mpc85xx_l2_sysfs_attributes;
451 }
452
453 /***************************** L2 ops ***********************************/
454
455 static void mpc85xx_l2_check(struct edac_device_ctl_info *edac_dev)
456 {
457         struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
458         u32 err_detect;
459
460         err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET);
461
462         if (!(err_detect & L2_EDE_MASK))
463                 return;
464
465         printk(KERN_ERR "ECC Error in CPU L2 cache\n");
466         printk(KERN_ERR "L2 Error Detect Register: 0x%08x\n", err_detect);
467         printk(KERN_ERR "L2 Error Capture Data High Register: 0x%08x\n",
468                in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATAHI));
469         printk(KERN_ERR "L2 Error Capture Data Lo Register: 0x%08x\n",
470                in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATALO));
471         printk(KERN_ERR "L2 Error Syndrome Register: 0x%08x\n",
472                in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTECC));
473         printk(KERN_ERR "L2 Error Attributes Capture Register: 0x%08x\n",
474                in_be32(pdata->l2_vbase + MPC85XX_L2_ERRATTR));
475         printk(KERN_ERR "L2 Error Address Capture Register: 0x%08x\n",
476                in_be32(pdata->l2_vbase + MPC85XX_L2_ERRADDR));
477
478         /* clear error detect register */
479         out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, err_detect);
480
481         if (err_detect & L2_EDE_CE_MASK)
482                 edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name);
483
484         if (err_detect & L2_EDE_UE_MASK)
485                 edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name);
486 }
487
488 static irqreturn_t mpc85xx_l2_isr(int irq, void *dev_id)
489 {
490         struct edac_device_ctl_info *edac_dev = dev_id;
491         struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
492         u32 err_detect;
493
494         err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET);
495
496         if (!(err_detect & L2_EDE_MASK))
497                 return IRQ_NONE;
498
499         mpc85xx_l2_check(edac_dev);
500
501         return IRQ_HANDLED;
502 }
503
504 static int __devinit mpc85xx_l2_err_probe(struct of_device *op,
505                                           const struct of_device_id *match)
506 {
507         struct edac_device_ctl_info *edac_dev;
508         struct mpc85xx_l2_pdata *pdata;
509         struct resource r;
510         int res;
511
512         if (!devres_open_group(&op->dev, mpc85xx_l2_err_probe, GFP_KERNEL))
513                 return -ENOMEM;
514
515         edac_dev = edac_device_alloc_ctl_info(sizeof(*pdata),
516                                               "cpu", 1, "L", 1, 2, NULL, 0,
517                                               edac_dev_idx);
518         if (!edac_dev) {
519                 devres_release_group(&op->dev, mpc85xx_l2_err_probe);
520                 return -ENOMEM;
521         }
522
523         pdata = edac_dev->pvt_info;
524         pdata->name = "mpc85xx_l2_err";
525         pdata->irq = NO_IRQ;
526         edac_dev->dev = &op->dev;
527         dev_set_drvdata(edac_dev->dev, edac_dev);
528         edac_dev->ctl_name = pdata->name;
529         edac_dev->dev_name = pdata->name;
530
531         res = of_address_to_resource(op->node, 0, &r);
532         if (res) {
533                 printk(KERN_ERR "%s: Unable to get resource for "
534                        "L2 err regs\n", __func__);
535                 goto err;
536         }
537
538         /* we only need the error registers */
539         r.start += 0xe00;
540
541         if (!devm_request_mem_region(&op->dev, r.start,
542                                      r.end - r.start + 1, pdata->name)) {
543                 printk(KERN_ERR "%s: Error while requesting mem region\n",
544                        __func__);
545                 res = -EBUSY;
546                 goto err;
547         }
548
549         pdata->l2_vbase = devm_ioremap(&op->dev, r.start, r.end - r.start + 1);
550         if (!pdata->l2_vbase) {
551                 printk(KERN_ERR "%s: Unable to setup L2 err regs\n", __func__);
552                 res = -ENOMEM;
553                 goto err;
554         }
555
556         out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, ~0);
557
558         orig_l2_err_disable = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS);
559
560         /* clear the err_dis */
561         out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, 0);
562
563         edac_dev->mod_name = EDAC_MOD_STR;
564
565         if (edac_op_state == EDAC_OPSTATE_POLL)
566                 edac_dev->edac_check = mpc85xx_l2_check;
567
568         mpc85xx_set_l2_sysfs_attributes(edac_dev);
569
570         pdata->edac_idx = edac_dev_idx++;
571
572         if (edac_device_add_device(edac_dev) > 0) {
573                 debugf3("%s(): failed edac_device_add_device()\n", __func__);
574                 goto err;
575         }
576
577         if (edac_op_state == EDAC_OPSTATE_INT) {
578                 pdata->irq = irq_of_parse_and_map(op->node, 0);
579                 res = devm_request_irq(&op->dev, pdata->irq,
580                                        mpc85xx_l2_isr, IRQF_DISABLED,
581                                        "[EDAC] L2 err", edac_dev);
582                 if (res < 0) {
583                         printk(KERN_ERR
584                                "%s: Unable to requiest irq %d for "
585                                "MPC85xx L2 err\n", __func__, pdata->irq);
586                         irq_dispose_mapping(pdata->irq);
587                         res = -ENODEV;
588                         goto err2;
589                 }
590
591                 printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for L2 Err\n",
592                        pdata->irq);
593
594                 edac_dev->op_state = OP_RUNNING_INTERRUPT;
595
596                 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, L2_EIE_MASK);
597         }
598
599         devres_remove_group(&op->dev, mpc85xx_l2_err_probe);
600
601         debugf3("%s(): success\n", __func__);
602         printk(KERN_INFO EDAC_MOD_STR " L2 err registered\n");
603
604         return 0;
605
606 err2:
607         edac_device_del_device(&op->dev);
608 err:
609         devres_release_group(&op->dev, mpc85xx_l2_err_probe);
610         edac_device_free_ctl_info(edac_dev);
611         return res;
612 }
613
614 static int mpc85xx_l2_err_remove(struct of_device *op)
615 {
616         struct edac_device_ctl_info *edac_dev = dev_get_drvdata(&op->dev);
617         struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
618
619         debugf0("%s()\n", __func__);
620
621         if (edac_op_state == EDAC_OPSTATE_INT) {
622                 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, 0);
623                 irq_dispose_mapping(pdata->irq);
624         }
625
626         out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, orig_l2_err_disable);
627         edac_device_del_device(&op->dev);
628         edac_device_free_ctl_info(edac_dev);
629         return 0;
630 }
631
632 static struct of_device_id mpc85xx_l2_err_of_match[] = {
633         {
634          .compatible = "fsl,8540-l2-cache-controller",
635          },
636         {
637          .compatible = "fsl,8541-l2-cache-controller",
638          },
639         {
640          .compatible = "fsl,8544-l2-cache-controller",
641          },
642         {
643          .compatible = "fsl,8548-l2-cache-controller",
644          },
645         {
646          .compatible = "fsl,8555-l2-cache-controller",
647          },
648         {
649          .compatible = "fsl,8568-l2-cache-controller",
650          },
651         {
652          .compatible = "fsl,mpc8572-l2-cache-controller",
653          },
654         {},
655 };
656
657 static struct of_platform_driver mpc85xx_l2_err_driver = {
658         .owner = THIS_MODULE,
659         .name = "mpc85xx_l2_err",
660         .match_table = mpc85xx_l2_err_of_match,
661         .probe = mpc85xx_l2_err_probe,
662         .remove = mpc85xx_l2_err_remove,
663         .driver = {
664                    .name = "mpc85xx_l2_err",
665                    .owner = THIS_MODULE,
666                    },
667 };
668
669 /**************************** MC Err device ***************************/
670
671 static void mpc85xx_mc_check(struct mem_ctl_info *mci)
672 {
673         struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
674         struct csrow_info *csrow;
675         u32 err_detect;
676         u32 syndrome;
677         u32 err_addr;
678         u32 pfn;
679         int row_index;
680
681         err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT);
682         if (err_detect)
683                 return;
684
685         mpc85xx_mc_printk(mci, KERN_ERR, "Err Detect Register: %#8.8x\n",
686                           err_detect);
687
688         /* no more processing if not ECC bit errors */
689         if (!(err_detect & (DDR_EDE_SBE | DDR_EDE_MBE))) {
690                 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect);
691                 return;
692         }
693
694         syndrome = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ECC);
695         err_addr = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ADDRESS);
696         pfn = err_addr >> PAGE_SHIFT;
697
698         for (row_index = 0; row_index < mci->nr_csrows; row_index++) {
699                 csrow = &mci->csrows[row_index];
700                 if ((pfn >= csrow->first_page) && (pfn <= csrow->last_page))
701                         break;
702         }
703
704         mpc85xx_mc_printk(mci, KERN_ERR, "Capture Data High: %#8.8x\n",
705                           in_be32(pdata->mc_vbase +
706                                   MPC85XX_MC_CAPTURE_DATA_HI));
707         mpc85xx_mc_printk(mci, KERN_ERR, "Capture Data Low: %#8.8x\n",
708                           in_be32(pdata->mc_vbase +
709                                   MPC85XX_MC_CAPTURE_DATA_LO));
710         mpc85xx_mc_printk(mci, KERN_ERR, "syndrome: %#8.8x\n", syndrome);
711         mpc85xx_mc_printk(mci, KERN_ERR, "err addr: %#8.8x\n", err_addr);
712         mpc85xx_mc_printk(mci, KERN_ERR, "PFN: %#8.8x\n", pfn);
713
714         /* we are out of range */
715         if (row_index == mci->nr_csrows)
716                 mpc85xx_mc_printk(mci, KERN_ERR, "PFN out of range!\n");
717
718         if (err_detect & DDR_EDE_SBE)
719                 edac_mc_handle_ce(mci, pfn, err_addr & PAGE_MASK,
720                                   syndrome, row_index, 0, mci->ctl_name);
721
722         if (err_detect & DDR_EDE_MBE)
723                 edac_mc_handle_ue(mci, pfn, err_addr & PAGE_MASK,
724                                   row_index, mci->ctl_name);
725
726         out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect);
727 }
728
729 static irqreturn_t mpc85xx_mc_isr(int irq, void *dev_id)
730 {
731         struct mem_ctl_info *mci = dev_id;
732         struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
733         u32 err_detect;
734
735         err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT);
736         if (!err_detect)
737                 return IRQ_NONE;
738
739         mpc85xx_mc_check(mci);
740
741         return IRQ_HANDLED;
742 }
743
744 static void __devinit mpc85xx_init_csrows(struct mem_ctl_info *mci)
745 {
746         struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
747         struct csrow_info *csrow;
748         u32 sdram_ctl;
749         u32 sdtype;
750         enum mem_type mtype;
751         u32 cs_bnds;
752         int index;
753
754         sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG);
755
756         sdtype = sdram_ctl & DSC_SDTYPE_MASK;
757         if (sdram_ctl & DSC_RD_EN) {
758                 switch (sdtype) {
759                 case DSC_SDTYPE_DDR:
760                         mtype = MEM_RDDR;
761                         break;
762                 case DSC_SDTYPE_DDR2:
763                         mtype = MEM_RDDR2;
764                         break;
765                 default:
766                         mtype = MEM_UNKNOWN;
767                         break;
768                 }
769         } else {
770                 switch (sdtype) {
771                 case DSC_SDTYPE_DDR:
772                         mtype = MEM_DDR;
773                         break;
774                 case DSC_SDTYPE_DDR2:
775                         mtype = MEM_DDR2;
776                         break;
777                 default:
778                         mtype = MEM_UNKNOWN;
779                         break;
780                 }
781         }
782
783         for (index = 0; index < mci->nr_csrows; index++) {
784                 u32 start;
785                 u32 end;
786
787                 csrow = &mci->csrows[index];
788                 cs_bnds = in_be32(pdata->mc_vbase + MPC85XX_MC_CS_BNDS_0 +
789                                   (index * MPC85XX_MC_CS_BNDS_OFS));
790                 start = (cs_bnds & 0xfff0000) << 4;
791                 end = ((cs_bnds & 0xfff) << 20);
792                 if (start)
793                         start |= 0xfffff;
794                 if (end)
795                         end |= 0xfffff;
796
797                 if (start == end)
798                         continue;       /* not populated */
799
800                 csrow->first_page = start >> PAGE_SHIFT;
801                 csrow->last_page = end >> PAGE_SHIFT;
802                 csrow->nr_pages = csrow->last_page + 1 - csrow->first_page;
803                 csrow->grain = 8;
804                 csrow->mtype = mtype;
805                 csrow->dtype = DEV_UNKNOWN;
806                 if (sdram_ctl & DSC_X32_EN)
807                         csrow->dtype = DEV_X32;
808                 csrow->edac_mode = EDAC_SECDED;
809         }
810 }
811
812 static int __devinit mpc85xx_mc_err_probe(struct of_device *op,
813                                           const struct of_device_id *match)
814 {
815         struct mem_ctl_info *mci;
816         struct mpc85xx_mc_pdata *pdata;
817         struct resource r;
818         u32 sdram_ctl;
819         int res;
820
821         if (!devres_open_group(&op->dev, mpc85xx_mc_err_probe, GFP_KERNEL))
822                 return -ENOMEM;
823
824         mci = edac_mc_alloc(sizeof(*pdata), 4, 1, edac_mc_idx);
825         if (!mci) {
826                 devres_release_group(&op->dev, mpc85xx_mc_err_probe);
827                 return -ENOMEM;
828         }
829
830         pdata = mci->pvt_info;
831         pdata->name = "mpc85xx_mc_err";
832         pdata->irq = NO_IRQ;
833         mci->dev = &op->dev;
834         pdata->edac_idx = edac_mc_idx++;
835         dev_set_drvdata(mci->dev, mci);
836         mci->ctl_name = pdata->name;
837         mci->dev_name = pdata->name;
838
839         res = of_address_to_resource(op->node, 0, &r);
840         if (res) {
841                 printk(KERN_ERR "%s: Unable to get resource for MC err regs\n",
842                        __func__);
843                 goto err;
844         }
845
846         if (!devm_request_mem_region(&op->dev, r.start,
847                                      r.end - r.start + 1, pdata->name)) {
848                 printk(KERN_ERR "%s: Error while requesting mem region\n",
849                        __func__);
850                 res = -EBUSY;
851                 goto err;
852         }
853
854         pdata->mc_vbase = devm_ioremap(&op->dev, r.start, r.end - r.start + 1);
855         if (!pdata->mc_vbase) {
856                 printk(KERN_ERR "%s: Unable to setup MC err regs\n", __func__);
857                 res = -ENOMEM;
858                 goto err;
859         }
860
861         sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG);
862         if (!(sdram_ctl & DSC_ECC_EN)) {
863                 /* no ECC */
864                 printk(KERN_WARNING "%s: No ECC DIMMs discovered\n", __func__);
865                 res = -ENODEV;
866                 goto err;
867         }
868
869         debugf3("%s(): init mci\n", __func__);
870         mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_RDDR2 |
871             MEM_FLAG_DDR | MEM_FLAG_DDR2;
872         mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
873         mci->edac_cap = EDAC_FLAG_SECDED;
874         mci->mod_name = EDAC_MOD_STR;
875         mci->mod_ver = MPC85XX_REVISION;
876
877         if (edac_op_state == EDAC_OPSTATE_POLL)
878                 mci->edac_check = mpc85xx_mc_check;
879
880         mci->ctl_page_to_phys = NULL;
881
882         mci->scrub_mode = SCRUB_SW_SRC;
883
884         mpc85xx_set_mc_sysfs_attributes(mci);
885
886         mpc85xx_init_csrows(mci);
887
888 #ifdef CONFIG_EDAC_DEBUG
889         edac_mc_register_mcidev_debug((struct attribute **)debug_attr);
890 #endif
891
892         /* store the original error disable bits */
893         orig_ddr_err_disable =
894             in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE);
895         out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, 0);
896
897         /* clear all error bits */
898         out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, ~0);
899
900         if (edac_mc_add_mc(mci)) {
901                 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
902                 goto err;
903         }
904
905         if (edac_op_state == EDAC_OPSTATE_INT) {
906                 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN,
907                          DDR_EIE_MBEE | DDR_EIE_SBEE);
908
909                 /* store the original error management threshold */
910                 orig_ddr_err_sbe = in_be32(pdata->mc_vbase +
911                                            MPC85XX_MC_ERR_SBE) & 0xff0000;
912
913                 /* set threshold to 1 error per interrupt */
914                 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, 0x10000);
915
916                 /* register interrupts */
917                 pdata->irq = irq_of_parse_and_map(op->node, 0);
918                 res = devm_request_irq(&op->dev, pdata->irq,
919                                        mpc85xx_mc_isr,
920                                         IRQF_DISABLED | IRQF_SHARED,
921                                        "[EDAC] MC err", mci);
922                 if (res < 0) {
923                         printk(KERN_ERR "%s: Unable to request irq %d for "
924                                "MPC85xx DRAM ERR\n", __func__, pdata->irq);
925                         irq_dispose_mapping(pdata->irq);
926                         res = -ENODEV;
927                         goto err2;
928                 }
929
930                 printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for MC\n",
931                        pdata->irq);
932         }
933
934         devres_remove_group(&op->dev, mpc85xx_mc_err_probe);
935         debugf3("%s(): success\n", __func__);
936         printk(KERN_INFO EDAC_MOD_STR " MC err registered\n");
937
938         return 0;
939
940 err2:
941         edac_mc_del_mc(&op->dev);
942 err:
943         devres_release_group(&op->dev, mpc85xx_mc_err_probe);
944         edac_mc_free(mci);
945         return res;
946 }
947
948 static int mpc85xx_mc_err_remove(struct of_device *op)
949 {
950         struct mem_ctl_info *mci = dev_get_drvdata(&op->dev);
951         struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
952
953         debugf0("%s()\n", __func__);
954
955         if (edac_op_state == EDAC_OPSTATE_INT) {
956                 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, 0);
957                 irq_dispose_mapping(pdata->irq);
958         }
959
960         out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE,
961                  orig_ddr_err_disable);
962         out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, orig_ddr_err_sbe);
963
964         edac_mc_del_mc(&op->dev);
965         edac_mc_free(mci);
966         return 0;
967 }
968
969 static struct of_device_id mpc85xx_mc_err_of_match[] = {
970         {
971          .compatible = "fsl,8540-memory-controller",
972          },
973         {
974          .compatible = "fsl,8541-memory-controller",
975          },
976         {
977          .compatible = "fsl,8544-memory-controller",
978          },
979         {
980          .compatible = "fsl,8548-memory-controller",
981          },
982         {
983          .compatible = "fsl,8555-memory-controller",
984          },
985         {
986          .compatible = "fsl,8568-memory-controller",
987          },
988         {
989          .compatible = "fsl,mpc8572-memory-controller",
990          },
991         {},
992 };
993
994 static struct of_platform_driver mpc85xx_mc_err_driver = {
995         .owner = THIS_MODULE,
996         .name = "mpc85xx_mc_err",
997         .match_table = mpc85xx_mc_err_of_match,
998         .probe = mpc85xx_mc_err_probe,
999         .remove = mpc85xx_mc_err_remove,
1000         .driver = {
1001                    .name = "mpc85xx_mc_err",
1002                    .owner = THIS_MODULE,
1003                    },
1004 };
1005
1006
1007 static void __init mpc85xx_mc_clear_rfxe(void *data)
1008 {
1009         orig_hid1[smp_processor_id()] = mfspr(SPRN_HID1);
1010         mtspr(SPRN_HID1, (orig_hid1[smp_processor_id()] & ~0x20000));
1011 }
1012
1013
1014 static int __init mpc85xx_mc_init(void)
1015 {
1016         int res = 0;
1017
1018         printk(KERN_INFO "Freescale(R) MPC85xx EDAC driver, "
1019                "(C) 2006 Montavista Software\n");
1020
1021         /* make sure error reporting method is sane */
1022         switch (edac_op_state) {
1023         case EDAC_OPSTATE_POLL:
1024         case EDAC_OPSTATE_INT:
1025                 break;
1026         default:
1027                 edac_op_state = EDAC_OPSTATE_INT;
1028                 break;
1029         }
1030
1031         res = of_register_platform_driver(&mpc85xx_mc_err_driver);
1032         if (res)
1033                 printk(KERN_WARNING EDAC_MOD_STR "MC fails to register\n");
1034
1035         res = of_register_platform_driver(&mpc85xx_l2_err_driver);
1036         if (res)
1037                 printk(KERN_WARNING EDAC_MOD_STR "L2 fails to register\n");
1038
1039 #ifdef CONFIG_PCI
1040         res = of_register_platform_driver(&mpc85xx_pci_err_driver);
1041         if (res)
1042                 printk(KERN_WARNING EDAC_MOD_STR "PCI fails to register\n");
1043 #endif
1044
1045         /*
1046          * need to clear HID1[RFXE] to disable machine check int
1047          * so we can catch it
1048          */
1049         if (edac_op_state == EDAC_OPSTATE_INT)
1050                 on_each_cpu(mpc85xx_mc_clear_rfxe, NULL, 0);
1051
1052         return 0;
1053 }
1054
1055 module_init(mpc85xx_mc_init);
1056
1057 static void __exit mpc85xx_mc_restore_hid1(void *data)
1058 {
1059         mtspr(SPRN_HID1, orig_hid1[smp_processor_id()]);
1060 }
1061
1062 static void __exit mpc85xx_mc_exit(void)
1063 {
1064         on_each_cpu(mpc85xx_mc_restore_hid1, NULL, 0);
1065 #ifdef CONFIG_PCI
1066         of_unregister_platform_driver(&mpc85xx_pci_err_driver);
1067 #endif
1068         of_unregister_platform_driver(&mpc85xx_l2_err_driver);
1069         of_unregister_platform_driver(&mpc85xx_mc_err_driver);
1070 }
1071
1072 module_exit(mpc85xx_mc_exit);
1073
1074 MODULE_LICENSE("GPL");
1075 MODULE_AUTHOR("Montavista Software, Inc.");
1076 module_param(edac_op_state, int, 0444);
1077 MODULE_PARM_DESC(edac_op_state,
1078                  "EDAC Error Reporting state: 0=Poll, 2=Interrupt");