ecfca7c6bba635780b80780b0bd40f40768e9040
[linux-3.10.git] / drivers / edac / e7xxx_edac.c
1 /*
2  * Intel e7xxx Memory Controller kernel module
3  * (C) 2003 Linux Networx (http://lnxi.com)
4  * This file may be distributed under the terms of the
5  * GNU General Public License.
6  *
7  * See "enum e7xxx_chips" below for supported chipsets
8  *
9  * Written by Thayne Harbaugh
10  * Based on work by Dan Hollis <goemon at anime dot net> and others.
11  *      http://www.anime.net/~goemon/linux-ecc/
12  *
13  * Contributors:
14  *      Eric Biederman (Linux Networx)
15  *      Tom Zimmerman (Linux Networx)
16  *      Jim Garlick (Lawrence Livermore National Labs)
17  *      Dave Peterson (Lawrence Livermore National Labs)
18  *      That One Guy (Some other place)
19  *      Wang Zhenyu (intel.com)
20  *
21  * $Id: edac_e7xxx.c,v 1.5.2.9 2005/10/05 00:43:44 dsp_llnl Exp $
22  *
23  */
24
25 #include <linux/module.h>
26 #include <linux/init.h>
27 #include <linux/pci.h>
28 #include <linux/pci_ids.h>
29 #include <linux/slab.h>
30 #include "edac_mc.h"
31
32 #define e7xxx_printk(level, fmt, arg...) \
33         edac_printk(level, "e7xxx", fmt, ##arg)
34
35 #define e7xxx_mc_printk(mci, level, fmt, arg...) \
36         edac_mc_chipset_printk(mci, level, "e7xxx", fmt, ##arg)
37
38 #ifndef PCI_DEVICE_ID_INTEL_7205_0
39 #define PCI_DEVICE_ID_INTEL_7205_0      0x255d
40 #endif                          /* PCI_DEVICE_ID_INTEL_7205_0 */
41
42 #ifndef PCI_DEVICE_ID_INTEL_7205_1_ERR
43 #define PCI_DEVICE_ID_INTEL_7205_1_ERR  0x2551
44 #endif                          /* PCI_DEVICE_ID_INTEL_7205_1_ERR */
45
46 #ifndef PCI_DEVICE_ID_INTEL_7500_0
47 #define PCI_DEVICE_ID_INTEL_7500_0      0x2540
48 #endif                          /* PCI_DEVICE_ID_INTEL_7500_0 */
49
50 #ifndef PCI_DEVICE_ID_INTEL_7500_1_ERR
51 #define PCI_DEVICE_ID_INTEL_7500_1_ERR  0x2541
52 #endif                          /* PCI_DEVICE_ID_INTEL_7500_1_ERR */
53
54 #ifndef PCI_DEVICE_ID_INTEL_7501_0
55 #define PCI_DEVICE_ID_INTEL_7501_0      0x254c
56 #endif                          /* PCI_DEVICE_ID_INTEL_7501_0 */
57
58 #ifndef PCI_DEVICE_ID_INTEL_7501_1_ERR
59 #define PCI_DEVICE_ID_INTEL_7501_1_ERR  0x2541
60 #endif                          /* PCI_DEVICE_ID_INTEL_7501_1_ERR */
61
62 #ifndef PCI_DEVICE_ID_INTEL_7505_0
63 #define PCI_DEVICE_ID_INTEL_7505_0      0x2550
64 #endif                          /* PCI_DEVICE_ID_INTEL_7505_0 */
65
66 #ifndef PCI_DEVICE_ID_INTEL_7505_1_ERR
67 #define PCI_DEVICE_ID_INTEL_7505_1_ERR  0x2551
68 #endif                          /* PCI_DEVICE_ID_INTEL_7505_1_ERR */
69
70 #define E7XXX_NR_CSROWS         8       /* number of csrows */
71 #define E7XXX_NR_DIMMS          8       /* FIXME - is this correct? */
72
73 /* E7XXX register addresses - device 0 function 0 */
74 #define E7XXX_DRB               0x60    /* DRAM row boundary register (8b) */
75 #define E7XXX_DRA               0x70    /* DRAM row attribute register (8b) */
76                                         /*
77                                          * 31   Device width row 7 0=x8 1=x4
78                                          * 27   Device width row 6
79                                          * 23   Device width row 5
80                                          * 19   Device width row 4
81                                          * 15   Device width row 3
82                                          * 11   Device width row 2
83                                          *  7   Device width row 1
84                                          *  3   Device width row 0
85                                          */
86 #define E7XXX_DRC               0x7C    /* DRAM controller mode reg (32b) */
87                                         /*
88                                          * 22    Number channels 0=1,1=2
89                                          * 19:18 DRB Granularity 32/64MB
90                                          */
91 #define E7XXX_TOLM              0xC4    /* DRAM top of low memory reg (16b) */
92 #define E7XXX_REMAPBASE         0xC6    /* DRAM remap base address reg (16b) */
93 #define E7XXX_REMAPLIMIT        0xC8    /* DRAM remap limit address reg (16b) */
94
95 /* E7XXX register addresses - device 0 function 1 */
96 #define E7XXX_DRAM_FERR         0x80    /* DRAM first error register (8b) */
97 #define E7XXX_DRAM_NERR         0x82    /* DRAM next error register (8b) */
98 #define E7XXX_DRAM_CELOG_ADD    0xA0    /* DRAM first correctable memory */
99                                         /*     error address register (32b) */
100                                         /*
101                                          * 31:28 Reserved
102                                          * 27:6  CE address (4k block 33:12)
103                                          *  5:0  Reserved
104                                          */
105 #define E7XXX_DRAM_UELOG_ADD    0xB0    /* DRAM first uncorrectable memory */
106                                         /*     error address register (32b) */
107                                         /*
108                                          * 31:28 Reserved
109                                          * 27:6  CE address (4k block 33:12)
110                                          *  5:0  Reserved
111                                          */
112 #define E7XXX_DRAM_CELOG_SYNDROME 0xD0  /* DRAM first correctable memory */
113                                         /*     error syndrome register (16b) */
114
115 enum e7xxx_chips {
116         E7500 = 0,
117         E7501,
118         E7505,
119         E7205,
120 };
121
122 struct e7xxx_pvt {
123         struct pci_dev *bridge_ck;
124         u32 tolm;
125         u32 remapbase;
126         u32 remaplimit;
127         const struct e7xxx_dev_info *dev_info;
128 };
129
130 struct e7xxx_dev_info {
131         u16 err_dev;
132         const char *ctl_name;
133 };
134
135 struct e7xxx_error_info {
136         u8 dram_ferr;
137         u8 dram_nerr;
138         u32 dram_celog_add;
139         u16 dram_celog_syndrome;
140         u32 dram_uelog_add;
141 };
142
143 static const struct e7xxx_dev_info e7xxx_devs[] = {
144         [E7500] = {
145                 .err_dev = PCI_DEVICE_ID_INTEL_7500_1_ERR,
146                 .ctl_name = "E7500"
147         },
148         [E7501] = {
149                 .err_dev = PCI_DEVICE_ID_INTEL_7501_1_ERR,
150                 .ctl_name = "E7501"
151         },
152         [E7505] = {
153                 .err_dev = PCI_DEVICE_ID_INTEL_7505_1_ERR,
154                 .ctl_name = "E7505"
155         },
156         [E7205] = {
157                 .err_dev = PCI_DEVICE_ID_INTEL_7205_1_ERR,
158                 .ctl_name = "E7205"
159         },
160 };
161
162 /* FIXME - is this valid for both SECDED and S4ECD4ED? */
163 static inline int e7xxx_find_channel(u16 syndrome)
164 {
165         debugf3("%s()\n", __func__);
166
167         if ((syndrome & 0xff00) == 0)
168                 return 0;
169
170         if ((syndrome & 0x00ff) == 0)
171                 return 1;
172
173         if ((syndrome & 0xf000) == 0 || (syndrome & 0x0f00) == 0)
174                 return 0;
175
176         return 1;
177 }
178
179 static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci,
180                 unsigned long page)
181 {
182         u32 remap;
183         struct e7xxx_pvt *pvt = (struct e7xxx_pvt *) mci->pvt_info;
184
185         debugf3("%s()\n", __func__);
186
187         if ((page < pvt->tolm) ||
188                         ((page >= 0x100000) && (page < pvt->remapbase)))
189                 return page;
190
191         remap = (page - pvt->tolm) + pvt->remapbase;
192
193         if (remap < pvt->remaplimit)
194                 return remap;
195
196         e7xxx_printk(KERN_ERR, "Invalid page %lx - out of range\n", page);
197         return pvt->tolm - 1;
198 }
199
200 static void process_ce(struct mem_ctl_info *mci,
201                 struct e7xxx_error_info *info)
202 {
203         u32 error_1b, page;
204         u16 syndrome;
205         int row;
206         int channel;
207
208         debugf3("%s()\n", __func__);
209         /* read the error address */
210         error_1b = info->dram_celog_add;
211         /* FIXME - should use PAGE_SHIFT */
212         page = error_1b >> 6;  /* convert the address to 4k page */
213         /* read the syndrome */
214         syndrome = info->dram_celog_syndrome;
215         /* FIXME - check for -1 */
216         row = edac_mc_find_csrow_by_page(mci, page);
217         /* convert syndrome to channel */
218         channel = e7xxx_find_channel(syndrome);
219         edac_mc_handle_ce(mci, page, 0, syndrome, row, channel, "e7xxx CE");
220 }
221
222 static void process_ce_no_info(struct mem_ctl_info *mci)
223 {
224         debugf3("%s()\n", __func__);
225         edac_mc_handle_ce_no_info(mci, "e7xxx CE log register overflow");
226 }
227
228 static void process_ue(struct mem_ctl_info *mci,
229                 struct e7xxx_error_info *info)
230 {
231         u32 error_2b, block_page;
232         int row;
233
234         debugf3("%s()\n", __func__);
235         /* read the error address */
236         error_2b = info->dram_uelog_add;
237         /* FIXME - should use PAGE_SHIFT */
238         block_page = error_2b >> 6;  /* convert to 4k address */
239         row = edac_mc_find_csrow_by_page(mci, block_page);
240         edac_mc_handle_ue(mci, block_page, 0, row, "e7xxx UE");
241 }
242
243 static void process_ue_no_info(struct mem_ctl_info *mci)
244 {
245         debugf3("%s()\n", __func__);
246         edac_mc_handle_ue_no_info(mci, "e7xxx UE log register overflow");
247 }
248
249 static void e7xxx_get_error_info (struct mem_ctl_info *mci,
250                 struct e7xxx_error_info *info)
251 {
252         struct e7xxx_pvt *pvt;
253
254         pvt = (struct e7xxx_pvt *) mci->pvt_info;
255         pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_FERR,
256                         &info->dram_ferr);
257         pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_NERR,
258                         &info->dram_nerr);
259
260         if ((info->dram_ferr & 1) || (info->dram_nerr & 1)) {
261                 pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_CELOG_ADD,
262                                 &info->dram_celog_add);
263                 pci_read_config_word(pvt->bridge_ck,
264                                 E7XXX_DRAM_CELOG_SYNDROME,
265                                 &info->dram_celog_syndrome);
266         }
267
268         if ((info->dram_ferr & 2) || (info->dram_nerr & 2))
269                 pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_UELOG_ADD,
270                                 &info->dram_uelog_add);
271
272         if (info->dram_ferr & 3)
273                 pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_FERR, 0x03, 0x03);
274
275         if (info->dram_nerr & 3)
276                 pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_NERR, 0x03, 0x03);
277 }
278
279 static int e7xxx_process_error_info (struct mem_ctl_info *mci,
280                 struct e7xxx_error_info *info, int handle_errors)
281 {
282         int error_found;
283
284         error_found = 0;
285
286         /* decode and report errors */
287         if (info->dram_ferr & 1) {      /* check first error correctable */
288                 error_found = 1;
289
290                 if (handle_errors)
291                         process_ce(mci, info);
292         }
293
294         if (info->dram_ferr & 2) {      /* check first error uncorrectable */
295                 error_found = 1;
296
297                 if (handle_errors)
298                         process_ue(mci, info);
299         }
300
301         if (info->dram_nerr & 1) {      /* check next error correctable */
302                 error_found = 1;
303
304                 if (handle_errors) {
305                         if (info->dram_ferr & 1)
306                                 process_ce_no_info(mci);
307                         else
308                                 process_ce(mci, info);
309                 }
310         }
311
312         if (info->dram_nerr & 2) {      /* check next error uncorrectable */
313                 error_found = 1;
314
315                 if (handle_errors) {
316                         if (info->dram_ferr & 2)
317                                 process_ue_no_info(mci);
318                         else
319                                 process_ue(mci, info);
320                 }
321         }
322
323         return error_found;
324 }
325
326 static void e7xxx_check(struct mem_ctl_info *mci)
327 {
328         struct e7xxx_error_info info;
329
330         debugf3("%s()\n", __func__);
331         e7xxx_get_error_info(mci, &info);
332         e7xxx_process_error_info(mci, &info, 1);
333 }
334
335 static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx)
336 {
337         int rc = -ENODEV;
338         int index;
339         u16 pci_data;
340         struct mem_ctl_info *mci = NULL;
341         struct e7xxx_pvt *pvt = NULL;
342         u32 drc;
343         int drc_chan = 1;       /* Number of channels 0=1chan,1=2chan */
344         int drc_drbg = 1;       /* DRB granularity 0=32mb,1=64mb */
345         int drc_ddim;           /* DRAM Data Integrity Mode 0=none,2=edac */
346         u32 dra;
347         unsigned long last_cumul_size;
348         struct e7xxx_error_info discard;
349
350         debugf0("%s(): mci\n", __func__);
351
352         /* need to find out the number of channels */
353         pci_read_config_dword(pdev, E7XXX_DRC, &drc);
354
355         /* only e7501 can be single channel */
356         if (dev_idx == E7501) {
357                 drc_chan = ((drc >> 22) & 0x1);
358                 drc_drbg = (drc >> 18) & 0x3;
359         }
360
361         drc_ddim = (drc >> 20) & 0x3;
362         mci = edac_mc_alloc(sizeof(*pvt), E7XXX_NR_CSROWS, drc_chan + 1);
363
364         if (mci == NULL) {
365                 rc = -ENOMEM;
366                 goto fail;
367         }
368
369         debugf3("%s(): init mci\n", __func__);
370         mci->mtype_cap = MEM_FLAG_RDDR;
371         mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED |
372                         EDAC_FLAG_S4ECD4ED;
373         /* FIXME - what if different memory types are in different csrows? */
374         mci->mod_name = EDAC_MOD_STR;
375         mci->mod_ver = "$Revision: 1.5.2.9 $";
376         mci->pdev = pdev;
377
378         debugf3("%s(): init pvt\n", __func__);
379         pvt = (struct e7xxx_pvt *) mci->pvt_info;
380         pvt->dev_info = &e7xxx_devs[dev_idx];
381         pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL,
382                                         pvt->dev_info->err_dev,
383                                         pvt->bridge_ck);
384
385         if (!pvt->bridge_ck) {
386                 e7xxx_printk(KERN_ERR, "error reporting device not found:"
387                         "vendor %x device 0x%x (broken BIOS?)\n",
388                         PCI_VENDOR_ID_INTEL, e7xxx_devs[dev_idx].err_dev);
389                 goto fail;
390         }
391
392         debugf3("%s(): more mci init\n", __func__);
393         mci->ctl_name = pvt->dev_info->ctl_name;
394         mci->edac_check = e7xxx_check;
395         mci->ctl_page_to_phys = ctl_page_to_phys;
396
397         /* find out the device types */
398         pci_read_config_dword(pdev, E7XXX_DRA, &dra);
399
400         /*
401          * The dram row boundary (DRB) reg values are boundary address
402          * for each DRAM row with a granularity of 32 or 64MB (single/dual
403          * channel operation).  DRB regs are cumulative; therefore DRB7 will
404          * contain the total memory contained in all eight rows.
405          */
406         for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) {
407                 u8 value;
408                 u32 cumul_size;
409                 /* mem_dev 0=x8, 1=x4 */
410                 int mem_dev = (dra >> (index * 4 + 3)) & 0x1;
411                 struct csrow_info *csrow = &mci->csrows[index];
412
413                 pci_read_config_byte(mci->pdev, E7XXX_DRB + index, &value);
414                 /* convert a 64 or 32 MiB DRB to a page size. */
415                 cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
416                 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
417                         cumul_size);
418
419                 if (cumul_size == last_cumul_size)
420                         continue;  /* not populated */
421
422                 csrow->first_page = last_cumul_size;
423                 csrow->last_page = cumul_size - 1;
424                 csrow->nr_pages = cumul_size - last_cumul_size;
425                 last_cumul_size = cumul_size;
426                 csrow->grain = 1 << 12;  /* 4KiB - resolution of CELOG */
427                 csrow->mtype = MEM_RDDR;  /* only one type supported */
428                 csrow->dtype = mem_dev ? DEV_X4 : DEV_X8;
429
430                 /*
431                  * if single channel or x8 devices then SECDED
432                  * if dual channel and x4 then S4ECD4ED
433                  */
434                 if (drc_ddim) {
435                         if (drc_chan && mem_dev) {
436                                 csrow->edac_mode = EDAC_S4ECD4ED;
437                                 mci->edac_cap |= EDAC_FLAG_S4ECD4ED;
438                         } else {
439                                 csrow->edac_mode = EDAC_SECDED;
440                                 mci->edac_cap |= EDAC_FLAG_SECDED;
441                         }
442                 } else
443                         csrow->edac_mode = EDAC_NONE;
444         }
445
446         mci->edac_cap |= EDAC_FLAG_NONE;
447
448         debugf3("%s(): tolm, remapbase, remaplimit\n", __func__);
449         /* load the top of low memory, remap base, and remap limit vars */
450         pci_read_config_word(mci->pdev, E7XXX_TOLM, &pci_data);
451         pvt->tolm = ((u32) pci_data) << 4;
452         pci_read_config_word(mci->pdev, E7XXX_REMAPBASE, &pci_data);
453         pvt->remapbase = ((u32) pci_data) << 14;
454         pci_read_config_word(mci->pdev, E7XXX_REMAPLIMIT, &pci_data);
455         pvt->remaplimit = ((u32) pci_data) << 14;
456         e7xxx_printk(KERN_INFO,
457                 "tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm,
458                 pvt->remapbase, pvt->remaplimit);
459
460         /* clear any pending errors, or initial state bits */
461         e7xxx_get_error_info(mci, &discard);
462
463         if (edac_mc_add_mc(mci) != 0) {
464                 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
465                 goto fail;
466         }
467
468         /* get this far and it's successful */
469         debugf3("%s(): success\n", __func__);
470         return 0;
471
472 fail:
473         if (mci != NULL) {
474                 if(pvt != NULL && pvt->bridge_ck)
475                         pci_dev_put(pvt->bridge_ck);
476                 edac_mc_free(mci);
477         }
478
479         return rc;
480 }
481
482 /* returns count (>= 0), or negative on error */
483 static int __devinit e7xxx_init_one(struct pci_dev *pdev,
484                 const struct pci_device_id *ent)
485 {
486         debugf0("%s()\n", __func__);
487
488         /* wake up and enable device */
489         return pci_enable_device(pdev) ?
490                 -EIO : e7xxx_probe1(pdev, ent->driver_data);
491 }
492
493 static void __devexit e7xxx_remove_one(struct pci_dev *pdev)
494 {
495         struct mem_ctl_info *mci;
496         struct e7xxx_pvt *pvt;
497
498         debugf0("%s()\n", __func__);
499
500         if ((mci = edac_mc_del_mc(pdev)) == NULL)
501                 return;
502
503         pvt = (struct e7xxx_pvt *) mci->pvt_info;
504         pci_dev_put(pvt->bridge_ck);
505         edac_mc_free(mci);
506 }
507
508 static const struct pci_device_id e7xxx_pci_tbl[] __devinitdata = {
509         {
510                 PCI_VEND_DEV(INTEL, 7205_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
511                 E7205
512         },
513         {
514                 PCI_VEND_DEV(INTEL, 7500_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
515                 E7500
516         },
517         {
518                 PCI_VEND_DEV(INTEL, 7501_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
519                 E7501
520         },
521         {
522                 PCI_VEND_DEV(INTEL, 7505_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
523                 E7505
524         },
525         {
526                 0,
527         }       /* 0 terminated list. */
528 };
529
530 MODULE_DEVICE_TABLE(pci, e7xxx_pci_tbl);
531
532 static struct pci_driver e7xxx_driver = {
533         .name = EDAC_MOD_STR,
534         .probe = e7xxx_init_one,
535         .remove = __devexit_p(e7xxx_remove_one),
536         .id_table = e7xxx_pci_tbl,
537 };
538
539 static int __init e7xxx_init(void)
540 {
541         return pci_register_driver(&e7xxx_driver);
542 }
543
544 static void __exit e7xxx_exit(void)
545 {
546         pci_unregister_driver(&e7xxx_driver);
547 }
548
549 module_init(e7xxx_init);
550 module_exit(e7xxx_exit);
551
552 MODULE_LICENSE("GPL");
553 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh et al\n"
554         "Based on.work by Dan Hollis et al");
555 MODULE_DESCRIPTION("MC support for Intel e7xxx memory controllers");