691d7067a141fef26edf727279700a0597493519
[linux-3.10.git] / drivers / edac / e7xxx_edac.c
1 /*
2  * Intel e7xxx Memory Controller kernel module
3  * (C) 2003 Linux Networx (http://lnxi.com)
4  * This file may be distributed under the terms of the
5  * GNU General Public License.
6  *
7  * See "enum e7xxx_chips" below for supported chipsets
8  *
9  * Written by Thayne Harbaugh
10  * Based on work by Dan Hollis <goemon at anime dot net> and others.
11  *      http://www.anime.net/~goemon/linux-ecc/
12  *
13  * Datasheet:
14  *      http://www.intel.com/content/www/us/en/chipsets/e7501-chipset-memory-controller-hub-datasheet.html
15  *
16  * Contributors:
17  *      Eric Biederman (Linux Networx)
18  *      Tom Zimmerman (Linux Networx)
19  *      Jim Garlick (Lawrence Livermore National Labs)
20  *      Dave Peterson (Lawrence Livermore National Labs)
21  *      That One Guy (Some other place)
22  *      Wang Zhenyu (intel.com)
23  *
24  * $Id: edac_e7xxx.c,v 1.5.2.9 2005/10/05 00:43:44 dsp_llnl Exp $
25  *
26  */
27
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/pci.h>
31 #include <linux/pci_ids.h>
32 #include <linux/edac.h>
33 #include "edac_core.h"
34
35 #define E7XXX_REVISION " Ver: 2.0.2"
36 #define EDAC_MOD_STR    "e7xxx_edac"
37
38 #define e7xxx_printk(level, fmt, arg...) \
39         edac_printk(level, "e7xxx", fmt, ##arg)
40
41 #define e7xxx_mc_printk(mci, level, fmt, arg...) \
42         edac_mc_chipset_printk(mci, level, "e7xxx", fmt, ##arg)
43
44 #ifndef PCI_DEVICE_ID_INTEL_7205_0
45 #define PCI_DEVICE_ID_INTEL_7205_0      0x255d
46 #endif                          /* PCI_DEVICE_ID_INTEL_7205_0 */
47
48 #ifndef PCI_DEVICE_ID_INTEL_7205_1_ERR
49 #define PCI_DEVICE_ID_INTEL_7205_1_ERR  0x2551
50 #endif                          /* PCI_DEVICE_ID_INTEL_7205_1_ERR */
51
52 #ifndef PCI_DEVICE_ID_INTEL_7500_0
53 #define PCI_DEVICE_ID_INTEL_7500_0      0x2540
54 #endif                          /* PCI_DEVICE_ID_INTEL_7500_0 */
55
56 #ifndef PCI_DEVICE_ID_INTEL_7500_1_ERR
57 #define PCI_DEVICE_ID_INTEL_7500_1_ERR  0x2541
58 #endif                          /* PCI_DEVICE_ID_INTEL_7500_1_ERR */
59
60 #ifndef PCI_DEVICE_ID_INTEL_7501_0
61 #define PCI_DEVICE_ID_INTEL_7501_0      0x254c
62 #endif                          /* PCI_DEVICE_ID_INTEL_7501_0 */
63
64 #ifndef PCI_DEVICE_ID_INTEL_7501_1_ERR
65 #define PCI_DEVICE_ID_INTEL_7501_1_ERR  0x2541
66 #endif                          /* PCI_DEVICE_ID_INTEL_7501_1_ERR */
67
68 #ifndef PCI_DEVICE_ID_INTEL_7505_0
69 #define PCI_DEVICE_ID_INTEL_7505_0      0x2550
70 #endif                          /* PCI_DEVICE_ID_INTEL_7505_0 */
71
72 #ifndef PCI_DEVICE_ID_INTEL_7505_1_ERR
73 #define PCI_DEVICE_ID_INTEL_7505_1_ERR  0x2551
74 #endif                          /* PCI_DEVICE_ID_INTEL_7505_1_ERR */
75
76 #define E7XXX_NR_CSROWS         8       /* number of csrows */
77 #define E7XXX_NR_DIMMS          8       /* 2 channels, 4 dimms/channel */
78
79 /* E7XXX register addresses - device 0 function 0 */
80 #define E7XXX_DRB               0x60    /* DRAM row boundary register (8b) */
81 #define E7XXX_DRA               0x70    /* DRAM row attribute register (8b) */
82                                         /*
83                                          * 31   Device width row 7 0=x8 1=x4
84                                          * 27   Device width row 6
85                                          * 23   Device width row 5
86                                          * 19   Device width row 4
87                                          * 15   Device width row 3
88                                          * 11   Device width row 2
89                                          *  7   Device width row 1
90                                          *  3   Device width row 0
91                                          */
92 #define E7XXX_DRC               0x7C    /* DRAM controller mode reg (32b) */
93                                         /*
94                                          * 22    Number channels 0=1,1=2
95                                          * 19:18 DRB Granularity 32/64MB
96                                          */
97 #define E7XXX_TOLM              0xC4    /* DRAM top of low memory reg (16b) */
98 #define E7XXX_REMAPBASE         0xC6    /* DRAM remap base address reg (16b) */
99 #define E7XXX_REMAPLIMIT        0xC8    /* DRAM remap limit address reg (16b) */
100
101 /* E7XXX register addresses - device 0 function 1 */
102 #define E7XXX_DRAM_FERR         0x80    /* DRAM first error register (8b) */
103 #define E7XXX_DRAM_NERR         0x82    /* DRAM next error register (8b) */
104 #define E7XXX_DRAM_CELOG_ADD    0xA0    /* DRAM first correctable memory */
105                                         /*     error address register (32b) */
106                                         /*
107                                          * 31:28 Reserved
108                                          * 27:6  CE address (4k block 33:12)
109                                          *  5:0  Reserved
110                                          */
111 #define E7XXX_DRAM_UELOG_ADD    0xB0    /* DRAM first uncorrectable memory */
112                                         /*     error address register (32b) */
113                                         /*
114                                          * 31:28 Reserved
115                                          * 27:6  CE address (4k block 33:12)
116                                          *  5:0  Reserved
117                                          */
118 #define E7XXX_DRAM_CELOG_SYNDROME 0xD0  /* DRAM first correctable memory */
119                                         /*     error syndrome register (16b) */
120
121 enum e7xxx_chips {
122         E7500 = 0,
123         E7501,
124         E7505,
125         E7205,
126 };
127
128 struct e7xxx_pvt {
129         struct pci_dev *bridge_ck;
130         u32 tolm;
131         u32 remapbase;
132         u32 remaplimit;
133         const struct e7xxx_dev_info *dev_info;
134 };
135
136 struct e7xxx_dev_info {
137         u16 err_dev;
138         const char *ctl_name;
139 };
140
141 struct e7xxx_error_info {
142         u8 dram_ferr;
143         u8 dram_nerr;
144         u32 dram_celog_add;
145         u16 dram_celog_syndrome;
146         u32 dram_uelog_add;
147 };
148
149 static struct edac_pci_ctl_info *e7xxx_pci;
150
151 static const struct e7xxx_dev_info e7xxx_devs[] = {
152         [E7500] = {
153                 .err_dev = PCI_DEVICE_ID_INTEL_7500_1_ERR,
154                 .ctl_name = "E7500"},
155         [E7501] = {
156                 .err_dev = PCI_DEVICE_ID_INTEL_7501_1_ERR,
157                 .ctl_name = "E7501"},
158         [E7505] = {
159                 .err_dev = PCI_DEVICE_ID_INTEL_7505_1_ERR,
160                 .ctl_name = "E7505"},
161         [E7205] = {
162                 .err_dev = PCI_DEVICE_ID_INTEL_7205_1_ERR,
163                 .ctl_name = "E7205"},
164 };
165
166 /* FIXME - is this valid for both SECDED and S4ECD4ED? */
167 static inline int e7xxx_find_channel(u16 syndrome)
168 {
169         debugf3("\n");
170
171         if ((syndrome & 0xff00) == 0)
172                 return 0;
173
174         if ((syndrome & 0x00ff) == 0)
175                 return 1;
176
177         if ((syndrome & 0xf000) == 0 || (syndrome & 0x0f00) == 0)
178                 return 0;
179
180         return 1;
181 }
182
183 static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci,
184                                 unsigned long page)
185 {
186         u32 remap;
187         struct e7xxx_pvt *pvt = (struct e7xxx_pvt *)mci->pvt_info;
188
189         debugf3("\n");
190
191         if ((page < pvt->tolm) ||
192                 ((page >= 0x100000) && (page < pvt->remapbase)))
193                 return page;
194
195         remap = (page - pvt->tolm) + pvt->remapbase;
196
197         if (remap < pvt->remaplimit)
198                 return remap;
199
200         e7xxx_printk(KERN_ERR, "Invalid page %lx - out of range\n", page);
201         return pvt->tolm - 1;
202 }
203
204 static void process_ce(struct mem_ctl_info *mci, struct e7xxx_error_info *info)
205 {
206         u32 error_1b, page;
207         u16 syndrome;
208         int row;
209         int channel;
210
211         debugf3("\n");
212         /* read the error address */
213         error_1b = info->dram_celog_add;
214         /* FIXME - should use PAGE_SHIFT */
215         page = error_1b >> 6;   /* convert the address to 4k page */
216         /* read the syndrome */
217         syndrome = info->dram_celog_syndrome;
218         /* FIXME - check for -1 */
219         row = edac_mc_find_csrow_by_page(mci, page);
220         /* convert syndrome to channel */
221         channel = e7xxx_find_channel(syndrome);
222         edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, page, 0, syndrome,
223                              row, channel, -1, "e7xxx CE", "", NULL);
224 }
225
226 static void process_ce_no_info(struct mem_ctl_info *mci)
227 {
228         debugf3("\n");
229         edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 0, 0, 0, -1, -1, -1,
230                              "e7xxx CE log register overflow", "", NULL);
231 }
232
233 static void process_ue(struct mem_ctl_info *mci, struct e7xxx_error_info *info)
234 {
235         u32 error_2b, block_page;
236         int row;
237
238         debugf3("\n");
239         /* read the error address */
240         error_2b = info->dram_uelog_add;
241         /* FIXME - should use PAGE_SHIFT */
242         block_page = error_2b >> 6;     /* convert to 4k address */
243         row = edac_mc_find_csrow_by_page(mci, block_page);
244
245         edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, block_page, 0, 0,
246                              row, -1, -1, "e7xxx UE", "", NULL);
247 }
248
249 static void process_ue_no_info(struct mem_ctl_info *mci)
250 {
251         debugf3("\n");
252
253         edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 0, 0, 0, -1, -1, -1,
254                              "e7xxx UE log register overflow", "", NULL);
255 }
256
257 static void e7xxx_get_error_info(struct mem_ctl_info *mci,
258                                  struct e7xxx_error_info *info)
259 {
260         struct e7xxx_pvt *pvt;
261
262         pvt = (struct e7xxx_pvt *)mci->pvt_info;
263         pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_FERR, &info->dram_ferr);
264         pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_NERR, &info->dram_nerr);
265
266         if ((info->dram_ferr & 1) || (info->dram_nerr & 1)) {
267                 pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_CELOG_ADD,
268                                 &info->dram_celog_add);
269                 pci_read_config_word(pvt->bridge_ck,
270                                 E7XXX_DRAM_CELOG_SYNDROME,
271                                 &info->dram_celog_syndrome);
272         }
273
274         if ((info->dram_ferr & 2) || (info->dram_nerr & 2))
275                 pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_UELOG_ADD,
276                                 &info->dram_uelog_add);
277
278         if (info->dram_ferr & 3)
279                 pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_FERR, 0x03, 0x03);
280
281         if (info->dram_nerr & 3)
282                 pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_NERR, 0x03, 0x03);
283 }
284
285 static int e7xxx_process_error_info(struct mem_ctl_info *mci,
286                                 struct e7xxx_error_info *info,
287                                 int handle_errors)
288 {
289         int error_found;
290
291         error_found = 0;
292
293         /* decode and report errors */
294         if (info->dram_ferr & 1) {      /* check first error correctable */
295                 error_found = 1;
296
297                 if (handle_errors)
298                         process_ce(mci, info);
299         }
300
301         if (info->dram_ferr & 2) {      /* check first error uncorrectable */
302                 error_found = 1;
303
304                 if (handle_errors)
305                         process_ue(mci, info);
306         }
307
308         if (info->dram_nerr & 1) {      /* check next error correctable */
309                 error_found = 1;
310
311                 if (handle_errors) {
312                         if (info->dram_ferr & 1)
313                                 process_ce_no_info(mci);
314                         else
315                                 process_ce(mci, info);
316                 }
317         }
318
319         if (info->dram_nerr & 2) {      /* check next error uncorrectable */
320                 error_found = 1;
321
322                 if (handle_errors) {
323                         if (info->dram_ferr & 2)
324                                 process_ue_no_info(mci);
325                         else
326                                 process_ue(mci, info);
327                 }
328         }
329
330         return error_found;
331 }
332
333 static void e7xxx_check(struct mem_ctl_info *mci)
334 {
335         struct e7xxx_error_info info;
336
337         debugf3("\n");
338         e7xxx_get_error_info(mci, &info);
339         e7xxx_process_error_info(mci, &info, 1);
340 }
341
342 /* Return 1 if dual channel mode is active.  Else return 0. */
343 static inline int dual_channel_active(u32 drc, int dev_idx)
344 {
345         return (dev_idx == E7501) ? ((drc >> 22) & 0x1) : 1;
346 }
347
348 /* Return DRB granularity (0=32mb, 1=64mb). */
349 static inline int drb_granularity(u32 drc, int dev_idx)
350 {
351         /* only e7501 can be single channel */
352         return (dev_idx == E7501) ? ((drc >> 18) & 0x3) : 1;
353 }
354
355 static void e7xxx_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
356                         int dev_idx, u32 drc)
357 {
358         unsigned long last_cumul_size;
359         int index, j;
360         u8 value;
361         u32 dra, cumul_size, nr_pages;
362         int drc_chan, drc_drbg, drc_ddim, mem_dev;
363         struct csrow_info *csrow;
364         struct dimm_info *dimm;
365         enum edac_type edac_mode;
366
367         pci_read_config_dword(pdev, E7XXX_DRA, &dra);
368         drc_chan = dual_channel_active(drc, dev_idx);
369         drc_drbg = drb_granularity(drc, dev_idx);
370         drc_ddim = (drc >> 20) & 0x3;
371         last_cumul_size = 0;
372
373         /* The dram row boundary (DRB) reg values are boundary address
374          * for each DRAM row with a granularity of 32 or 64MB (single/dual
375          * channel operation).  DRB regs are cumulative; therefore DRB7 will
376          * contain the total memory contained in all eight rows.
377          */
378         for (index = 0; index < mci->nr_csrows; index++) {
379                 /* mem_dev 0=x8, 1=x4 */
380                 mem_dev = (dra >> (index * 4 + 3)) & 0x1;
381                 csrow = mci->csrows[index];
382
383                 pci_read_config_byte(pdev, E7XXX_DRB + index, &value);
384                 /* convert a 64 or 32 MiB DRB to a page size. */
385                 cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
386                 debugf3("(%d) cumul_size 0x%x\n", index,
387                         cumul_size);
388                 if (cumul_size == last_cumul_size)
389                         continue;       /* not populated */
390
391                 csrow->first_page = last_cumul_size;
392                 csrow->last_page = cumul_size - 1;
393                 nr_pages = cumul_size - last_cumul_size;
394                 last_cumul_size = cumul_size;
395
396                 /*
397                 * if single channel or x8 devices then SECDED
398                 * if dual channel and x4 then S4ECD4ED
399                 */
400                 if (drc_ddim) {
401                         if (drc_chan && mem_dev) {
402                                 edac_mode = EDAC_S4ECD4ED;
403                                 mci->edac_cap |= EDAC_FLAG_S4ECD4ED;
404                         } else {
405                                 edac_mode = EDAC_SECDED;
406                                 mci->edac_cap |= EDAC_FLAG_SECDED;
407                         }
408                 } else
409                         edac_mode = EDAC_NONE;
410
411                 for (j = 0; j < drc_chan + 1; j++) {
412                         dimm = csrow->channels[j]->dimm;
413
414                         dimm->nr_pages = nr_pages / (drc_chan + 1);
415                         dimm->grain = 1 << 12;  /* 4KiB - resolution of CELOG */
416                         dimm->mtype = MEM_RDDR; /* only one type supported */
417                         dimm->dtype = mem_dev ? DEV_X4 : DEV_X8;
418                         dimm->edac_mode = edac_mode;
419                 }
420         }
421 }
422
423 static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx)
424 {
425         u16 pci_data;
426         struct mem_ctl_info *mci = NULL;
427         struct edac_mc_layer layers[2];
428         struct e7xxx_pvt *pvt = NULL;
429         u32 drc;
430         int drc_chan;
431         struct e7xxx_error_info discard;
432
433         debugf0("mci\n");
434
435         pci_read_config_dword(pdev, E7XXX_DRC, &drc);
436
437         drc_chan = dual_channel_active(drc, dev_idx);
438         /*
439          * According with the datasheet, this device has a maximum of
440          * 4 DIMMS per channel, either single-rank or dual-rank. So, the
441          * total amount of dimms is 8 (E7XXX_NR_DIMMS).
442          * That means that the DIMM is mapped as CSROWs, and the channel
443          * will map the rank. So, an error to either channel should be
444          * attributed to the same dimm.
445          */
446         layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
447         layers[0].size = E7XXX_NR_CSROWS;
448         layers[0].is_virt_csrow = true;
449         layers[1].type = EDAC_MC_LAYER_CHANNEL;
450         layers[1].size = drc_chan + 1;
451         layers[1].is_virt_csrow = false;
452         mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
453         if (mci == NULL)
454                 return -ENOMEM;
455
456         debugf3("init mci\n");
457         mci->mtype_cap = MEM_FLAG_RDDR;
458         mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED |
459                 EDAC_FLAG_S4ECD4ED;
460         /* FIXME - what if different memory types are in different csrows? */
461         mci->mod_name = EDAC_MOD_STR;
462         mci->mod_ver = E7XXX_REVISION;
463         mci->pdev = &pdev->dev;
464         debugf3("init pvt\n");
465         pvt = (struct e7xxx_pvt *)mci->pvt_info;
466         pvt->dev_info = &e7xxx_devs[dev_idx];
467         pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL,
468                                         pvt->dev_info->err_dev, pvt->bridge_ck);
469
470         if (!pvt->bridge_ck) {
471                 e7xxx_printk(KERN_ERR, "error reporting device not found:"
472                         "vendor %x device 0x%x (broken BIOS?)\n",
473                         PCI_VENDOR_ID_INTEL, e7xxx_devs[dev_idx].err_dev);
474                 goto fail0;
475         }
476
477         debugf3("more mci init\n");
478         mci->ctl_name = pvt->dev_info->ctl_name;
479         mci->dev_name = pci_name(pdev);
480         mci->edac_check = e7xxx_check;
481         mci->ctl_page_to_phys = ctl_page_to_phys;
482         e7xxx_init_csrows(mci, pdev, dev_idx, drc);
483         mci->edac_cap |= EDAC_FLAG_NONE;
484         debugf3("tolm, remapbase, remaplimit\n");
485         /* load the top of low memory, remap base, and remap limit vars */
486         pci_read_config_word(pdev, E7XXX_TOLM, &pci_data);
487         pvt->tolm = ((u32) pci_data) << 4;
488         pci_read_config_word(pdev, E7XXX_REMAPBASE, &pci_data);
489         pvt->remapbase = ((u32) pci_data) << 14;
490         pci_read_config_word(pdev, E7XXX_REMAPLIMIT, &pci_data);
491         pvt->remaplimit = ((u32) pci_data) << 14;
492         e7xxx_printk(KERN_INFO,
493                 "tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm,
494                 pvt->remapbase, pvt->remaplimit);
495
496         /* clear any pending errors, or initial state bits */
497         e7xxx_get_error_info(mci, &discard);
498
499         /* Here we assume that we will never see multiple instances of this
500          * type of memory controller.  The ID is therefore hardcoded to 0.
501          */
502         if (edac_mc_add_mc(mci)) {
503                 debugf3("failed edac_mc_add_mc()\n");
504                 goto fail1;
505         }
506
507         /* allocating generic PCI control info */
508         e7xxx_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
509         if (!e7xxx_pci) {
510                 printk(KERN_WARNING
511                         "%s(): Unable to create PCI control\n",
512                         __func__);
513                 printk(KERN_WARNING
514                         "%s(): PCI error report via EDAC not setup\n",
515                         __func__);
516         }
517
518         /* get this far and it's successful */
519         debugf3("success\n");
520         return 0;
521
522 fail1:
523         pci_dev_put(pvt->bridge_ck);
524
525 fail0:
526         edac_mc_free(mci);
527
528         return -ENODEV;
529 }
530
531 /* returns count (>= 0), or negative on error */
532 static int __devinit e7xxx_init_one(struct pci_dev *pdev,
533                                 const struct pci_device_id *ent)
534 {
535         debugf0("\n");
536
537         /* wake up and enable device */
538         return pci_enable_device(pdev) ?
539                 -EIO : e7xxx_probe1(pdev, ent->driver_data);
540 }
541
542 static void __devexit e7xxx_remove_one(struct pci_dev *pdev)
543 {
544         struct mem_ctl_info *mci;
545         struct e7xxx_pvt *pvt;
546
547         debugf0("\n");
548
549         if (e7xxx_pci)
550                 edac_pci_release_generic_ctl(e7xxx_pci);
551
552         if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
553                 return;
554
555         pvt = (struct e7xxx_pvt *)mci->pvt_info;
556         pci_dev_put(pvt->bridge_ck);
557         edac_mc_free(mci);
558 }
559
560 static DEFINE_PCI_DEVICE_TABLE(e7xxx_pci_tbl) = {
561         {
562          PCI_VEND_DEV(INTEL, 7205_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
563          E7205},
564         {
565          PCI_VEND_DEV(INTEL, 7500_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
566          E7500},
567         {
568          PCI_VEND_DEV(INTEL, 7501_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
569          E7501},
570         {
571          PCI_VEND_DEV(INTEL, 7505_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
572          E7505},
573         {
574          0,
575          }                      /* 0 terminated list. */
576 };
577
578 MODULE_DEVICE_TABLE(pci, e7xxx_pci_tbl);
579
580 static struct pci_driver e7xxx_driver = {
581         .name = EDAC_MOD_STR,
582         .probe = e7xxx_init_one,
583         .remove = __devexit_p(e7xxx_remove_one),
584         .id_table = e7xxx_pci_tbl,
585 };
586
587 static int __init e7xxx_init(void)
588 {
589        /* Ensure that the OPSTATE is set correctly for POLL or NMI */
590        opstate_init();
591
592         return pci_register_driver(&e7xxx_driver);
593 }
594
595 static void __exit e7xxx_exit(void)
596 {
597         pci_unregister_driver(&e7xxx_driver);
598 }
599
600 module_init(e7xxx_init);
601 module_exit(e7xxx_exit);
602
603 MODULE_LICENSE("GPL");
604 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh et al\n"
605                 "Based on.work by Dan Hollis et al");
606 MODULE_DESCRIPTION("MC support for Intel e7xxx memory controllers");
607 module_param(edac_op_state, int, 0444);
608 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");