drivers/edac: updated PCI monitoring
[linux-3.10.git] / drivers / edac / e752x_edac.c
1 /*
2  * Intel e752x Memory Controller kernel module
3  * (C) 2004 Linux Networx (http://lnxi.com)
4  * This file may be distributed under the terms of the
5  * GNU General Public License.
6  *
7  * See "enum e752x_chips" below for supported chipsets
8  *
9  * Written by Tom Zimmerman
10  *
11  * Contributors:
12  *      Thayne Harbaugh at realmsys.com (?)
13  *      Wang Zhenyu at intel.com
14  *      Dave Jiang at mvista.com
15  *
16  * $Id: edac_e752x.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/pci.h>
23 #include <linux/pci_ids.h>
24 #include <linux/slab.h>
25 #include <linux/edac.h>
26 #include "edac_core.h"
27
28 #define E752X_REVISION  " Ver: 2.0.2 " __DATE__
29 #define EDAC_MOD_STR    "e752x_edac"
30
31 static int force_function_unhide;
32
33 static struct edac_pci_ctl_info *e752x_pci;
34
35 #define e752x_printk(level, fmt, arg...) \
36         edac_printk(level, "e752x", fmt, ##arg)
37
38 #define e752x_mc_printk(mci, level, fmt, arg...) \
39         edac_mc_chipset_printk(mci, level, "e752x", fmt, ##arg)
40
41 #ifndef PCI_DEVICE_ID_INTEL_7520_0
42 #define PCI_DEVICE_ID_INTEL_7520_0      0x3590
43 #endif                          /* PCI_DEVICE_ID_INTEL_7520_0      */
44
45 #ifndef PCI_DEVICE_ID_INTEL_7520_1_ERR
46 #define PCI_DEVICE_ID_INTEL_7520_1_ERR  0x3591
47 #endif                          /* PCI_DEVICE_ID_INTEL_7520_1_ERR  */
48
49 #ifndef PCI_DEVICE_ID_INTEL_7525_0
50 #define PCI_DEVICE_ID_INTEL_7525_0      0x359E
51 #endif                          /* PCI_DEVICE_ID_INTEL_7525_0      */
52
53 #ifndef PCI_DEVICE_ID_INTEL_7525_1_ERR
54 #define PCI_DEVICE_ID_INTEL_7525_1_ERR  0x3593
55 #endif                          /* PCI_DEVICE_ID_INTEL_7525_1_ERR  */
56
57 #ifndef PCI_DEVICE_ID_INTEL_7320_0
58 #define PCI_DEVICE_ID_INTEL_7320_0      0x3592
59 #endif                          /* PCI_DEVICE_ID_INTEL_7320_0 */
60
61 #ifndef PCI_DEVICE_ID_INTEL_7320_1_ERR
62 #define PCI_DEVICE_ID_INTEL_7320_1_ERR  0x3593
63 #endif                          /* PCI_DEVICE_ID_INTEL_7320_1_ERR */
64
65 #define E752X_NR_CSROWS         8       /* number of csrows */
66
67 /* E752X register addresses - device 0 function 0 */
68 #define E752X_DRB               0x60    /* DRAM row boundary register (8b) */
69 #define E752X_DRA               0x70    /* DRAM row attribute register (8b) */
70                                         /*
71                                          * 31:30   Device width row 7
72                                          *      01=x8 10=x4 11=x8 DDR2
73                                          * 27:26   Device width row 6
74                                          * 23:22   Device width row 5
75                                          * 19:20   Device width row 4
76                                          * 15:14   Device width row 3
77                                          * 11:10   Device width row 2
78                                          *  7:6    Device width row 1
79                                          *  3:2    Device width row 0
80                                          */
81 #define E752X_DRC               0x7C    /* DRAM controller mode reg (32b) */
82                                         /* FIXME:IS THIS RIGHT? */
83                                         /*
84                                          * 22    Number channels 0=1,1=2
85                                          * 19:18 DRB Granularity 32/64MB
86                                          */
87 #define E752X_DRM               0x80    /* Dimm mapping register */
88 #define E752X_DDRCSR            0x9A    /* DDR control and status reg (16b) */
89                                         /*
90                                          * 14:12 1 single A, 2 single B, 3 dual
91                                          */
92 #define E752X_TOLM              0xC4    /* DRAM top of low memory reg (16b) */
93 #define E752X_REMAPBASE         0xC6    /* DRAM remap base address reg (16b) */
94 #define E752X_REMAPLIMIT        0xC8    /* DRAM remap limit address reg (16b) */
95 #define E752X_REMAPOFFSET       0xCA    /* DRAM remap limit offset reg (16b) */
96
97 /* E752X register addresses - device 0 function 1 */
98 #define E752X_FERR_GLOBAL       0x40    /* Global first error register (32b) */
99 #define E752X_NERR_GLOBAL       0x44    /* Global next error register (32b) */
100 #define E752X_HI_FERR           0x50    /* Hub interface first error reg (8b) */
101 #define E752X_HI_NERR           0x52    /* Hub interface next error reg (8b) */
102 #define E752X_HI_ERRMASK        0x54    /* Hub interface error mask reg (8b) */
103 #define E752X_HI_SMICMD         0x5A    /* Hub interface SMI command reg (8b) */
104 #define E752X_SYSBUS_FERR       0x60    /* System buss first error reg (16b) */
105 #define E752X_SYSBUS_NERR       0x62    /* System buss next error reg (16b) */
106 #define E752X_SYSBUS_ERRMASK    0x64    /* System buss error mask reg (16b) */
107 #define E752X_SYSBUS_SMICMD     0x6A    /* System buss SMI command reg (16b) */
108 #define E752X_BUF_FERR          0x70    /* Memory buffer first error reg (8b) */
109 #define E752X_BUF_NERR          0x72    /* Memory buffer next error reg (8b) */
110 #define E752X_BUF_ERRMASK       0x74    /* Memory buffer error mask reg (8b) */
111 #define E752X_BUF_SMICMD        0x7A    /* Memory buffer SMI command reg (8b) */
112 #define E752X_DRAM_FERR         0x80    /* DRAM first error register (16b) */
113 #define E752X_DRAM_NERR         0x82    /* DRAM next error register (16b) */
114 #define E752X_DRAM_ERRMASK      0x84    /* DRAM error mask register (8b) */
115 #define E752X_DRAM_SMICMD       0x8A    /* DRAM SMI command register (8b) */
116 #define E752X_DRAM_RETR_ADD     0xAC    /* DRAM Retry address register (32b) */
117 #define E752X_DRAM_SEC1_ADD     0xA0    /* DRAM first correctable memory */
118                                         /*     error address register (32b) */
119                                         /*
120                                          * 31    Reserved
121                                          * 30:2  CE address (64 byte block 34:6)
122                                          * 1     Reserved
123                                          * 0     HiLoCS
124                                          */
125 #define E752X_DRAM_SEC2_ADD     0xC8    /* DRAM first correctable memory */
126                                         /*     error address register (32b) */
127                                         /*
128                                          * 31    Reserved
129                                          * 30:2  CE address (64 byte block 34:6)
130                                          * 1     Reserved
131                                          * 0     HiLoCS
132                                          */
133 #define E752X_DRAM_DED_ADD      0xA4    /* DRAM first uncorrectable memory */
134                                         /*     error address register (32b) */
135                                         /*
136                                          * 31    Reserved
137                                          * 30:2  CE address (64 byte block 34:6)
138                                          * 1     Reserved
139                                          * 0     HiLoCS
140                                          */
141 #define E752X_DRAM_SCRB_ADD     0xA8    /* DRAM first uncorrectable scrub memory */
142                                         /*     error address register (32b) */
143                                         /*
144                                          * 31    Reserved
145                                          * 30:2  CE address (64 byte block 34:6)
146                                          * 1     Reserved
147                                          * 0     HiLoCS
148                                          */
149 #define E752X_DRAM_SEC1_SYNDROME 0xC4   /* DRAM first correctable memory */
150                                         /*     error syndrome register (16b) */
151 #define E752X_DRAM_SEC2_SYNDROME 0xC6   /* DRAM second correctable memory */
152                                         /*     error syndrome register (16b) */
153 #define E752X_DEVPRES1          0xF4    /* Device Present 1 register (8b) */
154
155 /* ICH5R register addresses - device 30 function 0 */
156 #define ICH5R_PCI_STAT          0x06    /* PCI status register (16b) */
157 #define ICH5R_PCI_2ND_STAT      0x1E    /* PCI status secondary reg (16b) */
158 #define ICH5R_PCI_BRIDGE_CTL    0x3E    /* PCI bridge control register (16b) */
159
160 enum e752x_chips {
161         E7520 = 0,
162         E7525 = 1,
163         E7320 = 2
164 };
165
166 struct e752x_pvt {
167         struct pci_dev *bridge_ck;
168         struct pci_dev *dev_d0f0;
169         struct pci_dev *dev_d0f1;
170         u32 tolm;
171         u32 remapbase;
172         u32 remaplimit;
173         int mc_symmetric;
174         u8 map[8];
175         int map_type;
176         const struct e752x_dev_info *dev_info;
177 };
178
179 struct e752x_dev_info {
180         u16 err_dev;
181         u16 ctl_dev;
182         const char *ctl_name;
183 };
184
185 struct e752x_error_info {
186         u32 ferr_global;
187         u32 nerr_global;
188         u8 hi_ferr;
189         u8 hi_nerr;
190         u16 sysbus_ferr;
191         u16 sysbus_nerr;
192         u8 buf_ferr;
193         u8 buf_nerr;
194         u16 dram_ferr;
195         u16 dram_nerr;
196         u32 dram_sec1_add;
197         u32 dram_sec2_add;
198         u16 dram_sec1_syndrome;
199         u16 dram_sec2_syndrome;
200         u32 dram_ded_add;
201         u32 dram_scrb_add;
202         u32 dram_retr_add;
203 };
204
205 static const struct e752x_dev_info e752x_devs[] = {
206         [E7520] = {
207                 .err_dev = PCI_DEVICE_ID_INTEL_7520_1_ERR,
208                 .ctl_dev = PCI_DEVICE_ID_INTEL_7520_0,
209                 .ctl_name = "E7520"
210         },
211         [E7525] = {
212                 .err_dev = PCI_DEVICE_ID_INTEL_7525_1_ERR,
213                 .ctl_dev = PCI_DEVICE_ID_INTEL_7525_0,
214                 .ctl_name = "E7525"
215         },
216         [E7320] = {
217                 .err_dev = PCI_DEVICE_ID_INTEL_7320_1_ERR,
218                 .ctl_dev = PCI_DEVICE_ID_INTEL_7320_0,
219                 .ctl_name = "E7320"
220         },
221 };
222
223 static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci,
224                 unsigned long page)
225 {
226         u32 remap;
227         struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
228
229         debugf3("%s()\n", __func__);
230
231         if (page < pvt->tolm)
232                 return page;
233
234         if ((page >= 0x100000) && (page < pvt->remapbase))
235                 return page;
236
237         remap = (page - pvt->tolm) + pvt->remapbase;
238
239         if (remap < pvt->remaplimit)
240                 return remap;
241
242         e752x_printk(KERN_ERR, "Invalid page %lx - out of range\n", page);
243         return pvt->tolm - 1;
244 }
245
246 static void do_process_ce(struct mem_ctl_info *mci, u16 error_one,
247                 u32 sec1_add, u16 sec1_syndrome)
248 {
249         u32 page;
250         int row;
251         int channel;
252         int i;
253         struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
254
255         debugf3("%s()\n", __func__);
256
257         /* convert the addr to 4k page */
258         page = sec1_add >> (PAGE_SHIFT - 4);
259
260         /* FIXME - check for -1 */
261         if (pvt->mc_symmetric) {
262                 /* chip select are bits 14 & 13 */
263                 row = ((page >> 1) & 3);
264                 e752x_printk(KERN_WARNING,
265                         "Test row %d Table %d %d %d %d %d %d %d %d\n", row,
266                         pvt->map[0], pvt->map[1], pvt->map[2], pvt->map[3],
267                         pvt->map[4], pvt->map[5], pvt->map[6], pvt->map[7]);
268
269                 /* test for channel remapping */
270                 for (i = 0; i < 8; i++) {
271                         if (pvt->map[i] == row)
272                                 break;
273                 }
274
275                 e752x_printk(KERN_WARNING, "Test computed row %d\n", i);
276
277                 if (i < 8)
278                         row = i;
279                 else
280                         e752x_mc_printk(mci, KERN_WARNING,
281                                 "row %d not found in remap table\n", row);
282         } else
283                 row = edac_mc_find_csrow_by_page(mci, page);
284
285         /* 0 = channel A, 1 = channel B */
286         channel = !(error_one & 1);
287
288         if (!pvt->map_type)
289                 row = 7 - row;
290
291         /* e752x mc reads 34:6 of the DRAM linear address */
292         edac_mc_handle_ce(mci, page, offset_in_page(sec1_add << 4),
293                         sec1_syndrome, row, channel, "e752x CE");
294 }
295
296 static inline void process_ce(struct mem_ctl_info *mci, u16 error_one,
297                 u32 sec1_add, u16 sec1_syndrome, int *error_found,
298                 int handle_error)
299 {
300         *error_found = 1;
301
302         if (handle_error)
303                 do_process_ce(mci, error_one, sec1_add, sec1_syndrome);
304 }
305
306 static void do_process_ue(struct mem_ctl_info *mci, u16 error_one,
307                 u32 ded_add, u32 scrb_add)
308 {
309         u32 error_2b, block_page;
310         int row;
311         struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
312
313         debugf3("%s()\n", __func__);
314
315         if (error_one & 0x0202) {
316                 error_2b = ded_add;
317
318                 /* convert to 4k address */
319                 block_page = error_2b >> (PAGE_SHIFT - 4);
320
321                 row = pvt->mc_symmetric ?
322                         /* chip select are bits 14 & 13 */
323                         ((block_page >> 1) & 3) :
324                         edac_mc_find_csrow_by_page(mci, block_page);
325
326                 /* e752x mc reads 34:6 of the DRAM linear address */
327                 edac_mc_handle_ue(mci, block_page,
328                                         offset_in_page(error_2b << 4),
329                                         row, "e752x UE from Read");
330         }
331         if (error_one & 0x0404) {
332                 error_2b = scrb_add;
333
334                 /* convert to 4k address */
335                 block_page = error_2b >> (PAGE_SHIFT - 4);
336
337                 row = pvt->mc_symmetric ?
338                         /* chip select are bits 14 & 13 */
339                         ((block_page >> 1) & 3) :
340                         edac_mc_find_csrow_by_page(mci, block_page);
341
342                 /* e752x mc reads 34:6 of the DRAM linear address */
343                 edac_mc_handle_ue(mci, block_page,
344                                         offset_in_page(error_2b << 4),
345                                         row, "e752x UE from Scruber");
346         }
347 }
348
349 static inline void process_ue(struct mem_ctl_info *mci, u16 error_one,
350                 u32 ded_add, u32 scrb_add, int *error_found, int handle_error)
351 {
352         *error_found = 1;
353
354         if (handle_error)
355                 do_process_ue(mci, error_one, ded_add, scrb_add);
356 }
357
358 static inline void process_ue_no_info_wr(struct mem_ctl_info *mci,
359                 int *error_found, int handle_error)
360 {
361         *error_found = 1;
362
363         if (!handle_error)
364                 return;
365
366         debugf3("%s()\n", __func__);
367         edac_mc_handle_ue_no_info(mci, "e752x UE log memory write");
368 }
369
370 static void do_process_ded_retry(struct mem_ctl_info *mci, u16 error,
371                 u32 retry_add)
372 {
373         u32 error_1b, page;
374         int row;
375         struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
376
377         error_1b = retry_add;
378         page = error_1b >> (PAGE_SHIFT - 4); /* convert the addr to 4k page */
379         row = pvt->mc_symmetric ?
380                 ((page >> 1) & 3) : /* chip select are bits 14 & 13 */
381                 edac_mc_find_csrow_by_page(mci, page);
382         e752x_mc_printk(mci, KERN_WARNING,
383                 "CE page 0x%lx, row %d : Memory read retry\n",
384                 (long unsigned int) page, row);
385 }
386
387 static inline void process_ded_retry(struct mem_ctl_info *mci, u16 error,
388                 u32 retry_add, int *error_found, int handle_error)
389 {
390         *error_found = 1;
391
392         if (handle_error)
393                 do_process_ded_retry(mci, error, retry_add);
394 }
395
396 static inline void process_threshold_ce(struct mem_ctl_info *mci, u16 error,
397                 int *error_found, int handle_error)
398 {
399         *error_found = 1;
400
401         if (handle_error)
402                 e752x_mc_printk(mci, KERN_WARNING, "Memory threshold CE\n");
403 }
404
405 static char *global_message[11] = {
406         "PCI Express C1", "PCI Express C", "PCI Express B1",
407         "PCI Express B", "PCI Express A1", "PCI Express A",
408         "DMA Controler", "HUB Interface", "System Bus",
409         "DRAM Controler", "Internal Buffer"
410 };
411
412 static char *fatal_message[2] = { "Non-Fatal ", "Fatal " };
413
414 static void do_global_error(int fatal, u32 errors)
415 {
416         int i;
417
418         for (i = 0; i < 11; i++) {
419                 if (errors & (1 << i))
420                         e752x_printk(KERN_WARNING, "%sError %s\n",
421                                 fatal_message[fatal], global_message[i]);
422         }
423 }
424
425 static inline void global_error(int fatal, u32 errors, int *error_found,
426                 int handle_error)
427 {
428         *error_found = 1;
429
430         if (handle_error)
431                 do_global_error(fatal, errors);
432 }
433
434 static char *hub_message[7] = {
435         "HI Address or Command Parity", "HI Illegal Access",
436         "HI Internal Parity", "Out of Range Access",
437         "HI Data Parity", "Enhanced Config Access",
438         "Hub Interface Target Abort"
439 };
440
441 static void do_hub_error(int fatal, u8 errors)
442 {
443         int i;
444
445         for (i = 0; i < 7; i++) {
446                 if (errors & (1 << i))
447                         e752x_printk(KERN_WARNING, "%sError %s\n",
448                                 fatal_message[fatal], hub_message[i]);
449         }
450 }
451
452 static inline void hub_error(int fatal, u8 errors, int *error_found,
453                 int handle_error)
454 {
455         *error_found = 1;
456
457         if (handle_error)
458                 do_hub_error(fatal, errors);
459 }
460
461 static char *membuf_message[4] = {
462         "Internal PMWB to DRAM parity",
463         "Internal PMWB to System Bus Parity",
464         "Internal System Bus or IO to PMWB Parity",
465         "Internal DRAM to PMWB Parity"
466 };
467
468 static void do_membuf_error(u8 errors)
469 {
470         int i;
471
472         for (i = 0; i < 4; i++) {
473                 if (errors & (1 << i))
474                         e752x_printk(KERN_WARNING, "Non-Fatal Error %s\n",
475                                 membuf_message[i]);
476         }
477 }
478
479 static inline void membuf_error(u8 errors, int *error_found, int handle_error)
480 {
481         *error_found = 1;
482
483         if (handle_error)
484                 do_membuf_error(errors);
485 }
486
487 static char *sysbus_message[10] = {
488         "Addr or Request Parity",
489         "Data Strobe Glitch",
490         "Addr Strobe Glitch",
491         "Data Parity",
492         "Addr Above TOM",
493         "Non DRAM Lock Error",
494         "MCERR", "BINIT",
495         "Memory Parity",
496         "IO Subsystem Parity"
497 };
498
499 static void do_sysbus_error(int fatal, u32 errors)
500 {
501         int i;
502
503         for (i = 0; i < 10; i++) {
504                 if (errors & (1 << i))
505                         e752x_printk(KERN_WARNING, "%sError System Bus %s\n",
506                                 fatal_message[fatal], sysbus_message[i]);
507         }
508 }
509
510 static inline void sysbus_error(int fatal, u32 errors, int *error_found,
511                 int handle_error)
512 {
513         *error_found = 1;
514
515         if (handle_error)
516                 do_sysbus_error(fatal, errors);
517 }
518
519 static void e752x_check_hub_interface(struct e752x_error_info *info,
520                 int *error_found, int handle_error)
521 {
522         u8 stat8;
523
524         //pci_read_config_byte(dev,E752X_HI_FERR,&stat8);
525
526         stat8 = info->hi_ferr;
527
528         if(stat8 & 0x7f) { /* Error, so process */
529                 stat8 &= 0x7f;
530
531                 if(stat8 & 0x2b)
532                         hub_error(1, stat8 & 0x2b, error_found, handle_error);
533
534                 if(stat8 & 0x54)
535                         hub_error(0, stat8 & 0x54, error_found, handle_error);
536         }
537
538         //pci_read_config_byte(dev,E752X_HI_NERR,&stat8);
539
540         stat8 = info->hi_nerr;
541
542         if(stat8 & 0x7f) { /* Error, so process */
543                 stat8 &= 0x7f;
544
545                 if (stat8 & 0x2b)
546                         hub_error(1, stat8 & 0x2b, error_found, handle_error);
547
548                 if(stat8 & 0x54)
549                         hub_error(0, stat8 & 0x54, error_found, handle_error);
550         }
551 }
552
553 static void e752x_check_sysbus(struct e752x_error_info *info,
554                 int *error_found, int handle_error)
555 {
556         u32 stat32, error32;
557
558         //pci_read_config_dword(dev,E752X_SYSBUS_FERR,&stat32);
559         stat32 = info->sysbus_ferr + (info->sysbus_nerr << 16);
560
561         if (stat32 == 0)
562                 return;  /* no errors */
563
564         error32 = (stat32 >> 16) & 0x3ff;
565         stat32 = stat32 & 0x3ff;
566
567         if(stat32 & 0x087)
568                 sysbus_error(1, stat32 & 0x087, error_found, handle_error);
569
570         if(stat32 & 0x378)
571                 sysbus_error(0, stat32 & 0x378, error_found, handle_error);
572
573         if(error32 & 0x087)
574                 sysbus_error(1, error32 & 0x087, error_found, handle_error);
575
576         if(error32 & 0x378)
577                 sysbus_error(0, error32 & 0x378, error_found, handle_error);
578 }
579
580 static void e752x_check_membuf (struct e752x_error_info *info,
581                 int *error_found, int handle_error)
582 {
583         u8 stat8;
584
585         stat8 = info->buf_ferr;
586
587         if (stat8 & 0x0f) { /* Error, so process */
588                 stat8 &= 0x0f;
589                 membuf_error(stat8, error_found, handle_error);
590         }
591
592         stat8 = info->buf_nerr;
593
594         if (stat8 & 0x0f) { /* Error, so process */
595                 stat8 &= 0x0f;
596                 membuf_error(stat8, error_found, handle_error);
597         }
598 }
599
600 static void e752x_check_dram (struct mem_ctl_info *mci,
601                 struct e752x_error_info *info, int *error_found,
602                 int handle_error)
603 {
604         u16 error_one, error_next;
605
606         error_one = info->dram_ferr;
607         error_next = info->dram_nerr;
608
609         /* decode and report errors */
610         if(error_one & 0x0101)  /* check first error correctable */
611                 process_ce(mci, error_one, info->dram_sec1_add,
612                            info->dram_sec1_syndrome, error_found,
613                            handle_error);
614
615         if(error_next & 0x0101)  /* check next error correctable */
616                 process_ce(mci, error_next, info->dram_sec2_add,
617                            info->dram_sec2_syndrome, error_found,
618                            handle_error);
619
620         if(error_one & 0x4040)
621                 process_ue_no_info_wr(mci, error_found, handle_error);
622
623         if(error_next & 0x4040)
624                 process_ue_no_info_wr(mci, error_found, handle_error);
625
626         if(error_one & 0x2020)
627                 process_ded_retry(mci, error_one, info->dram_retr_add,
628                                   error_found, handle_error);
629
630         if(error_next & 0x2020)
631                 process_ded_retry(mci, error_next, info->dram_retr_add,
632                                   error_found, handle_error);
633
634         if(error_one & 0x0808)
635                 process_threshold_ce(mci, error_one, error_found,
636                                      handle_error);
637
638         if(error_next & 0x0808)
639                 process_threshold_ce(mci, error_next, error_found,
640                                      handle_error);
641
642         if(error_one & 0x0606)
643                 process_ue(mci, error_one, info->dram_ded_add,
644                            info->dram_scrb_add, error_found, handle_error);
645
646         if(error_next & 0x0606)
647                 process_ue(mci, error_next, info->dram_ded_add,
648                            info->dram_scrb_add, error_found, handle_error);
649 }
650
651 static void e752x_get_error_info (struct mem_ctl_info *mci,
652                 struct e752x_error_info *info)
653 {
654         struct pci_dev *dev;
655         struct e752x_pvt *pvt;
656
657         memset(info, 0, sizeof(*info));
658         pvt = (struct e752x_pvt *) mci->pvt_info;
659         dev = pvt->dev_d0f1;
660         pci_read_config_dword(dev, E752X_FERR_GLOBAL, &info->ferr_global);
661
662         if (info->ferr_global) {
663                 pci_read_config_byte(dev, E752X_HI_FERR, &info->hi_ferr);
664                 pci_read_config_word(dev, E752X_SYSBUS_FERR,
665                                 &info->sysbus_ferr);
666                 pci_read_config_byte(dev, E752X_BUF_FERR, &info->buf_ferr);
667                 pci_read_config_word(dev, E752X_DRAM_FERR,
668                                 &info->dram_ferr);
669                 pci_read_config_dword(dev, E752X_DRAM_SEC1_ADD,
670                                 &info->dram_sec1_add);
671                 pci_read_config_word(dev, E752X_DRAM_SEC1_SYNDROME,
672                                 &info->dram_sec1_syndrome);
673                 pci_read_config_dword(dev, E752X_DRAM_DED_ADD,
674                                 &info->dram_ded_add);
675                 pci_read_config_dword(dev, E752X_DRAM_SCRB_ADD,
676                                 &info->dram_scrb_add);
677                 pci_read_config_dword(dev, E752X_DRAM_RETR_ADD,
678                                 &info->dram_retr_add);
679
680                 if (info->hi_ferr & 0x7f)
681                         pci_write_config_byte(dev, E752X_HI_FERR,
682                                         info->hi_ferr);
683
684                 if (info->sysbus_ferr)
685                         pci_write_config_word(dev, E752X_SYSBUS_FERR,
686                                         info->sysbus_ferr);
687
688                 if (info->buf_ferr & 0x0f)
689                         pci_write_config_byte(dev, E752X_BUF_FERR,
690                                         info->buf_ferr);
691
692                 if (info->dram_ferr)
693                         pci_write_bits16(pvt->bridge_ck, E752X_DRAM_FERR,
694                                         info->dram_ferr, info->dram_ferr);
695
696                 pci_write_config_dword(dev, E752X_FERR_GLOBAL,
697                                 info->ferr_global);
698         }
699
700         pci_read_config_dword(dev, E752X_NERR_GLOBAL, &info->nerr_global);
701
702         if (info->nerr_global) {
703                 pci_read_config_byte(dev, E752X_HI_NERR, &info->hi_nerr);
704                 pci_read_config_word(dev, E752X_SYSBUS_NERR,
705                                 &info->sysbus_nerr);
706                 pci_read_config_byte(dev, E752X_BUF_NERR, &info->buf_nerr);
707                 pci_read_config_word(dev, E752X_DRAM_NERR,
708                                 &info->dram_nerr);
709                 pci_read_config_dword(dev, E752X_DRAM_SEC2_ADD,
710                                 &info->dram_sec2_add);
711                 pci_read_config_word(dev, E752X_DRAM_SEC2_SYNDROME,
712                                 &info->dram_sec2_syndrome);
713
714                 if (info->hi_nerr & 0x7f)
715                         pci_write_config_byte(dev, E752X_HI_NERR,
716                                         info->hi_nerr);
717
718                 if (info->sysbus_nerr)
719                         pci_write_config_word(dev, E752X_SYSBUS_NERR,
720                                         info->sysbus_nerr);
721
722                 if (info->buf_nerr & 0x0f)
723                         pci_write_config_byte(dev, E752X_BUF_NERR,
724                                         info->buf_nerr);
725
726                 if (info->dram_nerr)
727                         pci_write_bits16(pvt->bridge_ck, E752X_DRAM_NERR,
728                                         info->dram_nerr, info->dram_nerr);
729
730                 pci_write_config_dword(dev, E752X_NERR_GLOBAL,
731                                 info->nerr_global);
732         }
733 }
734
735 static int e752x_process_error_info (struct mem_ctl_info *mci,
736                 struct e752x_error_info *info, int handle_errors)
737 {
738         u32 error32, stat32;
739         int error_found;
740
741         error_found = 0;
742         error32 = (info->ferr_global >> 18) & 0x3ff;
743         stat32 = (info->ferr_global >> 4) & 0x7ff;
744
745         if (error32)
746                 global_error(1, error32, &error_found, handle_errors);
747
748         if (stat32)
749                 global_error(0, stat32, &error_found, handle_errors);
750
751         error32 = (info->nerr_global >> 18) & 0x3ff;
752         stat32 = (info->nerr_global >> 4) & 0x7ff;
753
754         if (error32)
755                 global_error(1, error32, &error_found, handle_errors);
756
757         if (stat32)
758                 global_error(0, stat32, &error_found, handle_errors);
759
760         e752x_check_hub_interface(info, &error_found, handle_errors);
761         e752x_check_sysbus(info, &error_found, handle_errors);
762         e752x_check_membuf(info, &error_found, handle_errors);
763         e752x_check_dram(mci, info, &error_found, handle_errors);
764         return error_found;
765 }
766
767 static void e752x_check(struct mem_ctl_info *mci)
768 {
769         struct e752x_error_info info;
770
771         debugf3("%s()\n", __func__);
772         e752x_get_error_info(mci, &info);
773         e752x_process_error_info(mci, &info, 1);
774 }
775
776 /* Return 1 if dual channel mode is active.  Else return 0. */
777 static inline int dual_channel_active(u16 ddrcsr)
778 {
779         return (((ddrcsr >> 12) & 3) == 3);
780 }
781
782 static void e752x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
783                 u16 ddrcsr)
784 {
785         struct csrow_info *csrow;
786         unsigned long last_cumul_size;
787         int index, mem_dev, drc_chan;
788         int drc_drbg;  /* DRB granularity 0=64mb, 1=128mb */
789         int drc_ddim;  /* DRAM Data Integrity Mode 0=none, 2=edac */
790         u8 value;
791         u32 dra, drc, cumul_size;
792
793         dra = 0;
794         for (index=0; index < 4; index++) {
795                 u8 dra_reg;
796                 pci_read_config_byte(pdev, E752X_DRA+index, &dra_reg);
797                 dra |= dra_reg << (index * 8);
798         }
799         pci_read_config_dword(pdev, E752X_DRC, &drc);
800         drc_chan = dual_channel_active(ddrcsr);
801         drc_drbg = drc_chan + 1;  /* 128 in dual mode, 64 in single */
802         drc_ddim = (drc >> 20) & 0x3;
803
804         /* The dram row boundary (DRB) reg values are boundary address for
805          * each DRAM row with a granularity of 64 or 128MB (single/dual
806          * channel operation).  DRB regs are cumulative; therefore DRB7 will
807          * contain the total memory contained in all eight rows.
808          */
809         for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) {
810                 /* mem_dev 0=x8, 1=x4 */
811                 mem_dev = (dra >> (index * 4 + 2)) & 0x3;
812                 csrow = &mci->csrows[index];
813
814                 mem_dev = (mem_dev == 2);
815                 pci_read_config_byte(pdev, E752X_DRB + index, &value);
816                 /* convert a 128 or 64 MiB DRB to a page size. */
817                 cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
818                 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
819                         cumul_size);
820                 if (cumul_size == last_cumul_size)
821                         continue;       /* not populated */
822
823                 csrow->first_page = last_cumul_size;
824                 csrow->last_page = cumul_size - 1;
825                 csrow->nr_pages = cumul_size - last_cumul_size;
826                 last_cumul_size = cumul_size;
827                 csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */
828                 csrow->mtype = MEM_RDDR;        /* only one type supported */
829                 csrow->dtype = mem_dev ? DEV_X4 : DEV_X8;
830
831                 /*
832                  * if single channel or x8 devices then SECDED
833                  * if dual channel and x4 then S4ECD4ED
834                  */
835                 if (drc_ddim) {
836                         if (drc_chan && mem_dev) {
837                                 csrow->edac_mode = EDAC_S4ECD4ED;
838                                 mci->edac_cap |= EDAC_FLAG_S4ECD4ED;
839                         } else {
840                                 csrow->edac_mode = EDAC_SECDED;
841                                 mci->edac_cap |= EDAC_FLAG_SECDED;
842                         }
843                 } else
844                         csrow->edac_mode = EDAC_NONE;
845         }
846 }
847
848 static void e752x_init_mem_map_table(struct pci_dev *pdev,
849                 struct e752x_pvt *pvt)
850 {
851         int index;
852         u8 value, last, row, stat8;
853
854         last = 0;
855         row = 0;
856
857         for (index = 0; index < 8; index += 2) {
858                 pci_read_config_byte(pdev, E752X_DRB + index, &value);
859                 /* test if there is a dimm in this slot */
860                 if (value == last) {
861                         /* no dimm in the slot, so flag it as empty */
862                         pvt->map[index] = 0xff;
863                         pvt->map[index + 1] = 0xff;
864                 } else {        /* there is a dimm in the slot */
865                         pvt->map[index] = row;
866                         row++;
867                         last = value;
868                         /* test the next value to see if the dimm is double
869                          * sided
870                          */
871                         pci_read_config_byte(pdev, E752X_DRB + index + 1,
872                                              &value);
873                         pvt->map[index + 1] = (value == last) ?
874                             0xff :      /* the dimm is single sided,
875                                            so flag as empty */
876                             row;        /* this is a double sided dimm
877                                            to save the next row # */
878                         row++;
879                         last = value;
880                 }
881         }
882
883         /* set the map type.  1 = normal, 0 = reversed */
884         pci_read_config_byte(pdev, E752X_DRM, &stat8);
885         pvt->map_type = ((stat8 & 0x0f) > ((stat8 >> 4) & 0x0f));
886 }
887
888 /* Return 0 on success or 1 on failure. */
889 static int e752x_get_devs(struct pci_dev *pdev, int dev_idx,
890                 struct e752x_pvt *pvt)
891 {
892         struct pci_dev *dev;
893
894         pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL,
895                                         pvt->dev_info->err_dev,
896                                         pvt->bridge_ck);
897
898         if (pvt->bridge_ck == NULL)
899                 pvt->bridge_ck = pci_scan_single_device(pdev->bus,
900                                                         PCI_DEVFN(0, 1));
901
902         if (pvt->bridge_ck == NULL) {
903                 e752x_printk(KERN_ERR, "error reporting device not found:"
904                        "vendor %x device 0x%x (broken BIOS?)\n",
905                        PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].err_dev);
906                 return 1;
907         }
908
909         dev = pci_get_device(PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].ctl_dev,
910                              NULL);
911
912         if (dev == NULL)
913                 goto fail;
914
915         pvt->dev_d0f0 = dev;
916         pvt->dev_d0f1 = pci_dev_get(pvt->bridge_ck);
917
918         return 0;
919
920 fail:
921         pci_dev_put(pvt->bridge_ck);
922         return 1;
923 }
924
925 static void e752x_init_error_reporting_regs(struct e752x_pvt *pvt)
926 {
927         struct pci_dev *dev;
928
929         dev = pvt->dev_d0f1;
930         /* Turn off error disable & SMI in case the BIOS turned it on */
931         pci_write_config_byte(dev, E752X_HI_ERRMASK, 0x00);
932         pci_write_config_byte(dev, E752X_HI_SMICMD, 0x00);
933         pci_write_config_word(dev, E752X_SYSBUS_ERRMASK, 0x00);
934         pci_write_config_word(dev, E752X_SYSBUS_SMICMD, 0x00);
935         pci_write_config_byte(dev, E752X_BUF_ERRMASK, 0x00);
936         pci_write_config_byte(dev, E752X_BUF_SMICMD, 0x00);
937         pci_write_config_byte(dev, E752X_DRAM_ERRMASK, 0x00);
938         pci_write_config_byte(dev, E752X_DRAM_SMICMD, 0x00);
939 }
940
941 static int e752x_probe1(struct pci_dev *pdev, int dev_idx)
942 {
943         u16 pci_data;
944         u8 stat8;
945         struct mem_ctl_info *mci;
946         struct e752x_pvt *pvt;
947         u16 ddrcsr;
948         int drc_chan;   /* Number of channels 0=1chan,1=2chan */
949         struct e752x_error_info discard;
950
951         debugf0("%s(): mci\n", __func__);
952         debugf0("Starting Probe1\n");
953
954         /* make sure error reporting method is sane */
955         switch(edac_op_state) {
956                 case EDAC_OPSTATE_POLL:
957                 case EDAC_OPSTATE_NMI:
958                         break;
959                 default:
960                         edac_op_state = EDAC_OPSTATE_POLL;
961                         break;
962         }
963
964         /* check to see if device 0 function 1 is enabled; if it isn't, we
965          * assume the BIOS has reserved it for a reason and is expecting
966          * exclusive access, we take care not to violate that assumption and
967          * fail the probe. */
968         pci_read_config_byte(pdev, E752X_DEVPRES1, &stat8);
969         if (!force_function_unhide && !(stat8 & (1 << 5))) {
970                 printk(KERN_INFO "Contact your BIOS vendor to see if the "
971                         "E752x error registers can be safely un-hidden\n");
972                 return -ENOMEM;
973         }
974         stat8 |= (1 << 5);
975         pci_write_config_byte(pdev, E752X_DEVPRES1, stat8);
976
977         pci_read_config_word(pdev, E752X_DDRCSR, &ddrcsr);
978         /* FIXME: should check >>12 or 0xf, true for all? */
979         /* Dual channel = 1, Single channel = 0 */
980         drc_chan = dual_channel_active(ddrcsr);
981
982         mci = edac_mc_alloc(sizeof(*pvt), E752X_NR_CSROWS, drc_chan + 1);
983
984         if (mci == NULL) {
985                 return -ENOMEM;
986         }
987
988         debugf3("%s(): init mci\n", __func__);
989         mci->mtype_cap = MEM_FLAG_RDDR;
990         mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED |
991             EDAC_FLAG_S4ECD4ED;
992         /* FIXME - what if different memory types are in different csrows? */
993         mci->mod_name = EDAC_MOD_STR;
994         mci->mod_ver = E752X_REVISION;
995         mci->dev = &pdev->dev;
996
997         debugf3("%s(): init pvt\n", __func__);
998         pvt = (struct e752x_pvt *) mci->pvt_info;
999         pvt->dev_info = &e752x_devs[dev_idx];
1000         pvt->mc_symmetric = ((ddrcsr & 0x10) != 0);
1001
1002         if (e752x_get_devs(pdev, dev_idx, pvt)) {
1003                 edac_mc_free(mci);
1004                 return -ENODEV;
1005         }
1006
1007         debugf3("%s(): more mci init\n", __func__);
1008         mci->ctl_name = pvt->dev_info->ctl_name;
1009         mci->dev_name = pci_name(pdev);
1010         mci->edac_check = e752x_check;
1011         mci->ctl_page_to_phys = ctl_page_to_phys;
1012
1013         e752x_init_csrows(mci, pdev, ddrcsr);
1014         e752x_init_mem_map_table(pdev, pvt);
1015
1016         /* set the map type.  1 = normal, 0 = reversed */
1017         pci_read_config_byte(pdev, E752X_DRM, &stat8);
1018         pvt->map_type = ((stat8 & 0x0f) > ((stat8 >> 4) & 0x0f));
1019
1020         mci->edac_cap |= EDAC_FLAG_NONE;
1021         debugf3("%s(): tolm, remapbase, remaplimit\n", __func__);
1022
1023         /* load the top of low memory, remap base, and remap limit vars */
1024         pci_read_config_word(pdev, E752X_TOLM, &pci_data);
1025         pvt->tolm = ((u32) pci_data) << 4;
1026         pci_read_config_word(pdev, E752X_REMAPBASE, &pci_data);
1027         pvt->remapbase = ((u32) pci_data) << 14;
1028         pci_read_config_word(pdev, E752X_REMAPLIMIT, &pci_data);
1029         pvt->remaplimit = ((u32) pci_data) << 14;
1030         e752x_printk(KERN_INFO,
1031                 "tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm,
1032                 pvt->remapbase, pvt->remaplimit);
1033
1034         /* Here we assume that we will never see multiple instances of this
1035          * type of memory controller.  The ID is therefore hardcoded to 0.
1036          */
1037         if (edac_mc_add_mc(mci,0)) {
1038                 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
1039                 goto fail;
1040         }
1041
1042         e752x_init_error_reporting_regs(pvt);
1043         e752x_get_error_info(mci, &discard); /* clear other MCH errors */
1044
1045         /* allocating generic PCI control info */
1046         e752x_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
1047         if (!e752x_pci) {
1048                 printk(KERN_WARNING
1049                         "%s(): Unable to create PCI control\n",
1050                         __func__);
1051                 printk(KERN_WARNING
1052                         "%s(): PCI error report via EDAC not setup\n",
1053                         __func__);
1054         }
1055
1056         /* get this far and it's successful */
1057         debugf3("%s(): success\n", __func__);
1058         return 0;
1059
1060 fail:
1061         pci_dev_put(pvt->dev_d0f0);
1062         pci_dev_put(pvt->dev_d0f1);
1063         pci_dev_put(pvt->bridge_ck);
1064         edac_mc_free(mci);
1065
1066         return -ENODEV;
1067 }
1068
1069 /* returns count (>= 0), or negative on error */
1070 static int __devinit e752x_init_one(struct pci_dev *pdev,
1071                 const struct pci_device_id *ent)
1072 {
1073         debugf0("%s()\n", __func__);
1074
1075         /* wake up and enable device */
1076         if(pci_enable_device(pdev) < 0)
1077                 return -EIO;
1078
1079         return e752x_probe1(pdev, ent->driver_data);
1080 }
1081
1082 static void __devexit e752x_remove_one(struct pci_dev *pdev)
1083 {
1084         struct mem_ctl_info *mci;
1085         struct e752x_pvt *pvt;
1086
1087         debugf0("%s()\n", __func__);
1088
1089         if (e752x_pci)
1090                 edac_pci_release_generic_ctl(e752x_pci);
1091
1092         if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
1093                 return;
1094
1095         pvt = (struct e752x_pvt *) mci->pvt_info;
1096         pci_dev_put(pvt->dev_d0f0);
1097         pci_dev_put(pvt->dev_d0f1);
1098         pci_dev_put(pvt->bridge_ck);
1099         edac_mc_free(mci);
1100 }
1101
1102 static const struct pci_device_id e752x_pci_tbl[] __devinitdata = {
1103         {
1104                 PCI_VEND_DEV(INTEL, 7520_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1105                 E7520
1106         },
1107         {
1108                 PCI_VEND_DEV(INTEL, 7525_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1109                 E7525
1110         },
1111         {
1112                 PCI_VEND_DEV(INTEL, 7320_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1113                 E7320
1114         },
1115         {
1116                 0,
1117         }       /* 0 terminated list. */
1118 };
1119
1120 MODULE_DEVICE_TABLE(pci, e752x_pci_tbl);
1121
1122 static struct pci_driver e752x_driver = {
1123         .name = EDAC_MOD_STR,
1124         .probe = e752x_init_one,
1125         .remove = __devexit_p(e752x_remove_one),
1126         .id_table = e752x_pci_tbl,
1127 };
1128
1129 static int __init e752x_init(void)
1130 {
1131         int pci_rc;
1132
1133         debugf3("%s()\n", __func__);
1134         pci_rc = pci_register_driver(&e752x_driver);
1135         return (pci_rc < 0) ? pci_rc : 0;
1136 }
1137
1138 static void __exit e752x_exit(void)
1139 {
1140         debugf3("%s()\n", __func__);
1141         pci_unregister_driver(&e752x_driver);
1142 }
1143
1144 module_init(e752x_init);
1145 module_exit(e752x_exit);
1146
1147 MODULE_LICENSE("GPL");
1148 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Tom Zimmerman\n");
1149 MODULE_DESCRIPTION("MC support for Intel e752x memory controllers");
1150
1151 module_param(force_function_unhide, int, 0444);
1152 MODULE_PARM_DESC(force_function_unhide, "if BIOS sets Dev0:Fun1 up as hidden:"
1153 " 1=force unhide and hope BIOS doesn't fight driver for Dev0:Fun1 access");
1154 module_param(edac_op_state, int, 0444);
1155 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");