drivers/dma/ioat/dma_v2.c: fix warnings
[linux-3.10.git] / drivers / dma / ioat / dma_v2.c
1 /*
2  * Intel I/OAT DMA Linux driver
3  * Copyright(c) 2004 - 2009 Intel Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms and conditions of the GNU General Public License,
7  * version 2, as published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, write to the Free Software Foundation, Inc.,
16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17  *
18  * The full GNU General Public License is included in this distribution in
19  * the file called "COPYING".
20  *
21  */
22
23 /*
24  * This driver supports an Intel I/OAT DMA engine (versions >= 2), which
25  * does asynchronous data movement and checksumming operations.
26  */
27
28 #include <linux/init.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/interrupt.h>
32 #include <linux/dmaengine.h>
33 #include <linux/delay.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/workqueue.h>
36 #include <linux/i7300_idle.h>
37 #include "dma.h"
38 #include "dma_v2.h"
39 #include "registers.h"
40 #include "hw.h"
41
42 int ioat_ring_alloc_order = 8;
43 module_param(ioat_ring_alloc_order, int, 0644);
44 MODULE_PARM_DESC(ioat_ring_alloc_order,
45                  "ioat2+: allocate 2^n descriptors per channel"
46                  " (default: 8 max: 16)");
47 static int ioat_ring_max_alloc_order = IOAT_MAX_ORDER;
48 module_param(ioat_ring_max_alloc_order, int, 0644);
49 MODULE_PARM_DESC(ioat_ring_max_alloc_order,
50                  "ioat2+: upper limit for ring size (default: 16)");
51
52 void __ioat2_issue_pending(struct ioat2_dma_chan *ioat)
53 {
54         void * __iomem reg_base = ioat->base.reg_base;
55
56         ioat->pending = 0;
57         ioat->dmacount += ioat2_ring_pending(ioat);
58         ioat->issued = ioat->head;
59         /* make descriptor updates globally visible before notifying channel */
60         wmb();
61         writew(ioat->dmacount, reg_base + IOAT_CHAN_DMACOUNT_OFFSET);
62         dev_dbg(to_dev(&ioat->base),
63                 "%s: head: %#x tail: %#x issued: %#x count: %#x\n",
64                 __func__, ioat->head, ioat->tail, ioat->issued, ioat->dmacount);
65 }
66
67 void ioat2_issue_pending(struct dma_chan *chan)
68 {
69         struct ioat2_dma_chan *ioat = to_ioat2_chan(chan);
70
71         spin_lock_bh(&ioat->ring_lock);
72         if (ioat->pending == 1)
73                 __ioat2_issue_pending(ioat);
74         spin_unlock_bh(&ioat->ring_lock);
75 }
76
77 /**
78  * ioat2_update_pending - log pending descriptors
79  * @ioat: ioat2+ channel
80  *
81  * set pending to '1' unless pending is already set to '2', pending == 2
82  * indicates that submission is temporarily blocked due to an in-flight
83  * reset.  If we are already above the ioat_pending_level threshold then
84  * just issue pending.
85  *
86  * called with ring_lock held
87  */
88 static void ioat2_update_pending(struct ioat2_dma_chan *ioat)
89 {
90         if (unlikely(ioat->pending == 2))
91                 return;
92         else if (ioat2_ring_pending(ioat) > ioat_pending_level)
93                 __ioat2_issue_pending(ioat);
94         else
95                 ioat->pending = 1;
96 }
97
98 static void __ioat2_start_null_desc(struct ioat2_dma_chan *ioat)
99 {
100         struct ioat_ring_ent *desc;
101         struct ioat_dma_descriptor *hw;
102         int idx;
103
104         if (ioat2_ring_space(ioat) < 1) {
105                 dev_err(to_dev(&ioat->base),
106                         "Unable to start null desc - ring full\n");
107                 return;
108         }
109
110         dev_dbg(to_dev(&ioat->base), "%s: head: %#x tail: %#x issued: %#x\n",
111                 __func__, ioat->head, ioat->tail, ioat->issued);
112         idx = ioat2_desc_alloc(ioat, 1);
113         desc = ioat2_get_ring_ent(ioat, idx);
114
115         hw = desc->hw;
116         hw->ctl = 0;
117         hw->ctl_f.null = 1;
118         hw->ctl_f.int_en = 1;
119         hw->ctl_f.compl_write = 1;
120         /* set size to non-zero value (channel returns error when size is 0) */
121         hw->size = NULL_DESC_BUFFER_SIZE;
122         hw->src_addr = 0;
123         hw->dst_addr = 0;
124         async_tx_ack(&desc->txd);
125         ioat2_set_chainaddr(ioat, desc->txd.phys);
126         dump_desc_dbg(ioat, desc);
127         __ioat2_issue_pending(ioat);
128 }
129
130 static void ioat2_start_null_desc(struct ioat2_dma_chan *ioat)
131 {
132         spin_lock_bh(&ioat->ring_lock);
133         __ioat2_start_null_desc(ioat);
134         spin_unlock_bh(&ioat->ring_lock);
135 }
136
137 static void __cleanup(struct ioat2_dma_chan *ioat, unsigned long phys_complete)
138 {
139         struct ioat_chan_common *chan = &ioat->base;
140         struct dma_async_tx_descriptor *tx;
141         struct ioat_ring_ent *desc;
142         bool seen_current = false;
143         u16 active;
144         int i;
145
146         dev_dbg(to_dev(chan), "%s: head: %#x tail: %#x issued: %#x\n",
147                 __func__, ioat->head, ioat->tail, ioat->issued);
148
149         active = ioat2_ring_active(ioat);
150         for (i = 0; i < active && !seen_current; i++) {
151                 prefetch(ioat2_get_ring_ent(ioat, ioat->tail + i + 1));
152                 desc = ioat2_get_ring_ent(ioat, ioat->tail + i);
153                 tx = &desc->txd;
154                 dump_desc_dbg(ioat, desc);
155                 if (tx->cookie) {
156                         ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw);
157                         chan->completed_cookie = tx->cookie;
158                         tx->cookie = 0;
159                         if (tx->callback) {
160                                 tx->callback(tx->callback_param);
161                                 tx->callback = NULL;
162                         }
163                 }
164
165                 if (tx->phys == phys_complete)
166                         seen_current = true;
167         }
168         ioat->tail += i;
169         BUG_ON(!seen_current); /* no active descs have written a completion? */
170
171         chan->last_completion = phys_complete;
172         if (ioat->head == ioat->tail) {
173                 dev_dbg(to_dev(chan), "%s: cancel completion timeout\n",
174                         __func__);
175                 clear_bit(IOAT_COMPLETION_PENDING, &chan->state);
176                 mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT);
177         }
178 }
179
180 /**
181  * ioat2_cleanup - clean finished descriptors (advance tail pointer)
182  * @chan: ioat channel to be cleaned up
183  */
184 static void ioat2_cleanup(struct ioat2_dma_chan *ioat)
185 {
186         struct ioat_chan_common *chan = &ioat->base;
187         unsigned long phys_complete;
188
189         prefetch(chan->completion);
190
191         if (!spin_trylock_bh(&chan->cleanup_lock))
192                 return;
193
194         if (!ioat_cleanup_preamble(chan, &phys_complete)) {
195                 spin_unlock_bh(&chan->cleanup_lock);
196                 return;
197         }
198
199         if (!spin_trylock_bh(&ioat->ring_lock)) {
200                 spin_unlock_bh(&chan->cleanup_lock);
201                 return;
202         }
203
204         __cleanup(ioat, phys_complete);
205
206         spin_unlock_bh(&ioat->ring_lock);
207         spin_unlock_bh(&chan->cleanup_lock);
208 }
209
210 void ioat2_cleanup_tasklet(unsigned long data)
211 {
212         struct ioat2_dma_chan *ioat = (void *) data;
213
214         ioat2_cleanup(ioat);
215         writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET);
216 }
217
218 void __ioat2_restart_chan(struct ioat2_dma_chan *ioat)
219 {
220         struct ioat_chan_common *chan = &ioat->base;
221
222         /* set the tail to be re-issued */
223         ioat->issued = ioat->tail;
224         ioat->dmacount = 0;
225         set_bit(IOAT_COMPLETION_PENDING, &chan->state);
226         mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
227
228         dev_dbg(to_dev(chan),
229                 "%s: head: %#x tail: %#x issued: %#x count: %#x\n",
230                 __func__, ioat->head, ioat->tail, ioat->issued, ioat->dmacount);
231
232         if (ioat2_ring_pending(ioat)) {
233                 struct ioat_ring_ent *desc;
234
235                 desc = ioat2_get_ring_ent(ioat, ioat->tail);
236                 ioat2_set_chainaddr(ioat, desc->txd.phys);
237                 __ioat2_issue_pending(ioat);
238         } else
239                 __ioat2_start_null_desc(ioat);
240 }
241
242 static void ioat2_restart_channel(struct ioat2_dma_chan *ioat)
243 {
244         struct ioat_chan_common *chan = &ioat->base;
245         unsigned long phys_complete;
246         u32 status;
247
248         status = ioat_chansts(chan);
249         if (is_ioat_active(status) || is_ioat_idle(status))
250                 ioat_suspend(chan);
251         while (is_ioat_active(status) || is_ioat_idle(status)) {
252                 status = ioat_chansts(chan);
253                 cpu_relax();
254         }
255
256         if (ioat_cleanup_preamble(chan, &phys_complete))
257                 __cleanup(ioat, phys_complete);
258
259         __ioat2_restart_chan(ioat);
260 }
261
262 void ioat2_timer_event(unsigned long data)
263 {
264         struct ioat2_dma_chan *ioat = (void *) data;
265         struct ioat_chan_common *chan = &ioat->base;
266
267         spin_lock_bh(&chan->cleanup_lock);
268         if (test_bit(IOAT_COMPLETION_PENDING, &chan->state)) {
269                 unsigned long phys_complete;
270                 u64 status;
271
272                 spin_lock_bh(&ioat->ring_lock);
273                 status = ioat_chansts(chan);
274
275                 /* when halted due to errors check for channel
276                  * programming errors before advancing the completion state
277                  */
278                 if (is_ioat_halted(status)) {
279                         u32 chanerr;
280
281                         chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
282                         BUG_ON(is_ioat_bug(chanerr));
283                 }
284
285                 /* if we haven't made progress and we have already
286                  * acknowledged a pending completion once, then be more
287                  * forceful with a restart
288                  */
289                 if (ioat_cleanup_preamble(chan, &phys_complete))
290                         __cleanup(ioat, phys_complete);
291                 else if (test_bit(IOAT_COMPLETION_ACK, &chan->state))
292                         ioat2_restart_channel(ioat);
293                 else {
294                         set_bit(IOAT_COMPLETION_ACK, &chan->state);
295                         mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
296                 }
297                 spin_unlock_bh(&ioat->ring_lock);
298         } else {
299                 u16 active;
300
301                 /* if the ring is idle, empty, and oversized try to step
302                  * down the size
303                  */
304                 spin_lock_bh(&ioat->ring_lock);
305                 active = ioat2_ring_active(ioat);
306                 if (active == 0 && ioat->alloc_order > ioat_get_alloc_order())
307                         reshape_ring(ioat, ioat->alloc_order-1);
308                 spin_unlock_bh(&ioat->ring_lock);
309
310                 /* keep shrinking until we get back to our minimum
311                  * default size
312                  */
313                 if (ioat->alloc_order > ioat_get_alloc_order())
314                         mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT);
315         }
316         spin_unlock_bh(&chan->cleanup_lock);
317 }
318
319 /**
320  * ioat2_enumerate_channels - find and initialize the device's channels
321  * @device: the device to be enumerated
322  */
323 int ioat2_enumerate_channels(struct ioatdma_device *device)
324 {
325         struct ioat2_dma_chan *ioat;
326         struct device *dev = &device->pdev->dev;
327         struct dma_device *dma = &device->common;
328         u8 xfercap_log;
329         int i;
330
331         INIT_LIST_HEAD(&dma->channels);
332         dma->chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET);
333         dma->chancnt &= 0x1f; /* bits [4:0] valid */
334         if (dma->chancnt > ARRAY_SIZE(device->idx)) {
335                 dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n",
336                          dma->chancnt, ARRAY_SIZE(device->idx));
337                 dma->chancnt = ARRAY_SIZE(device->idx);
338         }
339         xfercap_log = readb(device->reg_base + IOAT_XFERCAP_OFFSET);
340         xfercap_log &= 0x1f; /* bits [4:0] valid */
341         if (xfercap_log == 0)
342                 return 0;
343         dev_dbg(dev, "%s: xfercap = %d\n", __func__, 1 << xfercap_log);
344
345         /* FIXME which i/oat version is i7300? */
346 #ifdef CONFIG_I7300_IDLE_IOAT_CHANNEL
347         if (i7300_idle_platform_probe(NULL, NULL, 1) == 0)
348                 dma->chancnt--;
349 #endif
350         for (i = 0; i < dma->chancnt; i++) {
351                 ioat = devm_kzalloc(dev, sizeof(*ioat), GFP_KERNEL);
352                 if (!ioat)
353                         break;
354
355                 ioat_init_channel(device, &ioat->base, i,
356                                   device->timer_fn,
357                                   device->cleanup_tasklet,
358                                   (unsigned long) ioat);
359                 ioat->xfercap_log = xfercap_log;
360                 spin_lock_init(&ioat->ring_lock);
361         }
362         dma->chancnt = i;
363         return i;
364 }
365
366 static dma_cookie_t ioat2_tx_submit_unlock(struct dma_async_tx_descriptor *tx)
367 {
368         struct dma_chan *c = tx->chan;
369         struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
370         struct ioat_chan_common *chan = &ioat->base;
371         dma_cookie_t cookie = c->cookie;
372
373         cookie++;
374         if (cookie < 0)
375                 cookie = 1;
376         tx->cookie = cookie;
377         c->cookie = cookie;
378         dev_dbg(to_dev(&ioat->base), "%s: cookie: %d\n", __func__, cookie);
379
380         if (!test_and_set_bit(IOAT_COMPLETION_PENDING, &chan->state))
381                 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
382         ioat2_update_pending(ioat);
383         spin_unlock_bh(&ioat->ring_lock);
384
385         return cookie;
386 }
387
388 static struct ioat_ring_ent *ioat2_alloc_ring_ent(struct dma_chan *chan, gfp_t flags)
389 {
390         struct ioat_dma_descriptor *hw;
391         struct ioat_ring_ent *desc;
392         struct ioatdma_device *dma;
393         dma_addr_t phys;
394
395         dma = to_ioatdma_device(chan->device);
396         hw = pci_pool_alloc(dma->dma_pool, flags, &phys);
397         if (!hw)
398                 return NULL;
399         memset(hw, 0, sizeof(*hw));
400
401         desc = kmem_cache_alloc(ioat2_cache, flags);
402         if (!desc) {
403                 pci_pool_free(dma->dma_pool, hw, phys);
404                 return NULL;
405         }
406         memset(desc, 0, sizeof(*desc));
407
408         dma_async_tx_descriptor_init(&desc->txd, chan);
409         desc->txd.tx_submit = ioat2_tx_submit_unlock;
410         desc->hw = hw;
411         desc->txd.phys = phys;
412         return desc;
413 }
414
415 static void ioat2_free_ring_ent(struct ioat_ring_ent *desc, struct dma_chan *chan)
416 {
417         struct ioatdma_device *dma;
418
419         dma = to_ioatdma_device(chan->device);
420         pci_pool_free(dma->dma_pool, desc->hw, desc->txd.phys);
421         kmem_cache_free(ioat2_cache, desc);
422 }
423
424 static struct ioat_ring_ent **ioat2_alloc_ring(struct dma_chan *c, int order, gfp_t flags)
425 {
426         struct ioat_ring_ent **ring;
427         int descs = 1 << order;
428         int i;
429
430         if (order > ioat_get_max_alloc_order())
431                 return NULL;
432
433         /* allocate the array to hold the software ring */
434         ring = kcalloc(descs, sizeof(*ring), flags);
435         if (!ring)
436                 return NULL;
437         for (i = 0; i < descs; i++) {
438                 ring[i] = ioat2_alloc_ring_ent(c, flags);
439                 if (!ring[i]) {
440                         while (i--)
441                                 ioat2_free_ring_ent(ring[i], c);
442                         kfree(ring);
443                         return NULL;
444                 }
445                 set_desc_id(ring[i], i);
446         }
447
448         /* link descs */
449         for (i = 0; i < descs-1; i++) {
450                 struct ioat_ring_ent *next = ring[i+1];
451                 struct ioat_dma_descriptor *hw = ring[i]->hw;
452
453                 hw->next = next->txd.phys;
454         }
455         ring[i]->hw->next = ring[0]->txd.phys;
456
457         return ring;
458 }
459
460 /* ioat2_alloc_chan_resources - allocate/initialize ioat2 descriptor ring
461  * @chan: channel to be initialized
462  */
463 int ioat2_alloc_chan_resources(struct dma_chan *c)
464 {
465         struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
466         struct ioat_chan_common *chan = &ioat->base;
467         struct ioat_ring_ent **ring;
468         u32 chanerr;
469         int order;
470
471         /* have we already been set up? */
472         if (ioat->ring)
473                 return 1 << ioat->alloc_order;
474
475         /* Setup register to interrupt and write completion status on error */
476         writew(IOAT_CHANCTRL_RUN, chan->reg_base + IOAT_CHANCTRL_OFFSET);
477
478         chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
479         if (chanerr) {
480                 dev_err(to_dev(chan), "CHANERR = %x, clearing\n", chanerr);
481                 writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET);
482         }
483
484         /* allocate a completion writeback area */
485         /* doing 2 32bit writes to mmio since 1 64b write doesn't work */
486         chan->completion = pci_pool_alloc(chan->device->completion_pool,
487                                           GFP_KERNEL, &chan->completion_dma);
488         if (!chan->completion)
489                 return -ENOMEM;
490
491         memset(chan->completion, 0, sizeof(*chan->completion));
492         writel(((u64) chan->completion_dma) & 0x00000000FFFFFFFF,
493                chan->reg_base + IOAT_CHANCMP_OFFSET_LOW);
494         writel(((u64) chan->completion_dma) >> 32,
495                chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH);
496
497         order = ioat_get_alloc_order();
498         ring = ioat2_alloc_ring(c, order, GFP_KERNEL);
499         if (!ring)
500                 return -ENOMEM;
501
502         spin_lock_bh(&ioat->ring_lock);
503         ioat->ring = ring;
504         ioat->head = 0;
505         ioat->issued = 0;
506         ioat->tail = 0;
507         ioat->pending = 0;
508         ioat->alloc_order = order;
509         spin_unlock_bh(&ioat->ring_lock);
510
511         tasklet_enable(&chan->cleanup_task);
512         ioat2_start_null_desc(ioat);
513
514         return 1 << ioat->alloc_order;
515 }
516
517 bool reshape_ring(struct ioat2_dma_chan *ioat, int order)
518 {
519         /* reshape differs from normal ring allocation in that we want
520          * to allocate a new software ring while only
521          * extending/truncating the hardware ring
522          */
523         struct ioat_chan_common *chan = &ioat->base;
524         struct dma_chan *c = &chan->common;
525         const u16 curr_size = ioat2_ring_mask(ioat) + 1;
526         const u16 active = ioat2_ring_active(ioat);
527         const u16 new_size = 1 << order;
528         struct ioat_ring_ent **ring;
529         u16 i;
530
531         if (order > ioat_get_max_alloc_order())
532                 return false;
533
534         /* double check that we have at least 1 free descriptor */
535         if (active == curr_size)
536                 return false;
537
538         /* when shrinking, verify that we can hold the current active
539          * set in the new ring
540          */
541         if (active >= new_size)
542                 return false;
543
544         /* allocate the array to hold the software ring */
545         ring = kcalloc(new_size, sizeof(*ring), GFP_NOWAIT);
546         if (!ring)
547                 return false;
548
549         /* allocate/trim descriptors as needed */
550         if (new_size > curr_size) {
551                 /* copy current descriptors to the new ring */
552                 for (i = 0; i < curr_size; i++) {
553                         u16 curr_idx = (ioat->tail+i) & (curr_size-1);
554                         u16 new_idx = (ioat->tail+i) & (new_size-1);
555
556                         ring[new_idx] = ioat->ring[curr_idx];
557                         set_desc_id(ring[new_idx], new_idx);
558                 }
559
560                 /* add new descriptors to the ring */
561                 for (i = curr_size; i < new_size; i++) {
562                         u16 new_idx = (ioat->tail+i) & (new_size-1);
563
564                         ring[new_idx] = ioat2_alloc_ring_ent(c, GFP_NOWAIT);
565                         if (!ring[new_idx]) {
566                                 while (i--) {
567                                         u16 new_idx = (ioat->tail+i) & (new_size-1);
568
569                                         ioat2_free_ring_ent(ring[new_idx], c);
570                                 }
571                                 kfree(ring);
572                                 return false;
573                         }
574                         set_desc_id(ring[new_idx], new_idx);
575                 }
576
577                 /* hw link new descriptors */
578                 for (i = curr_size-1; i < new_size; i++) {
579                         u16 new_idx = (ioat->tail+i) & (new_size-1);
580                         struct ioat_ring_ent *next = ring[(new_idx+1) & (new_size-1)];
581                         struct ioat_dma_descriptor *hw = ring[new_idx]->hw;
582
583                         hw->next = next->txd.phys;
584                 }
585         } else {
586                 struct ioat_dma_descriptor *hw;
587                 struct ioat_ring_ent *next;
588
589                 /* copy current descriptors to the new ring, dropping the
590                  * removed descriptors
591                  */
592                 for (i = 0; i < new_size; i++) {
593                         u16 curr_idx = (ioat->tail+i) & (curr_size-1);
594                         u16 new_idx = (ioat->tail+i) & (new_size-1);
595
596                         ring[new_idx] = ioat->ring[curr_idx];
597                         set_desc_id(ring[new_idx], new_idx);
598                 }
599
600                 /* free deleted descriptors */
601                 for (i = new_size; i < curr_size; i++) {
602                         struct ioat_ring_ent *ent;
603
604                         ent = ioat2_get_ring_ent(ioat, ioat->tail+i);
605                         ioat2_free_ring_ent(ent, c);
606                 }
607
608                 /* fix up hardware ring */
609                 hw = ring[(ioat->tail+new_size-1) & (new_size-1)]->hw;
610                 next = ring[(ioat->tail+new_size) & (new_size-1)];
611                 hw->next = next->txd.phys;
612         }
613
614         dev_dbg(to_dev(chan), "%s: allocated %d descriptors\n",
615                 __func__, new_size);
616
617         kfree(ioat->ring);
618         ioat->ring = ring;
619         ioat->alloc_order = order;
620
621         return true;
622 }
623
624 /**
625  * ioat2_alloc_and_lock - common descriptor alloc boilerplate for ioat2,3 ops
626  * @idx: gets starting descriptor index on successful allocation
627  * @ioat: ioat2,3 channel (ring) to operate on
628  * @num_descs: allocation length
629  */
630 int ioat2_alloc_and_lock(u16 *idx, struct ioat2_dma_chan *ioat, int num_descs)
631 {
632         struct ioat_chan_common *chan = &ioat->base;
633
634         spin_lock_bh(&ioat->ring_lock);
635         /* never allow the last descriptor to be consumed, we need at
636          * least one free at all times to allow for on-the-fly ring
637          * resizing.
638          */
639         while (unlikely(ioat2_ring_space(ioat) <= num_descs)) {
640                 if (reshape_ring(ioat, ioat->alloc_order + 1) &&
641                     ioat2_ring_space(ioat) > num_descs)
642                                 break;
643
644                 if (printk_ratelimit())
645                         dev_dbg(to_dev(chan),
646                                 "%s: ring full! num_descs: %d (%x:%x:%x)\n",
647                                 __func__, num_descs, ioat->head, ioat->tail,
648                                 ioat->issued);
649                 spin_unlock_bh(&ioat->ring_lock);
650
651                 /* progress reclaim in the allocation failure case we
652                  * may be called under bh_disabled so we need to trigger
653                  * the timer event directly
654                  */
655                 spin_lock_bh(&chan->cleanup_lock);
656                 if (jiffies > chan->timer.expires &&
657                     timer_pending(&chan->timer)) {
658                         struct ioatdma_device *device = chan->device;
659
660                         mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
661                         spin_unlock_bh(&chan->cleanup_lock);
662                         device->timer_fn((unsigned long) ioat);
663                 } else
664                         spin_unlock_bh(&chan->cleanup_lock);
665                 return -ENOMEM;
666         }
667
668         dev_dbg(to_dev(chan), "%s: num_descs: %d (%x:%x:%x)\n",
669                 __func__, num_descs, ioat->head, ioat->tail, ioat->issued);
670
671         *idx = ioat2_desc_alloc(ioat, num_descs);
672         return 0;  /* with ioat->ring_lock held */
673 }
674
675 struct dma_async_tx_descriptor *
676 ioat2_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest,
677                            dma_addr_t dma_src, size_t len, unsigned long flags)
678 {
679         struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
680         struct ioat_dma_descriptor *hw;
681         struct ioat_ring_ent *desc;
682         dma_addr_t dst = dma_dest;
683         dma_addr_t src = dma_src;
684         size_t total_len = len;
685         int num_descs;
686         u16 idx;
687         int i;
688
689         num_descs = ioat2_xferlen_to_descs(ioat, len);
690         if (likely(num_descs) &&
691             ioat2_alloc_and_lock(&idx, ioat, num_descs) == 0)
692                 /* pass */;
693         else
694                 return NULL;
695         i = 0;
696         do {
697                 size_t copy = min_t(size_t, len, 1 << ioat->xfercap_log);
698
699                 desc = ioat2_get_ring_ent(ioat, idx + i);
700                 hw = desc->hw;
701
702                 hw->size = copy;
703                 hw->ctl = 0;
704                 hw->src_addr = src;
705                 hw->dst_addr = dst;
706
707                 len -= copy;
708                 dst += copy;
709                 src += copy;
710                 dump_desc_dbg(ioat, desc);
711         } while (++i < num_descs);
712
713         desc->txd.flags = flags;
714         desc->len = total_len;
715         hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
716         hw->ctl_f.fence = !!(flags & DMA_PREP_FENCE);
717         hw->ctl_f.compl_write = 1;
718         dump_desc_dbg(ioat, desc);
719         /* we leave the channel locked to ensure in order submission */
720
721         return &desc->txd;
722 }
723
724 /**
725  * ioat2_free_chan_resources - release all the descriptors
726  * @chan: the channel to be cleaned
727  */
728 void ioat2_free_chan_resources(struct dma_chan *c)
729 {
730         struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
731         struct ioat_chan_common *chan = &ioat->base;
732         struct ioatdma_device *device = chan->device;
733         struct ioat_ring_ent *desc;
734         const u16 total_descs = 1 << ioat->alloc_order;
735         int descs;
736         int i;
737
738         /* Before freeing channel resources first check
739          * if they have been previously allocated for this channel.
740          */
741         if (!ioat->ring)
742                 return;
743
744         tasklet_disable(&chan->cleanup_task);
745         del_timer_sync(&chan->timer);
746         device->cleanup_tasklet((unsigned long) ioat);
747
748         /* Delay 100ms after reset to allow internal DMA logic to quiesce
749          * before removing DMA descriptor resources.
750          */
751         writeb(IOAT_CHANCMD_RESET,
752                chan->reg_base + IOAT_CHANCMD_OFFSET(chan->device->version));
753         mdelay(100);
754
755         spin_lock_bh(&ioat->ring_lock);
756         descs = ioat2_ring_space(ioat);
757         dev_dbg(to_dev(chan), "freeing %d idle descriptors\n", descs);
758         for (i = 0; i < descs; i++) {
759                 desc = ioat2_get_ring_ent(ioat, ioat->head + i);
760                 ioat2_free_ring_ent(desc, c);
761         }
762
763         if (descs < total_descs)
764                 dev_err(to_dev(chan), "Freeing %d in use descriptors!\n",
765                         total_descs - descs);
766
767         for (i = 0; i < total_descs - descs; i++) {
768                 desc = ioat2_get_ring_ent(ioat, ioat->tail + i);
769                 dump_desc_dbg(ioat, desc);
770                 ioat2_free_ring_ent(desc, c);
771         }
772
773         kfree(ioat->ring);
774         ioat->ring = NULL;
775         ioat->alloc_order = 0;
776         pci_pool_free(device->completion_pool, chan->completion,
777                       chan->completion_dma);
778         spin_unlock_bh(&ioat->ring_lock);
779
780         chan->last_completion = 0;
781         chan->completion_dma = 0;
782         ioat->pending = 0;
783         ioat->dmacount = 0;
784 }
785
786 enum dma_status
787 ioat2_is_complete(struct dma_chan *c, dma_cookie_t cookie,
788                      dma_cookie_t *done, dma_cookie_t *used)
789 {
790         struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
791         struct ioatdma_device *device = ioat->base.device;
792
793         if (ioat_is_complete(c, cookie, done, used) == DMA_SUCCESS)
794                 return DMA_SUCCESS;
795
796         device->cleanup_tasklet((unsigned long) ioat);
797
798         return ioat_is_complete(c, cookie, done, used);
799 }
800
801 static ssize_t ring_size_show(struct dma_chan *c, char *page)
802 {
803         struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
804
805         return sprintf(page, "%d\n", (1 << ioat->alloc_order) & ~1);
806 }
807 static struct ioat_sysfs_entry ring_size_attr = __ATTR_RO(ring_size);
808
809 static ssize_t ring_active_show(struct dma_chan *c, char *page)
810 {
811         struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
812
813         /* ...taken outside the lock, no need to be precise */
814         return sprintf(page, "%d\n", ioat2_ring_active(ioat));
815 }
816 static struct ioat_sysfs_entry ring_active_attr = __ATTR_RO(ring_active);
817
818 static struct attribute *ioat2_attrs[] = {
819         &ring_size_attr.attr,
820         &ring_active_attr.attr,
821         &ioat_cap_attr.attr,
822         &ioat_version_attr.attr,
823         NULL,
824 };
825
826 struct kobj_type ioat2_ktype = {
827         .sysfs_ops = &ioat_sysfs_ops,
828         .default_attrs = ioat2_attrs,
829 };
830
831 int __devinit ioat2_dma_probe(struct ioatdma_device *device, int dca)
832 {
833         struct pci_dev *pdev = device->pdev;
834         struct dma_device *dma;
835         struct dma_chan *c;
836         struct ioat_chan_common *chan;
837         int err;
838
839         device->enumerate_channels = ioat2_enumerate_channels;
840         device->cleanup_tasklet = ioat2_cleanup_tasklet;
841         device->timer_fn = ioat2_timer_event;
842         device->self_test = ioat_dma_self_test;
843         dma = &device->common;
844         dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy_lock;
845         dma->device_issue_pending = ioat2_issue_pending;
846         dma->device_alloc_chan_resources = ioat2_alloc_chan_resources;
847         dma->device_free_chan_resources = ioat2_free_chan_resources;
848         dma->device_is_tx_complete = ioat2_is_complete;
849
850         err = ioat_probe(device);
851         if (err)
852                 return err;
853         ioat_set_tcp_copy_break(2048);
854
855         list_for_each_entry(c, &dma->channels, device_node) {
856                 chan = to_chan_common(c);
857                 writel(IOAT_DCACTRL_CMPL_WRITE_ENABLE | IOAT_DMA_DCA_ANY_CPU,
858                        chan->reg_base + IOAT_DCACTRL_OFFSET);
859         }
860
861         err = ioat_register(device);
862         if (err)
863                 return err;
864
865         ioat_kobject_add(device, &ioat2_ktype);
866
867         if (dca)
868                 device->dca = ioat2_dca_init(pdev, device->reg_base);
869
870         return err;
871 }