include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[linux-3.10.git] / drivers / clocksource / sh_mtu2.c
1 /*
2  * SuperH Timer Support - MTU2
3  *
4  *  Copyright (C) 2009 Magnus Damm
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
18  */
19
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/ioport.h>
25 #include <linux/delay.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/irq.h>
29 #include <linux/err.h>
30 #include <linux/clockchips.h>
31 #include <linux/sh_timer.h>
32 #include <linux/slab.h>
33
34 struct sh_mtu2_priv {
35         void __iomem *mapbase;
36         struct clk *clk;
37         struct irqaction irqaction;
38         struct platform_device *pdev;
39         unsigned long rate;
40         unsigned long periodic;
41         struct clock_event_device ced;
42 };
43
44 static DEFINE_SPINLOCK(sh_mtu2_lock);
45
46 #define TSTR -1 /* shared register */
47 #define TCR  0 /* channel register */
48 #define TMDR 1 /* channel register */
49 #define TIOR 2 /* channel register */
50 #define TIER 3 /* channel register */
51 #define TSR  4 /* channel register */
52 #define TCNT 5 /* channel register */
53 #define TGR  6 /* channel register */
54
55 static unsigned long mtu2_reg_offs[] = {
56         [TCR] = 0,
57         [TMDR] = 1,
58         [TIOR] = 2,
59         [TIER] = 4,
60         [TSR] = 5,
61         [TCNT] = 6,
62         [TGR] = 8,
63 };
64
65 static inline unsigned long sh_mtu2_read(struct sh_mtu2_priv *p, int reg_nr)
66 {
67         struct sh_timer_config *cfg = p->pdev->dev.platform_data;
68         void __iomem *base = p->mapbase;
69         unsigned long offs;
70
71         if (reg_nr == TSTR)
72                 return ioread8(base + cfg->channel_offset);
73
74         offs = mtu2_reg_offs[reg_nr];
75
76         if ((reg_nr == TCNT) || (reg_nr == TGR))
77                 return ioread16(base + offs);
78         else
79                 return ioread8(base + offs);
80 }
81
82 static inline void sh_mtu2_write(struct sh_mtu2_priv *p, int reg_nr,
83                                 unsigned long value)
84 {
85         struct sh_timer_config *cfg = p->pdev->dev.platform_data;
86         void __iomem *base = p->mapbase;
87         unsigned long offs;
88
89         if (reg_nr == TSTR) {
90                 iowrite8(value, base + cfg->channel_offset);
91                 return;
92         }
93
94         offs = mtu2_reg_offs[reg_nr];
95
96         if ((reg_nr == TCNT) || (reg_nr == TGR))
97                 iowrite16(value, base + offs);
98         else
99                 iowrite8(value, base + offs);
100 }
101
102 static void sh_mtu2_start_stop_ch(struct sh_mtu2_priv *p, int start)
103 {
104         struct sh_timer_config *cfg = p->pdev->dev.platform_data;
105         unsigned long flags, value;
106
107         /* start stop register shared by multiple timer channels */
108         spin_lock_irqsave(&sh_mtu2_lock, flags);
109         value = sh_mtu2_read(p, TSTR);
110
111         if (start)
112                 value |= 1 << cfg->timer_bit;
113         else
114                 value &= ~(1 << cfg->timer_bit);
115
116         sh_mtu2_write(p, TSTR, value);
117         spin_unlock_irqrestore(&sh_mtu2_lock, flags);
118 }
119
120 static int sh_mtu2_enable(struct sh_mtu2_priv *p)
121 {
122         struct sh_timer_config *cfg = p->pdev->dev.platform_data;
123         int ret;
124
125         /* enable clock */
126         ret = clk_enable(p->clk);
127         if (ret) {
128                 pr_err("sh_mtu2: cannot enable clock \"%s\"\n", cfg->clk);
129                 return ret;
130         }
131
132         /* make sure channel is disabled */
133         sh_mtu2_start_stop_ch(p, 0);
134
135         p->rate = clk_get_rate(p->clk) / 64;
136         p->periodic = (p->rate + HZ/2) / HZ;
137
138         /* "Periodic Counter Operation" */
139         sh_mtu2_write(p, TCR, 0x23); /* TGRA clear, divide clock by 64 */
140         sh_mtu2_write(p, TIOR, 0);
141         sh_mtu2_write(p, TGR, p->periodic);
142         sh_mtu2_write(p, TCNT, 0);
143         sh_mtu2_write(p, TMDR, 0);
144         sh_mtu2_write(p, TIER, 0x01);
145
146         /* enable channel */
147         sh_mtu2_start_stop_ch(p, 1);
148
149         return 0;
150 }
151
152 static void sh_mtu2_disable(struct sh_mtu2_priv *p)
153 {
154         /* disable channel */
155         sh_mtu2_start_stop_ch(p, 0);
156
157         /* stop clock */
158         clk_disable(p->clk);
159 }
160
161 static irqreturn_t sh_mtu2_interrupt(int irq, void *dev_id)
162 {
163         struct sh_mtu2_priv *p = dev_id;
164
165         /* acknowledge interrupt */
166         sh_mtu2_read(p, TSR);
167         sh_mtu2_write(p, TSR, 0xfe);
168
169         /* notify clockevent layer */
170         p->ced.event_handler(&p->ced);
171         return IRQ_HANDLED;
172 }
173
174 static struct sh_mtu2_priv *ced_to_sh_mtu2(struct clock_event_device *ced)
175 {
176         return container_of(ced, struct sh_mtu2_priv, ced);
177 }
178
179 static void sh_mtu2_clock_event_mode(enum clock_event_mode mode,
180                                     struct clock_event_device *ced)
181 {
182         struct sh_mtu2_priv *p = ced_to_sh_mtu2(ced);
183         int disabled = 0;
184
185         /* deal with old setting first */
186         switch (ced->mode) {
187         case CLOCK_EVT_MODE_PERIODIC:
188                 sh_mtu2_disable(p);
189                 disabled = 1;
190                 break;
191         default:
192                 break;
193         }
194
195         switch (mode) {
196         case CLOCK_EVT_MODE_PERIODIC:
197                 pr_info("sh_mtu2: %s used for periodic clock events\n",
198                         ced->name);
199                 sh_mtu2_enable(p);
200                 break;
201         case CLOCK_EVT_MODE_UNUSED:
202                 if (!disabled)
203                         sh_mtu2_disable(p);
204                 break;
205         case CLOCK_EVT_MODE_SHUTDOWN:
206         default:
207                 break;
208         }
209 }
210
211 static void sh_mtu2_register_clockevent(struct sh_mtu2_priv *p,
212                                        char *name, unsigned long rating)
213 {
214         struct clock_event_device *ced = &p->ced;
215         int ret;
216
217         memset(ced, 0, sizeof(*ced));
218
219         ced->name = name;
220         ced->features = CLOCK_EVT_FEAT_PERIODIC;
221         ced->rating = rating;
222         ced->cpumask = cpumask_of(0);
223         ced->set_mode = sh_mtu2_clock_event_mode;
224
225         pr_info("sh_mtu2: %s used for clock events\n", ced->name);
226         clockevents_register_device(ced);
227
228         ret = setup_irq(p->irqaction.irq, &p->irqaction);
229         if (ret) {
230                 pr_err("sh_mtu2: failed to request irq %d\n",
231                        p->irqaction.irq);
232                 return;
233         }
234 }
235
236 static int sh_mtu2_register(struct sh_mtu2_priv *p, char *name,
237                             unsigned long clockevent_rating)
238 {
239         if (clockevent_rating)
240                 sh_mtu2_register_clockevent(p, name, clockevent_rating);
241
242         return 0;
243 }
244
245 static int sh_mtu2_setup(struct sh_mtu2_priv *p, struct platform_device *pdev)
246 {
247         struct sh_timer_config *cfg = pdev->dev.platform_data;
248         struct resource *res;
249         int irq, ret;
250         ret = -ENXIO;
251
252         memset(p, 0, sizeof(*p));
253         p->pdev = pdev;
254
255         if (!cfg) {
256                 dev_err(&p->pdev->dev, "missing platform data\n");
257                 goto err0;
258         }
259
260         platform_set_drvdata(pdev, p);
261
262         res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
263         if (!res) {
264                 dev_err(&p->pdev->dev, "failed to get I/O memory\n");
265                 goto err0;
266         }
267
268         irq = platform_get_irq(p->pdev, 0);
269         if (irq < 0) {
270                 dev_err(&p->pdev->dev, "failed to get irq\n");
271                 goto err0;
272         }
273
274         /* map memory, let mapbase point to our channel */
275         p->mapbase = ioremap_nocache(res->start, resource_size(res));
276         if (p->mapbase == NULL) {
277                 pr_err("sh_mtu2: failed to remap I/O memory\n");
278                 goto err0;
279         }
280
281         /* setup data for setup_irq() (too early for request_irq()) */
282         p->irqaction.name = cfg->name;
283         p->irqaction.handler = sh_mtu2_interrupt;
284         p->irqaction.dev_id = p;
285         p->irqaction.irq = irq;
286         p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL;
287
288         /* get hold of clock */
289         p->clk = clk_get(&p->pdev->dev, cfg->clk);
290         if (IS_ERR(p->clk)) {
291                 pr_err("sh_mtu2: cannot get clock \"%s\"\n", cfg->clk);
292                 ret = PTR_ERR(p->clk);
293                 goto err1;
294         }
295
296         return sh_mtu2_register(p, cfg->name, cfg->clockevent_rating);
297  err1:
298         iounmap(p->mapbase);
299  err0:
300         return ret;
301 }
302
303 static int __devinit sh_mtu2_probe(struct platform_device *pdev)
304 {
305         struct sh_mtu2_priv *p = platform_get_drvdata(pdev);
306         struct sh_timer_config *cfg = pdev->dev.platform_data;
307         int ret;
308
309         if (p) {
310                 pr_info("sh_mtu2: %s kept as earlytimer\n", cfg->name);
311                 return 0;
312         }
313
314         p = kmalloc(sizeof(*p), GFP_KERNEL);
315         if (p == NULL) {
316                 dev_err(&pdev->dev, "failed to allocate driver data\n");
317                 return -ENOMEM;
318         }
319
320         ret = sh_mtu2_setup(p, pdev);
321         if (ret) {
322                 kfree(p);
323                 platform_set_drvdata(pdev, NULL);
324         }
325         return ret;
326 }
327
328 static int __devexit sh_mtu2_remove(struct platform_device *pdev)
329 {
330         return -EBUSY; /* cannot unregister clockevent */
331 }
332
333 static struct platform_driver sh_mtu2_device_driver = {
334         .probe          = sh_mtu2_probe,
335         .remove         = __devexit_p(sh_mtu2_remove),
336         .driver         = {
337                 .name   = "sh_mtu2",
338         }
339 };
340
341 static int __init sh_mtu2_init(void)
342 {
343         return platform_driver_register(&sh_mtu2_device_driver);
344 }
345
346 static void __exit sh_mtu2_exit(void)
347 {
348         platform_driver_unregister(&sh_mtu2_device_driver);
349 }
350
351 early_platform_init("earlytimer", &sh_mtu2_device_driver);
352 module_init(sh_mtu2_init);
353 module_exit(sh_mtu2_exit);
354
355 MODULE_AUTHOR("Magnus Damm");
356 MODULE_DESCRIPTION("SuperH MTU2 Timer Driver");
357 MODULE_LICENSE("GPL v2");