Remove all inclusions of <linux/config.h>
[linux-3.10.git] / drivers / char / watchdog / pnx4008_wdt.c
1 /*
2  * drivers/char/watchdog/pnx4008_wdt.c
3  *
4  * Watchdog driver for PNX4008 board
5  *
6  * Authors: Dmitry Chigirev <source@mvista.com>,
7  *          Vitaly Wool <vitalywool@gmail.com>
8  * Based on sa1100 driver,
9  * Copyright (C) 2000 Oleg Drokin <green@crimea.edu>
10  *
11  * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
12  * the terms of the GNU General Public License version 2. This program
13  * is licensed "as is" without any warranty of any kind, whether express
14  * or implied.
15  */
16
17 #include <linux/module.h>
18 #include <linux/moduleparam.h>
19 #include <linux/types.h>
20 #include <linux/kernel.h>
21 #include <linux/fs.h>
22 #include <linux/miscdevice.h>
23 #include <linux/watchdog.h>
24 #include <linux/init.h>
25 #include <linux/bitops.h>
26 #include <linux/ioport.h>
27 #include <linux/device.h>
28 #include <linux/platform_device.h>
29 #include <linux/clk.h>
30 #include <linux/spinlock.h>
31
32 #include <asm/hardware.h>
33 #include <asm/uaccess.h>
34 #include <asm/io.h>
35
36 #define MODULE_NAME "PNX4008-WDT: "
37
38 /* WatchDog Timer - Chapter 23 Page 207 */
39
40 #define DEFAULT_HEARTBEAT 19
41 #define MAX_HEARTBEAT     60
42
43 /* Watchdog timer register set definition */
44 #define WDTIM_INT(p)     ((p) + 0x0)
45 #define WDTIM_CTRL(p)    ((p) + 0x4)
46 #define WDTIM_COUNTER(p) ((p) + 0x8)
47 #define WDTIM_MCTRL(p)   ((p) + 0xC)
48 #define WDTIM_MATCH0(p)  ((p) + 0x10)
49 #define WDTIM_EMR(p)     ((p) + 0x14)
50 #define WDTIM_PULSE(p)   ((p) + 0x18)
51 #define WDTIM_RES(p)     ((p) + 0x1C)
52
53 /* WDTIM_INT bit definitions */
54 #define MATCH_INT      1
55
56 /* WDTIM_CTRL bit definitions */
57 #define COUNT_ENAB     1
58 #define RESET_COUNT    (1<<1)
59 #define DEBUG_EN       (1<<2)
60
61 /* WDTIM_MCTRL bit definitions */
62 #define MR0_INT        1
63 #undef  RESET_COUNT0
64 #define RESET_COUNT0   (1<<2)
65 #define STOP_COUNT0    (1<<2)
66 #define M_RES1         (1<<3)
67 #define M_RES2         (1<<4)
68 #define RESFRC1        (1<<5)
69 #define RESFRC2        (1<<6)
70
71 /* WDTIM_EMR bit definitions */
72 #define EXT_MATCH0      1
73 #define MATCH_OUTPUT_HIGH (2<<4)        /*a MATCH_CTRL setting */
74
75 /* WDTIM_RES bit definitions */
76 #define WDOG_RESET      1       /* read only */
77
78 #define WDOG_COUNTER_RATE 13000000      /*the counter clock is 13 MHz fixed */
79
80 static int nowayout = WATCHDOG_NOWAYOUT;
81 static int heartbeat = DEFAULT_HEARTBEAT;
82
83 static spinlock_t io_lock;
84 static unsigned long wdt_status;
85 #define WDT_IN_USE        0
86 #define WDT_OK_TO_CLOSE   1
87 #define WDT_REGION_INITED 2
88 #define WDT_DEVICE_INITED 3
89
90 static unsigned long boot_status;
91
92 static struct resource  *wdt_mem;
93 static void __iomem     *wdt_base;
94 struct clk              *wdt_clk;
95
96 static void wdt_enable(void)
97 {
98         spin_lock(&io_lock);
99
100         if (wdt_clk)
101                 clk_set_rate(wdt_clk, 1);
102
103         /* stop counter, initiate counter reset */
104         __raw_writel(RESET_COUNT, WDTIM_CTRL(wdt_base));
105         /*wait for reset to complete. 100% guarantee event */
106         while (__raw_readl(WDTIM_COUNTER(wdt_base)))
107                 cpu_relax();
108         /* internal and external reset, stop after that */
109         __raw_writel(M_RES2 | STOP_COUNT0 | RESET_COUNT0,
110                 WDTIM_MCTRL(wdt_base));
111         /* configure match output */
112         __raw_writel(MATCH_OUTPUT_HIGH, WDTIM_EMR(wdt_base));
113         /* clear interrupt, just in case */
114         __raw_writel(MATCH_INT, WDTIM_INT(wdt_base));
115         /* the longest pulse period 65541/(13*10^6) seconds ~ 5 ms. */
116         __raw_writel(0xFFFF, WDTIM_PULSE(wdt_base));
117         __raw_writel(heartbeat * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base));
118         /*enable counter, stop when debugger active */
119         __raw_writel(COUNT_ENAB | DEBUG_EN, WDTIM_CTRL(wdt_base));
120
121         spin_unlock(&io_lock);
122 }
123
124 static void wdt_disable(void)
125 {
126         spin_lock(&io_lock);
127
128         __raw_writel(0, WDTIM_CTRL(wdt_base));  /*stop counter */
129         if (wdt_clk)
130                 clk_set_rate(wdt_clk, 0);
131
132         spin_unlock(&io_lock);
133 }
134
135 static int pnx4008_wdt_open(struct inode *inode, struct file *file)
136 {
137         if (test_and_set_bit(WDT_IN_USE, &wdt_status))
138                 return -EBUSY;
139
140         clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
141
142         wdt_enable();
143
144         return nonseekable_open(inode, file);
145 }
146
147 static ssize_t
148 pnx4008_wdt_write(struct file *file, const char *data, size_t len,
149                   loff_t * ppos)
150 {
151         /*  Can't seek (pwrite) on this device  */
152         if (ppos != &file->f_pos)
153                 return -ESPIPE;
154
155         if (len) {
156                 if (!nowayout) {
157                         size_t i;
158
159                         clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
160
161                         for (i = 0; i != len; i++) {
162                                 char c;
163
164                                 if (get_user(c, data + i))
165                                         return -EFAULT;
166                                 if (c == 'V')
167                                         set_bit(WDT_OK_TO_CLOSE, &wdt_status);
168                         }
169                 }
170                 wdt_enable();
171         }
172
173         return len;
174 }
175
176 static struct watchdog_info ident = {
177         .options = WDIOF_CARDRESET | WDIOF_MAGICCLOSE |
178             WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
179         .identity = "PNX4008 Watchdog",
180 };
181
182 static int
183 pnx4008_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
184                   unsigned long arg)
185 {
186         int ret = -ENOTTY;
187         int time;
188
189         switch (cmd) {
190         case WDIOC_GETSUPPORT:
191                 ret = copy_to_user((struct watchdog_info *)arg, &ident,
192                                    sizeof(ident)) ? -EFAULT : 0;
193                 break;
194
195         case WDIOC_GETSTATUS:
196                 ret = put_user(0, (int *)arg);
197                 break;
198
199         case WDIOC_GETBOOTSTATUS:
200                 ret = put_user(boot_status, (int *)arg);
201                 break;
202
203         case WDIOC_SETTIMEOUT:
204                 ret = get_user(time, (int *)arg);
205                 if (ret)
206                         break;
207
208                 if (time <= 0 || time > MAX_HEARTBEAT) {
209                         ret = -EINVAL;
210                         break;
211                 }
212
213                 heartbeat = time;
214                 wdt_enable();
215                 /* Fall through */
216
217         case WDIOC_GETTIMEOUT:
218                 ret = put_user(heartbeat, (int *)arg);
219                 break;
220
221         case WDIOC_KEEPALIVE:
222                 wdt_enable();
223                 ret = 0;
224                 break;
225         }
226         return ret;
227 }
228
229 static int pnx4008_wdt_release(struct inode *inode, struct file *file)
230 {
231         if (!test_bit(WDT_OK_TO_CLOSE, &wdt_status))
232                 printk(KERN_WARNING "WATCHDOG: Device closed unexpectdly\n");
233
234         wdt_disable();
235         clear_bit(WDT_IN_USE, &wdt_status);
236         clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
237
238         return 0;
239 }
240
241 static struct file_operations pnx4008_wdt_fops = {
242         .owner = THIS_MODULE,
243         .llseek = no_llseek,
244         .write = pnx4008_wdt_write,
245         .ioctl = pnx4008_wdt_ioctl,
246         .open = pnx4008_wdt_open,
247         .release = pnx4008_wdt_release,
248 };
249
250 static struct miscdevice pnx4008_wdt_miscdev = {
251         .minor = WATCHDOG_MINOR,
252         .name = "watchdog",
253         .fops = &pnx4008_wdt_fops,
254 };
255
256 static int pnx4008_wdt_probe(struct platform_device *pdev)
257 {
258         int ret = 0, size;
259         struct resource *res;
260
261         spin_lock_init(&io_lock);
262
263         if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT)
264                 heartbeat = DEFAULT_HEARTBEAT;
265
266         printk(KERN_INFO MODULE_NAME
267                 "PNX4008 Watchdog Timer: heartbeat %d sec\n", heartbeat);
268
269         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
270         if (res == NULL) {
271                 printk(KERN_INFO MODULE_NAME
272                         "failed to get memory region resouce\n");
273                 return -ENOENT;
274         }
275
276         size = res->end - res->start + 1;
277         wdt_mem = request_mem_region(res->start, size, pdev->name);
278
279         if (wdt_mem == NULL) {
280                 printk(KERN_INFO MODULE_NAME "failed to get memory region\n");
281                 return -ENOENT;
282         }
283         wdt_base = (void __iomem *)IO_ADDRESS(res->start);
284
285         wdt_clk = clk_get(&pdev->dev, "wdt_ck");
286         if (!wdt_clk) {
287                 release_resource(wdt_mem);
288                 kfree(wdt_mem);
289                 goto out;
290         } else
291                 clk_set_rate(wdt_clk, 1);
292
293         ret = misc_register(&pnx4008_wdt_miscdev);
294         if (ret < 0) {
295                 printk(KERN_ERR MODULE_NAME "cannot register misc device\n");
296                 release_resource(wdt_mem);
297                 kfree(wdt_mem);
298                 clk_set_rate(wdt_clk, 0);
299         } else {
300                 boot_status = (__raw_readl(WDTIM_RES(wdt_base)) & WDOG_RESET) ?
301                     WDIOF_CARDRESET : 0;
302                 wdt_disable();          /*disable for now */
303                 set_bit(WDT_DEVICE_INITED, &wdt_status);
304         }
305
306 out:
307         return ret;
308 }
309
310 static int pnx4008_wdt_remove(struct platform_device *pdev)
311 {
312         misc_deregister(&pnx4008_wdt_miscdev);
313         if (wdt_clk) {
314                 clk_set_rate(wdt_clk, 0);
315                 clk_put(wdt_clk);
316                 wdt_clk = NULL;
317         }
318         if (wdt_mem) {
319                 release_resource(wdt_mem);
320                 kfree(wdt_mem);
321                 wdt_mem = NULL;
322         }
323         return 0;
324 }
325
326 static struct platform_driver platform_wdt_driver = {
327         .driver = {
328                 .name = "watchdog",
329         },
330         .probe = pnx4008_wdt_probe,
331         .remove = pnx4008_wdt_remove,
332 };
333
334 static int __init pnx4008_wdt_init(void)
335 {
336         return platform_driver_register(&platform_wdt_driver);
337 }
338
339 static void __exit pnx4008_wdt_exit(void)
340 {
341         return platform_driver_unregister(&platform_wdt_driver);
342 }
343
344 module_init(pnx4008_wdt_init);
345 module_exit(pnx4008_wdt_exit);
346
347 MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
348 MODULE_DESCRIPTION("PNX4008 Watchdog Driver");
349
350 module_param(heartbeat, int, 0);
351 MODULE_PARM_DESC(heartbeat,
352                  "Watchdog heartbeat period in seconds from 1 to "
353                  __MODULE_STRING(MAX_HEARTBEAT) ", default "
354                  __MODULE_STRING(DEFAULT_HEARTBEAT));
355
356 module_param(nowayout, int, 0);
357 MODULE_PARM_DESC(nowayout,
358                  "Set to 1 to keep watchdog running after device release");
359
360 MODULE_LICENSE("GPL");
361 MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);