d4334c79f8d44cece757c8f56630a39a23308fb7
[linux-3.10.git] / drivers / char / synclink_gt.c
1 /*
2  * $Id: synclink_gt.c,v 4.36 2006/08/28 20:47:14 paulkf Exp $
3  *
4  * Device driver for Microgate SyncLink GT serial adapters.
5  *
6  * written by Paul Fulghum for Microgate Corporation
7  * paulkf@microgate.com
8  *
9  * Microgate and SyncLink are trademarks of Microgate Corporation
10  *
11  * This code is released under the GNU General Public License (GPL)
12  *
13  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
17  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
19  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
21  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
22  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
23  * OF THE POSSIBILITY OF SUCH DAMAGE.
24  */
25
26 /*
27  * DEBUG OUTPUT DEFINITIONS
28  *
29  * uncomment lines below to enable specific types of debug output
30  *
31  * DBGINFO   information - most verbose output
32  * DBGERR    serious errors
33  * DBGBH     bottom half service routine debugging
34  * DBGISR    interrupt service routine debugging
35  * DBGDATA   output receive and transmit data
36  * DBGTBUF   output transmit DMA buffers and registers
37  * DBGRBUF   output receive DMA buffers and registers
38  */
39
40 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
41 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
42 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
43 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
44 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
45 //#define DBGTBUF(info) dump_tbufs(info)
46 //#define DBGRBUF(info) dump_rbufs(info)
47
48
49 #include <linux/module.h>
50 #include <linux/version.h>
51 #include <linux/errno.h>
52 #include <linux/signal.h>
53 #include <linux/sched.h>
54 #include <linux/timer.h>
55 #include <linux/interrupt.h>
56 #include <linux/pci.h>
57 #include <linux/tty.h>
58 #include <linux/tty_flip.h>
59 #include <linux/serial.h>
60 #include <linux/major.h>
61 #include <linux/string.h>
62 #include <linux/fcntl.h>
63 #include <linux/ptrace.h>
64 #include <linux/ioport.h>
65 #include <linux/mm.h>
66 #include <linux/slab.h>
67 #include <linux/netdevice.h>
68 #include <linux/vmalloc.h>
69 #include <linux/init.h>
70 #include <linux/delay.h>
71 #include <linux/ioctl.h>
72 #include <linux/termios.h>
73 #include <linux/bitops.h>
74 #include <linux/workqueue.h>
75 #include <linux/hdlc.h>
76
77 #include <asm/system.h>
78 #include <asm/io.h>
79 #include <asm/irq.h>
80 #include <asm/dma.h>
81 #include <asm/types.h>
82 #include <asm/uaccess.h>
83
84 #include "linux/synclink.h"
85
86 #ifdef CONFIG_HDLC_MODULE
87 #define CONFIG_HDLC 1
88 #endif
89
90 /*
91  * module identification
92  */
93 static char *driver_name     = "SyncLink GT";
94 static char *driver_version  = "$Revision: 4.36 $";
95 static char *tty_driver_name = "synclink_gt";
96 static char *tty_dev_prefix  = "ttySLG";
97 MODULE_LICENSE("GPL");
98 #define MGSL_MAGIC 0x5401
99 #define MAX_DEVICES 32
100
101 static struct pci_device_id pci_table[] = {
102         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
103         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
104         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
105         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
106         {0,}, /* terminate list */
107 };
108 MODULE_DEVICE_TABLE(pci, pci_table);
109
110 static int  init_one(struct pci_dev *dev,const struct pci_device_id *ent);
111 static void remove_one(struct pci_dev *dev);
112 static struct pci_driver pci_driver = {
113         .name           = "synclink_gt",
114         .id_table       = pci_table,
115         .probe          = init_one,
116         .remove         = __devexit_p(remove_one),
117 };
118
119 static int pci_registered;
120
121 /*
122  * module configuration and status
123  */
124 static struct slgt_info *slgt_device_list;
125 static int slgt_device_count;
126
127 static int ttymajor;
128 static int debug_level;
129 static int maxframe[MAX_DEVICES];
130 static int dosyncppp[MAX_DEVICES];
131
132 module_param(ttymajor, int, 0);
133 module_param(debug_level, int, 0);
134 module_param_array(maxframe, int, NULL, 0);
135 module_param_array(dosyncppp, int, NULL, 0);
136
137 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
138 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
139 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
140 MODULE_PARM_DESC(dosyncppp, "Enable synchronous net device, 0=disable 1=enable");
141
142 /*
143  * tty support and callbacks
144  */
145 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
146
147 static struct tty_driver *serial_driver;
148
149 static int  open(struct tty_struct *tty, struct file * filp);
150 static void close(struct tty_struct *tty, struct file * filp);
151 static void hangup(struct tty_struct *tty);
152 static void set_termios(struct tty_struct *tty, struct termios *old_termios);
153
154 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
155 static void put_char(struct tty_struct *tty, unsigned char ch);
156 static void send_xchar(struct tty_struct *tty, char ch);
157 static void wait_until_sent(struct tty_struct *tty, int timeout);
158 static int  write_room(struct tty_struct *tty);
159 static void flush_chars(struct tty_struct *tty);
160 static void flush_buffer(struct tty_struct *tty);
161 static void tx_hold(struct tty_struct *tty);
162 static void tx_release(struct tty_struct *tty);
163
164 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
165 static int  read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
166 static int  chars_in_buffer(struct tty_struct *tty);
167 static void throttle(struct tty_struct * tty);
168 static void unthrottle(struct tty_struct * tty);
169 static void set_break(struct tty_struct *tty, int break_state);
170
171 /*
172  * generic HDLC support and callbacks
173  */
174 #ifdef CONFIG_HDLC
175 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
176 static void hdlcdev_tx_done(struct slgt_info *info);
177 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
178 static int  hdlcdev_init(struct slgt_info *info);
179 static void hdlcdev_exit(struct slgt_info *info);
180 #endif
181
182
183 /*
184  * device specific structures, macros and functions
185  */
186
187 #define SLGT_MAX_PORTS 4
188 #define SLGT_REG_SIZE  256
189
190 /*
191  * conditional wait facility
192  */
193 struct cond_wait {
194         struct cond_wait *next;
195         wait_queue_head_t q;
196         wait_queue_t wait;
197         unsigned int data;
198 };
199 static void init_cond_wait(struct cond_wait *w, unsigned int data);
200 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
201 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
202 static void flush_cond_wait(struct cond_wait **head);
203
204 /*
205  * DMA buffer descriptor and access macros
206  */
207 struct slgt_desc
208 {
209         unsigned short count;
210         unsigned short status;
211         unsigned int pbuf;  /* physical address of data buffer */
212         unsigned int next;  /* physical address of next descriptor */
213
214         /* driver book keeping */
215         char *buf;          /* virtual  address of data buffer */
216         unsigned int pdesc; /* physical address of this descriptor */
217         dma_addr_t buf_dma_addr;
218 };
219
220 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
221 #define set_desc_next(a,b) (a).next   = cpu_to_le32((unsigned int)(b))
222 #define set_desc_count(a,b)(a).count  = cpu_to_le16((unsigned short)(b))
223 #define set_desc_eof(a,b)  (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
224 #define desc_count(a)      (le16_to_cpu((a).count))
225 #define desc_status(a)     (le16_to_cpu((a).status))
226 #define desc_complete(a)   (le16_to_cpu((a).status) & BIT15)
227 #define desc_eof(a)        (le16_to_cpu((a).status) & BIT2)
228 #define desc_crc_error(a)  (le16_to_cpu((a).status) & BIT1)
229 #define desc_abort(a)      (le16_to_cpu((a).status) & BIT0)
230 #define desc_residue(a)    ((le16_to_cpu((a).status) & 0x38) >> 3)
231
232 struct _input_signal_events {
233         int ri_up;
234         int ri_down;
235         int dsr_up;
236         int dsr_down;
237         int dcd_up;
238         int dcd_down;
239         int cts_up;
240         int cts_down;
241 };
242
243 /*
244  * device instance data structure
245  */
246 struct slgt_info {
247         void *if_ptr;           /* General purpose pointer (used by SPPP) */
248
249         struct slgt_info *next_device;  /* device list link */
250
251         int magic;
252         int flags;
253
254         char device_name[25];
255         struct pci_dev *pdev;
256
257         int port_count;  /* count of ports on adapter */
258         int adapter_num; /* adapter instance number */
259         int port_num;    /* port instance number */
260
261         /* array of pointers to port contexts on this adapter */
262         struct slgt_info *port_array[SLGT_MAX_PORTS];
263
264         int                     count;          /* count of opens */
265         int                     line;           /* tty line instance number */
266         unsigned short          close_delay;
267         unsigned short          closing_wait;   /* time to wait before closing */
268
269         struct mgsl_icount      icount;
270
271         struct tty_struct       *tty;
272         int                     timeout;
273         int                     x_char;         /* xon/xoff character */
274         int                     blocked_open;   /* # of blocked opens */
275         unsigned int            read_status_mask;
276         unsigned int            ignore_status_mask;
277
278         wait_queue_head_t       open_wait;
279         wait_queue_head_t       close_wait;
280
281         wait_queue_head_t       status_event_wait_q;
282         wait_queue_head_t       event_wait_q;
283         struct timer_list       tx_timer;
284         struct timer_list       rx_timer;
285
286         unsigned int            gpio_present;
287         struct cond_wait        *gpio_wait_q;
288
289         spinlock_t lock;        /* spinlock for synchronizing with ISR */
290
291         struct work_struct task;
292         u32 pending_bh;
293         int bh_requested;
294         int bh_running;
295
296         int isr_overflow;
297         int irq_requested;      /* nonzero if IRQ requested */
298         int irq_occurred;       /* for diagnostics use */
299
300         /* device configuration */
301
302         unsigned int bus_type;
303         unsigned int irq_level;
304         unsigned long irq_flags;
305
306         unsigned char __iomem * reg_addr;  /* memory mapped registers address */
307         u32 phys_reg_addr;
308         int reg_addr_requested;
309
310         MGSL_PARAMS params;       /* communications parameters */
311         u32 idle_mode;
312         u32 max_frame_size;       /* as set by device config */
313
314         unsigned int raw_rx_size;
315         unsigned int if_mode;
316
317         /* device status */
318
319         int rx_enabled;
320         int rx_restart;
321
322         int tx_enabled;
323         int tx_active;
324
325         unsigned char signals;    /* serial signal states */
326         int init_error;  /* initialization error */
327
328         unsigned char *tx_buf;
329         int tx_count;
330
331         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
332         char char_buf[MAX_ASYNC_BUFFER_SIZE];
333         BOOLEAN drop_rts_on_tx_done;
334         struct  _input_signal_events    input_signal_events;
335
336         int dcd_chkcount;       /* check counts to prevent */
337         int cts_chkcount;       /* too many IRQs if a signal */
338         int dsr_chkcount;       /* is floating */
339         int ri_chkcount;
340
341         char *bufs;             /* virtual address of DMA buffer lists */
342         dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
343
344         unsigned int rbuf_count;
345         struct slgt_desc *rbufs;
346         unsigned int rbuf_current;
347         unsigned int rbuf_index;
348
349         unsigned int tbuf_count;
350         struct slgt_desc *tbufs;
351         unsigned int tbuf_current;
352         unsigned int tbuf_start;
353
354         unsigned char *tmp_rbuf;
355         unsigned int tmp_rbuf_count;
356
357         /* SPPP/Cisco HDLC device parts */
358
359         int netcount;
360         int dosyncppp;
361         spinlock_t netlock;
362 #ifdef CONFIG_HDLC
363         struct net_device *netdev;
364 #endif
365
366 };
367
368 static MGSL_PARAMS default_params = {
369         .mode            = MGSL_MODE_HDLC,
370         .loopback        = 0,
371         .flags           = HDLC_FLAG_UNDERRUN_ABORT15,
372         .encoding        = HDLC_ENCODING_NRZI_SPACE,
373         .clock_speed     = 0,
374         .addr_filter     = 0xff,
375         .crc_type        = HDLC_CRC_16_CCITT,
376         .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
377         .preamble        = HDLC_PREAMBLE_PATTERN_NONE,
378         .data_rate       = 9600,
379         .data_bits       = 8,
380         .stop_bits       = 1,
381         .parity          = ASYNC_PARITY_NONE
382 };
383
384
385 #define BH_RECEIVE  1
386 #define BH_TRANSMIT 2
387 #define BH_STATUS   4
388 #define IO_PIN_SHUTDOWN_LIMIT 100
389
390 #define DMABUFSIZE 256
391 #define DESC_LIST_SIZE 4096
392
393 #define MASK_PARITY  BIT1
394 #define MASK_FRAMING BIT0
395 #define MASK_BREAK   BIT14
396 #define MASK_OVERRUN BIT4
397
398 #define GSR   0x00 /* global status */
399 #define JCR   0x04 /* JTAG control */
400 #define IODR  0x08 /* GPIO direction */
401 #define IOER  0x0c /* GPIO interrupt enable */
402 #define IOVR  0x10 /* GPIO value */
403 #define IOSR  0x14 /* GPIO interrupt status */
404 #define TDR   0x80 /* tx data */
405 #define RDR   0x80 /* rx data */
406 #define TCR   0x82 /* tx control */
407 #define TIR   0x84 /* tx idle */
408 #define TPR   0x85 /* tx preamble */
409 #define RCR   0x86 /* rx control */
410 #define VCR   0x88 /* V.24 control */
411 #define CCR   0x89 /* clock control */
412 #define BDR   0x8a /* baud divisor */
413 #define SCR   0x8c /* serial control */
414 #define SSR   0x8e /* serial status */
415 #define RDCSR 0x90 /* rx DMA control/status */
416 #define TDCSR 0x94 /* tx DMA control/status */
417 #define RDDAR 0x98 /* rx DMA descriptor address */
418 #define TDDAR 0x9c /* tx DMA descriptor address */
419
420 #define RXIDLE      BIT14
421 #define RXBREAK     BIT14
422 #define IRQ_TXDATA  BIT13
423 #define IRQ_TXIDLE  BIT12
424 #define IRQ_TXUNDER BIT11 /* HDLC */
425 #define IRQ_RXDATA  BIT10
426 #define IRQ_RXIDLE  BIT9  /* HDLC */
427 #define IRQ_RXBREAK BIT9  /* async */
428 #define IRQ_RXOVER  BIT8
429 #define IRQ_DSR     BIT7
430 #define IRQ_CTS     BIT6
431 #define IRQ_DCD     BIT5
432 #define IRQ_RI      BIT4
433 #define IRQ_ALL     0x3ff0
434 #define IRQ_MASTER  BIT0
435
436 #define slgt_irq_on(info, mask) \
437         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
438 #define slgt_irq_off(info, mask) \
439         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
440
441 static __u8  rd_reg8(struct slgt_info *info, unsigned int addr);
442 static void  wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
443 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
444 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
445 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
446 static void  wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
447
448 static void  msc_set_vcr(struct slgt_info *info);
449
450 static int  startup(struct slgt_info *info);
451 static int  block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
452 static void shutdown(struct slgt_info *info);
453 static void program_hw(struct slgt_info *info);
454 static void change_params(struct slgt_info *info);
455
456 static int  register_test(struct slgt_info *info);
457 static int  irq_test(struct slgt_info *info);
458 static int  loopback_test(struct slgt_info *info);
459 static int  adapter_test(struct slgt_info *info);
460
461 static void reset_adapter(struct slgt_info *info);
462 static void reset_port(struct slgt_info *info);
463 static void async_mode(struct slgt_info *info);
464 static void sync_mode(struct slgt_info *info);
465
466 static void rx_stop(struct slgt_info *info);
467 static void rx_start(struct slgt_info *info);
468 static void reset_rbufs(struct slgt_info *info);
469 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
470 static void rdma_reset(struct slgt_info *info);
471 static int  rx_get_frame(struct slgt_info *info);
472 static int  rx_get_buf(struct slgt_info *info);
473
474 static void tx_start(struct slgt_info *info);
475 static void tx_stop(struct slgt_info *info);
476 static void tx_set_idle(struct slgt_info *info);
477 static unsigned int free_tbuf_count(struct slgt_info *info);
478 static void reset_tbufs(struct slgt_info *info);
479 static void tdma_reset(struct slgt_info *info);
480 static void tx_load(struct slgt_info *info, const char *buf, unsigned int count);
481
482 static void get_signals(struct slgt_info *info);
483 static void set_signals(struct slgt_info *info);
484 static void enable_loopback(struct slgt_info *info);
485 static void set_rate(struct slgt_info *info, u32 data_rate);
486
487 static int  bh_action(struct slgt_info *info);
488 static void bh_handler(void* context);
489 static void bh_transmit(struct slgt_info *info);
490 static void isr_serial(struct slgt_info *info);
491 static void isr_rdma(struct slgt_info *info);
492 static void isr_txeom(struct slgt_info *info, unsigned short status);
493 static void isr_tdma(struct slgt_info *info);
494 static irqreturn_t slgt_interrupt(int irq, void *dev_id);
495
496 static int  alloc_dma_bufs(struct slgt_info *info);
497 static void free_dma_bufs(struct slgt_info *info);
498 static int  alloc_desc(struct slgt_info *info);
499 static void free_desc(struct slgt_info *info);
500 static int  alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
501 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
502
503 static int  alloc_tmp_rbuf(struct slgt_info *info);
504 static void free_tmp_rbuf(struct slgt_info *info);
505
506 static void tx_timeout(unsigned long context);
507 static void rx_timeout(unsigned long context);
508
509 /*
510  * ioctl handlers
511  */
512 static int  get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
513 static int  get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
514 static int  set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
515 static int  get_txidle(struct slgt_info *info, int __user *idle_mode);
516 static int  set_txidle(struct slgt_info *info, int idle_mode);
517 static int  tx_enable(struct slgt_info *info, int enable);
518 static int  tx_abort(struct slgt_info *info);
519 static int  rx_enable(struct slgt_info *info, int enable);
520 static int  modem_input_wait(struct slgt_info *info,int arg);
521 static int  wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
522 static int  tiocmget(struct tty_struct *tty, struct file *file);
523 static int  tiocmset(struct tty_struct *tty, struct file *file,
524                      unsigned int set, unsigned int clear);
525 static void set_break(struct tty_struct *tty, int break_state);
526 static int  get_interface(struct slgt_info *info, int __user *if_mode);
527 static int  set_interface(struct slgt_info *info, int if_mode);
528 static int  set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
529 static int  get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
530 static int  wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
531
532 /*
533  * driver functions
534  */
535 static void add_device(struct slgt_info *info);
536 static void device_init(int adapter_num, struct pci_dev *pdev);
537 static int  claim_resources(struct slgt_info *info);
538 static void release_resources(struct slgt_info *info);
539
540 /*
541  * DEBUG OUTPUT CODE
542  */
543 #ifndef DBGINFO
544 #define DBGINFO(fmt)
545 #endif
546 #ifndef DBGERR
547 #define DBGERR(fmt)
548 #endif
549 #ifndef DBGBH
550 #define DBGBH(fmt)
551 #endif
552 #ifndef DBGISR
553 #define DBGISR(fmt)
554 #endif
555
556 #ifdef DBGDATA
557 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
558 {
559         int i;
560         int linecount;
561         printk("%s %s data:\n",info->device_name, label);
562         while(count) {
563                 linecount = (count > 16) ? 16 : count;
564                 for(i=0; i < linecount; i++)
565                         printk("%02X ",(unsigned char)data[i]);
566                 for(;i<17;i++)
567                         printk("   ");
568                 for(i=0;i<linecount;i++) {
569                         if (data[i]>=040 && data[i]<=0176)
570                                 printk("%c",data[i]);
571                         else
572                                 printk(".");
573                 }
574                 printk("\n");
575                 data  += linecount;
576                 count -= linecount;
577         }
578 }
579 #else
580 #define DBGDATA(info, buf, size, label)
581 #endif
582
583 #ifdef DBGTBUF
584 static void dump_tbufs(struct slgt_info *info)
585 {
586         int i;
587         printk("tbuf_current=%d\n", info->tbuf_current);
588         for (i=0 ; i < info->tbuf_count ; i++) {
589                 printk("%d: count=%04X status=%04X\n",
590                         i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
591         }
592 }
593 #else
594 #define DBGTBUF(info)
595 #endif
596
597 #ifdef DBGRBUF
598 static void dump_rbufs(struct slgt_info *info)
599 {
600         int i;
601         printk("rbuf_current=%d\n", info->rbuf_current);
602         for (i=0 ; i < info->rbuf_count ; i++) {
603                 printk("%d: count=%04X status=%04X\n",
604                         i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
605         }
606 }
607 #else
608 #define DBGRBUF(info)
609 #endif
610
611 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
612 {
613 #ifdef SANITY_CHECK
614         if (!info) {
615                 printk("null struct slgt_info for (%s) in %s\n", devname, name);
616                 return 1;
617         }
618         if (info->magic != MGSL_MAGIC) {
619                 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
620                 return 1;
621         }
622 #else
623         if (!info)
624                 return 1;
625 #endif
626         return 0;
627 }
628
629 /**
630  * line discipline callback wrappers
631  *
632  * The wrappers maintain line discipline references
633  * while calling into the line discipline.
634  *
635  * ldisc_receive_buf  - pass receive data to line discipline
636  */
637 static void ldisc_receive_buf(struct tty_struct *tty,
638                               const __u8 *data, char *flags, int count)
639 {
640         struct tty_ldisc *ld;
641         if (!tty)
642                 return;
643         ld = tty_ldisc_ref(tty);
644         if (ld) {
645                 if (ld->receive_buf)
646                         ld->receive_buf(tty, data, flags, count);
647                 tty_ldisc_deref(ld);
648         }
649 }
650
651 /* tty callbacks */
652
653 static int open(struct tty_struct *tty, struct file *filp)
654 {
655         struct slgt_info *info;
656         int retval, line;
657         unsigned long flags;
658
659         line = tty->index;
660         if ((line < 0) || (line >= slgt_device_count)) {
661                 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
662                 return -ENODEV;
663         }
664
665         info = slgt_device_list;
666         while(info && info->line != line)
667                 info = info->next_device;
668         if (sanity_check(info, tty->name, "open"))
669                 return -ENODEV;
670         if (info->init_error) {
671                 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
672                 return -ENODEV;
673         }
674
675         tty->driver_data = info;
676         info->tty = tty;
677
678         DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->count));
679
680         /* If port is closing, signal caller to try again */
681         if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
682                 if (info->flags & ASYNC_CLOSING)
683                         interruptible_sleep_on(&info->close_wait);
684                 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
685                         -EAGAIN : -ERESTARTSYS);
686                 goto cleanup;
687         }
688
689         info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
690
691         spin_lock_irqsave(&info->netlock, flags);
692         if (info->netcount) {
693                 retval = -EBUSY;
694                 spin_unlock_irqrestore(&info->netlock, flags);
695                 goto cleanup;
696         }
697         info->count++;
698         spin_unlock_irqrestore(&info->netlock, flags);
699
700         if (info->count == 1) {
701                 /* 1st open on this device, init hardware */
702                 retval = startup(info);
703                 if (retval < 0)
704                         goto cleanup;
705         }
706
707         retval = block_til_ready(tty, filp, info);
708         if (retval) {
709                 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
710                 goto cleanup;
711         }
712
713         retval = 0;
714
715 cleanup:
716         if (retval) {
717                 if (tty->count == 1)
718                         info->tty = NULL; /* tty layer will release tty struct */
719                 if(info->count)
720                         info->count--;
721         }
722
723         DBGINFO(("%s open rc=%d\n", info->device_name, retval));
724         return retval;
725 }
726
727 static void close(struct tty_struct *tty, struct file *filp)
728 {
729         struct slgt_info *info = tty->driver_data;
730
731         if (sanity_check(info, tty->name, "close"))
732                 return;
733         DBGINFO(("%s close entry, count=%d\n", info->device_name, info->count));
734
735         if (!info->count)
736                 return;
737
738         if (tty_hung_up_p(filp))
739                 goto cleanup;
740
741         if ((tty->count == 1) && (info->count != 1)) {
742                 /*
743                  * tty->count is 1 and the tty structure will be freed.
744                  * info->count should be one in this case.
745                  * if it's not, correct it so that the port is shutdown.
746                  */
747                 DBGERR(("%s close: bad refcount; tty->count=1, "
748                        "info->count=%d\n", info->device_name, info->count));
749                 info->count = 1;
750         }
751
752         info->count--;
753
754         /* if at least one open remaining, leave hardware active */
755         if (info->count)
756                 goto cleanup;
757
758         info->flags |= ASYNC_CLOSING;
759
760         /* set tty->closing to notify line discipline to
761          * only process XON/XOFF characters. Only the N_TTY
762          * discipline appears to use this (ppp does not).
763          */
764         tty->closing = 1;
765
766         /* wait for transmit data to clear all layers */
767
768         if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
769                 DBGINFO(("%s call tty_wait_until_sent\n", info->device_name));
770                 tty_wait_until_sent(tty, info->closing_wait);
771         }
772
773         if (info->flags & ASYNC_INITIALIZED)
774                 wait_until_sent(tty, info->timeout);
775         if (tty->driver->flush_buffer)
776                 tty->driver->flush_buffer(tty);
777         tty_ldisc_flush(tty);
778
779         shutdown(info);
780
781         tty->closing = 0;
782         info->tty = NULL;
783
784         if (info->blocked_open) {
785                 if (info->close_delay) {
786                         msleep_interruptible(jiffies_to_msecs(info->close_delay));
787                 }
788                 wake_up_interruptible(&info->open_wait);
789         }
790
791         info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
792
793         wake_up_interruptible(&info->close_wait);
794
795 cleanup:
796         DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->count));
797 }
798
799 static void hangup(struct tty_struct *tty)
800 {
801         struct slgt_info *info = tty->driver_data;
802
803         if (sanity_check(info, tty->name, "hangup"))
804                 return;
805         DBGINFO(("%s hangup\n", info->device_name));
806
807         flush_buffer(tty);
808         shutdown(info);
809
810         info->count = 0;
811         info->flags &= ~ASYNC_NORMAL_ACTIVE;
812         info->tty = NULL;
813
814         wake_up_interruptible(&info->open_wait);
815 }
816
817 static void set_termios(struct tty_struct *tty, struct termios *old_termios)
818 {
819         struct slgt_info *info = tty->driver_data;
820         unsigned long flags;
821
822         DBGINFO(("%s set_termios\n", tty->driver->name));
823
824         /* just return if nothing has changed */
825         if ((tty->termios->c_cflag == old_termios->c_cflag)
826             && (RELEVANT_IFLAG(tty->termios->c_iflag)
827                 == RELEVANT_IFLAG(old_termios->c_iflag)))
828                 return;
829
830         change_params(info);
831
832         /* Handle transition to B0 status */
833         if (old_termios->c_cflag & CBAUD &&
834             !(tty->termios->c_cflag & CBAUD)) {
835                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
836                 spin_lock_irqsave(&info->lock,flags);
837                 set_signals(info);
838                 spin_unlock_irqrestore(&info->lock,flags);
839         }
840
841         /* Handle transition away from B0 status */
842         if (!(old_termios->c_cflag & CBAUD) &&
843             tty->termios->c_cflag & CBAUD) {
844                 info->signals |= SerialSignal_DTR;
845                 if (!(tty->termios->c_cflag & CRTSCTS) ||
846                     !test_bit(TTY_THROTTLED, &tty->flags)) {
847                         info->signals |= SerialSignal_RTS;
848                 }
849                 spin_lock_irqsave(&info->lock,flags);
850                 set_signals(info);
851                 spin_unlock_irqrestore(&info->lock,flags);
852         }
853
854         /* Handle turning off CRTSCTS */
855         if (old_termios->c_cflag & CRTSCTS &&
856             !(tty->termios->c_cflag & CRTSCTS)) {
857                 tty->hw_stopped = 0;
858                 tx_release(tty);
859         }
860 }
861
862 static int write(struct tty_struct *tty,
863                  const unsigned char *buf, int count)
864 {
865         int ret = 0;
866         struct slgt_info *info = tty->driver_data;
867         unsigned long flags;
868
869         if (sanity_check(info, tty->name, "write"))
870                 goto cleanup;
871         DBGINFO(("%s write count=%d\n", info->device_name, count));
872
873         if (!info->tx_buf)
874                 goto cleanup;
875
876         if (count > info->max_frame_size) {
877                 ret = -EIO;
878                 goto cleanup;
879         }
880
881         if (!count)
882                 goto cleanup;
883
884         if (info->params.mode == MGSL_MODE_RAW ||
885             info->params.mode == MGSL_MODE_MONOSYNC ||
886             info->params.mode == MGSL_MODE_BISYNC) {
887                 unsigned int bufs_needed = (count/DMABUFSIZE);
888                 unsigned int bufs_free = free_tbuf_count(info);
889                 if (count % DMABUFSIZE)
890                         ++bufs_needed;
891                 if (bufs_needed > bufs_free)
892                         goto cleanup;
893         } else {
894                 if (info->tx_active)
895                         goto cleanup;
896                 if (info->tx_count) {
897                         /* send accumulated data from send_char() calls */
898                         /* as frame and wait before accepting more data. */
899                         tx_load(info, info->tx_buf, info->tx_count);
900                         goto start;
901                 }
902         }
903
904         ret = info->tx_count = count;
905         tx_load(info, buf, count);
906         goto start;
907
908 start:
909         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
910                 spin_lock_irqsave(&info->lock,flags);
911                 if (!info->tx_active)
912                         tx_start(info);
913                 spin_unlock_irqrestore(&info->lock,flags);
914         }
915
916 cleanup:
917         DBGINFO(("%s write rc=%d\n", info->device_name, ret));
918         return ret;
919 }
920
921 static void put_char(struct tty_struct *tty, unsigned char ch)
922 {
923         struct slgt_info *info = tty->driver_data;
924         unsigned long flags;
925
926         if (sanity_check(info, tty->name, "put_char"))
927                 return;
928         DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
929         if (!info->tx_buf)
930                 return;
931         spin_lock_irqsave(&info->lock,flags);
932         if (!info->tx_active && (info->tx_count < info->max_frame_size))
933                 info->tx_buf[info->tx_count++] = ch;
934         spin_unlock_irqrestore(&info->lock,flags);
935 }
936
937 static void send_xchar(struct tty_struct *tty, char ch)
938 {
939         struct slgt_info *info = tty->driver_data;
940         unsigned long flags;
941
942         if (sanity_check(info, tty->name, "send_xchar"))
943                 return;
944         DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
945         info->x_char = ch;
946         if (ch) {
947                 spin_lock_irqsave(&info->lock,flags);
948                 if (!info->tx_enabled)
949                         tx_start(info);
950                 spin_unlock_irqrestore(&info->lock,flags);
951         }
952 }
953
954 static void wait_until_sent(struct tty_struct *tty, int timeout)
955 {
956         struct slgt_info *info = tty->driver_data;
957         unsigned long orig_jiffies, char_time;
958
959         if (!info )
960                 return;
961         if (sanity_check(info, tty->name, "wait_until_sent"))
962                 return;
963         DBGINFO(("%s wait_until_sent entry\n", info->device_name));
964         if (!(info->flags & ASYNC_INITIALIZED))
965                 goto exit;
966
967         orig_jiffies = jiffies;
968
969         /* Set check interval to 1/5 of estimated time to
970          * send a character, and make it at least 1. The check
971          * interval should also be less than the timeout.
972          * Note: use tight timings here to satisfy the NIST-PCTS.
973          */
974
975         if (info->params.data_rate) {
976                 char_time = info->timeout/(32 * 5);
977                 if (!char_time)
978                         char_time++;
979         } else
980                 char_time = 1;
981
982         if (timeout)
983                 char_time = min_t(unsigned long, char_time, timeout);
984
985         while (info->tx_active) {
986                 msleep_interruptible(jiffies_to_msecs(char_time));
987                 if (signal_pending(current))
988                         break;
989                 if (timeout && time_after(jiffies, orig_jiffies + timeout))
990                         break;
991         }
992
993 exit:
994         DBGINFO(("%s wait_until_sent exit\n", info->device_name));
995 }
996
997 static int write_room(struct tty_struct *tty)
998 {
999         struct slgt_info *info = tty->driver_data;
1000         int ret;
1001
1002         if (sanity_check(info, tty->name, "write_room"))
1003                 return 0;
1004         ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1005         DBGINFO(("%s write_room=%d\n", info->device_name, ret));
1006         return ret;
1007 }
1008
1009 static void flush_chars(struct tty_struct *tty)
1010 {
1011         struct slgt_info *info = tty->driver_data;
1012         unsigned long flags;
1013
1014         if (sanity_check(info, tty->name, "flush_chars"))
1015                 return;
1016         DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
1017
1018         if (info->tx_count <= 0 || tty->stopped ||
1019             tty->hw_stopped || !info->tx_buf)
1020                 return;
1021
1022         DBGINFO(("%s flush_chars start transmit\n", info->device_name));
1023
1024         spin_lock_irqsave(&info->lock,flags);
1025         if (!info->tx_active && info->tx_count) {
1026                 tx_load(info, info->tx_buf,info->tx_count);
1027                 tx_start(info);
1028         }
1029         spin_unlock_irqrestore(&info->lock,flags);
1030 }
1031
1032 static void flush_buffer(struct tty_struct *tty)
1033 {
1034         struct slgt_info *info = tty->driver_data;
1035         unsigned long flags;
1036
1037         if (sanity_check(info, tty->name, "flush_buffer"))
1038                 return;
1039         DBGINFO(("%s flush_buffer\n", info->device_name));
1040
1041         spin_lock_irqsave(&info->lock,flags);
1042         if (!info->tx_active)
1043                 info->tx_count = 0;
1044         spin_unlock_irqrestore(&info->lock,flags);
1045
1046         wake_up_interruptible(&tty->write_wait);
1047         tty_wakeup(tty);
1048 }
1049
1050 /*
1051  * throttle (stop) transmitter
1052  */
1053 static void tx_hold(struct tty_struct *tty)
1054 {
1055         struct slgt_info *info = tty->driver_data;
1056         unsigned long flags;
1057
1058         if (sanity_check(info, tty->name, "tx_hold"))
1059                 return;
1060         DBGINFO(("%s tx_hold\n", info->device_name));
1061         spin_lock_irqsave(&info->lock,flags);
1062         if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
1063                 tx_stop(info);
1064         spin_unlock_irqrestore(&info->lock,flags);
1065 }
1066
1067 /*
1068  * release (start) transmitter
1069  */
1070 static void tx_release(struct tty_struct *tty)
1071 {
1072         struct slgt_info *info = tty->driver_data;
1073         unsigned long flags;
1074
1075         if (sanity_check(info, tty->name, "tx_release"))
1076                 return;
1077         DBGINFO(("%s tx_release\n", info->device_name));
1078         spin_lock_irqsave(&info->lock,flags);
1079         if (!info->tx_active && info->tx_count) {
1080                 tx_load(info, info->tx_buf, info->tx_count);
1081                 tx_start(info);
1082         }
1083         spin_unlock_irqrestore(&info->lock,flags);
1084 }
1085
1086 /*
1087  * Service an IOCTL request
1088  *
1089  * Arguments
1090  *
1091  *      tty     pointer to tty instance data
1092  *      file    pointer to associated file object for device
1093  *      cmd     IOCTL command code
1094  *      arg     command argument/context
1095  *
1096  * Return 0 if success, otherwise error code
1097  */
1098 static int ioctl(struct tty_struct *tty, struct file *file,
1099                  unsigned int cmd, unsigned long arg)
1100 {
1101         struct slgt_info *info = tty->driver_data;
1102         struct mgsl_icount cnow;        /* kernel counter temps */
1103         struct serial_icounter_struct __user *p_cuser;  /* user space */
1104         unsigned long flags;
1105         void __user *argp = (void __user *)arg;
1106
1107         if (sanity_check(info, tty->name, "ioctl"))
1108                 return -ENODEV;
1109         DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1110
1111         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1112             (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1113                 if (tty->flags & (1 << TTY_IO_ERROR))
1114                     return -EIO;
1115         }
1116
1117         switch (cmd) {
1118         case MGSL_IOCGPARAMS:
1119                 return get_params(info, argp);
1120         case MGSL_IOCSPARAMS:
1121                 return set_params(info, argp);
1122         case MGSL_IOCGTXIDLE:
1123                 return get_txidle(info, argp);
1124         case MGSL_IOCSTXIDLE:
1125                 return set_txidle(info, (int)arg);
1126         case MGSL_IOCTXENABLE:
1127                 return tx_enable(info, (int)arg);
1128         case MGSL_IOCRXENABLE:
1129                 return rx_enable(info, (int)arg);
1130         case MGSL_IOCTXABORT:
1131                 return tx_abort(info);
1132         case MGSL_IOCGSTATS:
1133                 return get_stats(info, argp);
1134         case MGSL_IOCWAITEVENT:
1135                 return wait_mgsl_event(info, argp);
1136         case TIOCMIWAIT:
1137                 return modem_input_wait(info,(int)arg);
1138         case MGSL_IOCGIF:
1139                 return get_interface(info, argp);
1140         case MGSL_IOCSIF:
1141                 return set_interface(info,(int)arg);
1142         case MGSL_IOCSGPIO:
1143                 return set_gpio(info, argp);
1144         case MGSL_IOCGGPIO:
1145                 return get_gpio(info, argp);
1146         case MGSL_IOCWAITGPIO:
1147                 return wait_gpio(info, argp);
1148         case TIOCGICOUNT:
1149                 spin_lock_irqsave(&info->lock,flags);
1150                 cnow = info->icount;
1151                 spin_unlock_irqrestore(&info->lock,flags);
1152                 p_cuser = argp;
1153                 if (put_user(cnow.cts, &p_cuser->cts) ||
1154                     put_user(cnow.dsr, &p_cuser->dsr) ||
1155                     put_user(cnow.rng, &p_cuser->rng) ||
1156                     put_user(cnow.dcd, &p_cuser->dcd) ||
1157                     put_user(cnow.rx, &p_cuser->rx) ||
1158                     put_user(cnow.tx, &p_cuser->tx) ||
1159                     put_user(cnow.frame, &p_cuser->frame) ||
1160                     put_user(cnow.overrun, &p_cuser->overrun) ||
1161                     put_user(cnow.parity, &p_cuser->parity) ||
1162                     put_user(cnow.brk, &p_cuser->brk) ||
1163                     put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1164                         return -EFAULT;
1165                 return 0;
1166         default:
1167                 return -ENOIOCTLCMD;
1168         }
1169         return 0;
1170 }
1171
1172 /*
1173  * proc fs support
1174  */
1175 static inline int line_info(char *buf, struct slgt_info *info)
1176 {
1177         char stat_buf[30];
1178         int ret;
1179         unsigned long flags;
1180
1181         ret = sprintf(buf, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1182                       info->device_name, info->phys_reg_addr,
1183                       info->irq_level, info->max_frame_size);
1184
1185         /* output current serial signal states */
1186         spin_lock_irqsave(&info->lock,flags);
1187         get_signals(info);
1188         spin_unlock_irqrestore(&info->lock,flags);
1189
1190         stat_buf[0] = 0;
1191         stat_buf[1] = 0;
1192         if (info->signals & SerialSignal_RTS)
1193                 strcat(stat_buf, "|RTS");
1194         if (info->signals & SerialSignal_CTS)
1195                 strcat(stat_buf, "|CTS");
1196         if (info->signals & SerialSignal_DTR)
1197                 strcat(stat_buf, "|DTR");
1198         if (info->signals & SerialSignal_DSR)
1199                 strcat(stat_buf, "|DSR");
1200         if (info->signals & SerialSignal_DCD)
1201                 strcat(stat_buf, "|CD");
1202         if (info->signals & SerialSignal_RI)
1203                 strcat(stat_buf, "|RI");
1204
1205         if (info->params.mode != MGSL_MODE_ASYNC) {
1206                 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1207                                info->icount.txok, info->icount.rxok);
1208                 if (info->icount.txunder)
1209                         ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1210                 if (info->icount.txabort)
1211                         ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1212                 if (info->icount.rxshort)
1213                         ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1214                 if (info->icount.rxlong)
1215                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1216                 if (info->icount.rxover)
1217                         ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1218                 if (info->icount.rxcrc)
1219                         ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
1220         } else {
1221                 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1222                                info->icount.tx, info->icount.rx);
1223                 if (info->icount.frame)
1224                         ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1225                 if (info->icount.parity)
1226                         ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1227                 if (info->icount.brk)
1228                         ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1229                 if (info->icount.overrun)
1230                         ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1231         }
1232
1233         /* Append serial signal status to end */
1234         ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1235
1236         ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1237                        info->tx_active,info->bh_requested,info->bh_running,
1238                        info->pending_bh);
1239
1240         return ret;
1241 }
1242
1243 /* Called to print information about devices
1244  */
1245 static int read_proc(char *page, char **start, off_t off, int count,
1246                      int *eof, void *data)
1247 {
1248         int len = 0, l;
1249         off_t   begin = 0;
1250         struct slgt_info *info;
1251
1252         len += sprintf(page, "synclink_gt driver:%s\n", driver_version);
1253
1254         info = slgt_device_list;
1255         while( info ) {
1256                 l = line_info(page + len, info);
1257                 len += l;
1258                 if (len+begin > off+count)
1259                         goto done;
1260                 if (len+begin < off) {
1261                         begin += len;
1262                         len = 0;
1263                 }
1264                 info = info->next_device;
1265         }
1266
1267         *eof = 1;
1268 done:
1269         if (off >= len+begin)
1270                 return 0;
1271         *start = page + (off-begin);
1272         return ((count < begin+len-off) ? count : begin+len-off);
1273 }
1274
1275 /*
1276  * return count of bytes in transmit buffer
1277  */
1278 static int chars_in_buffer(struct tty_struct *tty)
1279 {
1280         struct slgt_info *info = tty->driver_data;
1281         if (sanity_check(info, tty->name, "chars_in_buffer"))
1282                 return 0;
1283         DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, info->tx_count));
1284         return info->tx_count;
1285 }
1286
1287 /*
1288  * signal remote device to throttle send data (our receive data)
1289  */
1290 static void throttle(struct tty_struct * tty)
1291 {
1292         struct slgt_info *info = tty->driver_data;
1293         unsigned long flags;
1294
1295         if (sanity_check(info, tty->name, "throttle"))
1296                 return;
1297         DBGINFO(("%s throttle\n", info->device_name));
1298         if (I_IXOFF(tty))
1299                 send_xchar(tty, STOP_CHAR(tty));
1300         if (tty->termios->c_cflag & CRTSCTS) {
1301                 spin_lock_irqsave(&info->lock,flags);
1302                 info->signals &= ~SerialSignal_RTS;
1303                 set_signals(info);
1304                 spin_unlock_irqrestore(&info->lock,flags);
1305         }
1306 }
1307
1308 /*
1309  * signal remote device to stop throttling send data (our receive data)
1310  */
1311 static void unthrottle(struct tty_struct * tty)
1312 {
1313         struct slgt_info *info = tty->driver_data;
1314         unsigned long flags;
1315
1316         if (sanity_check(info, tty->name, "unthrottle"))
1317                 return;
1318         DBGINFO(("%s unthrottle\n", info->device_name));
1319         if (I_IXOFF(tty)) {
1320                 if (info->x_char)
1321                         info->x_char = 0;
1322                 else
1323                         send_xchar(tty, START_CHAR(tty));
1324         }
1325         if (tty->termios->c_cflag & CRTSCTS) {
1326                 spin_lock_irqsave(&info->lock,flags);
1327                 info->signals |= SerialSignal_RTS;
1328                 set_signals(info);
1329                 spin_unlock_irqrestore(&info->lock,flags);
1330         }
1331 }
1332
1333 /*
1334  * set or clear transmit break condition
1335  * break_state  -1=set break condition, 0=clear
1336  */
1337 static void set_break(struct tty_struct *tty, int break_state)
1338 {
1339         struct slgt_info *info = tty->driver_data;
1340         unsigned short value;
1341         unsigned long flags;
1342
1343         if (sanity_check(info, tty->name, "set_break"))
1344                 return;
1345         DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1346
1347         spin_lock_irqsave(&info->lock,flags);
1348         value = rd_reg16(info, TCR);
1349         if (break_state == -1)
1350                 value |= BIT6;
1351         else
1352                 value &= ~BIT6;
1353         wr_reg16(info, TCR, value);
1354         spin_unlock_irqrestore(&info->lock,flags);
1355 }
1356
1357 #ifdef CONFIG_HDLC
1358
1359 /**
1360  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1361  * set encoding and frame check sequence (FCS) options
1362  *
1363  * dev       pointer to network device structure
1364  * encoding  serial encoding setting
1365  * parity    FCS setting
1366  *
1367  * returns 0 if success, otherwise error code
1368  */
1369 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1370                           unsigned short parity)
1371 {
1372         struct slgt_info *info = dev_to_port(dev);
1373         unsigned char  new_encoding;
1374         unsigned short new_crctype;
1375
1376         /* return error if TTY interface open */
1377         if (info->count)
1378                 return -EBUSY;
1379
1380         DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1381
1382         switch (encoding)
1383         {
1384         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1385         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1386         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1387         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1388         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1389         default: return -EINVAL;
1390         }
1391
1392         switch (parity)
1393         {
1394         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1395         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1396         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1397         default: return -EINVAL;
1398         }
1399
1400         info->params.encoding = new_encoding;
1401         info->params.crc_type = new_crctype;
1402
1403         /* if network interface up, reprogram hardware */
1404         if (info->netcount)
1405                 program_hw(info);
1406
1407         return 0;
1408 }
1409
1410 /**
1411  * called by generic HDLC layer to send frame
1412  *
1413  * skb  socket buffer containing HDLC frame
1414  * dev  pointer to network device structure
1415  *
1416  * returns 0 if success, otherwise error code
1417  */
1418 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1419 {
1420         struct slgt_info *info = dev_to_port(dev);
1421         struct net_device_stats *stats = hdlc_stats(dev);
1422         unsigned long flags;
1423
1424         DBGINFO(("%s hdlc_xmit\n", dev->name));
1425
1426         /* stop sending until this frame completes */
1427         netif_stop_queue(dev);
1428
1429         /* copy data to device buffers */
1430         info->tx_count = skb->len;
1431         tx_load(info, skb->data, skb->len);
1432
1433         /* update network statistics */
1434         stats->tx_packets++;
1435         stats->tx_bytes += skb->len;
1436
1437         /* done with socket buffer, so free it */
1438         dev_kfree_skb(skb);
1439
1440         /* save start time for transmit timeout detection */
1441         dev->trans_start = jiffies;
1442
1443         /* start hardware transmitter if necessary */
1444         spin_lock_irqsave(&info->lock,flags);
1445         if (!info->tx_active)
1446                 tx_start(info);
1447         spin_unlock_irqrestore(&info->lock,flags);
1448
1449         return 0;
1450 }
1451
1452 /**
1453  * called by network layer when interface enabled
1454  * claim resources and initialize hardware
1455  *
1456  * dev  pointer to network device structure
1457  *
1458  * returns 0 if success, otherwise error code
1459  */
1460 static int hdlcdev_open(struct net_device *dev)
1461 {
1462         struct slgt_info *info = dev_to_port(dev);
1463         int rc;
1464         unsigned long flags;
1465
1466         DBGINFO(("%s hdlcdev_open\n", dev->name));
1467
1468         /* generic HDLC layer open processing */
1469         if ((rc = hdlc_open(dev)))
1470                 return rc;
1471
1472         /* arbitrate between network and tty opens */
1473         spin_lock_irqsave(&info->netlock, flags);
1474         if (info->count != 0 || info->netcount != 0) {
1475                 DBGINFO(("%s hdlc_open busy\n", dev->name));
1476                 spin_unlock_irqrestore(&info->netlock, flags);
1477                 return -EBUSY;
1478         }
1479         info->netcount=1;
1480         spin_unlock_irqrestore(&info->netlock, flags);
1481
1482         /* claim resources and init adapter */
1483         if ((rc = startup(info)) != 0) {
1484                 spin_lock_irqsave(&info->netlock, flags);
1485                 info->netcount=0;
1486                 spin_unlock_irqrestore(&info->netlock, flags);
1487                 return rc;
1488         }
1489
1490         /* assert DTR and RTS, apply hardware settings */
1491         info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1492         program_hw(info);
1493
1494         /* enable network layer transmit */
1495         dev->trans_start = jiffies;
1496         netif_start_queue(dev);
1497
1498         /* inform generic HDLC layer of current DCD status */
1499         spin_lock_irqsave(&info->lock, flags);
1500         get_signals(info);
1501         spin_unlock_irqrestore(&info->lock, flags);
1502         if (info->signals & SerialSignal_DCD)
1503                 netif_carrier_on(dev);
1504         else
1505                 netif_carrier_off(dev);
1506         return 0;
1507 }
1508
1509 /**
1510  * called by network layer when interface is disabled
1511  * shutdown hardware and release resources
1512  *
1513  * dev  pointer to network device structure
1514  *
1515  * returns 0 if success, otherwise error code
1516  */
1517 static int hdlcdev_close(struct net_device *dev)
1518 {
1519         struct slgt_info *info = dev_to_port(dev);
1520         unsigned long flags;
1521
1522         DBGINFO(("%s hdlcdev_close\n", dev->name));
1523
1524         netif_stop_queue(dev);
1525
1526         /* shutdown adapter and release resources */
1527         shutdown(info);
1528
1529         hdlc_close(dev);
1530
1531         spin_lock_irqsave(&info->netlock, flags);
1532         info->netcount=0;
1533         spin_unlock_irqrestore(&info->netlock, flags);
1534
1535         return 0;
1536 }
1537
1538 /**
1539  * called by network layer to process IOCTL call to network device
1540  *
1541  * dev  pointer to network device structure
1542  * ifr  pointer to network interface request structure
1543  * cmd  IOCTL command code
1544  *
1545  * returns 0 if success, otherwise error code
1546  */
1547 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1548 {
1549         const size_t size = sizeof(sync_serial_settings);
1550         sync_serial_settings new_line;
1551         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1552         struct slgt_info *info = dev_to_port(dev);
1553         unsigned int flags;
1554
1555         DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1556
1557         /* return error if TTY interface open */
1558         if (info->count)
1559                 return -EBUSY;
1560
1561         if (cmd != SIOCWANDEV)
1562                 return hdlc_ioctl(dev, ifr, cmd);
1563
1564         switch(ifr->ifr_settings.type) {
1565         case IF_GET_IFACE: /* return current sync_serial_settings */
1566
1567                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1568                 if (ifr->ifr_settings.size < size) {
1569                         ifr->ifr_settings.size = size; /* data size wanted */
1570                         return -ENOBUFS;
1571                 }
1572
1573                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1574                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1575                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1576                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1577
1578                 switch (flags){
1579                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1580                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1581                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1582                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1583                 default: new_line.clock_type = CLOCK_DEFAULT;
1584                 }
1585
1586                 new_line.clock_rate = info->params.clock_speed;
1587                 new_line.loopback   = info->params.loopback ? 1:0;
1588
1589                 if (copy_to_user(line, &new_line, size))
1590                         return -EFAULT;
1591                 return 0;
1592
1593         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1594
1595                 if(!capable(CAP_NET_ADMIN))
1596                         return -EPERM;
1597                 if (copy_from_user(&new_line, line, size))
1598                         return -EFAULT;
1599
1600                 switch (new_line.clock_type)
1601                 {
1602                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1603                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1604                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1605                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1606                 case CLOCK_DEFAULT:  flags = info->params.flags &
1607                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1608                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1609                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1610                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1611                 default: return -EINVAL;
1612                 }
1613
1614                 if (new_line.loopback != 0 && new_line.loopback != 1)
1615                         return -EINVAL;
1616
1617                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1618                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1619                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1620                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1621                 info->params.flags |= flags;
1622
1623                 info->params.loopback = new_line.loopback;
1624
1625                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1626                         info->params.clock_speed = new_line.clock_rate;
1627                 else
1628                         info->params.clock_speed = 0;
1629
1630                 /* if network interface up, reprogram hardware */
1631                 if (info->netcount)
1632                         program_hw(info);
1633                 return 0;
1634
1635         default:
1636                 return hdlc_ioctl(dev, ifr, cmd);
1637         }
1638 }
1639
1640 /**
1641  * called by network layer when transmit timeout is detected
1642  *
1643  * dev  pointer to network device structure
1644  */
1645 static void hdlcdev_tx_timeout(struct net_device *dev)
1646 {
1647         struct slgt_info *info = dev_to_port(dev);
1648         struct net_device_stats *stats = hdlc_stats(dev);
1649         unsigned long flags;
1650
1651         DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1652
1653         stats->tx_errors++;
1654         stats->tx_aborted_errors++;
1655
1656         spin_lock_irqsave(&info->lock,flags);
1657         tx_stop(info);
1658         spin_unlock_irqrestore(&info->lock,flags);
1659
1660         netif_wake_queue(dev);
1661 }
1662
1663 /**
1664  * called by device driver when transmit completes
1665  * reenable network layer transmit if stopped
1666  *
1667  * info  pointer to device instance information
1668  */
1669 static void hdlcdev_tx_done(struct slgt_info *info)
1670 {
1671         if (netif_queue_stopped(info->netdev))
1672                 netif_wake_queue(info->netdev);
1673 }
1674
1675 /**
1676  * called by device driver when frame received
1677  * pass frame to network layer
1678  *
1679  * info  pointer to device instance information
1680  * buf   pointer to buffer contianing frame data
1681  * size  count of data bytes in buf
1682  */
1683 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1684 {
1685         struct sk_buff *skb = dev_alloc_skb(size);
1686         struct net_device *dev = info->netdev;
1687         struct net_device_stats *stats = hdlc_stats(dev);
1688
1689         DBGINFO(("%s hdlcdev_rx\n", dev->name));
1690
1691         if (skb == NULL) {
1692                 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1693                 stats->rx_dropped++;
1694                 return;
1695         }
1696
1697         memcpy(skb_put(skb, size),buf,size);
1698
1699         skb->protocol = hdlc_type_trans(skb, info->netdev);
1700
1701         stats->rx_packets++;
1702         stats->rx_bytes += size;
1703
1704         netif_rx(skb);
1705
1706         info->netdev->last_rx = jiffies;
1707 }
1708
1709 /**
1710  * called by device driver when adding device instance
1711  * do generic HDLC initialization
1712  *
1713  * info  pointer to device instance information
1714  *
1715  * returns 0 if success, otherwise error code
1716  */
1717 static int hdlcdev_init(struct slgt_info *info)
1718 {
1719         int rc;
1720         struct net_device *dev;
1721         hdlc_device *hdlc;
1722
1723         /* allocate and initialize network and HDLC layer objects */
1724
1725         if (!(dev = alloc_hdlcdev(info))) {
1726                 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1727                 return -ENOMEM;
1728         }
1729
1730         /* for network layer reporting purposes only */
1731         dev->mem_start = info->phys_reg_addr;
1732         dev->mem_end   = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1733         dev->irq       = info->irq_level;
1734
1735         /* network layer callbacks and settings */
1736         dev->do_ioctl       = hdlcdev_ioctl;
1737         dev->open           = hdlcdev_open;
1738         dev->stop           = hdlcdev_close;
1739         dev->tx_timeout     = hdlcdev_tx_timeout;
1740         dev->watchdog_timeo = 10*HZ;
1741         dev->tx_queue_len   = 50;
1742
1743         /* generic HDLC layer callbacks and settings */
1744         hdlc         = dev_to_hdlc(dev);
1745         hdlc->attach = hdlcdev_attach;
1746         hdlc->xmit   = hdlcdev_xmit;
1747
1748         /* register objects with HDLC layer */
1749         if ((rc = register_hdlc_device(dev))) {
1750                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1751                 free_netdev(dev);
1752                 return rc;
1753         }
1754
1755         info->netdev = dev;
1756         return 0;
1757 }
1758
1759 /**
1760  * called by device driver when removing device instance
1761  * do generic HDLC cleanup
1762  *
1763  * info  pointer to device instance information
1764  */
1765 static void hdlcdev_exit(struct slgt_info *info)
1766 {
1767         unregister_hdlc_device(info->netdev);
1768         free_netdev(info->netdev);
1769         info->netdev = NULL;
1770 }
1771
1772 #endif /* ifdef CONFIG_HDLC */
1773
1774 /*
1775  * get async data from rx DMA buffers
1776  */
1777 static void rx_async(struct slgt_info *info)
1778 {
1779         struct tty_struct *tty = info->tty;
1780         struct mgsl_icount *icount = &info->icount;
1781         unsigned int start, end;
1782         unsigned char *p;
1783         unsigned char status;
1784         struct slgt_desc *bufs = info->rbufs;
1785         int i, count;
1786         int chars = 0;
1787         int stat;
1788         unsigned char ch;
1789
1790         start = end = info->rbuf_current;
1791
1792         while(desc_complete(bufs[end])) {
1793                 count = desc_count(bufs[end]) - info->rbuf_index;
1794                 p     = bufs[end].buf + info->rbuf_index;
1795
1796                 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1797                 DBGDATA(info, p, count, "rx");
1798
1799                 for(i=0 ; i < count; i+=2, p+=2) {
1800                         ch = *p;
1801                         icount->rx++;
1802
1803                         stat = 0;
1804
1805                         if ((status = *(p+1) & (BIT1 + BIT0))) {
1806                                 if (status & BIT1)
1807                                         icount->parity++;
1808                                 else if (status & BIT0)
1809                                         icount->frame++;
1810                                 /* discard char if tty control flags say so */
1811                                 if (status & info->ignore_status_mask)
1812                                         continue;
1813                                 if (status & BIT1)
1814                                         stat = TTY_PARITY;
1815                                 else if (status & BIT0)
1816                                         stat = TTY_FRAME;
1817                         }
1818                         if (tty) {
1819                                 tty_insert_flip_char(tty, ch, stat);
1820                                 chars++;
1821                         }
1822                 }
1823
1824                 if (i < count) {
1825                         /* receive buffer not completed */
1826                         info->rbuf_index += i;
1827                         info->rx_timer.expires = jiffies + 1;
1828                         add_timer(&info->rx_timer);
1829                         break;
1830                 }
1831
1832                 info->rbuf_index = 0;
1833                 free_rbufs(info, end, end);
1834
1835                 if (++end == info->rbuf_count)
1836                         end = 0;
1837
1838                 /* if entire list searched then no frame available */
1839                 if (end == start)
1840                         break;
1841         }
1842
1843         if (tty && chars)
1844                 tty_flip_buffer_push(tty);
1845 }
1846
1847 /*
1848  * return next bottom half action to perform
1849  */
1850 static int bh_action(struct slgt_info *info)
1851 {
1852         unsigned long flags;
1853         int rc;
1854
1855         spin_lock_irqsave(&info->lock,flags);
1856
1857         if (info->pending_bh & BH_RECEIVE) {
1858                 info->pending_bh &= ~BH_RECEIVE;
1859                 rc = BH_RECEIVE;
1860         } else if (info->pending_bh & BH_TRANSMIT) {
1861                 info->pending_bh &= ~BH_TRANSMIT;
1862                 rc = BH_TRANSMIT;
1863         } else if (info->pending_bh & BH_STATUS) {
1864                 info->pending_bh &= ~BH_STATUS;
1865                 rc = BH_STATUS;
1866         } else {
1867                 /* Mark BH routine as complete */
1868                 info->bh_running   = 0;
1869                 info->bh_requested = 0;
1870                 rc = 0;
1871         }
1872
1873         spin_unlock_irqrestore(&info->lock,flags);
1874
1875         return rc;
1876 }
1877
1878 /*
1879  * perform bottom half processing
1880  */
1881 static void bh_handler(void* context)
1882 {
1883         struct slgt_info *info = context;
1884         int action;
1885
1886         if (!info)
1887                 return;
1888         info->bh_running = 1;
1889
1890         while((action = bh_action(info))) {
1891                 switch (action) {
1892                 case BH_RECEIVE:
1893                         DBGBH(("%s bh receive\n", info->device_name));
1894                         switch(info->params.mode) {
1895                         case MGSL_MODE_ASYNC:
1896                                 rx_async(info);
1897                                 break;
1898                         case MGSL_MODE_HDLC:
1899                                 while(rx_get_frame(info));
1900                                 break;
1901                         case MGSL_MODE_RAW:
1902                         case MGSL_MODE_MONOSYNC:
1903                         case MGSL_MODE_BISYNC:
1904                                 while(rx_get_buf(info));
1905                                 break;
1906                         }
1907                         /* restart receiver if rx DMA buffers exhausted */
1908                         if (info->rx_restart)
1909                                 rx_start(info);
1910                         break;
1911                 case BH_TRANSMIT:
1912                         bh_transmit(info);
1913                         break;
1914                 case BH_STATUS:
1915                         DBGBH(("%s bh status\n", info->device_name));
1916                         info->ri_chkcount = 0;
1917                         info->dsr_chkcount = 0;
1918                         info->dcd_chkcount = 0;
1919                         info->cts_chkcount = 0;
1920                         break;
1921                 default:
1922                         DBGBH(("%s unknown action\n", info->device_name));
1923                         break;
1924                 }
1925         }
1926         DBGBH(("%s bh_handler exit\n", info->device_name));
1927 }
1928
1929 static void bh_transmit(struct slgt_info *info)
1930 {
1931         struct tty_struct *tty = info->tty;
1932
1933         DBGBH(("%s bh_transmit\n", info->device_name));
1934         if (tty) {
1935                 tty_wakeup(tty);
1936                 wake_up_interruptible(&tty->write_wait);
1937         }
1938 }
1939
1940 static void dsr_change(struct slgt_info *info)
1941 {
1942         get_signals(info);
1943         DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
1944         if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1945                 slgt_irq_off(info, IRQ_DSR);
1946                 return;
1947         }
1948         info->icount.dsr++;
1949         if (info->signals & SerialSignal_DSR)
1950                 info->input_signal_events.dsr_up++;
1951         else
1952                 info->input_signal_events.dsr_down++;
1953         wake_up_interruptible(&info->status_event_wait_q);
1954         wake_up_interruptible(&info->event_wait_q);
1955         info->pending_bh |= BH_STATUS;
1956 }
1957
1958 static void cts_change(struct slgt_info *info)
1959 {
1960         get_signals(info);
1961         DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
1962         if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1963                 slgt_irq_off(info, IRQ_CTS);
1964                 return;
1965         }
1966         info->icount.cts++;
1967         if (info->signals & SerialSignal_CTS)
1968                 info->input_signal_events.cts_up++;
1969         else
1970                 info->input_signal_events.cts_down++;
1971         wake_up_interruptible(&info->status_event_wait_q);
1972         wake_up_interruptible(&info->event_wait_q);
1973         info->pending_bh |= BH_STATUS;
1974
1975         if (info->flags & ASYNC_CTS_FLOW) {
1976                 if (info->tty) {
1977                         if (info->tty->hw_stopped) {
1978                                 if (info->signals & SerialSignal_CTS) {
1979                                         info->tty->hw_stopped = 0;
1980                                         info->pending_bh |= BH_TRANSMIT;
1981                                         return;
1982                                 }
1983                         } else {
1984                                 if (!(info->signals & SerialSignal_CTS))
1985                                         info->tty->hw_stopped = 1;
1986                         }
1987                 }
1988         }
1989 }
1990
1991 static void dcd_change(struct slgt_info *info)
1992 {
1993         get_signals(info);
1994         DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
1995         if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1996                 slgt_irq_off(info, IRQ_DCD);
1997                 return;
1998         }
1999         info->icount.dcd++;
2000         if (info->signals & SerialSignal_DCD) {
2001                 info->input_signal_events.dcd_up++;
2002         } else {
2003                 info->input_signal_events.dcd_down++;
2004         }
2005 #ifdef CONFIG_HDLC
2006         if (info->netcount) {
2007                 if (info->signals & SerialSignal_DCD)
2008                         netif_carrier_on(info->netdev);
2009                 else
2010                         netif_carrier_off(info->netdev);
2011         }
2012 #endif
2013         wake_up_interruptible(&info->status_event_wait_q);
2014         wake_up_interruptible(&info->event_wait_q);
2015         info->pending_bh |= BH_STATUS;
2016
2017         if (info->flags & ASYNC_CHECK_CD) {
2018                 if (info->signals & SerialSignal_DCD)
2019                         wake_up_interruptible(&info->open_wait);
2020                 else {
2021                         if (info->tty)
2022                                 tty_hangup(info->tty);
2023                 }
2024         }
2025 }
2026
2027 static void ri_change(struct slgt_info *info)
2028 {
2029         get_signals(info);
2030         DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2031         if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2032                 slgt_irq_off(info, IRQ_RI);
2033                 return;
2034         }
2035         info->icount.dcd++;
2036         if (info->signals & SerialSignal_RI) {
2037                 info->input_signal_events.ri_up++;
2038         } else {
2039                 info->input_signal_events.ri_down++;
2040         }
2041         wake_up_interruptible(&info->status_event_wait_q);
2042         wake_up_interruptible(&info->event_wait_q);
2043         info->pending_bh |= BH_STATUS;
2044 }
2045
2046 static void isr_serial(struct slgt_info *info)
2047 {
2048         unsigned short status = rd_reg16(info, SSR);
2049
2050         DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2051
2052         wr_reg16(info, SSR, status); /* clear pending */
2053
2054         info->irq_occurred = 1;
2055
2056         if (info->params.mode == MGSL_MODE_ASYNC) {
2057                 if (status & IRQ_TXIDLE) {
2058                         if (info->tx_count)
2059                                 isr_txeom(info, status);
2060                 }
2061                 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2062                         info->icount.brk++;
2063                         /* process break detection if tty control allows */
2064                         if (info->tty) {
2065                                 if (!(status & info->ignore_status_mask)) {
2066                                         if (info->read_status_mask & MASK_BREAK) {
2067                                                 tty_insert_flip_char(info->tty, 0, TTY_BREAK);
2068                                                 if (info->flags & ASYNC_SAK)
2069                                                         do_SAK(info->tty);
2070                                         }
2071                                 }
2072                         }
2073                 }
2074         } else {
2075                 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2076                         isr_txeom(info, status);
2077
2078                 if (status & IRQ_RXIDLE) {
2079                         if (status & RXIDLE)
2080                                 info->icount.rxidle++;
2081                         else
2082                                 info->icount.exithunt++;
2083                         wake_up_interruptible(&info->event_wait_q);
2084                 }
2085
2086                 if (status & IRQ_RXOVER)
2087                         rx_start(info);
2088         }
2089
2090         if (status & IRQ_DSR)
2091                 dsr_change(info);
2092         if (status & IRQ_CTS)
2093                 cts_change(info);
2094         if (status & IRQ_DCD)
2095                 dcd_change(info);
2096         if (status & IRQ_RI)
2097                 ri_change(info);
2098 }
2099
2100 static void isr_rdma(struct slgt_info *info)
2101 {
2102         unsigned int status = rd_reg32(info, RDCSR);
2103
2104         DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2105
2106         /* RDCSR (rx DMA control/status)
2107          *
2108          * 31..07  reserved
2109          * 06      save status byte to DMA buffer
2110          * 05      error
2111          * 04      eol (end of list)
2112          * 03      eob (end of buffer)
2113          * 02      IRQ enable
2114          * 01      reset
2115          * 00      enable
2116          */
2117         wr_reg32(info, RDCSR, status);  /* clear pending */
2118
2119         if (status & (BIT5 + BIT4)) {
2120                 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2121                 info->rx_restart = 1;
2122         }
2123         info->pending_bh |= BH_RECEIVE;
2124 }
2125
2126 static void isr_tdma(struct slgt_info *info)
2127 {
2128         unsigned int status = rd_reg32(info, TDCSR);
2129
2130         DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2131
2132         /* TDCSR (tx DMA control/status)
2133          *
2134          * 31..06  reserved
2135          * 05      error
2136          * 04      eol (end of list)
2137          * 03      eob (end of buffer)
2138          * 02      IRQ enable
2139          * 01      reset
2140          * 00      enable
2141          */
2142         wr_reg32(info, TDCSR, status);  /* clear pending */
2143
2144         if (status & (BIT5 + BIT4 + BIT3)) {
2145                 // another transmit buffer has completed
2146                 // run bottom half to get more send data from user
2147                 info->pending_bh |= BH_TRANSMIT;
2148         }
2149 }
2150
2151 static void isr_txeom(struct slgt_info *info, unsigned short status)
2152 {
2153         DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2154
2155         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2156         tdma_reset(info);
2157         reset_tbufs(info);
2158         if (status & IRQ_TXUNDER) {
2159                 unsigned short val = rd_reg16(info, TCR);
2160                 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2161                 wr_reg16(info, TCR, val); /* clear reset bit */
2162         }
2163
2164         if (info->tx_active) {
2165                 if (info->params.mode != MGSL_MODE_ASYNC) {
2166                         if (status & IRQ_TXUNDER)
2167                                 info->icount.txunder++;
2168                         else if (status & IRQ_TXIDLE)
2169                                 info->icount.txok++;
2170                 }
2171
2172                 info->tx_active = 0;
2173                 info->tx_count = 0;
2174
2175                 del_timer(&info->tx_timer);
2176
2177                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2178                         info->signals &= ~SerialSignal_RTS;
2179                         info->drop_rts_on_tx_done = 0;
2180                         set_signals(info);
2181                 }
2182
2183 #ifdef CONFIG_HDLC
2184                 if (info->netcount)
2185                         hdlcdev_tx_done(info);
2186                 else
2187 #endif
2188                 {
2189                         if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2190                                 tx_stop(info);
2191                                 return;
2192                         }
2193                         info->pending_bh |= BH_TRANSMIT;
2194                 }
2195         }
2196 }
2197
2198 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2199 {
2200         struct cond_wait *w, *prev;
2201
2202         /* wake processes waiting for specific transitions */
2203         for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2204                 if (w->data & changed) {
2205                         w->data = state;
2206                         wake_up_interruptible(&w->q);
2207                         if (prev != NULL)
2208                                 prev->next = w->next;
2209                         else
2210                                 info->gpio_wait_q = w->next;
2211                 } else
2212                         prev = w;
2213         }
2214 }
2215
2216 /* interrupt service routine
2217  *
2218  *      irq     interrupt number
2219  *      dev_id  device ID supplied during interrupt registration
2220  */
2221 static irqreturn_t slgt_interrupt(int irq, void *dev_id)
2222 {
2223         struct slgt_info *info;
2224         unsigned int gsr;
2225         unsigned int i;
2226
2227         DBGISR(("slgt_interrupt irq=%d entry\n", irq));
2228
2229         info = dev_id;
2230         if (!info)
2231                 return IRQ_NONE;
2232
2233         spin_lock(&info->lock);
2234
2235         while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2236                 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2237                 info->irq_occurred = 1;
2238                 for(i=0; i < info->port_count ; i++) {
2239                         if (info->port_array[i] == NULL)
2240                                 continue;
2241                         if (gsr & (BIT8 << i))
2242                                 isr_serial(info->port_array[i]);
2243                         if (gsr & (BIT16 << (i*2)))
2244                                 isr_rdma(info->port_array[i]);
2245                         if (gsr & (BIT17 << (i*2)))
2246                                 isr_tdma(info->port_array[i]);
2247                 }
2248         }
2249
2250         if (info->gpio_present) {
2251                 unsigned int state;
2252                 unsigned int changed;
2253                 while ((changed = rd_reg32(info, IOSR)) != 0) {
2254                         DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2255                         /* read latched state of GPIO signals */
2256                         state = rd_reg32(info, IOVR);
2257                         /* clear pending GPIO interrupt bits */
2258                         wr_reg32(info, IOSR, changed);
2259                         for (i=0 ; i < info->port_count ; i++) {
2260                                 if (info->port_array[i] != NULL)
2261                                         isr_gpio(info->port_array[i], changed, state);
2262                         }
2263                 }
2264         }
2265
2266         for(i=0; i < info->port_count ; i++) {
2267                 struct slgt_info *port = info->port_array[i];
2268
2269                 if (port && (port->count || port->netcount) &&
2270                     port->pending_bh && !port->bh_running &&
2271                     !port->bh_requested) {
2272                         DBGISR(("%s bh queued\n", port->device_name));
2273                         schedule_work(&port->task);
2274                         port->bh_requested = 1;
2275                 }
2276         }
2277
2278         spin_unlock(&info->lock);
2279
2280         DBGISR(("slgt_interrupt irq=%d exit\n", irq));
2281         return IRQ_HANDLED;
2282 }
2283
2284 static int startup(struct slgt_info *info)
2285 {
2286         DBGINFO(("%s startup\n", info->device_name));
2287
2288         if (info->flags & ASYNC_INITIALIZED)
2289                 return 0;
2290
2291         if (!info->tx_buf) {
2292                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2293                 if (!info->tx_buf) {
2294                         DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2295                         return -ENOMEM;
2296                 }
2297         }
2298
2299         info->pending_bh = 0;
2300
2301         memset(&info->icount, 0, sizeof(info->icount));
2302
2303         /* program hardware for current parameters */
2304         change_params(info);
2305
2306         if (info->tty)
2307                 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2308
2309         info->flags |= ASYNC_INITIALIZED;
2310
2311         return 0;
2312 }
2313
2314 /*
2315  *  called by close() and hangup() to shutdown hardware
2316  */
2317 static void shutdown(struct slgt_info *info)
2318 {
2319         unsigned long flags;
2320
2321         if (!(info->flags & ASYNC_INITIALIZED))
2322                 return;
2323
2324         DBGINFO(("%s shutdown\n", info->device_name));
2325
2326         /* clear status wait queue because status changes */
2327         /* can't happen after shutting down the hardware */
2328         wake_up_interruptible(&info->status_event_wait_q);
2329         wake_up_interruptible(&info->event_wait_q);
2330
2331         del_timer_sync(&info->tx_timer);
2332         del_timer_sync(&info->rx_timer);
2333
2334         kfree(info->tx_buf);
2335         info->tx_buf = NULL;
2336
2337         spin_lock_irqsave(&info->lock,flags);
2338
2339         tx_stop(info);
2340         rx_stop(info);
2341
2342         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2343
2344         if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
2345                 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2346                 set_signals(info);
2347         }
2348
2349         flush_cond_wait(&info->gpio_wait_q);
2350
2351         spin_unlock_irqrestore(&info->lock,flags);
2352
2353         if (info->tty)
2354                 set_bit(TTY_IO_ERROR, &info->tty->flags);
2355
2356         info->flags &= ~ASYNC_INITIALIZED;
2357 }
2358
2359 static void program_hw(struct slgt_info *info)
2360 {
2361         unsigned long flags;
2362
2363         spin_lock_irqsave(&info->lock,flags);
2364
2365         rx_stop(info);
2366         tx_stop(info);
2367
2368         if (info->params.mode != MGSL_MODE_ASYNC ||
2369             info->netcount)
2370                 sync_mode(info);
2371         else
2372                 async_mode(info);
2373
2374         set_signals(info);
2375
2376         info->dcd_chkcount = 0;
2377         info->cts_chkcount = 0;
2378         info->ri_chkcount = 0;
2379         info->dsr_chkcount = 0;
2380
2381         slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR);
2382         get_signals(info);
2383
2384         if (info->netcount ||
2385             (info->tty && info->tty->termios->c_cflag & CREAD))
2386                 rx_start(info);
2387
2388         spin_unlock_irqrestore(&info->lock,flags);
2389 }
2390
2391 /*
2392  * reconfigure adapter based on new parameters
2393  */
2394 static void change_params(struct slgt_info *info)
2395 {
2396         unsigned cflag;
2397         int bits_per_char;
2398
2399         if (!info->tty || !info->tty->termios)
2400                 return;
2401         DBGINFO(("%s change_params\n", info->device_name));
2402
2403         cflag = info->tty->termios->c_cflag;
2404
2405         /* if B0 rate (hangup) specified then negate DTR and RTS */
2406         /* otherwise assert DTR and RTS */
2407         if (cflag & CBAUD)
2408                 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2409         else
2410                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2411
2412         /* byte size and parity */
2413
2414         switch (cflag & CSIZE) {
2415         case CS5: info->params.data_bits = 5; break;
2416         case CS6: info->params.data_bits = 6; break;
2417         case CS7: info->params.data_bits = 7; break;
2418         case CS8: info->params.data_bits = 8; break;
2419         default:  info->params.data_bits = 7; break;
2420         }
2421
2422         info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2423
2424         if (cflag & PARENB)
2425                 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2426         else
2427                 info->params.parity = ASYNC_PARITY_NONE;
2428
2429         /* calculate number of jiffies to transmit a full
2430          * FIFO (32 bytes) at specified data rate
2431          */
2432         bits_per_char = info->params.data_bits +
2433                         info->params.stop_bits + 1;
2434
2435         info->params.data_rate = tty_get_baud_rate(info->tty);
2436
2437         if (info->params.data_rate) {
2438                 info->timeout = (32*HZ*bits_per_char) /
2439                                 info->params.data_rate;
2440         }
2441         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2442
2443         if (cflag & CRTSCTS)
2444                 info->flags |= ASYNC_CTS_FLOW;
2445         else
2446                 info->flags &= ~ASYNC_CTS_FLOW;
2447
2448         if (cflag & CLOCAL)
2449                 info->flags &= ~ASYNC_CHECK_CD;
2450         else
2451                 info->flags |= ASYNC_CHECK_CD;
2452
2453         /* process tty input control flags */
2454
2455         info->read_status_mask = IRQ_RXOVER;
2456         if (I_INPCK(info->tty))
2457                 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2458         if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2459                 info->read_status_mask |= MASK_BREAK;
2460         if (I_IGNPAR(info->tty))
2461                 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2462         if (I_IGNBRK(info->tty)) {
2463                 info->ignore_status_mask |= MASK_BREAK;
2464                 /* If ignoring parity and break indicators, ignore
2465                  * overruns too.  (For real raw support).
2466                  */
2467                 if (I_IGNPAR(info->tty))
2468                         info->ignore_status_mask |= MASK_OVERRUN;
2469         }
2470
2471         program_hw(info);
2472 }
2473
2474 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2475 {
2476         DBGINFO(("%s get_stats\n",  info->device_name));
2477         if (!user_icount) {
2478                 memset(&info->icount, 0, sizeof(info->icount));
2479         } else {
2480                 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2481                         return -EFAULT;
2482         }
2483         return 0;
2484 }
2485
2486 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2487 {
2488         DBGINFO(("%s get_params\n", info->device_name));
2489         if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2490                 return -EFAULT;
2491         return 0;
2492 }
2493
2494 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2495 {
2496         unsigned long flags;
2497         MGSL_PARAMS tmp_params;
2498
2499         DBGINFO(("%s set_params\n", info->device_name));
2500         if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2501                 return -EFAULT;
2502
2503         spin_lock_irqsave(&info->lock, flags);
2504         memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2505         spin_unlock_irqrestore(&info->lock, flags);
2506
2507         change_params(info);
2508
2509         return 0;
2510 }
2511
2512 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2513 {
2514         DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2515         if (put_user(info->idle_mode, idle_mode))
2516                 return -EFAULT;
2517         return 0;
2518 }
2519
2520 static int set_txidle(struct slgt_info *info, int idle_mode)
2521 {
2522         unsigned long flags;
2523         DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2524         spin_lock_irqsave(&info->lock,flags);
2525         info->idle_mode = idle_mode;
2526         if (info->params.mode != MGSL_MODE_ASYNC)
2527                 tx_set_idle(info);
2528         spin_unlock_irqrestore(&info->lock,flags);
2529         return 0;
2530 }
2531
2532 static int tx_enable(struct slgt_info *info, int enable)
2533 {
2534         unsigned long flags;
2535         DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2536         spin_lock_irqsave(&info->lock,flags);
2537         if (enable) {
2538                 if (!info->tx_enabled)
2539                         tx_start(info);
2540         } else {
2541                 if (info->tx_enabled)
2542                         tx_stop(info);
2543         }
2544         spin_unlock_irqrestore(&info->lock,flags);
2545         return 0;
2546 }
2547
2548 /*
2549  * abort transmit HDLC frame
2550  */
2551 static int tx_abort(struct slgt_info *info)
2552 {
2553         unsigned long flags;
2554         DBGINFO(("%s tx_abort\n", info->device_name));
2555         spin_lock_irqsave(&info->lock,flags);
2556         tdma_reset(info);
2557         spin_unlock_irqrestore(&info->lock,flags);
2558         return 0;
2559 }
2560
2561 static int rx_enable(struct slgt_info *info, int enable)
2562 {
2563         unsigned long flags;
2564         DBGINFO(("%s rx_enable(%d)\n", info->device_name, enable));
2565         spin_lock_irqsave(&info->lock,flags);
2566         if (enable) {
2567                 if (!info->rx_enabled)
2568                         rx_start(info);
2569                 else if (enable == 2) {
2570                         /* force hunt mode (write 1 to RCR[3]) */
2571                         wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2572                 }
2573         } else {
2574                 if (info->rx_enabled)
2575                         rx_stop(info);
2576         }
2577         spin_unlock_irqrestore(&info->lock,flags);
2578         return 0;
2579 }
2580
2581 /*
2582  *  wait for specified event to occur
2583  */
2584 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2585 {
2586         unsigned long flags;
2587         int s;
2588         int rc=0;
2589         struct mgsl_icount cprev, cnow;
2590         int events;
2591         int mask;
2592         struct  _input_signal_events oldsigs, newsigs;
2593         DECLARE_WAITQUEUE(wait, current);
2594
2595         if (get_user(mask, mask_ptr))
2596                 return -EFAULT;
2597
2598         DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2599
2600         spin_lock_irqsave(&info->lock,flags);
2601
2602         /* return immediately if state matches requested events */
2603         get_signals(info);
2604         s = info->signals;
2605
2606         events = mask &
2607                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2608                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2609                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2610                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2611         if (events) {
2612                 spin_unlock_irqrestore(&info->lock,flags);
2613                 goto exit;
2614         }
2615
2616         /* save current irq counts */
2617         cprev = info->icount;
2618         oldsigs = info->input_signal_events;
2619
2620         /* enable hunt and idle irqs if needed */
2621         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2622                 unsigned short val = rd_reg16(info, SCR);
2623                 if (!(val & IRQ_RXIDLE))
2624                         wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2625         }
2626
2627         set_current_state(TASK_INTERRUPTIBLE);
2628         add_wait_queue(&info->event_wait_q, &wait);
2629
2630         spin_unlock_irqrestore(&info->lock,flags);
2631
2632         for(;;) {
2633                 schedule();
2634                 if (signal_pending(current)) {
2635                         rc = -ERESTARTSYS;
2636                         break;
2637                 }
2638
2639                 /* get current irq counts */
2640                 spin_lock_irqsave(&info->lock,flags);
2641                 cnow = info->icount;
2642                 newsigs = info->input_signal_events;
2643                 set_current_state(TASK_INTERRUPTIBLE);
2644                 spin_unlock_irqrestore(&info->lock,flags);
2645
2646                 /* if no change, wait aborted for some reason */
2647                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
2648                     newsigs.dsr_down == oldsigs.dsr_down &&
2649                     newsigs.dcd_up   == oldsigs.dcd_up   &&
2650                     newsigs.dcd_down == oldsigs.dcd_down &&
2651                     newsigs.cts_up   == oldsigs.cts_up   &&
2652                     newsigs.cts_down == oldsigs.cts_down &&
2653                     newsigs.ri_up    == oldsigs.ri_up    &&
2654                     newsigs.ri_down  == oldsigs.ri_down  &&
2655                     cnow.exithunt    == cprev.exithunt   &&
2656                     cnow.rxidle      == cprev.rxidle) {
2657                         rc = -EIO;
2658                         break;
2659                 }
2660
2661                 events = mask &
2662                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
2663                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2664                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
2665                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2666                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
2667                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2668                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
2669                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
2670                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
2671                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
2672                 if (events)
2673                         break;
2674
2675                 cprev = cnow;
2676                 oldsigs = newsigs;
2677         }
2678
2679         remove_wait_queue(&info->event_wait_q, &wait);
2680         set_current_state(TASK_RUNNING);
2681
2682
2683         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2684                 spin_lock_irqsave(&info->lock,flags);
2685                 if (!waitqueue_active(&info->event_wait_q)) {
2686                         /* disable enable exit hunt mode/idle rcvd IRQs */
2687                         wr_reg16(info, SCR,
2688                                 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2689                 }
2690                 spin_unlock_irqrestore(&info->lock,flags);
2691         }
2692 exit:
2693         if (rc == 0)
2694                 rc = put_user(events, mask_ptr);
2695         return rc;
2696 }
2697
2698 static int get_interface(struct slgt_info *info, int __user *if_mode)
2699 {
2700         DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2701         if (put_user(info->if_mode, if_mode))
2702                 return -EFAULT;
2703         return 0;
2704 }
2705
2706 static int set_interface(struct slgt_info *info, int if_mode)
2707 {
2708         unsigned long flags;
2709         unsigned short val;
2710
2711         DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2712         spin_lock_irqsave(&info->lock,flags);
2713         info->if_mode = if_mode;
2714
2715         msc_set_vcr(info);
2716
2717         /* TCR (tx control) 07  1=RTS driver control */
2718         val = rd_reg16(info, TCR);
2719         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2720                 val |= BIT7;
2721         else
2722                 val &= ~BIT7;
2723         wr_reg16(info, TCR, val);
2724
2725         spin_unlock_irqrestore(&info->lock,flags);
2726         return 0;
2727 }
2728
2729 /*
2730  * set general purpose IO pin state and direction
2731  *
2732  * user_gpio fields:
2733  * state   each bit indicates a pin state
2734  * smask   set bit indicates pin state to set
2735  * dir     each bit indicates a pin direction (0=input, 1=output)
2736  * dmask   set bit indicates pin direction to set
2737  */
2738 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2739 {
2740         unsigned long flags;
2741         struct gpio_desc gpio;
2742         __u32 data;
2743
2744         if (!info->gpio_present)
2745                 return -EINVAL;
2746         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2747                 return -EFAULT;
2748         DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2749                  info->device_name, gpio.state, gpio.smask,
2750                  gpio.dir, gpio.dmask));
2751
2752         spin_lock_irqsave(&info->lock,flags);
2753         if (gpio.dmask) {
2754                 data = rd_reg32(info, IODR);
2755                 data |= gpio.dmask & gpio.dir;
2756                 data &= ~(gpio.dmask & ~gpio.dir);
2757                 wr_reg32(info, IODR, data);
2758         }
2759         if (gpio.smask) {
2760                 data = rd_reg32(info, IOVR);
2761                 data |= gpio.smask & gpio.state;
2762                 data &= ~(gpio.smask & ~gpio.state);
2763                 wr_reg32(info, IOVR, data);
2764         }
2765         spin_unlock_irqrestore(&info->lock,flags);
2766
2767         return 0;
2768 }
2769
2770 /*
2771  * get general purpose IO pin state and direction
2772  */
2773 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2774 {
2775         struct gpio_desc gpio;
2776         if (!info->gpio_present)
2777                 return -EINVAL;
2778         gpio.state = rd_reg32(info, IOVR);
2779         gpio.smask = 0xffffffff;
2780         gpio.dir   = rd_reg32(info, IODR);
2781         gpio.dmask = 0xffffffff;
2782         if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2783                 return -EFAULT;
2784         DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2785                  info->device_name, gpio.state, gpio.dir));
2786         return 0;
2787 }
2788
2789 /*
2790  * conditional wait facility
2791  */
2792 static void init_cond_wait(struct cond_wait *w, unsigned int data)
2793 {
2794         init_waitqueue_head(&w->q);
2795         init_waitqueue_entry(&w->wait, current);
2796         w->data = data;
2797 }
2798
2799 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2800 {
2801         set_current_state(TASK_INTERRUPTIBLE);
2802         add_wait_queue(&w->q, &w->wait);
2803         w->next = *head;
2804         *head = w;
2805 }
2806
2807 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2808 {
2809         struct cond_wait *w, *prev;
2810         remove_wait_queue(&cw->q, &cw->wait);
2811         set_current_state(TASK_RUNNING);
2812         for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2813                 if (w == cw) {
2814                         if (prev != NULL)
2815                                 prev->next = w->next;
2816                         else
2817                                 *head = w->next;
2818                         break;
2819                 }
2820         }
2821 }
2822
2823 static void flush_cond_wait(struct cond_wait **head)
2824 {
2825         while (*head != NULL) {
2826                 wake_up_interruptible(&(*head)->q);
2827                 *head = (*head)->next;
2828         }
2829 }
2830
2831 /*
2832  * wait for general purpose I/O pin(s) to enter specified state
2833  *
2834  * user_gpio fields:
2835  * state - bit indicates target pin state
2836  * smask - set bit indicates watched pin
2837  *
2838  * The wait ends when at least one watched pin enters the specified
2839  * state. When 0 (no error) is returned, user_gpio->state is set to the
2840  * state of all GPIO pins when the wait ends.
2841  *
2842  * Note: Each pin may be a dedicated input, dedicated output, or
2843  * configurable input/output. The number and configuration of pins
2844  * varies with the specific adapter model. Only input pins (dedicated
2845  * or configured) can be monitored with this function.
2846  */
2847 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2848 {
2849         unsigned long flags;
2850         int rc = 0;
2851         struct gpio_desc gpio;
2852         struct cond_wait wait;
2853         u32 state;
2854
2855         if (!info->gpio_present)
2856                 return -EINVAL;
2857         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2858                 return -EFAULT;
2859         DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
2860                  info->device_name, gpio.state, gpio.smask));
2861         /* ignore output pins identified by set IODR bit */
2862         if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
2863                 return -EINVAL;
2864         init_cond_wait(&wait, gpio.smask);
2865
2866         spin_lock_irqsave(&info->lock, flags);
2867         /* enable interrupts for watched pins */
2868         wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
2869         /* get current pin states */
2870         state = rd_reg32(info, IOVR);
2871
2872         if (gpio.smask & ~(state ^ gpio.state)) {
2873                 /* already in target state */
2874                 gpio.state = state;
2875         } else {
2876                 /* wait for target state */
2877                 add_cond_wait(&info->gpio_wait_q, &wait);
2878                 spin_unlock_irqrestore(&info->lock, flags);
2879                 schedule();
2880                 if (signal_pending(current))
2881                         rc = -ERESTARTSYS;
2882                 else
2883                         gpio.state = wait.data;
2884                 spin_lock_irqsave(&info->lock, flags);
2885                 remove_cond_wait(&info->gpio_wait_q, &wait);
2886         }
2887
2888         /* disable all GPIO interrupts if no waiting processes */
2889         if (info->gpio_wait_q == NULL)
2890                 wr_reg32(info, IOER, 0);
2891         spin_unlock_irqrestore(&info->lock,flags);
2892
2893         if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2894                 rc = -EFAULT;
2895         return rc;
2896 }
2897
2898 static int modem_input_wait(struct slgt_info *info,int arg)
2899 {
2900         unsigned long flags;
2901         int rc;
2902         struct mgsl_icount cprev, cnow;
2903         DECLARE_WAITQUEUE(wait, current);
2904
2905         /* save current irq counts */
2906         spin_lock_irqsave(&info->lock,flags);
2907         cprev = info->icount;
2908         add_wait_queue(&info->status_event_wait_q, &wait);
2909         set_current_state(TASK_INTERRUPTIBLE);
2910         spin_unlock_irqrestore(&info->lock,flags);
2911
2912         for(;;) {
2913                 schedule();
2914                 if (signal_pending(current)) {
2915                         rc = -ERESTARTSYS;
2916                         break;
2917                 }
2918
2919                 /* get new irq counts */
2920                 spin_lock_irqsave(&info->lock,flags);
2921                 cnow = info->icount;
2922                 set_current_state(TASK_INTERRUPTIBLE);
2923                 spin_unlock_irqrestore(&info->lock,flags);
2924
2925                 /* if no change, wait aborted for some reason */
2926                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2927                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2928                         rc = -EIO;
2929                         break;
2930                 }
2931
2932                 /* check for change in caller specified modem input */
2933                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2934                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2935                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
2936                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2937                         rc = 0;
2938                         break;
2939                 }
2940
2941                 cprev = cnow;
2942         }
2943         remove_wait_queue(&info->status_event_wait_q, &wait);
2944         set_current_state(TASK_RUNNING);
2945         return rc;
2946 }
2947
2948 /*
2949  *  return state of serial control and status signals
2950  */
2951 static int tiocmget(struct tty_struct *tty, struct file *file)
2952 {
2953         struct slgt_info *info = tty->driver_data;
2954         unsigned int result;
2955         unsigned long flags;
2956
2957         spin_lock_irqsave(&info->lock,flags);
2958         get_signals(info);
2959         spin_unlock_irqrestore(&info->lock,flags);
2960
2961         result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2962                 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2963                 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2964                 ((info->signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
2965                 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2966                 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2967
2968         DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
2969         return result;
2970 }
2971
2972 /*
2973  * set modem control signals (DTR/RTS)
2974  *
2975  *      cmd     signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
2976  *              TIOCMSET = set/clear signal values
2977  *      value   bit mask for command
2978  */
2979 static int tiocmset(struct tty_struct *tty, struct file *file,
2980                     unsigned int set, unsigned int clear)
2981 {
2982         struct slgt_info *info = tty->driver_data;
2983         unsigned long flags;
2984
2985         DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
2986
2987         if (set & TIOCM_RTS)
2988                 info->signals |= SerialSignal_RTS;
2989         if (set & TIOCM_DTR)
2990                 info->signals |= SerialSignal_DTR;
2991         if (clear & TIOCM_RTS)
2992                 info->signals &= ~SerialSignal_RTS;
2993         if (clear & TIOCM_DTR)
2994                 info->signals &= ~SerialSignal_DTR;
2995
2996         spin_lock_irqsave(&info->lock,flags);
2997         set_signals(info);
2998         spin_unlock_irqrestore(&info->lock,flags);
2999         return 0;
3000 }
3001
3002 /*
3003  *  block current process until the device is ready to open
3004  */
3005 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3006                            struct slgt_info *info)
3007 {
3008         DECLARE_WAITQUEUE(wait, current);
3009         int             retval;
3010         int             do_clocal = 0, extra_count = 0;
3011         unsigned long   flags;
3012
3013         DBGINFO(("%s block_til_ready\n", tty->driver->name));
3014
3015         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3016                 /* nonblock mode is set or port is not enabled */
3017                 info->flags |= ASYNC_NORMAL_ACTIVE;
3018                 return 0;
3019         }
3020
3021         if (tty->termios->c_cflag & CLOCAL)
3022                 do_clocal = 1;
3023
3024         /* Wait for carrier detect and the line to become
3025          * free (i.e., not in use by the callout).  While we are in
3026          * this loop, info->count is dropped by one, so that
3027          * close() knows when to free things.  We restore it upon
3028          * exit, either normal or abnormal.
3029          */
3030
3031         retval = 0;
3032         add_wait_queue(&info->open_wait, &wait);
3033
3034         spin_lock_irqsave(&info->lock, flags);
3035         if (!tty_hung_up_p(filp)) {
3036                 extra_count = 1;
3037                 info->count--;
3038         }
3039         spin_unlock_irqrestore(&info->lock, flags);
3040         info->blocked_open++;
3041
3042         while (1) {
3043                 if ((tty->termios->c_cflag & CBAUD)) {
3044                         spin_lock_irqsave(&info->lock,flags);
3045                         info->signals |= SerialSignal_RTS + SerialSignal_DTR;
3046                         set_signals(info);
3047                         spin_unlock_irqrestore(&info->lock,flags);
3048                 }
3049
3050                 set_current_state(TASK_INTERRUPTIBLE);
3051
3052                 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3053                         retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3054                                         -EAGAIN : -ERESTARTSYS;
3055                         break;
3056                 }
3057
3058                 spin_lock_irqsave(&info->lock,flags);
3059                 get_signals(info);
3060                 spin_unlock_irqrestore(&info->lock,flags);
3061
3062                 if (!(info->flags & ASYNC_CLOSING) &&
3063                     (do_clocal || (info->signals & SerialSignal_DCD)) ) {
3064                         break;
3065                 }
3066
3067                 if (signal_pending(current)) {
3068                         retval = -ERESTARTSYS;
3069                         break;
3070                 }
3071
3072                 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3073                 schedule();
3074         }
3075
3076         set_current_state(TASK_RUNNING);
3077         remove_wait_queue(&info->open_wait, &wait);
3078
3079         if (extra_count)
3080                 info->count++;
3081         info->blocked_open--;
3082
3083         if (!retval)
3084                 info->flags |= ASYNC_NORMAL_ACTIVE;
3085
3086         DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3087         return retval;
3088 }
3089
3090 static int alloc_tmp_rbuf(struct slgt_info *info)
3091 {
3092         info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3093         if (info->tmp_rbuf == NULL)
3094                 return -ENOMEM;
3095         return 0;
3096 }
3097
3098 static void free_tmp_rbuf(struct slgt_info *info)
3099 {
3100         kfree(info->tmp_rbuf);
3101         info->tmp_rbuf = NULL;
3102 }
3103
3104 /*
3105  * allocate DMA descriptor lists.
3106  */
3107 static int alloc_desc(struct slgt_info *info)
3108 {
3109         unsigned int i;
3110         unsigned int pbufs;
3111
3112         /* allocate memory to hold descriptor lists */
3113         info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3114         if (info->bufs == NULL)
3115                 return -ENOMEM;
3116
3117         memset(info->bufs, 0, DESC_LIST_SIZE);
3118
3119         info->rbufs = (struct slgt_desc*)info->bufs;
3120         info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3121
3122         pbufs = (unsigned int)info->bufs_dma_addr;
3123
3124         /*
3125          * Build circular lists of descriptors
3126          */
3127
3128         for (i=0; i < info->rbuf_count; i++) {
3129                 /* physical address of this descriptor */
3130                 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3131
3132                 /* physical address of next descriptor */
3133                 if (i == info->rbuf_count - 1)
3134                         info->rbufs[i].next = cpu_to_le32(pbufs);
3135                 else
3136                         info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3137                 set_desc_count(info->rbufs[i], DMABUFSIZE);
3138         }
3139
3140         for (i=0; i < info->tbuf_count; i++) {
3141                 /* physical address of this descriptor */
3142                 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3143
3144                 /* physical address of next descriptor */
3145                 if (i == info->tbuf_count - 1)
3146                         info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3147                 else
3148                         info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3149         }
3150
3151         return 0;
3152 }
3153
3154 static void free_desc(struct slgt_info *info)
3155 {
3156         if (info->bufs != NULL) {
3157                 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3158                 info->bufs  = NULL;
3159                 info->rbufs = NULL;
3160                 info->tbufs = NULL;
3161         }
3162 }
3163
3164 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3165 {
3166         int i;
3167         for (i=0; i < count; i++) {
3168                 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3169                         return -ENOMEM;
3170                 bufs[i].pbuf  = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3171         }
3172         return 0;
3173 }
3174
3175 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3176 {
3177         int i;
3178         for (i=0; i < count; i++) {
3179                 if (bufs[i].buf == NULL)
3180                         continue;
3181                 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3182                 bufs[i].buf = NULL;
3183         }
3184 }
3185
3186 static int alloc_dma_bufs(struct slgt_info *info)
3187 {
3188         info->rbuf_count = 32;
3189         info->tbuf_count = 32;
3190
3191         if (alloc_desc(info) < 0 ||
3192             alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3193             alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3194             alloc_tmp_rbuf(info) < 0) {
3195                 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3196                 return -ENOMEM;
3197         }
3198         reset_rbufs(info);
3199         return 0;
3200 }
3201
3202 static void free_dma_bufs(struct slgt_info *info)
3203 {
3204         if (info->bufs) {
3205                 free_bufs(info, info->rbufs, info->rbuf_count);
3206                 free_bufs(info, info->tbufs, info->tbuf_count);
3207                 free_desc(info);
3208         }
3209         free_tmp_rbuf(info);
3210 }
3211
3212 static int claim_resources(struct slgt_info *info)
3213 {
3214         if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3215                 DBGERR(("%s reg addr conflict, addr=%08X\n",
3216                         info->device_name, info->phys_reg_addr));
3217                 info->init_error = DiagStatus_AddressConflict;
3218                 goto errout;
3219         }
3220         else
3221                 info->reg_addr_requested = 1;
3222
3223         info->reg_addr = ioremap(info->phys_reg_addr, SLGT_REG_SIZE);
3224         if (!info->reg_addr) {
3225                 DBGERR(("%s cant map device registers, addr=%08X\n",
3226                         info->device_name, info->phys_reg_addr));
3227                 info->init_error = DiagStatus_CantAssignPciResources;
3228                 goto errout;
3229         }
3230         return 0;
3231
3232 errout:
3233         release_resources(info);
3234         return -ENODEV;
3235 }
3236
3237 static void release_resources(struct slgt_info *info)
3238 {
3239         if (info->irq_requested) {
3240                 free_irq(info->irq_level, info);
3241                 info->irq_requested = 0;
3242         }
3243
3244         if (info->reg_addr_requested) {
3245                 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3246                 info->reg_addr_requested = 0;
3247         }
3248
3249         if (info->reg_addr) {
3250                 iounmap(info->reg_addr);
3251                 info->reg_addr = NULL;
3252         }
3253 }
3254
3255 /* Add the specified device instance data structure to the
3256  * global linked list of devices and increment the device count.
3257  */
3258 static void add_device(struct slgt_info *info)
3259 {
3260         char *devstr;
3261
3262         info->next_device = NULL;
3263         info->line = slgt_device_count;
3264         sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3265
3266         if (info->line < MAX_DEVICES) {
3267                 if (maxframe[info->line])
3268                         info->max_frame_size = maxframe[info->line];
3269                 info->dosyncppp = dosyncppp[info->line];
3270         }
3271
3272         slgt_device_count++;
3273
3274         if (!slgt_device_list)
3275                 slgt_device_list = info;
3276         else {
3277                 struct slgt_info *current_dev = slgt_device_list;
3278                 while(current_dev->next_device)
3279                         current_dev = current_dev->next_device;
3280                 current_dev->next_device = info;
3281         }
3282
3283         if (info->max_frame_size < 4096)
3284                 info->max_frame_size = 4096;
3285         else if (info->max_frame_size > 65535)
3286                 info->max_frame_size = 65535;
3287
3288         switch(info->pdev->device) {
3289         case SYNCLINK_GT_DEVICE_ID:
3290                 devstr = "GT";
3291                 break;
3292         case SYNCLINK_GT2_DEVICE_ID:
3293                 devstr = "GT2";
3294                 break;
3295         case SYNCLINK_GT4_DEVICE_ID:
3296                 devstr = "GT4";
3297                 break;
3298         case SYNCLINK_AC_DEVICE_ID:
3299                 devstr = "AC";
3300                 info->params.mode = MGSL_MODE_ASYNC;
3301                 break;
3302         default:
3303                 devstr = "(unknown model)";
3304         }
3305         printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3306                 devstr, info->device_name, info->phys_reg_addr,
3307                 info->irq_level, info->max_frame_size);
3308
3309 #ifdef CONFIG_HDLC
3310         hdlcdev_init(info);
3311 #endif
3312 }
3313
3314 /*
3315  *  allocate device instance structure, return NULL on failure
3316  */
3317 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3318 {
3319         struct slgt_info *info;
3320
3321         info = kmalloc(sizeof(struct slgt_info), GFP_KERNEL);
3322
3323         if (!info) {
3324                 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3325                         driver_name, adapter_num, port_num));
3326         } else {
3327                 memset(info, 0, sizeof(struct slgt_info));
3328                 info->magic = MGSL_MAGIC;
3329                 INIT_WORK(&info->task, bh_handler, info);
3330                 info->max_frame_size = 4096;
3331                 info->raw_rx_size = DMABUFSIZE;
3332                 info->close_delay = 5*HZ/10;
3333                 info->closing_wait = 30*HZ;
3334                 init_waitqueue_head(&info->open_wait);
3335                 init_waitqueue_head(&info->close_wait);
3336                 init_waitqueue_head(&info->status_event_wait_q);
3337                 init_waitqueue_head(&info->event_wait_q);
3338                 spin_lock_init(&info->netlock);
3339                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3340                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3341                 info->adapter_num = adapter_num;
3342                 info->port_num = port_num;
3343
3344                 init_timer(&info->tx_timer);
3345                 info->tx_timer.data = (unsigned long)info;
3346                 info->tx_timer.function = tx_timeout;
3347
3348                 init_timer(&info->rx_timer);
3349                 info->rx_timer.data = (unsigned long)info;
3350                 info->rx_timer.function = rx_timeout;
3351
3352                 /* Copy configuration info to device instance data */
3353                 info->pdev = pdev;
3354                 info->irq_level = pdev->irq;
3355                 info->phys_reg_addr = pci_resource_start(pdev,0);
3356
3357                 info->bus_type = MGSL_BUS_TYPE_PCI;
3358                 info->irq_flags = IRQF_SHARED;
3359
3360                 info->init_error = -1; /* assume error, set to 0 on successful init */
3361         }
3362
3363         return info;
3364 }
3365
3366 static void device_init(int adapter_num, struct pci_dev *pdev)
3367 {
3368         struct slgt_info *port_array[SLGT_MAX_PORTS];
3369         int i;
3370         int port_count = 1;
3371
3372         if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3373                 port_count = 2;
3374         else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3375                 port_count = 4;
3376
3377         /* allocate device instances for all ports */
3378         for (i=0; i < port_count; ++i) {
3379                 port_array[i] = alloc_dev(adapter_num, i, pdev);
3380                 if (port_array[i] == NULL) {
3381                         for (--i; i >= 0; --i)
3382                                 kfree(port_array[i]);
3383                         return;
3384                 }
3385         }
3386
3387         /* give copy of port_array to all ports and add to device list  */
3388         for (i=0; i < port_count; ++i) {
3389                 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3390                 add_device(port_array[i]);
3391                 port_array[i]->port_count = port_count;
3392                 spin_lock_init(&port_array[i]->lock);
3393         }
3394
3395         /* Allocate and claim adapter resources */
3396         if (!claim_resources(port_array[0])) {
3397
3398                 alloc_dma_bufs(port_array[0]);
3399
3400                 /* copy resource information from first port to others */
3401                 for (i = 1; i < port_count; ++i) {
3402                         port_array[i]->lock      = port_array[0]->lock;
3403                         port_array[i]->irq_level = port_array[0]->irq_level;
3404                         port_array[i]->reg_addr  = port_array[0]->reg_addr;
3405                         alloc_dma_bufs(port_array[i]);
3406                 }
3407
3408                 if (request_irq(port_array[0]->irq_level,
3409                                         slgt_interrupt,
3410                                         port_array[0]->irq_flags,
3411                                         port_array[0]->device_name,
3412                                         port_array[0]) < 0) {
3413                         DBGERR(("%s request_irq failed IRQ=%d\n",
3414                                 port_array[0]->device_name,
3415                                 port_array[0]->irq_level));
3416                 } else {
3417                         port_array[0]->irq_requested = 1;
3418                         adapter_test(port_array[0]);
3419                         for (i=1 ; i < port_count ; i++) {
3420                                 port_array[i]->init_error = port_array[0]->init_error;
3421                                 port_array[i]->gpio_present = port_array[0]->gpio_present;
3422                         }
3423                 }
3424         }
3425 }
3426
3427 static int __devinit init_one(struct pci_dev *dev,
3428                               const struct pci_device_id *ent)
3429 {
3430         if (pci_enable_device(dev)) {
3431                 printk("error enabling pci device %p\n", dev);
3432                 return -EIO;
3433         }
3434         pci_set_master(dev);
3435         device_init(slgt_device_count, dev);
3436         return 0;
3437 }
3438
3439 static void __devexit remove_one(struct pci_dev *dev)
3440 {
3441 }
3442
3443 static const struct tty_operations ops = {
3444         .open = open,
3445         .close = close,
3446         .write = write,
3447         .put_char = put_char,
3448         .flush_chars = flush_chars,
3449         .write_room = write_room,
3450         .chars_in_buffer = chars_in_buffer,
3451         .flush_buffer = flush_buffer,
3452         .ioctl = ioctl,
3453         .throttle = throttle,
3454         .unthrottle = unthrottle,
3455         .send_xchar = send_xchar,
3456         .break_ctl = set_break,
3457         .wait_until_sent = wait_until_sent,
3458         .read_proc = read_proc,
3459         .set_termios = set_termios,
3460         .stop = tx_hold,
3461         .start = tx_release,
3462         .hangup = hangup,
3463         .tiocmget = tiocmget,
3464         .tiocmset = tiocmset,
3465 };
3466
3467 static void slgt_cleanup(void)
3468 {
3469         int rc;
3470         struct slgt_info *info;
3471         struct slgt_info *tmp;
3472
3473         printk("unload %s %s\n", driver_name, driver_version);
3474
3475         if (serial_driver) {
3476                 if ((rc = tty_unregister_driver(serial_driver)))
3477                         DBGERR(("tty_unregister_driver error=%d\n", rc));
3478                 put_tty_driver(serial_driver);
3479         }
3480
3481         /* reset devices */
3482         info = slgt_device_list;
3483         while(info) {
3484                 reset_port(info);
3485                 info = info->next_device;
3486         }
3487
3488         /* release devices */
3489         info = slgt_device_list;
3490         while(info) {
3491 #ifdef CONFIG_HDLC
3492                 hdlcdev_exit(info);
3493 #endif
3494                 free_dma_bufs(info);
3495                 free_tmp_rbuf(info);
3496                 if (info->port_num == 0)
3497                         release_resources(info);
3498                 tmp = info;
3499                 info = info->next_device;
3500                 kfree(tmp);
3501         }
3502
3503         if (pci_registered)
3504                 pci_unregister_driver(&pci_driver);
3505 }
3506
3507 /*
3508  *  Driver initialization entry point.
3509  */
3510 static int __init slgt_init(void)
3511 {
3512         int rc;
3513
3514         printk("%s %s\n", driver_name, driver_version);
3515
3516         slgt_device_count = 0;
3517         if ((rc = pci_register_driver(&pci_driver)) < 0) {
3518                 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3519                 return rc;
3520         }
3521         pci_registered = 1;
3522
3523         if (!slgt_device_list) {
3524                 printk("%s no devices found\n",driver_name);
3525                 return -ENODEV;
3526         }
3527
3528         serial_driver = alloc_tty_driver(MAX_DEVICES);
3529         if (!serial_driver) {
3530                 rc = -ENOMEM;
3531                 goto error;
3532         }
3533
3534         /* Initialize the tty_driver structure */
3535
3536         serial_driver->owner = THIS_MODULE;
3537         serial_driver->driver_name = tty_driver_name;
3538         serial_driver->name = tty_dev_prefix;
3539         serial_driver->major = ttymajor;
3540         serial_driver->minor_start = 64;
3541         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3542         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3543         serial_driver->init_termios = tty_std_termios;
3544         serial_driver->init_termios.c_cflag =
3545                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3546         serial_driver->flags = TTY_DRIVER_REAL_RAW;
3547         tty_set_operations(serial_driver, &ops);
3548         if ((rc = tty_register_driver(serial_driver)) < 0) {
3549                 DBGERR(("%s can't register serial driver\n", driver_name));
3550                 put_tty_driver(serial_driver);
3551                 serial_driver = NULL;
3552                 goto error;
3553         }
3554
3555         printk("%s %s, tty major#%d\n",
3556                 driver_name, driver_version,
3557                 serial_driver->major);
3558
3559         return 0;
3560
3561 error:
3562         slgt_cleanup();
3563         return rc;
3564 }
3565
3566 static void __exit slgt_exit(void)
3567 {
3568         slgt_cleanup();
3569 }
3570
3571 module_init(slgt_init);
3572 module_exit(slgt_exit);
3573
3574 /*
3575  * register access routines
3576  */
3577
3578 #define CALC_REGADDR() \
3579         unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3580         if (addr >= 0x80) \
3581                 reg_addr += (info->port_num) * 32;
3582
3583 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3584 {
3585         CALC_REGADDR();
3586         return readb((void __iomem *)reg_addr);
3587 }
3588
3589 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3590 {
3591         CALC_REGADDR();
3592         writeb(value, (void __iomem *)reg_addr);
3593 }
3594
3595 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3596 {
3597         CALC_REGADDR();
3598         return readw((void __iomem *)reg_addr);
3599 }
3600
3601 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3602 {
3603         CALC_REGADDR();
3604         writew(value, (void __iomem *)reg_addr);
3605 }
3606
3607 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3608 {
3609         CALC_REGADDR();
3610         return readl((void __iomem *)reg_addr);
3611 }
3612
3613 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3614 {
3615         CALC_REGADDR();
3616         writel(value, (void __iomem *)reg_addr);
3617 }
3618
3619 static void rdma_reset(struct slgt_info *info)
3620 {
3621         unsigned int i;
3622
3623         /* set reset bit */
3624         wr_reg32(info, RDCSR, BIT1);
3625
3626         /* wait for enable bit cleared */
3627         for(i=0 ; i < 1000 ; i++)
3628                 if (!(rd_reg32(info, RDCSR) & BIT0))
3629                         break;
3630 }
3631
3632 static void tdma_reset(struct slgt_info *info)
3633 {
3634         unsigned int i;
3635
3636         /* set reset bit */
3637         wr_reg32(info, TDCSR, BIT1);
3638
3639         /* wait for enable bit cleared */
3640         for(i=0 ; i < 1000 ; i++)
3641                 if (!(rd_reg32(info, TDCSR) & BIT0))
3642                         break;
3643 }
3644
3645 /*
3646  * enable internal loopback
3647  * TxCLK and RxCLK are generated from BRG
3648  * and TxD is looped back to RxD internally.
3649  */
3650 static void enable_loopback(struct slgt_info *info)
3651 {
3652         /* SCR (serial control) BIT2=looopback enable */
3653         wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3654
3655         if (info->params.mode != MGSL_MODE_ASYNC) {
3656                 /* CCR (clock control)
3657                  * 07..05  tx clock source (010 = BRG)
3658                  * 04..02  rx clock source (010 = BRG)
3659                  * 01      auxclk enable   (0 = disable)
3660                  * 00      BRG enable      (1 = enable)
3661                  *
3662                  * 0100 1001
3663                  */
3664                 wr_reg8(info, CCR, 0x49);
3665
3666                 /* set speed if available, otherwise use default */
3667                 if (info->params.clock_speed)
3668                         set_rate(info, info->params.clock_speed);
3669                 else
3670                         set_rate(info, 3686400);
3671         }
3672 }
3673
3674 /*
3675  *  set baud rate generator to specified rate
3676  */
3677 static void set_rate(struct slgt_info *info, u32 rate)
3678 {
3679         unsigned int div;
3680         static unsigned int osc = 14745600;
3681
3682         /* div = osc/rate - 1
3683          *
3684          * Round div up if osc/rate is not integer to
3685          * force to next slowest rate.
3686          */
3687
3688         if (rate) {
3689                 div = osc/rate;
3690                 if (!(osc % rate) && div)
3691                         div--;
3692                 wr_reg16(info, BDR, (unsigned short)div);
3693         }
3694 }
3695
3696 static void rx_stop(struct slgt_info *info)
3697 {
3698         unsigned short val;
3699
3700         /* disable and reset receiver */
3701         val = rd_reg16(info, RCR) & ~BIT1;          /* clear enable bit */
3702         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3703         wr_reg16(info, RCR, val);                  /* clear reset bit */
3704
3705         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3706
3707         /* clear pending rx interrupts */
3708         wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3709
3710         rdma_reset(info);
3711
3712         info->rx_enabled = 0;
3713         info->rx_restart = 0;
3714 }
3715
3716 static void rx_start(struct slgt_info *info)
3717 {
3718         unsigned short val;
3719
3720         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3721
3722         /* clear pending rx overrun IRQ */
3723         wr_reg16(info, SSR, IRQ_RXOVER);
3724
3725         /* reset and disable receiver */
3726         val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3727         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3728         wr_reg16(info, RCR, val);                  /* clear reset bit */
3729
3730         rdma_reset(info);
3731         reset_rbufs(info);
3732
3733         /* set 1st descriptor address */
3734         wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3735
3736         if (info->params.mode != MGSL_MODE_ASYNC) {
3737                 /* enable rx DMA and DMA interrupt */
3738                 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3739         } else {
3740                 /* enable saving of rx status, rx DMA and DMA interrupt */
3741                 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3742         }
3743
3744         slgt_irq_on(info, IRQ_RXOVER);
3745
3746         /* enable receiver */
3747         wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3748
3749         info->rx_restart = 0;
3750         info->rx_enabled = 1;
3751 }
3752
3753 static void tx_start(struct slgt_info *info)
3754 {
3755         if (!info->tx_enabled) {
3756                 wr_reg16(info, TCR,
3757                          (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3758                 info->tx_enabled = TRUE;
3759         }
3760
3761         if (info->tx_count) {
3762                 info->drop_rts_on_tx_done = 0;
3763
3764                 if (info->params.mode != MGSL_MODE_ASYNC) {
3765                         if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3766                                 get_signals(info);
3767                                 if (!(info->signals & SerialSignal_RTS)) {
3768                                         info->signals |= SerialSignal_RTS;
3769                                         set_signals(info);
3770                                         info->drop_rts_on_tx_done = 1;
3771                                 }
3772                         }
3773
3774                         slgt_irq_off(info, IRQ_TXDATA);
3775                         slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3776                         /* clear tx idle and underrun status bits */
3777                         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3778
3779                         if (!(rd_reg32(info, TDCSR) & BIT0)) {
3780                                 /* tx DMA stopped, restart tx DMA */
3781                                 tdma_reset(info);
3782                                 /* set 1st descriptor address */
3783                                 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3784                                 switch(info->params.mode) {
3785                                 case MGSL_MODE_RAW:
3786                                 case MGSL_MODE_MONOSYNC:
3787                                 case MGSL_MODE_BISYNC:
3788                                         wr_reg32(info, TDCSR, BIT2 + BIT0); /* IRQ + DMA enable */
3789                                         break;
3790                                 default:
3791                                         wr_reg32(info, TDCSR, BIT0); /* DMA enable */
3792                                 }
3793                         }
3794
3795                         if (info->params.mode == MGSL_MODE_HDLC) {
3796                                 info->tx_timer.expires = jiffies + msecs_to_jiffies(5000);
3797                                 add_timer(&info->tx_timer);
3798                         }
3799                 } else {
3800                         tdma_reset(info);
3801                         /* set 1st descriptor address */
3802                         wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3803
3804                         slgt_irq_off(info, IRQ_TXDATA);
3805                         slgt_irq_on(info, IRQ_TXIDLE);
3806                         /* clear tx idle status bit */
3807                         wr_reg16(info, SSR, IRQ_TXIDLE);
3808
3809                         /* enable tx DMA */
3810                         wr_reg32(info, TDCSR, BIT0);
3811                 }
3812
3813                 info->tx_active = 1;
3814         }
3815 }
3816
3817 static void tx_stop(struct slgt_info *info)
3818 {
3819         unsigned short val;
3820
3821         del_timer(&info->tx_timer);
3822
3823         tdma_reset(info);
3824
3825         /* reset and disable transmitter */
3826         val = rd_reg16(info, TCR) & ~BIT1;          /* clear enable bit */
3827         wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3828
3829         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3830
3831         /* clear tx idle and underrun status bit */
3832         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3833
3834         reset_tbufs(info);
3835
3836         info->tx_enabled = 0;
3837         info->tx_active  = 0;
3838 }
3839
3840 static void reset_port(struct slgt_info *info)
3841 {
3842         if (!info->reg_addr)
3843                 return;
3844
3845         tx_stop(info);
3846         rx_stop(info);
3847
3848         info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
3849         set_signals(info);
3850
3851         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3852 }
3853
3854 static void reset_adapter(struct slgt_info *info)
3855 {
3856         int i;
3857         for (i=0; i < info->port_count; ++i) {
3858                 if (info->port_array[i])
3859                         reset_port(info->port_array[i]);
3860         }
3861 }
3862
3863 static void async_mode(struct slgt_info *info)
3864 {
3865         unsigned short val;
3866
3867         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3868         tx_stop(info);
3869         rx_stop(info);
3870
3871         /* TCR (tx control)
3872          *
3873          * 15..13  mode, 010=async
3874          * 12..10  encoding, 000=NRZ
3875          * 09      parity enable
3876          * 08      1=odd parity, 0=even parity
3877          * 07      1=RTS driver control
3878          * 06      1=break enable
3879          * 05..04  character length
3880          *         00=5 bits
3881          *         01=6 bits
3882          *         10=7 bits
3883          *         11=8 bits
3884          * 03      0=1 stop bit, 1=2 stop bits
3885          * 02      reset
3886          * 01      enable
3887          * 00      auto-CTS enable
3888          */
3889         val = 0x4000;
3890
3891         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
3892                 val |= BIT7;
3893
3894         if (info->params.parity != ASYNC_PARITY_NONE) {
3895                 val |= BIT9;
3896                 if (info->params.parity == ASYNC_PARITY_ODD)
3897                         val |= BIT8;
3898         }
3899
3900         switch (info->params.data_bits)
3901         {
3902         case 6: val |= BIT4; break;
3903         case 7: val |= BIT5; break;
3904         case 8: val |= BIT5 + BIT4; break;
3905         }
3906
3907         if (info->params.stop_bits != 1)
3908                 val |= BIT3;
3909
3910         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
3911                 val |= BIT0;
3912
3913         wr_reg16(info, TCR, val);
3914
3915         /* RCR (rx control)
3916          *
3917          * 15..13  mode, 010=async
3918          * 12..10  encoding, 000=NRZ
3919          * 09      parity enable
3920          * 08      1=odd parity, 0=even parity
3921          * 07..06  reserved, must be 0
3922          * 05..04  character length
3923          *         00=5 bits
3924          *         01=6 bits
3925          *         10=7 bits
3926          *         11=8 bits
3927          * 03      reserved, must be zero
3928          * 02      reset
3929          * 01      enable
3930          * 00      auto-DCD enable
3931          */
3932         val = 0x4000;
3933
3934         if (info->params.parity != ASYNC_PARITY_NONE) {
3935                 val |= BIT9;
3936                 if (info->params.parity == ASYNC_PARITY_ODD)
3937                         val |= BIT8;
3938         }
3939
3940         switch (info->params.data_bits)
3941         {
3942         case 6: val |= BIT4; break;
3943         case 7: val |= BIT5; break;
3944         case 8: val |= BIT5 + BIT4; break;
3945         }
3946
3947         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
3948                 val |= BIT0;
3949
3950         wr_reg16(info, RCR, val);
3951
3952         /* CCR (clock control)
3953          *
3954          * 07..05  011 = tx clock source is BRG/16
3955          * 04..02  010 = rx clock source is BRG
3956          * 01      0 = auxclk disabled
3957          * 00      1 = BRG enabled
3958          *
3959          * 0110 1001
3960          */
3961         wr_reg8(info, CCR, 0x69);
3962
3963         msc_set_vcr(info);
3964
3965         /* SCR (serial control)
3966          *
3967          * 15  1=tx req on FIFO half empty
3968          * 14  1=rx req on FIFO half full
3969          * 13  tx data  IRQ enable
3970          * 12  tx idle  IRQ enable
3971          * 11  rx break on IRQ enable
3972          * 10  rx data  IRQ enable
3973          * 09  rx break off IRQ enable
3974          * 08  overrun  IRQ enable
3975          * 07  DSR      IRQ enable
3976          * 06  CTS      IRQ enable
3977          * 05  DCD      IRQ enable
3978          * 04  RI       IRQ enable
3979          * 03  reserved, must be zero
3980          * 02  1=txd->rxd internal loopback enable
3981          * 01  reserved, must be zero
3982          * 00  1=master IRQ enable
3983          */
3984         val = BIT15 + BIT14 + BIT0;
3985         wr_reg16(info, SCR, val);
3986
3987         slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
3988
3989         set_rate(info, info->params.data_rate * 16);
3990
3991         if (info->params.loopback)
3992                 enable_loopback(info);
3993 }
3994
3995 static void sync_mode(struct slgt_info *info)
3996 {
3997         unsigned short val;
3998
3999         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4000         tx_stop(info);
4001         rx_stop(info);
4002
4003         /* TCR (tx control)
4004          *
4005          * 15..13  mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4006          * 12..10  encoding
4007          * 09      CRC enable
4008          * 08      CRC32
4009          * 07      1=RTS driver control
4010          * 06      preamble enable
4011          * 05..04  preamble length
4012          * 03      share open/close flag
4013          * 02      reset
4014          * 01      enable
4015          * 00      auto-CTS enable
4016          */
4017         val = 0;
4018
4019         switch(info->params.mode) {
4020         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4021         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4022         case MGSL_MODE_RAW:      val |= BIT13; break;
4023         }
4024         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4025                 val |= BIT7;
4026
4027         switch(info->params.encoding)
4028         {
4029         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4030         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4031         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4032         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4033         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4034         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4035         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4036         }
4037
4038         switch (info->params.crc_type & HDLC_CRC_MASK)
4039         {
4040         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4041         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4042         }
4043
4044         if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4045                 val |= BIT6;
4046
4047         switch (info->params.preamble_length)
4048         {
4049         case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4050         case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4051         case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4052         }
4053
4054         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4055                 val |= BIT0;
4056
4057         wr_reg16(info, TCR, val);
4058
4059         /* TPR (transmit preamble) */
4060
4061         switch (info->params.preamble)
4062         {
4063         case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4064         case HDLC_PREAMBLE_PATTERN_ONES:  val = 0xff; break;
4065         case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4066         case HDLC_PREAMBLE_PATTERN_10:    val = 0x55; break;
4067         case HDLC_PREAMBLE_PATTERN_01:    val = 0xaa; break;
4068         default:                          val = 0x7e; break;
4069         }
4070         wr_reg8(info, TPR, (unsigned char)val);
4071
4072         /* RCR (rx control)
4073          *
4074          * 15..13  mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4075          * 12..10  encoding
4076          * 09      CRC enable
4077          * 08      CRC32
4078          * 07..03  reserved, must be 0
4079          * 02      reset
4080          * 01      enable
4081          * 00      auto-DCD enable
4082          */
4083         val = 0;
4084
4085         switch(info->params.mode) {
4086         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4087         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4088         case MGSL_MODE_RAW:      val |= BIT13; break;
4089         }
4090
4091         switch(info->params.encoding)
4092         {
4093         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4094         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4095         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4096         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4097         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4098         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4099         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4100         }
4101
4102         switch (info->params.crc_type & HDLC_CRC_MASK)
4103         {
4104         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4105         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4106         }
4107
4108         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4109                 val |= BIT0;
4110
4111         wr_reg16(info, RCR, val);
4112
4113         /* CCR (clock control)
4114          *
4115          * 07..05  tx clock source
4116          * 04..02  rx clock source
4117          * 01      auxclk enable
4118          * 00      BRG enable
4119          */
4120         val = 0;
4121
4122         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4123         {
4124                 // when RxC source is DPLL, BRG generates 16X DPLL
4125                 // reference clock, so take TxC from BRG/16 to get
4126                 // transmit clock at actual data rate
4127                 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4128                         val |= BIT6 + BIT5;     /* 011, txclk = BRG/16 */
4129                 else
4130                         val |= BIT6;    /* 010, txclk = BRG */
4131         }
4132         else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4133                 val |= BIT7;    /* 100, txclk = DPLL Input */
4134         else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4135                 val |= BIT5;    /* 001, txclk = RXC Input */
4136
4137         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4138                 val |= BIT3;    /* 010, rxclk = BRG */
4139         else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4140                 val |= BIT4;    /* 100, rxclk = DPLL */
4141         else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4142                 val |= BIT2;    /* 001, rxclk = TXC Input */
4143
4144         if (info->params.clock_speed)
4145                 val |= BIT1 + BIT0;
4146
4147         wr_reg8(info, CCR, (unsigned char)val);
4148
4149         if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4150         {
4151                 // program DPLL mode
4152                 switch(info->params.encoding)
4153                 {
4154                 case HDLC_ENCODING_BIPHASE_MARK:
4155                 case HDLC_ENCODING_BIPHASE_SPACE:
4156                         val = BIT7; break;
4157                 case HDLC_ENCODING_BIPHASE_LEVEL:
4158                 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4159                         val = BIT7 + BIT6; break;
4160                 default: val = BIT6;    // NRZ encodings
4161                 }
4162                 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4163
4164                 // DPLL requires a 16X reference clock from BRG
4165                 set_rate(info, info->params.clock_speed * 16);
4166         }
4167         else
4168                 set_rate(info, info->params.clock_speed);
4169
4170         tx_set_idle(info);
4171
4172         msc_set_vcr(info);
4173
4174         /* SCR (serial control)
4175          *
4176          * 15  1=tx req on FIFO half empty
4177          * 14  1=rx req on FIFO half full
4178          * 13  tx data  IRQ enable
4179          * 12  tx idle  IRQ enable
4180          * 11  underrun IRQ enable
4181          * 10  rx data  IRQ enable
4182          * 09  rx idle  IRQ enable
4183          * 08  overrun  IRQ enable
4184          * 07  DSR      IRQ enable
4185          * 06  CTS      IRQ enable
4186          * 05  DCD      IRQ enable
4187          * 04  RI       IRQ enable
4188          * 03  reserved, must be zero
4189          * 02  1=txd->rxd internal loopback enable
4190          * 01  reserved, must be zero
4191          * 00  1=master IRQ enable
4192          */
4193         wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4194
4195         if (info->params.loopback)
4196                 enable_loopback(info);
4197 }
4198
4199 /*
4200  *  set transmit idle mode
4201  */
4202 static void tx_set_idle(struct slgt_info *info)
4203 {
4204         unsigned char val;
4205         unsigned short tcr;
4206
4207         /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4208          * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4209          */
4210         tcr = rd_reg16(info, TCR);
4211         if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4212                 /* disable preamble, set idle size to 16 bits */
4213                 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4214                 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4215                 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4216         } else if (!(tcr & BIT6)) {
4217                 /* preamble is disabled, set idle size to 8 bits */
4218                 tcr &= ~(BIT5 + BIT4);
4219         }
4220         wr_reg16(info, TCR, tcr);
4221
4222         if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4223                 /* LSB of custom tx idle specified in tx idle register */
4224                 val = (unsigned char)(info->idle_mode & 0xff);
4225         } else {
4226                 /* standard 8 bit idle patterns */
4227                 switch(info->idle_mode)
4228                 {
4229                 case HDLC_TXIDLE_FLAGS:          val = 0x7e; break;
4230                 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4231                 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4232                 case HDLC_TXIDLE_ZEROS:
4233                 case HDLC_TXIDLE_SPACE:          val = 0x00; break;
4234                 default:                         val = 0xff;
4235                 }
4236         }
4237
4238         wr_reg8(info, TIR, val);
4239 }
4240
4241 /*
4242  * get state of V24 status (input) signals
4243  */
4244 static void get_signals(struct slgt_info *info)
4245 {
4246         unsigned short status = rd_reg16(info, SSR);
4247
4248         /* clear all serial signals except DTR and RTS */
4249         info->signals &= SerialSignal_DTR + SerialSignal_RTS;
4250
4251         if (status & BIT3)
4252                 info->signals |= SerialSignal_DSR;
4253         if (status & BIT2)
4254                 info->signals |= SerialSignal_CTS;
4255         if (status & BIT1)
4256                 info->signals |= SerialSignal_DCD;
4257         if (status & BIT0)
4258                 info->signals |= SerialSignal_RI;
4259 }
4260
4261 /*
4262  * set V.24 Control Register based on current configuration
4263  */
4264 static void msc_set_vcr(struct slgt_info *info)
4265 {
4266         unsigned char val = 0;
4267
4268         /* VCR (V.24 control)
4269          *
4270          * 07..04  serial IF select
4271          * 03      DTR
4272          * 02      RTS
4273          * 01      LL
4274          * 00      RL
4275          */
4276
4277         switch(info->if_mode & MGSL_INTERFACE_MASK)
4278         {
4279         case MGSL_INTERFACE_RS232:
4280                 val |= BIT5; /* 0010 */
4281                 break;
4282         case MGSL_INTERFACE_V35:
4283                 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4284                 break;
4285         case MGSL_INTERFACE_RS422:
4286                 val |= BIT6; /* 0100 */
4287                 break;
4288         }
4289
4290         if (info->signals & SerialSignal_DTR)
4291                 val |= BIT3;
4292         if (info->signals & SerialSignal_RTS)
4293                 val |= BIT2;
4294         if (info->if_mode & MGSL_INTERFACE_LL)
4295                 val |= BIT1;
4296         if (info->if_mode & MGSL_INTERFACE_RL)
4297                 val |= BIT0;
4298         wr_reg8(info, VCR, val);
4299 }
4300
4301 /*
4302  * set state of V24 control (output) signals
4303  */
4304 static void set_signals(struct slgt_info *info)
4305 {
4306         unsigned char val = rd_reg8(info, VCR);
4307         if (info->signals & SerialSignal_DTR)
4308                 val |= BIT3;
4309         else
4310                 val &= ~BIT3;
4311         if (info->signals & SerialSignal_RTS)
4312                 val |= BIT2;
4313         else
4314                 val &= ~BIT2;
4315         wr_reg8(info, VCR, val);
4316 }
4317
4318 /*
4319  * free range of receive DMA buffers (i to last)
4320  */
4321 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4322 {
4323         int done = 0;
4324
4325         while(!done) {
4326                 /* reset current buffer for reuse */
4327                 info->rbufs[i].status = 0;
4328                 switch(info->params.mode) {
4329                 case MGSL_MODE_RAW:
4330                 case MGSL_MODE_MONOSYNC:
4331                 case MGSL_MODE_BISYNC:
4332                         set_desc_count(info->rbufs[i], info->raw_rx_size);
4333                         break;
4334                 default:
4335                         set_desc_count(info->rbufs[i], DMABUFSIZE);
4336                 }
4337
4338                 if (i == last)
4339                         done = 1;
4340                 if (++i == info->rbuf_count)
4341                         i = 0;
4342         }
4343         info->rbuf_current = i;
4344 }
4345
4346 /*
4347  * mark all receive DMA buffers as free
4348  */
4349 static void reset_rbufs(struct slgt_info *info)
4350 {
4351         free_rbufs(info, 0, info->rbuf_count - 1);
4352 }
4353
4354 /*
4355  * pass receive HDLC frame to upper layer
4356  *
4357  * return 1 if frame available, otherwise 0
4358  */
4359 static int rx_get_frame(struct slgt_info *info)
4360 {
4361         unsigned int start, end;
4362         unsigned short status;
4363         unsigned int framesize = 0;
4364         int rc = 0;
4365         unsigned long flags;
4366         struct tty_struct *tty = info->tty;
4367         unsigned char addr_field = 0xff;
4368         unsigned int crc_size = 0;
4369
4370         switch (info->params.crc_type & HDLC_CRC_MASK) {
4371         case HDLC_CRC_16_CCITT: crc_size = 2; break;
4372         case HDLC_CRC_32_CCITT: crc_size = 4; break;
4373         }
4374
4375 check_again:
4376
4377         framesize = 0;
4378         addr_field = 0xff;
4379         start = end = info->rbuf_current;
4380
4381         for (;;) {
4382                 if (!desc_complete(info->rbufs[end]))
4383                         goto cleanup;
4384
4385                 if (framesize == 0 && info->params.addr_filter != 0xff)
4386                         addr_field = info->rbufs[end].buf[0];
4387
4388                 framesize += desc_count(info->rbufs[end]);
4389
4390                 if (desc_eof(info->rbufs[end]))
4391                         break;
4392
4393                 if (++end == info->rbuf_count)
4394                         end = 0;
4395
4396                 if (end == info->rbuf_current) {
4397                         if (info->rx_enabled){
4398                                 spin_lock_irqsave(&info->lock,flags);
4399                                 rx_start(info);
4400                                 spin_unlock_irqrestore(&info->lock,flags);
4401                         }
4402                         goto cleanup;
4403                 }
4404         }
4405
4406         /* status
4407          *
4408          * 15      buffer complete
4409          * 14..06  reserved
4410          * 05..04  residue
4411          * 02      eof (end of frame)
4412          * 01      CRC error
4413          * 00      abort
4414          */
4415         status = desc_status(info->rbufs[end]);
4416
4417         /* ignore CRC bit if not using CRC (bit is undefined) */
4418         if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4419                 status &= ~BIT1;
4420
4421         if (framesize == 0 ||
4422                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4423                 free_rbufs(info, start, end);
4424                 goto check_again;
4425         }
4426
4427         if (framesize < (2 + crc_size) || status & BIT0) {
4428                 info->icount.rxshort++;
4429                 framesize = 0;
4430         } else if (status & BIT1) {
4431                 info->icount.rxcrc++;
4432                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4433                         framesize = 0;
4434         }
4435
4436 #ifdef CONFIG_HDLC
4437         if (framesize == 0) {
4438                 struct net_device_stats *stats = hdlc_stats(info->netdev);
4439                 stats->rx_errors++;
4440                 stats->rx_frame_errors++;
4441         }
4442 #endif
4443
4444         DBGBH(("%s rx frame status=%04X size=%d\n",
4445                 info->device_name, status, framesize));
4446         DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, DMABUFSIZE), "rx");
4447
4448         if (framesize) {
4449                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4450                         framesize -= crc_size;
4451                         crc_size = 0;
4452                 }
4453
4454                 if (framesize > info->max_frame_size + crc_size)
4455                         info->icount.rxlong++;
4456                 else {
4457                         /* copy dma buffer(s) to contiguous temp buffer */
4458                         int copy_count = framesize;
4459                         int i = start;
4460                         unsigned char *p = info->tmp_rbuf;
4461                         info->tmp_rbuf_count = framesize;
4462
4463                         info->icount.rxok++;
4464
4465                         while(copy_count) {
4466                                 int partial_count = min(copy_count, DMABUFSIZE);
4467                                 memcpy(p, info->rbufs[i].buf, partial_count);
4468                                 p += partial_count;
4469                                 copy_count -= partial_count;
4470                                 if (++i == info->rbuf_count)
4471                                         i = 0;
4472                         }
4473
4474                         if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4475                                 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4476                                 framesize++;
4477                         }
4478
4479 #ifdef CONFIG_HDLC
4480                         if (info->netcount)
4481                                 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4482                         else
4483 #endif
4484                                 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4485                 }
4486         }
4487         free_rbufs(info, start, end);
4488         rc = 1;
4489
4490 cleanup:
4491         return rc;
4492 }
4493
4494 /*
4495  * pass receive buffer (RAW synchronous mode) to tty layer
4496  * return 1 if buffer available, otherwise 0
4497  */
4498 static int rx_get_buf(struct slgt_info *info)
4499 {
4500         unsigned int i = info->rbuf_current;
4501         unsigned int count;
4502
4503         if (!desc_complete(info->rbufs[i]))
4504                 return 0;
4505         count = desc_count(info->rbufs[i]);
4506         switch(info->params.mode) {
4507         case MGSL_MODE_MONOSYNC:
4508         case MGSL_MODE_BISYNC:
4509                 /* ignore residue in byte synchronous modes */
4510                 if (desc_residue(info->rbufs[i]))
4511                         count--;
4512                 break;
4513         }
4514         DBGDATA(info, info->rbufs[i].buf, count, "rx");
4515         DBGINFO(("rx_get_buf size=%d\n", count));
4516         if (count)
4517                 ldisc_receive_buf(info->tty, info->rbufs[i].buf,
4518                                   info->flag_buf, count);
4519         free_rbufs(info, i, i);
4520         return 1;
4521 }
4522
4523 static void reset_tbufs(struct slgt_info *info)
4524 {
4525         unsigned int i;
4526         info->tbuf_current = 0;
4527         for (i=0 ; i < info->tbuf_count ; i++) {
4528                 info->tbufs[i].status = 0;
4529                 info->tbufs[i].count  = 0;
4530         }
4531 }
4532
4533 /*
4534  * return number of free transmit DMA buffers
4535  */
4536 static unsigned int free_tbuf_count(struct slgt_info *info)
4537 {
4538         unsigned int count = 0;
4539         unsigned int i = info->tbuf_current;
4540
4541         do
4542         {
4543                 if (desc_count(info->tbufs[i]))
4544                         break; /* buffer in use */
4545                 ++count;
4546                 if (++i == info->tbuf_count)
4547                         i=0;
4548         } while (i != info->tbuf_current);
4549
4550         /* last buffer with zero count may be in use, assume it is */
4551         if (count)
4552                 --count;
4553
4554         return count;
4555 }
4556
4557 /*
4558  * load transmit DMA buffer(s) with data
4559  */
4560 static void tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4561 {
4562         unsigned short count;
4563         unsigned int i;
4564         struct slgt_desc *d;
4565
4566         if (size == 0)
4567                 return;
4568
4569         DBGDATA(info, buf, size, "tx");
4570
4571         info->tbuf_start = i = info->tbuf_current;
4572
4573         while (size) {
4574                 d = &info->tbufs[i];
4575                 if (++i == info->tbuf_count)
4576                         i = 0;
4577
4578                 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4579                 memcpy(d->buf, buf, count);
4580
4581                 size -= count;
4582                 buf  += count;
4583
4584                 /*
4585                  * set EOF bit for last buffer of HDLC frame or
4586                  * for every buffer in raw mode
4587                  */
4588                 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4589                     info->params.mode == MGSL_MODE_RAW)
4590                         set_desc_eof(*d, 1);
4591                 else
4592                         set_desc_eof(*d, 0);
4593
4594                 set_desc_count(*d, count);
4595         }
4596
4597         info->tbuf_current = i;
4598 }
4599
4600 static int register_test(struct slgt_info *info)
4601 {
4602         static unsigned short patterns[] =
4603                 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4604         static unsigned int count = sizeof(patterns)/sizeof(patterns[0]);
4605         unsigned int i;
4606         int rc = 0;
4607
4608         for (i=0 ; i < count ; i++) {
4609                 wr_reg16(info, TIR, patterns[i]);
4610                 wr_reg16(info, BDR, patterns[(i+1)%count]);
4611                 if ((rd_reg16(info, TIR) != patterns[i]) ||
4612                     (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4613                         rc = -ENODEV;
4614                         break;
4615                 }
4616         }
4617         info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4618         info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4619         return rc;
4620 }
4621
4622 static int irq_test(struct slgt_info *info)
4623 {
4624         unsigned long timeout;
4625         unsigned long flags;
4626         struct tty_struct *oldtty = info->tty;
4627         u32 speed = info->params.data_rate;
4628
4629         info->params.data_rate = 921600;
4630         info->tty = NULL;
4631
4632         spin_lock_irqsave(&info->lock, flags);
4633         async_mode(info);
4634         slgt_irq_on(info, IRQ_TXIDLE);
4635
4636         /* enable transmitter */
4637         wr_reg16(info, TCR,
4638                 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4639
4640         /* write one byte and wait for tx idle */
4641         wr_reg16(info, TDR, 0);
4642
4643         /* assume failure */
4644         info->init_error = DiagStatus_IrqFailure;
4645         info->irq_occurred = FALSE;
4646
4647         spin_unlock_irqrestore(&info->lock, flags);
4648
4649         timeout=100;
4650         while(timeout-- && !info->irq_occurred)
4651                 msleep_interruptible(10);
4652
4653         spin_lock_irqsave(&info->lock,flags);
4654         reset_port(info);
4655         spin_unlock_irqrestore(&info->lock,flags);
4656
4657         info->params.data_rate = speed;
4658         info->tty = oldtty;
4659
4660         info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4661         return info->irq_occurred ? 0 : -ENODEV;
4662 }
4663
4664 static int loopback_test_rx(struct slgt_info *info)
4665 {
4666         unsigned char *src, *dest;
4667         int count;
4668
4669         if (desc_complete(info->rbufs[0])) {
4670                 count = desc_count(info->rbufs[0]);
4671                 src   = info->rbufs[0].buf;
4672                 dest  = info->tmp_rbuf;
4673
4674                 for( ; count ; count-=2, src+=2) {
4675                         /* src=data byte (src+1)=status byte */
4676                         if (!(*(src+1) & (BIT9 + BIT8))) {
4677                                 *dest = *src;
4678                                 dest++;
4679                                 info->tmp_rbuf_count++;
4680                         }
4681                 }
4682                 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4683                 return 1;
4684         }
4685         return 0;
4686 }
4687
4688 static int loopback_test(struct slgt_info *info)
4689 {
4690 #define TESTFRAMESIZE 20
4691
4692         unsigned long timeout;
4693         u16 count = TESTFRAMESIZE;
4694         unsigned char buf[TESTFRAMESIZE];
4695         int rc = -ENODEV;
4696         unsigned long flags;
4697
4698         struct tty_struct *oldtty = info->tty;
4699         MGSL_PARAMS params;
4700
4701         memcpy(&params, &info->params, sizeof(params));
4702
4703         info->params.mode = MGSL_MODE_ASYNC;
4704         info->params.data_rate = 921600;
4705         info->params.loopback = 1;
4706         info->tty = NULL;
4707
4708         /* build and send transmit frame */
4709         for (count = 0; count < TESTFRAMESIZE; ++count)
4710                 buf[count] = (unsigned char)count;
4711
4712         info->tmp_rbuf_count = 0;
4713         memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4714
4715         /* program hardware for HDLC and enabled receiver */
4716         spin_lock_irqsave(&info->lock,flags);
4717         async_mode(info);
4718         rx_start(info);
4719         info->tx_count = count;
4720         tx_load(info, buf, count);
4721         tx_start(info);
4722         spin_unlock_irqrestore(&info->lock, flags);
4723
4724         /* wait for receive complete */
4725         for (timeout = 100; timeout; --timeout) {
4726                 msleep_interruptible(10);
4727                 if (loopback_test_rx(info)) {
4728                         rc = 0;
4729                         break;
4730                 }
4731         }
4732
4733         /* verify received frame length and contents */
4734         if (!rc && (info->tmp_rbuf_count != count ||
4735                   memcmp(buf, info->tmp_rbuf, count))) {
4736                 rc = -ENODEV;
4737         }
4738
4739         spin_lock_irqsave(&info->lock,flags);
4740         reset_adapter(info);
4741         spin_unlock_irqrestore(&info->lock,flags);
4742
4743         memcpy(&info->params, &params, sizeof(info->params));
4744         info->tty = oldtty;
4745
4746         info->init_error = rc ? DiagStatus_DmaFailure : 0;
4747         return rc;
4748 }
4749
4750 static int adapter_test(struct slgt_info *info)
4751 {
4752         DBGINFO(("testing %s\n", info->device_name));
4753         if (register_test(info) < 0) {
4754                 printk("register test failure %s addr=%08X\n",
4755                         info->device_name, info->phys_reg_addr);
4756         } else if (irq_test(info) < 0) {
4757                 printk("IRQ test failure %s IRQ=%d\n",
4758                         info->device_name, info->irq_level);
4759         } else if (loopback_test(info) < 0) {
4760                 printk("loopback test failure %s\n", info->device_name);
4761         }
4762         return info->init_error;
4763 }
4764
4765 /*
4766  * transmit timeout handler
4767  */
4768 static void tx_timeout(unsigned long context)
4769 {
4770         struct slgt_info *info = (struct slgt_info*)context;
4771         unsigned long flags;
4772
4773         DBGINFO(("%s tx_timeout\n", info->device_name));
4774         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
4775                 info->icount.txtimeout++;
4776         }
4777         spin_lock_irqsave(&info->lock,flags);
4778         info->tx_active = 0;
4779         info->tx_count = 0;
4780         spin_unlock_irqrestore(&info->lock,flags);
4781
4782 #ifdef CONFIG_HDLC
4783         if (info->netcount)
4784                 hdlcdev_tx_done(info);
4785         else
4786 #endif
4787                 bh_transmit(info);
4788 }
4789
4790 /*
4791  * receive buffer polling timer
4792  */
4793 static void rx_timeout(unsigned long context)
4794 {
4795         struct slgt_info *info = (struct slgt_info*)context;
4796         unsigned long flags;
4797
4798         DBGINFO(("%s rx_timeout\n", info->device_name));
4799         spin_lock_irqsave(&info->lock, flags);
4800         info->pending_bh |= BH_RECEIVE;
4801         spin_unlock_irqrestore(&info->lock, flags);
4802         bh_handler(info);
4803 }
4804