af77f71bdaa5e8832fea4b0eb858807a7934b1c9
[linux-3.10.git] / drivers / ata / sata_vsc.c
1 /*
2  *  sata_vsc.c - Vitesse VSC7174 4 port DPA SATA
3  *
4  *  Maintained by:  Jeremy Higdon @ SGI
5  *                  Please ALWAYS copy linux-ide@vger.kernel.org
6  *                  on emails.
7  *
8  *  Copyright 2004 SGI
9  *
10  *  Bits from Jeff Garzik, Copyright RedHat, Inc.
11  *
12  *
13  *  This program is free software; you can redistribute it and/or modify
14  *  it under the terms of the GNU General Public License as published by
15  *  the Free Software Foundation; either version 2, or (at your option)
16  *  any later version.
17  *
18  *  This program is distributed in the hope that it will be useful,
19  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
20  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
21  *  GNU General Public License for more details.
22  *
23  *  You should have received a copy of the GNU General Public License
24  *  along with this program; see the file COPYING.  If not, write to
25  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26  *
27  *
28  *  libata documentation is available via 'make {ps|pdf}docs',
29  *  as Documentation/DocBook/libata.*
30  *
31  *  Vitesse hardware documentation presumably available under NDA.
32  *  Intel 31244 (same hardware interface) documentation presumably
33  *  available from http://developer.intel.com/
34  *
35  */
36
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/init.h>
41 #include <linux/blkdev.h>
42 #include <linux/delay.h>
43 #include <linux/interrupt.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/device.h>
46 #include <scsi/scsi_host.h>
47 #include <linux/libata.h>
48
49 #define DRV_NAME        "sata_vsc"
50 #define DRV_VERSION     "2.0"
51
52 enum {
53         /* Interrupt register offsets (from chip base address) */
54         VSC_SATA_INT_STAT_OFFSET        = 0x00,
55         VSC_SATA_INT_MASK_OFFSET        = 0x04,
56
57         /* Taskfile registers offsets */
58         VSC_SATA_TF_CMD_OFFSET          = 0x00,
59         VSC_SATA_TF_DATA_OFFSET         = 0x00,
60         VSC_SATA_TF_ERROR_OFFSET        = 0x04,
61         VSC_SATA_TF_FEATURE_OFFSET      = 0x06,
62         VSC_SATA_TF_NSECT_OFFSET        = 0x08,
63         VSC_SATA_TF_LBAL_OFFSET         = 0x0c,
64         VSC_SATA_TF_LBAM_OFFSET         = 0x10,
65         VSC_SATA_TF_LBAH_OFFSET         = 0x14,
66         VSC_SATA_TF_DEVICE_OFFSET       = 0x18,
67         VSC_SATA_TF_STATUS_OFFSET       = 0x1c,
68         VSC_SATA_TF_COMMAND_OFFSET      = 0x1d,
69         VSC_SATA_TF_ALTSTATUS_OFFSET    = 0x28,
70         VSC_SATA_TF_CTL_OFFSET          = 0x29,
71
72         /* DMA base */
73         VSC_SATA_UP_DESCRIPTOR_OFFSET   = 0x64,
74         VSC_SATA_UP_DATA_BUFFER_OFFSET  = 0x6C,
75         VSC_SATA_DMA_CMD_OFFSET         = 0x70,
76
77         /* SCRs base */
78         VSC_SATA_SCR_STATUS_OFFSET      = 0x100,
79         VSC_SATA_SCR_ERROR_OFFSET       = 0x104,
80         VSC_SATA_SCR_CONTROL_OFFSET     = 0x108,
81
82         /* Port stride */
83         VSC_SATA_PORT_OFFSET            = 0x200,
84
85         /* Error interrupt status bit offsets */
86         VSC_SATA_INT_ERROR_CRC          = 0x40,
87         VSC_SATA_INT_ERROR_T            = 0x20,
88         VSC_SATA_INT_ERROR_P            = 0x10,
89         VSC_SATA_INT_ERROR_R            = 0x8,
90         VSC_SATA_INT_ERROR_E            = 0x4,
91         VSC_SATA_INT_ERROR_M            = 0x2,
92         VSC_SATA_INT_PHY_CHANGE         = 0x1,
93         VSC_SATA_INT_ERROR = (VSC_SATA_INT_ERROR_CRC  | VSC_SATA_INT_ERROR_T | \
94                               VSC_SATA_INT_ERROR_P    | VSC_SATA_INT_ERROR_R | \
95                               VSC_SATA_INT_ERROR_E    | VSC_SATA_INT_ERROR_M | \
96                               VSC_SATA_INT_PHY_CHANGE),
97 };
98
99 #define is_vsc_sata_int_err(port_idx, int_status) \
100          (int_status & (VSC_SATA_INT_ERROR << (8 * port_idx)))
101
102
103 static u32 vsc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
104 {
105         if (sc_reg > SCR_CONTROL)
106                 return 0xffffffffU;
107         return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
108 }
109
110
111 static void vsc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
112                                u32 val)
113 {
114         if (sc_reg > SCR_CONTROL)
115                 return;
116         writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
117 }
118
119
120 static void vsc_intr_mask_update(struct ata_port *ap, u8 ctl)
121 {
122         void __iomem *mask_addr;
123         u8 mask;
124
125         mask_addr = ap->host->mmio_base +
126                 VSC_SATA_INT_MASK_OFFSET + ap->port_no;
127         mask = readb(mask_addr);
128         if (ctl & ATA_NIEN)
129                 mask |= 0x80;
130         else
131                 mask &= 0x7F;
132         writeb(mask, mask_addr);
133 }
134
135
136 static void vsc_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
137 {
138         struct ata_ioports *ioaddr = &ap->ioaddr;
139         unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
140
141         /*
142          * The only thing the ctl register is used for is SRST.
143          * That is not enabled or disabled via tf_load.
144          * However, if ATA_NIEN is changed, then we need to change the interrupt register.
145          */
146         if ((tf->ctl & ATA_NIEN) != (ap->last_ctl & ATA_NIEN)) {
147                 ap->last_ctl = tf->ctl;
148                 vsc_intr_mask_update(ap, tf->ctl & ATA_NIEN);
149         }
150         if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
151                 writew(tf->feature | (((u16)tf->hob_feature) << 8),
152                        (void __iomem *) ioaddr->feature_addr);
153                 writew(tf->nsect | (((u16)tf->hob_nsect) << 8),
154                        (void __iomem *) ioaddr->nsect_addr);
155                 writew(tf->lbal | (((u16)tf->hob_lbal) << 8),
156                        (void __iomem *) ioaddr->lbal_addr);
157                 writew(tf->lbam | (((u16)tf->hob_lbam) << 8),
158                        (void __iomem *) ioaddr->lbam_addr);
159                 writew(tf->lbah | (((u16)tf->hob_lbah) << 8),
160                        (void __iomem *) ioaddr->lbah_addr);
161         } else if (is_addr) {
162                 writew(tf->feature, (void __iomem *) ioaddr->feature_addr);
163                 writew(tf->nsect, (void __iomem *) ioaddr->nsect_addr);
164                 writew(tf->lbal, (void __iomem *) ioaddr->lbal_addr);
165                 writew(tf->lbam, (void __iomem *) ioaddr->lbam_addr);
166                 writew(tf->lbah, (void __iomem *) ioaddr->lbah_addr);
167         }
168
169         if (tf->flags & ATA_TFLAG_DEVICE)
170                 writeb(tf->device, (void __iomem *) ioaddr->device_addr);
171
172         ata_wait_idle(ap);
173 }
174
175
176 static void vsc_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
177 {
178         struct ata_ioports *ioaddr = &ap->ioaddr;
179         u16 nsect, lbal, lbam, lbah, feature;
180
181         tf->command = ata_check_status(ap);
182         tf->device = readw((void __iomem *) ioaddr->device_addr);
183         feature = readw((void __iomem *) ioaddr->error_addr);
184         nsect = readw((void __iomem *) ioaddr->nsect_addr);
185         lbal = readw((void __iomem *) ioaddr->lbal_addr);
186         lbam = readw((void __iomem *) ioaddr->lbam_addr);
187         lbah = readw((void __iomem *) ioaddr->lbah_addr);
188
189         tf->feature = feature;
190         tf->nsect = nsect;
191         tf->lbal = lbal;
192         tf->lbam = lbam;
193         tf->lbah = lbah;
194
195         if (tf->flags & ATA_TFLAG_LBA48) {
196                 tf->hob_feature = feature >> 8;
197                 tf->hob_nsect = nsect >> 8;
198                 tf->hob_lbal = lbal >> 8;
199                 tf->hob_lbam = lbam >> 8;
200                 tf->hob_lbah = lbah >> 8;
201         }
202 }
203
204
205 /*
206  * vsc_sata_interrupt
207  *
208  * Read the interrupt register and process for the devices that have them pending.
209  */
210 static irqreturn_t vsc_sata_interrupt (int irq, void *dev_instance)
211 {
212         struct ata_host *host = dev_instance;
213         unsigned int i;
214         unsigned int handled = 0;
215         u32 int_status;
216
217         spin_lock(&host->lock);
218
219         int_status = readl(host->mmio_base + VSC_SATA_INT_STAT_OFFSET);
220
221         for (i = 0; i < host->n_ports; i++) {
222                 if (int_status & ((u32) 0xFF << (8 * i))) {
223                         struct ata_port *ap;
224
225                         ap = host->ports[i];
226
227                         if (is_vsc_sata_int_err(i, int_status)) {
228                                 u32 err_status;
229                                 printk(KERN_DEBUG "%s: ignoring interrupt(s)\n", __FUNCTION__);
230                                 err_status = ap ? vsc_sata_scr_read(ap, SCR_ERROR) : 0;
231                                 vsc_sata_scr_write(ap, SCR_ERROR, err_status);
232                                 handled++;
233                         }
234
235                         if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
236                                 struct ata_queued_cmd *qc;
237
238                                 qc = ata_qc_from_tag(ap, ap->active_tag);
239                                 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
240                                         handled += ata_host_intr(ap, qc);
241                                 else if (is_vsc_sata_int_err(i, int_status)) {
242                                         /*
243                                          * On some chips (i.e. Intel 31244), an error
244                                          * interrupt will sneak in at initialization
245                                          * time (phy state changes).  Clearing the SCR
246                                          * error register is not required, but it prevents
247                                          * the phy state change interrupts from recurring
248                                          * later.
249                                          */
250                                         u32 err_status;
251                                         err_status = vsc_sata_scr_read(ap, SCR_ERROR);
252                                         printk(KERN_DEBUG "%s: clearing interrupt, "
253                                                "status %x; sata err status %x\n",
254                                                __FUNCTION__,
255                                                int_status, err_status);
256                                         vsc_sata_scr_write(ap, SCR_ERROR, err_status);
257                                         /* Clear interrupt status */
258                                         ata_chk_status(ap);
259                                         handled++;
260                                 }
261                         }
262                 }
263         }
264
265         spin_unlock(&host->lock);
266
267         return IRQ_RETVAL(handled);
268 }
269
270
271 static struct scsi_host_template vsc_sata_sht = {
272         .module                 = THIS_MODULE,
273         .name                   = DRV_NAME,
274         .ioctl                  = ata_scsi_ioctl,
275         .queuecommand           = ata_scsi_queuecmd,
276         .can_queue              = ATA_DEF_QUEUE,
277         .this_id                = ATA_SHT_THIS_ID,
278         .sg_tablesize           = LIBATA_MAX_PRD,
279         .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
280         .emulated               = ATA_SHT_EMULATED,
281         .use_clustering         = ATA_SHT_USE_CLUSTERING,
282         .proc_name              = DRV_NAME,
283         .dma_boundary           = ATA_DMA_BOUNDARY,
284         .slave_configure        = ata_scsi_slave_config,
285         .slave_destroy          = ata_scsi_slave_destroy,
286         .bios_param             = ata_std_bios_param,
287 };
288
289
290 static const struct ata_port_operations vsc_sata_ops = {
291         .port_disable           = ata_port_disable,
292         .tf_load                = vsc_sata_tf_load,
293         .tf_read                = vsc_sata_tf_read,
294         .exec_command           = ata_exec_command,
295         .check_status           = ata_check_status,
296         .dev_select             = ata_std_dev_select,
297         .bmdma_setup            = ata_bmdma_setup,
298         .bmdma_start            = ata_bmdma_start,
299         .bmdma_stop             = ata_bmdma_stop,
300         .bmdma_status           = ata_bmdma_status,
301         .qc_prep                = ata_qc_prep,
302         .qc_issue               = ata_qc_issue_prot,
303         .data_xfer              = ata_mmio_data_xfer,
304         .freeze                 = ata_bmdma_freeze,
305         .thaw                   = ata_bmdma_thaw,
306         .error_handler          = ata_bmdma_error_handler,
307         .post_internal_cmd      = ata_bmdma_post_internal_cmd,
308         .irq_handler            = vsc_sata_interrupt,
309         .irq_clear              = ata_bmdma_irq_clear,
310         .scr_read               = vsc_sata_scr_read,
311         .scr_write              = vsc_sata_scr_write,
312         .port_start             = ata_port_start,
313 };
314
315 static void __devinit vsc_sata_setup_port(struct ata_ioports *port, unsigned long base)
316 {
317         port->cmd_addr          = base + VSC_SATA_TF_CMD_OFFSET;
318         port->data_addr         = base + VSC_SATA_TF_DATA_OFFSET;
319         port->error_addr        = base + VSC_SATA_TF_ERROR_OFFSET;
320         port->feature_addr      = base + VSC_SATA_TF_FEATURE_OFFSET;
321         port->nsect_addr        = base + VSC_SATA_TF_NSECT_OFFSET;
322         port->lbal_addr         = base + VSC_SATA_TF_LBAL_OFFSET;
323         port->lbam_addr         = base + VSC_SATA_TF_LBAM_OFFSET;
324         port->lbah_addr         = base + VSC_SATA_TF_LBAH_OFFSET;
325         port->device_addr       = base + VSC_SATA_TF_DEVICE_OFFSET;
326         port->status_addr       = base + VSC_SATA_TF_STATUS_OFFSET;
327         port->command_addr      = base + VSC_SATA_TF_COMMAND_OFFSET;
328         port->altstatus_addr    = base + VSC_SATA_TF_ALTSTATUS_OFFSET;
329         port->ctl_addr          = base + VSC_SATA_TF_CTL_OFFSET;
330         port->bmdma_addr        = base + VSC_SATA_DMA_CMD_OFFSET;
331         port->scr_addr          = base + VSC_SATA_SCR_STATUS_OFFSET;
332         writel(0, (void __iomem *) base + VSC_SATA_UP_DESCRIPTOR_OFFSET);
333         writel(0, (void __iomem *) base + VSC_SATA_UP_DATA_BUFFER_OFFSET);
334 }
335
336
337 static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
338 {
339         static int printed_version;
340         struct ata_probe_ent *probe_ent = NULL;
341         unsigned long base;
342         void __iomem *mmio_base;
343         int rc;
344
345         if (!printed_version++)
346                 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
347
348         rc = pcim_enable_device(pdev);
349         if (rc)
350                 return rc;
351
352         /*
353          * Check if we have needed resource mapped.
354          */
355         if (pci_resource_len(pdev, 0) == 0)
356                 return -ENODEV;
357
358         rc = pci_request_regions(pdev, DRV_NAME);
359         if (rc) {
360                 pcim_pin_device(pdev);
361                 return rc;
362         }
363
364         /*
365          * Use 32 bit DMA mask, because 64 bit address support is poor.
366          */
367         rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
368         if (rc)
369                 return rc;
370         rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
371         if (rc)
372                 return rc;
373
374         probe_ent = devm_kzalloc(&pdev->dev, sizeof(*probe_ent), GFP_KERNEL);
375         if (probe_ent == NULL)
376                 return -ENOMEM;
377         probe_ent->dev = pci_dev_to_dev(pdev);
378         INIT_LIST_HEAD(&probe_ent->node);
379
380         mmio_base = pcim_iomap(pdev, 0, 0);
381         if (mmio_base == NULL)
382                 return -ENOMEM;
383         base = (unsigned long) mmio_base;
384
385         /*
386          * Due to a bug in the chip, the default cache line size can't be used
387          */
388         pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);
389
390         if (pci_enable_msi(pdev) == 0)
391                 pci_intx(pdev, 0);
392         else
393                 probe_ent->irq_flags = IRQF_SHARED;
394
395         probe_ent->sht = &vsc_sata_sht;
396         probe_ent->port_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
397                                 ATA_FLAG_MMIO;
398         probe_ent->port_ops = &vsc_sata_ops;
399         probe_ent->n_ports = 4;
400         probe_ent->irq = pdev->irq;
401         probe_ent->mmio_base = mmio_base;
402
403         /* We don't care much about the PIO/UDMA masks, but the core won't like us
404          * if we don't fill these
405          */
406         probe_ent->pio_mask = 0x1f;
407         probe_ent->mwdma_mask = 0x07;
408         probe_ent->udma_mask = 0x7f;
409
410         /* We have 4 ports per PCI function */
411         vsc_sata_setup_port(&probe_ent->port[0], base + 1 * VSC_SATA_PORT_OFFSET);
412         vsc_sata_setup_port(&probe_ent->port[1], base + 2 * VSC_SATA_PORT_OFFSET);
413         vsc_sata_setup_port(&probe_ent->port[2], base + 3 * VSC_SATA_PORT_OFFSET);
414         vsc_sata_setup_port(&probe_ent->port[3], base + 4 * VSC_SATA_PORT_OFFSET);
415
416         pci_set_master(pdev);
417
418         /*
419          * Config offset 0x98 is "Extended Control and Status Register 0"
420          * Default value is (1 << 28).  All bits except bit 28 are reserved in
421          * DPA mode.  If bit 28 is set, LED 0 reflects all ports' activity.
422          * If bit 28 is clear, each port has its own LED.
423          */
424         pci_write_config_dword(pdev, 0x98, 0);
425
426         if (!ata_device_add(probe_ent))
427                 return -ENODEV;
428
429         devm_kfree(&pdev->dev, probe_ent);
430         return 0;
431 }
432
433 static const struct pci_device_id vsc_sata_pci_tbl[] = {
434         { PCI_VENDOR_ID_VITESSE, 0x7174,
435           PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
436         { PCI_VENDOR_ID_INTEL, 0x3200,
437           PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
438
439         { }     /* terminate list */
440 };
441
442 static struct pci_driver vsc_sata_pci_driver = {
443         .name                   = DRV_NAME,
444         .id_table               = vsc_sata_pci_tbl,
445         .probe                  = vsc_sata_init_one,
446         .remove                 = ata_pci_remove_one,
447 };
448
449 static int __init vsc_sata_init(void)
450 {
451         return pci_register_driver(&vsc_sata_pci_driver);
452 }
453
454 static void __exit vsc_sata_exit(void)
455 {
456         pci_unregister_driver(&vsc_sata_pci_driver);
457 }
458
459 MODULE_AUTHOR("Jeremy Higdon");
460 MODULE_DESCRIPTION("low-level driver for Vitesse VSC7174 SATA controller");
461 MODULE_LICENSE("GPL");
462 MODULE_DEVICE_TABLE(pci, vsc_sata_pci_tbl);
463 MODULE_VERSION(DRV_VERSION);
464
465 module_init(vsc_sata_init);
466 module_exit(vsc_sata_exit);