Merge master.kernel.org:/pub/scm/linux/kernel/git/lethal/genesis-2.6
[linux-3.10.git] / arch / x86 / oprofile / op_model_amd.c
1 /*
2  * @file op_model_amd.c
3  * athlon / K7 / K8 / Family 10h model-specific MSR operations
4  *
5  * @remark Copyright 2002-2009 OProfile authors
6  * @remark Read the file COPYING
7  *
8  * @author John Levon
9  * @author Philippe Elie
10  * @author Graydon Hoare
11  * @author Robert Richter <robert.richter@amd.com>
12  * @author Barry Kasindorf <barry.kasindorf@amd.com>
13  * @author Jason Yeh <jason.yeh@amd.com>
14  * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
15  */
16
17 #include <linux/oprofile.h>
18 #include <linux/device.h>
19 #include <linux/pci.h>
20 #include <linux/percpu.h>
21
22 #include <asm/ptrace.h>
23 #include <asm/msr.h>
24 #include <asm/nmi.h>
25 #include <asm/apic.h>
26 #include <asm/processor.h>
27 #include <asm/cpufeature.h>
28
29 #include "op_x86_model.h"
30 #include "op_counter.h"
31
32 #define NUM_COUNTERS 4
33 #define NUM_CONTROLS 4
34 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
35 #define NUM_VIRT_COUNTERS 32
36 #define NUM_VIRT_CONTROLS 32
37 #else
38 #define NUM_VIRT_COUNTERS NUM_COUNTERS
39 #define NUM_VIRT_CONTROLS NUM_CONTROLS
40 #endif
41
42 #define OP_EVENT_MASK                   0x0FFF
43 #define OP_CTR_OVERFLOW                 (1ULL<<31)
44
45 #define MSR_AMD_EVENTSEL_RESERVED       ((0xFFFFFCF0ULL<<32)|(1ULL<<21))
46
47 static unsigned long reset_value[NUM_VIRT_COUNTERS];
48
49 #define IBS_FETCH_SIZE                  6
50 #define IBS_OP_SIZE                     12
51
52 static u32 ibs_caps;
53
54 struct op_ibs_config {
55         unsigned long op_enabled;
56         unsigned long fetch_enabled;
57         unsigned long max_cnt_fetch;
58         unsigned long max_cnt_op;
59         unsigned long rand_en;
60         unsigned long dispatched_ops;
61 };
62
63 static struct op_ibs_config ibs_config;
64 static u64 ibs_op_ctl;
65
66 /*
67  * IBS cpuid feature detection
68  */
69
70 #define IBS_CPUID_FEATURES      0x8000001b
71
72 /*
73  * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
74  * bit 0 is used to indicate the existence of IBS.
75  */
76 #define IBS_CAPS_AVAIL                  (1LL<<0)
77 #define IBS_CAPS_RDWROPCNT              (1LL<<3)
78 #define IBS_CAPS_OPCNT                  (1LL<<4)
79
80 /*
81  * IBS randomization macros
82  */
83 #define IBS_RANDOM_BITS                 12
84 #define IBS_RANDOM_MASK                 ((1ULL << IBS_RANDOM_BITS) - 1)
85 #define IBS_RANDOM_MAXCNT_OFFSET        (1ULL << (IBS_RANDOM_BITS - 5))
86
87 static u32 get_ibs_caps(void)
88 {
89         u32 ibs_caps;
90         unsigned int max_level;
91
92         if (!boot_cpu_has(X86_FEATURE_IBS))
93                 return 0;
94
95         /* check IBS cpuid feature flags */
96         max_level = cpuid_eax(0x80000000);
97         if (max_level < IBS_CPUID_FEATURES)
98                 return IBS_CAPS_AVAIL;
99
100         ibs_caps = cpuid_eax(IBS_CPUID_FEATURES);
101         if (!(ibs_caps & IBS_CAPS_AVAIL))
102                 /* cpuid flags not valid */
103                 return IBS_CAPS_AVAIL;
104
105         return ibs_caps;
106 }
107
108 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
109
110 static void op_mux_switch_ctrl(struct op_x86_model_spec const *model,
111                                struct op_msrs const * const msrs)
112 {
113         u64 val;
114         int i;
115
116         /* enable active counters */
117         for (i = 0; i < NUM_COUNTERS; ++i) {
118                 int virt = op_x86_phys_to_virt(i);
119                 if (!reset_value[virt])
120                         continue;
121                 rdmsrl(msrs->controls[i].addr, val);
122                 val &= model->reserved;
123                 val |= op_x86_get_ctrl(model, &counter_config[virt]);
124                 wrmsrl(msrs->controls[i].addr, val);
125         }
126 }
127
128 #endif
129
130 /* functions for op_amd_spec */
131
132 static void op_amd_fill_in_addresses(struct op_msrs * const msrs)
133 {
134         int i;
135
136         for (i = 0; i < NUM_COUNTERS; i++) {
137                 if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
138                         msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
139         }
140
141         for (i = 0; i < NUM_CONTROLS; i++) {
142                 if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i))
143                         msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
144         }
145 }
146
147 static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
148                               struct op_msrs const * const msrs)
149 {
150         u64 val;
151         int i;
152
153         /* setup reset_value */
154         for (i = 0; i < NUM_VIRT_COUNTERS; ++i) {
155                 if (counter_config[i].enabled
156                     && msrs->counters[op_x86_virt_to_phys(i)].addr)
157                         reset_value[i] = counter_config[i].count;
158                 else
159                         reset_value[i] = 0;
160         }
161
162         /* clear all counters */
163         for (i = 0; i < NUM_CONTROLS; ++i) {
164                 if (unlikely(!msrs->controls[i].addr)) {
165                         if (counter_config[i].enabled && !smp_processor_id())
166                                 /*
167                                  * counter is reserved, this is on all
168                                  * cpus, so report only for cpu #0
169                                  */
170                                 op_x86_warn_reserved(i);
171                         continue;
172                 }
173                 rdmsrl(msrs->controls[i].addr, val);
174                 if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
175                         op_x86_warn_in_use(i);
176                 val &= model->reserved;
177                 wrmsrl(msrs->controls[i].addr, val);
178         }
179
180         /* avoid a false detection of ctr overflows in NMI handler */
181         for (i = 0; i < NUM_COUNTERS; ++i) {
182                 if (unlikely(!msrs->counters[i].addr))
183                         continue;
184                 wrmsrl(msrs->counters[i].addr, -1LL);
185         }
186
187         /* enable active counters */
188         for (i = 0; i < NUM_COUNTERS; ++i) {
189                 int virt = op_x86_phys_to_virt(i);
190                 if (!reset_value[virt])
191                         continue;
192
193                 /* setup counter registers */
194                 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
195
196                 /* setup control registers */
197                 rdmsrl(msrs->controls[i].addr, val);
198                 val &= model->reserved;
199                 val |= op_x86_get_ctrl(model, &counter_config[virt]);
200                 wrmsrl(msrs->controls[i].addr, val);
201         }
202 }
203
204 /*
205  * 16-bit Linear Feedback Shift Register (LFSR)
206  *
207  *                       16   14   13    11
208  * Feedback polynomial = X  + X  + X  +  X  + 1
209  */
210 static unsigned int lfsr_random(void)
211 {
212         static unsigned int lfsr_value = 0xF00D;
213         unsigned int bit;
214
215         /* Compute next bit to shift in */
216         bit = ((lfsr_value >> 0) ^
217                (lfsr_value >> 2) ^
218                (lfsr_value >> 3) ^
219                (lfsr_value >> 5)) & 0x0001;
220
221         /* Advance to next register value */
222         lfsr_value = (lfsr_value >> 1) | (bit << 15);
223
224         return lfsr_value;
225 }
226
227 /*
228  * IBS software randomization
229  *
230  * The IBS periodic op counter is randomized in software. The lower 12
231  * bits of the 20 bit counter are randomized. IbsOpCurCnt is
232  * initialized with a 12 bit random value.
233  */
234 static inline u64 op_amd_randomize_ibs_op(u64 val)
235 {
236         unsigned int random = lfsr_random();
237
238         if (!(ibs_caps & IBS_CAPS_RDWROPCNT))
239                 /*
240                  * Work around if the hw can not write to IbsOpCurCnt
241                  *
242                  * Randomize the lower 8 bits of the 16 bit
243                  * IbsOpMaxCnt [15:0] value in the range of -128 to
244                  * +127 by adding/subtracting an offset to the
245                  * maximum count (IbsOpMaxCnt).
246                  *
247                  * To avoid over or underflows and protect upper bits
248                  * starting at bit 16, the initial value for
249                  * IbsOpMaxCnt must fit in the range from 0x0081 to
250                  * 0xff80.
251                  */
252                 val += (s8)(random >> 4);
253         else
254                 val |= (u64)(random & IBS_RANDOM_MASK) << 32;
255
256         return val;
257 }
258
259 static inline void
260 op_amd_handle_ibs(struct pt_regs * const regs,
261                   struct op_msrs const * const msrs)
262 {
263         u64 val, ctl;
264         struct op_entry entry;
265
266         if (!ibs_caps)
267                 return;
268
269         if (ibs_config.fetch_enabled) {
270                 rdmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
271                 if (ctl & IBS_FETCH_VAL) {
272                         rdmsrl(MSR_AMD64_IBSFETCHLINAD, val);
273                         oprofile_write_reserve(&entry, regs, val,
274                                                IBS_FETCH_CODE, IBS_FETCH_SIZE);
275                         oprofile_add_data64(&entry, val);
276                         oprofile_add_data64(&entry, ctl);
277                         rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, val);
278                         oprofile_add_data64(&entry, val);
279                         oprofile_write_commit(&entry);
280
281                         /* reenable the IRQ */
282                         ctl &= ~(IBS_FETCH_VAL | IBS_FETCH_CNT);
283                         ctl |= IBS_FETCH_ENABLE;
284                         wrmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
285                 }
286         }
287
288         if (ibs_config.op_enabled) {
289                 rdmsrl(MSR_AMD64_IBSOPCTL, ctl);
290                 if (ctl & IBS_OP_VAL) {
291                         rdmsrl(MSR_AMD64_IBSOPRIP, val);
292                         oprofile_write_reserve(&entry, regs, val,
293                                                IBS_OP_CODE, IBS_OP_SIZE);
294                         oprofile_add_data64(&entry, val);
295                         rdmsrl(MSR_AMD64_IBSOPDATA, val);
296                         oprofile_add_data64(&entry, val);
297                         rdmsrl(MSR_AMD64_IBSOPDATA2, val);
298                         oprofile_add_data64(&entry, val);
299                         rdmsrl(MSR_AMD64_IBSOPDATA3, val);
300                         oprofile_add_data64(&entry, val);
301                         rdmsrl(MSR_AMD64_IBSDCLINAD, val);
302                         oprofile_add_data64(&entry, val);
303                         rdmsrl(MSR_AMD64_IBSDCPHYSAD, val);
304                         oprofile_add_data64(&entry, val);
305                         oprofile_write_commit(&entry);
306
307                         /* reenable the IRQ */
308                         ctl = op_amd_randomize_ibs_op(ibs_op_ctl);
309                         wrmsrl(MSR_AMD64_IBSOPCTL, ctl);
310                 }
311         }
312 }
313
314 static inline void op_amd_start_ibs(void)
315 {
316         u64 val;
317
318         if (!ibs_caps)
319                 return;
320
321         if (ibs_config.fetch_enabled) {
322                 val = (ibs_config.max_cnt_fetch >> 4) & IBS_FETCH_MAX_CNT;
323                 val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0;
324                 val |= IBS_FETCH_ENABLE;
325                 wrmsrl(MSR_AMD64_IBSFETCHCTL, val);
326         }
327
328         if (ibs_config.op_enabled) {
329                 ibs_op_ctl = ibs_config.max_cnt_op >> 4;
330                 if (!(ibs_caps & IBS_CAPS_RDWROPCNT)) {
331                         /*
332                          * IbsOpCurCnt not supported.  See
333                          * op_amd_randomize_ibs_op() for details.
334                          */
335                         ibs_op_ctl = clamp(ibs_op_ctl, 0x0081ULL, 0xFF80ULL);
336                 } else {
337                         /*
338                          * The start value is randomized with a
339                          * positive offset, we need to compensate it
340                          * with the half of the randomized range. Also
341                          * avoid underflows.
342                          */
343                         ibs_op_ctl = min(ibs_op_ctl + IBS_RANDOM_MAXCNT_OFFSET,
344                                          IBS_OP_MAX_CNT);
345                 }
346                 if (ibs_caps & IBS_CAPS_OPCNT && ibs_config.dispatched_ops)
347                         ibs_op_ctl |= IBS_OP_CNT_CTL;
348                 ibs_op_ctl |= IBS_OP_ENABLE;
349                 val = op_amd_randomize_ibs_op(ibs_op_ctl);
350                 wrmsrl(MSR_AMD64_IBSOPCTL, val);
351         }
352 }
353
354 static void op_amd_stop_ibs(void)
355 {
356         if (!ibs_caps)
357                 return;
358
359         if (ibs_config.fetch_enabled)
360                 /* clear max count and enable */
361                 wrmsrl(MSR_AMD64_IBSFETCHCTL, 0);
362
363         if (ibs_config.op_enabled)
364                 /* clear max count and enable */
365                 wrmsrl(MSR_AMD64_IBSOPCTL, 0);
366 }
367
368 static int op_amd_check_ctrs(struct pt_regs * const regs,
369                              struct op_msrs const * const msrs)
370 {
371         u64 val;
372         int i;
373
374         for (i = 0; i < NUM_COUNTERS; ++i) {
375                 int virt = op_x86_phys_to_virt(i);
376                 if (!reset_value[virt])
377                         continue;
378                 rdmsrl(msrs->counters[i].addr, val);
379                 /* bit is clear if overflowed: */
380                 if (val & OP_CTR_OVERFLOW)
381                         continue;
382                 oprofile_add_sample(regs, virt);
383                 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
384         }
385
386         op_amd_handle_ibs(regs, msrs);
387
388         /* See op_model_ppro.c */
389         return 1;
390 }
391
392 static void op_amd_start(struct op_msrs const * const msrs)
393 {
394         u64 val;
395         int i;
396
397         for (i = 0; i < NUM_COUNTERS; ++i) {
398                 if (!reset_value[op_x86_phys_to_virt(i)])
399                         continue;
400                 rdmsrl(msrs->controls[i].addr, val);
401                 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
402                 wrmsrl(msrs->controls[i].addr, val);
403         }
404
405         op_amd_start_ibs();
406 }
407
408 static void op_amd_stop(struct op_msrs const * const msrs)
409 {
410         u64 val;
411         int i;
412
413         /*
414          * Subtle: stop on all counters to avoid race with setting our
415          * pm callback
416          */
417         for (i = 0; i < NUM_COUNTERS; ++i) {
418                 if (!reset_value[op_x86_phys_to_virt(i)])
419                         continue;
420                 rdmsrl(msrs->controls[i].addr, val);
421                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
422                 wrmsrl(msrs->controls[i].addr, val);
423         }
424
425         op_amd_stop_ibs();
426 }
427
428 static void op_amd_shutdown(struct op_msrs const * const msrs)
429 {
430         int i;
431
432         for (i = 0; i < NUM_COUNTERS; ++i) {
433                 if (msrs->counters[i].addr)
434                         release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
435         }
436         for (i = 0; i < NUM_CONTROLS; ++i) {
437                 if (msrs->controls[i].addr)
438                         release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
439         }
440 }
441
442 static u8 ibs_eilvt_off;
443
444 static inline void apic_init_ibs_nmi_per_cpu(void *arg)
445 {
446         ibs_eilvt_off = setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_NMI, 0);
447 }
448
449 static inline void apic_clear_ibs_nmi_per_cpu(void *arg)
450 {
451         setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1);
452 }
453
454 static int init_ibs_nmi(void)
455 {
456 #define IBSCTL_LVTOFFSETVAL             (1 << 8)
457 #define IBSCTL                          0x1cc
458         struct pci_dev *cpu_cfg;
459         int nodes;
460         u32 value = 0;
461
462         /* per CPU setup */
463         on_each_cpu(apic_init_ibs_nmi_per_cpu, NULL, 1);
464
465         nodes = 0;
466         cpu_cfg = NULL;
467         do {
468                 cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
469                                          PCI_DEVICE_ID_AMD_10H_NB_MISC,
470                                          cpu_cfg);
471                 if (!cpu_cfg)
472                         break;
473                 ++nodes;
474                 pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
475                                        | IBSCTL_LVTOFFSETVAL);
476                 pci_read_config_dword(cpu_cfg, IBSCTL, &value);
477                 if (value != (ibs_eilvt_off | IBSCTL_LVTOFFSETVAL)) {
478                         pci_dev_put(cpu_cfg);
479                         printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
480                                 "IBSCTL = 0x%08x", value);
481                         return 1;
482                 }
483         } while (1);
484
485         if (!nodes) {
486                 printk(KERN_DEBUG "No CPU node configured for IBS");
487                 return 1;
488         }
489
490         return 0;
491 }
492
493 /* uninitialize the APIC for the IBS interrupts if needed */
494 static void clear_ibs_nmi(void)
495 {
496         if (ibs_caps)
497                 on_each_cpu(apic_clear_ibs_nmi_per_cpu, NULL, 1);
498 }
499
500 /* initialize the APIC for the IBS interrupts if available */
501 static void ibs_init(void)
502 {
503         ibs_caps = get_ibs_caps();
504
505         if (!ibs_caps)
506                 return;
507
508         if (init_ibs_nmi()) {
509                 ibs_caps = 0;
510                 return;
511         }
512
513         printk(KERN_INFO "oprofile: AMD IBS detected (0x%08x)\n",
514                (unsigned)ibs_caps);
515 }
516
517 static void ibs_exit(void)
518 {
519         if (!ibs_caps)
520                 return;
521
522         clear_ibs_nmi();
523 }
524
525 static int (*create_arch_files)(struct super_block *sb, struct dentry *root);
526
527 static int setup_ibs_files(struct super_block *sb, struct dentry *root)
528 {
529         struct dentry *dir;
530         int ret = 0;
531
532         /* architecture specific files */
533         if (create_arch_files)
534                 ret = create_arch_files(sb, root);
535
536         if (ret)
537                 return ret;
538
539         if (!ibs_caps)
540                 return ret;
541
542         /* model specific files */
543
544         /* setup some reasonable defaults */
545         ibs_config.max_cnt_fetch = 250000;
546         ibs_config.fetch_enabled = 0;
547         ibs_config.max_cnt_op = 250000;
548         ibs_config.op_enabled = 0;
549         ibs_config.dispatched_ops = 0;
550
551         dir = oprofilefs_mkdir(sb, root, "ibs_fetch");
552         oprofilefs_create_ulong(sb, dir, "enable",
553                                 &ibs_config.fetch_enabled);
554         oprofilefs_create_ulong(sb, dir, "max_count",
555                                 &ibs_config.max_cnt_fetch);
556         oprofilefs_create_ulong(sb, dir, "rand_enable",
557                                 &ibs_config.rand_en);
558
559         dir = oprofilefs_mkdir(sb, root, "ibs_op");
560         oprofilefs_create_ulong(sb, dir, "enable",
561                                 &ibs_config.op_enabled);
562         oprofilefs_create_ulong(sb, dir, "max_count",
563                                 &ibs_config.max_cnt_op);
564         if (ibs_caps & IBS_CAPS_OPCNT)
565                 oprofilefs_create_ulong(sb, dir, "dispatched_ops",
566                                         &ibs_config.dispatched_ops);
567
568         return 0;
569 }
570
571 static int op_amd_init(struct oprofile_operations *ops)
572 {
573         ibs_init();
574         create_arch_files = ops->create_files;
575         ops->create_files = setup_ibs_files;
576         return 0;
577 }
578
579 static void op_amd_exit(void)
580 {
581         ibs_exit();
582 }
583
584 struct op_x86_model_spec op_amd_spec = {
585         .num_counters           = NUM_COUNTERS,
586         .num_controls           = NUM_CONTROLS,
587         .num_virt_counters      = NUM_VIRT_COUNTERS,
588         .reserved               = MSR_AMD_EVENTSEL_RESERVED,
589         .event_mask             = OP_EVENT_MASK,
590         .init                   = op_amd_init,
591         .exit                   = op_amd_exit,
592         .fill_in_addresses      = &op_amd_fill_in_addresses,
593         .setup_ctrs             = &op_amd_setup_ctrs,
594         .check_ctrs             = &op_amd_check_ctrs,
595         .start                  = &op_amd_start,
596         .stop                   = &op_amd_stop,
597         .shutdown               = &op_amd_shutdown,
598 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
599         .switch_ctrl            = &op_mux_switch_ctrl,
600 #endif
601 };