KVM: clean up kvm_(set|get)_apic_base
[linux-3.10.git] / arch / x86 / kvm / x86.c
1 /*
2  * Kernel-based Virtual Machine driver for Linux
3  *
4  * derived from drivers/kvm/kvm_main.c
5  *
6  * Copyright (C) 2006 Qumranet, Inc.
7  * Copyright (C) 2008 Qumranet, Inc.
8  * Copyright IBM Corporation, 2008
9  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10  *
11  * Authors:
12  *   Avi Kivity   <avi@qumranet.com>
13  *   Yaniv Kamay  <yaniv@qumranet.com>
14  *   Amit Shah    <amit.shah@qumranet.com>
15  *   Ben-Ami Yassour <benami@il.ibm.com>
16  *
17  * This work is licensed under the terms of the GNU GPL, version 2.  See
18  * the COPYING file in the top-level directory.
19  *
20  */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30
31 #include <linux/clocksource.h>
32 #include <linux/interrupt.h>
33 #include <linux/kvm.h>
34 #include <linux/fs.h>
35 #include <linux/vmalloc.h>
36 #include <linux/module.h>
37 #include <linux/mman.h>
38 #include <linux/highmem.h>
39 #include <linux/iommu.h>
40 #include <linux/intel-iommu.h>
41 #include <linux/cpufreq.h>
42 #include <linux/user-return-notifier.h>
43 #include <linux/srcu.h>
44 #include <linux/slab.h>
45 #include <linux/perf_event.h>
46 #include <linux/uaccess.h>
47 #include <linux/hash.h>
48 #include <linux/pci.h>
49 #include <trace/events/kvm.h>
50
51 #define CREATE_TRACE_POINTS
52 #include "trace.h"
53
54 #include <asm/debugreg.h>
55 #include <asm/msr.h>
56 #include <asm/desc.h>
57 #include <asm/mtrr.h>
58 #include <asm/mce.h>
59 #include <asm/i387.h>
60 #include <asm/fpu-internal.h> /* Ugh! */
61 #include <asm/xcr.h>
62 #include <asm/pvclock.h>
63 #include <asm/div64.h>
64
65 #define MAX_IO_MSRS 256
66 #define KVM_MAX_MCE_BANKS 32
67 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
68
69 #define emul_to_vcpu(ctxt) \
70         container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
71
72 /* EFER defaults:
73  * - enable syscall per default because its emulated by KVM
74  * - enable LME and LMA per default on 64 bit KVM
75  */
76 #ifdef CONFIG_X86_64
77 static
78 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
79 #else
80 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
81 #endif
82
83 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
84 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
85
86 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
87 static void process_nmi(struct kvm_vcpu *vcpu);
88
89 struct kvm_x86_ops *kvm_x86_ops;
90 EXPORT_SYMBOL_GPL(kvm_x86_ops);
91
92 static bool ignore_msrs = 0;
93 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
94
95 bool kvm_has_tsc_control;
96 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
97 u32  kvm_max_guest_tsc_khz;
98 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
99
100 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
101 static u32 tsc_tolerance_ppm = 250;
102 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
103
104 #define KVM_NR_SHARED_MSRS 16
105
106 struct kvm_shared_msrs_global {
107         int nr;
108         u32 msrs[KVM_NR_SHARED_MSRS];
109 };
110
111 struct kvm_shared_msrs {
112         struct user_return_notifier urn;
113         bool registered;
114         struct kvm_shared_msr_values {
115                 u64 host;
116                 u64 curr;
117         } values[KVM_NR_SHARED_MSRS];
118 };
119
120 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
121 static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
122
123 struct kvm_stats_debugfs_item debugfs_entries[] = {
124         { "pf_fixed", VCPU_STAT(pf_fixed) },
125         { "pf_guest", VCPU_STAT(pf_guest) },
126         { "tlb_flush", VCPU_STAT(tlb_flush) },
127         { "invlpg", VCPU_STAT(invlpg) },
128         { "exits", VCPU_STAT(exits) },
129         { "io_exits", VCPU_STAT(io_exits) },
130         { "mmio_exits", VCPU_STAT(mmio_exits) },
131         { "signal_exits", VCPU_STAT(signal_exits) },
132         { "irq_window", VCPU_STAT(irq_window_exits) },
133         { "nmi_window", VCPU_STAT(nmi_window_exits) },
134         { "halt_exits", VCPU_STAT(halt_exits) },
135         { "halt_wakeup", VCPU_STAT(halt_wakeup) },
136         { "hypercalls", VCPU_STAT(hypercalls) },
137         { "request_irq", VCPU_STAT(request_irq_exits) },
138         { "irq_exits", VCPU_STAT(irq_exits) },
139         { "host_state_reload", VCPU_STAT(host_state_reload) },
140         { "efer_reload", VCPU_STAT(efer_reload) },
141         { "fpu_reload", VCPU_STAT(fpu_reload) },
142         { "insn_emulation", VCPU_STAT(insn_emulation) },
143         { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
144         { "irq_injections", VCPU_STAT(irq_injections) },
145         { "nmi_injections", VCPU_STAT(nmi_injections) },
146         { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
147         { "mmu_pte_write", VM_STAT(mmu_pte_write) },
148         { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
149         { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
150         { "mmu_flooded", VM_STAT(mmu_flooded) },
151         { "mmu_recycled", VM_STAT(mmu_recycled) },
152         { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
153         { "mmu_unsync", VM_STAT(mmu_unsync) },
154         { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
155         { "largepages", VM_STAT(lpages) },
156         { NULL }
157 };
158
159 u64 __read_mostly host_xcr0;
160
161 int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
162
163 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
164 {
165         int i;
166         for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
167                 vcpu->arch.apf.gfns[i] = ~0;
168 }
169
170 static void kvm_on_user_return(struct user_return_notifier *urn)
171 {
172         unsigned slot;
173         struct kvm_shared_msrs *locals
174                 = container_of(urn, struct kvm_shared_msrs, urn);
175         struct kvm_shared_msr_values *values;
176
177         for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
178                 values = &locals->values[slot];
179                 if (values->host != values->curr) {
180                         wrmsrl(shared_msrs_global.msrs[slot], values->host);
181                         values->curr = values->host;
182                 }
183         }
184         locals->registered = false;
185         user_return_notifier_unregister(urn);
186 }
187
188 static void shared_msr_update(unsigned slot, u32 msr)
189 {
190         struct kvm_shared_msrs *smsr;
191         u64 value;
192
193         smsr = &__get_cpu_var(shared_msrs);
194         /* only read, and nobody should modify it at this time,
195          * so don't need lock */
196         if (slot >= shared_msrs_global.nr) {
197                 printk(KERN_ERR "kvm: invalid MSR slot!");
198                 return;
199         }
200         rdmsrl_safe(msr, &value);
201         smsr->values[slot].host = value;
202         smsr->values[slot].curr = value;
203 }
204
205 void kvm_define_shared_msr(unsigned slot, u32 msr)
206 {
207         if (slot >= shared_msrs_global.nr)
208                 shared_msrs_global.nr = slot + 1;
209         shared_msrs_global.msrs[slot] = msr;
210         /* we need ensured the shared_msr_global have been updated */
211         smp_wmb();
212 }
213 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
214
215 static void kvm_shared_msr_cpu_online(void)
216 {
217         unsigned i;
218
219         for (i = 0; i < shared_msrs_global.nr; ++i)
220                 shared_msr_update(i, shared_msrs_global.msrs[i]);
221 }
222
223 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
224 {
225         struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
226
227         if (((value ^ smsr->values[slot].curr) & mask) == 0)
228                 return;
229         smsr->values[slot].curr = value;
230         wrmsrl(shared_msrs_global.msrs[slot], value);
231         if (!smsr->registered) {
232                 smsr->urn.on_user_return = kvm_on_user_return;
233                 user_return_notifier_register(&smsr->urn);
234                 smsr->registered = true;
235         }
236 }
237 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
238
239 static void drop_user_return_notifiers(void *ignore)
240 {
241         struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
242
243         if (smsr->registered)
244                 kvm_on_user_return(&smsr->urn);
245 }
246
247 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
248 {
249         return vcpu->arch.apic_base;
250 }
251 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
252
253 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
254 {
255         /* TODO: reserve bits check */
256         kvm_lapic_set_base(vcpu, data);
257 }
258 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
259
260 #define EXCPT_BENIGN            0
261 #define EXCPT_CONTRIBUTORY      1
262 #define EXCPT_PF                2
263
264 static int exception_class(int vector)
265 {
266         switch (vector) {
267         case PF_VECTOR:
268                 return EXCPT_PF;
269         case DE_VECTOR:
270         case TS_VECTOR:
271         case NP_VECTOR:
272         case SS_VECTOR:
273         case GP_VECTOR:
274                 return EXCPT_CONTRIBUTORY;
275         default:
276                 break;
277         }
278         return EXCPT_BENIGN;
279 }
280
281 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
282                 unsigned nr, bool has_error, u32 error_code,
283                 bool reinject)
284 {
285         u32 prev_nr;
286         int class1, class2;
287
288         kvm_make_request(KVM_REQ_EVENT, vcpu);
289
290         if (!vcpu->arch.exception.pending) {
291         queue:
292                 vcpu->arch.exception.pending = true;
293                 vcpu->arch.exception.has_error_code = has_error;
294                 vcpu->arch.exception.nr = nr;
295                 vcpu->arch.exception.error_code = error_code;
296                 vcpu->arch.exception.reinject = reinject;
297                 return;
298         }
299
300         /* to check exception */
301         prev_nr = vcpu->arch.exception.nr;
302         if (prev_nr == DF_VECTOR) {
303                 /* triple fault -> shutdown */
304                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
305                 return;
306         }
307         class1 = exception_class(prev_nr);
308         class2 = exception_class(nr);
309         if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
310                 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
311                 /* generate double fault per SDM Table 5-5 */
312                 vcpu->arch.exception.pending = true;
313                 vcpu->arch.exception.has_error_code = true;
314                 vcpu->arch.exception.nr = DF_VECTOR;
315                 vcpu->arch.exception.error_code = 0;
316         } else
317                 /* replace previous exception with a new one in a hope
318                    that instruction re-execution will regenerate lost
319                    exception */
320                 goto queue;
321 }
322
323 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
324 {
325         kvm_multiple_exception(vcpu, nr, false, 0, false);
326 }
327 EXPORT_SYMBOL_GPL(kvm_queue_exception);
328
329 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
330 {
331         kvm_multiple_exception(vcpu, nr, false, 0, true);
332 }
333 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
334
335 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
336 {
337         if (err)
338                 kvm_inject_gp(vcpu, 0);
339         else
340                 kvm_x86_ops->skip_emulated_instruction(vcpu);
341 }
342 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
343
344 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
345 {
346         ++vcpu->stat.pf_guest;
347         vcpu->arch.cr2 = fault->address;
348         kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
349 }
350 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
351
352 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
353 {
354         if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
355                 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
356         else
357                 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
358 }
359
360 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
361 {
362         atomic_inc(&vcpu->arch.nmi_queued);
363         kvm_make_request(KVM_REQ_NMI, vcpu);
364 }
365 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
366
367 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
368 {
369         kvm_multiple_exception(vcpu, nr, true, error_code, false);
370 }
371 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
372
373 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
374 {
375         kvm_multiple_exception(vcpu, nr, true, error_code, true);
376 }
377 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
378
379 /*
380  * Checks if cpl <= required_cpl; if true, return true.  Otherwise queue
381  * a #GP and return false.
382  */
383 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
384 {
385         if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
386                 return true;
387         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
388         return false;
389 }
390 EXPORT_SYMBOL_GPL(kvm_require_cpl);
391
392 /*
393  * This function will be used to read from the physical memory of the currently
394  * running guest. The difference to kvm_read_guest_page is that this function
395  * can read from guest physical or from the guest's guest physical memory.
396  */
397 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
398                             gfn_t ngfn, void *data, int offset, int len,
399                             u32 access)
400 {
401         gfn_t real_gfn;
402         gpa_t ngpa;
403
404         ngpa     = gfn_to_gpa(ngfn);
405         real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
406         if (real_gfn == UNMAPPED_GVA)
407                 return -EFAULT;
408
409         real_gfn = gpa_to_gfn(real_gfn);
410
411         return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
412 }
413 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
414
415 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
416                                void *data, int offset, int len, u32 access)
417 {
418         return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
419                                        data, offset, len, access);
420 }
421
422 /*
423  * Load the pae pdptrs.  Return true is they are all valid.
424  */
425 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
426 {
427         gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
428         unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
429         int i;
430         int ret;
431         u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
432
433         ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
434                                       offset * sizeof(u64), sizeof(pdpte),
435                                       PFERR_USER_MASK|PFERR_WRITE_MASK);
436         if (ret < 0) {
437                 ret = 0;
438                 goto out;
439         }
440         for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
441                 if (is_present_gpte(pdpte[i]) &&
442                     (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
443                         ret = 0;
444                         goto out;
445                 }
446         }
447         ret = 1;
448
449         memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
450         __set_bit(VCPU_EXREG_PDPTR,
451                   (unsigned long *)&vcpu->arch.regs_avail);
452         __set_bit(VCPU_EXREG_PDPTR,
453                   (unsigned long *)&vcpu->arch.regs_dirty);
454 out:
455
456         return ret;
457 }
458 EXPORT_SYMBOL_GPL(load_pdptrs);
459
460 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
461 {
462         u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
463         bool changed = true;
464         int offset;
465         gfn_t gfn;
466         int r;
467
468         if (is_long_mode(vcpu) || !is_pae(vcpu))
469                 return false;
470
471         if (!test_bit(VCPU_EXREG_PDPTR,
472                       (unsigned long *)&vcpu->arch.regs_avail))
473                 return true;
474
475         gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
476         offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
477         r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
478                                        PFERR_USER_MASK | PFERR_WRITE_MASK);
479         if (r < 0)
480                 goto out;
481         changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
482 out:
483
484         return changed;
485 }
486
487 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
488 {
489         unsigned long old_cr0 = kvm_read_cr0(vcpu);
490         unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
491                                     X86_CR0_CD | X86_CR0_NW;
492
493         cr0 |= X86_CR0_ET;
494
495 #ifdef CONFIG_X86_64
496         if (cr0 & 0xffffffff00000000UL)
497                 return 1;
498 #endif
499
500         cr0 &= ~CR0_RESERVED_BITS;
501
502         if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
503                 return 1;
504
505         if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
506                 return 1;
507
508         if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
509 #ifdef CONFIG_X86_64
510                 if ((vcpu->arch.efer & EFER_LME)) {
511                         int cs_db, cs_l;
512
513                         if (!is_pae(vcpu))
514                                 return 1;
515                         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
516                         if (cs_l)
517                                 return 1;
518                 } else
519 #endif
520                 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
521                                                  kvm_read_cr3(vcpu)))
522                         return 1;
523         }
524
525         if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
526                 return 1;
527
528         kvm_x86_ops->set_cr0(vcpu, cr0);
529
530         if ((cr0 ^ old_cr0) & X86_CR0_PG) {
531                 kvm_clear_async_pf_completion_queue(vcpu);
532                 kvm_async_pf_hash_reset(vcpu);
533         }
534
535         if ((cr0 ^ old_cr0) & update_bits)
536                 kvm_mmu_reset_context(vcpu);
537         return 0;
538 }
539 EXPORT_SYMBOL_GPL(kvm_set_cr0);
540
541 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
542 {
543         (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
544 }
545 EXPORT_SYMBOL_GPL(kvm_lmsw);
546
547 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
548 {
549         u64 xcr0;
550
551         /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now  */
552         if (index != XCR_XFEATURE_ENABLED_MASK)
553                 return 1;
554         xcr0 = xcr;
555         if (kvm_x86_ops->get_cpl(vcpu) != 0)
556                 return 1;
557         if (!(xcr0 & XSTATE_FP))
558                 return 1;
559         if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
560                 return 1;
561         if (xcr0 & ~host_xcr0)
562                 return 1;
563         vcpu->arch.xcr0 = xcr0;
564         vcpu->guest_xcr0_loaded = 0;
565         return 0;
566 }
567
568 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
569 {
570         if (__kvm_set_xcr(vcpu, index, xcr)) {
571                 kvm_inject_gp(vcpu, 0);
572                 return 1;
573         }
574         return 0;
575 }
576 EXPORT_SYMBOL_GPL(kvm_set_xcr);
577
578 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
579 {
580         unsigned long old_cr4 = kvm_read_cr4(vcpu);
581         unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
582                                    X86_CR4_PAE | X86_CR4_SMEP;
583         if (cr4 & CR4_RESERVED_BITS)
584                 return 1;
585
586         if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
587                 return 1;
588
589         if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
590                 return 1;
591
592         if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
593                 return 1;
594
595         if (is_long_mode(vcpu)) {
596                 if (!(cr4 & X86_CR4_PAE))
597                         return 1;
598         } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
599                    && ((cr4 ^ old_cr4) & pdptr_bits)
600                    && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
601                                    kvm_read_cr3(vcpu)))
602                 return 1;
603
604         if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
605                 if (!guest_cpuid_has_pcid(vcpu))
606                         return 1;
607
608                 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
609                 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
610                         return 1;
611         }
612
613         if (kvm_x86_ops->set_cr4(vcpu, cr4))
614                 return 1;
615
616         if (((cr4 ^ old_cr4) & pdptr_bits) ||
617             (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
618                 kvm_mmu_reset_context(vcpu);
619
620         if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
621                 kvm_update_cpuid(vcpu);
622
623         return 0;
624 }
625 EXPORT_SYMBOL_GPL(kvm_set_cr4);
626
627 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
628 {
629         if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
630                 kvm_mmu_sync_roots(vcpu);
631                 kvm_mmu_flush_tlb(vcpu);
632                 return 0;
633         }
634
635         if (is_long_mode(vcpu)) {
636                 if (kvm_read_cr4(vcpu) & X86_CR4_PCIDE) {
637                         if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
638                                 return 1;
639                 } else
640                         if (cr3 & CR3_L_MODE_RESERVED_BITS)
641                                 return 1;
642         } else {
643                 if (is_pae(vcpu)) {
644                         if (cr3 & CR3_PAE_RESERVED_BITS)
645                                 return 1;
646                         if (is_paging(vcpu) &&
647                             !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
648                                 return 1;
649                 }
650                 /*
651                  * We don't check reserved bits in nonpae mode, because
652                  * this isn't enforced, and VMware depends on this.
653                  */
654         }
655
656         /*
657          * Does the new cr3 value map to physical memory? (Note, we
658          * catch an invalid cr3 even in real-mode, because it would
659          * cause trouble later on when we turn on paging anyway.)
660          *
661          * A real CPU would silently accept an invalid cr3 and would
662          * attempt to use it - with largely undefined (and often hard
663          * to debug) behavior on the guest side.
664          */
665         if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
666                 return 1;
667         vcpu->arch.cr3 = cr3;
668         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
669         vcpu->arch.mmu.new_cr3(vcpu);
670         return 0;
671 }
672 EXPORT_SYMBOL_GPL(kvm_set_cr3);
673
674 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
675 {
676         if (cr8 & CR8_RESERVED_BITS)
677                 return 1;
678         if (irqchip_in_kernel(vcpu->kvm))
679                 kvm_lapic_set_tpr(vcpu, cr8);
680         else
681                 vcpu->arch.cr8 = cr8;
682         return 0;
683 }
684 EXPORT_SYMBOL_GPL(kvm_set_cr8);
685
686 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
687 {
688         if (irqchip_in_kernel(vcpu->kvm))
689                 return kvm_lapic_get_cr8(vcpu);
690         else
691                 return vcpu->arch.cr8;
692 }
693 EXPORT_SYMBOL_GPL(kvm_get_cr8);
694
695 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
696 {
697         switch (dr) {
698         case 0 ... 3:
699                 vcpu->arch.db[dr] = val;
700                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
701                         vcpu->arch.eff_db[dr] = val;
702                 break;
703         case 4:
704                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
705                         return 1; /* #UD */
706                 /* fall through */
707         case 6:
708                 if (val & 0xffffffff00000000ULL)
709                         return -1; /* #GP */
710                 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
711                 break;
712         case 5:
713                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
714                         return 1; /* #UD */
715                 /* fall through */
716         default: /* 7 */
717                 if (val & 0xffffffff00000000ULL)
718                         return -1; /* #GP */
719                 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
720                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
721                         kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
722                         vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
723                 }
724                 break;
725         }
726
727         return 0;
728 }
729
730 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
731 {
732         int res;
733
734         res = __kvm_set_dr(vcpu, dr, val);
735         if (res > 0)
736                 kvm_queue_exception(vcpu, UD_VECTOR);
737         else if (res < 0)
738                 kvm_inject_gp(vcpu, 0);
739
740         return res;
741 }
742 EXPORT_SYMBOL_GPL(kvm_set_dr);
743
744 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
745 {
746         switch (dr) {
747         case 0 ... 3:
748                 *val = vcpu->arch.db[dr];
749                 break;
750         case 4:
751                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
752                         return 1;
753                 /* fall through */
754         case 6:
755                 *val = vcpu->arch.dr6;
756                 break;
757         case 5:
758                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
759                         return 1;
760                 /* fall through */
761         default: /* 7 */
762                 *val = vcpu->arch.dr7;
763                 break;
764         }
765
766         return 0;
767 }
768
769 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
770 {
771         if (_kvm_get_dr(vcpu, dr, val)) {
772                 kvm_queue_exception(vcpu, UD_VECTOR);
773                 return 1;
774         }
775         return 0;
776 }
777 EXPORT_SYMBOL_GPL(kvm_get_dr);
778
779 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
780 {
781         u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
782         u64 data;
783         int err;
784
785         err = kvm_pmu_read_pmc(vcpu, ecx, &data);
786         if (err)
787                 return err;
788         kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
789         kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
790         return err;
791 }
792 EXPORT_SYMBOL_GPL(kvm_rdpmc);
793
794 /*
795  * List of msr numbers which we expose to userspace through KVM_GET_MSRS
796  * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
797  *
798  * This list is modified at module load time to reflect the
799  * capabilities of the host cpu. This capabilities test skips MSRs that are
800  * kvm-specific. Those are put in the beginning of the list.
801  */
802
803 #define KVM_SAVE_MSRS_BEGIN     10
804 static u32 msrs_to_save[] = {
805         MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
806         MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
807         HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
808         HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
809         MSR_KVM_PV_EOI_EN,
810         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
811         MSR_STAR,
812 #ifdef CONFIG_X86_64
813         MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
814 #endif
815         MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
816 };
817
818 static unsigned num_msrs_to_save;
819
820 static u32 emulated_msrs[] = {
821         MSR_IA32_TSCDEADLINE,
822         MSR_IA32_MISC_ENABLE,
823         MSR_IA32_MCG_STATUS,
824         MSR_IA32_MCG_CTL,
825 };
826
827 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
828 {
829         u64 old_efer = vcpu->arch.efer;
830
831         if (efer & efer_reserved_bits)
832                 return 1;
833
834         if (is_paging(vcpu)
835             && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
836                 return 1;
837
838         if (efer & EFER_FFXSR) {
839                 struct kvm_cpuid_entry2 *feat;
840
841                 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
842                 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
843                         return 1;
844         }
845
846         if (efer & EFER_SVME) {
847                 struct kvm_cpuid_entry2 *feat;
848
849                 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
850                 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
851                         return 1;
852         }
853
854         efer &= ~EFER_LMA;
855         efer |= vcpu->arch.efer & EFER_LMA;
856
857         kvm_x86_ops->set_efer(vcpu, efer);
858
859         vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
860
861         /* Update reserved bits */
862         if ((efer ^ old_efer) & EFER_NX)
863                 kvm_mmu_reset_context(vcpu);
864
865         return 0;
866 }
867
868 void kvm_enable_efer_bits(u64 mask)
869 {
870        efer_reserved_bits &= ~mask;
871 }
872 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
873
874
875 /*
876  * Writes msr value into into the appropriate "register".
877  * Returns 0 on success, non-0 otherwise.
878  * Assumes vcpu_load() was already called.
879  */
880 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
881 {
882         return kvm_x86_ops->set_msr(vcpu, msr_index, data);
883 }
884
885 /*
886  * Adapt set_msr() to msr_io()'s calling convention
887  */
888 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
889 {
890         return kvm_set_msr(vcpu, index, *data);
891 }
892
893 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
894 {
895         int version;
896         int r;
897         struct pvclock_wall_clock wc;
898         struct timespec boot;
899
900         if (!wall_clock)
901                 return;
902
903         r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
904         if (r)
905                 return;
906
907         if (version & 1)
908                 ++version;  /* first time write, random junk */
909
910         ++version;
911
912         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
913
914         /*
915          * The guest calculates current wall clock time by adding
916          * system time (updated by kvm_guest_time_update below) to the
917          * wall clock specified here.  guest system time equals host
918          * system time for us, thus we must fill in host boot time here.
919          */
920         getboottime(&boot);
921
922         if (kvm->arch.kvmclock_offset) {
923                 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
924                 boot = timespec_sub(boot, ts);
925         }
926         wc.sec = boot.tv_sec;
927         wc.nsec = boot.tv_nsec;
928         wc.version = version;
929
930         kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
931
932         version++;
933         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
934 }
935
936 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
937 {
938         uint32_t quotient, remainder;
939
940         /* Don't try to replace with do_div(), this one calculates
941          * "(dividend << 32) / divisor" */
942         __asm__ ( "divl %4"
943                   : "=a" (quotient), "=d" (remainder)
944                   : "0" (0), "1" (dividend), "r" (divisor) );
945         return quotient;
946 }
947
948 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
949                                s8 *pshift, u32 *pmultiplier)
950 {
951         uint64_t scaled64;
952         int32_t  shift = 0;
953         uint64_t tps64;
954         uint32_t tps32;
955
956         tps64 = base_khz * 1000LL;
957         scaled64 = scaled_khz * 1000LL;
958         while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
959                 tps64 >>= 1;
960                 shift--;
961         }
962
963         tps32 = (uint32_t)tps64;
964         while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
965                 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
966                         scaled64 >>= 1;
967                 else
968                         tps32 <<= 1;
969                 shift++;
970         }
971
972         *pshift = shift;
973         *pmultiplier = div_frac(scaled64, tps32);
974
975         pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
976                  __func__, base_khz, scaled_khz, shift, *pmultiplier);
977 }
978
979 static inline u64 get_kernel_ns(void)
980 {
981         struct timespec ts;
982
983         WARN_ON(preemptible());
984         ktime_get_ts(&ts);
985         monotonic_to_bootbased(&ts);
986         return timespec_to_ns(&ts);
987 }
988
989 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
990 unsigned long max_tsc_khz;
991
992 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
993 {
994         return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
995                                    vcpu->arch.virtual_tsc_shift);
996 }
997
998 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
999 {
1000         u64 v = (u64)khz * (1000000 + ppm);
1001         do_div(v, 1000000);
1002         return v;
1003 }
1004
1005 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1006 {
1007         u32 thresh_lo, thresh_hi;
1008         int use_scaling = 0;
1009
1010         /* Compute a scale to convert nanoseconds in TSC cycles */
1011         kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1012                            &vcpu->arch.virtual_tsc_shift,
1013                            &vcpu->arch.virtual_tsc_mult);
1014         vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1015
1016         /*
1017          * Compute the variation in TSC rate which is acceptable
1018          * within the range of tolerance and decide if the
1019          * rate being applied is within that bounds of the hardware
1020          * rate.  If so, no scaling or compensation need be done.
1021          */
1022         thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1023         thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1024         if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1025                 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1026                 use_scaling = 1;
1027         }
1028         kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1029 }
1030
1031 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1032 {
1033         u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1034                                       vcpu->arch.virtual_tsc_mult,
1035                                       vcpu->arch.virtual_tsc_shift);
1036         tsc += vcpu->arch.this_tsc_write;
1037         return tsc;
1038 }
1039
1040 void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1041 {
1042         struct kvm *kvm = vcpu->kvm;
1043         u64 offset, ns, elapsed;
1044         unsigned long flags;
1045         s64 usdiff;
1046
1047         raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1048         offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1049         ns = get_kernel_ns();
1050         elapsed = ns - kvm->arch.last_tsc_nsec;
1051
1052         /* n.b - signed multiplication and division required */
1053         usdiff = data - kvm->arch.last_tsc_write;
1054 #ifdef CONFIG_X86_64
1055         usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1056 #else
1057         /* do_div() only does unsigned */
1058         asm("idivl %2; xor %%edx, %%edx"
1059             : "=A"(usdiff)
1060             : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
1061 #endif
1062         do_div(elapsed, 1000);
1063         usdiff -= elapsed;
1064         if (usdiff < 0)
1065                 usdiff = -usdiff;
1066
1067         /*
1068          * Special case: TSC write with a small delta (1 second) of virtual
1069          * cycle time against real time is interpreted as an attempt to
1070          * synchronize the CPU.
1071          *
1072          * For a reliable TSC, we can match TSC offsets, and for an unstable
1073          * TSC, we add elapsed time in this computation.  We could let the
1074          * compensation code attempt to catch up if we fall behind, but
1075          * it's better to try to match offsets from the beginning.
1076          */
1077         if (usdiff < USEC_PER_SEC &&
1078             vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1079                 if (!check_tsc_unstable()) {
1080                         offset = kvm->arch.cur_tsc_offset;
1081                         pr_debug("kvm: matched tsc offset for %llu\n", data);
1082                 } else {
1083                         u64 delta = nsec_to_cycles(vcpu, elapsed);
1084                         data += delta;
1085                         offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1086                         pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1087                 }
1088         } else {
1089                 /*
1090                  * We split periods of matched TSC writes into generations.
1091                  * For each generation, we track the original measured
1092                  * nanosecond time, offset, and write, so if TSCs are in
1093                  * sync, we can match exact offset, and if not, we can match
1094                  * exact software computation in compute_guest_tsc()
1095                  *
1096                  * These values are tracked in kvm->arch.cur_xxx variables.
1097                  */
1098                 kvm->arch.cur_tsc_generation++;
1099                 kvm->arch.cur_tsc_nsec = ns;
1100                 kvm->arch.cur_tsc_write = data;
1101                 kvm->arch.cur_tsc_offset = offset;
1102                 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1103                          kvm->arch.cur_tsc_generation, data);
1104         }
1105
1106         /*
1107          * We also track th most recent recorded KHZ, write and time to
1108          * allow the matching interval to be extended at each write.
1109          */
1110         kvm->arch.last_tsc_nsec = ns;
1111         kvm->arch.last_tsc_write = data;
1112         kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1113
1114         /* Reset of TSC must disable overshoot protection below */
1115         vcpu->arch.hv_clock.tsc_timestamp = 0;
1116         vcpu->arch.last_guest_tsc = data;
1117
1118         /* Keep track of which generation this VCPU has synchronized to */
1119         vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1120         vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1121         vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1122
1123         kvm_x86_ops->write_tsc_offset(vcpu, offset);
1124         raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1125 }
1126
1127 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1128
1129 static int kvm_guest_time_update(struct kvm_vcpu *v)
1130 {
1131         unsigned long flags;
1132         struct kvm_vcpu_arch *vcpu = &v->arch;
1133         void *shared_kaddr;
1134         unsigned long this_tsc_khz;
1135         s64 kernel_ns, max_kernel_ns;
1136         u64 tsc_timestamp;
1137
1138         /* Keep irq disabled to prevent changes to the clock */
1139         local_irq_save(flags);
1140         tsc_timestamp = kvm_x86_ops->read_l1_tsc(v);
1141         kernel_ns = get_kernel_ns();
1142         this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1143         if (unlikely(this_tsc_khz == 0)) {
1144                 local_irq_restore(flags);
1145                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1146                 return 1;
1147         }
1148
1149         /*
1150          * We may have to catch up the TSC to match elapsed wall clock
1151          * time for two reasons, even if kvmclock is used.
1152          *   1) CPU could have been running below the maximum TSC rate
1153          *   2) Broken TSC compensation resets the base at each VCPU
1154          *      entry to avoid unknown leaps of TSC even when running
1155          *      again on the same CPU.  This may cause apparent elapsed
1156          *      time to disappear, and the guest to stand still or run
1157          *      very slowly.
1158          */
1159         if (vcpu->tsc_catchup) {
1160                 u64 tsc = compute_guest_tsc(v, kernel_ns);
1161                 if (tsc > tsc_timestamp) {
1162                         adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1163                         tsc_timestamp = tsc;
1164                 }
1165         }
1166
1167         local_irq_restore(flags);
1168
1169         if (!vcpu->time_page)
1170                 return 0;
1171
1172         /*
1173          * Time as measured by the TSC may go backwards when resetting the base
1174          * tsc_timestamp.  The reason for this is that the TSC resolution is
1175          * higher than the resolution of the other clock scales.  Thus, many
1176          * possible measurments of the TSC correspond to one measurement of any
1177          * other clock, and so a spread of values is possible.  This is not a
1178          * problem for the computation of the nanosecond clock; with TSC rates
1179          * around 1GHZ, there can only be a few cycles which correspond to one
1180          * nanosecond value, and any path through this code will inevitably
1181          * take longer than that.  However, with the kernel_ns value itself,
1182          * the precision may be much lower, down to HZ granularity.  If the
1183          * first sampling of TSC against kernel_ns ends in the low part of the
1184          * range, and the second in the high end of the range, we can get:
1185          *
1186          * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1187          *
1188          * As the sampling errors potentially range in the thousands of cycles,
1189          * it is possible such a time value has already been observed by the
1190          * guest.  To protect against this, we must compute the system time as
1191          * observed by the guest and ensure the new system time is greater.
1192          */
1193         max_kernel_ns = 0;
1194         if (vcpu->hv_clock.tsc_timestamp) {
1195                 max_kernel_ns = vcpu->last_guest_tsc -
1196                                 vcpu->hv_clock.tsc_timestamp;
1197                 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1198                                     vcpu->hv_clock.tsc_to_system_mul,
1199                                     vcpu->hv_clock.tsc_shift);
1200                 max_kernel_ns += vcpu->last_kernel_ns;
1201         }
1202
1203         if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1204                 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1205                                    &vcpu->hv_clock.tsc_shift,
1206                                    &vcpu->hv_clock.tsc_to_system_mul);
1207                 vcpu->hw_tsc_khz = this_tsc_khz;
1208         }
1209
1210         if (max_kernel_ns > kernel_ns)
1211                 kernel_ns = max_kernel_ns;
1212
1213         /* With all the info we got, fill in the values */
1214         vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1215         vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1216         vcpu->last_kernel_ns = kernel_ns;
1217         vcpu->last_guest_tsc = tsc_timestamp;
1218         vcpu->hv_clock.flags = 0;
1219
1220         /*
1221          * The interface expects us to write an even number signaling that the
1222          * update is finished. Since the guest won't see the intermediate
1223          * state, we just increase by 2 at the end.
1224          */
1225         vcpu->hv_clock.version += 2;
1226
1227         shared_kaddr = kmap_atomic(vcpu->time_page);
1228
1229         memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
1230                sizeof(vcpu->hv_clock));
1231
1232         kunmap_atomic(shared_kaddr);
1233
1234         mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
1235         return 0;
1236 }
1237
1238 static bool msr_mtrr_valid(unsigned msr)
1239 {
1240         switch (msr) {
1241         case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1242         case MSR_MTRRfix64K_00000:
1243         case MSR_MTRRfix16K_80000:
1244         case MSR_MTRRfix16K_A0000:
1245         case MSR_MTRRfix4K_C0000:
1246         case MSR_MTRRfix4K_C8000:
1247         case MSR_MTRRfix4K_D0000:
1248         case MSR_MTRRfix4K_D8000:
1249         case MSR_MTRRfix4K_E0000:
1250         case MSR_MTRRfix4K_E8000:
1251         case MSR_MTRRfix4K_F0000:
1252         case MSR_MTRRfix4K_F8000:
1253         case MSR_MTRRdefType:
1254         case MSR_IA32_CR_PAT:
1255                 return true;
1256         case 0x2f8:
1257                 return true;
1258         }
1259         return false;
1260 }
1261
1262 static bool valid_pat_type(unsigned t)
1263 {
1264         return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1265 }
1266
1267 static bool valid_mtrr_type(unsigned t)
1268 {
1269         return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1270 }
1271
1272 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1273 {
1274         int i;
1275
1276         if (!msr_mtrr_valid(msr))
1277                 return false;
1278
1279         if (msr == MSR_IA32_CR_PAT) {
1280                 for (i = 0; i < 8; i++)
1281                         if (!valid_pat_type((data >> (i * 8)) & 0xff))
1282                                 return false;
1283                 return true;
1284         } else if (msr == MSR_MTRRdefType) {
1285                 if (data & ~0xcff)
1286                         return false;
1287                 return valid_mtrr_type(data & 0xff);
1288         } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1289                 for (i = 0; i < 8 ; i++)
1290                         if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1291                                 return false;
1292                 return true;
1293         }
1294
1295         /* variable MTRRs */
1296         return valid_mtrr_type(data & 0xff);
1297 }
1298
1299 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1300 {
1301         u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1302
1303         if (!mtrr_valid(vcpu, msr, data))
1304                 return 1;
1305
1306         if (msr == MSR_MTRRdefType) {
1307                 vcpu->arch.mtrr_state.def_type = data;
1308                 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1309         } else if (msr == MSR_MTRRfix64K_00000)
1310                 p[0] = data;
1311         else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1312                 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1313         else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1314                 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1315         else if (msr == MSR_IA32_CR_PAT)
1316                 vcpu->arch.pat = data;
1317         else {  /* Variable MTRRs */
1318                 int idx, is_mtrr_mask;
1319                 u64 *pt;
1320
1321                 idx = (msr - 0x200) / 2;
1322                 is_mtrr_mask = msr - 0x200 - 2 * idx;
1323                 if (!is_mtrr_mask)
1324                         pt =
1325                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1326                 else
1327                         pt =
1328                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1329                 *pt = data;
1330         }
1331
1332         kvm_mmu_reset_context(vcpu);
1333         return 0;
1334 }
1335
1336 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1337 {
1338         u64 mcg_cap = vcpu->arch.mcg_cap;
1339         unsigned bank_num = mcg_cap & 0xff;
1340
1341         switch (msr) {
1342         case MSR_IA32_MCG_STATUS:
1343                 vcpu->arch.mcg_status = data;
1344                 break;
1345         case MSR_IA32_MCG_CTL:
1346                 if (!(mcg_cap & MCG_CTL_P))
1347                         return 1;
1348                 if (data != 0 && data != ~(u64)0)
1349                         return -1;
1350                 vcpu->arch.mcg_ctl = data;
1351                 break;
1352         default:
1353                 if (msr >= MSR_IA32_MC0_CTL &&
1354                     msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1355                         u32 offset = msr - MSR_IA32_MC0_CTL;
1356                         /* only 0 or all 1s can be written to IA32_MCi_CTL
1357                          * some Linux kernels though clear bit 10 in bank 4 to
1358                          * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1359                          * this to avoid an uncatched #GP in the guest
1360                          */
1361                         if ((offset & 0x3) == 0 &&
1362                             data != 0 && (data | (1 << 10)) != ~(u64)0)
1363                                 return -1;
1364                         vcpu->arch.mce_banks[offset] = data;
1365                         break;
1366                 }
1367                 return 1;
1368         }
1369         return 0;
1370 }
1371
1372 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1373 {
1374         struct kvm *kvm = vcpu->kvm;
1375         int lm = is_long_mode(vcpu);
1376         u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1377                 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1378         u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1379                 : kvm->arch.xen_hvm_config.blob_size_32;
1380         u32 page_num = data & ~PAGE_MASK;
1381         u64 page_addr = data & PAGE_MASK;
1382         u8 *page;
1383         int r;
1384
1385         r = -E2BIG;
1386         if (page_num >= blob_size)
1387                 goto out;
1388         r = -ENOMEM;
1389         page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1390         if (IS_ERR(page)) {
1391                 r = PTR_ERR(page);
1392                 goto out;
1393         }
1394         if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1395                 goto out_free;
1396         r = 0;
1397 out_free:
1398         kfree(page);
1399 out:
1400         return r;
1401 }
1402
1403 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1404 {
1405         return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1406 }
1407
1408 static bool kvm_hv_msr_partition_wide(u32 msr)
1409 {
1410         bool r = false;
1411         switch (msr) {
1412         case HV_X64_MSR_GUEST_OS_ID:
1413         case HV_X64_MSR_HYPERCALL:
1414                 r = true;
1415                 break;
1416         }
1417
1418         return r;
1419 }
1420
1421 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1422 {
1423         struct kvm *kvm = vcpu->kvm;
1424
1425         switch (msr) {
1426         case HV_X64_MSR_GUEST_OS_ID:
1427                 kvm->arch.hv_guest_os_id = data;
1428                 /* setting guest os id to zero disables hypercall page */
1429                 if (!kvm->arch.hv_guest_os_id)
1430                         kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1431                 break;
1432         case HV_X64_MSR_HYPERCALL: {
1433                 u64 gfn;
1434                 unsigned long addr;
1435                 u8 instructions[4];
1436
1437                 /* if guest os id is not set hypercall should remain disabled */
1438                 if (!kvm->arch.hv_guest_os_id)
1439                         break;
1440                 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1441                         kvm->arch.hv_hypercall = data;
1442                         break;
1443                 }
1444                 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1445                 addr = gfn_to_hva(kvm, gfn);
1446                 if (kvm_is_error_hva(addr))
1447                         return 1;
1448                 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1449                 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1450                 if (__copy_to_user((void __user *)addr, instructions, 4))
1451                         return 1;
1452                 kvm->arch.hv_hypercall = data;
1453                 break;
1454         }
1455         default:
1456                 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1457                             "data 0x%llx\n", msr, data);
1458                 return 1;
1459         }
1460         return 0;
1461 }
1462
1463 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1464 {
1465         switch (msr) {
1466         case HV_X64_MSR_APIC_ASSIST_PAGE: {
1467                 unsigned long addr;
1468
1469                 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1470                         vcpu->arch.hv_vapic = data;
1471                         break;
1472                 }
1473                 addr = gfn_to_hva(vcpu->kvm, data >>
1474                                   HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1475                 if (kvm_is_error_hva(addr))
1476                         return 1;
1477                 if (__clear_user((void __user *)addr, PAGE_SIZE))
1478                         return 1;
1479                 vcpu->arch.hv_vapic = data;
1480                 break;
1481         }
1482         case HV_X64_MSR_EOI:
1483                 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1484         case HV_X64_MSR_ICR:
1485                 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1486         case HV_X64_MSR_TPR:
1487                 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1488         default:
1489                 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1490                             "data 0x%llx\n", msr, data);
1491                 return 1;
1492         }
1493
1494         return 0;
1495 }
1496
1497 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1498 {
1499         gpa_t gpa = data & ~0x3f;
1500
1501         /* Bits 2:5 are reserved, Should be zero */
1502         if (data & 0x3c)
1503                 return 1;
1504
1505         vcpu->arch.apf.msr_val = data;
1506
1507         if (!(data & KVM_ASYNC_PF_ENABLED)) {
1508                 kvm_clear_async_pf_completion_queue(vcpu);
1509                 kvm_async_pf_hash_reset(vcpu);
1510                 return 0;
1511         }
1512
1513         if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1514                 return 1;
1515
1516         vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1517         kvm_async_pf_wakeup_all(vcpu);
1518         return 0;
1519 }
1520
1521 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1522 {
1523         if (vcpu->arch.time_page) {
1524                 kvm_release_page_dirty(vcpu->arch.time_page);
1525                 vcpu->arch.time_page = NULL;
1526         }
1527 }
1528
1529 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1530 {
1531         u64 delta;
1532
1533         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1534                 return;
1535
1536         delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1537         vcpu->arch.st.last_steal = current->sched_info.run_delay;
1538         vcpu->arch.st.accum_steal = delta;
1539 }
1540
1541 static void record_steal_time(struct kvm_vcpu *vcpu)
1542 {
1543         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1544                 return;
1545
1546         if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1547                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1548                 return;
1549
1550         vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1551         vcpu->arch.st.steal.version += 2;
1552         vcpu->arch.st.accum_steal = 0;
1553
1554         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1555                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1556 }
1557
1558 int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1559 {
1560         bool pr = false;
1561
1562         switch (msr) {
1563         case MSR_EFER:
1564                 return set_efer(vcpu, data);
1565         case MSR_K7_HWCR:
1566                 data &= ~(u64)0x40;     /* ignore flush filter disable */
1567                 data &= ~(u64)0x100;    /* ignore ignne emulation enable */
1568                 data &= ~(u64)0x8;      /* ignore TLB cache disable */
1569                 if (data != 0) {
1570                         vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1571                                     data);
1572                         return 1;
1573                 }
1574                 break;
1575         case MSR_FAM10H_MMIO_CONF_BASE:
1576                 if (data != 0) {
1577                         vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1578                                     "0x%llx\n", data);
1579                         return 1;
1580                 }
1581                 break;
1582         case MSR_AMD64_NB_CFG:
1583                 break;
1584         case MSR_IA32_DEBUGCTLMSR:
1585                 if (!data) {
1586                         /* We support the non-activated case already */
1587                         break;
1588                 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1589                         /* Values other than LBR and BTF are vendor-specific,
1590                            thus reserved and should throw a #GP */
1591                         return 1;
1592                 }
1593                 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1594                             __func__, data);
1595                 break;
1596         case MSR_IA32_UCODE_REV:
1597         case MSR_IA32_UCODE_WRITE:
1598         case MSR_VM_HSAVE_PA:
1599         case MSR_AMD64_PATCH_LOADER:
1600                 break;
1601         case 0x200 ... 0x2ff:
1602                 return set_msr_mtrr(vcpu, msr, data);
1603         case MSR_IA32_APICBASE:
1604                 kvm_set_apic_base(vcpu, data);
1605                 break;
1606         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1607                 return kvm_x2apic_msr_write(vcpu, msr, data);
1608         case MSR_IA32_TSCDEADLINE:
1609                 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1610                 break;
1611         case MSR_IA32_MISC_ENABLE:
1612                 vcpu->arch.ia32_misc_enable_msr = data;
1613                 break;
1614         case MSR_KVM_WALL_CLOCK_NEW:
1615         case MSR_KVM_WALL_CLOCK:
1616                 vcpu->kvm->arch.wall_clock = data;
1617                 kvm_write_wall_clock(vcpu->kvm, data);
1618                 break;
1619         case MSR_KVM_SYSTEM_TIME_NEW:
1620         case MSR_KVM_SYSTEM_TIME: {
1621                 kvmclock_reset(vcpu);
1622
1623                 vcpu->arch.time = data;
1624                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1625
1626                 /* we verify if the enable bit is set... */
1627                 if (!(data & 1))
1628                         break;
1629
1630                 /* ...but clean it before doing the actual write */
1631                 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1632
1633                 vcpu->arch.time_page =
1634                                 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
1635
1636                 if (is_error_page(vcpu->arch.time_page))
1637                         vcpu->arch.time_page = NULL;
1638
1639                 break;
1640         }
1641         case MSR_KVM_ASYNC_PF_EN:
1642                 if (kvm_pv_enable_async_pf(vcpu, data))
1643                         return 1;
1644                 break;
1645         case MSR_KVM_STEAL_TIME:
1646
1647                 if (unlikely(!sched_info_on()))
1648                         return 1;
1649
1650                 if (data & KVM_STEAL_RESERVED_MASK)
1651                         return 1;
1652
1653                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1654                                                         data & KVM_STEAL_VALID_BITS))
1655                         return 1;
1656
1657                 vcpu->arch.st.msr_val = data;
1658
1659                 if (!(data & KVM_MSR_ENABLED))
1660                         break;
1661
1662                 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1663
1664                 preempt_disable();
1665                 accumulate_steal_time(vcpu);
1666                 preempt_enable();
1667
1668                 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1669
1670                 break;
1671         case MSR_KVM_PV_EOI_EN:
1672                 if (kvm_lapic_enable_pv_eoi(vcpu, data))
1673                         return 1;
1674                 break;
1675
1676         case MSR_IA32_MCG_CTL:
1677         case MSR_IA32_MCG_STATUS:
1678         case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1679                 return set_msr_mce(vcpu, msr, data);
1680
1681         /* Performance counters are not protected by a CPUID bit,
1682          * so we should check all of them in the generic path for the sake of
1683          * cross vendor migration.
1684          * Writing a zero into the event select MSRs disables them,
1685          * which we perfectly emulate ;-). Any other value should be at least
1686          * reported, some guests depend on them.
1687          */
1688         case MSR_K7_EVNTSEL0:
1689         case MSR_K7_EVNTSEL1:
1690         case MSR_K7_EVNTSEL2:
1691         case MSR_K7_EVNTSEL3:
1692                 if (data != 0)
1693                         vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1694                                     "0x%x data 0x%llx\n", msr, data);
1695                 break;
1696         /* at least RHEL 4 unconditionally writes to the perfctr registers,
1697          * so we ignore writes to make it happy.
1698          */
1699         case MSR_K7_PERFCTR0:
1700         case MSR_K7_PERFCTR1:
1701         case MSR_K7_PERFCTR2:
1702         case MSR_K7_PERFCTR3:
1703                 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1704                             "0x%x data 0x%llx\n", msr, data);
1705                 break;
1706         case MSR_P6_PERFCTR0:
1707         case MSR_P6_PERFCTR1:
1708                 pr = true;
1709         case MSR_P6_EVNTSEL0:
1710         case MSR_P6_EVNTSEL1:
1711                 if (kvm_pmu_msr(vcpu, msr))
1712                         return kvm_pmu_set_msr(vcpu, msr, data);
1713
1714                 if (pr || data != 0)
1715                         vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
1716                                     "0x%x data 0x%llx\n", msr, data);
1717                 break;
1718         case MSR_K7_CLK_CTL:
1719                 /*
1720                  * Ignore all writes to this no longer documented MSR.
1721                  * Writes are only relevant for old K7 processors,
1722                  * all pre-dating SVM, but a recommended workaround from
1723                  * AMD for these chips. It is possible to specify the
1724                  * affected processor models on the command line, hence
1725                  * the need to ignore the workaround.
1726                  */
1727                 break;
1728         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1729                 if (kvm_hv_msr_partition_wide(msr)) {
1730                         int r;
1731                         mutex_lock(&vcpu->kvm->lock);
1732                         r = set_msr_hyperv_pw(vcpu, msr, data);
1733                         mutex_unlock(&vcpu->kvm->lock);
1734                         return r;
1735                 } else
1736                         return set_msr_hyperv(vcpu, msr, data);
1737                 break;
1738         case MSR_IA32_BBL_CR_CTL3:
1739                 /* Drop writes to this legacy MSR -- see rdmsr
1740                  * counterpart for further detail.
1741                  */
1742                 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
1743                 break;
1744         case MSR_AMD64_OSVW_ID_LENGTH:
1745                 if (!guest_cpuid_has_osvw(vcpu))
1746                         return 1;
1747                 vcpu->arch.osvw.length = data;
1748                 break;
1749         case MSR_AMD64_OSVW_STATUS:
1750                 if (!guest_cpuid_has_osvw(vcpu))
1751                         return 1;
1752                 vcpu->arch.osvw.status = data;
1753                 break;
1754         default:
1755                 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1756                         return xen_hvm_config(vcpu, data);
1757                 if (kvm_pmu_msr(vcpu, msr))
1758                         return kvm_pmu_set_msr(vcpu, msr, data);
1759                 if (!ignore_msrs) {
1760                         vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1761                                     msr, data);
1762                         return 1;
1763                 } else {
1764                         vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1765                                     msr, data);
1766                         break;
1767                 }
1768         }
1769         return 0;
1770 }
1771 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1772
1773
1774 /*
1775  * Reads an msr value (of 'msr_index') into 'pdata'.
1776  * Returns 0 on success, non-0 otherwise.
1777  * Assumes vcpu_load() was already called.
1778  */
1779 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1780 {
1781         return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1782 }
1783
1784 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1785 {
1786         u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1787
1788         if (!msr_mtrr_valid(msr))
1789                 return 1;
1790
1791         if (msr == MSR_MTRRdefType)
1792                 *pdata = vcpu->arch.mtrr_state.def_type +
1793                          (vcpu->arch.mtrr_state.enabled << 10);
1794         else if (msr == MSR_MTRRfix64K_00000)
1795                 *pdata = p[0];
1796         else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1797                 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1798         else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1799                 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1800         else if (msr == MSR_IA32_CR_PAT)
1801                 *pdata = vcpu->arch.pat;
1802         else {  /* Variable MTRRs */
1803                 int idx, is_mtrr_mask;
1804                 u64 *pt;
1805
1806                 idx = (msr - 0x200) / 2;
1807                 is_mtrr_mask = msr - 0x200 - 2 * idx;
1808                 if (!is_mtrr_mask)
1809                         pt =
1810                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1811                 else
1812                         pt =
1813                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1814                 *pdata = *pt;
1815         }
1816
1817         return 0;
1818 }
1819
1820 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1821 {
1822         u64 data;
1823         u64 mcg_cap = vcpu->arch.mcg_cap;
1824         unsigned bank_num = mcg_cap & 0xff;
1825
1826         switch (msr) {
1827         case MSR_IA32_P5_MC_ADDR:
1828         case MSR_IA32_P5_MC_TYPE:
1829                 data = 0;
1830                 break;
1831         case MSR_IA32_MCG_CAP:
1832                 data = vcpu->arch.mcg_cap;
1833                 break;
1834         case MSR_IA32_MCG_CTL:
1835                 if (!(mcg_cap & MCG_CTL_P))
1836                         return 1;
1837                 data = vcpu->arch.mcg_ctl;
1838                 break;
1839         case MSR_IA32_MCG_STATUS:
1840                 data = vcpu->arch.mcg_status;
1841                 break;
1842         default:
1843                 if (msr >= MSR_IA32_MC0_CTL &&
1844                     msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1845                         u32 offset = msr - MSR_IA32_MC0_CTL;
1846                         data = vcpu->arch.mce_banks[offset];
1847                         break;
1848                 }
1849                 return 1;
1850         }
1851         *pdata = data;
1852         return 0;
1853 }
1854
1855 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1856 {
1857         u64 data = 0;
1858         struct kvm *kvm = vcpu->kvm;
1859
1860         switch (msr) {
1861         case HV_X64_MSR_GUEST_OS_ID:
1862                 data = kvm->arch.hv_guest_os_id;
1863                 break;
1864         case HV_X64_MSR_HYPERCALL:
1865                 data = kvm->arch.hv_hypercall;
1866                 break;
1867         default:
1868                 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1869                 return 1;
1870         }
1871
1872         *pdata = data;
1873         return 0;
1874 }
1875
1876 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1877 {
1878         u64 data = 0;
1879
1880         switch (msr) {
1881         case HV_X64_MSR_VP_INDEX: {
1882                 int r;
1883                 struct kvm_vcpu *v;
1884                 kvm_for_each_vcpu(r, v, vcpu->kvm)
1885                         if (v == vcpu)
1886                                 data = r;
1887                 break;
1888         }
1889         case HV_X64_MSR_EOI:
1890                 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1891         case HV_X64_MSR_ICR:
1892                 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1893         case HV_X64_MSR_TPR:
1894                 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
1895         case HV_X64_MSR_APIC_ASSIST_PAGE:
1896                 data = vcpu->arch.hv_vapic;
1897                 break;
1898         default:
1899                 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1900                 return 1;
1901         }
1902         *pdata = data;
1903         return 0;
1904 }
1905
1906 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1907 {
1908         u64 data;
1909
1910         switch (msr) {
1911         case MSR_IA32_PLATFORM_ID:
1912         case MSR_IA32_EBL_CR_POWERON:
1913         case MSR_IA32_DEBUGCTLMSR:
1914         case MSR_IA32_LASTBRANCHFROMIP:
1915         case MSR_IA32_LASTBRANCHTOIP:
1916         case MSR_IA32_LASTINTFROMIP:
1917         case MSR_IA32_LASTINTTOIP:
1918         case MSR_K8_SYSCFG:
1919         case MSR_K7_HWCR:
1920         case MSR_VM_HSAVE_PA:
1921         case MSR_K7_EVNTSEL0:
1922         case MSR_K7_PERFCTR0:
1923         case MSR_K8_INT_PENDING_MSG:
1924         case MSR_AMD64_NB_CFG:
1925         case MSR_FAM10H_MMIO_CONF_BASE:
1926                 data = 0;
1927                 break;
1928         case MSR_P6_PERFCTR0:
1929         case MSR_P6_PERFCTR1:
1930         case MSR_P6_EVNTSEL0:
1931         case MSR_P6_EVNTSEL1:
1932                 if (kvm_pmu_msr(vcpu, msr))
1933                         return kvm_pmu_get_msr(vcpu, msr, pdata);
1934                 data = 0;
1935                 break;
1936         case MSR_IA32_UCODE_REV:
1937                 data = 0x100000000ULL;
1938                 break;
1939         case MSR_MTRRcap:
1940                 data = 0x500 | KVM_NR_VAR_MTRR;
1941                 break;
1942         case 0x200 ... 0x2ff:
1943                 return get_msr_mtrr(vcpu, msr, pdata);
1944         case 0xcd: /* fsb frequency */
1945                 data = 3;
1946                 break;
1947                 /*
1948                  * MSR_EBC_FREQUENCY_ID
1949                  * Conservative value valid for even the basic CPU models.
1950                  * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1951                  * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1952                  * and 266MHz for model 3, or 4. Set Core Clock
1953                  * Frequency to System Bus Frequency Ratio to 1 (bits
1954                  * 31:24) even though these are only valid for CPU
1955                  * models > 2, however guests may end up dividing or
1956                  * multiplying by zero otherwise.
1957                  */
1958         case MSR_EBC_FREQUENCY_ID:
1959                 data = 1 << 24;
1960                 break;
1961         case MSR_IA32_APICBASE:
1962                 data = kvm_get_apic_base(vcpu);
1963                 break;
1964         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1965                 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1966                 break;
1967         case MSR_IA32_TSCDEADLINE:
1968                 data = kvm_get_lapic_tscdeadline_msr(vcpu);
1969                 break;
1970         case MSR_IA32_MISC_ENABLE:
1971                 data = vcpu->arch.ia32_misc_enable_msr;
1972                 break;
1973         case MSR_IA32_PERF_STATUS:
1974                 /* TSC increment by tick */
1975                 data = 1000ULL;
1976                 /* CPU multiplier */
1977                 data |= (((uint64_t)4ULL) << 40);
1978                 break;
1979         case MSR_EFER:
1980                 data = vcpu->arch.efer;
1981                 break;
1982         case MSR_KVM_WALL_CLOCK:
1983         case MSR_KVM_WALL_CLOCK_NEW:
1984                 data = vcpu->kvm->arch.wall_clock;
1985                 break;
1986         case MSR_KVM_SYSTEM_TIME:
1987         case MSR_KVM_SYSTEM_TIME_NEW:
1988                 data = vcpu->arch.time;
1989                 break;
1990         case MSR_KVM_ASYNC_PF_EN:
1991                 data = vcpu->arch.apf.msr_val;
1992                 break;
1993         case MSR_KVM_STEAL_TIME:
1994                 data = vcpu->arch.st.msr_val;
1995                 break;
1996         case MSR_IA32_P5_MC_ADDR:
1997         case MSR_IA32_P5_MC_TYPE:
1998         case MSR_IA32_MCG_CAP:
1999         case MSR_IA32_MCG_CTL:
2000         case MSR_IA32_MCG_STATUS:
2001         case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2002                 return get_msr_mce(vcpu, msr, pdata);
2003         case MSR_K7_CLK_CTL:
2004                 /*
2005                  * Provide expected ramp-up count for K7. All other
2006                  * are set to zero, indicating minimum divisors for
2007                  * every field.
2008                  *
2009                  * This prevents guest kernels on AMD host with CPU
2010                  * type 6, model 8 and higher from exploding due to
2011                  * the rdmsr failing.
2012                  */
2013                 data = 0x20000000;
2014                 break;
2015         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2016                 if (kvm_hv_msr_partition_wide(msr)) {
2017                         int r;
2018                         mutex_lock(&vcpu->kvm->lock);
2019                         r = get_msr_hyperv_pw(vcpu, msr, pdata);
2020                         mutex_unlock(&vcpu->kvm->lock);
2021                         return r;
2022                 } else
2023                         return get_msr_hyperv(vcpu, msr, pdata);
2024                 break;
2025         case MSR_IA32_BBL_CR_CTL3:
2026                 /* This legacy MSR exists but isn't fully documented in current
2027                  * silicon.  It is however accessed by winxp in very narrow
2028                  * scenarios where it sets bit #19, itself documented as
2029                  * a "reserved" bit.  Best effort attempt to source coherent
2030                  * read data here should the balance of the register be
2031                  * interpreted by the guest:
2032                  *
2033                  * L2 cache control register 3: 64GB range, 256KB size,
2034                  * enabled, latency 0x1, configured
2035                  */
2036                 data = 0xbe702111;
2037                 break;
2038         case MSR_AMD64_OSVW_ID_LENGTH:
2039                 if (!guest_cpuid_has_osvw(vcpu))
2040                         return 1;
2041                 data = vcpu->arch.osvw.length;
2042                 break;
2043         case MSR_AMD64_OSVW_STATUS:
2044                 if (!guest_cpuid_has_osvw(vcpu))
2045                         return 1;
2046                 data = vcpu->arch.osvw.status;
2047                 break;
2048         default:
2049                 if (kvm_pmu_msr(vcpu, msr))
2050                         return kvm_pmu_get_msr(vcpu, msr, pdata);
2051                 if (!ignore_msrs) {
2052                         vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2053                         return 1;
2054                 } else {
2055                         vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2056                         data = 0;
2057                 }
2058                 break;
2059         }
2060         *pdata = data;
2061         return 0;
2062 }
2063 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2064
2065 /*
2066  * Read or write a bunch of msrs. All parameters are kernel addresses.
2067  *
2068  * @return number of msrs set successfully.
2069  */
2070 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2071                     struct kvm_msr_entry *entries,
2072                     int (*do_msr)(struct kvm_vcpu *vcpu,
2073                                   unsigned index, u64 *data))
2074 {
2075         int i, idx;
2076
2077         idx = srcu_read_lock(&vcpu->kvm->srcu);
2078         for (i = 0; i < msrs->nmsrs; ++i)
2079                 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2080                         break;
2081         srcu_read_unlock(&vcpu->kvm->srcu, idx);
2082
2083         return i;
2084 }
2085
2086 /*
2087  * Read or write a bunch of msrs. Parameters are user addresses.
2088  *
2089  * @return number of msrs set successfully.
2090  */
2091 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2092                   int (*do_msr)(struct kvm_vcpu *vcpu,
2093                                 unsigned index, u64 *data),
2094                   int writeback)
2095 {
2096         struct kvm_msrs msrs;
2097         struct kvm_msr_entry *entries;
2098         int r, n;
2099         unsigned size;
2100
2101         r = -EFAULT;
2102         if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2103                 goto out;
2104
2105         r = -E2BIG;
2106         if (msrs.nmsrs >= MAX_IO_MSRS)
2107                 goto out;
2108
2109         size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2110         entries = memdup_user(user_msrs->entries, size);
2111         if (IS_ERR(entries)) {
2112                 r = PTR_ERR(entries);
2113                 goto out;
2114         }
2115
2116         r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2117         if (r < 0)
2118                 goto out_free;
2119
2120         r = -EFAULT;
2121         if (writeback && copy_to_user(user_msrs->entries, entries, size))
2122                 goto out_free;
2123
2124         r = n;
2125
2126 out_free:
2127         kfree(entries);
2128 out:
2129         return r;
2130 }
2131
2132 int kvm_dev_ioctl_check_extension(long ext)
2133 {
2134         int r;
2135
2136         switch (ext) {
2137         case KVM_CAP_IRQCHIP:
2138         case KVM_CAP_HLT:
2139         case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2140         case KVM_CAP_SET_TSS_ADDR:
2141         case KVM_CAP_EXT_CPUID:
2142         case KVM_CAP_CLOCKSOURCE:
2143         case KVM_CAP_PIT:
2144         case KVM_CAP_NOP_IO_DELAY:
2145         case KVM_CAP_MP_STATE:
2146         case KVM_CAP_SYNC_MMU:
2147         case KVM_CAP_USER_NMI:
2148         case KVM_CAP_REINJECT_CONTROL:
2149         case KVM_CAP_IRQ_INJECT_STATUS:
2150         case KVM_CAP_ASSIGN_DEV_IRQ:
2151         case KVM_CAP_IRQFD:
2152         case KVM_CAP_IOEVENTFD:
2153         case KVM_CAP_PIT2:
2154         case KVM_CAP_PIT_STATE2:
2155         case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2156         case KVM_CAP_XEN_HVM:
2157         case KVM_CAP_ADJUST_CLOCK:
2158         case KVM_CAP_VCPU_EVENTS:
2159         case KVM_CAP_HYPERV:
2160         case KVM_CAP_HYPERV_VAPIC:
2161         case KVM_CAP_HYPERV_SPIN:
2162         case KVM_CAP_PCI_SEGMENT:
2163         case KVM_CAP_DEBUGREGS:
2164         case KVM_CAP_X86_ROBUST_SINGLESTEP:
2165         case KVM_CAP_XSAVE:
2166         case KVM_CAP_ASYNC_PF:
2167         case KVM_CAP_GET_TSC_KHZ:
2168         case KVM_CAP_PCI_2_3:
2169         case KVM_CAP_KVMCLOCK_CTRL:
2170                 r = 1;
2171                 break;
2172         case KVM_CAP_COALESCED_MMIO:
2173                 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2174                 break;
2175         case KVM_CAP_VAPIC:
2176                 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2177                 break;
2178         case KVM_CAP_NR_VCPUS:
2179                 r = KVM_SOFT_MAX_VCPUS;
2180                 break;
2181         case KVM_CAP_MAX_VCPUS:
2182                 r = KVM_MAX_VCPUS;
2183                 break;
2184         case KVM_CAP_NR_MEMSLOTS:
2185                 r = KVM_MEMORY_SLOTS;
2186                 break;
2187         case KVM_CAP_PV_MMU:    /* obsolete */
2188                 r = 0;
2189                 break;
2190         case KVM_CAP_IOMMU:
2191                 r = iommu_present(&pci_bus_type);
2192                 break;
2193         case KVM_CAP_MCE:
2194                 r = KVM_MAX_MCE_BANKS;
2195                 break;
2196         case KVM_CAP_XCRS:
2197                 r = cpu_has_xsave;
2198                 break;
2199         case KVM_CAP_TSC_CONTROL:
2200                 r = kvm_has_tsc_control;
2201                 break;
2202         case KVM_CAP_TSC_DEADLINE_TIMER:
2203                 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2204                 break;
2205         default:
2206                 r = 0;
2207                 break;
2208         }
2209         return r;
2210
2211 }
2212
2213 long kvm_arch_dev_ioctl(struct file *filp,
2214                         unsigned int ioctl, unsigned long arg)
2215 {
2216         void __user *argp = (void __user *)arg;
2217         long r;
2218
2219         switch (ioctl) {
2220         case KVM_GET_MSR_INDEX_LIST: {
2221                 struct kvm_msr_list __user *user_msr_list = argp;
2222                 struct kvm_msr_list msr_list;
2223                 unsigned n;
2224
2225                 r = -EFAULT;
2226                 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2227                         goto out;
2228                 n = msr_list.nmsrs;
2229                 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2230                 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2231                         goto out;
2232                 r = -E2BIG;
2233                 if (n < msr_list.nmsrs)
2234                         goto out;
2235                 r = -EFAULT;
2236                 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2237                                  num_msrs_to_save * sizeof(u32)))
2238                         goto out;
2239                 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2240                                  &emulated_msrs,
2241                                  ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2242                         goto out;
2243                 r = 0;
2244                 break;
2245         }
2246         case KVM_GET_SUPPORTED_CPUID: {
2247                 struct kvm_cpuid2 __user *cpuid_arg = argp;
2248                 struct kvm_cpuid2 cpuid;
2249
2250                 r = -EFAULT;
2251                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2252                         goto out;
2253                 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
2254                                                       cpuid_arg->entries);
2255                 if (r)
2256                         goto out;
2257
2258                 r = -EFAULT;
2259                 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2260                         goto out;
2261                 r = 0;
2262                 break;
2263         }
2264         case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2265                 u64 mce_cap;
2266
2267                 mce_cap = KVM_MCE_CAP_SUPPORTED;
2268                 r = -EFAULT;
2269                 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2270                         goto out;
2271                 r = 0;
2272                 break;
2273         }
2274         default:
2275                 r = -EINVAL;
2276         }
2277 out:
2278         return r;
2279 }
2280
2281 static void wbinvd_ipi(void *garbage)
2282 {
2283         wbinvd();
2284 }
2285
2286 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2287 {
2288         return vcpu->kvm->arch.iommu_domain &&
2289                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2290 }
2291
2292 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2293 {
2294         /* Address WBINVD may be executed by guest */
2295         if (need_emulate_wbinvd(vcpu)) {
2296                 if (kvm_x86_ops->has_wbinvd_exit())
2297                         cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2298                 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2299                         smp_call_function_single(vcpu->cpu,
2300                                         wbinvd_ipi, NULL, 1);
2301         }
2302
2303         kvm_x86_ops->vcpu_load(vcpu, cpu);
2304
2305         /* Apply any externally detected TSC adjustments (due to suspend) */
2306         if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2307                 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2308                 vcpu->arch.tsc_offset_adjustment = 0;
2309                 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2310         }
2311
2312         if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2313                 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2314                                 native_read_tsc() - vcpu->arch.last_host_tsc;
2315                 if (tsc_delta < 0)
2316                         mark_tsc_unstable("KVM discovered backwards TSC");
2317                 if (check_tsc_unstable()) {
2318                         u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2319                                                 vcpu->arch.last_guest_tsc);
2320                         kvm_x86_ops->write_tsc_offset(vcpu, offset);
2321                         vcpu->arch.tsc_catchup = 1;
2322                 }
2323                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2324                 if (vcpu->cpu != cpu)
2325                         kvm_migrate_timers(vcpu);
2326                 vcpu->cpu = cpu;
2327         }
2328
2329         accumulate_steal_time(vcpu);
2330         kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2331 }
2332
2333 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2334 {
2335         kvm_x86_ops->vcpu_put(vcpu);
2336         kvm_put_guest_fpu(vcpu);
2337         vcpu->arch.last_host_tsc = native_read_tsc();
2338 }
2339
2340 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2341                                     struct kvm_lapic_state *s)
2342 {
2343         memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2344
2345         return 0;
2346 }
2347
2348 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2349                                     struct kvm_lapic_state *s)
2350 {
2351         memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
2352         kvm_apic_post_state_restore(vcpu);
2353         update_cr8_intercept(vcpu);
2354
2355         return 0;
2356 }
2357
2358 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2359                                     struct kvm_interrupt *irq)
2360 {
2361         if (irq->irq < 0 || irq->irq >= 256)
2362                 return -EINVAL;
2363         if (irqchip_in_kernel(vcpu->kvm))
2364                 return -ENXIO;
2365
2366         kvm_queue_interrupt(vcpu, irq->irq, false);
2367         kvm_make_request(KVM_REQ_EVENT, vcpu);
2368
2369         return 0;
2370 }
2371
2372 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2373 {
2374         kvm_inject_nmi(vcpu);
2375
2376         return 0;
2377 }
2378
2379 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2380                                            struct kvm_tpr_access_ctl *tac)
2381 {
2382         if (tac->flags)
2383                 return -EINVAL;
2384         vcpu->arch.tpr_access_reporting = !!tac->enabled;
2385         return 0;
2386 }
2387
2388 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2389                                         u64 mcg_cap)
2390 {
2391         int r;
2392         unsigned bank_num = mcg_cap & 0xff, bank;
2393
2394         r = -EINVAL;
2395         if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2396                 goto out;
2397         if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2398                 goto out;
2399         r = 0;
2400         vcpu->arch.mcg_cap = mcg_cap;
2401         /* Init IA32_MCG_CTL to all 1s */
2402         if (mcg_cap & MCG_CTL_P)
2403                 vcpu->arch.mcg_ctl = ~(u64)0;
2404         /* Init IA32_MCi_CTL to all 1s */
2405         for (bank = 0; bank < bank_num; bank++)
2406                 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2407 out:
2408         return r;
2409 }
2410
2411 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2412                                       struct kvm_x86_mce *mce)
2413 {
2414         u64 mcg_cap = vcpu->arch.mcg_cap;
2415         unsigned bank_num = mcg_cap & 0xff;
2416         u64 *banks = vcpu->arch.mce_banks;
2417
2418         if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2419                 return -EINVAL;
2420         /*
2421          * if IA32_MCG_CTL is not all 1s, the uncorrected error
2422          * reporting is disabled
2423          */
2424         if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2425             vcpu->arch.mcg_ctl != ~(u64)0)
2426                 return 0;
2427         banks += 4 * mce->bank;
2428         /*
2429          * if IA32_MCi_CTL is not all 1s, the uncorrected error
2430          * reporting is disabled for the bank
2431          */
2432         if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2433                 return 0;
2434         if (mce->status & MCI_STATUS_UC) {
2435                 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2436                     !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2437                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2438                         return 0;
2439                 }
2440                 if (banks[1] & MCI_STATUS_VAL)
2441                         mce->status |= MCI_STATUS_OVER;
2442                 banks[2] = mce->addr;
2443                 banks[3] = mce->misc;
2444                 vcpu->arch.mcg_status = mce->mcg_status;
2445                 banks[1] = mce->status;
2446                 kvm_queue_exception(vcpu, MC_VECTOR);
2447         } else if (!(banks[1] & MCI_STATUS_VAL)
2448                    || !(banks[1] & MCI_STATUS_UC)) {
2449                 if (banks[1] & MCI_STATUS_VAL)
2450                         mce->status |= MCI_STATUS_OVER;
2451                 banks[2] = mce->addr;
2452                 banks[3] = mce->misc;
2453                 banks[1] = mce->status;
2454         } else
2455                 banks[1] |= MCI_STATUS_OVER;
2456         return 0;
2457 }
2458
2459 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2460                                                struct kvm_vcpu_events *events)
2461 {
2462         process_nmi(vcpu);
2463         events->exception.injected =
2464                 vcpu->arch.exception.pending &&
2465                 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2466         events->exception.nr = vcpu->arch.exception.nr;
2467         events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2468         events->exception.pad = 0;
2469         events->exception.error_code = vcpu->arch.exception.error_code;
2470
2471         events->interrupt.injected =
2472                 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2473         events->interrupt.nr = vcpu->arch.interrupt.nr;
2474         events->interrupt.soft = 0;
2475         events->interrupt.shadow =
2476                 kvm_x86_ops->get_interrupt_shadow(vcpu,
2477                         KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2478
2479         events->nmi.injected = vcpu->arch.nmi_injected;
2480         events->nmi.pending = vcpu->arch.nmi_pending != 0;
2481         events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2482         events->nmi.pad = 0;
2483
2484         events->sipi_vector = vcpu->arch.sipi_vector;
2485
2486         events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2487                          | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2488                          | KVM_VCPUEVENT_VALID_SHADOW);
2489         memset(&events->reserved, 0, sizeof(events->reserved));
2490 }
2491
2492 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2493                                               struct kvm_vcpu_events *events)
2494 {
2495         if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2496                               | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2497                               | KVM_VCPUEVENT_VALID_SHADOW))
2498                 return -EINVAL;
2499
2500         process_nmi(vcpu);
2501         vcpu->arch.exception.pending = events->exception.injected;
2502         vcpu->arch.exception.nr = events->exception.nr;
2503         vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2504         vcpu->arch.exception.error_code = events->exception.error_code;
2505
2506         vcpu->arch.interrupt.pending = events->interrupt.injected;
2507         vcpu->arch.interrupt.nr = events->interrupt.nr;
2508         vcpu->arch.interrupt.soft = events->interrupt.soft;
2509         if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2510                 kvm_x86_ops->set_interrupt_shadow(vcpu,
2511                                                   events->interrupt.shadow);
2512
2513         vcpu->arch.nmi_injected = events->nmi.injected;
2514         if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2515                 vcpu->arch.nmi_pending = events->nmi.pending;
2516         kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2517
2518         if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2519                 vcpu->arch.sipi_vector = events->sipi_vector;
2520
2521         kvm_make_request(KVM_REQ_EVENT, vcpu);
2522
2523         return 0;
2524 }
2525
2526 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2527                                              struct kvm_debugregs *dbgregs)
2528 {
2529         memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2530         dbgregs->dr6 = vcpu->arch.dr6;
2531         dbgregs->dr7 = vcpu->arch.dr7;
2532         dbgregs->flags = 0;
2533         memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
2534 }
2535
2536 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2537                                             struct kvm_debugregs *dbgregs)
2538 {
2539         if (dbgregs->flags)
2540                 return -EINVAL;
2541
2542         memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2543         vcpu->arch.dr6 = dbgregs->dr6;
2544         vcpu->arch.dr7 = dbgregs->dr7;
2545
2546         return 0;
2547 }
2548
2549 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2550                                          struct kvm_xsave *guest_xsave)
2551 {
2552         if (cpu_has_xsave)
2553                 memcpy(guest_xsave->region,
2554                         &vcpu->arch.guest_fpu.state->xsave,
2555                         xstate_size);
2556         else {
2557                 memcpy(guest_xsave->region,
2558                         &vcpu->arch.guest_fpu.state->fxsave,
2559                         sizeof(struct i387_fxsave_struct));
2560                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2561                         XSTATE_FPSSE;
2562         }
2563 }
2564
2565 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2566                                         struct kvm_xsave *guest_xsave)
2567 {
2568         u64 xstate_bv =
2569                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2570
2571         if (cpu_has_xsave)
2572                 memcpy(&vcpu->arch.guest_fpu.state->xsave,
2573                         guest_xsave->region, xstate_size);
2574         else {
2575                 if (xstate_bv & ~XSTATE_FPSSE)
2576                         return -EINVAL;
2577                 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2578                         guest_xsave->region, sizeof(struct i387_fxsave_struct));
2579         }
2580         return 0;
2581 }
2582
2583 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2584                                         struct kvm_xcrs *guest_xcrs)
2585 {
2586         if (!cpu_has_xsave) {
2587                 guest_xcrs->nr_xcrs = 0;
2588                 return;
2589         }
2590
2591         guest_xcrs->nr_xcrs = 1;
2592         guest_xcrs->flags = 0;
2593         guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2594         guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2595 }
2596
2597 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2598                                        struct kvm_xcrs *guest_xcrs)
2599 {
2600         int i, r = 0;
2601
2602         if (!cpu_has_xsave)
2603                 return -EINVAL;
2604
2605         if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2606                 return -EINVAL;
2607
2608         for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2609                 /* Only support XCR0 currently */
2610                 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2611                         r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2612                                 guest_xcrs->xcrs[0].value);
2613                         break;
2614                 }
2615         if (r)
2616                 r = -EINVAL;
2617         return r;
2618 }
2619
2620 /*
2621  * kvm_set_guest_paused() indicates to the guest kernel that it has been
2622  * stopped by the hypervisor.  This function will be called from the host only.
2623  * EINVAL is returned when the host attempts to set the flag for a guest that
2624  * does not support pv clocks.
2625  */
2626 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
2627 {
2628         struct pvclock_vcpu_time_info *src = &vcpu->arch.hv_clock;
2629         if (!vcpu->arch.time_page)
2630                 return -EINVAL;
2631         src->flags |= PVCLOCK_GUEST_STOPPED;
2632         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2633         return 0;
2634 }
2635
2636 long kvm_arch_vcpu_ioctl(struct file *filp,
2637                          unsigned int ioctl, unsigned long arg)
2638 {
2639         struct kvm_vcpu *vcpu = filp->private_data;
2640         void __user *argp = (void __user *)arg;
2641         int r;
2642         union {
2643                 struct kvm_lapic_state *lapic;
2644                 struct kvm_xsave *xsave;
2645                 struct kvm_xcrs *xcrs;
2646                 void *buffer;
2647         } u;
2648
2649         u.buffer = NULL;
2650         switch (ioctl) {
2651         case KVM_GET_LAPIC: {
2652                 r = -EINVAL;
2653                 if (!vcpu->arch.apic)
2654                         goto out;
2655                 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2656
2657                 r = -ENOMEM;
2658                 if (!u.lapic)
2659                         goto out;
2660                 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
2661                 if (r)
2662                         goto out;
2663                 r = -EFAULT;
2664                 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
2665                         goto out;
2666                 r = 0;
2667                 break;
2668         }
2669         case KVM_SET_LAPIC: {
2670                 r = -EINVAL;
2671                 if (!vcpu->arch.apic)
2672                         goto out;
2673                 u.lapic = memdup_user(argp, sizeof(*u.lapic));
2674                 if (IS_ERR(u.lapic)) {
2675                         r = PTR_ERR(u.lapic);
2676                         goto out;
2677                 }
2678
2679                 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
2680                 if (r)
2681                         goto out;
2682                 r = 0;
2683                 break;
2684         }
2685         case KVM_INTERRUPT: {
2686                 struct kvm_interrupt irq;
2687
2688                 r = -EFAULT;
2689                 if (copy_from_user(&irq, argp, sizeof irq))
2690                         goto out;
2691                 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2692                 if (r)
2693                         goto out;
2694                 r = 0;
2695                 break;
2696         }
2697         case KVM_NMI: {
2698                 r = kvm_vcpu_ioctl_nmi(vcpu);
2699                 if (r)
2700                         goto out;
2701                 r = 0;
2702                 break;
2703         }
2704         case KVM_SET_CPUID: {
2705                 struct kvm_cpuid __user *cpuid_arg = argp;
2706                 struct kvm_cpuid cpuid;
2707
2708                 r = -EFAULT;
2709                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2710                         goto out;
2711                 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2712                 if (r)
2713                         goto out;
2714                 break;
2715         }
2716         case KVM_SET_CPUID2: {
2717                 struct kvm_cpuid2 __user *cpuid_arg = argp;
2718                 struct kvm_cpuid2 cpuid;
2719
2720                 r = -EFAULT;
2721                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2722                         goto out;
2723                 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
2724                                               cpuid_arg->entries);
2725                 if (r)
2726                         goto out;
2727                 break;
2728         }
2729         case KVM_GET_CPUID2: {
2730                 struct kvm_cpuid2 __user *cpuid_arg = argp;
2731                 struct kvm_cpuid2 cpuid;
2732
2733                 r = -EFAULT;
2734                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2735                         goto out;
2736                 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
2737                                               cpuid_arg->entries);
2738                 if (r)
2739                         goto out;
2740                 r = -EFAULT;
2741                 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2742                         goto out;
2743                 r = 0;
2744                 break;
2745         }
2746         case KVM_GET_MSRS:
2747                 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2748                 break;
2749         case KVM_SET_MSRS:
2750                 r = msr_io(vcpu, argp, do_set_msr, 0);
2751                 break;
2752         case KVM_TPR_ACCESS_REPORTING: {
2753                 struct kvm_tpr_access_ctl tac;
2754
2755                 r = -EFAULT;
2756                 if (copy_from_user(&tac, argp, sizeof tac))
2757                         goto out;
2758                 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2759                 if (r)
2760                         goto out;
2761                 r = -EFAULT;
2762                 if (copy_to_user(argp, &tac, sizeof tac))
2763                         goto out;
2764                 r = 0;
2765                 break;
2766         };
2767         case KVM_SET_VAPIC_ADDR: {
2768                 struct kvm_vapic_addr va;
2769
2770                 r = -EINVAL;
2771                 if (!irqchip_in_kernel(vcpu->kvm))
2772                         goto out;
2773                 r = -EFAULT;
2774                 if (copy_from_user(&va, argp, sizeof va))
2775                         goto out;
2776                 r = 0;
2777                 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2778                 break;
2779         }
2780         case KVM_X86_SETUP_MCE: {
2781                 u64 mcg_cap;
2782
2783                 r = -EFAULT;
2784                 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2785                         goto out;
2786                 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2787                 break;
2788         }
2789         case KVM_X86_SET_MCE: {
2790                 struct kvm_x86_mce mce;
2791
2792                 r = -EFAULT;
2793                 if (copy_from_user(&mce, argp, sizeof mce))
2794                         goto out;
2795                 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2796                 break;
2797         }
2798         case KVM_GET_VCPU_EVENTS: {
2799                 struct kvm_vcpu_events events;
2800
2801                 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2802
2803                 r = -EFAULT;
2804                 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2805                         break;
2806                 r = 0;
2807                 break;
2808         }
2809         case KVM_SET_VCPU_EVENTS: {
2810                 struct kvm_vcpu_events events;
2811
2812                 r = -EFAULT;
2813                 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2814                         break;
2815
2816                 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2817                 break;
2818         }
2819         case KVM_GET_DEBUGREGS: {
2820                 struct kvm_debugregs dbgregs;
2821
2822                 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2823
2824                 r = -EFAULT;
2825                 if (copy_to_user(argp, &dbgregs,
2826                                  sizeof(struct kvm_debugregs)))
2827                         break;
2828                 r = 0;
2829                 break;
2830         }
2831         case KVM_SET_DEBUGREGS: {
2832                 struct kvm_debugregs dbgregs;
2833
2834                 r = -EFAULT;
2835                 if (copy_from_user(&dbgregs, argp,
2836                                    sizeof(struct kvm_debugregs)))
2837                         break;
2838
2839                 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2840                 break;
2841         }
2842         case KVM_GET_XSAVE: {
2843                 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2844                 r = -ENOMEM;
2845                 if (!u.xsave)
2846                         break;
2847
2848                 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2849
2850                 r = -EFAULT;
2851                 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2852                         break;
2853                 r = 0;
2854                 break;
2855         }
2856         case KVM_SET_XSAVE: {
2857                 u.xsave = memdup_user(argp, sizeof(*u.xsave));
2858                 if (IS_ERR(u.xsave)) {
2859                         r = PTR_ERR(u.xsave);
2860                         goto out;
2861                 }
2862
2863                 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2864                 break;
2865         }
2866         case KVM_GET_XCRS: {
2867                 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2868                 r = -ENOMEM;
2869                 if (!u.xcrs)
2870                         break;
2871
2872                 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2873
2874                 r = -EFAULT;
2875                 if (copy_to_user(argp, u.xcrs,
2876                                  sizeof(struct kvm_xcrs)))
2877                         break;
2878                 r = 0;
2879                 break;
2880         }
2881         case KVM_SET_XCRS: {
2882                 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
2883                 if (IS_ERR(u.xcrs)) {
2884                         r = PTR_ERR(u.xcrs);
2885                         goto out;
2886                 }
2887
2888                 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2889                 break;
2890         }
2891         case KVM_SET_TSC_KHZ: {
2892                 u32 user_tsc_khz;
2893
2894                 r = -EINVAL;
2895                 user_tsc_khz = (u32)arg;
2896
2897                 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
2898                         goto out;
2899
2900                 if (user_tsc_khz == 0)
2901                         user_tsc_khz = tsc_khz;
2902
2903                 kvm_set_tsc_khz(vcpu, user_tsc_khz);
2904
2905                 r = 0;
2906                 goto out;
2907         }
2908         case KVM_GET_TSC_KHZ: {
2909                 r = vcpu->arch.virtual_tsc_khz;
2910                 goto out;
2911         }
2912         case KVM_KVMCLOCK_CTRL: {
2913                 r = kvm_set_guest_paused(vcpu);
2914                 goto out;
2915         }
2916         default:
2917                 r = -EINVAL;
2918         }
2919 out:
2920         kfree(u.buffer);
2921         return r;
2922 }
2923
2924 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
2925 {
2926         return VM_FAULT_SIGBUS;
2927 }
2928
2929 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2930 {
2931         int ret;
2932
2933         if (addr > (unsigned int)(-3 * PAGE_SIZE))
2934                 return -1;
2935         ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2936         return ret;
2937 }
2938
2939 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2940                                               u64 ident_addr)
2941 {
2942         kvm->arch.ept_identity_map_addr = ident_addr;
2943         return 0;
2944 }
2945
2946 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2947                                           u32 kvm_nr_mmu_pages)
2948 {
2949         if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2950                 return -EINVAL;
2951
2952         mutex_lock(&kvm->slots_lock);
2953         spin_lock(&kvm->mmu_lock);
2954
2955         kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
2956         kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
2957
2958         spin_unlock(&kvm->mmu_lock);
2959         mutex_unlock(&kvm->slots_lock);
2960         return 0;
2961 }
2962
2963 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2964 {
2965         return kvm->arch.n_max_mmu_pages;
2966 }
2967
2968 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2969 {
2970         int r;
2971
2972         r = 0;
2973         switch (chip->chip_id) {
2974         case KVM_IRQCHIP_PIC_MASTER:
2975                 memcpy(&chip->chip.pic,
2976                         &pic_irqchip(kvm)->pics[0],
2977                         sizeof(struct kvm_pic_state));
2978                 break;
2979         case KVM_IRQCHIP_PIC_SLAVE:
2980                 memcpy(&chip->chip.pic,
2981                         &pic_irqchip(kvm)->pics[1],
2982                         sizeof(struct kvm_pic_state));
2983                 break;
2984         case KVM_IRQCHIP_IOAPIC:
2985                 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
2986                 break;
2987         default:
2988                 r = -EINVAL;
2989                 break;
2990         }
2991         return r;
2992 }
2993
2994 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2995 {
2996         int r;
2997
2998         r = 0;
2999         switch (chip->chip_id) {
3000         case KVM_IRQCHIP_PIC_MASTER:
3001                 spin_lock(&pic_irqchip(kvm)->lock);
3002                 memcpy(&pic_irqchip(kvm)->pics[0],
3003                         &chip->chip.pic,
3004                         sizeof(struct kvm_pic_state));
3005                 spin_unlock(&pic_irqchip(kvm)->lock);
3006                 break;
3007         case KVM_IRQCHIP_PIC_SLAVE:
3008                 spin_lock(&pic_irqchip(kvm)->lock);
3009                 memcpy(&pic_irqchip(kvm)->pics[1],
3010                         &chip->chip.pic,
3011                         sizeof(struct kvm_pic_state));
3012                 spin_unlock(&pic_irqchip(kvm)->lock);
3013                 break;
3014         case KVM_IRQCHIP_IOAPIC:
3015                 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3016                 break;
3017         default:
3018                 r = -EINVAL;
3019                 break;
3020         }
3021         kvm_pic_update_irq(pic_irqchip(kvm));
3022         return r;
3023 }
3024
3025 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3026 {
3027         int r = 0;
3028
3029         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3030         memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3031         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3032         return r;
3033 }
3034
3035 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3036 {
3037         int r = 0;
3038
3039         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3040         memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3041         kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3042         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3043         return r;
3044 }
3045
3046 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3047 {
3048         int r = 0;
3049
3050         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3051         memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3052                 sizeof(ps->channels));
3053         ps->flags = kvm->arch.vpit->pit_state.flags;
3054         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3055         memset(&ps->reserved, 0, sizeof(ps->reserved));
3056         return r;
3057 }
3058
3059 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3060 {
3061         int r = 0, start = 0;
3062         u32 prev_legacy, cur_legacy;
3063         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3064         prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3065         cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3066         if (!prev_legacy && cur_legacy)
3067                 start = 1;
3068         memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3069                sizeof(kvm->arch.vpit->pit_state.channels));
3070         kvm->arch.vpit->pit_state.flags = ps->flags;
3071         kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3072         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3073         return r;
3074 }
3075
3076 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3077                                  struct kvm_reinject_control *control)
3078 {
3079         if (!kvm->arch.vpit)
3080                 return -ENXIO;
3081         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3082         kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3083         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3084         return 0;
3085 }
3086
3087 /**
3088  * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3089  * @kvm: kvm instance
3090  * @log: slot id and address to which we copy the log
3091  *
3092  * We need to keep it in mind that VCPU threads can write to the bitmap
3093  * concurrently.  So, to avoid losing data, we keep the following order for
3094  * each bit:
3095  *
3096  *   1. Take a snapshot of the bit and clear it if needed.
3097  *   2. Write protect the corresponding page.
3098  *   3. Flush TLB's if needed.
3099  *   4. Copy the snapshot to the userspace.
3100  *
3101  * Between 2 and 3, the guest may write to the page using the remaining TLB
3102  * entry.  This is not a problem because the page will be reported dirty at
3103  * step 4 using the snapshot taken before and step 3 ensures that successive
3104  * writes will be logged for the next call.
3105  */
3106 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3107 {
3108         int r;
3109         struct kvm_memory_slot *memslot;
3110         unsigned long n, i;
3111         unsigned long *dirty_bitmap;
3112         unsigned long *dirty_bitmap_buffer;
3113         bool is_dirty = false;
3114
3115         mutex_lock(&kvm->slots_lock);
3116
3117         r = -EINVAL;
3118         if (log->slot >= KVM_MEMORY_SLOTS)
3119                 goto out;
3120
3121         memslot = id_to_memslot(kvm->memslots, log->slot);
3122
3123         dirty_bitmap = memslot->dirty_bitmap;
3124         r = -ENOENT;
3125         if (!dirty_bitmap)
3126                 goto out;
3127
3128         n = kvm_dirty_bitmap_bytes(memslot);
3129
3130         dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3131         memset(dirty_bitmap_buffer, 0, n);
3132
3133         spin_lock(&kvm->mmu_lock);
3134
3135         for (i = 0; i < n / sizeof(long); i++) {
3136                 unsigned long mask;
3137                 gfn_t offset;
3138
3139                 if (!dirty_bitmap[i])
3140                         continue;
3141
3142                 is_dirty = true;
3143
3144                 mask = xchg(&dirty_bitmap[i], 0);
3145                 dirty_bitmap_buffer[i] = mask;
3146
3147                 offset = i * BITS_PER_LONG;
3148                 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
3149         }
3150         if (is_dirty)
3151                 kvm_flush_remote_tlbs(kvm);
3152
3153         spin_unlock(&kvm->mmu_lock);
3154
3155         r = -EFAULT;
3156         if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3157                 goto out;
3158
3159         r = 0;
3160 out:
3161         mutex_unlock(&kvm->slots_lock);
3162         return r;
3163 }
3164
3165 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event)
3166 {
3167         if (!irqchip_in_kernel(kvm))
3168                 return -ENXIO;
3169
3170         irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3171                                         irq_event->irq, irq_event->level);
3172         return 0;
3173 }
3174
3175 long kvm_arch_vm_ioctl(struct file *filp,
3176                        unsigned int ioctl, unsigned long arg)
3177 {
3178         struct kvm *kvm = filp->private_data;
3179         void __user *argp = (void __user *)arg;
3180         int r = -ENOTTY;
3181         /*
3182          * This union makes it completely explicit to gcc-3.x
3183          * that these two variables' stack usage should be
3184          * combined, not added together.
3185          */
3186         union {
3187                 struct kvm_pit_state ps;
3188                 struct kvm_pit_state2 ps2;
3189                 struct kvm_pit_config pit_config;
3190         } u;
3191
3192         switch (ioctl) {
3193         case KVM_SET_TSS_ADDR:
3194                 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3195                 if (r < 0)
3196                         goto out;
3197                 break;
3198         case KVM_SET_IDENTITY_MAP_ADDR: {
3199                 u64 ident_addr;
3200
3201                 r = -EFAULT;
3202                 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3203                         goto out;
3204                 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3205                 if (r < 0)
3206                         goto out;
3207                 break;
3208         }
3209         case KVM_SET_NR_MMU_PAGES:
3210                 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3211                 if (r)
3212                         goto out;
3213                 break;
3214         case KVM_GET_NR_MMU_PAGES:
3215                 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3216                 break;
3217         case KVM_CREATE_IRQCHIP: {
3218                 struct kvm_pic *vpic;
3219
3220                 mutex_lock(&kvm->lock);
3221                 r = -EEXIST;
3222                 if (kvm->arch.vpic)
3223                         goto create_irqchip_unlock;
3224                 r = -EINVAL;
3225                 if (atomic_read(&kvm->online_vcpus))
3226                         goto create_irqchip_unlock;
3227                 r = -ENOMEM;
3228                 vpic = kvm_create_pic(kvm);
3229                 if (vpic) {
3230                         r = kvm_ioapic_init(kvm);
3231                         if (r) {
3232                                 mutex_lock(&kvm->slots_lock);
3233                                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3234                                                           &vpic->dev_master);
3235                                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3236                                                           &vpic->dev_slave);
3237                                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3238                                                           &vpic->dev_eclr);
3239                                 mutex_unlock(&kvm->slots_lock);
3240                                 kfree(vpic);
3241                                 goto create_irqchip_unlock;
3242                         }
3243                 } else
3244                         goto create_irqchip_unlock;
3245                 smp_wmb();
3246                 kvm->arch.vpic = vpic;
3247                 smp_wmb();
3248                 r = kvm_setup_default_irq_routing(kvm);
3249                 if (r) {
3250                         mutex_lock(&kvm->slots_lock);
3251                         mutex_lock(&kvm->irq_lock);
3252                         kvm_ioapic_destroy(kvm);
3253                         kvm_destroy_pic(kvm);
3254                         mutex_unlock(&kvm->irq_lock);
3255                         mutex_unlock(&kvm->slots_lock);
3256                 }
3257         create_irqchip_unlock:
3258                 mutex_unlock(&kvm->lock);
3259                 break;
3260         }
3261         case KVM_CREATE_PIT:
3262                 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3263                 goto create_pit;
3264         case KVM_CREATE_PIT2:
3265                 r = -EFAULT;
3266                 if (copy_from_user(&u.pit_config, argp,
3267                                    sizeof(struct kvm_pit_config)))
3268                         goto out;
3269         create_pit:
3270                 mutex_lock(&kvm->slots_lock);
3271                 r = -EEXIST;
3272                 if (kvm->arch.vpit)
3273                         goto create_pit_unlock;
3274                 r = -ENOMEM;
3275                 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3276                 if (kvm->arch.vpit)
3277                         r = 0;
3278         create_pit_unlock:
3279                 mutex_unlock(&kvm->slots_lock);
3280                 break;
3281         case KVM_GET_IRQCHIP: {
3282                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3283                 struct kvm_irqchip *chip;
3284
3285                 chip = memdup_user(argp, sizeof(*chip));
3286                 if (IS_ERR(chip)) {
3287                         r = PTR_ERR(chip);
3288                         goto out;
3289                 }
3290
3291                 r = -ENXIO;
3292                 if (!irqchip_in_kernel(kvm))
3293                         goto get_irqchip_out;
3294                 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3295                 if (r)
3296                         goto get_irqchip_out;
3297                 r = -EFAULT;
3298                 if (copy_to_user(argp, chip, sizeof *chip))
3299                         goto get_irqchip_out;
3300                 r = 0;
3301         get_irqchip_out:
3302                 kfree(chip);
3303                 if (r)
3304                         goto out;
3305                 break;
3306         }
3307         case KVM_SET_IRQCHIP: {
3308                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3309                 struct kvm_irqchip *chip;
3310
3311                 chip = memdup_user(argp, sizeof(*chip));
3312                 if (IS_ERR(chip)) {
3313                         r = PTR_ERR(chip);
3314                         goto out;
3315                 }
3316
3317                 r = -ENXIO;
3318                 if (!irqchip_in_kernel(kvm))
3319                         goto set_irqchip_out;
3320                 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3321                 if (r)
3322                         goto set_irqchip_out;
3323                 r = 0;
3324         set_irqchip_out:
3325                 kfree(chip);
3326                 if (r)
3327                         goto out;
3328                 break;
3329         }
3330         case KVM_GET_PIT: {
3331                 r = -EFAULT;
3332                 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3333                         goto out;
3334                 r = -ENXIO;
3335                 if (!kvm->arch.vpit)
3336                         goto out;
3337                 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3338                 if (r)
3339                         goto out;
3340                 r = -EFAULT;
3341                 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3342                         goto out;
3343                 r = 0;
3344                 break;
3345         }
3346         case KVM_SET_PIT: {
3347                 r = -EFAULT;
3348                 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3349                         goto out;
3350                 r = -ENXIO;
3351                 if (!kvm->arch.vpit)
3352                         goto out;
3353                 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3354                 if (r)
3355                         goto out;
3356                 r = 0;
3357                 break;
3358         }
3359         case KVM_GET_PIT2: {
3360                 r = -ENXIO;
3361                 if (!kvm->arch.vpit)
3362                         goto out;
3363                 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3364                 if (r)
3365                         goto out;
3366                 r = -EFAULT;
3367                 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3368                         goto out;
3369                 r = 0;
3370                 break;
3371         }
3372         case KVM_SET_PIT2: {
3373                 r = -EFAULT;
3374                 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3375                         goto out;
3376                 r = -ENXIO;
3377                 if (!kvm->arch.vpit)
3378                         goto out;
3379                 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3380                 if (r)
3381                         goto out;
3382                 r = 0;
3383                 break;
3384         }
3385         case KVM_REINJECT_CONTROL: {
3386                 struct kvm_reinject_control control;
3387                 r =  -EFAULT;
3388                 if (copy_from_user(&control, argp, sizeof(control)))
3389                         goto out;
3390                 r = kvm_vm_ioctl_reinject(kvm, &control);
3391                 if (r)
3392                         goto out;
3393                 r = 0;
3394                 break;
3395         }
3396         case KVM_XEN_HVM_CONFIG: {
3397                 r = -EFAULT;
3398                 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3399                                    sizeof(struct kvm_xen_hvm_config)))
3400                         goto out;
3401                 r = -EINVAL;
3402                 if (kvm->arch.xen_hvm_config.flags)
3403                         goto out;
3404                 r = 0;
3405                 break;
3406         }
3407         case KVM_SET_CLOCK: {
3408                 struct kvm_clock_data user_ns;
3409                 u64 now_ns;
3410                 s64 delta;
3411
3412                 r = -EFAULT;
3413                 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3414                         goto out;
3415
3416                 r = -EINVAL;
3417                 if (user_ns.flags)
3418                         goto out;
3419
3420                 r = 0;
3421                 local_irq_disable();
3422                 now_ns = get_kernel_ns();
3423                 delta = user_ns.clock - now_ns;
3424                 local_irq_enable();
3425                 kvm->arch.kvmclock_offset = delta;
3426                 break;
3427         }
3428         case KVM_GET_CLOCK: {
3429                 struct kvm_clock_data user_ns;
3430                 u64 now_ns;
3431
3432                 local_irq_disable();
3433                 now_ns = get_kernel_ns();
3434                 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3435                 local_irq_enable();
3436                 user_ns.flags = 0;
3437                 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3438
3439                 r = -EFAULT;
3440                 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3441                         goto out;
3442                 r = 0;
3443                 break;
3444         }
3445
3446         default:
3447                 ;
3448         }
3449 out:
3450         return r;
3451 }
3452
3453 static void kvm_init_msr_list(void)
3454 {
3455         u32 dummy[2];
3456         unsigned i, j;
3457
3458         /* skip the first msrs in the list. KVM-specific */
3459         for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3460                 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3461                         continue;
3462                 if (j < i)
3463                         msrs_to_save[j] = msrs_to_save[i];
3464                 j++;
3465         }
3466         num_msrs_to_save = j;
3467 }
3468
3469 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3470                            const void *v)
3471 {
3472         int handled = 0;
3473         int n;
3474
3475         do {
3476                 n = min(len, 8);
3477                 if (!(vcpu->arch.apic &&
3478                       !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3479                     && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3480                         break;
3481                 handled += n;
3482                 addr += n;
3483                 len -= n;
3484                 v += n;
3485         } while (len);
3486
3487         return handled;
3488 }
3489
3490 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3491 {
3492         int handled = 0;
3493         int n;
3494
3495         do {
3496                 n = min(len, 8);
3497                 if (!(vcpu->arch.apic &&
3498                       !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3499                     && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3500                         break;
3501                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3502                 handled += n;
3503                 addr += n;
3504                 len -= n;
3505                 v += n;
3506         } while (len);
3507
3508         return handled;
3509 }
3510
3511 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3512                         struct kvm_segment *var, int seg)
3513 {
3514         kvm_x86_ops->set_segment(vcpu, var, seg);
3515 }
3516
3517 void kvm_get_segment(struct kvm_vcpu *vcpu,
3518                      struct kvm_segment *var, int seg)
3519 {
3520         kvm_x86_ops->get_segment(vcpu, var, seg);
3521 }
3522
3523 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3524 {
3525         gpa_t t_gpa;
3526         struct x86_exception exception;
3527
3528         BUG_ON(!mmu_is_nested(vcpu));
3529
3530         /* NPT walks are always user-walks */
3531         access |= PFERR_USER_MASK;
3532         t_gpa  = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
3533
3534         return t_gpa;
3535 }
3536
3537 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3538                               struct x86_exception *exception)
3539 {
3540         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3541         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3542 }
3543
3544  gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3545                                 struct x86_exception *exception)
3546 {
3547         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3548         access |= PFERR_FETCH_MASK;
3549         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3550 }
3551
3552 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3553                                struct x86_exception *exception)
3554 {
3555         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3556         access |= PFERR_WRITE_MASK;
3557         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3558 }
3559
3560 /* uses this to access any guest's mapped memory without checking CPL */
3561 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3562                                 struct x86_exception *exception)
3563 {
3564         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
3565 }
3566
3567 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3568                                       struct kvm_vcpu *vcpu, u32 access,
3569                                       struct x86_exception *exception)
3570 {
3571         void *data = val;
3572         int r = X86EMUL_CONTINUE;
3573
3574         while (bytes) {
3575                 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3576                                                             exception);
3577                 unsigned offset = addr & (PAGE_SIZE-1);
3578                 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
3579                 int ret;
3580
3581                 if (gpa == UNMAPPED_GVA)
3582                         return X86EMUL_PROPAGATE_FAULT;
3583                 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
3584                 if (ret < 0) {
3585                         r = X86EMUL_IO_NEEDED;
3586                         goto out;
3587                 }
3588
3589                 bytes -= toread;
3590                 data += toread;
3591                 addr += toread;
3592         }
3593 out:
3594         return r;
3595 }
3596
3597 /* used for instruction fetching */
3598 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3599                                 gva_t addr, void *val, unsigned int bytes,
3600                                 struct x86_exception *exception)
3601 {
3602         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3603         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3604
3605         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3606                                           access | PFERR_FETCH_MASK,
3607                                           exception);
3608 }
3609
3610 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
3611                                gva_t addr, void *val, unsigned int bytes,
3612                                struct x86_exception *exception)
3613 {
3614         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3615         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3616
3617         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3618                                           exception);
3619 }
3620 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
3621
3622 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3623                                       gva_t addr, void *val, unsigned int bytes,
3624                                       struct x86_exception *exception)
3625 {
3626         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3627         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
3628 }
3629
3630 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3631                                        gva_t addr, void *val,
3632                                        unsigned int bytes,
3633                                        struct x86_exception *exception)
3634 {
3635         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3636         void *data = val;
3637         int r = X86EMUL_CONTINUE;
3638
3639         while (bytes) {
3640                 gpa_t gpa =  vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3641                                                              PFERR_WRITE_MASK,
3642                                                              exception);
3643                 unsigned offset = addr & (PAGE_SIZE-1);
3644                 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3645                 int ret;
3646
3647                 if (gpa == UNMAPPED_GVA)
3648                         return X86EMUL_PROPAGATE_FAULT;
3649                 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3650                 if (ret < 0) {
3651                         r = X86EMUL_IO_NEEDED;
3652                         goto out;
3653                 }
3654
3655                 bytes -= towrite;
3656                 data += towrite;
3657                 addr += towrite;
3658         }
3659 out:
3660         return r;
3661 }
3662 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
3663
3664 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3665                                 gpa_t *gpa, struct x86_exception *exception,
3666                                 bool write)
3667 {
3668         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3669
3670         if (vcpu_match_mmio_gva(vcpu, gva) &&
3671                   check_write_user_access(vcpu, write, access,
3672                   vcpu->arch.access)) {
3673                 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3674                                         (gva & (PAGE_SIZE - 1));
3675                 trace_vcpu_match_mmio(gva, *gpa, write, false);
3676                 return 1;
3677         }
3678
3679         if (write)
3680                 access |= PFERR_WRITE_MASK;
3681
3682         *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3683
3684         if (*gpa == UNMAPPED_GVA)
3685                 return -1;
3686
3687         /* For APIC access vmexit */
3688         if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3689                 return 1;
3690
3691         if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
3692                 trace_vcpu_match_mmio(gva, *gpa, write, true);
3693                 return 1;
3694         }
3695
3696         return 0;
3697 }
3698
3699 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
3700                         const void *val, int bytes)
3701 {
3702         int ret;
3703
3704         ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
3705         if (ret < 0)
3706                 return 0;
3707         kvm_mmu_pte_write(vcpu, gpa, val, bytes);
3708         return 1;
3709 }
3710
3711 struct read_write_emulator_ops {
3712         int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
3713                                   int bytes);
3714         int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
3715                                   void *val, int bytes);
3716         int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3717                                int bytes, void *val);
3718         int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3719                                     void *val, int bytes);
3720         bool write;
3721 };
3722
3723 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
3724 {
3725         if (vcpu->mmio_read_completed) {
3726                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3727                                vcpu->mmio_fragments[0].gpa, *(u64 *)val);
3728                 vcpu->mmio_read_completed = 0;
3729                 return 1;
3730         }
3731
3732         return 0;
3733 }
3734
3735 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3736                         void *val, int bytes)
3737 {
3738         return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
3739 }
3740
3741 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3742                          void *val, int bytes)
3743 {
3744         return emulator_write_phys(vcpu, gpa, val, bytes);
3745 }
3746
3747 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
3748 {
3749         trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
3750         return vcpu_mmio_write(vcpu, gpa, bytes, val);
3751 }
3752
3753 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3754                           void *val, int bytes)
3755 {
3756         trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
3757         return X86EMUL_IO_NEEDED;
3758 }
3759
3760 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3761                            void *val, int bytes)
3762 {
3763         struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
3764
3765         memcpy(vcpu->run->mmio.data, frag->data, frag->len);
3766         return X86EMUL_CONTINUE;
3767 }
3768
3769 static struct read_write_emulator_ops read_emultor = {
3770         .read_write_prepare = read_prepare,
3771         .read_write_emulate = read_emulate,
3772         .read_write_mmio = vcpu_mmio_read,
3773         .read_write_exit_mmio = read_exit_mmio,
3774 };
3775
3776 static struct read_write_emulator_ops write_emultor = {
3777         .read_write_emulate = write_emulate,
3778         .read_write_mmio = write_mmio,
3779         .read_write_exit_mmio = write_exit_mmio,
3780         .write = true,
3781 };
3782
3783 static int emulator_read_write_onepage(unsigned long addr, void *val,
3784                                        unsigned int bytes,
3785                                        struct x86_exception *exception,
3786                                        struct kvm_vcpu *vcpu,
3787                                        struct read_write_emulator_ops *ops)
3788 {
3789         gpa_t gpa;
3790         int handled, ret;
3791         bool write = ops->write;
3792         struct kvm_mmio_fragment *frag;
3793
3794         ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
3795
3796         if (ret < 0)
3797                 return X86EMUL_PROPAGATE_FAULT;
3798
3799         /* For APIC access vmexit */
3800         if (ret)
3801                 goto mmio;
3802
3803         if (ops->read_write_emulate(vcpu, gpa, val, bytes))
3804                 return X86EMUL_CONTINUE;
3805
3806 mmio:
3807         /*
3808          * Is this MMIO handled locally?
3809          */
3810         handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
3811         if (handled == bytes)
3812                 return X86EMUL_CONTINUE;
3813
3814         gpa += handled;
3815         bytes -= handled;
3816         val += handled;
3817
3818         while (bytes) {
3819                 unsigned now = min(bytes, 8U);
3820
3821                 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
3822                 frag->gpa = gpa;
3823                 frag->data = val;
3824                 frag->len = now;
3825
3826                 gpa += now;
3827                 val += now;
3828                 bytes -= now;
3829         }
3830         return X86EMUL_CONTINUE;
3831 }
3832
3833 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
3834                         void *val, unsigned int bytes,
3835                         struct x86_exception *exception,
3836                         struct read_write_emulator_ops *ops)
3837 {
3838         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3839         gpa_t gpa;
3840         int rc;
3841
3842         if (ops->read_write_prepare &&
3843                   ops->read_write_prepare(vcpu, val, bytes))
3844                 return X86EMUL_CONTINUE;
3845
3846         vcpu->mmio_nr_fragments = 0;
3847
3848         /* Crossing a page boundary? */
3849         if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3850                 int now;
3851
3852                 now = -addr & ~PAGE_MASK;
3853                 rc = emulator_read_write_onepage(addr, val, now, exception,
3854                                                  vcpu, ops);
3855
3856                 if (rc != X86EMUL_CONTINUE)
3857                         return rc;
3858                 addr += now;
3859                 val += now;
3860                 bytes -= now;
3861         }
3862
3863         rc = emulator_read_write_onepage(addr, val, bytes, exception,
3864                                          vcpu, ops);
3865         if (rc != X86EMUL_CONTINUE)
3866                 return rc;
3867
3868         if (!vcpu->mmio_nr_fragments)
3869                 return rc;
3870
3871         gpa = vcpu->mmio_fragments[0].gpa;
3872
3873         vcpu->mmio_needed = 1;
3874         vcpu->mmio_cur_fragment = 0;
3875
3876         vcpu->run->mmio.len = vcpu->mmio_fragments[0].len;
3877         vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
3878         vcpu->run->exit_reason = KVM_EXIT_MMIO;
3879         vcpu->run->mmio.phys_addr = gpa;
3880
3881         return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
3882 }
3883
3884 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
3885                                   unsigned long addr,
3886                                   void *val,
3887                                   unsigned int bytes,
3888                                   struct x86_exception *exception)
3889 {
3890         return emulator_read_write(ctxt, addr, val, bytes,
3891                                    exception, &read_emultor);
3892 }
3893
3894 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
3895                             unsigned long addr,
3896                             const void *val,
3897                             unsigned int bytes,
3898                             struct x86_exception *exception)
3899 {
3900         return emulator_read_write(ctxt, addr, (void *)val, bytes,
3901                                    exception, &write_emultor);
3902 }
3903
3904 #define CMPXCHG_TYPE(t, ptr, old, new) \
3905         (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3906
3907 #ifdef CONFIG_X86_64
3908 #  define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3909 #else
3910 #  define CMPXCHG64(ptr, old, new) \
3911         (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
3912 #endif
3913
3914 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
3915                                      unsigned long addr,
3916                                      const void *old,
3917                                      const void *new,
3918                                      unsigned int bytes,
3919                                      struct x86_exception *exception)
3920 {
3921         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3922         gpa_t gpa;
3923         struct page *page;
3924         char *kaddr;
3925         bool exchanged;
3926
3927         /* guests cmpxchg8b have to be emulated atomically */
3928         if (bytes > 8 || (bytes & (bytes - 1)))
3929                 goto emul_write;
3930
3931         gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
3932
3933         if (gpa == UNMAPPED_GVA ||
3934             (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3935                 goto emul_write;
3936
3937         if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3938                 goto emul_write;
3939
3940         page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
3941         if (is_error_page(page))
3942                 goto emul_write;
3943
3944         kaddr = kmap_atomic(page);
3945         kaddr += offset_in_page(gpa);
3946         switch (bytes) {
3947         case 1:
3948                 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3949                 break;
3950         case 2:
3951                 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3952                 break;
3953         case 4:
3954                 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3955                 break;
3956         case 8:
3957                 exchanged = CMPXCHG64(kaddr, old, new);
3958                 break;
3959         default:
3960                 BUG();
3961         }
3962         kunmap_atomic(kaddr);
3963         kvm_release_page_dirty(page);
3964
3965         if (!exchanged)
3966                 return X86EMUL_CMPXCHG_FAILED;
3967
3968         kvm_mmu_pte_write(vcpu, gpa, new, bytes);
3969
3970         return X86EMUL_CONTINUE;
3971
3972 emul_write:
3973         printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
3974
3975         return emulator_write_emulated(ctxt, addr, new, bytes, exception);
3976 }
3977
3978 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3979 {
3980         /* TODO: String I/O for in kernel device */
3981         int r;
3982
3983         if (vcpu->arch.pio.in)
3984                 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3985                                     vcpu->arch.pio.size, pd);
3986         else
3987                 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3988                                      vcpu->arch.pio.port, vcpu->arch.pio.size,
3989                                      pd);
3990         return r;
3991 }
3992
3993 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
3994                                unsigned short port, void *val,
3995                                unsigned int count, bool in)
3996 {
3997         trace_kvm_pio(!in, port, size, count);
3998
3999         vcpu->arch.pio.port = port;
4000         vcpu->arch.pio.in = in;
4001         vcpu->arch.pio.count  = count;
4002         vcpu->arch.pio.size = size;
4003
4004         if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4005                 vcpu->arch.pio.count = 0;
4006                 return 1;
4007         }
4008
4009         vcpu->run->exit_reason = KVM_EXIT_IO;
4010         vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4011         vcpu->run->io.size = size;
4012         vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4013         vcpu->run->io.count = count;
4014         vcpu->run->io.port = port;
4015
4016         return 0;
4017 }
4018
4019 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4020                                     int size, unsigned short port, void *val,
4021                                     unsigned int count)
4022 {
4023         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4024         int ret;
4025
4026         if (vcpu->arch.pio.count)
4027                 goto data_avail;
4028
4029         ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4030         if (ret) {
4031 data_avail:
4032                 memcpy(val, vcpu->arch.pio_data, size * count);
4033                 vcpu->arch.pio.count = 0;
4034                 return 1;
4035         }
4036
4037         return 0;
4038 }
4039
4040 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4041                                      int size, unsigned short port,
4042                                      const void *val, unsigned int count)
4043 {
4044         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4045
4046         memcpy(vcpu->arch.pio_data, val, size * count);
4047         return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4048 }
4049
4050 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4051 {
4052         return kvm_x86_ops->get_segment_base(vcpu, seg);
4053 }
4054
4055 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4056 {
4057         kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4058 }
4059
4060 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4061 {
4062         if (!need_emulate_wbinvd(vcpu))
4063                 return X86EMUL_CONTINUE;
4064
4065         if (kvm_x86_ops->has_wbinvd_exit()) {
4066                 int cpu = get_cpu();
4067
4068                 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4069                 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4070                                 wbinvd_ipi, NULL, 1);
4071                 put_cpu();
4072                 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4073         } else
4074                 wbinvd();
4075         return X86EMUL_CONTINUE;
4076 }
4077 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4078
4079 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4080 {
4081         kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4082 }
4083
4084 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
4085 {
4086         return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4087 }
4088
4089 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
4090 {
4091
4092         return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4093 }
4094
4095 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4096 {
4097         return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4098 }
4099
4100 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4101 {
4102         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4103         unsigned long value;
4104
4105         switch (cr) {
4106         case 0:
4107                 value = kvm_read_cr0(vcpu);
4108                 break;
4109         case 2:
4110                 value = vcpu->arch.cr2;
4111                 break;
4112         case 3:
4113                 value = kvm_read_cr3(vcpu);
4114                 break;
4115         case 4:
4116                 value = kvm_read_cr4(vcpu);
4117                 break;
4118         case 8:
4119                 value = kvm_get_cr8(vcpu);
4120                 break;
4121         default:
4122                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4123                 return 0;
4124         }
4125
4126         return value;
4127 }
4128
4129 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4130 {
4131         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4132         int res = 0;
4133
4134         switch (cr) {
4135         case 0:
4136                 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4137                 break;
4138         case 2:
4139                 vcpu->arch.cr2 = val;
4140                 break;
4141         case 3:
4142                 res = kvm_set_cr3(vcpu, val);
4143                 break;
4144         case 4:
4145                 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4146                 break;
4147         case 8:
4148                 res = kvm_set_cr8(vcpu, val);
4149                 break;
4150         default:
4151                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4152                 res = -1;
4153         }
4154
4155         return res;
4156 }
4157
4158 static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4159 {
4160         kvm_set_rflags(emul_to_vcpu(ctxt), val);
4161 }
4162
4163 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4164 {
4165         return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4166 }
4167
4168 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4169 {
4170         kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4171 }
4172
4173 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4174 {
4175         kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4176 }
4177
4178 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4179 {
4180         kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4181 }
4182
4183 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4184 {
4185         kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4186 }
4187
4188 static unsigned long emulator_get_cached_segment_base(
4189         struct x86_emulate_ctxt *ctxt, int seg)
4190 {
4191         return get_segment_base(emul_to_vcpu(ctxt), seg);
4192 }
4193
4194 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4195                                  struct desc_struct *desc, u32 *base3,
4196                                  int seg)
4197 {
4198         struct kvm_segment var;
4199
4200         kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4201         *selector = var.selector;
4202
4203         if (var.unusable)
4204                 return false;
4205
4206         if (var.g)
4207                 var.limit >>= 12;
4208         set_desc_limit(desc, var.limit);
4209         set_desc_base(desc, (unsigned long)var.base);
4210 #ifdef CONFIG_X86_64
4211         if (base3)
4212                 *base3 = var.base >> 32;
4213 #endif
4214         desc->type = var.type;
4215         desc->s = var.s;
4216         desc->dpl = var.dpl;
4217         desc->p = var.present;
4218         desc->avl = var.avl;
4219         desc->l = var.l;
4220         desc->d = var.db;
4221         desc->g = var.g;
4222
4223         return true;
4224 }
4225
4226 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4227                                  struct desc_struct *desc, u32 base3,
4228                                  int seg)
4229 {
4230         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4231         struct kvm_segment var;
4232
4233         var.selector = selector;
4234         var.base = get_desc_base(desc);
4235 #ifdef CONFIG_X86_64
4236         var.base |= ((u64)base3) << 32;
4237 #endif
4238         var.limit = get_desc_limit(desc);
4239         if (desc->g)
4240                 var.limit = (var.limit << 12) | 0xfff;
4241         var.type = desc->type;
4242         var.present = desc->p;
4243         var.dpl = desc->dpl;
4244         var.db = desc->d;
4245         var.s = desc->s;
4246         var.l = desc->l;
4247         var.g = desc->g;
4248         var.avl = desc->avl;
4249         var.present = desc->p;
4250         var.unusable = !var.present;
4251         var.padding = 0;
4252
4253         kvm_set_segment(vcpu, &var, seg);
4254         return;
4255 }
4256
4257 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4258                             u32 msr_index, u64 *pdata)
4259 {
4260         return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4261 }
4262
4263 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4264                             u32 msr_index, u64 data)
4265 {
4266         return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4267 }
4268
4269 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4270                              u32 pmc, u64 *pdata)
4271 {
4272         return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4273 }
4274
4275 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4276 {
4277         emul_to_vcpu(ctxt)->arch.halt_request = 1;
4278 }
4279
4280 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4281 {
4282         preempt_disable();
4283         kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4284         /*
4285          * CR0.TS may reference the host fpu state, not the guest fpu state,
4286          * so it may be clear at this point.
4287          */
4288         clts();
4289 }
4290
4291 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4292 {
4293         preempt_enable();
4294 }
4295
4296 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4297                               struct x86_instruction_info *info,
4298                               enum x86_intercept_stage stage)
4299 {
4300         return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4301 }
4302
4303 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4304                                u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4305 {
4306         kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4307 }
4308
4309 static struct x86_emulate_ops emulate_ops = {
4310         .read_std            = kvm_read_guest_virt_system,
4311         .write_std           = kvm_write_guest_virt_system,
4312         .fetch               = kvm_fetch_guest_virt,
4313         .read_emulated       = emulator_read_emulated,
4314         .write_emulated      = emulator_write_emulated,
4315         .cmpxchg_emulated    = emulator_cmpxchg_emulated,
4316         .invlpg              = emulator_invlpg,
4317         .pio_in_emulated     = emulator_pio_in_emulated,
4318         .pio_out_emulated    = emulator_pio_out_emulated,
4319         .get_segment         = emulator_get_segment,
4320         .set_segment         = emulator_set_segment,
4321         .get_cached_segment_base = emulator_get_cached_segment_base,
4322         .get_gdt             = emulator_get_gdt,
4323         .get_idt             = emulator_get_idt,
4324         .set_gdt             = emulator_set_gdt,
4325         .set_idt             = emulator_set_idt,
4326         .get_cr              = emulator_get_cr,
4327         .set_cr              = emulator_set_cr,
4328         .set_rflags          = emulator_set_rflags,
4329         .cpl                 = emulator_get_cpl,
4330         .get_dr              = emulator_get_dr,
4331         .set_dr              = emulator_set_dr,
4332         .set_msr             = emulator_set_msr,
4333         .get_msr             = emulator_get_msr,
4334         .read_pmc            = emulator_read_pmc,
4335         .halt                = emulator_halt,
4336         .wbinvd              = emulator_wbinvd,
4337         .fix_hypercall       = emulator_fix_hypercall,
4338         .get_fpu             = emulator_get_fpu,
4339         .put_fpu             = emulator_put_fpu,
4340         .intercept           = emulator_intercept,
4341         .get_cpuid           = emulator_get_cpuid,
4342 };
4343
4344 static void cache_all_regs(struct kvm_vcpu *vcpu)
4345 {
4346         kvm_register_read(vcpu, VCPU_REGS_RAX);
4347         kvm_register_read(vcpu, VCPU_REGS_RSP);
4348         kvm_register_read(vcpu, VCPU_REGS_RIP);
4349         vcpu->arch.regs_dirty = ~0;
4350 }
4351
4352 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4353 {
4354         u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4355         /*
4356          * an sti; sti; sequence only disable interrupts for the first
4357          * instruction. So, if the last instruction, be it emulated or
4358          * not, left the system with the INT_STI flag enabled, it
4359          * means that the last instruction is an sti. We should not
4360          * leave the flag on in this case. The same goes for mov ss
4361          */
4362         if (!(int_shadow & mask))
4363                 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4364 }
4365
4366 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4367 {
4368         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4369         if (ctxt->exception.vector == PF_VECTOR)
4370                 kvm_propagate_fault(vcpu, &ctxt->exception);
4371         else if (ctxt->exception.error_code_valid)
4372                 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4373                                       ctxt->exception.error_code);
4374         else
4375                 kvm_queue_exception(vcpu, ctxt->exception.vector);
4376 }
4377
4378 static void init_decode_cache(struct x86_emulate_ctxt *ctxt,
4379                               const unsigned long *regs)
4380 {
4381         memset(&ctxt->twobyte, 0,
4382                (void *)&ctxt->regs - (void *)&ctxt->twobyte);
4383         memcpy(ctxt->regs, regs, sizeof(ctxt->regs));
4384
4385         ctxt->fetch.start = 0;
4386         ctxt->fetch.end = 0;
4387         ctxt->io_read.pos = 0;
4388         ctxt->io_read.end = 0;
4389         ctxt->mem_read.pos = 0;
4390         ctxt->mem_read.end = 0;
4391 }
4392
4393 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4394 {
4395         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4396         int cs_db, cs_l;
4397
4398         /*
4399          * TODO: fix emulate.c to use guest_read/write_register
4400          * instead of direct ->regs accesses, can save hundred cycles
4401          * on Intel for instructions that don't read/change RSP, for
4402          * for example.
4403          */
4404         cache_all_regs(vcpu);
4405
4406         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4407
4408         ctxt->eflags = kvm_get_rflags(vcpu);
4409         ctxt->eip = kvm_rip_read(vcpu);
4410         ctxt->mode = (!is_protmode(vcpu))               ? X86EMUL_MODE_REAL :
4411                      (ctxt->eflags & X86_EFLAGS_VM)     ? X86EMUL_MODE_VM86 :
4412                      cs_l                               ? X86EMUL_MODE_PROT64 :
4413                      cs_db                              ? X86EMUL_MODE_PROT32 :
4414                                                           X86EMUL_MODE_PROT16;
4415         ctxt->guest_mode = is_guest_mode(vcpu);
4416
4417         init_decode_cache(ctxt, vcpu->arch.regs);
4418         vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4419 }
4420
4421 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4422 {
4423         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4424         int ret;
4425
4426         init_emulate_ctxt(vcpu);
4427
4428         ctxt->op_bytes = 2;
4429         ctxt->ad_bytes = 2;
4430         ctxt->_eip = ctxt->eip + inc_eip;
4431         ret = emulate_int_real(ctxt, irq);
4432
4433         if (ret != X86EMUL_CONTINUE)
4434                 return EMULATE_FAIL;
4435
4436         ctxt->eip = ctxt->_eip;
4437         memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
4438         kvm_rip_write(vcpu, ctxt->eip);
4439         kvm_set_rflags(vcpu, ctxt->eflags);
4440
4441         if (irq == NMI_VECTOR)
4442                 vcpu->arch.nmi_pending = 0;
4443         else
4444                 vcpu->arch.interrupt.pending = false;
4445
4446         return EMULATE_DONE;
4447 }
4448 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4449
4450 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4451 {
4452         int r = EMULATE_DONE;
4453
4454         ++vcpu->stat.insn_emulation_fail;
4455         trace_kvm_emulate_insn_failed(vcpu);
4456         if (!is_guest_mode(vcpu)) {
4457                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4458                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4459                 vcpu->run->internal.ndata = 0;
4460                 r = EMULATE_FAIL;
4461         }
4462         kvm_queue_exception(vcpu, UD_VECTOR);
4463
4464         return r;
4465 }
4466
4467 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4468 {
4469         gpa_t gpa;
4470
4471         if (tdp_enabled)
4472                 return false;
4473
4474         /*
4475          * if emulation was due to access to shadowed page table
4476          * and it failed try to unshadow page and re-enter the
4477          * guest to let CPU execute the instruction.
4478          */
4479         if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4480                 return true;
4481
4482         gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4483
4484         if (gpa == UNMAPPED_GVA)
4485                 return true; /* let cpu generate fault */
4486
4487         if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4488                 return true;
4489
4490         return false;
4491 }
4492
4493 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4494                               unsigned long cr2,  int emulation_type)
4495 {
4496         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4497         unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4498
4499         last_retry_eip = vcpu->arch.last_retry_eip;
4500         last_retry_addr = vcpu->arch.last_retry_addr;
4501
4502         /*
4503          * If the emulation is caused by #PF and it is non-page_table
4504          * writing instruction, it means the VM-EXIT is caused by shadow
4505          * page protected, we can zap the shadow page and retry this
4506          * instruction directly.
4507          *
4508          * Note: if the guest uses a non-page-table modifying instruction
4509          * on the PDE that points to the instruction, then we will unmap
4510          * the instruction and go to an infinite loop. So, we cache the
4511          * last retried eip and the last fault address, if we meet the eip
4512          * and the address again, we can break out of the potential infinite
4513          * loop.
4514          */
4515         vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4516
4517         if (!(emulation_type & EMULTYPE_RETRY))
4518                 return false;
4519
4520         if (x86_page_table_writing_insn(ctxt))
4521                 return false;
4522
4523         if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4524                 return false;
4525
4526         vcpu->arch.last_retry_eip = ctxt->eip;
4527         vcpu->arch.last_retry_addr = cr2;
4528
4529         if (!vcpu->arch.mmu.direct_map)
4530                 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4531
4532         kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4533
4534         return true;
4535 }
4536
4537 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4538                             unsigned long cr2,
4539                             int emulation_type,
4540                             void *insn,
4541                             int insn_len)
4542 {
4543         int r;
4544         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4545         bool writeback = true;
4546
4547         kvm_clear_exception_queue(vcpu);
4548
4549         if (!(emulation_type & EMULTYPE_NO_DECODE)) {
4550                 init_emulate_ctxt(vcpu);
4551                 ctxt->interruptibility = 0;
4552                 ctxt->have_exception = false;
4553                 ctxt->perm_ok = false;
4554
4555                 ctxt->only_vendor_specific_insn
4556                         = emulation_type & EMULTYPE_TRAP_UD;
4557
4558                 r = x86_decode_insn(ctxt, insn, insn_len);
4559
4560                 trace_kvm_emulate_insn_start(vcpu);
4561                 ++vcpu->stat.insn_emulation;
4562                 if (r != EMULATION_OK)  {
4563                         if (emulation_type & EMULTYPE_TRAP_UD)
4564                                 return EMULATE_FAIL;
4565                         if (reexecute_instruction(vcpu, cr2))
4566                                 return EMULATE_DONE;
4567                         if (emulation_type & EMULTYPE_SKIP)
4568                                 return EMULATE_FAIL;
4569                         return handle_emulation_failure(vcpu);
4570                 }
4571         }
4572
4573         if (emulation_type & EMULTYPE_SKIP) {
4574                 kvm_rip_write(vcpu, ctxt->_eip);
4575                 return EMULATE_DONE;
4576         }
4577
4578         if (retry_instruction(ctxt, cr2, emulation_type))
4579                 return EMULATE_DONE;
4580
4581         /* this is needed for vmware backdoor interface to work since it
4582            changes registers values  during IO operation */
4583         if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4584                 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4585                 memcpy(ctxt->regs, vcpu->arch.regs, sizeof ctxt->regs);
4586         }
4587
4588 restart:
4589         r = x86_emulate_insn(ctxt);
4590
4591         if (r == EMULATION_INTERCEPTED)
4592                 return EMULATE_DONE;
4593
4594         if (r == EMULATION_FAILED) {
4595                 if (reexecute_instruction(vcpu, cr2))
4596                         return EMULATE_DONE;
4597
4598                 return handle_emulation_failure(vcpu);
4599         }
4600
4601         if (ctxt->have_exception) {
4602                 inject_emulated_exception(vcpu);
4603                 r = EMULATE_DONE;
4604         } else if (vcpu->arch.pio.count) {
4605                 if (!vcpu->arch.pio.in)
4606                         vcpu->arch.pio.count = 0;
4607                 else
4608                         writeback = false;
4609                 r = EMULATE_DO_MMIO;
4610         } else if (vcpu->mmio_needed) {
4611                 if (!vcpu->mmio_is_write)
4612                         writeback = false;
4613                 r = EMULATE_DO_MMIO;
4614         } else if (r == EMULATION_RESTART)
4615                 goto restart;
4616         else
4617                 r = EMULATE_DONE;
4618
4619         if (writeback) {
4620                 toggle_interruptibility(vcpu, ctxt->interruptibility);
4621                 kvm_set_rflags(vcpu, ctxt->eflags);
4622                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4623                 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
4624                 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
4625                 kvm_rip_write(vcpu, ctxt->eip);
4626         } else
4627                 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
4628
4629         return r;
4630 }
4631 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
4632
4633 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
4634 {
4635         unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4636         int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4637                                             size, port, &val, 1);
4638         /* do not return to emulator after return from userspace */
4639         vcpu->arch.pio.count = 0;
4640         return ret;
4641 }
4642 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
4643
4644 static void tsc_bad(void *info)
4645 {
4646         __this_cpu_write(cpu_tsc_khz, 0);
4647 }
4648
4649 static void tsc_khz_changed(void *data)
4650 {
4651         struct cpufreq_freqs *freq = data;
4652         unsigned long khz = 0;
4653
4654         if (data)
4655                 khz = freq->new;
4656         else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4657                 khz = cpufreq_quick_get(raw_smp_processor_id());
4658         if (!khz)
4659                 khz = tsc_khz;
4660         __this_cpu_write(cpu_tsc_khz, khz);
4661 }
4662
4663 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4664                                      void *data)
4665 {
4666         struct cpufreq_freqs *freq = data;
4667         struct kvm *kvm;
4668         struct kvm_vcpu *vcpu;
4669         int i, send_ipi = 0;
4670
4671         /*
4672          * We allow guests to temporarily run on slowing clocks,
4673          * provided we notify them after, or to run on accelerating
4674          * clocks, provided we notify them before.  Thus time never
4675          * goes backwards.
4676          *
4677          * However, we have a problem.  We can't atomically update
4678          * the frequency of a given CPU from this function; it is
4679          * merely a notifier, which can be called from any CPU.
4680          * Changing the TSC frequency at arbitrary points in time
4681          * requires a recomputation of local variables related to
4682          * the TSC for each VCPU.  We must flag these local variables
4683          * to be updated and be sure the update takes place with the
4684          * new frequency before any guests proceed.
4685          *
4686          * Unfortunately, the combination of hotplug CPU and frequency
4687          * change creates an intractable locking scenario; the order
4688          * of when these callouts happen is undefined with respect to
4689          * CPU hotplug, and they can race with each other.  As such,
4690          * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4691          * undefined; you can actually have a CPU frequency change take
4692          * place in between the computation of X and the setting of the
4693          * variable.  To protect against this problem, all updates of
4694          * the per_cpu tsc_khz variable are done in an interrupt
4695          * protected IPI, and all callers wishing to update the value
4696          * must wait for a synchronous IPI to complete (which is trivial
4697          * if the caller is on the CPU already).  This establishes the
4698          * necessary total order on variable updates.
4699          *
4700          * Note that because a guest time update may take place
4701          * anytime after the setting of the VCPU's request bit, the
4702          * correct TSC value must be set before the request.  However,
4703          * to ensure the update actually makes it to any guest which
4704          * starts running in hardware virtualization between the set
4705          * and the acquisition of the spinlock, we must also ping the
4706          * CPU after setting the request bit.
4707          *
4708          */
4709
4710         if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4711                 return 0;
4712         if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4713                 return 0;
4714
4715         smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
4716
4717         raw_spin_lock(&kvm_lock);
4718         list_for_each_entry(kvm, &vm_list, vm_list) {
4719                 kvm_for_each_vcpu(i, vcpu, kvm) {
4720                         if (vcpu->cpu != freq->cpu)
4721                                 continue;
4722                         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4723                         if (vcpu->cpu != smp_processor_id())
4724                                 send_ipi = 1;
4725                 }
4726         }
4727         raw_spin_unlock(&kvm_lock);
4728
4729         if (freq->old < freq->new && send_ipi) {
4730                 /*
4731                  * We upscale the frequency.  Must make the guest
4732                  * doesn't see old kvmclock values while running with
4733                  * the new frequency, otherwise we risk the guest sees
4734                  * time go backwards.
4735                  *
4736                  * In case we update the frequency for another cpu
4737                  * (which might be in guest context) send an interrupt
4738                  * to kick the cpu out of guest context.  Next time
4739                  * guest context is entered kvmclock will be updated,
4740                  * so the guest will not see stale values.
4741                  */
4742                 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
4743         }
4744         return 0;
4745 }
4746
4747 static struct notifier_block kvmclock_cpufreq_notifier_block = {
4748         .notifier_call  = kvmclock_cpufreq_notifier
4749 };
4750
4751 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4752                                         unsigned long action, void *hcpu)
4753 {
4754         unsigned int cpu = (unsigned long)hcpu;
4755
4756         switch (action) {
4757                 case CPU_ONLINE:
4758                 case CPU_DOWN_FAILED:
4759                         smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4760                         break;
4761                 case CPU_DOWN_PREPARE:
4762                         smp_call_function_single(cpu, tsc_bad, NULL, 1);
4763                         break;
4764         }
4765         return NOTIFY_OK;
4766 }
4767
4768 static struct notifier_block kvmclock_cpu_notifier_block = {
4769         .notifier_call  = kvmclock_cpu_notifier,
4770         .priority = -INT_MAX
4771 };
4772
4773 static void kvm_timer_init(void)
4774 {
4775         int cpu;
4776
4777         max_tsc_khz = tsc_khz;
4778         register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
4779         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
4780 #ifdef CONFIG_CPU_FREQ
4781                 struct cpufreq_policy policy;
4782                 memset(&policy, 0, sizeof(policy));
4783                 cpu = get_cpu();
4784                 cpufreq_get_policy(&policy, cpu);
4785                 if (policy.cpuinfo.max_freq)
4786                         max_tsc_khz = policy.cpuinfo.max_freq;
4787                 put_cpu();
4788 #endif
4789                 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4790                                           CPUFREQ_TRANSITION_NOTIFIER);
4791         }
4792         pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
4793         for_each_online_cpu(cpu)
4794                 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4795 }
4796
4797 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4798
4799 int kvm_is_in_guest(void)
4800 {
4801         return __this_cpu_read(current_vcpu) != NULL;
4802 }
4803
4804 static int kvm_is_user_mode(void)
4805 {
4806         int user_mode = 3;
4807
4808         if (__this_cpu_read(current_vcpu))
4809                 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
4810
4811         return user_mode != 0;
4812 }
4813
4814 static unsigned long kvm_get_guest_ip(void)
4815 {
4816         unsigned long ip = 0;
4817
4818         if (__this_cpu_read(current_vcpu))
4819                 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
4820
4821         return ip;
4822 }
4823
4824 static struct perf_guest_info_callbacks kvm_guest_cbs = {
4825         .is_in_guest            = kvm_is_in_guest,
4826         .is_user_mode           = kvm_is_user_mode,
4827         .get_guest_ip           = kvm_get_guest_ip,
4828 };
4829
4830 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4831 {
4832         __this_cpu_write(current_vcpu, vcpu);
4833 }
4834 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4835
4836 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4837 {
4838         __this_cpu_write(current_vcpu, NULL);
4839 }
4840 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4841
4842 static void kvm_set_mmio_spte_mask(void)
4843 {
4844         u64 mask;
4845         int maxphyaddr = boot_cpu_data.x86_phys_bits;
4846
4847         /*
4848          * Set the reserved bits and the present bit of an paging-structure
4849          * entry to generate page fault with PFER.RSV = 1.
4850          */
4851         mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
4852         mask |= 1ull;
4853
4854 #ifdef CONFIG_X86_64
4855         /*
4856          * If reserved bit is not supported, clear the present bit to disable
4857          * mmio page fault.
4858          */
4859         if (maxphyaddr == 52)
4860                 mask &= ~1ull;
4861 #endif
4862
4863         kvm_mmu_set_mmio_spte_mask(mask);
4864 }
4865
4866 int kvm_arch_init(void *opaque)
4867 {
4868         int r;
4869         struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4870
4871         if (kvm_x86_ops) {
4872                 printk(KERN_ERR "kvm: already loaded the other module\n");
4873                 r = -EEXIST;
4874                 goto out;
4875         }
4876
4877         if (!ops->cpu_has_kvm_support()) {
4878                 printk(KERN_ERR "kvm: no hardware support\n");
4879                 r = -EOPNOTSUPP;
4880                 goto out;
4881         }
4882         if (ops->disabled_by_bios()) {
4883                 printk(KERN_ERR "kvm: disabled by bios\n");
4884                 r = -EOPNOTSUPP;
4885                 goto out;
4886         }
4887
4888         r = kvm_mmu_module_init();
4889         if (r)
4890                 goto out;
4891
4892         kvm_set_mmio_spte_mask();
4893         kvm_init_msr_list();
4894
4895         kvm_x86_ops = ops;
4896         kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4897                         PT_DIRTY_MASK, PT64_NX_MASK, 0);
4898
4899         kvm_timer_init();
4900
4901         perf_register_guest_info_callbacks(&kvm_guest_cbs);
4902
4903         if (cpu_has_xsave)
4904                 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4905
4906         return 0;
4907
4908 out:
4909         return r;
4910 }
4911
4912 void kvm_arch_exit(void)
4913 {
4914         perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4915
4916         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4917                 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4918                                             CPUFREQ_TRANSITION_NOTIFIER);
4919         unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
4920         kvm_x86_ops = NULL;
4921         kvm_mmu_module_exit();
4922 }
4923
4924 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4925 {
4926         ++vcpu->stat.halt_exits;
4927         if (irqchip_in_kernel(vcpu->kvm)) {
4928                 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
4929                 return 1;
4930         } else {
4931                 vcpu->run->exit_reason = KVM_EXIT_HLT;
4932                 return 0;
4933         }
4934 }
4935 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4936
4937 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4938 {
4939         u64 param, ingpa, outgpa, ret;
4940         uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4941         bool fast, longmode;
4942         int cs_db, cs_l;
4943
4944         /*
4945          * hypercall generates UD from non zero cpl and real mode
4946          * per HYPER-V spec
4947          */
4948         if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
4949                 kvm_queue_exception(vcpu, UD_VECTOR);
4950                 return 0;
4951         }
4952
4953         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4954         longmode = is_long_mode(vcpu) && cs_l == 1;
4955
4956         if (!longmode) {
4957                 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4958                         (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4959                 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4960                         (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4961                 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4962                         (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
4963         }
4964 #ifdef CONFIG_X86_64
4965         else {
4966                 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4967                 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4968                 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4969         }
4970 #endif
4971
4972         code = param & 0xffff;
4973         fast = (param >> 16) & 0x1;
4974         rep_cnt = (param >> 32) & 0xfff;
4975         rep_idx = (param >> 48) & 0xfff;
4976
4977         trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4978
4979         switch (code) {
4980         case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4981                 kvm_vcpu_on_spin(vcpu);
4982                 break;
4983         default:
4984                 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4985                 break;
4986         }
4987
4988         ret = res | (((u64)rep_done & 0xfff) << 32);
4989         if (longmode) {
4990                 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4991         } else {
4992                 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4993                 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4994         }
4995
4996         return 1;
4997 }
4998
4999 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5000 {
5001         unsigned long nr, a0, a1, a2, a3, ret;
5002         int r = 1;
5003
5004         if (kvm_hv_hypercall_enabled(vcpu->kvm))
5005                 return kvm_hv_hypercall(vcpu);
5006
5007         nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5008         a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5009         a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5010         a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5011         a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5012
5013         trace_kvm_hypercall(nr, a0, a1, a2, a3);
5014
5015         if (!is_long_mode(vcpu)) {
5016                 nr &= 0xFFFFFFFF;
5017                 a0 &= 0xFFFFFFFF;
5018                 a1 &= 0xFFFFFFFF;
5019                 a2 &= 0xFFFFFFFF;
5020                 a3 &= 0xFFFFFFFF;
5021         }
5022
5023         if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5024                 ret = -KVM_EPERM;
5025                 goto out;
5026         }
5027
5028         switch (nr) {
5029         case KVM_HC_VAPIC_POLL_IRQ:
5030                 ret = 0;
5031                 break;
5032         default:
5033                 ret = -KVM_ENOSYS;
5034                 break;
5035         }
5036 out:
5037         kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5038         ++vcpu->stat.hypercalls;
5039         return r;
5040 }
5041 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5042
5043 int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5044 {
5045         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5046         char instruction[3];
5047         unsigned long rip = kvm_rip_read(vcpu);
5048
5049         /*
5050          * Blow out the MMU to ensure that no other VCPU has an active mapping
5051          * to ensure that the updated hypercall appears atomically across all
5052          * VCPUs.
5053          */
5054         kvm_mmu_zap_all(vcpu->kvm);
5055
5056         kvm_x86_ops->patch_hypercall(vcpu, instruction);
5057
5058         return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5059 }
5060
5061 /*
5062  * Check if userspace requested an interrupt window, and that the
5063  * interrupt window is open.
5064  *
5065  * No need to exit to userspace if we already have an interrupt queued.
5066  */
5067 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5068 {
5069         return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5070                 vcpu->run->request_interrupt_window &&
5071                 kvm_arch_interrupt_allowed(vcpu));
5072 }
5073
5074 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5075 {
5076         struct kvm_run *kvm_run = vcpu->run;
5077
5078         kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5079         kvm_run->cr8 = kvm_get_cr8(vcpu);
5080         kvm_run->apic_base = kvm_get_apic_base(vcpu);
5081         if (irqchip_in_kernel(vcpu->kvm))
5082                 kvm_run->ready_for_interrupt_injection = 1;
5083         else
5084                 kvm_run->ready_for_interrupt_injection =
5085                         kvm_arch_interrupt_allowed(vcpu) &&
5086                         !kvm_cpu_has_interrupt(vcpu) &&
5087                         !kvm_event_needs_reinjection(vcpu);
5088 }
5089
5090 static void vapic_enter(struct kvm_vcpu *vcpu)
5091 {
5092         struct kvm_lapic *apic = vcpu->arch.apic;
5093         struct page *page;
5094
5095         if (!apic || !apic->vapic_addr)
5096                 return;
5097
5098         page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5099
5100         vcpu->arch.apic->vapic_page = page;
5101 }
5102
5103 static void vapic_exit(struct kvm_vcpu *vcpu)
5104 {
5105         struct kvm_lapic *apic = vcpu->arch.apic;
5106         int idx;
5107
5108         if (!apic || !apic->vapic_addr)
5109                 return;
5110
5111         idx = srcu_read_lock(&vcpu->kvm->srcu);
5112         kvm_release_page_dirty(apic->vapic_page);
5113         mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5114         srcu_read_unlock(&vcpu->kvm->srcu, idx);
5115 }
5116
5117 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5118 {
5119         int max_irr, tpr;
5120
5121         if (!kvm_x86_ops->update_cr8_intercept)
5122                 return;
5123
5124         if (!vcpu->arch.apic)
5125                 return;
5126
5127         if (!vcpu->arch.apic->vapic_addr)
5128                 max_irr = kvm_lapic_find_highest_irr(vcpu);
5129         else
5130                 max_irr = -1;
5131
5132         if (max_irr != -1)
5133                 max_irr >>= 4;
5134
5135         tpr = kvm_lapic_get_cr8(vcpu);
5136
5137         kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5138 }
5139
5140 static void inject_pending_event(struct kvm_vcpu *vcpu)
5141 {
5142         /* try to reinject previous events if any */
5143         if (vcpu->arch.exception.pending) {
5144                 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5145                                         vcpu->arch.exception.has_error_code,
5146                                         vcpu->arch.exception.error_code);
5147                 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5148                                           vcpu->arch.exception.has_error_code,
5149                                           vcpu->arch.exception.error_code,
5150                                           vcpu->arch.exception.reinject);
5151                 return;
5152         }
5153
5154         if (vcpu->arch.nmi_injected) {
5155                 kvm_x86_ops->set_nmi(vcpu);
5156                 return;
5157         }
5158
5159         if (vcpu->arch.interrupt.pending) {
5160                 kvm_x86_ops->set_irq(vcpu);
5161                 return;
5162         }
5163
5164         /* try to inject new event if pending */
5165         if (vcpu->arch.nmi_pending) {
5166                 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5167                         --vcpu->arch.nmi_pending;
5168                         vcpu->arch.nmi_injected = true;
5169                         kvm_x86_ops->set_nmi(vcpu);
5170                 }
5171         } else if (kvm_cpu_has_interrupt(vcpu)) {
5172                 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5173                         kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5174                                             false);
5175                         kvm_x86_ops->set_irq(vcpu);
5176                 }
5177         }
5178 }
5179
5180 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5181 {
5182         if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5183                         !vcpu->guest_xcr0_loaded) {
5184                 /* kvm_set_xcr() also depends on this */
5185                 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5186                 vcpu->guest_xcr0_loaded = 1;
5187         }
5188 }
5189
5190 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5191 {
5192         if (vcpu->guest_xcr0_loaded) {
5193                 if (vcpu->arch.xcr0 != host_xcr0)
5194                         xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5195                 vcpu->guest_xcr0_loaded = 0;
5196         }
5197 }
5198
5199 static void process_nmi(struct kvm_vcpu *vcpu)
5200 {
5201         unsigned limit = 2;
5202
5203         /*
5204          * x86 is limited to one NMI running, and one NMI pending after it.
5205          * If an NMI is already in progress, limit further NMIs to just one.
5206          * Otherwise, allow two (and we'll inject the first one immediately).
5207          */
5208         if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5209                 limit = 1;
5210
5211         vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5212         vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5213         kvm_make_request(KVM_REQ_EVENT, vcpu);
5214 }
5215
5216 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
5217 {
5218         int r;
5219         bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
5220                 vcpu->run->request_interrupt_window;
5221         bool req_immediate_exit = 0;
5222
5223         if (vcpu->requests) {
5224                 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
5225                         kvm_mmu_unload(vcpu);
5226                 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
5227                         __kvm_migrate_timers(vcpu);
5228                 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5229                         r = kvm_guest_time_update(vcpu);
5230                         if (unlikely(r))
5231                                 goto out;
5232                 }
5233                 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
5234                         kvm_mmu_sync_roots(vcpu);
5235                 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
5236                         kvm_x86_ops->tlb_flush(vcpu);
5237                 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
5238                         vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
5239                         r = 0;
5240                         goto out;
5241                 }
5242                 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
5243                         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5244                         r = 0;
5245                         goto out;
5246                 }
5247                 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
5248                         vcpu->fpu_active = 0;
5249                         kvm_x86_ops->fpu_deactivate(vcpu);
5250                 }
5251                 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5252                         /* Page is swapped out. Do synthetic halt */
5253                         vcpu->arch.apf.halted = true;
5254                         r = 1;
5255                         goto out;
5256                 }
5257                 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5258                         record_steal_time(vcpu);
5259                 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5260                         process_nmi(vcpu);
5261                 req_immediate_exit =
5262                         kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
5263                 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5264                         kvm_handle_pmu_event(vcpu);
5265                 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5266                         kvm_deliver_pmi(vcpu);
5267         }
5268
5269         if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5270                 inject_pending_event(vcpu);
5271
5272                 /* enable NMI/IRQ window open exits if needed */
5273                 if (vcpu->arch.nmi_pending)
5274                         kvm_x86_ops->enable_nmi_window(vcpu);
5275                 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5276                         kvm_x86_ops->enable_irq_window(vcpu);
5277
5278                 if (kvm_lapic_enabled(vcpu)) {
5279                         update_cr8_intercept(vcpu);
5280                         kvm_lapic_sync_to_vapic(vcpu);
5281                 }
5282         }
5283
5284         r = kvm_mmu_reload(vcpu);
5285         if (unlikely(r)) {
5286                 goto cancel_injection;
5287         }
5288
5289         preempt_disable();
5290
5291         kvm_x86_ops->prepare_guest_switch(vcpu);
5292         if (vcpu->fpu_active)
5293                 kvm_load_guest_fpu(vcpu);
5294         kvm_load_guest_xcr0(vcpu);
5295
5296         vcpu->mode = IN_GUEST_MODE;
5297
5298         /* We should set ->mode before check ->requests,
5299          * see the comment in make_all_cpus_request.
5300          */
5301         smp_mb();
5302
5303         local_irq_disable();
5304
5305         if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
5306             || need_resched() || signal_pending(current)) {
5307                 vcpu->mode = OUTSIDE_GUEST_MODE;
5308                 smp_wmb();
5309                 local_irq_enable();
5310                 preempt_enable();
5311                 r = 1;
5312                 goto cancel_injection;
5313         }
5314
5315         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5316
5317         if (req_immediate_exit)
5318                 smp_send_reschedule(vcpu->cpu);
5319
5320         kvm_guest_enter();
5321
5322         if (unlikely(vcpu->arch.switch_db_regs)) {
5323                 set_debugreg(0, 7);
5324                 set_debugreg(vcpu->arch.eff_db[0], 0);
5325                 set_debugreg(vcpu->arch.eff_db[1], 1);
5326                 set_debugreg(vcpu->arch.eff_db[2], 2);
5327                 set_debugreg(vcpu->arch.eff_db[3], 3);
5328         }
5329
5330         trace_kvm_entry(vcpu->vcpu_id);
5331         kvm_x86_ops->run(vcpu);
5332
5333         /*
5334          * If the guest has used debug registers, at least dr7
5335          * will be disabled while returning to the host.
5336          * If we don't have active breakpoints in the host, we don't
5337          * care about the messed up debug address registers. But if
5338          * we have some of them active, restore the old state.
5339          */
5340         if (hw_breakpoint_active())
5341                 hw_breakpoint_restore();
5342
5343         vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
5344
5345         vcpu->mode = OUTSIDE_GUEST_MODE;
5346         smp_wmb();
5347         local_irq_enable();
5348
5349         ++vcpu->stat.exits;
5350
5351         /*
5352          * We must have an instruction between local_irq_enable() and
5353          * kvm_guest_exit(), so the timer interrupt isn't delayed by
5354          * the interrupt shadow.  The stat.exits increment will do nicely.
5355          * But we need to prevent reordering, hence this barrier():
5356          */
5357         barrier();
5358
5359         kvm_guest_exit();
5360
5361         preempt_enable();
5362
5363         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5364
5365         /*
5366          * Profile KVM exit RIPs:
5367          */
5368         if (unlikely(prof_on == KVM_PROFILING)) {
5369                 unsigned long rip = kvm_rip_read(vcpu);
5370                 profile_hit(KVM_PROFILING, (void *)rip);
5371         }
5372
5373         if (unlikely(vcpu->arch.tsc_always_catchup))
5374                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5375
5376         if (vcpu->arch.apic_attention)
5377                 kvm_lapic_sync_from_vapic(vcpu);
5378
5379         r = kvm_x86_ops->handle_exit(vcpu);
5380         return r;
5381
5382 cancel_injection:
5383         kvm_x86_ops->cancel_injection(vcpu);
5384         if (unlikely(vcpu->arch.apic_attention))
5385                 kvm_lapic_sync_from_vapic(vcpu);
5386 out:
5387         return r;
5388 }
5389
5390
5391 static int __vcpu_run(struct kvm_vcpu *vcpu)
5392 {
5393         int r;
5394         struct kvm *kvm = vcpu->kvm;
5395
5396         if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
5397                 pr_debug("vcpu %d received sipi with vector # %x\n",
5398                          vcpu->vcpu_id, vcpu->arch.sipi_vector);
5399                 kvm_lapic_reset(vcpu);
5400                 r = kvm_arch_vcpu_reset(vcpu);
5401                 if (r)
5402                         return r;
5403                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5404         }
5405
5406         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5407         vapic_enter(vcpu);
5408
5409         r = 1;
5410         while (r > 0) {
5411                 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5412                     !vcpu->arch.apf.halted)
5413                         r = vcpu_enter_guest(vcpu);
5414                 else {
5415                         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5416                         kvm_vcpu_block(vcpu);
5417                         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5418                         if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
5419                         {
5420                                 switch(vcpu->arch.mp_state) {
5421                                 case KVM_MP_STATE_HALTED:
5422                                         vcpu->arch.mp_state =
5423                                                 KVM_MP_STATE_RUNNABLE;
5424                                 case KVM_MP_STATE_RUNNABLE:
5425                                         vcpu->arch.apf.halted = false;
5426                                         break;
5427                                 case KVM_MP_STATE_SIPI_RECEIVED:
5428                                 default:
5429                                         r = -EINTR;
5430                                         break;
5431                                 }
5432                         }
5433                 }
5434
5435                 if (r <= 0)
5436                         break;
5437
5438                 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5439                 if (kvm_cpu_has_pending_timer(vcpu))
5440                         kvm_inject_pending_timer_irqs(vcpu);
5441
5442                 if (dm_request_for_irq_injection(vcpu)) {
5443                         r = -EINTR;
5444                         vcpu->run->exit_reason = KVM_EXIT_INTR;
5445                         ++vcpu->stat.request_irq_exits;
5446                 }
5447
5448                 kvm_check_async_pf_completion(vcpu);
5449
5450                 if (signal_pending(current)) {
5451                         r = -EINTR;
5452                         vcpu->run->exit_reason = KVM_EXIT_INTR;
5453                         ++vcpu->stat.signal_exits;
5454                 }
5455                 if (need_resched()) {
5456                         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5457                         kvm_resched(vcpu);
5458                         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5459                 }
5460         }
5461
5462         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5463
5464         vapic_exit(vcpu);
5465
5466         return r;
5467 }
5468
5469 /*
5470  * Implements the following, as a state machine:
5471  *
5472  * read:
5473  *   for each fragment
5474  *     write gpa, len
5475  *     exit
5476  *     copy data
5477  *   execute insn
5478  *
5479  * write:
5480  *   for each fragment
5481  *      write gpa, len
5482  *      copy data
5483  *      exit
5484  */
5485 static int complete_mmio(struct kvm_vcpu *vcpu)
5486 {
5487         struct kvm_run *run = vcpu->run;
5488         struct kvm_mmio_fragment *frag;
5489         int r;
5490
5491         if (!(vcpu->arch.pio.count || vcpu->mmio_needed))
5492                 return 1;
5493
5494         if (vcpu->mmio_needed) {
5495                 /* Complete previous fragment */
5496                 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment++];
5497                 if (!vcpu->mmio_is_write)
5498                         memcpy(frag->data, run->mmio.data, frag->len);
5499                 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
5500                         vcpu->mmio_needed = 0;
5501                         if (vcpu->mmio_is_write)
5502                                 return 1;
5503                         vcpu->mmio_read_completed = 1;
5504                         goto done;
5505                 }
5506                 /* Initiate next fragment */
5507                 ++frag;
5508                 run->exit_reason = KVM_EXIT_MMIO;
5509                 run->mmio.phys_addr = frag->gpa;
5510                 if (vcpu->mmio_is_write)
5511                         memcpy(run->mmio.data, frag->data, frag->len);
5512                 run->mmio.len = frag->len;
5513                 run->mmio.is_write = vcpu->mmio_is_write;
5514                 return 0;
5515
5516         }
5517 done:
5518         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5519         r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5520         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5521         if (r != EMULATE_DONE)
5522                 return 0;
5523         return 1;
5524 }
5525
5526 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5527 {
5528         int r;
5529         sigset_t sigsaved;
5530
5531         if (!tsk_used_math(current) && init_fpu(current))
5532                 return -ENOMEM;
5533
5534         if (vcpu->sigset_active)
5535                 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5536
5537         if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
5538                 kvm_vcpu_block(vcpu);
5539                 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
5540                 r = -EAGAIN;
5541                 goto out;
5542         }
5543
5544         /* re-sync apic's tpr */
5545         if (!irqchip_in_kernel(vcpu->kvm)) {
5546                 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5547                         r = -EINVAL;
5548                         goto out;
5549                 }
5550         }
5551
5552         r = complete_mmio(vcpu);
5553         if (r <= 0)
5554                 goto out;
5555
5556         r = __vcpu_run(vcpu);
5557
5558 out:
5559         post_kvm_run_save(vcpu);
5560         if (vcpu->sigset_active)
5561                 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5562
5563         return r;
5564 }
5565
5566 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5567 {
5568         if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5569                 /*
5570                  * We are here if userspace calls get_regs() in the middle of
5571                  * instruction emulation. Registers state needs to be copied
5572                  * back from emulation context to vcpu. Userspace shouldn't do
5573                  * that usually, but some bad designed PV devices (vmware
5574                  * backdoor interface) need this to work
5575                  */
5576                 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5577                 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
5578                 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5579         }
5580         regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5581         regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5582         regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5583         regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5584         regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5585         regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5586         regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5587         regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
5588 #ifdef CONFIG_X86_64
5589         regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5590         regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5591         regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5592         regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5593         regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5594         regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5595         regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5596         regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
5597 #endif
5598
5599         regs->rip = kvm_rip_read(vcpu);
5600         regs->rflags = kvm_get_rflags(vcpu);
5601
5602         return 0;
5603 }
5604
5605 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5606 {
5607         vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
5608         vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5609
5610         kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5611         kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5612         kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5613         kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5614         kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5615         kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5616         kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5617         kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
5618 #ifdef CONFIG_X86_64
5619         kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5620         kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5621         kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5622         kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5623         kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5624         kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5625         kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5626         kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
5627 #endif
5628
5629         kvm_rip_write(vcpu, regs->rip);
5630         kvm_set_rflags(vcpu, regs->rflags);
5631
5632         vcpu->arch.exception.pending = false;
5633
5634         kvm_make_request(KVM_REQ_EVENT, vcpu);
5635
5636         return 0;
5637 }
5638
5639 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5640 {
5641         struct kvm_segment cs;
5642
5643         kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
5644         *db = cs.db;
5645         *l = cs.l;
5646 }
5647 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5648
5649 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5650                                   struct kvm_sregs *sregs)
5651 {
5652         struct desc_ptr dt;
5653
5654         kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5655         kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5656         kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5657         kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5658         kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5659         kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
5660
5661         kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5662         kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
5663
5664         kvm_x86_ops->get_idt(vcpu, &dt);
5665         sregs->idt.limit = dt.size;
5666         sregs->idt.base = dt.address;
5667         kvm_x86_ops->get_gdt(vcpu, &dt);
5668         sregs->gdt.limit = dt.size;
5669         sregs->gdt.base = dt.address;
5670
5671         sregs->cr0 = kvm_read_cr0(vcpu);
5672         sregs->cr2 = vcpu->arch.cr2;
5673         sregs->cr3 = kvm_read_cr3(vcpu);
5674         sregs->cr4 = kvm_read_cr4(vcpu);
5675         sregs->cr8 = kvm_get_cr8(vcpu);
5676         sregs->efer = vcpu->arch.efer;
5677         sregs->apic_base = kvm_get_apic_base(vcpu);
5678
5679         memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
5680
5681         if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
5682                 set_bit(vcpu->arch.interrupt.nr,
5683                         (unsigned long *)sregs->interrupt_bitmap);
5684
5685         return 0;
5686 }
5687
5688 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5689                                     struct kvm_mp_state *mp_state)
5690 {
5691         mp_state->mp_state = vcpu->arch.mp_state;
5692         return 0;
5693 }
5694
5695 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5696                                     struct kvm_mp_state *mp_state)
5697 {
5698         vcpu->arch.mp_state = mp_state->mp_state;
5699         kvm_make_request(KVM_REQ_EVENT, vcpu);
5700         return 0;
5701 }
5702
5703 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
5704                     int reason, bool has_error_code, u32 error_code)
5705 {
5706         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5707         int ret;
5708
5709         init_emulate_ctxt(vcpu);
5710
5711         ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
5712                                    has_error_code, error_code);
5713
5714         if (ret)
5715                 return EMULATE_FAIL;
5716
5717         memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
5718         kvm_rip_write(vcpu, ctxt->eip);
5719         kvm_set_rflags(vcpu, ctxt->eflags);
5720         kvm_make_request(KVM_REQ_EVENT, vcpu);
5721         return EMULATE_DONE;
5722 }
5723 EXPORT_SYMBOL_GPL(kvm_task_switch);
5724
5725 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5726                                   struct kvm_sregs *sregs)
5727 {
5728         int mmu_reset_needed = 0;
5729         int pending_vec, max_bits, idx;
5730         struct desc_ptr dt;
5731
5732         dt.size = sregs->idt.limit;
5733         dt.address = sregs->idt.base;
5734         kvm_x86_ops->set_idt(vcpu, &dt);
5735         dt.size = sregs->gdt.limit;
5736         dt.address = sregs->gdt.base;
5737         kvm_x86_ops->set_gdt(vcpu, &dt);
5738
5739         vcpu->arch.cr2 = sregs->cr2;
5740         mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
5741         vcpu->arch.cr3 = sregs->cr3;
5742         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
5743
5744         kvm_set_cr8(vcpu, sregs->cr8);
5745
5746         mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
5747         kvm_x86_ops->set_efer(vcpu, sregs->efer);
5748         kvm_set_apic_base(vcpu, sregs->apic_base);
5749
5750         mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
5751         kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
5752         vcpu->arch.cr0 = sregs->cr0;
5753
5754         mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
5755         kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
5756         if (sregs->cr4 & X86_CR4_OSXSAVE)
5757                 kvm_update_cpuid(vcpu);
5758
5759         idx = srcu_read_lock(&vcpu->kvm->srcu);
5760         if (!is_long_mode(vcpu) && is_pae(vcpu)) {
5761                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
5762                 mmu_reset_needed = 1;
5763         }
5764         srcu_read_unlock(&vcpu->kvm->srcu, idx);
5765
5766         if (mmu_reset_needed)
5767                 kvm_mmu_reset_context(vcpu);
5768
5769         max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5770         pending_vec = find_first_bit(
5771                 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5772         if (pending_vec < max_bits) {
5773                 kvm_queue_interrupt(vcpu, pending_vec, false);
5774                 pr_debug("Set back pending irq %d\n", pending_vec);
5775         }
5776
5777         kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5778         kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5779         kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5780         kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5781         kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5782         kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
5783
5784         kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5785         kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
5786
5787         update_cr8_intercept(vcpu);
5788
5789         /* Older userspace won't unhalt the vcpu on reset. */
5790         if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
5791             sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
5792             !is_protmode(vcpu))
5793                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5794
5795         kvm_make_request(KVM_REQ_EVENT, vcpu);
5796
5797         return 0;
5798 }
5799
5800 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5801                                         struct kvm_guest_debug *dbg)
5802 {
5803         unsigned long rflags;
5804         int i, r;
5805
5806         if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5807                 r = -EBUSY;
5808                 if (vcpu->arch.exception.pending)
5809                         goto out;
5810                 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5811                         kvm_queue_exception(vcpu, DB_VECTOR);
5812                 else
5813                         kvm_queue_exception(vcpu, BP_VECTOR);
5814         }
5815
5816         /*
5817          * Read rflags as long as potentially injected trace flags are still
5818          * filtered out.
5819          */
5820         rflags = kvm_get_rflags(vcpu);
5821
5822         vcpu->guest_debug = dbg->control;
5823         if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5824                 vcpu->guest_debug = 0;
5825
5826         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5827                 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5828                         vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5829                 vcpu->arch.switch_db_regs =
5830                         (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5831         } else {
5832                 for (i = 0; i < KVM_NR_DB_REGS; i++)
5833                         vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5834                 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5835         }
5836
5837         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5838                 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5839                         get_segment_base(vcpu, VCPU_SREG_CS);
5840
5841         /*
5842          * Trigger an rflags update that will inject or remove the trace
5843          * flags.
5844          */
5845         kvm_set_rflags(vcpu, rflags);
5846
5847         kvm_x86_ops->set_guest_debug(vcpu, dbg);
5848
5849         r = 0;
5850
5851 out:
5852
5853         return r;
5854 }
5855
5856 /*
5857  * Translate a guest virtual address to a guest physical address.
5858  */
5859 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5860                                     struct kvm_translation *tr)
5861 {
5862         unsigned long vaddr = tr->linear_address;
5863         gpa_t gpa;
5864         int idx;
5865
5866         idx = srcu_read_lock(&vcpu->kvm->srcu);
5867         gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
5868         srcu_read_unlock(&vcpu->kvm->srcu, idx);
5869         tr->physical_address = gpa;
5870         tr->valid = gpa != UNMAPPED_GVA;
5871         tr->writeable = 1;
5872         tr->usermode = 0;
5873
5874         return 0;
5875 }
5876
5877 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5878 {
5879         struct i387_fxsave_struct *fxsave =
5880                         &vcpu->arch.guest_fpu.state->fxsave;
5881
5882         memcpy(fpu->fpr, fxsave->st_space, 128);
5883         fpu->fcw = fxsave->cwd;
5884         fpu->fsw = fxsave->swd;
5885         fpu->ftwx = fxsave->twd;
5886         fpu->last_opcode = fxsave->fop;
5887         fpu->last_ip = fxsave->rip;
5888         fpu->last_dp = fxsave->rdp;
5889         memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5890
5891         return 0;
5892 }
5893
5894 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5895 {
5896         struct i387_fxsave_struct *fxsave =
5897                         &vcpu->arch.guest_fpu.state->fxsave;
5898
5899         memcpy(fxsave->st_space, fpu->fpr, 128);
5900         fxsave->cwd = fpu->fcw;
5901         fxsave->swd = fpu->fsw;
5902         fxsave->twd = fpu->ftwx;
5903         fxsave->fop = fpu->last_opcode;
5904         fxsave->rip = fpu->last_ip;
5905         fxsave->rdp = fpu->last_dp;
5906         memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5907
5908         return 0;
5909 }
5910
5911 int fx_init(struct kvm_vcpu *vcpu)
5912 {
5913         int err;
5914
5915         err = fpu_alloc(&vcpu->arch.guest_fpu);
5916         if (err)
5917                 return err;
5918
5919         fpu_finit(&vcpu->arch.guest_fpu);
5920
5921         /*
5922          * Ensure guest xcr0 is valid for loading
5923          */
5924         vcpu->arch.xcr0 = XSTATE_FP;
5925
5926         vcpu->arch.cr0 |= X86_CR0_ET;
5927
5928         return 0;
5929 }
5930 EXPORT_SYMBOL_GPL(fx_init);
5931
5932 static void fx_free(struct kvm_vcpu *vcpu)
5933 {
5934         fpu_free(&vcpu->arch.guest_fpu);
5935 }
5936
5937 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5938 {
5939         if (vcpu->guest_fpu_loaded)
5940                 return;
5941
5942         /*
5943          * Restore all possible states in the guest,
5944          * and assume host would use all available bits.
5945          * Guest xcr0 would be loaded later.
5946          */
5947         kvm_put_guest_xcr0(vcpu);
5948         vcpu->guest_fpu_loaded = 1;
5949         unlazy_fpu(current);
5950         fpu_restore_checking(&vcpu->arch.guest_fpu);
5951         trace_kvm_fpu(1);
5952 }
5953
5954 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5955 {
5956         kvm_put_guest_xcr0(vcpu);
5957
5958         if (!vcpu->guest_fpu_loaded)
5959                 return;
5960
5961         vcpu->guest_fpu_loaded = 0;
5962         fpu_save_init(&vcpu->arch.guest_fpu);
5963         ++vcpu->stat.fpu_reload;
5964         kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
5965         trace_kvm_fpu(0);
5966 }
5967
5968 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5969 {
5970         kvmclock_reset(vcpu);
5971
5972         free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
5973         fx_free(vcpu);
5974         kvm_x86_ops->vcpu_free(vcpu);
5975 }
5976
5977 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5978                                                 unsigned int id)
5979 {
5980         if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5981                 printk_once(KERN_WARNING
5982                 "kvm: SMP vm created on host with unstable TSC; "
5983                 "guest TSC will not be reliable\n");
5984         return kvm_x86_ops->vcpu_create(kvm, id);
5985 }
5986
5987 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5988 {
5989         int r;
5990
5991         vcpu->arch.mtrr_state.have_fixed = 1;
5992         vcpu_load(vcpu);
5993         r = kvm_arch_vcpu_reset(vcpu);
5994         if (r == 0)
5995                 r = kvm_mmu_setup(vcpu);
5996         vcpu_put(vcpu);
5997
5998         return r;
5999 }
6000
6001 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
6002 {
6003         vcpu->arch.apf.msr_val = 0;
6004
6005         vcpu_load(vcpu);
6006         kvm_mmu_unload(vcpu);
6007         vcpu_put(vcpu);
6008
6009         fx_free(vcpu);
6010         kvm_x86_ops->vcpu_free(vcpu);
6011 }
6012
6013 int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
6014 {
6015         atomic_set(&vcpu->arch.nmi_queued, 0);
6016         vcpu->arch.nmi_pending = 0;
6017         vcpu->arch.nmi_injected = false;
6018
6019         vcpu->arch.switch_db_regs = 0;
6020         memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6021         vcpu->arch.dr6 = DR6_FIXED_1;
6022         vcpu->arch.dr7 = DR7_FIXED_1;
6023
6024         kvm_make_request(KVM_REQ_EVENT, vcpu);
6025         vcpu->arch.apf.msr_val = 0;
6026         vcpu->arch.st.msr_val = 0;
6027
6028         kvmclock_reset(vcpu);
6029
6030         kvm_clear_async_pf_completion_queue(vcpu);
6031         kvm_async_pf_hash_reset(vcpu);
6032         vcpu->arch.apf.halted = false;
6033
6034         kvm_pmu_reset(vcpu);
6035
6036         return kvm_x86_ops->vcpu_reset(vcpu);
6037 }
6038
6039 int kvm_arch_hardware_enable(void *garbage)
6040 {
6041         struct kvm *kvm;
6042         struct kvm_vcpu *vcpu;
6043         int i;
6044         int ret;
6045         u64 local_tsc;
6046         u64 max_tsc = 0;
6047         bool stable, backwards_tsc = false;
6048
6049         kvm_shared_msr_cpu_online();
6050         ret = kvm_x86_ops->hardware_enable(garbage);
6051         if (ret != 0)
6052                 return ret;
6053
6054         local_tsc = native_read_tsc();
6055         stable = !check_tsc_unstable();
6056         list_for_each_entry(kvm, &vm_list, vm_list) {
6057                 kvm_for_each_vcpu(i, vcpu, kvm) {
6058                         if (!stable && vcpu->cpu == smp_processor_id())
6059                                 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6060                         if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6061                                 backwards_tsc = true;
6062                                 if (vcpu->arch.last_host_tsc > max_tsc)
6063                                         max_tsc = vcpu->arch.last_host_tsc;
6064                         }
6065                 }
6066         }
6067
6068         /*
6069          * Sometimes, even reliable TSCs go backwards.  This happens on
6070          * platforms that reset TSC during suspend or hibernate actions, but
6071          * maintain synchronization.  We must compensate.  Fortunately, we can
6072          * detect that condition here, which happens early in CPU bringup,
6073          * before any KVM threads can be running.  Unfortunately, we can't
6074          * bring the TSCs fully up to date with real time, as we aren't yet far
6075          * enough into CPU bringup that we know how much real time has actually
6076          * elapsed; our helper function, get_kernel_ns() will be using boot
6077          * variables that haven't been updated yet.
6078          *
6079          * So we simply find the maximum observed TSC above, then record the
6080          * adjustment to TSC in each VCPU.  When the VCPU later gets loaded,
6081          * the adjustment will be applied.  Note that we accumulate
6082          * adjustments, in case multiple suspend cycles happen before some VCPU
6083          * gets a chance to run again.  In the event that no KVM threads get a
6084          * chance to run, we will miss the entire elapsed period, as we'll have
6085          * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6086          * loose cycle time.  This isn't too big a deal, since the loss will be
6087          * uniform across all VCPUs (not to mention the scenario is extremely
6088          * unlikely). It is possible that a second hibernate recovery happens
6089          * much faster than a first, causing the observed TSC here to be
6090          * smaller; this would require additional padding adjustment, which is
6091          * why we set last_host_tsc to the local tsc observed here.
6092          *
6093          * N.B. - this code below runs only on platforms with reliable TSC,
6094          * as that is the only way backwards_tsc is set above.  Also note
6095          * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6096          * have the same delta_cyc adjustment applied if backwards_tsc
6097          * is detected.  Note further, this adjustment is only done once,
6098          * as we reset last_host_tsc on all VCPUs to stop this from being
6099          * called multiple times (one for each physical CPU bringup).
6100          *
6101          * Platforms with unreliable TSCs don't have to deal with this, they
6102          * will be compensated by the logic in vcpu_load, which sets the TSC to
6103          * catchup mode.  This will catchup all VCPUs to real time, but cannot
6104          * guarantee that they stay in perfect synchronization.
6105          */
6106         if (backwards_tsc) {
6107                 u64 delta_cyc = max_tsc - local_tsc;
6108                 list_for_each_entry(kvm, &vm_list, vm_list) {
6109                         kvm_for_each_vcpu(i, vcpu, kvm) {
6110                                 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6111                                 vcpu->arch.last_host_tsc = local_tsc;
6112                         }
6113
6114                         /*
6115                          * We have to disable TSC offset matching.. if you were
6116                          * booting a VM while issuing an S4 host suspend....
6117                          * you may have some problem.  Solving this issue is
6118                          * left as an exercise to the reader.
6119                          */
6120                         kvm->arch.last_tsc_nsec = 0;
6121                         kvm->arch.last_tsc_write = 0;
6122                 }
6123
6124         }
6125         return 0;
6126 }
6127
6128 void kvm_arch_hardware_disable(void *garbage)
6129 {
6130         kvm_x86_ops->hardware_disable(garbage);
6131         drop_user_return_notifiers(garbage);
6132 }
6133
6134 int kvm_arch_hardware_setup(void)
6135 {
6136         return kvm_x86_ops->hardware_setup();
6137 }
6138
6139 void kvm_arch_hardware_unsetup(void)
6140 {
6141         kvm_x86_ops->hardware_unsetup();
6142 }
6143
6144 void kvm_arch_check_processor_compat(void *rtn)
6145 {
6146         kvm_x86_ops->check_processor_compatibility(rtn);
6147 }
6148
6149 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6150 {
6151         return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6152 }
6153
6154 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6155 {
6156         struct page *page;
6157         struct kvm *kvm;
6158         int r;
6159
6160         BUG_ON(vcpu->kvm == NULL);
6161         kvm = vcpu->kvm;
6162
6163         vcpu->arch.emulate_ctxt.ops = &emulate_ops;
6164         if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
6165                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6166         else
6167                 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
6168
6169         page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6170         if (!page) {
6171                 r = -ENOMEM;
6172                 goto fail;
6173         }
6174         vcpu->arch.pio_data = page_address(page);
6175
6176         kvm_set_tsc_khz(vcpu, max_tsc_khz);
6177
6178         r = kvm_mmu_create(vcpu);
6179         if (r < 0)
6180                 goto fail_free_pio_data;
6181
6182         if (irqchip_in_kernel(kvm)) {
6183                 r = kvm_create_lapic(vcpu);
6184                 if (r < 0)
6185                         goto fail_mmu_destroy;
6186         }
6187
6188         vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6189                                        GFP_KERNEL);
6190         if (!vcpu->arch.mce_banks) {
6191                 r = -ENOMEM;
6192                 goto fail_free_lapic;
6193         }
6194         vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6195
6196         if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6197                 goto fail_free_mce_banks;
6198
6199         kvm_async_pf_hash_reset(vcpu);
6200         kvm_pmu_init(vcpu);
6201
6202         return 0;
6203 fail_free_mce_banks:
6204         kfree(vcpu->arch.mce_banks);
6205 fail_free_lapic:
6206         kvm_free_lapic(vcpu);
6207 fail_mmu_destroy:
6208         kvm_mmu_destroy(vcpu);
6209 fail_free_pio_data:
6210         free_page((unsigned long)vcpu->arch.pio_data);
6211 fail:
6212         return r;
6213 }
6214
6215 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6216 {
6217         int idx;
6218
6219         kvm_pmu_destroy(vcpu);
6220         kfree(vcpu->arch.mce_banks);
6221         kvm_free_lapic(vcpu);
6222         idx = srcu_read_lock(&vcpu->kvm->srcu);
6223         kvm_mmu_destroy(vcpu);
6224         srcu_read_unlock(&vcpu->kvm->srcu, idx);
6225         free_page((unsigned long)vcpu->arch.pio_data);
6226 }
6227
6228 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
6229 {
6230         if (type)
6231                 return -EINVAL;
6232
6233         INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
6234         INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
6235
6236         /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6237         set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6238
6239         raw_spin_lock_init(&kvm->arch.tsc_write_lock);
6240
6241         return 0;
6242 }
6243
6244 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6245 {
6246         vcpu_load(vcpu);
6247         kvm_mmu_unload(vcpu);
6248         vcpu_put(vcpu);
6249 }
6250
6251 static void kvm_free_vcpus(struct kvm *kvm)
6252 {
6253         unsigned int i;
6254         struct kvm_vcpu *vcpu;
6255
6256         /*
6257          * Unpin any mmu pages first.
6258          */
6259         kvm_for_each_vcpu(i, vcpu, kvm) {
6260                 kvm_clear_async_pf_completion_queue(vcpu);
6261                 kvm_unload_vcpu_mmu(vcpu);
6262         }
6263         kvm_for_each_vcpu(i, vcpu, kvm)
6264                 kvm_arch_vcpu_free(vcpu);
6265
6266         mutex_lock(&kvm->lock);
6267         for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6268                 kvm->vcpus[i] = NULL;
6269