ebf2109318e0426721d59b35f81daa161eef9f70
[linux-3.10.git] / arch / x86 / kvm / x86.c
1 /*
2  * Kernel-based Virtual Machine driver for Linux
3  *
4  * derived from drivers/kvm/kvm_main.c
5  *
6  * Copyright (C) 2006 Qumranet, Inc.
7  * Copyright (C) 2008 Qumranet, Inc.
8  * Copyright IBM Corporation, 2008
9  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10  *
11  * Authors:
12  *   Avi Kivity   <avi@qumranet.com>
13  *   Yaniv Kamay  <yaniv@qumranet.com>
14  *   Amit Shah    <amit.shah@qumranet.com>
15  *   Ben-Ami Yassour <benami@il.ibm.com>
16  *
17  * This work is licensed under the terms of the GNU GPL, version 2.  See
18  * the COPYING file in the top-level directory.
19  *
20  */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30
31 #include <linux/clocksource.h>
32 #include <linux/interrupt.h>
33 #include <linux/kvm.h>
34 #include <linux/fs.h>
35 #include <linux/vmalloc.h>
36 #include <linux/module.h>
37 #include <linux/mman.h>
38 #include <linux/highmem.h>
39 #include <linux/iommu.h>
40 #include <linux/intel-iommu.h>
41 #include <linux/cpufreq.h>
42 #include <linux/user-return-notifier.h>
43 #include <linux/srcu.h>
44 #include <linux/slab.h>
45 #include <linux/perf_event.h>
46 #include <linux/uaccess.h>
47 #include <linux/hash.h>
48 #include <linux/pci.h>
49 #include <trace/events/kvm.h>
50
51 #define CREATE_TRACE_POINTS
52 #include "trace.h"
53
54 #include <asm/debugreg.h>
55 #include <asm/msr.h>
56 #include <asm/desc.h>
57 #include <asm/mtrr.h>
58 #include <asm/mce.h>
59 #include <asm/i387.h>
60 #include <asm/fpu-internal.h> /* Ugh! */
61 #include <asm/xcr.h>
62 #include <asm/pvclock.h>
63 #include <asm/div64.h>
64
65 #define MAX_IO_MSRS 256
66 #define KVM_MAX_MCE_BANKS 32
67 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
68
69 #define emul_to_vcpu(ctxt) \
70         container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
71
72 /* EFER defaults:
73  * - enable syscall per default because its emulated by KVM
74  * - enable LME and LMA per default on 64 bit KVM
75  */
76 #ifdef CONFIG_X86_64
77 static
78 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
79 #else
80 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
81 #endif
82
83 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
84 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
85
86 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
87 static void process_nmi(struct kvm_vcpu *vcpu);
88
89 struct kvm_x86_ops *kvm_x86_ops;
90 EXPORT_SYMBOL_GPL(kvm_x86_ops);
91
92 static bool ignore_msrs = 0;
93 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
94
95 bool kvm_has_tsc_control;
96 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
97 u32  kvm_max_guest_tsc_khz;
98 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
99
100 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
101 static u32 tsc_tolerance_ppm = 250;
102 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
103
104 #define KVM_NR_SHARED_MSRS 16
105
106 struct kvm_shared_msrs_global {
107         int nr;
108         u32 msrs[KVM_NR_SHARED_MSRS];
109 };
110
111 struct kvm_shared_msrs {
112         struct user_return_notifier urn;
113         bool registered;
114         struct kvm_shared_msr_values {
115                 u64 host;
116                 u64 curr;
117         } values[KVM_NR_SHARED_MSRS];
118 };
119
120 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
121 static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
122
123 struct kvm_stats_debugfs_item debugfs_entries[] = {
124         { "pf_fixed", VCPU_STAT(pf_fixed) },
125         { "pf_guest", VCPU_STAT(pf_guest) },
126         { "tlb_flush", VCPU_STAT(tlb_flush) },
127         { "invlpg", VCPU_STAT(invlpg) },
128         { "exits", VCPU_STAT(exits) },
129         { "io_exits", VCPU_STAT(io_exits) },
130         { "mmio_exits", VCPU_STAT(mmio_exits) },
131         { "signal_exits", VCPU_STAT(signal_exits) },
132         { "irq_window", VCPU_STAT(irq_window_exits) },
133         { "nmi_window", VCPU_STAT(nmi_window_exits) },
134         { "halt_exits", VCPU_STAT(halt_exits) },
135         { "halt_wakeup", VCPU_STAT(halt_wakeup) },
136         { "hypercalls", VCPU_STAT(hypercalls) },
137         { "request_irq", VCPU_STAT(request_irq_exits) },
138         { "irq_exits", VCPU_STAT(irq_exits) },
139         { "host_state_reload", VCPU_STAT(host_state_reload) },
140         { "efer_reload", VCPU_STAT(efer_reload) },
141         { "fpu_reload", VCPU_STAT(fpu_reload) },
142         { "insn_emulation", VCPU_STAT(insn_emulation) },
143         { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
144         { "irq_injections", VCPU_STAT(irq_injections) },
145         { "nmi_injections", VCPU_STAT(nmi_injections) },
146         { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
147         { "mmu_pte_write", VM_STAT(mmu_pte_write) },
148         { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
149         { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
150         { "mmu_flooded", VM_STAT(mmu_flooded) },
151         { "mmu_recycled", VM_STAT(mmu_recycled) },
152         { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
153         { "mmu_unsync", VM_STAT(mmu_unsync) },
154         { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
155         { "largepages", VM_STAT(lpages) },
156         { NULL }
157 };
158
159 u64 __read_mostly host_xcr0;
160
161 int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
162
163 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
164 {
165         int i;
166         for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
167                 vcpu->arch.apf.gfns[i] = ~0;
168 }
169
170 static void kvm_on_user_return(struct user_return_notifier *urn)
171 {
172         unsigned slot;
173         struct kvm_shared_msrs *locals
174                 = container_of(urn, struct kvm_shared_msrs, urn);
175         struct kvm_shared_msr_values *values;
176
177         for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
178                 values = &locals->values[slot];
179                 if (values->host != values->curr) {
180                         wrmsrl(shared_msrs_global.msrs[slot], values->host);
181                         values->curr = values->host;
182                 }
183         }
184         locals->registered = false;
185         user_return_notifier_unregister(urn);
186 }
187
188 static void shared_msr_update(unsigned slot, u32 msr)
189 {
190         struct kvm_shared_msrs *smsr;
191         u64 value;
192
193         smsr = &__get_cpu_var(shared_msrs);
194         /* only read, and nobody should modify it at this time,
195          * so don't need lock */
196         if (slot >= shared_msrs_global.nr) {
197                 printk(KERN_ERR "kvm: invalid MSR slot!");
198                 return;
199         }
200         rdmsrl_safe(msr, &value);
201         smsr->values[slot].host = value;
202         smsr->values[slot].curr = value;
203 }
204
205 void kvm_define_shared_msr(unsigned slot, u32 msr)
206 {
207         if (slot >= shared_msrs_global.nr)
208                 shared_msrs_global.nr = slot + 1;
209         shared_msrs_global.msrs[slot] = msr;
210         /* we need ensured the shared_msr_global have been updated */
211         smp_wmb();
212 }
213 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
214
215 static void kvm_shared_msr_cpu_online(void)
216 {
217         unsigned i;
218
219         for (i = 0; i < shared_msrs_global.nr; ++i)
220                 shared_msr_update(i, shared_msrs_global.msrs[i]);
221 }
222
223 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
224 {
225         struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
226
227         if (((value ^ smsr->values[slot].curr) & mask) == 0)
228                 return;
229         smsr->values[slot].curr = value;
230         wrmsrl(shared_msrs_global.msrs[slot], value);
231         if (!smsr->registered) {
232                 smsr->urn.on_user_return = kvm_on_user_return;
233                 user_return_notifier_register(&smsr->urn);
234                 smsr->registered = true;
235         }
236 }
237 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
238
239 static void drop_user_return_notifiers(void *ignore)
240 {
241         struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
242
243         if (smsr->registered)
244                 kvm_on_user_return(&smsr->urn);
245 }
246
247 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
248 {
249         if (irqchip_in_kernel(vcpu->kvm))
250                 return vcpu->arch.apic_base;
251         else
252                 return vcpu->arch.apic_base;
253 }
254 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
255
256 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
257 {
258         /* TODO: reserve bits check */
259         if (irqchip_in_kernel(vcpu->kvm))
260                 kvm_lapic_set_base(vcpu, data);
261         else
262                 vcpu->arch.apic_base = data;
263 }
264 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
265
266 #define EXCPT_BENIGN            0
267 #define EXCPT_CONTRIBUTORY      1
268 #define EXCPT_PF                2
269
270 static int exception_class(int vector)
271 {
272         switch (vector) {
273         case PF_VECTOR:
274                 return EXCPT_PF;
275         case DE_VECTOR:
276         case TS_VECTOR:
277         case NP_VECTOR:
278         case SS_VECTOR:
279         case GP_VECTOR:
280                 return EXCPT_CONTRIBUTORY;
281         default:
282                 break;
283         }
284         return EXCPT_BENIGN;
285 }
286
287 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
288                 unsigned nr, bool has_error, u32 error_code,
289                 bool reinject)
290 {
291         u32 prev_nr;
292         int class1, class2;
293
294         kvm_make_request(KVM_REQ_EVENT, vcpu);
295
296         if (!vcpu->arch.exception.pending) {
297         queue:
298                 vcpu->arch.exception.pending = true;
299                 vcpu->arch.exception.has_error_code = has_error;
300                 vcpu->arch.exception.nr = nr;
301                 vcpu->arch.exception.error_code = error_code;
302                 vcpu->arch.exception.reinject = reinject;
303                 return;
304         }
305
306         /* to check exception */
307         prev_nr = vcpu->arch.exception.nr;
308         if (prev_nr == DF_VECTOR) {
309                 /* triple fault -> shutdown */
310                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
311                 return;
312         }
313         class1 = exception_class(prev_nr);
314         class2 = exception_class(nr);
315         if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
316                 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
317                 /* generate double fault per SDM Table 5-5 */
318                 vcpu->arch.exception.pending = true;
319                 vcpu->arch.exception.has_error_code = true;
320                 vcpu->arch.exception.nr = DF_VECTOR;
321                 vcpu->arch.exception.error_code = 0;
322         } else
323                 /* replace previous exception with a new one in a hope
324                    that instruction re-execution will regenerate lost
325                    exception */
326                 goto queue;
327 }
328
329 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
330 {
331         kvm_multiple_exception(vcpu, nr, false, 0, false);
332 }
333 EXPORT_SYMBOL_GPL(kvm_queue_exception);
334
335 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
336 {
337         kvm_multiple_exception(vcpu, nr, false, 0, true);
338 }
339 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
340
341 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
342 {
343         if (err)
344                 kvm_inject_gp(vcpu, 0);
345         else
346                 kvm_x86_ops->skip_emulated_instruction(vcpu);
347 }
348 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
349
350 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
351 {
352         ++vcpu->stat.pf_guest;
353         vcpu->arch.cr2 = fault->address;
354         kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
355 }
356 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
357
358 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
359 {
360         if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
361                 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
362         else
363                 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
364 }
365
366 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
367 {
368         atomic_inc(&vcpu->arch.nmi_queued);
369         kvm_make_request(KVM_REQ_NMI, vcpu);
370 }
371 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
372
373 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
374 {
375         kvm_multiple_exception(vcpu, nr, true, error_code, false);
376 }
377 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
378
379 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
380 {
381         kvm_multiple_exception(vcpu, nr, true, error_code, true);
382 }
383 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
384
385 /*
386  * Checks if cpl <= required_cpl; if true, return true.  Otherwise queue
387  * a #GP and return false.
388  */
389 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
390 {
391         if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
392                 return true;
393         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
394         return false;
395 }
396 EXPORT_SYMBOL_GPL(kvm_require_cpl);
397
398 /*
399  * This function will be used to read from the physical memory of the currently
400  * running guest. The difference to kvm_read_guest_page is that this function
401  * can read from guest physical or from the guest's guest physical memory.
402  */
403 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
404                             gfn_t ngfn, void *data, int offset, int len,
405                             u32 access)
406 {
407         gfn_t real_gfn;
408         gpa_t ngpa;
409
410         ngpa     = gfn_to_gpa(ngfn);
411         real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
412         if (real_gfn == UNMAPPED_GVA)
413                 return -EFAULT;
414
415         real_gfn = gpa_to_gfn(real_gfn);
416
417         return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
418 }
419 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
420
421 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
422                                void *data, int offset, int len, u32 access)
423 {
424         return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
425                                        data, offset, len, access);
426 }
427
428 /*
429  * Load the pae pdptrs.  Return true is they are all valid.
430  */
431 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
432 {
433         gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
434         unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
435         int i;
436         int ret;
437         u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
438
439         ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
440                                       offset * sizeof(u64), sizeof(pdpte),
441                                       PFERR_USER_MASK|PFERR_WRITE_MASK);
442         if (ret < 0) {
443                 ret = 0;
444                 goto out;
445         }
446         for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
447                 if (is_present_gpte(pdpte[i]) &&
448                     (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
449                         ret = 0;
450                         goto out;
451                 }
452         }
453         ret = 1;
454
455         memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
456         __set_bit(VCPU_EXREG_PDPTR,
457                   (unsigned long *)&vcpu->arch.regs_avail);
458         __set_bit(VCPU_EXREG_PDPTR,
459                   (unsigned long *)&vcpu->arch.regs_dirty);
460 out:
461
462         return ret;
463 }
464 EXPORT_SYMBOL_GPL(load_pdptrs);
465
466 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
467 {
468         u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
469         bool changed = true;
470         int offset;
471         gfn_t gfn;
472         int r;
473
474         if (is_long_mode(vcpu) || !is_pae(vcpu))
475                 return false;
476
477         if (!test_bit(VCPU_EXREG_PDPTR,
478                       (unsigned long *)&vcpu->arch.regs_avail))
479                 return true;
480
481         gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
482         offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
483         r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
484                                        PFERR_USER_MASK | PFERR_WRITE_MASK);
485         if (r < 0)
486                 goto out;
487         changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
488 out:
489
490         return changed;
491 }
492
493 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
494 {
495         unsigned long old_cr0 = kvm_read_cr0(vcpu);
496         unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
497                                     X86_CR0_CD | X86_CR0_NW;
498
499         cr0 |= X86_CR0_ET;
500
501 #ifdef CONFIG_X86_64
502         if (cr0 & 0xffffffff00000000UL)
503                 return 1;
504 #endif
505
506         cr0 &= ~CR0_RESERVED_BITS;
507
508         if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
509                 return 1;
510
511         if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
512                 return 1;
513
514         if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
515 #ifdef CONFIG_X86_64
516                 if ((vcpu->arch.efer & EFER_LME)) {
517                         int cs_db, cs_l;
518
519                         if (!is_pae(vcpu))
520                                 return 1;
521                         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
522                         if (cs_l)
523                                 return 1;
524                 } else
525 #endif
526                 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
527                                                  kvm_read_cr3(vcpu)))
528                         return 1;
529         }
530
531         if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
532                 return 1;
533
534         kvm_x86_ops->set_cr0(vcpu, cr0);
535
536         if ((cr0 ^ old_cr0) & X86_CR0_PG) {
537                 kvm_clear_async_pf_completion_queue(vcpu);
538                 kvm_async_pf_hash_reset(vcpu);
539         }
540
541         if ((cr0 ^ old_cr0) & update_bits)
542                 kvm_mmu_reset_context(vcpu);
543         return 0;
544 }
545 EXPORT_SYMBOL_GPL(kvm_set_cr0);
546
547 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
548 {
549         (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
550 }
551 EXPORT_SYMBOL_GPL(kvm_lmsw);
552
553 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
554 {
555         u64 xcr0;
556
557         /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now  */
558         if (index != XCR_XFEATURE_ENABLED_MASK)
559                 return 1;
560         xcr0 = xcr;
561         if (kvm_x86_ops->get_cpl(vcpu) != 0)
562                 return 1;
563         if (!(xcr0 & XSTATE_FP))
564                 return 1;
565         if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
566                 return 1;
567         if (xcr0 & ~host_xcr0)
568                 return 1;
569         vcpu->arch.xcr0 = xcr0;
570         vcpu->guest_xcr0_loaded = 0;
571         return 0;
572 }
573
574 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
575 {
576         if (__kvm_set_xcr(vcpu, index, xcr)) {
577                 kvm_inject_gp(vcpu, 0);
578                 return 1;
579         }
580         return 0;
581 }
582 EXPORT_SYMBOL_GPL(kvm_set_xcr);
583
584 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
585 {
586         unsigned long old_cr4 = kvm_read_cr4(vcpu);
587         unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
588                                    X86_CR4_PAE | X86_CR4_SMEP;
589         if (cr4 & CR4_RESERVED_BITS)
590                 return 1;
591
592         if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
593                 return 1;
594
595         if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
596                 return 1;
597
598         if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
599                 return 1;
600
601         if (is_long_mode(vcpu)) {
602                 if (!(cr4 & X86_CR4_PAE))
603                         return 1;
604         } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
605                    && ((cr4 ^ old_cr4) & pdptr_bits)
606                    && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
607                                    kvm_read_cr3(vcpu)))
608                 return 1;
609
610         if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
611                 if (!guest_cpuid_has_pcid(vcpu))
612                         return 1;
613
614                 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
615                 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
616                         return 1;
617         }
618
619         if (kvm_x86_ops->set_cr4(vcpu, cr4))
620                 return 1;
621
622         if (((cr4 ^ old_cr4) & pdptr_bits) ||
623             (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
624                 kvm_mmu_reset_context(vcpu);
625
626         if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
627                 kvm_update_cpuid(vcpu);
628
629         return 0;
630 }
631 EXPORT_SYMBOL_GPL(kvm_set_cr4);
632
633 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
634 {
635         if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
636                 kvm_mmu_sync_roots(vcpu);
637                 kvm_mmu_flush_tlb(vcpu);
638                 return 0;
639         }
640
641         if (is_long_mode(vcpu)) {
642                 if (kvm_read_cr4(vcpu) & X86_CR4_PCIDE) {
643                         if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
644                                 return 1;
645                 } else
646                         if (cr3 & CR3_L_MODE_RESERVED_BITS)
647                                 return 1;
648         } else {
649                 if (is_pae(vcpu)) {
650                         if (cr3 & CR3_PAE_RESERVED_BITS)
651                                 return 1;
652                         if (is_paging(vcpu) &&
653                             !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
654                                 return 1;
655                 }
656                 /*
657                  * We don't check reserved bits in nonpae mode, because
658                  * this isn't enforced, and VMware depends on this.
659                  */
660         }
661
662         /*
663          * Does the new cr3 value map to physical memory? (Note, we
664          * catch an invalid cr3 even in real-mode, because it would
665          * cause trouble later on when we turn on paging anyway.)
666          *
667          * A real CPU would silently accept an invalid cr3 and would
668          * attempt to use it - with largely undefined (and often hard
669          * to debug) behavior on the guest side.
670          */
671         if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
672                 return 1;
673         vcpu->arch.cr3 = cr3;
674         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
675         vcpu->arch.mmu.new_cr3(vcpu);
676         return 0;
677 }
678 EXPORT_SYMBOL_GPL(kvm_set_cr3);
679
680 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
681 {
682         if (cr8 & CR8_RESERVED_BITS)
683                 return 1;
684         if (irqchip_in_kernel(vcpu->kvm))
685                 kvm_lapic_set_tpr(vcpu, cr8);
686         else
687                 vcpu->arch.cr8 = cr8;
688         return 0;
689 }
690 EXPORT_SYMBOL_GPL(kvm_set_cr8);
691
692 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
693 {
694         if (irqchip_in_kernel(vcpu->kvm))
695                 return kvm_lapic_get_cr8(vcpu);
696         else
697                 return vcpu->arch.cr8;
698 }
699 EXPORT_SYMBOL_GPL(kvm_get_cr8);
700
701 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
702 {
703         switch (dr) {
704         case 0 ... 3:
705                 vcpu->arch.db[dr] = val;
706                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
707                         vcpu->arch.eff_db[dr] = val;
708                 break;
709         case 4:
710                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
711                         return 1; /* #UD */
712                 /* fall through */
713         case 6:
714                 if (val & 0xffffffff00000000ULL)
715                         return -1; /* #GP */
716                 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
717                 break;
718         case 5:
719                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
720                         return 1; /* #UD */
721                 /* fall through */
722         default: /* 7 */
723                 if (val & 0xffffffff00000000ULL)
724                         return -1; /* #GP */
725                 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
726                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
727                         kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
728                         vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
729                 }
730                 break;
731         }
732
733         return 0;
734 }
735
736 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
737 {
738         int res;
739
740         res = __kvm_set_dr(vcpu, dr, val);
741         if (res > 0)
742                 kvm_queue_exception(vcpu, UD_VECTOR);
743         else if (res < 0)
744                 kvm_inject_gp(vcpu, 0);
745
746         return res;
747 }
748 EXPORT_SYMBOL_GPL(kvm_set_dr);
749
750 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
751 {
752         switch (dr) {
753         case 0 ... 3:
754                 *val = vcpu->arch.db[dr];
755                 break;
756         case 4:
757                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
758                         return 1;
759                 /* fall through */
760         case 6:
761                 *val = vcpu->arch.dr6;
762                 break;
763         case 5:
764                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
765                         return 1;
766                 /* fall through */
767         default: /* 7 */
768                 *val = vcpu->arch.dr7;
769                 break;
770         }
771
772         return 0;
773 }
774
775 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
776 {
777         if (_kvm_get_dr(vcpu, dr, val)) {
778                 kvm_queue_exception(vcpu, UD_VECTOR);
779                 return 1;
780         }
781         return 0;
782 }
783 EXPORT_SYMBOL_GPL(kvm_get_dr);
784
785 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
786 {
787         u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
788         u64 data;
789         int err;
790
791         err = kvm_pmu_read_pmc(vcpu, ecx, &data);
792         if (err)
793                 return err;
794         kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
795         kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
796         return err;
797 }
798 EXPORT_SYMBOL_GPL(kvm_rdpmc);
799
800 /*
801  * List of msr numbers which we expose to userspace through KVM_GET_MSRS
802  * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
803  *
804  * This list is modified at module load time to reflect the
805  * capabilities of the host cpu. This capabilities test skips MSRs that are
806  * kvm-specific. Those are put in the beginning of the list.
807  */
808
809 #define KVM_SAVE_MSRS_BEGIN     10
810 static u32 msrs_to_save[] = {
811         MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
812         MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
813         HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
814         HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
815         MSR_KVM_PV_EOI_EN,
816         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
817         MSR_STAR,
818 #ifdef CONFIG_X86_64
819         MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
820 #endif
821         MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
822 };
823
824 static unsigned num_msrs_to_save;
825
826 static u32 emulated_msrs[] = {
827         MSR_IA32_TSCDEADLINE,
828         MSR_IA32_MISC_ENABLE,
829         MSR_IA32_MCG_STATUS,
830         MSR_IA32_MCG_CTL,
831 };
832
833 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
834 {
835         u64 old_efer = vcpu->arch.efer;
836
837         if (efer & efer_reserved_bits)
838                 return 1;
839
840         if (is_paging(vcpu)
841             && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
842                 return 1;
843
844         if (efer & EFER_FFXSR) {
845                 struct kvm_cpuid_entry2 *feat;
846
847                 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
848                 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
849                         return 1;
850         }
851
852         if (efer & EFER_SVME) {
853                 struct kvm_cpuid_entry2 *feat;
854
855                 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
856                 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
857                         return 1;
858         }
859
860         efer &= ~EFER_LMA;
861         efer |= vcpu->arch.efer & EFER_LMA;
862
863         kvm_x86_ops->set_efer(vcpu, efer);
864
865         vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
866
867         /* Update reserved bits */
868         if ((efer ^ old_efer) & EFER_NX)
869                 kvm_mmu_reset_context(vcpu);
870
871         return 0;
872 }
873
874 void kvm_enable_efer_bits(u64 mask)
875 {
876        efer_reserved_bits &= ~mask;
877 }
878 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
879
880
881 /*
882  * Writes msr value into into the appropriate "register".
883  * Returns 0 on success, non-0 otherwise.
884  * Assumes vcpu_load() was already called.
885  */
886 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
887 {
888         return kvm_x86_ops->set_msr(vcpu, msr_index, data);
889 }
890
891 /*
892  * Adapt set_msr() to msr_io()'s calling convention
893  */
894 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
895 {
896         return kvm_set_msr(vcpu, index, *data);
897 }
898
899 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
900 {
901         int version;
902         int r;
903         struct pvclock_wall_clock wc;
904         struct timespec boot;
905
906         if (!wall_clock)
907                 return;
908
909         r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
910         if (r)
911                 return;
912
913         if (version & 1)
914                 ++version;  /* first time write, random junk */
915
916         ++version;
917
918         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
919
920         /*
921          * The guest calculates current wall clock time by adding
922          * system time (updated by kvm_guest_time_update below) to the
923          * wall clock specified here.  guest system time equals host
924          * system time for us, thus we must fill in host boot time here.
925          */
926         getboottime(&boot);
927
928         if (kvm->arch.kvmclock_offset) {
929                 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
930                 boot = timespec_sub(boot, ts);
931         }
932         wc.sec = boot.tv_sec;
933         wc.nsec = boot.tv_nsec;
934         wc.version = version;
935
936         kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
937
938         version++;
939         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
940 }
941
942 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
943 {
944         uint32_t quotient, remainder;
945
946         /* Don't try to replace with do_div(), this one calculates
947          * "(dividend << 32) / divisor" */
948         __asm__ ( "divl %4"
949                   : "=a" (quotient), "=d" (remainder)
950                   : "0" (0), "1" (dividend), "r" (divisor) );
951         return quotient;
952 }
953
954 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
955                                s8 *pshift, u32 *pmultiplier)
956 {
957         uint64_t scaled64;
958         int32_t  shift = 0;
959         uint64_t tps64;
960         uint32_t tps32;
961
962         tps64 = base_khz * 1000LL;
963         scaled64 = scaled_khz * 1000LL;
964         while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
965                 tps64 >>= 1;
966                 shift--;
967         }
968
969         tps32 = (uint32_t)tps64;
970         while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
971                 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
972                         scaled64 >>= 1;
973                 else
974                         tps32 <<= 1;
975                 shift++;
976         }
977
978         *pshift = shift;
979         *pmultiplier = div_frac(scaled64, tps32);
980
981         pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
982                  __func__, base_khz, scaled_khz, shift, *pmultiplier);
983 }
984
985 static inline u64 get_kernel_ns(void)
986 {
987         struct timespec ts;
988
989         WARN_ON(preemptible());
990         ktime_get_ts(&ts);
991         monotonic_to_bootbased(&ts);
992         return timespec_to_ns(&ts);
993 }
994
995 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
996 unsigned long max_tsc_khz;
997
998 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
999 {
1000         return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1001                                    vcpu->arch.virtual_tsc_shift);
1002 }
1003
1004 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1005 {
1006         u64 v = (u64)khz * (1000000 + ppm);
1007         do_div(v, 1000000);
1008         return v;
1009 }
1010
1011 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1012 {
1013         u32 thresh_lo, thresh_hi;
1014         int use_scaling = 0;
1015
1016         /* Compute a scale to convert nanoseconds in TSC cycles */
1017         kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1018                            &vcpu->arch.virtual_tsc_shift,
1019                            &vcpu->arch.virtual_tsc_mult);
1020         vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1021
1022         /*
1023          * Compute the variation in TSC rate which is acceptable
1024          * within the range of tolerance and decide if the
1025          * rate being applied is within that bounds of the hardware
1026          * rate.  If so, no scaling or compensation need be done.
1027          */
1028         thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1029         thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1030         if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1031                 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1032                 use_scaling = 1;
1033         }
1034         kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1035 }
1036
1037 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1038 {
1039         u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1040                                       vcpu->arch.virtual_tsc_mult,
1041                                       vcpu->arch.virtual_tsc_shift);
1042         tsc += vcpu->arch.this_tsc_write;
1043         return tsc;
1044 }
1045
1046 void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1047 {
1048         struct kvm *kvm = vcpu->kvm;
1049         u64 offset, ns, elapsed;
1050         unsigned long flags;
1051         s64 usdiff;
1052
1053         raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1054         offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1055         ns = get_kernel_ns();
1056         elapsed = ns - kvm->arch.last_tsc_nsec;
1057
1058         /* n.b - signed multiplication and division required */
1059         usdiff = data - kvm->arch.last_tsc_write;
1060 #ifdef CONFIG_X86_64
1061         usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1062 #else
1063         /* do_div() only does unsigned */
1064         asm("idivl %2; xor %%edx, %%edx"
1065             : "=A"(usdiff)
1066             : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
1067 #endif
1068         do_div(elapsed, 1000);
1069         usdiff -= elapsed;
1070         if (usdiff < 0)
1071                 usdiff = -usdiff;
1072
1073         /*
1074          * Special case: TSC write with a small delta (1 second) of virtual
1075          * cycle time against real time is interpreted as an attempt to
1076          * synchronize the CPU.
1077          *
1078          * For a reliable TSC, we can match TSC offsets, and for an unstable
1079          * TSC, we add elapsed time in this computation.  We could let the
1080          * compensation code attempt to catch up if we fall behind, but
1081          * it's better to try to match offsets from the beginning.
1082          */
1083         if (usdiff < USEC_PER_SEC &&
1084             vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1085                 if (!check_tsc_unstable()) {
1086                         offset = kvm->arch.cur_tsc_offset;
1087                         pr_debug("kvm: matched tsc offset for %llu\n", data);
1088                 } else {
1089                         u64 delta = nsec_to_cycles(vcpu, elapsed);
1090                         data += delta;
1091                         offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1092                         pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1093                 }
1094         } else {
1095                 /*
1096                  * We split periods of matched TSC writes into generations.
1097                  * For each generation, we track the original measured
1098                  * nanosecond time, offset, and write, so if TSCs are in
1099                  * sync, we can match exact offset, and if not, we can match
1100                  * exact software computation in compute_guest_tsc()
1101                  *
1102                  * These values are tracked in kvm->arch.cur_xxx variables.
1103                  */
1104                 kvm->arch.cur_tsc_generation++;
1105                 kvm->arch.cur_tsc_nsec = ns;
1106                 kvm->arch.cur_tsc_write = data;
1107                 kvm->arch.cur_tsc_offset = offset;
1108                 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1109                          kvm->arch.cur_tsc_generation, data);
1110         }
1111
1112         /*
1113          * We also track th most recent recorded KHZ, write and time to
1114          * allow the matching interval to be extended at each write.
1115          */
1116         kvm->arch.last_tsc_nsec = ns;
1117         kvm->arch.last_tsc_write = data;
1118         kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1119
1120         /* Reset of TSC must disable overshoot protection below */
1121         vcpu->arch.hv_clock.tsc_timestamp = 0;
1122         vcpu->arch.last_guest_tsc = data;
1123
1124         /* Keep track of which generation this VCPU has synchronized to */
1125         vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1126         vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1127         vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1128
1129         kvm_x86_ops->write_tsc_offset(vcpu, offset);
1130         raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1131 }
1132
1133 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1134
1135 static int kvm_guest_time_update(struct kvm_vcpu *v)
1136 {
1137         unsigned long flags;
1138         struct kvm_vcpu_arch *vcpu = &v->arch;
1139         void *shared_kaddr;
1140         unsigned long this_tsc_khz;
1141         s64 kernel_ns, max_kernel_ns;
1142         u64 tsc_timestamp;
1143
1144         /* Keep irq disabled to prevent changes to the clock */
1145         local_irq_save(flags);
1146         tsc_timestamp = kvm_x86_ops->read_l1_tsc(v);
1147         kernel_ns = get_kernel_ns();
1148         this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1149         if (unlikely(this_tsc_khz == 0)) {
1150                 local_irq_restore(flags);
1151                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1152                 return 1;
1153         }
1154
1155         /*
1156          * We may have to catch up the TSC to match elapsed wall clock
1157          * time for two reasons, even if kvmclock is used.
1158          *   1) CPU could have been running below the maximum TSC rate
1159          *   2) Broken TSC compensation resets the base at each VCPU
1160          *      entry to avoid unknown leaps of TSC even when running
1161          *      again on the same CPU.  This may cause apparent elapsed
1162          *      time to disappear, and the guest to stand still or run
1163          *      very slowly.
1164          */
1165         if (vcpu->tsc_catchup) {
1166                 u64 tsc = compute_guest_tsc(v, kernel_ns);
1167                 if (tsc > tsc_timestamp) {
1168                         adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1169                         tsc_timestamp = tsc;
1170                 }
1171         }
1172
1173         local_irq_restore(flags);
1174
1175         if (!vcpu->time_page)
1176                 return 0;
1177
1178         /*
1179          * Time as measured by the TSC may go backwards when resetting the base
1180          * tsc_timestamp.  The reason for this is that the TSC resolution is
1181          * higher than the resolution of the other clock scales.  Thus, many
1182          * possible measurments of the TSC correspond to one measurement of any
1183          * other clock, and so a spread of values is possible.  This is not a
1184          * problem for the computation of the nanosecond clock; with TSC rates
1185          * around 1GHZ, there can only be a few cycles which correspond to one
1186          * nanosecond value, and any path through this code will inevitably
1187          * take longer than that.  However, with the kernel_ns value itself,
1188          * the precision may be much lower, down to HZ granularity.  If the
1189          * first sampling of TSC against kernel_ns ends in the low part of the
1190          * range, and the second in the high end of the range, we can get:
1191          *
1192          * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1193          *
1194          * As the sampling errors potentially range in the thousands of cycles,
1195          * it is possible such a time value has already been observed by the
1196          * guest.  To protect against this, we must compute the system time as
1197          * observed by the guest and ensure the new system time is greater.
1198          */
1199         max_kernel_ns = 0;
1200         if (vcpu->hv_clock.tsc_timestamp) {
1201                 max_kernel_ns = vcpu->last_guest_tsc -
1202                                 vcpu->hv_clock.tsc_timestamp;
1203                 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1204                                     vcpu->hv_clock.tsc_to_system_mul,
1205                                     vcpu->hv_clock.tsc_shift);
1206                 max_kernel_ns += vcpu->last_kernel_ns;
1207         }
1208
1209         if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1210                 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1211                                    &vcpu->hv_clock.tsc_shift,
1212                                    &vcpu->hv_clock.tsc_to_system_mul);
1213                 vcpu->hw_tsc_khz = this_tsc_khz;
1214         }
1215
1216         if (max_kernel_ns > kernel_ns)
1217                 kernel_ns = max_kernel_ns;
1218
1219         /* With all the info we got, fill in the values */
1220         vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1221         vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1222         vcpu->last_kernel_ns = kernel_ns;
1223         vcpu->last_guest_tsc = tsc_timestamp;
1224         vcpu->hv_clock.flags = 0;
1225
1226         /*
1227          * The interface expects us to write an even number signaling that the
1228          * update is finished. Since the guest won't see the intermediate
1229          * state, we just increase by 2 at the end.
1230          */
1231         vcpu->hv_clock.version += 2;
1232
1233         shared_kaddr = kmap_atomic(vcpu->time_page);
1234
1235         memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
1236                sizeof(vcpu->hv_clock));
1237
1238         kunmap_atomic(shared_kaddr);
1239
1240         mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
1241         return 0;
1242 }
1243
1244 static bool msr_mtrr_valid(unsigned msr)
1245 {
1246         switch (msr) {
1247         case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1248         case MSR_MTRRfix64K_00000:
1249         case MSR_MTRRfix16K_80000:
1250         case MSR_MTRRfix16K_A0000:
1251         case MSR_MTRRfix4K_C0000:
1252         case MSR_MTRRfix4K_C8000:
1253         case MSR_MTRRfix4K_D0000:
1254         case MSR_MTRRfix4K_D8000:
1255         case MSR_MTRRfix4K_E0000:
1256         case MSR_MTRRfix4K_E8000:
1257         case MSR_MTRRfix4K_F0000:
1258         case MSR_MTRRfix4K_F8000:
1259         case MSR_MTRRdefType:
1260         case MSR_IA32_CR_PAT:
1261                 return true;
1262         case 0x2f8:
1263                 return true;
1264         }
1265         return false;
1266 }
1267
1268 static bool valid_pat_type(unsigned t)
1269 {
1270         return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1271 }
1272
1273 static bool valid_mtrr_type(unsigned t)
1274 {
1275         return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1276 }
1277
1278 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1279 {
1280         int i;
1281
1282         if (!msr_mtrr_valid(msr))
1283                 return false;
1284
1285         if (msr == MSR_IA32_CR_PAT) {
1286                 for (i = 0; i < 8; i++)
1287                         if (!valid_pat_type((data >> (i * 8)) & 0xff))
1288                                 return false;
1289                 return true;
1290         } else if (msr == MSR_MTRRdefType) {
1291                 if (data & ~0xcff)
1292                         return false;
1293                 return valid_mtrr_type(data & 0xff);
1294         } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1295                 for (i = 0; i < 8 ; i++)
1296                         if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1297                                 return false;
1298                 return true;
1299         }
1300
1301         /* variable MTRRs */
1302         return valid_mtrr_type(data & 0xff);
1303 }
1304
1305 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1306 {
1307         u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1308
1309         if (!mtrr_valid(vcpu, msr, data))
1310                 return 1;
1311
1312         if (msr == MSR_MTRRdefType) {
1313                 vcpu->arch.mtrr_state.def_type = data;
1314                 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1315         } else if (msr == MSR_MTRRfix64K_00000)
1316                 p[0] = data;
1317         else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1318                 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1319         else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1320                 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1321         else if (msr == MSR_IA32_CR_PAT)
1322                 vcpu->arch.pat = data;
1323         else {  /* Variable MTRRs */
1324                 int idx, is_mtrr_mask;
1325                 u64 *pt;
1326
1327                 idx = (msr - 0x200) / 2;
1328                 is_mtrr_mask = msr - 0x200 - 2 * idx;
1329                 if (!is_mtrr_mask)
1330                         pt =
1331                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1332                 else
1333                         pt =
1334                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1335                 *pt = data;
1336         }
1337
1338         kvm_mmu_reset_context(vcpu);
1339         return 0;
1340 }
1341
1342 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1343 {
1344         u64 mcg_cap = vcpu->arch.mcg_cap;
1345         unsigned bank_num = mcg_cap & 0xff;
1346
1347         switch (msr) {
1348         case MSR_IA32_MCG_STATUS:
1349                 vcpu->arch.mcg_status = data;
1350                 break;
1351         case MSR_IA32_MCG_CTL:
1352                 if (!(mcg_cap & MCG_CTL_P))
1353                         return 1;
1354                 if (data != 0 && data != ~(u64)0)
1355                         return -1;
1356                 vcpu->arch.mcg_ctl = data;
1357                 break;
1358         default:
1359                 if (msr >= MSR_IA32_MC0_CTL &&
1360                     msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1361                         u32 offset = msr - MSR_IA32_MC0_CTL;
1362                         /* only 0 or all 1s can be written to IA32_MCi_CTL
1363                          * some Linux kernels though clear bit 10 in bank 4 to
1364                          * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1365                          * this to avoid an uncatched #GP in the guest
1366                          */
1367                         if ((offset & 0x3) == 0 &&
1368                             data != 0 && (data | (1 << 10)) != ~(u64)0)
1369                                 return -1;
1370                         vcpu->arch.mce_banks[offset] = data;
1371                         break;
1372                 }
1373                 return 1;
1374         }
1375         return 0;
1376 }
1377
1378 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1379 {
1380         struct kvm *kvm = vcpu->kvm;
1381         int lm = is_long_mode(vcpu);
1382         u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1383                 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1384         u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1385                 : kvm->arch.xen_hvm_config.blob_size_32;
1386         u32 page_num = data & ~PAGE_MASK;
1387         u64 page_addr = data & PAGE_MASK;
1388         u8 *page;
1389         int r;
1390
1391         r = -E2BIG;
1392         if (page_num >= blob_size)
1393                 goto out;
1394         r = -ENOMEM;
1395         page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1396         if (IS_ERR(page)) {
1397                 r = PTR_ERR(page);
1398                 goto out;
1399         }
1400         if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1401                 goto out_free;
1402         r = 0;
1403 out_free:
1404         kfree(page);
1405 out:
1406         return r;
1407 }
1408
1409 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1410 {
1411         return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1412 }
1413
1414 static bool kvm_hv_msr_partition_wide(u32 msr)
1415 {
1416         bool r = false;
1417         switch (msr) {
1418         case HV_X64_MSR_GUEST_OS_ID:
1419         case HV_X64_MSR_HYPERCALL:
1420                 r = true;
1421                 break;
1422         }
1423
1424         return r;
1425 }
1426
1427 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1428 {
1429         struct kvm *kvm = vcpu->kvm;
1430
1431         switch (msr) {
1432         case HV_X64_MSR_GUEST_OS_ID:
1433                 kvm->arch.hv_guest_os_id = data;
1434                 /* setting guest os id to zero disables hypercall page */
1435                 if (!kvm->arch.hv_guest_os_id)
1436                         kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1437                 break;
1438         case HV_X64_MSR_HYPERCALL: {
1439                 u64 gfn;
1440                 unsigned long addr;
1441                 u8 instructions[4];
1442
1443                 /* if guest os id is not set hypercall should remain disabled */
1444                 if (!kvm->arch.hv_guest_os_id)
1445                         break;
1446                 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1447                         kvm->arch.hv_hypercall = data;
1448                         break;
1449                 }
1450                 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1451                 addr = gfn_to_hva(kvm, gfn);
1452                 if (kvm_is_error_hva(addr))
1453                         return 1;
1454                 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1455                 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1456                 if (__copy_to_user((void __user *)addr, instructions, 4))
1457                         return 1;
1458                 kvm->arch.hv_hypercall = data;
1459                 break;
1460         }
1461         default:
1462                 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1463                             "data 0x%llx\n", msr, data);
1464                 return 1;
1465         }
1466         return 0;
1467 }
1468
1469 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1470 {
1471         switch (msr) {
1472         case HV_X64_MSR_APIC_ASSIST_PAGE: {
1473                 unsigned long addr;
1474
1475                 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1476                         vcpu->arch.hv_vapic = data;
1477                         break;
1478                 }
1479                 addr = gfn_to_hva(vcpu->kvm, data >>
1480                                   HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1481                 if (kvm_is_error_hva(addr))
1482                         return 1;
1483                 if (__clear_user((void __user *)addr, PAGE_SIZE))
1484                         return 1;
1485                 vcpu->arch.hv_vapic = data;
1486                 break;
1487         }
1488         case HV_X64_MSR_EOI:
1489                 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1490         case HV_X64_MSR_ICR:
1491                 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1492         case HV_X64_MSR_TPR:
1493                 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1494         default:
1495                 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1496                             "data 0x%llx\n", msr, data);
1497                 return 1;
1498         }
1499
1500         return 0;
1501 }
1502
1503 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1504 {
1505         gpa_t gpa = data & ~0x3f;
1506
1507         /* Bits 2:5 are reserved, Should be zero */
1508         if (data & 0x3c)
1509                 return 1;
1510
1511         vcpu->arch.apf.msr_val = data;
1512
1513         if (!(data & KVM_ASYNC_PF_ENABLED)) {
1514                 kvm_clear_async_pf_completion_queue(vcpu);
1515                 kvm_async_pf_hash_reset(vcpu);
1516                 return 0;
1517         }
1518
1519         if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1520                 return 1;
1521
1522         vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1523         kvm_async_pf_wakeup_all(vcpu);
1524         return 0;
1525 }
1526
1527 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1528 {
1529         if (vcpu->arch.time_page) {
1530                 kvm_release_page_dirty(vcpu->arch.time_page);
1531                 vcpu->arch.time_page = NULL;
1532         }
1533 }
1534
1535 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1536 {
1537         u64 delta;
1538
1539         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1540                 return;
1541
1542         delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1543         vcpu->arch.st.last_steal = current->sched_info.run_delay;
1544         vcpu->arch.st.accum_steal = delta;
1545 }
1546
1547 static void record_steal_time(struct kvm_vcpu *vcpu)
1548 {
1549         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1550                 return;
1551
1552         if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1553                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1554                 return;
1555
1556         vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1557         vcpu->arch.st.steal.version += 2;
1558         vcpu->arch.st.accum_steal = 0;
1559
1560         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1561                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1562 }
1563
1564 int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1565 {
1566         bool pr = false;
1567
1568         switch (msr) {
1569         case MSR_EFER:
1570                 return set_efer(vcpu, data);
1571         case MSR_K7_HWCR:
1572                 data &= ~(u64)0x40;     /* ignore flush filter disable */
1573                 data &= ~(u64)0x100;    /* ignore ignne emulation enable */
1574                 data &= ~(u64)0x8;      /* ignore TLB cache disable */
1575                 if (data != 0) {
1576                         vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1577                                     data);
1578                         return 1;
1579                 }
1580                 break;
1581         case MSR_FAM10H_MMIO_CONF_BASE:
1582                 if (data != 0) {
1583                         vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1584                                     "0x%llx\n", data);
1585                         return 1;
1586                 }
1587                 break;
1588         case MSR_AMD64_NB_CFG:
1589                 break;
1590         case MSR_IA32_DEBUGCTLMSR:
1591                 if (!data) {
1592                         /* We support the non-activated case already */
1593                         break;
1594                 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1595                         /* Values other than LBR and BTF are vendor-specific,
1596                            thus reserved and should throw a #GP */
1597                         return 1;
1598                 }
1599                 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1600                             __func__, data);
1601                 break;
1602         case MSR_IA32_UCODE_REV:
1603         case MSR_IA32_UCODE_WRITE:
1604         case MSR_VM_HSAVE_PA:
1605         case MSR_AMD64_PATCH_LOADER:
1606                 break;
1607         case 0x200 ... 0x2ff:
1608                 return set_msr_mtrr(vcpu, msr, data);
1609         case MSR_IA32_APICBASE:
1610                 kvm_set_apic_base(vcpu, data);
1611                 break;
1612         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1613                 return kvm_x2apic_msr_write(vcpu, msr, data);
1614         case MSR_IA32_TSCDEADLINE:
1615                 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1616                 break;
1617         case MSR_IA32_MISC_ENABLE:
1618                 vcpu->arch.ia32_misc_enable_msr = data;
1619                 break;
1620         case MSR_KVM_WALL_CLOCK_NEW:
1621         case MSR_KVM_WALL_CLOCK:
1622                 vcpu->kvm->arch.wall_clock = data;
1623                 kvm_write_wall_clock(vcpu->kvm, data);
1624                 break;
1625         case MSR_KVM_SYSTEM_TIME_NEW:
1626         case MSR_KVM_SYSTEM_TIME: {
1627                 kvmclock_reset(vcpu);
1628
1629                 vcpu->arch.time = data;
1630                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1631
1632                 /* we verify if the enable bit is set... */
1633                 if (!(data & 1))
1634                         break;
1635
1636                 /* ...but clean it before doing the actual write */
1637                 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1638
1639                 vcpu->arch.time_page =
1640                                 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
1641
1642                 if (is_error_page(vcpu->arch.time_page)) {
1643                         kvm_release_page_clean(vcpu->arch.time_page);
1644                         vcpu->arch.time_page = NULL;
1645                 }
1646                 break;
1647         }
1648         case MSR_KVM_ASYNC_PF_EN:
1649                 if (kvm_pv_enable_async_pf(vcpu, data))
1650                         return 1;
1651                 break;
1652         case MSR_KVM_STEAL_TIME:
1653
1654                 if (unlikely(!sched_info_on()))
1655                         return 1;
1656
1657                 if (data & KVM_STEAL_RESERVED_MASK)
1658                         return 1;
1659
1660                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1661                                                         data & KVM_STEAL_VALID_BITS))
1662                         return 1;
1663
1664                 vcpu->arch.st.msr_val = data;
1665
1666                 if (!(data & KVM_MSR_ENABLED))
1667                         break;
1668
1669                 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1670
1671                 preempt_disable();
1672                 accumulate_steal_time(vcpu);
1673                 preempt_enable();
1674
1675                 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1676
1677                 break;
1678         case MSR_KVM_PV_EOI_EN:
1679                 if (kvm_lapic_enable_pv_eoi(vcpu, data))
1680                         return 1;
1681                 break;
1682
1683         case MSR_IA32_MCG_CTL:
1684         case MSR_IA32_MCG_STATUS:
1685         case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1686                 return set_msr_mce(vcpu, msr, data);
1687
1688         /* Performance counters are not protected by a CPUID bit,
1689          * so we should check all of them in the generic path for the sake of
1690          * cross vendor migration.
1691          * Writing a zero into the event select MSRs disables them,
1692          * which we perfectly emulate ;-). Any other value should be at least
1693          * reported, some guests depend on them.
1694          */
1695         case MSR_K7_EVNTSEL0:
1696         case MSR_K7_EVNTSEL1:
1697         case MSR_K7_EVNTSEL2:
1698         case MSR_K7_EVNTSEL3:
1699                 if (data != 0)
1700                         vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1701                                     "0x%x data 0x%llx\n", msr, data);
1702                 break;
1703         /* at least RHEL 4 unconditionally writes to the perfctr registers,
1704          * so we ignore writes to make it happy.
1705          */
1706         case MSR_K7_PERFCTR0:
1707         case MSR_K7_PERFCTR1:
1708         case MSR_K7_PERFCTR2:
1709         case MSR_K7_PERFCTR3:
1710                 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1711                             "0x%x data 0x%llx\n", msr, data);
1712                 break;
1713         case MSR_P6_PERFCTR0:
1714         case MSR_P6_PERFCTR1:
1715                 pr = true;
1716         case MSR_P6_EVNTSEL0:
1717         case MSR_P6_EVNTSEL1:
1718                 if (kvm_pmu_msr(vcpu, msr))
1719                         return kvm_pmu_set_msr(vcpu, msr, data);
1720
1721                 if (pr || data != 0)
1722                         vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
1723                                     "0x%x data 0x%llx\n", msr, data);
1724                 break;
1725         case MSR_K7_CLK_CTL:
1726                 /*
1727                  * Ignore all writes to this no longer documented MSR.
1728                  * Writes are only relevant for old K7 processors,
1729                  * all pre-dating SVM, but a recommended workaround from
1730                  * AMD for these chips. It is possible to specify the
1731                  * affected processor models on the command line, hence
1732                  * the need to ignore the workaround.
1733                  */
1734                 break;
1735         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1736                 if (kvm_hv_msr_partition_wide(msr)) {
1737                         int r;
1738                         mutex_lock(&vcpu->kvm->lock);
1739                         r = set_msr_hyperv_pw(vcpu, msr, data);
1740                         mutex_unlock(&vcpu->kvm->lock);
1741                         return r;
1742                 } else
1743                         return set_msr_hyperv(vcpu, msr, data);
1744                 break;
1745         case MSR_IA32_BBL_CR_CTL3:
1746                 /* Drop writes to this legacy MSR -- see rdmsr
1747                  * counterpart for further detail.
1748                  */
1749                 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
1750                 break;
1751         case MSR_AMD64_OSVW_ID_LENGTH:
1752                 if (!guest_cpuid_has_osvw(vcpu))
1753                         return 1;
1754                 vcpu->arch.osvw.length = data;
1755                 break;
1756         case MSR_AMD64_OSVW_STATUS:
1757                 if (!guest_cpuid_has_osvw(vcpu))
1758                         return 1;
1759                 vcpu->arch.osvw.status = data;
1760                 break;
1761         default:
1762                 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1763                         return xen_hvm_config(vcpu, data);
1764                 if (kvm_pmu_msr(vcpu, msr))
1765                         return kvm_pmu_set_msr(vcpu, msr, data);
1766                 if (!ignore_msrs) {
1767                         vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1768                                     msr, data);
1769                         return 1;
1770                 } else {
1771                         vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1772                                     msr, data);
1773                         break;
1774                 }
1775         }
1776         return 0;
1777 }
1778 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1779
1780
1781 /*
1782  * Reads an msr value (of 'msr_index') into 'pdata'.
1783  * Returns 0 on success, non-0 otherwise.
1784  * Assumes vcpu_load() was already called.
1785  */
1786 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1787 {
1788         return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1789 }
1790
1791 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1792 {
1793         u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1794
1795         if (!msr_mtrr_valid(msr))
1796                 return 1;
1797
1798         if (msr == MSR_MTRRdefType)
1799                 *pdata = vcpu->arch.mtrr_state.def_type +
1800                          (vcpu->arch.mtrr_state.enabled << 10);
1801         else if (msr == MSR_MTRRfix64K_00000)
1802                 *pdata = p[0];
1803         else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1804                 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1805         else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1806                 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1807         else if (msr == MSR_IA32_CR_PAT)
1808                 *pdata = vcpu->arch.pat;
1809         else {  /* Variable MTRRs */
1810                 int idx, is_mtrr_mask;
1811                 u64 *pt;
1812
1813                 idx = (msr - 0x200) / 2;
1814                 is_mtrr_mask = msr - 0x200 - 2 * idx;
1815                 if (!is_mtrr_mask)
1816                         pt =
1817                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1818                 else
1819                         pt =
1820                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1821                 *pdata = *pt;
1822         }
1823
1824         return 0;
1825 }
1826
1827 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1828 {
1829         u64 data;
1830         u64 mcg_cap = vcpu->arch.mcg_cap;
1831         unsigned bank_num = mcg_cap & 0xff;
1832
1833         switch (msr) {
1834         case MSR_IA32_P5_MC_ADDR:
1835         case MSR_IA32_P5_MC_TYPE:
1836                 data = 0;
1837                 break;
1838         case MSR_IA32_MCG_CAP:
1839                 data = vcpu->arch.mcg_cap;
1840                 break;
1841         case MSR_IA32_MCG_CTL:
1842                 if (!(mcg_cap & MCG_CTL_P))
1843                         return 1;
1844                 data = vcpu->arch.mcg_ctl;
1845                 break;
1846         case MSR_IA32_MCG_STATUS:
1847                 data = vcpu->arch.mcg_status;
1848                 break;
1849         default:
1850                 if (msr >= MSR_IA32_MC0_CTL &&
1851                     msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1852                         u32 offset = msr - MSR_IA32_MC0_CTL;
1853                         data = vcpu->arch.mce_banks[offset];
1854                         break;
1855                 }
1856                 return 1;
1857         }
1858         *pdata = data;
1859         return 0;
1860 }
1861
1862 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1863 {
1864         u64 data = 0;
1865         struct kvm *kvm = vcpu->kvm;
1866
1867         switch (msr) {
1868         case HV_X64_MSR_GUEST_OS_ID:
1869                 data = kvm->arch.hv_guest_os_id;
1870                 break;
1871         case HV_X64_MSR_HYPERCALL:
1872                 data = kvm->arch.hv_hypercall;
1873                 break;
1874         default:
1875                 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1876                 return 1;
1877         }
1878
1879         *pdata = data;
1880         return 0;
1881 }
1882
1883 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1884 {
1885         u64 data = 0;
1886
1887         switch (msr) {
1888         case HV_X64_MSR_VP_INDEX: {
1889                 int r;
1890                 struct kvm_vcpu *v;
1891                 kvm_for_each_vcpu(r, v, vcpu->kvm)
1892                         if (v == vcpu)
1893                                 data = r;
1894                 break;
1895         }
1896         case HV_X64_MSR_EOI:
1897                 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1898         case HV_X64_MSR_ICR:
1899                 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1900         case HV_X64_MSR_TPR:
1901                 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
1902         case HV_X64_MSR_APIC_ASSIST_PAGE:
1903                 data = vcpu->arch.hv_vapic;
1904                 break;
1905         default:
1906                 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1907                 return 1;
1908         }
1909         *pdata = data;
1910         return 0;
1911 }
1912
1913 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1914 {
1915         u64 data;
1916
1917         switch (msr) {
1918         case MSR_IA32_PLATFORM_ID:
1919         case MSR_IA32_EBL_CR_POWERON:
1920         case MSR_IA32_DEBUGCTLMSR:
1921         case MSR_IA32_LASTBRANCHFROMIP:
1922         case MSR_IA32_LASTBRANCHTOIP:
1923         case MSR_IA32_LASTINTFROMIP:
1924         case MSR_IA32_LASTINTTOIP:
1925         case MSR_K8_SYSCFG:
1926         case MSR_K7_HWCR:
1927         case MSR_VM_HSAVE_PA:
1928         case MSR_K7_EVNTSEL0:
1929         case MSR_K7_PERFCTR0:
1930         case MSR_K8_INT_PENDING_MSG:
1931         case MSR_AMD64_NB_CFG:
1932         case MSR_FAM10H_MMIO_CONF_BASE:
1933                 data = 0;
1934                 break;
1935         case MSR_P6_PERFCTR0:
1936         case MSR_P6_PERFCTR1:
1937         case MSR_P6_EVNTSEL0:
1938         case MSR_P6_EVNTSEL1:
1939                 if (kvm_pmu_msr(vcpu, msr))
1940                         return kvm_pmu_get_msr(vcpu, msr, pdata);
1941                 data = 0;
1942                 break;
1943         case MSR_IA32_UCODE_REV:
1944                 data = 0x100000000ULL;
1945                 break;
1946         case MSR_MTRRcap:
1947                 data = 0x500 | KVM_NR_VAR_MTRR;
1948                 break;
1949         case 0x200 ... 0x2ff:
1950                 return get_msr_mtrr(vcpu, msr, pdata);
1951         case 0xcd: /* fsb frequency */
1952                 data = 3;
1953                 break;
1954                 /*
1955                  * MSR_EBC_FREQUENCY_ID
1956                  * Conservative value valid for even the basic CPU models.
1957                  * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1958                  * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1959                  * and 266MHz for model 3, or 4. Set Core Clock
1960                  * Frequency to System Bus Frequency Ratio to 1 (bits
1961                  * 31:24) even though these are only valid for CPU
1962                  * models > 2, however guests may end up dividing or
1963                  * multiplying by zero otherwise.
1964                  */
1965         case MSR_EBC_FREQUENCY_ID:
1966                 data = 1 << 24;
1967                 break;
1968         case MSR_IA32_APICBASE:
1969                 data = kvm_get_apic_base(vcpu);
1970                 break;
1971         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1972                 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1973                 break;
1974         case MSR_IA32_TSCDEADLINE:
1975                 data = kvm_get_lapic_tscdeadline_msr(vcpu);
1976                 break;
1977         case MSR_IA32_MISC_ENABLE:
1978                 data = vcpu->arch.ia32_misc_enable_msr;
1979                 break;
1980         case MSR_IA32_PERF_STATUS:
1981                 /* TSC increment by tick */
1982                 data = 1000ULL;
1983                 /* CPU multiplier */
1984                 data |= (((uint64_t)4ULL) << 40);
1985                 break;
1986         case MSR_EFER:
1987                 data = vcpu->arch.efer;
1988                 break;
1989         case MSR_KVM_WALL_CLOCK:
1990         case MSR_KVM_WALL_CLOCK_NEW:
1991                 data = vcpu->kvm->arch.wall_clock;
1992                 break;
1993         case MSR_KVM_SYSTEM_TIME:
1994         case MSR_KVM_SYSTEM_TIME_NEW:
1995                 data = vcpu->arch.time;
1996                 break;
1997         case MSR_KVM_ASYNC_PF_EN:
1998                 data = vcpu->arch.apf.msr_val;
1999                 break;
2000         case MSR_KVM_STEAL_TIME:
2001                 data = vcpu->arch.st.msr_val;
2002                 break;
2003         case MSR_IA32_P5_MC_ADDR:
2004         case MSR_IA32_P5_MC_TYPE:
2005         case MSR_IA32_MCG_CAP:
2006         case MSR_IA32_MCG_CTL:
2007         case MSR_IA32_MCG_STATUS:
2008         case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2009                 return get_msr_mce(vcpu, msr, pdata);
2010         case MSR_K7_CLK_CTL:
2011                 /*
2012                  * Provide expected ramp-up count for K7. All other
2013                  * are set to zero, indicating minimum divisors for
2014                  * every field.
2015                  *
2016                  * This prevents guest kernels on AMD host with CPU
2017                  * type 6, model 8 and higher from exploding due to
2018                  * the rdmsr failing.
2019                  */
2020                 data = 0x20000000;
2021                 break;
2022         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2023                 if (kvm_hv_msr_partition_wide(msr)) {
2024                         int r;
2025                         mutex_lock(&vcpu->kvm->lock);
2026                         r = get_msr_hyperv_pw(vcpu, msr, pdata);
2027                         mutex_unlock(&vcpu->kvm->lock);
2028                         return r;
2029                 } else
2030                         return get_msr_hyperv(vcpu, msr, pdata);
2031                 break;
2032         case MSR_IA32_BBL_CR_CTL3:
2033                 /* This legacy MSR exists but isn't fully documented in current
2034                  * silicon.  It is however accessed by winxp in very narrow
2035                  * scenarios where it sets bit #19, itself documented as
2036                  * a "reserved" bit.  Best effort attempt to source coherent
2037                  * read data here should the balance of the register be
2038                  * interpreted by the guest:
2039                  *
2040                  * L2 cache control register 3: 64GB range, 256KB size,
2041                  * enabled, latency 0x1, configured
2042                  */
2043                 data = 0xbe702111;
2044                 break;
2045         case MSR_AMD64_OSVW_ID_LENGTH:
2046                 if (!guest_cpuid_has_osvw(vcpu))
2047                         return 1;
2048                 data = vcpu->arch.osvw.length;
2049                 break;
2050         case MSR_AMD64_OSVW_STATUS:
2051                 if (!guest_cpuid_has_osvw(vcpu))
2052                         return 1;
2053                 data = vcpu->arch.osvw.status;
2054                 break;
2055         default:
2056                 if (kvm_pmu_msr(vcpu, msr))
2057                         return kvm_pmu_get_msr(vcpu, msr, pdata);
2058                 if (!ignore_msrs) {
2059                         vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2060                         return 1;
2061                 } else {
2062                         vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2063                         data = 0;
2064                 }
2065                 break;
2066         }
2067         *pdata = data;
2068         return 0;
2069 }
2070 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2071
2072 /*
2073  * Read or write a bunch of msrs. All parameters are kernel addresses.
2074  *
2075  * @return number of msrs set successfully.
2076  */
2077 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2078                     struct kvm_msr_entry *entries,
2079                     int (*do_msr)(struct kvm_vcpu *vcpu,
2080                                   unsigned index, u64 *data))
2081 {
2082         int i, idx;
2083
2084         idx = srcu_read_lock(&vcpu->kvm->srcu);
2085         for (i = 0; i < msrs->nmsrs; ++i)
2086                 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2087                         break;
2088         srcu_read_unlock(&vcpu->kvm->srcu, idx);
2089
2090         return i;
2091 }
2092
2093 /*
2094  * Read or write a bunch of msrs. Parameters are user addresses.
2095  *
2096  * @return number of msrs set successfully.
2097  */
2098 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2099                   int (*do_msr)(struct kvm_vcpu *vcpu,
2100                                 unsigned index, u64 *data),
2101                   int writeback)
2102 {
2103         struct kvm_msrs msrs;
2104         struct kvm_msr_entry *entries;
2105         int r, n;
2106         unsigned size;
2107
2108         r = -EFAULT;
2109         if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2110                 goto out;
2111
2112         r = -E2BIG;
2113         if (msrs.nmsrs >= MAX_IO_MSRS)
2114                 goto out;
2115
2116         size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2117         entries = memdup_user(user_msrs->entries, size);
2118         if (IS_ERR(entries)) {
2119                 r = PTR_ERR(entries);
2120                 goto out;
2121         }
2122
2123         r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2124         if (r < 0)
2125                 goto out_free;
2126
2127         r = -EFAULT;
2128         if (writeback && copy_to_user(user_msrs->entries, entries, size))
2129                 goto out_free;
2130
2131         r = n;
2132
2133 out_free:
2134         kfree(entries);
2135 out:
2136         return r;
2137 }
2138
2139 int kvm_dev_ioctl_check_extension(long ext)
2140 {
2141         int r;
2142
2143         switch (ext) {
2144         case KVM_CAP_IRQCHIP:
2145         case KVM_CAP_HLT:
2146         case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2147         case KVM_CAP_SET_TSS_ADDR:
2148         case KVM_CAP_EXT_CPUID:
2149         case KVM_CAP_CLOCKSOURCE:
2150         case KVM_CAP_PIT:
2151         case KVM_CAP_NOP_IO_DELAY:
2152         case KVM_CAP_MP_STATE:
2153         case KVM_CAP_SYNC_MMU:
2154         case KVM_CAP_USER_NMI:
2155         case KVM_CAP_REINJECT_CONTROL:
2156         case KVM_CAP_IRQ_INJECT_STATUS:
2157         case KVM_CAP_ASSIGN_DEV_IRQ:
2158         case KVM_CAP_IRQFD:
2159         case KVM_CAP_IOEVENTFD:
2160         case KVM_CAP_PIT2:
2161         case KVM_CAP_PIT_STATE2:
2162         case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2163         case KVM_CAP_XEN_HVM:
2164         case KVM_CAP_ADJUST_CLOCK:
2165         case KVM_CAP_VCPU_EVENTS:
2166         case KVM_CAP_HYPERV:
2167         case KVM_CAP_HYPERV_VAPIC:
2168         case KVM_CAP_HYPERV_SPIN:
2169         case KVM_CAP_PCI_SEGMENT:
2170         case KVM_CAP_DEBUGREGS:
2171         case KVM_CAP_X86_ROBUST_SINGLESTEP:
2172         case KVM_CAP_XSAVE:
2173         case KVM_CAP_ASYNC_PF:
2174         case KVM_CAP_GET_TSC_KHZ:
2175         case KVM_CAP_PCI_2_3:
2176         case KVM_CAP_KVMCLOCK_CTRL:
2177                 r = 1;
2178                 break;
2179         case KVM_CAP_COALESCED_MMIO:
2180                 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2181                 break;
2182         case KVM_CAP_VAPIC:
2183                 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2184                 break;
2185         case KVM_CAP_NR_VCPUS:
2186                 r = KVM_SOFT_MAX_VCPUS;
2187                 break;
2188         case KVM_CAP_MAX_VCPUS:
2189                 r = KVM_MAX_VCPUS;
2190                 break;
2191         case KVM_CAP_NR_MEMSLOTS:
2192                 r = KVM_MEMORY_SLOTS;
2193                 break;
2194         case KVM_CAP_PV_MMU:    /* obsolete */
2195                 r = 0;
2196                 break;
2197         case KVM_CAP_IOMMU:
2198                 r = iommu_present(&pci_bus_type);
2199                 break;
2200         case KVM_CAP_MCE:
2201                 r = KVM_MAX_MCE_BANKS;
2202                 break;
2203         case KVM_CAP_XCRS:
2204                 r = cpu_has_xsave;
2205                 break;
2206         case KVM_CAP_TSC_CONTROL:
2207                 r = kvm_has_tsc_control;
2208                 break;
2209         case KVM_CAP_TSC_DEADLINE_TIMER:
2210                 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2211                 break;
2212         default:
2213                 r = 0;
2214                 break;
2215         }
2216         return r;
2217
2218 }
2219
2220 long kvm_arch_dev_ioctl(struct file *filp,
2221                         unsigned int ioctl, unsigned long arg)
2222 {
2223         void __user *argp = (void __user *)arg;
2224         long r;
2225
2226         switch (ioctl) {
2227         case KVM_GET_MSR_INDEX_LIST: {
2228                 struct kvm_msr_list __user *user_msr_list = argp;
2229                 struct kvm_msr_list msr_list;
2230                 unsigned n;
2231
2232                 r = -EFAULT;
2233                 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2234                         goto out;
2235                 n = msr_list.nmsrs;
2236                 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2237                 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2238                         goto out;
2239                 r = -E2BIG;
2240                 if (n < msr_list.nmsrs)
2241                         goto out;
2242                 r = -EFAULT;
2243                 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2244                                  num_msrs_to_save * sizeof(u32)))
2245                         goto out;
2246                 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2247                                  &emulated_msrs,
2248                                  ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2249                         goto out;
2250                 r = 0;
2251                 break;
2252         }
2253         case KVM_GET_SUPPORTED_CPUID: {
2254                 struct kvm_cpuid2 __user *cpuid_arg = argp;
2255                 struct kvm_cpuid2 cpuid;
2256
2257                 r = -EFAULT;
2258                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2259                         goto out;
2260                 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
2261                                                       cpuid_arg->entries);
2262                 if (r)
2263                         goto out;
2264
2265                 r = -EFAULT;
2266                 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2267                         goto out;
2268                 r = 0;
2269                 break;
2270         }
2271         case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2272                 u64 mce_cap;
2273
2274                 mce_cap = KVM_MCE_CAP_SUPPORTED;
2275                 r = -EFAULT;
2276                 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2277                         goto out;
2278                 r = 0;
2279                 break;
2280         }
2281         default:
2282                 r = -EINVAL;
2283         }
2284 out:
2285         return r;
2286 }
2287
2288 static void wbinvd_ipi(void *garbage)
2289 {
2290         wbinvd();
2291 }
2292
2293 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2294 {
2295         return vcpu->kvm->arch.iommu_domain &&
2296                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2297 }
2298
2299 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2300 {
2301         /* Address WBINVD may be executed by guest */
2302         if (need_emulate_wbinvd(vcpu)) {
2303                 if (kvm_x86_ops->has_wbinvd_exit())
2304                         cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2305                 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2306                         smp_call_function_single(vcpu->cpu,
2307                                         wbinvd_ipi, NULL, 1);
2308         }
2309
2310         kvm_x86_ops->vcpu_load(vcpu, cpu);
2311
2312         /* Apply any externally detected TSC adjustments (due to suspend) */
2313         if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2314                 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2315                 vcpu->arch.tsc_offset_adjustment = 0;
2316                 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2317         }
2318
2319         if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2320                 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2321                                 native_read_tsc() - vcpu->arch.last_host_tsc;
2322                 if (tsc_delta < 0)
2323                         mark_tsc_unstable("KVM discovered backwards TSC");
2324                 if (check_tsc_unstable()) {
2325                         u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2326                                                 vcpu->arch.last_guest_tsc);
2327                         kvm_x86_ops->write_tsc_offset(vcpu, offset);
2328                         vcpu->arch.tsc_catchup = 1;
2329                 }
2330                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2331                 if (vcpu->cpu != cpu)
2332                         kvm_migrate_timers(vcpu);
2333                 vcpu->cpu = cpu;
2334         }
2335
2336         accumulate_steal_time(vcpu);
2337         kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2338 }
2339
2340 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2341 {
2342         kvm_x86_ops->vcpu_put(vcpu);
2343         kvm_put_guest_fpu(vcpu);
2344         vcpu->arch.last_host_tsc = native_read_tsc();
2345 }
2346
2347 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2348                                     struct kvm_lapic_state *s)
2349 {
2350         memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2351
2352         return 0;
2353 }
2354
2355 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2356                                     struct kvm_lapic_state *s)
2357 {
2358         memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
2359         kvm_apic_post_state_restore(vcpu);
2360         update_cr8_intercept(vcpu);
2361
2362         return 0;
2363 }
2364
2365 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2366                                     struct kvm_interrupt *irq)
2367 {
2368         if (irq->irq < 0 || irq->irq >= 256)
2369                 return -EINVAL;
2370         if (irqchip_in_kernel(vcpu->kvm))
2371                 return -ENXIO;
2372
2373         kvm_queue_interrupt(vcpu, irq->irq, false);
2374         kvm_make_request(KVM_REQ_EVENT, vcpu);
2375
2376         return 0;
2377 }
2378
2379 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2380 {
2381         kvm_inject_nmi(vcpu);
2382
2383         return 0;
2384 }
2385
2386 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2387                                            struct kvm_tpr_access_ctl *tac)
2388 {
2389         if (tac->flags)
2390                 return -EINVAL;
2391         vcpu->arch.tpr_access_reporting = !!tac->enabled;
2392         return 0;
2393 }
2394
2395 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2396                                         u64 mcg_cap)
2397 {
2398         int r;
2399         unsigned bank_num = mcg_cap & 0xff, bank;
2400
2401         r = -EINVAL;
2402         if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2403                 goto out;
2404         if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2405                 goto out;
2406         r = 0;
2407         vcpu->arch.mcg_cap = mcg_cap;
2408         /* Init IA32_MCG_CTL to all 1s */
2409         if (mcg_cap & MCG_CTL_P)
2410                 vcpu->arch.mcg_ctl = ~(u64)0;
2411         /* Init IA32_MCi_CTL to all 1s */
2412         for (bank = 0; bank < bank_num; bank++)
2413                 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2414 out:
2415         return r;
2416 }
2417
2418 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2419                                       struct kvm_x86_mce *mce)
2420 {
2421         u64 mcg_cap = vcpu->arch.mcg_cap;
2422         unsigned bank_num = mcg_cap & 0xff;
2423         u64 *banks = vcpu->arch.mce_banks;
2424
2425         if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2426                 return -EINVAL;
2427         /*
2428          * if IA32_MCG_CTL is not all 1s, the uncorrected error
2429          * reporting is disabled
2430          */
2431         if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2432             vcpu->arch.mcg_ctl != ~(u64)0)
2433                 return 0;
2434         banks += 4 * mce->bank;
2435         /*
2436          * if IA32_MCi_CTL is not all 1s, the uncorrected error
2437          * reporting is disabled for the bank
2438          */
2439         if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2440                 return 0;
2441         if (mce->status & MCI_STATUS_UC) {
2442                 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2443                     !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2444                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2445                         return 0;
2446                 }
2447                 if (banks[1] & MCI_STATUS_VAL)
2448                         mce->status |= MCI_STATUS_OVER;
2449                 banks[2] = mce->addr;
2450                 banks[3] = mce->misc;
2451                 vcpu->arch.mcg_status = mce->mcg_status;
2452                 banks[1] = mce->status;
2453                 kvm_queue_exception(vcpu, MC_VECTOR);
2454         } else if (!(banks[1] & MCI_STATUS_VAL)
2455                    || !(banks[1] & MCI_STATUS_UC)) {
2456                 if (banks[1] & MCI_STATUS_VAL)
2457                         mce->status |= MCI_STATUS_OVER;
2458                 banks[2] = mce->addr;
2459                 banks[3] = mce->misc;
2460                 banks[1] = mce->status;
2461         } else
2462                 banks[1] |= MCI_STATUS_OVER;
2463         return 0;
2464 }
2465
2466 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2467                                                struct kvm_vcpu_events *events)
2468 {
2469         process_nmi(vcpu);
2470         events->exception.injected =
2471                 vcpu->arch.exception.pending &&
2472                 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2473         events->exception.nr = vcpu->arch.exception.nr;
2474         events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2475         events->exception.pad = 0;
2476         events->exception.error_code = vcpu->arch.exception.error_code;
2477
2478         events->interrupt.injected =
2479                 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2480         events->interrupt.nr = vcpu->arch.interrupt.nr;
2481         events->interrupt.soft = 0;
2482         events->interrupt.shadow =
2483                 kvm_x86_ops->get_interrupt_shadow(vcpu,
2484                         KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2485
2486         events->nmi.injected = vcpu->arch.nmi_injected;
2487         events->nmi.pending = vcpu->arch.nmi_pending != 0;
2488         events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2489         events->nmi.pad = 0;
2490
2491         events->sipi_vector = vcpu->arch.sipi_vector;
2492
2493         events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2494                          | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2495                          | KVM_VCPUEVENT_VALID_SHADOW);
2496         memset(&events->reserved, 0, sizeof(events->reserved));
2497 }
2498
2499 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2500                                               struct kvm_vcpu_events *events)
2501 {
2502         if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2503                               | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2504                               | KVM_VCPUEVENT_VALID_SHADOW))
2505                 return -EINVAL;
2506
2507         process_nmi(vcpu);
2508         vcpu->arch.exception.pending = events->exception.injected;
2509         vcpu->arch.exception.nr = events->exception.nr;
2510         vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2511         vcpu->arch.exception.error_code = events->exception.error_code;
2512
2513         vcpu->arch.interrupt.pending = events->interrupt.injected;
2514         vcpu->arch.interrupt.nr = events->interrupt.nr;
2515         vcpu->arch.interrupt.soft = events->interrupt.soft;
2516         if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2517                 kvm_x86_ops->set_interrupt_shadow(vcpu,
2518                                                   events->interrupt.shadow);
2519
2520         vcpu->arch.nmi_injected = events->nmi.injected;
2521         if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2522                 vcpu->arch.nmi_pending = events->nmi.pending;
2523         kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2524
2525         if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2526                 vcpu->arch.sipi_vector = events->sipi_vector;
2527
2528         kvm_make_request(KVM_REQ_EVENT, vcpu);
2529
2530         return 0;
2531 }
2532
2533 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2534                                              struct kvm_debugregs *dbgregs)
2535 {
2536         memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2537         dbgregs->dr6 = vcpu->arch.dr6;
2538         dbgregs->dr7 = vcpu->arch.dr7;
2539         dbgregs->flags = 0;
2540         memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
2541 }
2542
2543 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2544                                             struct kvm_debugregs *dbgregs)
2545 {
2546         if (dbgregs->flags)
2547                 return -EINVAL;
2548
2549         memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2550         vcpu->arch.dr6 = dbgregs->dr6;
2551         vcpu->arch.dr7 = dbgregs->dr7;
2552
2553         return 0;
2554 }
2555
2556 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2557                                          struct kvm_xsave *guest_xsave)
2558 {
2559         if (cpu_has_xsave)
2560                 memcpy(guest_xsave->region,
2561                         &vcpu->arch.guest_fpu.state->xsave,
2562                         xstate_size);
2563         else {
2564                 memcpy(guest_xsave->region,
2565                         &vcpu->arch.guest_fpu.state->fxsave,
2566                         sizeof(struct i387_fxsave_struct));
2567                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2568                         XSTATE_FPSSE;
2569         }
2570 }
2571
2572 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2573                                         struct kvm_xsave *guest_xsave)
2574 {
2575         u64 xstate_bv =
2576                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2577
2578         if (cpu_has_xsave)
2579                 memcpy(&vcpu->arch.guest_fpu.state->xsave,
2580                         guest_xsave->region, xstate_size);
2581         else {
2582                 if (xstate_bv & ~XSTATE_FPSSE)
2583                         return -EINVAL;
2584                 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2585                         guest_xsave->region, sizeof(struct i387_fxsave_struct));
2586         }
2587         return 0;
2588 }
2589
2590 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2591                                         struct kvm_xcrs *guest_xcrs)
2592 {
2593         if (!cpu_has_xsave) {
2594                 guest_xcrs->nr_xcrs = 0;
2595                 return;
2596         }
2597
2598         guest_xcrs->nr_xcrs = 1;
2599         guest_xcrs->flags = 0;
2600         guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2601         guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2602 }
2603
2604 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2605                                        struct kvm_xcrs *guest_xcrs)
2606 {
2607         int i, r = 0;
2608
2609         if (!cpu_has_xsave)
2610                 return -EINVAL;
2611
2612         if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2613                 return -EINVAL;
2614
2615         for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2616                 /* Only support XCR0 currently */
2617                 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2618                         r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2619                                 guest_xcrs->xcrs[0].value);
2620                         break;
2621                 }
2622         if (r)
2623                 r = -EINVAL;
2624         return r;
2625 }
2626
2627 /*
2628  * kvm_set_guest_paused() indicates to the guest kernel that it has been
2629  * stopped by the hypervisor.  This function will be called from the host only.
2630  * EINVAL is returned when the host attempts to set the flag for a guest that
2631  * does not support pv clocks.
2632  */
2633 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
2634 {
2635         struct pvclock_vcpu_time_info *src = &vcpu->arch.hv_clock;
2636         if (!vcpu->arch.time_page)
2637                 return -EINVAL;
2638         src->flags |= PVCLOCK_GUEST_STOPPED;
2639         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2640         return 0;
2641 }
2642
2643 long kvm_arch_vcpu_ioctl(struct file *filp,
2644                          unsigned int ioctl, unsigned long arg)
2645 {
2646         struct kvm_vcpu *vcpu = filp->private_data;
2647         void __user *argp = (void __user *)arg;
2648         int r;
2649         union {
2650                 struct kvm_lapic_state *lapic;
2651                 struct kvm_xsave *xsave;
2652                 struct kvm_xcrs *xcrs;
2653                 void *buffer;
2654         } u;
2655
2656         u.buffer = NULL;
2657         switch (ioctl) {
2658         case KVM_GET_LAPIC: {
2659                 r = -EINVAL;
2660                 if (!vcpu->arch.apic)
2661                         goto out;
2662                 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2663
2664                 r = -ENOMEM;
2665                 if (!u.lapic)
2666                         goto out;
2667                 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
2668                 if (r)
2669                         goto out;
2670                 r = -EFAULT;
2671                 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
2672                         goto out;
2673                 r = 0;
2674                 break;
2675         }
2676         case KVM_SET_LAPIC: {
2677                 r = -EINVAL;
2678                 if (!vcpu->arch.apic)
2679                         goto out;
2680                 u.lapic = memdup_user(argp, sizeof(*u.lapic));
2681                 if (IS_ERR(u.lapic)) {
2682                         r = PTR_ERR(u.lapic);
2683                         goto out;
2684                 }
2685
2686                 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
2687                 if (r)
2688                         goto out;
2689                 r = 0;
2690                 break;
2691         }
2692         case KVM_INTERRUPT: {
2693                 struct kvm_interrupt irq;
2694
2695                 r = -EFAULT;
2696                 if (copy_from_user(&irq, argp, sizeof irq))
2697                         goto out;
2698                 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2699                 if (r)
2700                         goto out;
2701                 r = 0;
2702                 break;
2703         }
2704         case KVM_NMI: {
2705                 r = kvm_vcpu_ioctl_nmi(vcpu);
2706                 if (r)
2707                         goto out;
2708                 r = 0;
2709                 break;
2710         }
2711         case KVM_SET_CPUID: {
2712                 struct kvm_cpuid __user *cpuid_arg = argp;
2713                 struct kvm_cpuid cpuid;
2714
2715                 r = -EFAULT;
2716                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2717                         goto out;
2718                 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2719                 if (r)
2720                         goto out;
2721                 break;
2722         }
2723         case KVM_SET_CPUID2: {
2724                 struct kvm_cpuid2 __user *cpuid_arg = argp;
2725                 struct kvm_cpuid2 cpuid;
2726
2727                 r = -EFAULT;
2728                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2729                         goto out;
2730                 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
2731                                               cpuid_arg->entries);
2732                 if (r)
2733                         goto out;
2734                 break;
2735         }
2736         case KVM_GET_CPUID2: {
2737                 struct kvm_cpuid2 __user *cpuid_arg = argp;
2738                 struct kvm_cpuid2 cpuid;
2739
2740                 r = -EFAULT;
2741                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2742                         goto out;
2743                 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
2744                                               cpuid_arg->entries);
2745                 if (r)
2746                         goto out;
2747                 r = -EFAULT;
2748                 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2749                         goto out;
2750                 r = 0;
2751                 break;
2752         }
2753         case KVM_GET_MSRS:
2754                 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2755                 break;
2756         case KVM_SET_MSRS:
2757                 r = msr_io(vcpu, argp, do_set_msr, 0);
2758                 break;
2759         case KVM_TPR_ACCESS_REPORTING: {
2760                 struct kvm_tpr_access_ctl tac;
2761
2762                 r = -EFAULT;
2763                 if (copy_from_user(&tac, argp, sizeof tac))
2764                         goto out;
2765                 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2766                 if (r)
2767                         goto out;
2768                 r = -EFAULT;
2769                 if (copy_to_user(argp, &tac, sizeof tac))
2770                         goto out;
2771                 r = 0;
2772                 break;
2773         };
2774         case KVM_SET_VAPIC_ADDR: {
2775                 struct kvm_vapic_addr va;
2776
2777                 r = -EINVAL;
2778                 if (!irqchip_in_kernel(vcpu->kvm))
2779                         goto out;
2780                 r = -EFAULT;
2781                 if (copy_from_user(&va, argp, sizeof va))
2782                         goto out;
2783                 r = 0;
2784                 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2785                 break;
2786         }
2787         case KVM_X86_SETUP_MCE: {
2788                 u64 mcg_cap;
2789
2790                 r = -EFAULT;
2791                 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2792                         goto out;
2793                 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2794                 break;
2795         }
2796         case KVM_X86_SET_MCE: {
2797                 struct kvm_x86_mce mce;
2798
2799                 r = -EFAULT;
2800                 if (copy_from_user(&mce, argp, sizeof mce))
2801                         goto out;
2802                 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2803                 break;
2804         }
2805         case KVM_GET_VCPU_EVENTS: {
2806                 struct kvm_vcpu_events events;
2807
2808                 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2809
2810                 r = -EFAULT;
2811                 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2812                         break;
2813                 r = 0;
2814                 break;
2815         }
2816         case KVM_SET_VCPU_EVENTS: {
2817                 struct kvm_vcpu_events events;
2818
2819                 r = -EFAULT;
2820                 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2821                         break;
2822
2823                 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2824                 break;
2825         }
2826         case KVM_GET_DEBUGREGS: {
2827                 struct kvm_debugregs dbgregs;
2828
2829                 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2830
2831                 r = -EFAULT;
2832                 if (copy_to_user(argp, &dbgregs,
2833                                  sizeof(struct kvm_debugregs)))
2834                         break;
2835                 r = 0;
2836                 break;
2837         }
2838         case KVM_SET_DEBUGREGS: {
2839                 struct kvm_debugregs dbgregs;
2840
2841                 r = -EFAULT;
2842                 if (copy_from_user(&dbgregs, argp,
2843                                    sizeof(struct kvm_debugregs)))
2844                         break;
2845
2846                 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2847                 break;
2848         }
2849         case KVM_GET_XSAVE: {
2850                 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2851                 r = -ENOMEM;
2852                 if (!u.xsave)
2853                         break;
2854
2855                 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2856
2857                 r = -EFAULT;
2858                 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2859                         break;
2860                 r = 0;
2861                 break;
2862         }
2863         case KVM_SET_XSAVE: {
2864                 u.xsave = memdup_user(argp, sizeof(*u.xsave));
2865                 if (IS_ERR(u.xsave)) {
2866                         r = PTR_ERR(u.xsave);
2867                         goto out;
2868                 }
2869
2870                 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2871                 break;
2872         }
2873         case KVM_GET_XCRS: {
2874                 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2875                 r = -ENOMEM;
2876                 if (!u.xcrs)
2877                         break;
2878
2879                 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2880
2881                 r = -EFAULT;
2882                 if (copy_to_user(argp, u.xcrs,
2883                                  sizeof(struct kvm_xcrs)))
2884                         break;
2885                 r = 0;
2886                 break;
2887         }
2888         case KVM_SET_XCRS: {
2889                 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
2890                 if (IS_ERR(u.xcrs)) {
2891                         r = PTR_ERR(u.xcrs);
2892                         goto out;
2893                 }
2894
2895                 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2896                 break;
2897         }
2898         case KVM_SET_TSC_KHZ: {
2899                 u32 user_tsc_khz;
2900
2901                 r = -EINVAL;
2902                 user_tsc_khz = (u32)arg;
2903
2904                 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
2905                         goto out;
2906
2907                 if (user_tsc_khz == 0)
2908                         user_tsc_khz = tsc_khz;
2909
2910                 kvm_set_tsc_khz(vcpu, user_tsc_khz);
2911
2912                 r = 0;
2913                 goto out;
2914         }
2915         case KVM_GET_TSC_KHZ: {
2916                 r = vcpu->arch.virtual_tsc_khz;
2917                 goto out;
2918         }
2919         case KVM_KVMCLOCK_CTRL: {
2920                 r = kvm_set_guest_paused(vcpu);
2921                 goto out;
2922         }
2923         default:
2924                 r = -EINVAL;
2925         }
2926 out:
2927         kfree(u.buffer);
2928         return r;
2929 }
2930
2931 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
2932 {
2933         return VM_FAULT_SIGBUS;
2934 }
2935
2936 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2937 {
2938         int ret;
2939
2940         if (addr > (unsigned int)(-3 * PAGE_SIZE))
2941                 return -1;
2942         ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2943         return ret;
2944 }
2945
2946 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2947                                               u64 ident_addr)
2948 {
2949         kvm->arch.ept_identity_map_addr = ident_addr;
2950         return 0;
2951 }
2952
2953 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2954                                           u32 kvm_nr_mmu_pages)
2955 {
2956         if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2957                 return -EINVAL;
2958
2959         mutex_lock(&kvm->slots_lock);
2960         spin_lock(&kvm->mmu_lock);
2961
2962         kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
2963         kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
2964
2965         spin_unlock(&kvm->mmu_lock);
2966         mutex_unlock(&kvm->slots_lock);
2967         return 0;
2968 }
2969
2970 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2971 {
2972         return kvm->arch.n_max_mmu_pages;
2973 }
2974
2975 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2976 {
2977         int r;
2978
2979         r = 0;
2980         switch (chip->chip_id) {
2981         case KVM_IRQCHIP_PIC_MASTER:
2982                 memcpy(&chip->chip.pic,
2983                         &pic_irqchip(kvm)->pics[0],
2984                         sizeof(struct kvm_pic_state));
2985                 break;
2986         case KVM_IRQCHIP_PIC_SLAVE:
2987                 memcpy(&chip->chip.pic,
2988                         &pic_irqchip(kvm)->pics[1],
2989                         sizeof(struct kvm_pic_state));
2990                 break;
2991         case KVM_IRQCHIP_IOAPIC:
2992                 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
2993                 break;
2994         default:
2995                 r = -EINVAL;
2996                 break;
2997         }
2998         return r;
2999 }
3000
3001 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3002 {
3003         int r;
3004
3005         r = 0;
3006         switch (chip->chip_id) {
3007         case KVM_IRQCHIP_PIC_MASTER:
3008                 spin_lock(&pic_irqchip(kvm)->lock);
3009                 memcpy(&pic_irqchip(kvm)->pics[0],
3010                         &chip->chip.pic,
3011                         sizeof(struct kvm_pic_state));
3012                 spin_unlock(&pic_irqchip(kvm)->lock);
3013                 break;
3014         case KVM_IRQCHIP_PIC_SLAVE:
3015                 spin_lock(&pic_irqchip(kvm)->lock);
3016                 memcpy(&pic_irqchip(kvm)->pics[1],
3017                         &chip->chip.pic,
3018                         sizeof(struct kvm_pic_state));
3019                 spin_unlock(&pic_irqchip(kvm)->lock);
3020                 break;
3021         case KVM_IRQCHIP_IOAPIC:
3022                 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3023                 break;
3024         default:
3025                 r = -EINVAL;
3026                 break;
3027         }
3028         kvm_pic_update_irq(pic_irqchip(kvm));
3029         return r;
3030 }
3031
3032 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3033 {
3034         int r = 0;
3035
3036         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3037         memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3038         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3039         return r;
3040 }
3041
3042 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3043 {
3044         int r = 0;
3045
3046         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3047         memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3048         kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3049         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3050         return r;
3051 }
3052
3053 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3054 {
3055         int r = 0;
3056
3057         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3058         memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3059                 sizeof(ps->channels));
3060         ps->flags = kvm->arch.vpit->pit_state.flags;
3061         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3062         memset(&ps->reserved, 0, sizeof(ps->reserved));
3063         return r;
3064 }
3065
3066 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3067 {
3068         int r = 0, start = 0;
3069         u32 prev_legacy, cur_legacy;
3070         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3071         prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3072         cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3073         if (!prev_legacy && cur_legacy)
3074                 start = 1;
3075         memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3076                sizeof(kvm->arch.vpit->pit_state.channels));
3077         kvm->arch.vpit->pit_state.flags = ps->flags;
3078         kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3079         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3080         return r;
3081 }
3082
3083 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3084                                  struct kvm_reinject_control *control)
3085 {
3086         if (!kvm->arch.vpit)
3087                 return -ENXIO;
3088         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3089         kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3090         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3091         return 0;
3092 }
3093
3094 /**
3095  * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3096  * @kvm: kvm instance
3097  * @log: slot id and address to which we copy the log
3098  *
3099  * We need to keep it in mind that VCPU threads can write to the bitmap
3100  * concurrently.  So, to avoid losing data, we keep the following order for
3101  * each bit:
3102  *
3103  *   1. Take a snapshot of the bit and clear it if needed.
3104  *   2. Write protect the corresponding page.
3105  *   3. Flush TLB's if needed.
3106  *   4. Copy the snapshot to the userspace.
3107  *
3108  * Between 2 and 3, the guest may write to the page using the remaining TLB
3109  * entry.  This is not a problem because the page will be reported dirty at
3110  * step 4 using the snapshot taken before and step 3 ensures that successive
3111  * writes will be logged for the next call.
3112  */
3113 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3114 {
3115         int r;
3116         struct kvm_memory_slot *memslot;
3117         unsigned long n, i;
3118         unsigned long *dirty_bitmap;
3119         unsigned long *dirty_bitmap_buffer;
3120         bool is_dirty = false;
3121
3122         mutex_lock(&kvm->slots_lock);
3123
3124         r = -EINVAL;
3125         if (log->slot >= KVM_MEMORY_SLOTS)
3126                 goto out;
3127
3128         memslot = id_to_memslot(kvm->memslots, log->slot);
3129
3130         dirty_bitmap = memslot->dirty_bitmap;
3131         r = -ENOENT;
3132         if (!dirty_bitmap)
3133                 goto out;
3134
3135         n = kvm_dirty_bitmap_bytes(memslot);
3136
3137         dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3138         memset(dirty_bitmap_buffer, 0, n);
3139
3140         spin_lock(&kvm->mmu_lock);
3141
3142         for (i = 0; i < n / sizeof(long); i++) {
3143                 unsigned long mask;
3144                 gfn_t offset;
3145
3146                 if (!dirty_bitmap[i])
3147                         continue;
3148
3149                 is_dirty = true;
3150
3151                 mask = xchg(&dirty_bitmap[i], 0);
3152                 dirty_bitmap_buffer[i] = mask;
3153
3154                 offset = i * BITS_PER_LONG;
3155                 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
3156         }
3157         if (is_dirty)
3158                 kvm_flush_remote_tlbs(kvm);
3159
3160         spin_unlock(&kvm->mmu_lock);
3161
3162         r = -EFAULT;
3163         if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3164                 goto out;
3165
3166         r = 0;
3167 out:
3168         mutex_unlock(&kvm->slots_lock);
3169         return r;
3170 }
3171
3172 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event)
3173 {
3174         if (!irqchip_in_kernel(kvm))
3175                 return -ENXIO;
3176
3177         irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3178                                         irq_event->irq, irq_event->level);
3179         return 0;
3180 }
3181
3182 long kvm_arch_vm_ioctl(struct file *filp,
3183                        unsigned int ioctl, unsigned long arg)
3184 {
3185         struct kvm *kvm = filp->private_data;
3186         void __user *argp = (void __user *)arg;
3187         int r = -ENOTTY;
3188         /*
3189          * This union makes it completely explicit to gcc-3.x
3190          * that these two variables' stack usage should be
3191          * combined, not added together.
3192          */
3193         union {
3194                 struct kvm_pit_state ps;
3195                 struct kvm_pit_state2 ps2;
3196                 struct kvm_pit_config pit_config;
3197         } u;
3198
3199         switch (ioctl) {
3200         case KVM_SET_TSS_ADDR:
3201                 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3202                 if (r < 0)
3203                         goto out;
3204                 break;
3205         case KVM_SET_IDENTITY_MAP_ADDR: {
3206                 u64 ident_addr;
3207
3208                 r = -EFAULT;
3209                 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3210                         goto out;
3211                 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3212                 if (r < 0)
3213                         goto out;
3214                 break;
3215         }
3216         case KVM_SET_NR_MMU_PAGES:
3217                 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3218                 if (r)
3219                         goto out;
3220                 break;
3221         case KVM_GET_NR_MMU_PAGES:
3222                 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3223                 break;
3224         case KVM_CREATE_IRQCHIP: {
3225                 struct kvm_pic *vpic;
3226
3227                 mutex_lock(&kvm->lock);
3228                 r = -EEXIST;
3229                 if (kvm->arch.vpic)
3230                         goto create_irqchip_unlock;
3231                 r = -EINVAL;
3232                 if (atomic_read(&kvm->online_vcpus))
3233                         goto create_irqchip_unlock;
3234                 r = -ENOMEM;
3235                 vpic = kvm_create_pic(kvm);
3236                 if (vpic) {
3237                         r = kvm_ioapic_init(kvm);
3238                         if (r) {
3239                                 mutex_lock(&kvm->slots_lock);
3240                                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3241                                                           &vpic->dev_master);
3242                                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3243                                                           &vpic->dev_slave);
3244                                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3245                                                           &vpic->dev_eclr);
3246                                 mutex_unlock(&kvm->slots_lock);
3247                                 kfree(vpic);
3248                                 goto create_irqchip_unlock;
3249                         }
3250                 } else
3251                         goto create_irqchip_unlock;
3252                 smp_wmb();
3253                 kvm->arch.vpic = vpic;
3254                 smp_wmb();
3255                 r = kvm_setup_default_irq_routing(kvm);
3256                 if (r) {
3257                         mutex_lock(&kvm->slots_lock);
3258                         mutex_lock(&kvm->irq_lock);
3259                         kvm_ioapic_destroy(kvm);
3260                         kvm_destroy_pic(kvm);
3261                         mutex_unlock(&kvm->irq_lock);
3262                         mutex_unlock(&kvm->slots_lock);
3263                 }
3264         create_irqchip_unlock:
3265                 mutex_unlock(&kvm->lock);
3266                 break;
3267         }
3268         case KVM_CREATE_PIT:
3269                 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3270                 goto create_pit;
3271         case KVM_CREATE_PIT2:
3272                 r = -EFAULT;
3273                 if (copy_from_user(&u.pit_config, argp,
3274                                    sizeof(struct kvm_pit_config)))
3275                         goto out;
3276         create_pit:
3277                 mutex_lock(&kvm->slots_lock);
3278                 r = -EEXIST;
3279                 if (kvm->arch.vpit)
3280                         goto create_pit_unlock;
3281                 r = -ENOMEM;
3282                 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3283                 if (kvm->arch.vpit)
3284                         r = 0;
3285         create_pit_unlock:
3286                 mutex_unlock(&kvm->slots_lock);
3287                 break;
3288         case KVM_GET_IRQCHIP: {
3289                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3290                 struct kvm_irqchip *chip;
3291
3292                 chip = memdup_user(argp, sizeof(*chip));
3293                 if (IS_ERR(chip)) {
3294                         r = PTR_ERR(chip);
3295                         goto out;
3296                 }
3297
3298                 r = -ENXIO;
3299                 if (!irqchip_in_kernel(kvm))
3300                         goto get_irqchip_out;
3301                 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3302                 if (r)
3303                         goto get_irqchip_out;
3304                 r = -EFAULT;
3305                 if (copy_to_user(argp, chip, sizeof *chip))
3306                         goto get_irqchip_out;
3307                 r = 0;
3308         get_irqchip_out:
3309                 kfree(chip);
3310                 if (r)
3311                         goto out;
3312                 break;
3313         }
3314         case KVM_SET_IRQCHIP: {
3315                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3316                 struct kvm_irqchip *chip;
3317
3318                 chip = memdup_user(argp, sizeof(*chip));
3319                 if (IS_ERR(chip)) {
3320                         r = PTR_ERR(chip);
3321                         goto out;
3322                 }
3323
3324                 r = -ENXIO;
3325                 if (!irqchip_in_kernel(kvm))
3326                         goto set_irqchip_out;
3327                 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3328                 if (r)
3329                         goto set_irqchip_out;
3330                 r = 0;
3331         set_irqchip_out:
3332                 kfree(chip);
3333                 if (r)
3334                         goto out;
3335                 break;
3336         }
3337         case KVM_GET_PIT: {
3338                 r = -EFAULT;
3339                 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3340                         goto out;
3341                 r = -ENXIO;
3342                 if (!kvm->arch.vpit)
3343                         goto out;
3344                 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3345                 if (r)
3346                         goto out;
3347                 r = -EFAULT;
3348                 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3349                         goto out;
3350                 r = 0;
3351                 break;
3352         }
3353         case KVM_SET_PIT: {
3354                 r = -EFAULT;
3355                 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3356                         goto out;
3357                 r = -ENXIO;
3358                 if (!kvm->arch.vpit)
3359                         goto out;
3360                 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3361                 if (r)
3362                         goto out;
3363                 r = 0;
3364                 break;
3365         }
3366         case KVM_GET_PIT2: {
3367                 r = -ENXIO;
3368                 if (!kvm->arch.vpit)
3369                         goto out;
3370                 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3371                 if (r)
3372                         goto out;
3373                 r = -EFAULT;
3374                 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3375                         goto out;
3376                 r = 0;
3377                 break;
3378         }
3379         case KVM_SET_PIT2: {
3380                 r = -EFAULT;
3381                 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3382                         goto out;
3383                 r = -ENXIO;
3384                 if (!kvm->arch.vpit)
3385                         goto out;
3386                 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3387                 if (r)
3388                         goto out;
3389                 r = 0;
3390                 break;
3391         }
3392         case KVM_REINJECT_CONTROL: {
3393                 struct kvm_reinject_control control;
3394                 r =  -EFAULT;
3395                 if (copy_from_user(&control, argp, sizeof(control)))
3396                         goto out;
3397                 r = kvm_vm_ioctl_reinject(kvm, &control);
3398                 if (r)
3399                         goto out;
3400                 r = 0;
3401                 break;
3402         }
3403         case KVM_XEN_HVM_CONFIG: {
3404                 r = -EFAULT;
3405                 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3406                                    sizeof(struct kvm_xen_hvm_config)))
3407                         goto out;
3408                 r = -EINVAL;
3409                 if (kvm->arch.xen_hvm_config.flags)
3410                         goto out;
3411                 r = 0;
3412                 break;
3413         }
3414         case KVM_SET_CLOCK: {
3415                 struct kvm_clock_data user_ns;
3416                 u64 now_ns;
3417                 s64 delta;
3418
3419                 r = -EFAULT;
3420                 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3421                         goto out;
3422
3423                 r = -EINVAL;
3424                 if (user_ns.flags)
3425                         goto out;
3426
3427                 r = 0;
3428                 local_irq_disable();
3429                 now_ns = get_kernel_ns();
3430                 delta = user_ns.clock - now_ns;
3431                 local_irq_enable();
3432                 kvm->arch.kvmclock_offset = delta;
3433                 break;
3434         }
3435         case KVM_GET_CLOCK: {
3436                 struct kvm_clock_data user_ns;
3437                 u64 now_ns;
3438
3439                 local_irq_disable();
3440                 now_ns = get_kernel_ns();
3441                 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3442                 local_irq_enable();
3443                 user_ns.flags = 0;
3444                 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3445
3446                 r = -EFAULT;
3447                 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3448                         goto out;
3449                 r = 0;
3450                 break;
3451         }
3452
3453         default:
3454                 ;
3455         }
3456 out:
3457         return r;
3458 }
3459
3460 static void kvm_init_msr_list(void)
3461 {
3462         u32 dummy[2];
3463         unsigned i, j;
3464
3465         /* skip the first msrs in the list. KVM-specific */
3466         for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3467                 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3468                         continue;
3469                 if (j < i)
3470                         msrs_to_save[j] = msrs_to_save[i];
3471                 j++;
3472         }
3473         num_msrs_to_save = j;
3474 }
3475
3476 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3477                            const void *v)
3478 {
3479         int handled = 0;
3480         int n;
3481
3482         do {
3483                 n = min(len, 8);
3484                 if (!(vcpu->arch.apic &&
3485                       !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3486                     && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3487                         break;
3488                 handled += n;
3489                 addr += n;
3490                 len -= n;
3491                 v += n;
3492         } while (len);
3493
3494         return handled;
3495 }
3496
3497 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3498 {
3499         int handled = 0;
3500         int n;
3501
3502         do {
3503                 n = min(len, 8);
3504                 if (!(vcpu->arch.apic &&
3505                       !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3506                     && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3507                         break;
3508                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3509                 handled += n;
3510                 addr += n;
3511                 len -= n;
3512                 v += n;
3513         } while (len);
3514
3515         return handled;
3516 }
3517
3518 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3519                         struct kvm_segment *var, int seg)
3520 {
3521         kvm_x86_ops->set_segment(vcpu, var, seg);
3522 }
3523
3524 void kvm_get_segment(struct kvm_vcpu *vcpu,
3525                      struct kvm_segment *var, int seg)
3526 {
3527         kvm_x86_ops->get_segment(vcpu, var, seg);
3528 }
3529
3530 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3531 {
3532         gpa_t t_gpa;
3533         struct x86_exception exception;
3534
3535         BUG_ON(!mmu_is_nested(vcpu));
3536
3537         /* NPT walks are always user-walks */
3538         access |= PFERR_USER_MASK;
3539         t_gpa  = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
3540
3541         return t_gpa;
3542 }
3543
3544 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3545                               struct x86_exception *exception)
3546 {
3547         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3548         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3549 }
3550
3551  gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3552                                 struct x86_exception *exception)
3553 {
3554         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3555         access |= PFERR_FETCH_MASK;
3556         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3557 }
3558
3559 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3560                                struct x86_exception *exception)
3561 {
3562         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3563         access |= PFERR_WRITE_MASK;
3564         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3565 }
3566
3567 /* uses this to access any guest's mapped memory without checking CPL */
3568 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3569                                 struct x86_exception *exception)
3570 {
3571         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
3572 }
3573
3574 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3575                                       struct kvm_vcpu *vcpu, u32 access,
3576                                       struct x86_exception *exception)
3577 {
3578         void *data = val;
3579         int r = X86EMUL_CONTINUE;
3580
3581         while (bytes) {
3582                 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3583                                                             exception);
3584                 unsigned offset = addr & (PAGE_SIZE-1);
3585                 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
3586                 int ret;
3587
3588                 if (gpa == UNMAPPED_GVA)
3589                         return X86EMUL_PROPAGATE_FAULT;
3590                 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
3591                 if (ret < 0) {
3592                         r = X86EMUL_IO_NEEDED;
3593                         goto out;
3594                 }
3595
3596                 bytes -= toread;
3597                 data += toread;
3598                 addr += toread;
3599         }
3600 out:
3601         return r;
3602 }
3603
3604 /* used for instruction fetching */
3605 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3606                                 gva_t addr, void *val, unsigned int bytes,
3607                                 struct x86_exception *exception)
3608 {
3609         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3610         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3611
3612         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3613                                           access | PFERR_FETCH_MASK,
3614                                           exception);
3615 }
3616
3617 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
3618                                gva_t addr, void *val, unsigned int bytes,
3619                                struct x86_exception *exception)
3620 {
3621         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3622         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3623
3624         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3625                                           exception);
3626 }
3627 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
3628
3629 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3630                                       gva_t addr, void *val, unsigned int bytes,
3631                                       struct x86_exception *exception)
3632 {
3633         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3634         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
3635 }
3636
3637 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3638                                        gva_t addr, void *val,
3639                                        unsigned int bytes,
3640                                        struct x86_exception *exception)
3641 {
3642         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3643         void *data = val;
3644         int r = X86EMUL_CONTINUE;
3645
3646         while (bytes) {
3647                 gpa_t gpa =  vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3648                                                              PFERR_WRITE_MASK,
3649                                                              exception);
3650                 unsigned offset = addr & (PAGE_SIZE-1);
3651                 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3652                 int ret;
3653
3654                 if (gpa == UNMAPPED_GVA)
3655                         return X86EMUL_PROPAGATE_FAULT;
3656                 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3657                 if (ret < 0) {
3658                         r = X86EMUL_IO_NEEDED;
3659                         goto out;
3660                 }
3661
3662                 bytes -= towrite;
3663                 data += towrite;
3664                 addr += towrite;
3665         }
3666 out:
3667         return r;
3668 }
3669 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
3670
3671 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3672                                 gpa_t *gpa, struct x86_exception *exception,
3673                                 bool write)
3674 {
3675         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3676
3677         if (vcpu_match_mmio_gva(vcpu, gva) &&
3678                   check_write_user_access(vcpu, write, access,
3679                   vcpu->arch.access)) {
3680                 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3681                                         (gva & (PAGE_SIZE - 1));
3682                 trace_vcpu_match_mmio(gva, *gpa, write, false);
3683                 return 1;
3684         }
3685
3686         if (write)
3687                 access |= PFERR_WRITE_MASK;
3688
3689         *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3690
3691         if (*gpa == UNMAPPED_GVA)
3692                 return -1;
3693
3694         /* For APIC access vmexit */
3695         if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3696                 return 1;
3697
3698         if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
3699                 trace_vcpu_match_mmio(gva, *gpa, write, true);
3700                 return 1;
3701         }
3702
3703         return 0;
3704 }
3705
3706 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
3707                         const void *val, int bytes)
3708 {
3709         int ret;
3710
3711         ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
3712         if (ret < 0)
3713                 return 0;
3714         kvm_mmu_pte_write(vcpu, gpa, val, bytes);
3715         return 1;
3716 }
3717
3718 struct read_write_emulator_ops {
3719         int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
3720                                   int bytes);
3721         int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
3722                                   void *val, int bytes);
3723         int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3724                                int bytes, void *val);
3725         int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3726                                     void *val, int bytes);
3727         bool write;
3728 };
3729
3730 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
3731 {
3732         if (vcpu->mmio_read_completed) {
3733                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3734                                vcpu->mmio_fragments[0].gpa, *(u64 *)val);
3735                 vcpu->mmio_read_completed = 0;
3736                 return 1;
3737         }
3738
3739         return 0;
3740 }
3741
3742 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3743                         void *val, int bytes)
3744 {
3745         return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
3746 }
3747
3748 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3749                          void *val, int bytes)
3750 {
3751         return emulator_write_phys(vcpu, gpa, val, bytes);
3752 }
3753
3754 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
3755 {
3756         trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
3757         return vcpu_mmio_write(vcpu, gpa, bytes, val);
3758 }
3759
3760 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3761                           void *val, int bytes)
3762 {
3763         trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
3764         return X86EMUL_IO_NEEDED;
3765 }
3766
3767 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3768                            void *val, int bytes)
3769 {
3770         struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
3771
3772         memcpy(vcpu->run->mmio.data, frag->data, frag->len);
3773         return X86EMUL_CONTINUE;
3774 }
3775
3776 static struct read_write_emulator_ops read_emultor = {
3777         .read_write_prepare = read_prepare,
3778         .read_write_emulate = read_emulate,
3779         .read_write_mmio = vcpu_mmio_read,
3780         .read_write_exit_mmio = read_exit_mmio,
3781 };
3782
3783 static struct read_write_emulator_ops write_emultor = {
3784         .read_write_emulate = write_emulate,
3785         .read_write_mmio = write_mmio,
3786         .read_write_exit_mmio = write_exit_mmio,
3787         .write = true,
3788 };
3789
3790 static int emulator_read_write_onepage(unsigned long addr, void *val,
3791                                        unsigned int bytes,
3792                                        struct x86_exception *exception,
3793                                        struct kvm_vcpu *vcpu,
3794                                        struct read_write_emulator_ops *ops)
3795 {
3796         gpa_t gpa;
3797         int handled, ret;
3798         bool write = ops->write;
3799         struct kvm_mmio_fragment *frag;
3800
3801         ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
3802
3803         if (ret < 0)
3804                 return X86EMUL_PROPAGATE_FAULT;
3805
3806         /* For APIC access vmexit */
3807         if (ret)
3808                 goto mmio;
3809
3810         if (ops->read_write_emulate(vcpu, gpa, val, bytes))
3811                 return X86EMUL_CONTINUE;
3812
3813 mmio:
3814         /*
3815          * Is this MMIO handled locally?
3816          */
3817         handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
3818         if (handled == bytes)
3819                 return X86EMUL_CONTINUE;
3820
3821         gpa += handled;
3822         bytes -= handled;
3823         val += handled;
3824
3825         while (bytes) {
3826                 unsigned now = min(bytes, 8U);
3827
3828                 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
3829                 frag->gpa = gpa;
3830                 frag->data = val;
3831                 frag->len = now;
3832
3833                 gpa += now;
3834                 val += now;
3835                 bytes -= now;
3836         }
3837         return X86EMUL_CONTINUE;
3838 }
3839
3840 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
3841                         void *val, unsigned int bytes,
3842                         struct x86_exception *exception,
3843                         struct read_write_emulator_ops *ops)
3844 {
3845         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3846         gpa_t gpa;
3847         int rc;
3848
3849         if (ops->read_write_prepare &&
3850                   ops->read_write_prepare(vcpu, val, bytes))
3851                 return X86EMUL_CONTINUE;
3852
3853         vcpu->mmio_nr_fragments = 0;
3854
3855         /* Crossing a page boundary? */
3856         if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3857                 int now;
3858
3859                 now = -addr & ~PAGE_MASK;
3860                 rc = emulator_read_write_onepage(addr, val, now, exception,
3861                                                  vcpu, ops);
3862
3863                 if (rc != X86EMUL_CONTINUE)
3864                         return rc;
3865                 addr += now;
3866                 val += now;
3867                 bytes -= now;
3868         }
3869
3870         rc = emulator_read_write_onepage(addr, val, bytes, exception,
3871                                          vcpu, ops);
3872         if (rc != X86EMUL_CONTINUE)
3873                 return rc;
3874
3875         if (!vcpu->mmio_nr_fragments)
3876                 return rc;
3877
3878         gpa = vcpu->mmio_fragments[0].gpa;
3879
3880         vcpu->mmio_needed = 1;
3881         vcpu->mmio_cur_fragment = 0;
3882
3883         vcpu->run->mmio.len = vcpu->mmio_fragments[0].len;
3884         vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
3885         vcpu->run->exit_reason = KVM_EXIT_MMIO;
3886         vcpu->run->mmio.phys_addr = gpa;
3887
3888         return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
3889 }
3890
3891 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
3892                                   unsigned long addr,
3893                                   void *val,
3894                                   unsigned int bytes,
3895                                   struct x86_exception *exception)
3896 {
3897         return emulator_read_write(ctxt, addr, val, bytes,
3898                                    exception, &read_emultor);
3899 }
3900
3901 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
3902                             unsigned long addr,
3903                             const void *val,
3904                             unsigned int bytes,
3905                             struct x86_exception *exception)
3906 {
3907         return emulator_read_write(ctxt, addr, (void *)val, bytes,
3908                                    exception, &write_emultor);
3909 }
3910
3911 #define CMPXCHG_TYPE(t, ptr, old, new) \
3912         (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3913
3914 #ifdef CONFIG_X86_64
3915 #  define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3916 #else
3917 #  define CMPXCHG64(ptr, old, new) \
3918         (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
3919 #endif
3920
3921 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
3922                                      unsigned long addr,
3923                                      const void *old,
3924                                      const void *new,
3925                                      unsigned int bytes,
3926                                      struct x86_exception *exception)
3927 {
3928         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3929         gpa_t gpa;
3930         struct page *page;
3931         char *kaddr;
3932         bool exchanged;
3933
3934         /* guests cmpxchg8b have to be emulated atomically */
3935         if (bytes > 8 || (bytes & (bytes - 1)))
3936                 goto emul_write;
3937
3938         gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
3939
3940         if (gpa == UNMAPPED_GVA ||
3941             (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3942                 goto emul_write;
3943
3944         if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3945                 goto emul_write;
3946
3947         page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
3948         if (is_error_page(page)) {
3949                 kvm_release_page_clean(page);
3950                 goto emul_write;
3951         }
3952
3953         kaddr = kmap_atomic(page);
3954         kaddr += offset_in_page(gpa);
3955         switch (bytes) {
3956         case 1:
3957                 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3958                 break;
3959         case 2:
3960                 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3961                 break;
3962         case 4:
3963                 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3964                 break;
3965         case 8:
3966                 exchanged = CMPXCHG64(kaddr, old, new);
3967                 break;
3968         default:
3969                 BUG();
3970         }
3971         kunmap_atomic(kaddr);
3972         kvm_release_page_dirty(page);
3973
3974         if (!exchanged)
3975                 return X86EMUL_CMPXCHG_FAILED;
3976
3977         kvm_mmu_pte_write(vcpu, gpa, new, bytes);
3978
3979         return X86EMUL_CONTINUE;
3980
3981 emul_write:
3982         printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
3983
3984         return emulator_write_emulated(ctxt, addr, new, bytes, exception);
3985 }
3986
3987 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3988 {
3989         /* TODO: String I/O for in kernel device */
3990         int r;
3991
3992         if (vcpu->arch.pio.in)
3993                 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3994                                     vcpu->arch.pio.size, pd);
3995         else
3996                 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3997                                      vcpu->arch.pio.port, vcpu->arch.pio.size,
3998                                      pd);
3999         return r;
4000 }
4001
4002 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4003                                unsigned short port, void *val,
4004                                unsigned int count, bool in)
4005 {
4006         trace_kvm_pio(!in, port, size, count);
4007
4008         vcpu->arch.pio.port = port;
4009         vcpu->arch.pio.in = in;
4010         vcpu->arch.pio.count  = count;
4011         vcpu->arch.pio.size = size;
4012
4013         if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4014                 vcpu->arch.pio.count = 0;
4015                 return 1;
4016         }
4017
4018         vcpu->run->exit_reason = KVM_EXIT_IO;
4019         vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4020         vcpu->run->io.size = size;
4021         vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4022         vcpu->run->io.count = count;
4023         vcpu->run->io.port = port;
4024
4025         return 0;
4026 }
4027
4028 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4029                                     int size, unsigned short port, void *val,
4030                                     unsigned int count)
4031 {
4032         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4033         int ret;
4034
4035         if (vcpu->arch.pio.count)
4036                 goto data_avail;
4037
4038         ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4039         if (ret) {
4040 data_avail:
4041                 memcpy(val, vcpu->arch.pio_data, size * count);
4042                 vcpu->arch.pio.count = 0;
4043                 return 1;
4044         }
4045
4046         return 0;
4047 }
4048
4049 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4050                                      int size, unsigned short port,
4051                                      const void *val, unsigned int count)
4052 {
4053         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4054
4055         memcpy(vcpu->arch.pio_data, val, size * count);
4056         return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4057 }
4058
4059 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4060 {
4061         return kvm_x86_ops->get_segment_base(vcpu, seg);
4062 }
4063
4064 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4065 {
4066         kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4067 }
4068
4069 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4070 {
4071         if (!need_emulate_wbinvd(vcpu))
4072                 return X86EMUL_CONTINUE;
4073
4074         if (kvm_x86_ops->has_wbinvd_exit()) {
4075                 int cpu = get_cpu();
4076
4077                 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4078                 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4079                                 wbinvd_ipi, NULL, 1);
4080                 put_cpu();
4081                 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4082         } else
4083                 wbinvd();
4084         return X86EMUL_CONTINUE;
4085 }
4086 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4087
4088 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4089 {
4090         kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4091 }
4092
4093 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
4094 {
4095         return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4096 }
4097
4098 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
4099 {
4100
4101         return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4102 }
4103
4104 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4105 {
4106         return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4107 }
4108
4109 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4110 {
4111         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4112         unsigned long value;
4113
4114         switch (cr) {
4115         case 0:
4116                 value = kvm_read_cr0(vcpu);
4117                 break;
4118         case 2:
4119                 value = vcpu->arch.cr2;
4120                 break;
4121         case 3:
4122                 value = kvm_read_cr3(vcpu);
4123                 break;
4124         case 4:
4125                 value = kvm_read_cr4(vcpu);
4126                 break;
4127         case 8:
4128                 value = kvm_get_cr8(vcpu);
4129                 break;
4130         default:
4131                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4132                 return 0;
4133         }
4134
4135         return value;
4136 }
4137
4138 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4139 {
4140         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4141         int res = 0;
4142
4143         switch (cr) {
4144         case 0:
4145                 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4146                 break;
4147         case 2:
4148                 vcpu->arch.cr2 = val;
4149                 break;
4150         case 3:
4151                 res = kvm_set_cr3(vcpu, val);
4152                 break;
4153         case 4:
4154                 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4155                 break;
4156         case 8:
4157                 res = kvm_set_cr8(vcpu, val);
4158                 break;
4159         default:
4160                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4161                 res = -1;
4162         }
4163
4164         return res;
4165 }
4166
4167 static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4168 {
4169         kvm_set_rflags(emul_to_vcpu(ctxt), val);
4170 }
4171
4172 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4173 {
4174         return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4175 }
4176
4177 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4178 {
4179         kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4180 }
4181
4182 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4183 {
4184         kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4185 }
4186
4187 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4188 {
4189         kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4190 }
4191
4192 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4193 {
4194         kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4195 }
4196
4197 static unsigned long emulator_get_cached_segment_base(
4198         struct x86_emulate_ctxt *ctxt, int seg)
4199 {
4200         return get_segment_base(emul_to_vcpu(ctxt), seg);
4201 }
4202
4203 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4204                                  struct desc_struct *desc, u32 *base3,
4205                                  int seg)
4206 {
4207         struct kvm_segment var;
4208
4209         kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4210         *selector = var.selector;
4211
4212         if (var.unusable)
4213                 return false;
4214
4215         if (var.g)
4216                 var.limit >>= 12;
4217         set_desc_limit(desc, var.limit);
4218         set_desc_base(desc, (unsigned long)var.base);
4219 #ifdef CONFIG_X86_64
4220         if (base3)
4221                 *base3 = var.base >> 32;
4222 #endif
4223         desc->type = var.type;
4224         desc->s = var.s;
4225         desc->dpl = var.dpl;
4226         desc->p = var.present;
4227         desc->avl = var.avl;
4228         desc->l = var.l;
4229         desc->d = var.db;
4230         desc->g = var.g;
4231
4232         return true;
4233 }
4234
4235 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4236                                  struct desc_struct *desc, u32 base3,
4237                                  int seg)
4238 {
4239         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4240         struct kvm_segment var;
4241
4242         var.selector = selector;
4243         var.base = get_desc_base(desc);
4244 #ifdef CONFIG_X86_64
4245         var.base |= ((u64)base3) << 32;
4246 #endif
4247         var.limit = get_desc_limit(desc);
4248         if (desc->g)
4249                 var.limit = (var.limit << 12) | 0xfff;
4250         var.type = desc->type;
4251         var.present = desc->p;
4252         var.dpl = desc->dpl;
4253         var.db = desc->d;
4254         var.s = desc->s;
4255         var.l = desc->l;
4256         var.g = desc->g;
4257         var.avl = desc->avl;
4258         var.present = desc->p;
4259         var.unusable = !var.present;
4260         var.padding = 0;
4261
4262         kvm_set_segment(vcpu, &var, seg);
4263         return;
4264 }
4265
4266 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4267                             u32 msr_index, u64 *pdata)
4268 {
4269         return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4270 }
4271
4272 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4273                             u32 msr_index, u64 data)
4274 {
4275         return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4276 }
4277
4278 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4279                              u32 pmc, u64 *pdata)
4280 {
4281         return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4282 }
4283
4284 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4285 {
4286         emul_to_vcpu(ctxt)->arch.halt_request = 1;
4287 }
4288
4289 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4290 {
4291         preempt_disable();
4292         kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4293         /*
4294          * CR0.TS may reference the host fpu state, not the guest fpu state,
4295          * so it may be clear at this point.
4296          */
4297         clts();
4298 }
4299
4300 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4301 {
4302         preempt_enable();
4303 }
4304
4305 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4306                               struct x86_instruction_info *info,
4307                               enum x86_intercept_stage stage)
4308 {
4309         return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4310 }
4311
4312 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4313                                u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4314 {
4315         kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4316 }
4317
4318 static struct x86_emulate_ops emulate_ops = {
4319         .read_std            = kvm_read_guest_virt_system,
4320         .write_std           = kvm_write_guest_virt_system,
4321         .fetch               = kvm_fetch_guest_virt,
4322         .read_emulated       = emulator_read_emulated,
4323         .write_emulated      = emulator_write_emulated,
4324         .cmpxchg_emulated    = emulator_cmpxchg_emulated,
4325         .invlpg              = emulator_invlpg,
4326         .pio_in_emulated     = emulator_pio_in_emulated,
4327         .pio_out_emulated    = emulator_pio_out_emulated,
4328         .get_segment         = emulator_get_segment,
4329         .set_segment         = emulator_set_segment,
4330         .get_cached_segment_base = emulator_get_cached_segment_base,
4331         .get_gdt             = emulator_get_gdt,
4332         .get_idt             = emulator_get_idt,
4333         .set_gdt             = emulator_set_gdt,
4334         .set_idt             = emulator_set_idt,
4335         .get_cr              = emulator_get_cr,
4336         .set_cr              = emulator_set_cr,
4337         .set_rflags          = emulator_set_rflags,
4338         .cpl                 = emulator_get_cpl,
4339         .get_dr              = emulator_get_dr,
4340         .set_dr              = emulator_set_dr,
4341         .set_msr             = emulator_set_msr,
4342         .get_msr             = emulator_get_msr,
4343         .read_pmc            = emulator_read_pmc,
4344         .halt                = emulator_halt,
4345         .wbinvd              = emulator_wbinvd,
4346         .fix_hypercall       = emulator_fix_hypercall,
4347         .get_fpu             = emulator_get_fpu,
4348         .put_fpu             = emulator_put_fpu,
4349         .intercept           = emulator_intercept,
4350         .get_cpuid           = emulator_get_cpuid,
4351 };
4352
4353 static void cache_all_regs(struct kvm_vcpu *vcpu)
4354 {
4355         kvm_register_read(vcpu, VCPU_REGS_RAX);
4356         kvm_register_read(vcpu, VCPU_REGS_RSP);
4357         kvm_register_read(vcpu, VCPU_REGS_RIP);
4358         vcpu->arch.regs_dirty = ~0;
4359 }
4360
4361 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4362 {
4363         u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4364         /*
4365          * an sti; sti; sequence only disable interrupts for the first
4366          * instruction. So, if the last instruction, be it emulated or
4367          * not, left the system with the INT_STI flag enabled, it
4368          * means that the last instruction is an sti. We should not
4369          * leave the flag on in this case. The same goes for mov ss
4370          */
4371         if (!(int_shadow & mask))
4372                 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4373 }
4374
4375 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4376 {
4377         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4378         if (ctxt->exception.vector == PF_VECTOR)
4379                 kvm_propagate_fault(vcpu, &ctxt->exception);
4380         else if (ctxt->exception.error_code_valid)
4381                 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4382                                       ctxt->exception.error_code);
4383         else
4384                 kvm_queue_exception(vcpu, ctxt->exception.vector);
4385 }
4386
4387 static void init_decode_cache(struct x86_emulate_ctxt *ctxt,
4388                               const unsigned long *regs)
4389 {
4390         memset(&ctxt->twobyte, 0,
4391                (void *)&ctxt->regs - (void *)&ctxt->twobyte);
4392         memcpy(ctxt->regs, regs, sizeof(ctxt->regs));
4393
4394         ctxt->fetch.start = 0;
4395         ctxt->fetch.end = 0;
4396         ctxt->io_read.pos = 0;
4397         ctxt->io_read.end = 0;
4398         ctxt->mem_read.pos = 0;
4399         ctxt->mem_read.end = 0;
4400 }
4401
4402 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4403 {
4404         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4405         int cs_db, cs_l;
4406
4407         /*
4408          * TODO: fix emulate.c to use guest_read/write_register
4409          * instead of direct ->regs accesses, can save hundred cycles
4410          * on Intel for instructions that don't read/change RSP, for
4411          * for example.
4412          */
4413         cache_all_regs(vcpu);
4414
4415         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4416
4417         ctxt->eflags = kvm_get_rflags(vcpu);
4418         ctxt->eip = kvm_rip_read(vcpu);
4419         ctxt->mode = (!is_protmode(vcpu))               ? X86EMUL_MODE_REAL :
4420                      (ctxt->eflags & X86_EFLAGS_VM)     ? X86EMUL_MODE_VM86 :
4421                      cs_l                               ? X86EMUL_MODE_PROT64 :
4422                      cs_db                              ? X86EMUL_MODE_PROT32 :
4423                                                           X86EMUL_MODE_PROT16;
4424         ctxt->guest_mode = is_guest_mode(vcpu);
4425
4426         init_decode_cache(ctxt, vcpu->arch.regs);
4427         vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4428 }
4429
4430 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4431 {
4432         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4433         int ret;
4434
4435         init_emulate_ctxt(vcpu);
4436
4437         ctxt->op_bytes = 2;
4438         ctxt->ad_bytes = 2;
4439         ctxt->_eip = ctxt->eip + inc_eip;
4440         ret = emulate_int_real(ctxt, irq);
4441
4442         if (ret != X86EMUL_CONTINUE)
4443                 return EMULATE_FAIL;
4444
4445         ctxt->eip = ctxt->_eip;
4446         memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
4447         kvm_rip_write(vcpu, ctxt->eip);
4448         kvm_set_rflags(vcpu, ctxt->eflags);
4449
4450         if (irq == NMI_VECTOR)
4451                 vcpu->arch.nmi_pending = 0;
4452         else
4453                 vcpu->arch.interrupt.pending = false;
4454
4455         return EMULATE_DONE;
4456 }
4457 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4458
4459 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4460 {
4461         int r = EMULATE_DONE;
4462
4463         ++vcpu->stat.insn_emulation_fail;
4464         trace_kvm_emulate_insn_failed(vcpu);
4465         if (!is_guest_mode(vcpu)) {
4466                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4467                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4468                 vcpu->run->internal.ndata = 0;
4469                 r = EMULATE_FAIL;
4470         }
4471         kvm_queue_exception(vcpu, UD_VECTOR);
4472
4473         return r;
4474 }
4475
4476 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4477 {
4478         gpa_t gpa;
4479
4480         if (tdp_enabled)
4481                 return false;
4482
4483         /*
4484          * if emulation was due to access to shadowed page table
4485          * and it failed try to unshadow page and re-enter the
4486          * guest to let CPU execute the instruction.
4487          */
4488         if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4489                 return true;
4490
4491         gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4492
4493         if (gpa == UNMAPPED_GVA)
4494                 return true; /* let cpu generate fault */
4495
4496         if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4497                 return true;
4498
4499         return false;
4500 }
4501
4502 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4503                               unsigned long cr2,  int emulation_type)
4504 {
4505         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4506         unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4507
4508         last_retry_eip = vcpu->arch.last_retry_eip;
4509         last_retry_addr = vcpu->arch.last_retry_addr;
4510
4511         /*
4512          * If the emulation is caused by #PF and it is non-page_table
4513          * writing instruction, it means the VM-EXIT is caused by shadow
4514          * page protected, we can zap the shadow page and retry this
4515          * instruction directly.
4516          *
4517          * Note: if the guest uses a non-page-table modifying instruction
4518          * on the PDE that points to the instruction, then we will unmap
4519          * the instruction and go to an infinite loop. So, we cache the
4520          * last retried eip and the last fault address, if we meet the eip
4521          * and the address again, we can break out of the potential infinite
4522          * loop.
4523          */
4524         vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4525
4526         if (!(emulation_type & EMULTYPE_RETRY))
4527                 return false;
4528
4529         if (x86_page_table_writing_insn(ctxt))
4530                 return false;
4531
4532         if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4533                 return false;
4534
4535         vcpu->arch.last_retry_eip = ctxt->eip;
4536         vcpu->arch.last_retry_addr = cr2;
4537
4538         if (!vcpu->arch.mmu.direct_map)
4539                 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4540
4541         kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4542
4543         return true;
4544 }
4545
4546 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4547                             unsigned long cr2,
4548                             int emulation_type,
4549                             void *insn,
4550                             int insn_len)
4551 {
4552         int r;
4553         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4554         bool writeback = true;
4555
4556         kvm_clear_exception_queue(vcpu);
4557
4558         if (!(emulation_type & EMULTYPE_NO_DECODE)) {
4559                 init_emulate_ctxt(vcpu);
4560                 ctxt->interruptibility = 0;
4561                 ctxt->have_exception = false;
4562                 ctxt->perm_ok = false;
4563
4564                 ctxt->only_vendor_specific_insn
4565                         = emulation_type & EMULTYPE_TRAP_UD;
4566
4567                 r = x86_decode_insn(ctxt, insn, insn_len);
4568
4569                 trace_kvm_emulate_insn_start(vcpu);
4570                 ++vcpu->stat.insn_emulation;
4571                 if (r != EMULATION_OK)  {
4572                         if (emulation_type & EMULTYPE_TRAP_UD)
4573                                 return EMULATE_FAIL;
4574                         if (reexecute_instruction(vcpu, cr2))
4575                                 return EMULATE_DONE;
4576                         if (emulation_type & EMULTYPE_SKIP)
4577                                 return EMULATE_FAIL;
4578                         return handle_emulation_failure(vcpu);
4579                 }
4580         }
4581
4582         if (emulation_type & EMULTYPE_SKIP) {
4583                 kvm_rip_write(vcpu, ctxt->_eip);
4584                 return EMULATE_DONE;
4585         }
4586
4587         if (retry_instruction(ctxt, cr2, emulation_type))
4588                 return EMULATE_DONE;
4589
4590         /* this is needed for vmware backdoor interface to work since it
4591            changes registers values  during IO operation */
4592         if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4593                 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4594                 memcpy(ctxt->regs, vcpu->arch.regs, sizeof ctxt->regs);
4595         }
4596
4597 restart:
4598         r = x86_emulate_insn(ctxt);
4599
4600         if (r == EMULATION_INTERCEPTED)
4601                 return EMULATE_DONE;
4602
4603         if (r == EMULATION_FAILED) {
4604                 if (reexecute_instruction(vcpu, cr2))
4605                         return EMULATE_DONE;
4606
4607                 return handle_emulation_failure(vcpu);
4608         }
4609
4610         if (ctxt->have_exception) {
4611                 inject_emulated_exception(vcpu);
4612                 r = EMULATE_DONE;
4613         } else if (vcpu->arch.pio.count) {
4614                 if (!vcpu->arch.pio.in)
4615                         vcpu->arch.pio.count = 0;
4616                 else
4617                         writeback = false;
4618                 r = EMULATE_DO_MMIO;
4619         } else if (vcpu->mmio_needed) {
4620                 if (!vcpu->mmio_is_write)
4621                         writeback = false;
4622                 r = EMULATE_DO_MMIO;
4623         } else if (r == EMULATION_RESTART)
4624                 goto restart;
4625         else
4626                 r = EMULATE_DONE;
4627
4628         if (writeback) {
4629                 toggle_interruptibility(vcpu, ctxt->interruptibility);
4630                 kvm_set_rflags(vcpu, ctxt->eflags);
4631                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4632                 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
4633                 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
4634                 kvm_rip_write(vcpu, ctxt->eip);
4635         } else
4636                 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
4637
4638         return r;
4639 }
4640 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
4641
4642 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
4643 {
4644         unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4645         int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4646                                             size, port, &val, 1);
4647         /* do not return to emulator after return from userspace */
4648         vcpu->arch.pio.count = 0;
4649         return ret;
4650 }
4651 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
4652
4653 static void tsc_bad(void *info)
4654 {
4655         __this_cpu_write(cpu_tsc_khz, 0);
4656 }
4657
4658 static void tsc_khz_changed(void *data)
4659 {
4660         struct cpufreq_freqs *freq = data;
4661         unsigned long khz = 0;
4662
4663         if (data)
4664                 khz = freq->new;
4665         else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4666                 khz = cpufreq_quick_get(raw_smp_processor_id());
4667         if (!khz)
4668                 khz = tsc_khz;
4669         __this_cpu_write(cpu_tsc_khz, khz);
4670 }
4671
4672 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4673                                      void *data)
4674 {
4675         struct cpufreq_freqs *freq = data;
4676         struct kvm *kvm;
4677         struct kvm_vcpu *vcpu;
4678         int i, send_ipi = 0;
4679
4680         /*
4681          * We allow guests to temporarily run on slowing clocks,
4682          * provided we notify them after, or to run on accelerating
4683          * clocks, provided we notify them before.  Thus time never
4684          * goes backwards.
4685          *
4686          * However, we have a problem.  We can't atomically update
4687          * the frequency of a given CPU from this function; it is
4688          * merely a notifier, which can be called from any CPU.
4689          * Changing the TSC frequency at arbitrary points in time
4690          * requires a recomputation of local variables related to
4691          * the TSC for each VCPU.  We must flag these local variables
4692          * to be updated and be sure the update takes place with the
4693          * new frequency before any guests proceed.
4694          *
4695          * Unfortunately, the combination of hotplug CPU and frequency
4696          * change creates an intractable locking scenario; the order
4697          * of when these callouts happen is undefined with respect to
4698          * CPU hotplug, and they can race with each other.  As such,
4699          * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4700          * undefined; you can actually have a CPU frequency change take
4701          * place in between the computation of X and the setting of the
4702          * variable.  To protect against this problem, all updates of
4703          * the per_cpu tsc_khz variable are done in an interrupt
4704          * protected IPI, and all callers wishing to update the value
4705          * must wait for a synchronous IPI to complete (which is trivial
4706          * if the caller is on the CPU already).  This establishes the
4707          * necessary total order on variable updates.
4708          *
4709          * Note that because a guest time update may take place
4710          * anytime after the setting of the VCPU's request bit, the
4711          * correct TSC value must be set before the request.  However,
4712          * to ensure the update actually makes it to any guest which
4713          * starts running in hardware virtualization between the set
4714          * and the acquisition of the spinlock, we must also ping the
4715          * CPU after setting the request bit.
4716          *
4717          */
4718
4719         if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4720                 return 0;
4721         if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4722                 return 0;
4723
4724         smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
4725
4726         raw_spin_lock(&kvm_lock);
4727         list_for_each_entry(kvm, &vm_list, vm_list) {
4728                 kvm_for_each_vcpu(i, vcpu, kvm) {
4729                         if (vcpu->cpu != freq->cpu)
4730                                 continue;
4731                         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4732                         if (vcpu->cpu != smp_processor_id())
4733                                 send_ipi = 1;
4734                 }
4735         }
4736         raw_spin_unlock(&kvm_lock);
4737
4738         if (freq->old < freq->new && send_ipi) {
4739                 /*
4740                  * We upscale the frequency.  Must make the guest
4741                  * doesn't see old kvmclock values while running with
4742                  * the new frequency, otherwise we risk the guest sees
4743                  * time go backwards.
4744                  *
4745                  * In case we update the frequency for another cpu
4746                  * (which might be in guest context) send an interrupt
4747                  * to kick the cpu out of guest context.  Next time
4748                  * guest context is entered kvmclock will be updated,
4749                  * so the guest will not see stale values.
4750                  */
4751                 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
4752         }
4753         return 0;
4754 }
4755
4756 static struct notifier_block kvmclock_cpufreq_notifier_block = {
4757         .notifier_call  = kvmclock_cpufreq_notifier
4758 };
4759
4760 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4761                                         unsigned long action, void *hcpu)
4762 {
4763         unsigned int cpu = (unsigned long)hcpu;
4764
4765         switch (action) {
4766                 case CPU_ONLINE:
4767                 case CPU_DOWN_FAILED:
4768                         smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4769                         break;
4770                 case CPU_DOWN_PREPARE:
4771                         smp_call_function_single(cpu, tsc_bad, NULL, 1);
4772                         break;
4773         }
4774         return NOTIFY_OK;
4775 }
4776
4777 static struct notifier_block kvmclock_cpu_notifier_block = {
4778         .notifier_call  = kvmclock_cpu_notifier,
4779         .priority = -INT_MAX
4780 };
4781
4782 static void kvm_timer_init(void)
4783 {
4784         int cpu;
4785
4786         max_tsc_khz = tsc_khz;
4787         register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
4788         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
4789 #ifdef CONFIG_CPU_FREQ
4790                 struct cpufreq_policy policy;
4791                 memset(&policy, 0, sizeof(policy));
4792                 cpu = get_cpu();
4793                 cpufreq_get_policy(&policy, cpu);
4794                 if (policy.cpuinfo.max_freq)
4795                         max_tsc_khz = policy.cpuinfo.max_freq;
4796                 put_cpu();
4797 #endif
4798                 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4799                                           CPUFREQ_TRANSITION_NOTIFIER);
4800         }
4801         pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
4802         for_each_online_cpu(cpu)
4803                 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4804 }
4805
4806 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4807
4808 int kvm_is_in_guest(void)
4809 {
4810         return __this_cpu_read(current_vcpu) != NULL;
4811 }
4812
4813 static int kvm_is_user_mode(void)
4814 {
4815         int user_mode = 3;
4816
4817         if (__this_cpu_read(current_vcpu))
4818                 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
4819
4820         return user_mode != 0;
4821 }
4822
4823 static unsigned long kvm_get_guest_ip(void)
4824 {
4825         unsigned long ip = 0;
4826
4827         if (__this_cpu_read(current_vcpu))
4828                 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
4829
4830         return ip;
4831 }
4832
4833 static struct perf_guest_info_callbacks kvm_guest_cbs = {
4834         .is_in_guest            = kvm_is_in_guest,
4835         .is_user_mode           = kvm_is_user_mode,
4836         .get_guest_ip           = kvm_get_guest_ip,
4837 };
4838
4839 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4840 {
4841         __this_cpu_write(current_vcpu, vcpu);
4842 }
4843 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4844
4845 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4846 {
4847         __this_cpu_write(current_vcpu, NULL);
4848 }
4849 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4850
4851 static void kvm_set_mmio_spte_mask(void)
4852 {
4853         u64 mask;
4854         int maxphyaddr = boot_cpu_data.x86_phys_bits;
4855
4856         /*
4857          * Set the reserved bits and the present bit of an paging-structure
4858          * entry to generate page fault with PFER.RSV = 1.
4859          */
4860         mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
4861         mask |= 1ull;
4862
4863 #ifdef CONFIG_X86_64
4864         /*
4865          * If reserved bit is not supported, clear the present bit to disable
4866          * mmio page fault.
4867          */
4868         if (maxphyaddr == 52)
4869                 mask &= ~1ull;
4870 #endif
4871
4872         kvm_mmu_set_mmio_spte_mask(mask);
4873 }
4874
4875 int kvm_arch_init(void *opaque)
4876 {
4877         int r;
4878         struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4879
4880         if (kvm_x86_ops) {
4881                 printk(KERN_ERR "kvm: already loaded the other module\n");
4882                 r = -EEXIST;
4883                 goto out;
4884         }
4885
4886         if (!ops->cpu_has_kvm_support()) {
4887                 printk(KERN_ERR "kvm: no hardware support\n");
4888                 r = -EOPNOTSUPP;
4889                 goto out;
4890         }
4891         if (ops->disabled_by_bios()) {
4892                 printk(KERN_ERR "kvm: disabled by bios\n");
4893                 r = -EOPNOTSUPP;
4894                 goto out;
4895         }
4896
4897         r = kvm_mmu_module_init();
4898         if (r)
4899                 goto out;
4900
4901         kvm_set_mmio_spte_mask();
4902         kvm_init_msr_list();
4903
4904         kvm_x86_ops = ops;
4905         kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4906                         PT_DIRTY_MASK, PT64_NX_MASK, 0);
4907
4908         kvm_timer_init();
4909
4910         perf_register_guest_info_callbacks(&kvm_guest_cbs);
4911
4912         if (cpu_has_xsave)
4913                 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4914
4915         return 0;
4916
4917 out:
4918         return r;
4919 }
4920
4921 void kvm_arch_exit(void)
4922 {
4923         perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4924
4925         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4926                 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4927                                             CPUFREQ_TRANSITION_NOTIFIER);
4928         unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
4929         kvm_x86_ops = NULL;
4930         kvm_mmu_module_exit();
4931 }
4932
4933 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4934 {
4935         ++vcpu->stat.halt_exits;
4936         if (irqchip_in_kernel(vcpu->kvm)) {
4937                 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
4938                 return 1;
4939         } else {
4940                 vcpu->run->exit_reason = KVM_EXIT_HLT;
4941                 return 0;
4942         }
4943 }
4944 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4945
4946 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4947 {
4948         u64 param, ingpa, outgpa, ret;
4949         uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4950         bool fast, longmode;
4951         int cs_db, cs_l;
4952
4953         /*
4954          * hypercall generates UD from non zero cpl and real mode
4955          * per HYPER-V spec
4956          */
4957         if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
4958                 kvm_queue_exception(vcpu, UD_VECTOR);
4959                 return 0;
4960         }
4961
4962         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4963         longmode = is_long_mode(vcpu) && cs_l == 1;
4964
4965         if (!longmode) {
4966                 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4967                         (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4968                 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4969                         (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4970                 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4971                         (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
4972         }
4973 #ifdef CONFIG_X86_64
4974         else {
4975                 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4976                 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4977                 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4978         }
4979 #endif
4980
4981         code = param & 0xffff;
4982         fast = (param >> 16) & 0x1;
4983         rep_cnt = (param >> 32) & 0xfff;
4984         rep_idx = (param >> 48) & 0xfff;
4985
4986         trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4987
4988         switch (code) {
4989         case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4990                 kvm_vcpu_on_spin(vcpu);
4991                 break;
4992         default:
4993                 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4994                 break;
4995         }
4996
4997         ret = res | (((u64)rep_done & 0xfff) << 32);
4998         if (longmode) {
4999                 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5000         } else {
5001                 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5002                 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5003         }
5004
5005         return 1;
5006 }
5007
5008 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5009 {
5010         unsigned long nr, a0, a1, a2, a3, ret;
5011         int r = 1;
5012
5013         if (kvm_hv_hypercall_enabled(vcpu->kvm))
5014                 return kvm_hv_hypercall(vcpu);
5015
5016         nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5017         a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5018         a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5019         a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5020         a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5021
5022         trace_kvm_hypercall(nr, a0, a1, a2, a3);
5023
5024         if (!is_long_mode(vcpu)) {
5025                 nr &= 0xFFFFFFFF;
5026                 a0 &= 0xFFFFFFFF;
5027                 a1 &= 0xFFFFFFFF;
5028                 a2 &= 0xFFFFFFFF;
5029                 a3 &= 0xFFFFFFFF;
5030         }
5031
5032         if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5033                 ret = -KVM_EPERM;
5034                 goto out;
5035         }
5036
5037         switch (nr) {
5038         case KVM_HC_VAPIC_POLL_IRQ:
5039                 ret = 0;
5040                 break;
5041         default:
5042                 ret = -KVM_ENOSYS;
5043                 break;
5044         }
5045 out:
5046         kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5047         ++vcpu->stat.hypercalls;
5048         return r;
5049 }
5050 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5051
5052 int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5053 {
5054         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5055         char instruction[3];
5056         unsigned long rip = kvm_rip_read(vcpu);
5057
5058         /*
5059          * Blow out the MMU to ensure that no other VCPU has an active mapping
5060          * to ensure that the updated hypercall appears atomically across all
5061          * VCPUs.
5062          */
5063         kvm_mmu_zap_all(vcpu->kvm);
5064
5065         kvm_x86_ops->patch_hypercall(vcpu, instruction);
5066
5067         return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5068 }
5069
5070 /*
5071  * Check if userspace requested an interrupt window, and that the
5072  * interrupt window is open.
5073  *
5074  * No need to exit to userspace if we already have an interrupt queued.
5075  */
5076 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5077 {
5078         return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5079                 vcpu->run->request_interrupt_window &&
5080                 kvm_arch_interrupt_allowed(vcpu));
5081 }
5082
5083 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5084 {
5085         struct kvm_run *kvm_run = vcpu->run;
5086
5087         kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5088         kvm_run->cr8 = kvm_get_cr8(vcpu);
5089         kvm_run->apic_base = kvm_get_apic_base(vcpu);
5090         if (irqchip_in_kernel(vcpu->kvm))
5091                 kvm_run->ready_for_interrupt_injection = 1;
5092         else
5093                 kvm_run->ready_for_interrupt_injection =
5094                         kvm_arch_interrupt_allowed(vcpu) &&
5095                         !kvm_cpu_has_interrupt(vcpu) &&
5096                         !kvm_event_needs_reinjection(vcpu);
5097 }
5098
5099 static void vapic_enter(struct kvm_vcpu *vcpu)
5100 {
5101         struct kvm_lapic *apic = vcpu->arch.apic;
5102         struct page *page;
5103
5104         if (!apic || !apic->vapic_addr)
5105                 return;
5106
5107         page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5108
5109         vcpu->arch.apic->vapic_page = page;
5110 }
5111
5112 static void vapic_exit(struct kvm_vcpu *vcpu)
5113 {
5114         struct kvm_lapic *apic = vcpu->arch.apic;
5115         int idx;
5116
5117         if (!apic || !apic->vapic_addr)
5118                 return;
5119
5120         idx = srcu_read_lock(&vcpu->kvm->srcu);
5121         kvm_release_page_dirty(apic->vapic_page);
5122         mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5123         srcu_read_unlock(&vcpu->kvm->srcu, idx);
5124 }
5125
5126 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5127 {
5128         int max_irr, tpr;
5129
5130         if (!kvm_x86_ops->update_cr8_intercept)
5131                 return;
5132
5133         if (!vcpu->arch.apic)
5134                 return;
5135
5136         if (!vcpu->arch.apic->vapic_addr)
5137                 max_irr = kvm_lapic_find_highest_irr(vcpu);
5138         else
5139                 max_irr = -1;
5140
5141         if (max_irr != -1)
5142                 max_irr >>= 4;
5143
5144         tpr = kvm_lapic_get_cr8(vcpu);
5145
5146         kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5147 }
5148
5149 static void inject_pending_event(struct kvm_vcpu *vcpu)
5150 {
5151         /* try to reinject previous events if any */
5152         if (vcpu->arch.exception.pending) {
5153                 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5154                                         vcpu->arch.exception.has_error_code,
5155                                         vcpu->arch.exception.error_code);
5156                 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5157                                           vcpu->arch.exception.has_error_code,
5158                                           vcpu->arch.exception.error_code,
5159                                           vcpu->arch.exception.reinject);
5160                 return;
5161         }
5162
5163         if (vcpu->arch.nmi_injected) {
5164                 kvm_x86_ops->set_nmi(vcpu);
5165                 return;
5166         }
5167
5168         if (vcpu->arch.interrupt.pending) {
5169                 kvm_x86_ops->set_irq(vcpu);
5170                 return;
5171         }
5172
5173         /* try to inject new event if pending */
5174         if (vcpu->arch.nmi_pending) {
5175                 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5176                         --vcpu->arch.nmi_pending;
5177                         vcpu->arch.nmi_injected = true;
5178                         kvm_x86_ops->set_nmi(vcpu);
5179                 }
5180         } else if (kvm_cpu_has_interrupt(vcpu)) {
5181                 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5182                         kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5183                                             false);
5184                         kvm_x86_ops->set_irq(vcpu);
5185                 }
5186         }
5187 }
5188
5189 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5190 {
5191         if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5192                         !vcpu->guest_xcr0_loaded) {
5193                 /* kvm_set_xcr() also depends on this */
5194                 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5195                 vcpu->guest_xcr0_loaded = 1;
5196         }
5197 }
5198
5199 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5200 {
5201         if (vcpu->guest_xcr0_loaded) {
5202                 if (vcpu->arch.xcr0 != host_xcr0)
5203                         xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5204                 vcpu->guest_xcr0_loaded = 0;
5205         }
5206 }
5207
5208 static void process_nmi(struct kvm_vcpu *vcpu)
5209 {
5210         unsigned limit = 2;
5211
5212         /*
5213          * x86 is limited to one NMI running, and one NMI pending after it.
5214          * If an NMI is already in progress, limit further NMIs to just one.
5215          * Otherwise, allow two (and we'll inject the first one immediately).
5216          */
5217         if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5218                 limit = 1;
5219
5220         vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5221         vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5222         kvm_make_request(KVM_REQ_EVENT, vcpu);
5223 }
5224
5225 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
5226 {
5227         int r;
5228         bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
5229                 vcpu->run->request_interrupt_window;
5230         bool req_immediate_exit = 0;
5231
5232         if (vcpu->requests) {
5233                 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
5234                         kvm_mmu_unload(vcpu);
5235                 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
5236                         __kvm_migrate_timers(vcpu);
5237                 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5238                         r = kvm_guest_time_update(vcpu);
5239                         if (unlikely(r))
5240                                 goto out;
5241                 }
5242                 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
5243                         kvm_mmu_sync_roots(vcpu);
5244                 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
5245                         kvm_x86_ops->tlb_flush(vcpu);
5246                 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
5247                         vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
5248                         r = 0;
5249                         goto out;
5250                 }
5251                 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
5252                         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5253                         r = 0;
5254                         goto out;
5255                 }
5256                 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
5257                         vcpu->fpu_active = 0;
5258                         kvm_x86_ops->fpu_deactivate(vcpu);
5259                 }
5260                 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5261                         /* Page is swapped out. Do synthetic halt */
5262                         vcpu->arch.apf.halted = true;
5263                         r = 1;
5264                         goto out;
5265                 }
5266                 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5267                         record_steal_time(vcpu);
5268                 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5269                         process_nmi(vcpu);
5270                 req_immediate_exit =
5271                         kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
5272                 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5273                         kvm_handle_pmu_event(vcpu);
5274                 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5275                         kvm_deliver_pmi(vcpu);
5276         }
5277
5278         if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5279                 inject_pending_event(vcpu);
5280
5281                 /* enable NMI/IRQ window open exits if needed */
5282                 if (vcpu->arch.nmi_pending)
5283                         kvm_x86_ops->enable_nmi_window(vcpu);
5284                 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5285                         kvm_x86_ops->enable_irq_window(vcpu);
5286
5287                 if (kvm_lapic_enabled(vcpu)) {
5288                         update_cr8_intercept(vcpu);
5289                         kvm_lapic_sync_to_vapic(vcpu);
5290                 }
5291         }
5292
5293         r = kvm_mmu_reload(vcpu);
5294         if (unlikely(r)) {
5295                 goto cancel_injection;
5296         }
5297
5298         preempt_disable();
5299
5300         kvm_x86_ops->prepare_guest_switch(vcpu);
5301         if (vcpu->fpu_active)
5302                 kvm_load_guest_fpu(vcpu);
5303         kvm_load_guest_xcr0(vcpu);
5304
5305         vcpu->mode = IN_GUEST_MODE;
5306
5307         /* We should set ->mode before check ->requests,
5308          * see the comment in make_all_cpus_request.
5309          */
5310         smp_mb();
5311
5312         local_irq_disable();
5313
5314         if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
5315             || need_resched() || signal_pending(current)) {
5316                 vcpu->mode = OUTSIDE_GUEST_MODE;
5317                 smp_wmb();
5318                 local_irq_enable();
5319                 preempt_enable();
5320                 r = 1;
5321                 goto cancel_injection;
5322         }
5323
5324         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5325
5326         if (req_immediate_exit)
5327                 smp_send_reschedule(vcpu->cpu);
5328
5329         kvm_guest_enter();
5330
5331         if (unlikely(vcpu->arch.switch_db_regs)) {
5332                 set_debugreg(0, 7);
5333                 set_debugreg(vcpu->arch.eff_db[0], 0);
5334                 set_debugreg(vcpu->arch.eff_db[1], 1);
5335                 set_debugreg(vcpu->arch.eff_db[2], 2);
5336                 set_debugreg(vcpu->arch.eff_db[3], 3);
5337         }
5338
5339         trace_kvm_entry(vcpu->vcpu_id);
5340         kvm_x86_ops->run(vcpu);
5341
5342         /*
5343          * If the guest has used debug registers, at least dr7
5344          * will be disabled while returning to the host.
5345          * If we don't have active breakpoints in the host, we don't
5346          * care about the messed up debug address registers. But if
5347          * we have some of them active, restore the old state.
5348          */
5349         if (hw_breakpoint_active())
5350                 hw_breakpoint_restore();
5351
5352         vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
5353
5354         vcpu->mode = OUTSIDE_GUEST_MODE;
5355         smp_wmb();
5356         local_irq_enable();
5357
5358         ++vcpu->stat.exits;
5359
5360         /*
5361          * We must have an instruction between local_irq_enable() and
5362          * kvm_guest_exit(), so the timer interrupt isn't delayed by
5363          * the interrupt shadow.  The stat.exits increment will do nicely.
5364          * But we need to prevent reordering, hence this barrier():
5365          */
5366         barrier();
5367
5368         kvm_guest_exit();
5369
5370         preempt_enable();
5371
5372         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5373
5374         /*
5375          * Profile KVM exit RIPs:
5376          */
5377         if (unlikely(prof_on == KVM_PROFILING)) {
5378                 unsigned long rip = kvm_rip_read(vcpu);
5379                 profile_hit(KVM_PROFILING, (void *)rip);
5380         }
5381
5382         if (unlikely(vcpu->arch.tsc_always_catchup))
5383                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5384
5385         if (vcpu->arch.apic_attention)
5386                 kvm_lapic_sync_from_vapic(vcpu);
5387
5388         r = kvm_x86_ops->handle_exit(vcpu);
5389         return r;
5390
5391 cancel_injection:
5392         kvm_x86_ops->cancel_injection(vcpu);
5393         if (unlikely(vcpu->arch.apic_attention))
5394                 kvm_lapic_sync_from_vapic(vcpu);
5395 out:
5396         return r;
5397 }
5398
5399
5400 static int __vcpu_run(struct kvm_vcpu *vcpu)
5401 {
5402         int r;
5403         struct kvm *kvm = vcpu->kvm;
5404
5405         if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
5406                 pr_debug("vcpu %d received sipi with vector # %x\n",
5407                          vcpu->vcpu_id, vcpu->arch.sipi_vector);
5408                 kvm_lapic_reset(vcpu);
5409                 r = kvm_arch_vcpu_reset(vcpu);
5410                 if (r)
5411                         return r;
5412                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5413         }
5414
5415         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5416         vapic_enter(vcpu);
5417
5418         r = 1;
5419         while (r > 0) {
5420                 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5421                     !vcpu->arch.apf.halted)
5422                         r = vcpu_enter_guest(vcpu);
5423                 else {
5424                         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5425                         kvm_vcpu_block(vcpu);
5426                         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5427                         if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
5428                         {
5429                                 switch(vcpu->arch.mp_state) {
5430                                 case KVM_MP_STATE_HALTED:
5431                                         vcpu->arch.mp_state =
5432                                                 KVM_MP_STATE_RUNNABLE;
5433                                 case KVM_MP_STATE_RUNNABLE:
5434                                         vcpu->arch.apf.halted = false;
5435                                         break;
5436                                 case KVM_MP_STATE_SIPI_RECEIVED:
5437                                 default:
5438                                         r = -EINTR;
5439                                         break;
5440                                 }
5441                         }
5442                 }
5443
5444                 if (r <= 0)
5445                         break;
5446
5447                 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5448                 if (kvm_cpu_has_pending_timer(vcpu))
5449                         kvm_inject_pending_timer_irqs(vcpu);
5450
5451                 if (dm_request_for_irq_injection(vcpu)) {
5452                         r = -EINTR;
5453                         vcpu->run->exit_reason = KVM_EXIT_INTR;
5454                         ++vcpu->stat.request_irq_exits;
5455                 }
5456
5457                 kvm_check_async_pf_completion(vcpu);
5458
5459                 if (signal_pending(current)) {
5460                         r = -EINTR;
5461                         vcpu->run->exit_reason = KVM_EXIT_INTR;
5462                         ++vcpu->stat.signal_exits;
5463                 }
5464                 if (need_resched()) {
5465                         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5466                         kvm_resched(vcpu);
5467                         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5468                 }
5469         }
5470
5471         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5472
5473         vapic_exit(vcpu);
5474
5475         return r;
5476 }
5477
5478 /*
5479  * Implements the following, as a state machine:
5480  *
5481  * read:
5482  *   for each fragment
5483  *     write gpa, len
5484  *     exit
5485  *     copy data
5486  *   execute insn
5487  *
5488  * write:
5489  *   for each fragment
5490  *      write gpa, len
5491  *      copy data
5492  *      exit
5493  */
5494 static int complete_mmio(struct kvm_vcpu *vcpu)
5495 {
5496         struct kvm_run *run = vcpu->run;
5497         struct kvm_mmio_fragment *frag;
5498         int r;
5499
5500         if (!(vcpu->arch.pio.count || vcpu->mmio_needed))
5501                 return 1;
5502
5503         if (vcpu->mmio_needed) {
5504                 /* Complete previous fragment */
5505                 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment++];
5506                 if (!vcpu->mmio_is_write)
5507                         memcpy(frag->data, run->mmio.data, frag->len);
5508                 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
5509                         vcpu->mmio_needed = 0;
5510                         if (vcpu->mmio_is_write)
5511                                 return 1;
5512                         vcpu->mmio_read_completed = 1;
5513                         goto done;
5514                 }
5515                 /* Initiate next fragment */
5516                 ++frag;
5517                 run->exit_reason = KVM_EXIT_MMIO;
5518                 run->mmio.phys_addr = frag->gpa;
5519                 if (vcpu->mmio_is_write)
5520                         memcpy(run->mmio.data, frag->data, frag->len);
5521                 run->mmio.len = frag->len;
5522                 run->mmio.is_write = vcpu->mmio_is_write;
5523                 return 0;
5524
5525         }
5526 done:
5527         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5528         r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5529         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5530         if (r != EMULATE_DONE)
5531                 return 0;
5532         return 1;
5533 }
5534
5535 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5536 {
5537         int r;
5538         sigset_t sigsaved;
5539
5540         if (!tsk_used_math(current) && init_fpu(current))
5541                 return -ENOMEM;
5542
5543         if (vcpu->sigset_active)
5544                 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5545
5546         if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
5547                 kvm_vcpu_block(vcpu);
5548                 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
5549                 r = -EAGAIN;
5550                 goto out;
5551         }
5552
5553         /* re-sync apic's tpr */
5554         if (!irqchip_in_kernel(vcpu->kvm)) {
5555                 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5556                         r = -EINVAL;
5557                         goto out;
5558                 }
5559         }
5560
5561         r = complete_mmio(vcpu);
5562         if (r <= 0)
5563                 goto out;
5564
5565         r = __vcpu_run(vcpu);
5566
5567 out:
5568         post_kvm_run_save(vcpu);
5569         if (vcpu->sigset_active)
5570                 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5571
5572         return r;
5573 }
5574
5575 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5576 {
5577         if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5578                 /*
5579                  * We are here if userspace calls get_regs() in the middle of
5580                  * instruction emulation. Registers state needs to be copied
5581                  * back from emulation context to vcpu. Userspace shouldn't do
5582                  * that usually, but some bad designed PV devices (vmware
5583                  * backdoor interface) need this to work
5584                  */
5585                 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5586                 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
5587                 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5588         }
5589         regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5590         regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5591         regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5592         regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5593         regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5594         regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5595         regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5596         regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
5597 #ifdef CONFIG_X86_64
5598         regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5599         regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5600         regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5601         regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5602         regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5603         regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5604         regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5605         regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
5606 #endif
5607
5608         regs->rip = kvm_rip_read(vcpu);
5609         regs->rflags = kvm_get_rflags(vcpu);
5610
5611         return 0;
5612 }
5613
5614 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5615 {
5616         vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
5617         vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5618
5619         kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5620         kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5621         kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5622         kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5623         kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5624         kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5625         kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5626         kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
5627 #ifdef CONFIG_X86_64
5628         kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5629         kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5630         kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5631         kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5632         kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5633         kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5634         kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5635         kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
5636 #endif
5637
5638         kvm_rip_write(vcpu, regs->rip);
5639         kvm_set_rflags(vcpu, regs->rflags);
5640
5641         vcpu->arch.exception.pending = false;
5642
5643         kvm_make_request(KVM_REQ_EVENT, vcpu);
5644
5645         return 0;
5646 }
5647
5648 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5649 {
5650         struct kvm_segment cs;
5651
5652         kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
5653         *db = cs.db;
5654         *l = cs.l;
5655 }
5656 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5657
5658 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5659                                   struct kvm_sregs *sregs)
5660 {
5661         struct desc_ptr dt;
5662
5663         kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5664         kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5665         kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5666         kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5667         kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5668         kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
5669
5670         kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5671         kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
5672
5673         kvm_x86_ops->get_idt(vcpu, &dt);
5674         sregs->idt.limit = dt.size;
5675         sregs->idt.base = dt.address;
5676         kvm_x86_ops->get_gdt(vcpu, &dt);
5677         sregs->gdt.limit = dt.size;
5678         sregs->gdt.base = dt.address;
5679
5680         sregs->cr0 = kvm_read_cr0(vcpu);
5681         sregs->cr2 = vcpu->arch.cr2;
5682         sregs->cr3 = kvm_read_cr3(vcpu);
5683         sregs->cr4 = kvm_read_cr4(vcpu);
5684         sregs->cr8 = kvm_get_cr8(vcpu);
5685         sregs->efer = vcpu->arch.efer;
5686         sregs->apic_base = kvm_get_apic_base(vcpu);
5687
5688         memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
5689
5690         if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
5691                 set_bit(vcpu->arch.interrupt.nr,
5692                         (unsigned long *)sregs->interrupt_bitmap);
5693
5694         return 0;
5695 }
5696
5697 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5698                                     struct kvm_mp_state *mp_state)
5699 {
5700         mp_state->mp_state = vcpu->arch.mp_state;
5701         return 0;
5702 }
5703
5704 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5705                                     struct kvm_mp_state *mp_state)
5706 {
5707         vcpu->arch.mp_state = mp_state->mp_state;
5708         kvm_make_request(KVM_REQ_EVENT, vcpu);
5709         return 0;
5710 }
5711
5712 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
5713                     int reason, bool has_error_code, u32 error_code)
5714 {
5715         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5716         int ret;
5717
5718         init_emulate_ctxt(vcpu);
5719
5720         ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
5721                                    has_error_code, error_code);
5722
5723         if (ret)
5724                 return EMULATE_FAIL;
5725
5726         memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
5727         kvm_rip_write(vcpu, ctxt->eip);
5728         kvm_set_rflags(vcpu, ctxt->eflags);
5729         kvm_make_request(KVM_REQ_EVENT, vcpu);
5730         return EMULATE_DONE;
5731 }
5732 EXPORT_SYMBOL_GPL(kvm_task_switch);
5733
5734 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5735                                   struct kvm_sregs *sregs)
5736 {
5737         int mmu_reset_needed = 0;
5738         int pending_vec, max_bits, idx;
5739         struct desc_ptr dt;
5740
5741         dt.size = sregs->idt.limit;
5742         dt.address = sregs->idt.base;
5743         kvm_x86_ops->set_idt(vcpu, &dt);
5744         dt.size = sregs->gdt.limit;
5745         dt.address = sregs->gdt.base;
5746         kvm_x86_ops->set_gdt(vcpu, &dt);
5747
5748         vcpu->arch.cr2 = sregs->cr2;
5749         mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
5750         vcpu->arch.cr3 = sregs->cr3;
5751         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
5752
5753         kvm_set_cr8(vcpu, sregs->cr8);
5754
5755         mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
5756         kvm_x86_ops->set_efer(vcpu, sregs->efer);
5757         kvm_set_apic_base(vcpu, sregs->apic_base);
5758
5759         mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
5760         kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
5761         vcpu->arch.cr0 = sregs->cr0;
5762
5763         mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
5764         kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
5765         if (sregs->cr4 & X86_CR4_OSXSAVE)
5766                 kvm_update_cpuid(vcpu);
5767
5768         idx = srcu_read_lock(&vcpu->kvm->srcu);
5769         if (!is_long_mode(vcpu) && is_pae(vcpu)) {
5770                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
5771                 mmu_reset_needed = 1;
5772         }
5773         srcu_read_unlock(&vcpu->kvm->srcu, idx);
5774
5775         if (mmu_reset_needed)
5776                 kvm_mmu_reset_context(vcpu);
5777
5778         max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5779         pending_vec = find_first_bit(
5780                 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5781         if (pending_vec < max_bits) {
5782                 kvm_queue_interrupt(vcpu, pending_vec, false);
5783                 pr_debug("Set back pending irq %d\n", pending_vec);
5784         }
5785
5786         kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5787         kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5788         kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5789         kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5790         kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5791         kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
5792
5793         kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5794         kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
5795
5796         update_cr8_intercept(vcpu);
5797
5798         /* Older userspace won't unhalt the vcpu on reset. */
5799         if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
5800             sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
5801             !is_protmode(vcpu))
5802                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5803
5804         kvm_make_request(KVM_REQ_EVENT, vcpu);
5805
5806         return 0;
5807 }
5808
5809 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5810                                         struct kvm_guest_debug *dbg)
5811 {
5812         unsigned long rflags;
5813         int i, r;
5814
5815         if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5816                 r = -EBUSY;
5817                 if (vcpu->arch.exception.pending)
5818                         goto out;
5819                 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5820                         kvm_queue_exception(vcpu, DB_VECTOR);
5821                 else
5822                         kvm_queue_exception(vcpu, BP_VECTOR);
5823         }
5824
5825         /*
5826          * Read rflags as long as potentially injected trace flags are still
5827          * filtered out.
5828          */
5829         rflags = kvm_get_rflags(vcpu);
5830
5831         vcpu->guest_debug = dbg->control;
5832         if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5833                 vcpu->guest_debug = 0;
5834
5835         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5836                 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5837                         vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5838                 vcpu->arch.switch_db_regs =
5839                         (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5840         } else {
5841                 for (i = 0; i < KVM_NR_DB_REGS; i++)
5842                         vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5843                 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5844         }
5845
5846         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5847                 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5848                         get_segment_base(vcpu, VCPU_SREG_CS);
5849
5850         /*
5851          * Trigger an rflags update that will inject or remove the trace
5852          * flags.
5853          */
5854         kvm_set_rflags(vcpu, rflags);
5855
5856         kvm_x86_ops->set_guest_debug(vcpu, dbg);
5857
5858         r = 0;
5859
5860 out:
5861
5862         return r;
5863 }
5864
5865 /*
5866  * Translate a guest virtual address to a guest physical address.
5867  */
5868 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5869                                     struct kvm_translation *tr)
5870 {
5871         unsigned long vaddr = tr->linear_address;
5872         gpa_t gpa;
5873         int idx;
5874
5875         idx = srcu_read_lock(&vcpu->kvm->srcu);
5876         gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
5877         srcu_read_unlock(&vcpu->kvm->srcu, idx);
5878         tr->physical_address = gpa;
5879         tr->valid = gpa != UNMAPPED_GVA;
5880         tr->writeable = 1;
5881         tr->usermode = 0;
5882
5883         return 0;
5884 }
5885
5886 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5887 {
5888         struct i387_fxsave_struct *fxsave =
5889                         &vcpu->arch.guest_fpu.state->fxsave;
5890
5891         memcpy(fpu->fpr, fxsave->st_space, 128);
5892         fpu->fcw = fxsave->cwd;
5893         fpu->fsw = fxsave->swd;
5894         fpu->ftwx = fxsave->twd;
5895         fpu->last_opcode = fxsave->fop;
5896         fpu->last_ip = fxsave->rip;
5897         fpu->last_dp = fxsave->rdp;
5898         memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5899
5900         return 0;
5901 }
5902
5903 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5904 {
5905         struct i387_fxsave_struct *fxsave =
5906                         &vcpu->arch.guest_fpu.state->fxsave;
5907
5908         memcpy(fxsave->st_space, fpu->fpr, 128);
5909         fxsave->cwd = fpu->fcw;
5910         fxsave->swd = fpu->fsw;
5911         fxsave->twd = fpu->ftwx;
5912         fxsave->fop = fpu->last_opcode;
5913         fxsave->rip = fpu->last_ip;
5914         fxsave->rdp = fpu->last_dp;
5915         memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5916
5917         return 0;
5918 }
5919
5920 int fx_init(struct kvm_vcpu *vcpu)
5921 {
5922         int err;
5923
5924         err = fpu_alloc(&vcpu->arch.guest_fpu);
5925         if (err)
5926                 return err;
5927
5928         fpu_finit(&vcpu->arch.guest_fpu);
5929
5930         /*
5931          * Ensure guest xcr0 is valid for loading
5932          */
5933         vcpu->arch.xcr0 = XSTATE_FP;
5934
5935         vcpu->arch.cr0 |= X86_CR0_ET;
5936
5937         return 0;
5938 }
5939 EXPORT_SYMBOL_GPL(fx_init);
5940
5941 static void fx_free(struct kvm_vcpu *vcpu)
5942 {
5943         fpu_free(&vcpu->arch.guest_fpu);
5944 }
5945
5946 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5947 {
5948         if (vcpu->guest_fpu_loaded)
5949                 return;
5950
5951         /*
5952          * Restore all possible states in the guest,
5953          * and assume host would use all available bits.
5954          * Guest xcr0 would be loaded later.
5955          */
5956         kvm_put_guest_xcr0(vcpu);
5957         vcpu->guest_fpu_loaded = 1;
5958         unlazy_fpu(current);
5959         fpu_restore_checking(&vcpu->arch.guest_fpu);
5960         trace_kvm_fpu(1);
5961 }
5962
5963 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5964 {
5965         kvm_put_guest_xcr0(vcpu);
5966
5967         if (!vcpu->guest_fpu_loaded)
5968                 return;
5969
5970         vcpu->guest_fpu_loaded = 0;
5971         fpu_save_init(&vcpu->arch.guest_fpu);
5972         ++vcpu->stat.fpu_reload;
5973         kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
5974         trace_kvm_fpu(0);
5975 }
5976
5977 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5978 {
5979         kvmclock_reset(vcpu);
5980
5981         free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
5982         fx_free(vcpu);
5983         kvm_x86_ops->vcpu_free(vcpu);
5984 }
5985
5986 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5987                                                 unsigned int id)
5988 {
5989         if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5990                 printk_once(KERN_WARNING
5991                 "kvm: SMP vm created on host with unstable TSC; "
5992                 "guest TSC will not be reliable\n");
5993         return kvm_x86_ops->vcpu_create(kvm, id);
5994 }
5995
5996 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5997 {
5998         int r;
5999
6000         vcpu->arch.mtrr_state.have_fixed = 1;
6001         vcpu_load(vcpu);
6002         r = kvm_arch_vcpu_reset(vcpu);
6003         if (r == 0)
6004                 r = kvm_mmu_setup(vcpu);
6005         vcpu_put(vcpu);
6006
6007         return r;
6008 }
6009
6010 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
6011 {
6012         vcpu->arch.apf.msr_val = 0;
6013
6014         vcpu_load(vcpu);
6015         kvm_mmu_unload(vcpu);
6016         vcpu_put(vcpu);
6017
6018         fx_free(vcpu);
6019         kvm_x86_ops->vcpu_free(vcpu);
6020 }
6021
6022 int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
6023 {
6024         atomic_set(&vcpu->arch.nmi_queued, 0);
6025         vcpu->arch.nmi_pending = 0;
6026         vcpu->arch.nmi_injected = false;
6027
6028         vcpu->arch.switch_db_regs = 0;
6029         memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6030         vcpu->arch.dr6 = DR6_FIXED_1;
6031         vcpu->arch.dr7 = DR7_FIXED_1;
6032
6033         kvm_make_request(KVM_REQ_EVENT, vcpu);
6034         vcpu->arch.apf.msr_val = 0;
6035         vcpu->arch.st.msr_val = 0;
6036
6037         kvmclock_reset(vcpu);
6038
6039         kvm_clear_async_pf_completion_queue(vcpu);
6040         kvm_async_pf_hash_reset(vcpu);
6041         vcpu->arch.apf.halted = false;
6042
6043         kvm_pmu_reset(vcpu);
6044
6045         return kvm_x86_ops->vcpu_reset(vcpu);
6046 }
6047
6048 int kvm_arch_hardware_enable(void *garbage)
6049 {
6050         struct kvm *kvm;
6051         struct kvm_vcpu *vcpu;
6052         int i;
6053         int ret;
6054         u64 local_tsc;
6055         u64 max_tsc = 0;
6056         bool stable, backwards_tsc = false;
6057
6058         kvm_shared_msr_cpu_online();
6059         ret = kvm_x86_ops->hardware_enable(garbage);
6060         if (ret != 0)
6061                 return ret;
6062
6063         local_tsc = native_read_tsc();
6064         stable = !check_tsc_unstable();
6065         list_for_each_entry(kvm, &vm_list, vm_list) {
6066                 kvm_for_each_vcpu(i, vcpu, kvm) {
6067                         if (!stable && vcpu->cpu == smp_processor_id())
6068                                 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6069                         if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6070                                 backwards_tsc = true;
6071                                 if (vcpu->arch.last_host_tsc > max_tsc)
6072                                         max_tsc = vcpu->arch.last_host_tsc;
6073                         }
6074                 }
6075         }
6076
6077         /*
6078          * Sometimes, even reliable TSCs go backwards.  This happens on
6079          * platforms that reset TSC during suspend or hibernate actions, but
6080          * maintain synchronization.  We must compensate.  Fortunately, we can
6081          * detect that condition here, which happens early in CPU bringup,
6082          * before any KVM threads can be running.  Unfortunately, we can't
6083          * bring the TSCs fully up to date with real time, as we aren't yet far
6084          * enough into CPU bringup that we know how much real time has actually
6085          * elapsed; our helper function, get_kernel_ns() will be using boot
6086          * variables that haven't been updated yet.
6087          *
6088          * So we simply find the maximum observed TSC above, then record the
6089          * adjustment to TSC in each VCPU.  When the VCPU later gets loaded,
6090          * the adjustment will be applied.  Note that we accumulate
6091          * adjustments, in case multiple suspend cycles happen before some VCPU
6092          * gets a chance to run again.  In the event that no KVM threads get a
6093          * chance to run, we will miss the entire elapsed period, as we'll have
6094          * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6095          * loose cycle time.  This isn't too big a deal, since the loss will be
6096          * uniform across all VCPUs (not to mention the scenario is extremely
6097          * unlikely). It is possible that a second hibernate recovery happens
6098          * much faster than a first, causing the observed TSC here to be
6099          * smaller; this would require additional padding adjustment, which is
6100          * why we set last_host_tsc to the local tsc observed here.
6101          *
6102          * N.B. - this code below runs only on platforms with reliable TSC,
6103          * as that is the only way backwards_tsc is set above.  Also note
6104          * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6105          * have the same delta_cyc adjustment applied if backwards_tsc
6106          * is detected.  Note further, this adjustment is only done once,
6107          * as we reset last_host_tsc on all VCPUs to stop this from being
6108          * called multiple times (one for each physical CPU bringup).
6109          *
6110          * Platforms with unreliable TSCs don't have to deal with this, they
6111          * will be compensated by the logic in vcpu_load, which sets the TSC to
6112          * catchup mode.  This will catchup all VCPUs to real time, but cannot
6113          * guarantee that they stay in perfect synchronization.
6114          */
6115         if (backwards_tsc) {
6116                 u64 delta_cyc = max_tsc - local_tsc;
6117                 list_for_each_entry(kvm, &vm_list, vm_list) {
6118                         kvm_for_each_vcpu(i, vcpu, kvm) {
6119                                 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6120                                 vcpu->arch.last_host_tsc = local_tsc;
6121                         }
6122
6123                         /*
6124                          * We have to disable TSC offset matching.. if you were
6125                          * booting a VM while issuing an S4 host suspend....
6126                          * you may have some problem.  Solving this issue is
6127                          * left as an exercise to the reader.
6128                          */
6129                         kvm->arch.last_tsc_nsec = 0;
6130                         kvm->arch.last_tsc_write = 0;
6131                 }
6132
6133         }
6134         return 0;
6135 }
6136
6137 void kvm_arch_hardware_disable(void *garbage)
6138 {
6139         kvm_x86_ops->hardware_disable(garbage);
6140         drop_user_return_notifiers(garbage);
6141 }
6142
6143 int kvm_arch_hardware_setup(void)
6144 {
6145         return kvm_x86_ops->hardware_setup();
6146 }
6147
6148 void kvm_arch_hardware_unsetup(void)
6149 {
6150         kvm_x86_ops->hardware_unsetup();
6151 }
6152
6153 void kvm_arch_check_processor_compat(void *rtn)
6154 {
6155         kvm_x86_ops->check_processor_compatibility(rtn);
6156 }
6157
6158 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6159 {
6160         return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6161 }
6162
6163 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6164 {
6165         struct page *page;
6166         struct kvm *kvm;
6167         int r;
6168
6169         BUG_ON(vcpu->kvm == NULL);
6170         kvm = vcpu->kvm;
6171
6172         vcpu->arch.emulate_ctxt.ops = &emulate_ops;
6173         if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
6174                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6175         else
6176                 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
6177
6178         page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6179         if (!page) {
6180                 r = -ENOMEM;
6181                 goto fail;
6182         }
6183         vcpu->arch.pio_data = page_address(page);
6184
6185         kvm_set_tsc_khz(vcpu, max_tsc_khz);
6186
6187         r = kvm_mmu_create(vcpu);
6188         if (r < 0)
6189                 goto fail_free_pio_data;
6190
6191         if (irqchip_in_kernel(kvm)) {
6192                 r = kvm_create_lapic(vcpu);
6193                 if (r < 0)
6194                         goto fail_mmu_destroy;
6195         }
6196
6197         vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6198                                        GFP_KERNEL);
6199         if (!vcpu->arch.mce_banks) {
6200                 r = -ENOMEM;
6201                 goto fail_free_lapic;
6202         }
6203         vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6204
6205         if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6206                 goto fail_free_mce_banks;
6207
6208         kvm_async_pf_hash_reset(vcpu);
6209         kvm_pmu_init(vcpu);
6210
6211         return 0;
6212 fail_free_mce_banks:
6213         kfree(vcpu->arch.mce_banks);
6214 fail_free_lapic:
6215         kvm_free_lapic(vcpu);
6216 fail_mmu_destroy:
6217         kvm_mmu_destroy(vcpu);
6218 fail_free_pio_data:
6219         free_page((unsigned long)vcpu->arch.pio_data);
6220 fail:
6221         return r;
6222 }
6223
6224 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6225 {
6226         int idx;
6227
6228         kvm_pmu_destroy(vcpu);
6229         kfree(vcpu->arch.mce_banks);
6230         kvm_free_lapic(vcpu);
6231         idx = srcu_read_lock(&vcpu->kvm->srcu);
6232         kvm_mmu_destroy(vcpu);
6233         srcu_read_unlock(&vcpu->kvm->srcu, idx);
6234         free_page((unsigned long)vcpu->arch.pio_data);
6235 }
6236
6237 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
6238 {
6239         if (type)
6240                 return -EINVAL;
6241
6242         INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
6243         INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
6244
6245         /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6246         set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6247
6248         raw_spin_lock_init(&kvm->arch.tsc_write_lock);
6249
6250         return 0;
6251 }
6252
6253 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6254 {
6255         vcpu_load(vcpu);
6256         kvm_mmu_unload(vcpu);
6257         vcpu_put(vcpu);
6258 }
6259
6260 static void kvm_free_vcpus(struct kvm *kvm)
6261 {
6262         unsigned int i;
6263         struct kvm_vcpu *vcpu;
6264
6265         /*
6266          * Unpin any mmu pages first.
6267          */
6268         kvm_for_each_vcpu(i, vcpu, kvm) {
6269                 kvm_clear_async_pf_completion_queue(vcpu);
6270                 kvm_unload_vcpu_mmu(vcpu);
6271         }
6272         kvm_for_each_vcpu(i, vcpu, kvm)
6273                 kvm_arch_vcpu_free(vcpu);