x86/PCI: Map PCI setup data with ioremap() so it can be in highmem
[linux-3.10.git] / arch / x86 / kvm / x86.c
1 /*
2  * Kernel-based Virtual Machine driver for Linux
3  *
4  * derived from drivers/kvm/kvm_main.c
5  *
6  * Copyright (C) 2006 Qumranet, Inc.
7  * Copyright (C) 2008 Qumranet, Inc.
8  * Copyright IBM Corporation, 2008
9  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10  *
11  * Authors:
12  *   Avi Kivity   <avi@qumranet.com>
13  *   Yaniv Kamay  <yaniv@qumranet.com>
14  *   Amit Shah    <amit.shah@qumranet.com>
15  *   Ben-Ami Yassour <benami@il.ibm.com>
16  *
17  * This work is licensed under the terms of the GNU GPL, version 2.  See
18  * the COPYING file in the top-level directory.
19  *
20  */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30
31 #include <linux/clocksource.h>
32 #include <linux/interrupt.h>
33 #include <linux/kvm.h>
34 #include <linux/fs.h>
35 #include <linux/vmalloc.h>
36 #include <linux/module.h>
37 #include <linux/mman.h>
38 #include <linux/highmem.h>
39 #include <linux/iommu.h>
40 #include <linux/intel-iommu.h>
41 #include <linux/cpufreq.h>
42 #include <linux/user-return-notifier.h>
43 #include <linux/srcu.h>
44 #include <linux/slab.h>
45 #include <linux/perf_event.h>
46 #include <linux/uaccess.h>
47 #include <linux/hash.h>
48 #include <linux/pci.h>
49 #include <linux/timekeeper_internal.h>
50 #include <linux/pvclock_gtod.h>
51 #include <trace/events/kvm.h>
52
53 #define CREATE_TRACE_POINTS
54 #include "trace.h"
55
56 #include <asm/debugreg.h>
57 #include <asm/msr.h>
58 #include <asm/desc.h>
59 #include <asm/mtrr.h>
60 #include <asm/mce.h>
61 #include <asm/i387.h>
62 #include <asm/fpu-internal.h> /* Ugh! */
63 #include <asm/xcr.h>
64 #include <asm/pvclock.h>
65 #include <asm/div64.h>
66
67 #define MAX_IO_MSRS 256
68 #define KVM_MAX_MCE_BANKS 32
69 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
70
71 #define emul_to_vcpu(ctxt) \
72         container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
74 /* EFER defaults:
75  * - enable syscall per default because its emulated by KVM
76  * - enable LME and LMA per default on 64 bit KVM
77  */
78 #ifdef CONFIG_X86_64
79 static
80 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
81 #else
82 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
83 #endif
84
85 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
87
88 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
89 static void process_nmi(struct kvm_vcpu *vcpu);
90
91 struct kvm_x86_ops *kvm_x86_ops;
92 EXPORT_SYMBOL_GPL(kvm_x86_ops);
93
94 static bool ignore_msrs = 0;
95 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
96
97 bool kvm_has_tsc_control;
98 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
99 u32  kvm_max_guest_tsc_khz;
100 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
101
102 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
103 static u32 tsc_tolerance_ppm = 250;
104 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
105
106 #define KVM_NR_SHARED_MSRS 16
107
108 struct kvm_shared_msrs_global {
109         int nr;
110         u32 msrs[KVM_NR_SHARED_MSRS];
111 };
112
113 struct kvm_shared_msrs {
114         struct user_return_notifier urn;
115         bool registered;
116         struct kvm_shared_msr_values {
117                 u64 host;
118                 u64 curr;
119         } values[KVM_NR_SHARED_MSRS];
120 };
121
122 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
123 static struct kvm_shared_msrs __percpu *shared_msrs;
124
125 struct kvm_stats_debugfs_item debugfs_entries[] = {
126         { "pf_fixed", VCPU_STAT(pf_fixed) },
127         { "pf_guest", VCPU_STAT(pf_guest) },
128         { "tlb_flush", VCPU_STAT(tlb_flush) },
129         { "invlpg", VCPU_STAT(invlpg) },
130         { "exits", VCPU_STAT(exits) },
131         { "io_exits", VCPU_STAT(io_exits) },
132         { "mmio_exits", VCPU_STAT(mmio_exits) },
133         { "signal_exits", VCPU_STAT(signal_exits) },
134         { "irq_window", VCPU_STAT(irq_window_exits) },
135         { "nmi_window", VCPU_STAT(nmi_window_exits) },
136         { "halt_exits", VCPU_STAT(halt_exits) },
137         { "halt_wakeup", VCPU_STAT(halt_wakeup) },
138         { "hypercalls", VCPU_STAT(hypercalls) },
139         { "request_irq", VCPU_STAT(request_irq_exits) },
140         { "irq_exits", VCPU_STAT(irq_exits) },
141         { "host_state_reload", VCPU_STAT(host_state_reload) },
142         { "efer_reload", VCPU_STAT(efer_reload) },
143         { "fpu_reload", VCPU_STAT(fpu_reload) },
144         { "insn_emulation", VCPU_STAT(insn_emulation) },
145         { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
146         { "irq_injections", VCPU_STAT(irq_injections) },
147         { "nmi_injections", VCPU_STAT(nmi_injections) },
148         { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
149         { "mmu_pte_write", VM_STAT(mmu_pte_write) },
150         { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
151         { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
152         { "mmu_flooded", VM_STAT(mmu_flooded) },
153         { "mmu_recycled", VM_STAT(mmu_recycled) },
154         { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
155         { "mmu_unsync", VM_STAT(mmu_unsync) },
156         { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
157         { "largepages", VM_STAT(lpages) },
158         { NULL }
159 };
160
161 u64 __read_mostly host_xcr0;
162
163 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
164
165 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
166 {
167         int i;
168         for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
169                 vcpu->arch.apf.gfns[i] = ~0;
170 }
171
172 static void kvm_on_user_return(struct user_return_notifier *urn)
173 {
174         unsigned slot;
175         struct kvm_shared_msrs *locals
176                 = container_of(urn, struct kvm_shared_msrs, urn);
177         struct kvm_shared_msr_values *values;
178
179         for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
180                 values = &locals->values[slot];
181                 if (values->host != values->curr) {
182                         wrmsrl(shared_msrs_global.msrs[slot], values->host);
183                         values->curr = values->host;
184                 }
185         }
186         locals->registered = false;
187         user_return_notifier_unregister(urn);
188 }
189
190 static void shared_msr_update(unsigned slot, u32 msr)
191 {
192         u64 value;
193         unsigned int cpu = smp_processor_id();
194         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
195
196         /* only read, and nobody should modify it at this time,
197          * so don't need lock */
198         if (slot >= shared_msrs_global.nr) {
199                 printk(KERN_ERR "kvm: invalid MSR slot!");
200                 return;
201         }
202         rdmsrl_safe(msr, &value);
203         smsr->values[slot].host = value;
204         smsr->values[slot].curr = value;
205 }
206
207 void kvm_define_shared_msr(unsigned slot, u32 msr)
208 {
209         if (slot >= shared_msrs_global.nr)
210                 shared_msrs_global.nr = slot + 1;
211         shared_msrs_global.msrs[slot] = msr;
212         /* we need ensured the shared_msr_global have been updated */
213         smp_wmb();
214 }
215 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
216
217 static void kvm_shared_msr_cpu_online(void)
218 {
219         unsigned i;
220
221         for (i = 0; i < shared_msrs_global.nr; ++i)
222                 shared_msr_update(i, shared_msrs_global.msrs[i]);
223 }
224
225 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
226 {
227         unsigned int cpu = smp_processor_id();
228         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
229
230         if (((value ^ smsr->values[slot].curr) & mask) == 0)
231                 return;
232         smsr->values[slot].curr = value;
233         wrmsrl(shared_msrs_global.msrs[slot], value);
234         if (!smsr->registered) {
235                 smsr->urn.on_user_return = kvm_on_user_return;
236                 user_return_notifier_register(&smsr->urn);
237                 smsr->registered = true;
238         }
239 }
240 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
241
242 static void drop_user_return_notifiers(void *ignore)
243 {
244         unsigned int cpu = smp_processor_id();
245         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
246
247         if (smsr->registered)
248                 kvm_on_user_return(&smsr->urn);
249 }
250
251 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
252 {
253         return vcpu->arch.apic_base;
254 }
255 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
256
257 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
258 {
259         /* TODO: reserve bits check */
260         kvm_lapic_set_base(vcpu, data);
261 }
262 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
263
264 asmlinkage void kvm_spurious_fault(void)
265 {
266         /* Fault while not rebooting.  We want the trace. */
267         BUG();
268 }
269 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
270
271 #define EXCPT_BENIGN            0
272 #define EXCPT_CONTRIBUTORY      1
273 #define EXCPT_PF                2
274
275 static int exception_class(int vector)
276 {
277         switch (vector) {
278         case PF_VECTOR:
279                 return EXCPT_PF;
280         case DE_VECTOR:
281         case TS_VECTOR:
282         case NP_VECTOR:
283         case SS_VECTOR:
284         case GP_VECTOR:
285                 return EXCPT_CONTRIBUTORY;
286         default:
287                 break;
288         }
289         return EXCPT_BENIGN;
290 }
291
292 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
293                 unsigned nr, bool has_error, u32 error_code,
294                 bool reinject)
295 {
296         u32 prev_nr;
297         int class1, class2;
298
299         kvm_make_request(KVM_REQ_EVENT, vcpu);
300
301         if (!vcpu->arch.exception.pending) {
302         queue:
303                 vcpu->arch.exception.pending = true;
304                 vcpu->arch.exception.has_error_code = has_error;
305                 vcpu->arch.exception.nr = nr;
306                 vcpu->arch.exception.error_code = error_code;
307                 vcpu->arch.exception.reinject = reinject;
308                 return;
309         }
310
311         /* to check exception */
312         prev_nr = vcpu->arch.exception.nr;
313         if (prev_nr == DF_VECTOR) {
314                 /* triple fault -> shutdown */
315                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
316                 return;
317         }
318         class1 = exception_class(prev_nr);
319         class2 = exception_class(nr);
320         if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
321                 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
322                 /* generate double fault per SDM Table 5-5 */
323                 vcpu->arch.exception.pending = true;
324                 vcpu->arch.exception.has_error_code = true;
325                 vcpu->arch.exception.nr = DF_VECTOR;
326                 vcpu->arch.exception.error_code = 0;
327         } else
328                 /* replace previous exception with a new one in a hope
329                    that instruction re-execution will regenerate lost
330                    exception */
331                 goto queue;
332 }
333
334 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
335 {
336         kvm_multiple_exception(vcpu, nr, false, 0, false);
337 }
338 EXPORT_SYMBOL_GPL(kvm_queue_exception);
339
340 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
341 {
342         kvm_multiple_exception(vcpu, nr, false, 0, true);
343 }
344 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
345
346 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
347 {
348         if (err)
349                 kvm_inject_gp(vcpu, 0);
350         else
351                 kvm_x86_ops->skip_emulated_instruction(vcpu);
352 }
353 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
354
355 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
356 {
357         ++vcpu->stat.pf_guest;
358         vcpu->arch.cr2 = fault->address;
359         kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
360 }
361 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
362
363 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
364 {
365         if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
366                 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
367         else
368                 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
369 }
370
371 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
372 {
373         atomic_inc(&vcpu->arch.nmi_queued);
374         kvm_make_request(KVM_REQ_NMI, vcpu);
375 }
376 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
377
378 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
379 {
380         kvm_multiple_exception(vcpu, nr, true, error_code, false);
381 }
382 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
383
384 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
385 {
386         kvm_multiple_exception(vcpu, nr, true, error_code, true);
387 }
388 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
389
390 /*
391  * Checks if cpl <= required_cpl; if true, return true.  Otherwise queue
392  * a #GP and return false.
393  */
394 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
395 {
396         if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
397                 return true;
398         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
399         return false;
400 }
401 EXPORT_SYMBOL_GPL(kvm_require_cpl);
402
403 /*
404  * This function will be used to read from the physical memory of the currently
405  * running guest. The difference to kvm_read_guest_page is that this function
406  * can read from guest physical or from the guest's guest physical memory.
407  */
408 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
409                             gfn_t ngfn, void *data, int offset, int len,
410                             u32 access)
411 {
412         gfn_t real_gfn;
413         gpa_t ngpa;
414
415         ngpa     = gfn_to_gpa(ngfn);
416         real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
417         if (real_gfn == UNMAPPED_GVA)
418                 return -EFAULT;
419
420         real_gfn = gpa_to_gfn(real_gfn);
421
422         return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
423 }
424 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
425
426 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
427                                void *data, int offset, int len, u32 access)
428 {
429         return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
430                                        data, offset, len, access);
431 }
432
433 /*
434  * Load the pae pdptrs.  Return true is they are all valid.
435  */
436 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
437 {
438         gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
439         unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
440         int i;
441         int ret;
442         u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
443
444         ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
445                                       offset * sizeof(u64), sizeof(pdpte),
446                                       PFERR_USER_MASK|PFERR_WRITE_MASK);
447         if (ret < 0) {
448                 ret = 0;
449                 goto out;
450         }
451         for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
452                 if (is_present_gpte(pdpte[i]) &&
453                     (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
454                         ret = 0;
455                         goto out;
456                 }
457         }
458         ret = 1;
459
460         memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
461         __set_bit(VCPU_EXREG_PDPTR,
462                   (unsigned long *)&vcpu->arch.regs_avail);
463         __set_bit(VCPU_EXREG_PDPTR,
464                   (unsigned long *)&vcpu->arch.regs_dirty);
465 out:
466
467         return ret;
468 }
469 EXPORT_SYMBOL_GPL(load_pdptrs);
470
471 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
472 {
473         u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
474         bool changed = true;
475         int offset;
476         gfn_t gfn;
477         int r;
478
479         if (is_long_mode(vcpu) || !is_pae(vcpu))
480                 return false;
481
482         if (!test_bit(VCPU_EXREG_PDPTR,
483                       (unsigned long *)&vcpu->arch.regs_avail))
484                 return true;
485
486         gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
487         offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
488         r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
489                                        PFERR_USER_MASK | PFERR_WRITE_MASK);
490         if (r < 0)
491                 goto out;
492         changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
493 out:
494
495         return changed;
496 }
497
498 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
499 {
500         unsigned long old_cr0 = kvm_read_cr0(vcpu);
501         unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
502                                     X86_CR0_CD | X86_CR0_NW;
503
504         cr0 |= X86_CR0_ET;
505
506 #ifdef CONFIG_X86_64
507         if (cr0 & 0xffffffff00000000UL)
508                 return 1;
509 #endif
510
511         cr0 &= ~CR0_RESERVED_BITS;
512
513         if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
514                 return 1;
515
516         if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
517                 return 1;
518
519         if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
520 #ifdef CONFIG_X86_64
521                 if ((vcpu->arch.efer & EFER_LME)) {
522                         int cs_db, cs_l;
523
524                         if (!is_pae(vcpu))
525                                 return 1;
526                         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
527                         if (cs_l)
528                                 return 1;
529                 } else
530 #endif
531                 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
532                                                  kvm_read_cr3(vcpu)))
533                         return 1;
534         }
535
536         if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
537                 return 1;
538
539         kvm_x86_ops->set_cr0(vcpu, cr0);
540
541         if ((cr0 ^ old_cr0) & X86_CR0_PG) {
542                 kvm_clear_async_pf_completion_queue(vcpu);
543                 kvm_async_pf_hash_reset(vcpu);
544         }
545
546         if ((cr0 ^ old_cr0) & update_bits)
547                 kvm_mmu_reset_context(vcpu);
548         return 0;
549 }
550 EXPORT_SYMBOL_GPL(kvm_set_cr0);
551
552 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
553 {
554         (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
555 }
556 EXPORT_SYMBOL_GPL(kvm_lmsw);
557
558 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
559 {
560         if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
561                         !vcpu->guest_xcr0_loaded) {
562                 /* kvm_set_xcr() also depends on this */
563                 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
564                 vcpu->guest_xcr0_loaded = 1;
565         }
566 }
567
568 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
569 {
570         if (vcpu->guest_xcr0_loaded) {
571                 if (vcpu->arch.xcr0 != host_xcr0)
572                         xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
573                 vcpu->guest_xcr0_loaded = 0;
574         }
575 }
576
577 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
578 {
579         u64 xcr0;
580
581         /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now  */
582         if (index != XCR_XFEATURE_ENABLED_MASK)
583                 return 1;
584         xcr0 = xcr;
585         if (kvm_x86_ops->get_cpl(vcpu) != 0)
586                 return 1;
587         if (!(xcr0 & XSTATE_FP))
588                 return 1;
589         if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
590                 return 1;
591         if (xcr0 & ~host_xcr0)
592                 return 1;
593         kvm_put_guest_xcr0(vcpu);
594         vcpu->arch.xcr0 = xcr0;
595         return 0;
596 }
597
598 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
599 {
600         if (__kvm_set_xcr(vcpu, index, xcr)) {
601                 kvm_inject_gp(vcpu, 0);
602                 return 1;
603         }
604         return 0;
605 }
606 EXPORT_SYMBOL_GPL(kvm_set_xcr);
607
608 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
609 {
610         unsigned long old_cr4 = kvm_read_cr4(vcpu);
611         unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
612                                    X86_CR4_PAE | X86_CR4_SMEP;
613         if (cr4 & CR4_RESERVED_BITS)
614                 return 1;
615
616         if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
617                 return 1;
618
619         if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
620                 return 1;
621
622         if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
623                 return 1;
624
625         if (is_long_mode(vcpu)) {
626                 if (!(cr4 & X86_CR4_PAE))
627                         return 1;
628         } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
629                    && ((cr4 ^ old_cr4) & pdptr_bits)
630                    && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
631                                    kvm_read_cr3(vcpu)))
632                 return 1;
633
634         if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
635                 if (!guest_cpuid_has_pcid(vcpu))
636                         return 1;
637
638                 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
639                 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
640                         return 1;
641         }
642
643         if (kvm_x86_ops->set_cr4(vcpu, cr4))
644                 return 1;
645
646         if (((cr4 ^ old_cr4) & pdptr_bits) ||
647             (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
648                 kvm_mmu_reset_context(vcpu);
649
650         if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
651                 kvm_update_cpuid(vcpu);
652
653         return 0;
654 }
655 EXPORT_SYMBOL_GPL(kvm_set_cr4);
656
657 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
658 {
659         if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
660                 kvm_mmu_sync_roots(vcpu);
661                 kvm_mmu_flush_tlb(vcpu);
662                 return 0;
663         }
664
665         if (is_long_mode(vcpu)) {
666                 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
667                         if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
668                                 return 1;
669                 } else
670                         if (cr3 & CR3_L_MODE_RESERVED_BITS)
671                                 return 1;
672         } else {
673                 if (is_pae(vcpu)) {
674                         if (cr3 & CR3_PAE_RESERVED_BITS)
675                                 return 1;
676                         if (is_paging(vcpu) &&
677                             !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
678                                 return 1;
679                 }
680                 /*
681                  * We don't check reserved bits in nonpae mode, because
682                  * this isn't enforced, and VMware depends on this.
683                  */
684         }
685
686         /*
687          * Does the new cr3 value map to physical memory? (Note, we
688          * catch an invalid cr3 even in real-mode, because it would
689          * cause trouble later on when we turn on paging anyway.)
690          *
691          * A real CPU would silently accept an invalid cr3 and would
692          * attempt to use it - with largely undefined (and often hard
693          * to debug) behavior on the guest side.
694          */
695         if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
696                 return 1;
697         vcpu->arch.cr3 = cr3;
698         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
699         vcpu->arch.mmu.new_cr3(vcpu);
700         return 0;
701 }
702 EXPORT_SYMBOL_GPL(kvm_set_cr3);
703
704 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
705 {
706         if (cr8 & CR8_RESERVED_BITS)
707                 return 1;
708         if (irqchip_in_kernel(vcpu->kvm))
709                 kvm_lapic_set_tpr(vcpu, cr8);
710         else
711                 vcpu->arch.cr8 = cr8;
712         return 0;
713 }
714 EXPORT_SYMBOL_GPL(kvm_set_cr8);
715
716 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
717 {
718         if (irqchip_in_kernel(vcpu->kvm))
719                 return kvm_lapic_get_cr8(vcpu);
720         else
721                 return vcpu->arch.cr8;
722 }
723 EXPORT_SYMBOL_GPL(kvm_get_cr8);
724
725 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
726 {
727         unsigned long dr7;
728
729         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
730                 dr7 = vcpu->arch.guest_debug_dr7;
731         else
732                 dr7 = vcpu->arch.dr7;
733         kvm_x86_ops->set_dr7(vcpu, dr7);
734         vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
735 }
736
737 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
738 {
739         switch (dr) {
740         case 0 ... 3:
741                 vcpu->arch.db[dr] = val;
742                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
743                         vcpu->arch.eff_db[dr] = val;
744                 break;
745         case 4:
746                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
747                         return 1; /* #UD */
748                 /* fall through */
749         case 6:
750                 if (val & 0xffffffff00000000ULL)
751                         return -1; /* #GP */
752                 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
753                 break;
754         case 5:
755                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
756                         return 1; /* #UD */
757                 /* fall through */
758         default: /* 7 */
759                 if (val & 0xffffffff00000000ULL)
760                         return -1; /* #GP */
761                 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
762                 kvm_update_dr7(vcpu);
763                 break;
764         }
765
766         return 0;
767 }
768
769 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
770 {
771         int res;
772
773         res = __kvm_set_dr(vcpu, dr, val);
774         if (res > 0)
775                 kvm_queue_exception(vcpu, UD_VECTOR);
776         else if (res < 0)
777                 kvm_inject_gp(vcpu, 0);
778
779         return res;
780 }
781 EXPORT_SYMBOL_GPL(kvm_set_dr);
782
783 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
784 {
785         switch (dr) {
786         case 0 ... 3:
787                 *val = vcpu->arch.db[dr];
788                 break;
789         case 4:
790                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
791                         return 1;
792                 /* fall through */
793         case 6:
794                 *val = vcpu->arch.dr6;
795                 break;
796         case 5:
797                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
798                         return 1;
799                 /* fall through */
800         default: /* 7 */
801                 *val = vcpu->arch.dr7;
802                 break;
803         }
804
805         return 0;
806 }
807
808 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
809 {
810         if (_kvm_get_dr(vcpu, dr, val)) {
811                 kvm_queue_exception(vcpu, UD_VECTOR);
812                 return 1;
813         }
814         return 0;
815 }
816 EXPORT_SYMBOL_GPL(kvm_get_dr);
817
818 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
819 {
820         u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
821         u64 data;
822         int err;
823
824         err = kvm_pmu_read_pmc(vcpu, ecx, &data);
825         if (err)
826                 return err;
827         kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
828         kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
829         return err;
830 }
831 EXPORT_SYMBOL_GPL(kvm_rdpmc);
832
833 /*
834  * List of msr numbers which we expose to userspace through KVM_GET_MSRS
835  * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
836  *
837  * This list is modified at module load time to reflect the
838  * capabilities of the host cpu. This capabilities test skips MSRs that are
839  * kvm-specific. Those are put in the beginning of the list.
840  */
841
842 #define KVM_SAVE_MSRS_BEGIN     10
843 static u32 msrs_to_save[] = {
844         MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
845         MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
846         HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
847         HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
848         MSR_KVM_PV_EOI_EN,
849         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
850         MSR_STAR,
851 #ifdef CONFIG_X86_64
852         MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
853 #endif
854         MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
855 };
856
857 static unsigned num_msrs_to_save;
858
859 static const u32 emulated_msrs[] = {
860         MSR_IA32_TSC_ADJUST,
861         MSR_IA32_TSCDEADLINE,
862         MSR_IA32_MISC_ENABLE,
863         MSR_IA32_MCG_STATUS,
864         MSR_IA32_MCG_CTL,
865 };
866
867 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
868 {
869         if (efer & efer_reserved_bits)
870                 return false;
871
872         if (efer & EFER_FFXSR) {
873                 struct kvm_cpuid_entry2 *feat;
874
875                 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
876                 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
877                         return false;
878         }
879
880         if (efer & EFER_SVME) {
881                 struct kvm_cpuid_entry2 *feat;
882
883                 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
884                 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
885                         return false;
886         }
887
888         return true;
889 }
890 EXPORT_SYMBOL_GPL(kvm_valid_efer);
891
892 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
893 {
894         u64 old_efer = vcpu->arch.efer;
895
896         if (!kvm_valid_efer(vcpu, efer))
897                 return 1;
898
899         if (is_paging(vcpu)
900             && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
901                 return 1;
902
903         efer &= ~EFER_LMA;
904         efer |= vcpu->arch.efer & EFER_LMA;
905
906         kvm_x86_ops->set_efer(vcpu, efer);
907
908         /* Update reserved bits */
909         if ((efer ^ old_efer) & EFER_NX)
910                 kvm_mmu_reset_context(vcpu);
911
912         return 0;
913 }
914
915 void kvm_enable_efer_bits(u64 mask)
916 {
917        efer_reserved_bits &= ~mask;
918 }
919 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
920
921
922 /*
923  * Writes msr value into into the appropriate "register".
924  * Returns 0 on success, non-0 otherwise.
925  * Assumes vcpu_load() was already called.
926  */
927 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
928 {
929         return kvm_x86_ops->set_msr(vcpu, msr);
930 }
931
932 /*
933  * Adapt set_msr() to msr_io()'s calling convention
934  */
935 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
936 {
937         struct msr_data msr;
938
939         msr.data = *data;
940         msr.index = index;
941         msr.host_initiated = true;
942         return kvm_set_msr(vcpu, &msr);
943 }
944
945 #ifdef CONFIG_X86_64
946 struct pvclock_gtod_data {
947         seqcount_t      seq;
948
949         struct { /* extract of a clocksource struct */
950                 int vclock_mode;
951                 cycle_t cycle_last;
952                 cycle_t mask;
953                 u32     mult;
954                 u32     shift;
955         } clock;
956
957         /* open coded 'struct timespec' */
958         u64             monotonic_time_snsec;
959         time_t          monotonic_time_sec;
960 };
961
962 static struct pvclock_gtod_data pvclock_gtod_data;
963
964 static void update_pvclock_gtod(struct timekeeper *tk)
965 {
966         struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
967
968         write_seqcount_begin(&vdata->seq);
969
970         /* copy pvclock gtod data */
971         vdata->clock.vclock_mode        = tk->clock->archdata.vclock_mode;
972         vdata->clock.cycle_last         = tk->clock->cycle_last;
973         vdata->clock.mask               = tk->clock->mask;
974         vdata->clock.mult               = tk->mult;
975         vdata->clock.shift              = tk->shift;
976
977         vdata->monotonic_time_sec       = tk->xtime_sec
978                                         + tk->wall_to_monotonic.tv_sec;
979         vdata->monotonic_time_snsec     = tk->xtime_nsec
980                                         + (tk->wall_to_monotonic.tv_nsec
981                                                 << tk->shift);
982         while (vdata->monotonic_time_snsec >=
983                                         (((u64)NSEC_PER_SEC) << tk->shift)) {
984                 vdata->monotonic_time_snsec -=
985                                         ((u64)NSEC_PER_SEC) << tk->shift;
986                 vdata->monotonic_time_sec++;
987         }
988
989         write_seqcount_end(&vdata->seq);
990 }
991 #endif
992
993
994 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
995 {
996         int version;
997         int r;
998         struct pvclock_wall_clock wc;
999         struct timespec boot;
1000
1001         if (!wall_clock)
1002                 return;
1003
1004         r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1005         if (r)
1006                 return;
1007
1008         if (version & 1)
1009                 ++version;  /* first time write, random junk */
1010
1011         ++version;
1012
1013         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1014
1015         /*
1016          * The guest calculates current wall clock time by adding
1017          * system time (updated by kvm_guest_time_update below) to the
1018          * wall clock specified here.  guest system time equals host
1019          * system time for us, thus we must fill in host boot time here.
1020          */
1021         getboottime(&boot);
1022
1023         if (kvm->arch.kvmclock_offset) {
1024                 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1025                 boot = timespec_sub(boot, ts);
1026         }
1027         wc.sec = boot.tv_sec;
1028         wc.nsec = boot.tv_nsec;
1029         wc.version = version;
1030
1031         kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1032
1033         version++;
1034         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1035 }
1036
1037 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1038 {
1039         uint32_t quotient, remainder;
1040
1041         /* Don't try to replace with do_div(), this one calculates
1042          * "(dividend << 32) / divisor" */
1043         __asm__ ( "divl %4"
1044                   : "=a" (quotient), "=d" (remainder)
1045                   : "0" (0), "1" (dividend), "r" (divisor) );
1046         return quotient;
1047 }
1048
1049 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1050                                s8 *pshift, u32 *pmultiplier)
1051 {
1052         uint64_t scaled64;
1053         int32_t  shift = 0;
1054         uint64_t tps64;
1055         uint32_t tps32;
1056
1057         tps64 = base_khz * 1000LL;
1058         scaled64 = scaled_khz * 1000LL;
1059         while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1060                 tps64 >>= 1;
1061                 shift--;
1062         }
1063
1064         tps32 = (uint32_t)tps64;
1065         while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1066                 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1067                         scaled64 >>= 1;
1068                 else
1069                         tps32 <<= 1;
1070                 shift++;
1071         }
1072
1073         *pshift = shift;
1074         *pmultiplier = div_frac(scaled64, tps32);
1075
1076         pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1077                  __func__, base_khz, scaled_khz, shift, *pmultiplier);
1078 }
1079
1080 static inline u64 get_kernel_ns(void)
1081 {
1082         struct timespec ts;
1083
1084         WARN_ON(preemptible());
1085         ktime_get_ts(&ts);
1086         monotonic_to_bootbased(&ts);
1087         return timespec_to_ns(&ts);
1088 }
1089
1090 #ifdef CONFIG_X86_64
1091 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1092 #endif
1093
1094 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1095 unsigned long max_tsc_khz;
1096
1097 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1098 {
1099         return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1100                                    vcpu->arch.virtual_tsc_shift);
1101 }
1102
1103 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1104 {
1105         u64 v = (u64)khz * (1000000 + ppm);
1106         do_div(v, 1000000);
1107         return v;
1108 }
1109
1110 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1111 {
1112         u32 thresh_lo, thresh_hi;
1113         int use_scaling = 0;
1114
1115         /* tsc_khz can be zero if TSC calibration fails */
1116         if (this_tsc_khz == 0)
1117                 return;
1118
1119         /* Compute a scale to convert nanoseconds in TSC cycles */
1120         kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1121                            &vcpu->arch.virtual_tsc_shift,
1122                            &vcpu->arch.virtual_tsc_mult);
1123         vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1124
1125         /*
1126          * Compute the variation in TSC rate which is acceptable
1127          * within the range of tolerance and decide if the
1128          * rate being applied is within that bounds of the hardware
1129          * rate.  If so, no scaling or compensation need be done.
1130          */
1131         thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1132         thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1133         if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1134                 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1135                 use_scaling = 1;
1136         }
1137         kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1138 }
1139
1140 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1141 {
1142         u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1143                                       vcpu->arch.virtual_tsc_mult,
1144                                       vcpu->arch.virtual_tsc_shift);
1145         tsc += vcpu->arch.this_tsc_write;
1146         return tsc;
1147 }
1148
1149 void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1150 {
1151 #ifdef CONFIG_X86_64
1152         bool vcpus_matched;
1153         bool do_request = false;
1154         struct kvm_arch *ka = &vcpu->kvm->arch;
1155         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1156
1157         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1158                          atomic_read(&vcpu->kvm->online_vcpus));
1159
1160         if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1161                 if (!ka->use_master_clock)
1162                         do_request = 1;
1163
1164         if (!vcpus_matched && ka->use_master_clock)
1165                         do_request = 1;
1166
1167         if (do_request)
1168                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1169
1170         trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1171                             atomic_read(&vcpu->kvm->online_vcpus),
1172                             ka->use_master_clock, gtod->clock.vclock_mode);
1173 #endif
1174 }
1175
1176 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1177 {
1178         u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1179         vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1180 }
1181
1182 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1183 {
1184         struct kvm *kvm = vcpu->kvm;
1185         u64 offset, ns, elapsed;
1186         unsigned long flags;
1187         s64 usdiff;
1188         bool matched;
1189         u64 data = msr->data;
1190
1191         raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1192         offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1193         ns = get_kernel_ns();
1194         elapsed = ns - kvm->arch.last_tsc_nsec;
1195
1196         if (vcpu->arch.virtual_tsc_khz) {
1197                 /* n.b - signed multiplication and division required */
1198                 usdiff = data - kvm->arch.last_tsc_write;
1199 #ifdef CONFIG_X86_64
1200                 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1201 #else
1202                 /* do_div() only does unsigned */
1203                 asm("idivl %2; xor %%edx, %%edx"
1204                 : "=A"(usdiff)
1205                 : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
1206 #endif
1207                 do_div(elapsed, 1000);
1208                 usdiff -= elapsed;
1209                 if (usdiff < 0)
1210                         usdiff = -usdiff;
1211         } else
1212                 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1213
1214         /*
1215          * Special case: TSC write with a small delta (1 second) of virtual
1216          * cycle time against real time is interpreted as an attempt to
1217          * synchronize the CPU.
1218          *
1219          * For a reliable TSC, we can match TSC offsets, and for an unstable
1220          * TSC, we add elapsed time in this computation.  We could let the
1221          * compensation code attempt to catch up if we fall behind, but
1222          * it's better to try to match offsets from the beginning.
1223          */
1224         if (usdiff < USEC_PER_SEC &&
1225             vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1226                 if (!check_tsc_unstable()) {
1227                         offset = kvm->arch.cur_tsc_offset;
1228                         pr_debug("kvm: matched tsc offset for %llu\n", data);
1229                 } else {
1230                         u64 delta = nsec_to_cycles(vcpu, elapsed);
1231                         data += delta;
1232                         offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1233                         pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1234                 }
1235                 matched = true;
1236         } else {
1237                 /*
1238                  * We split periods of matched TSC writes into generations.
1239                  * For each generation, we track the original measured
1240                  * nanosecond time, offset, and write, so if TSCs are in
1241                  * sync, we can match exact offset, and if not, we can match
1242                  * exact software computation in compute_guest_tsc()
1243                  *
1244                  * These values are tracked in kvm->arch.cur_xxx variables.
1245                  */
1246                 kvm->arch.cur_tsc_generation++;
1247                 kvm->arch.cur_tsc_nsec = ns;
1248                 kvm->arch.cur_tsc_write = data;
1249                 kvm->arch.cur_tsc_offset = offset;
1250                 matched = false;
1251                 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1252                          kvm->arch.cur_tsc_generation, data);
1253         }
1254
1255         /*
1256          * We also track th most recent recorded KHZ, write and time to
1257          * allow the matching interval to be extended at each write.
1258          */
1259         kvm->arch.last_tsc_nsec = ns;
1260         kvm->arch.last_tsc_write = data;
1261         kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1262
1263         /* Reset of TSC must disable overshoot protection below */
1264         vcpu->arch.hv_clock.tsc_timestamp = 0;
1265         vcpu->arch.last_guest_tsc = data;
1266
1267         /* Keep track of which generation this VCPU has synchronized to */
1268         vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1269         vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1270         vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1271
1272         if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1273                 update_ia32_tsc_adjust_msr(vcpu, offset);
1274         kvm_x86_ops->write_tsc_offset(vcpu, offset);
1275         raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1276
1277         spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1278         if (matched)
1279                 kvm->arch.nr_vcpus_matched_tsc++;
1280         else
1281                 kvm->arch.nr_vcpus_matched_tsc = 0;
1282
1283         kvm_track_tsc_matching(vcpu);
1284         spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1285 }
1286
1287 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1288
1289 #ifdef CONFIG_X86_64
1290
1291 static cycle_t read_tsc(void)
1292 {
1293         cycle_t ret;
1294         u64 last;
1295
1296         /*
1297          * Empirically, a fence (of type that depends on the CPU)
1298          * before rdtsc is enough to ensure that rdtsc is ordered
1299          * with respect to loads.  The various CPU manuals are unclear
1300          * as to whether rdtsc can be reordered with later loads,
1301          * but no one has ever seen it happen.
1302          */
1303         rdtsc_barrier();
1304         ret = (cycle_t)vget_cycles();
1305
1306         last = pvclock_gtod_data.clock.cycle_last;
1307
1308         if (likely(ret >= last))
1309                 return ret;
1310
1311         /*
1312          * GCC likes to generate cmov here, but this branch is extremely
1313          * predictable (it's just a funciton of time and the likely is
1314          * very likely) and there's a data dependence, so force GCC
1315          * to generate a branch instead.  I don't barrier() because
1316          * we don't actually need a barrier, and if this function
1317          * ever gets inlined it will generate worse code.
1318          */
1319         asm volatile ("");
1320         return last;
1321 }
1322
1323 static inline u64 vgettsc(cycle_t *cycle_now)
1324 {
1325         long v;
1326         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1327
1328         *cycle_now = read_tsc();
1329
1330         v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1331         return v * gtod->clock.mult;
1332 }
1333
1334 static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1335 {
1336         unsigned long seq;
1337         u64 ns;
1338         int mode;
1339         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1340
1341         ts->tv_nsec = 0;
1342         do {
1343                 seq = read_seqcount_begin(&gtod->seq);
1344                 mode = gtod->clock.vclock_mode;
1345                 ts->tv_sec = gtod->monotonic_time_sec;
1346                 ns = gtod->monotonic_time_snsec;
1347                 ns += vgettsc(cycle_now);
1348                 ns >>= gtod->clock.shift;
1349         } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1350         timespec_add_ns(ts, ns);
1351
1352         return mode;
1353 }
1354
1355 /* returns true if host is using tsc clocksource */
1356 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1357 {
1358         struct timespec ts;
1359
1360         /* checked again under seqlock below */
1361         if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1362                 return false;
1363
1364         if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1365                 return false;
1366
1367         monotonic_to_bootbased(&ts);
1368         *kernel_ns = timespec_to_ns(&ts);
1369
1370         return true;
1371 }
1372 #endif
1373
1374 /*
1375  *
1376  * Assuming a stable TSC across physical CPUS, and a stable TSC
1377  * across virtual CPUs, the following condition is possible.
1378  * Each numbered line represents an event visible to both
1379  * CPUs at the next numbered event.
1380  *
1381  * "timespecX" represents host monotonic time. "tscX" represents
1382  * RDTSC value.
1383  *
1384  *              VCPU0 on CPU0           |       VCPU1 on CPU1
1385  *
1386  * 1.  read timespec0,tsc0
1387  * 2.                                   | timespec1 = timespec0 + N
1388  *                                      | tsc1 = tsc0 + M
1389  * 3. transition to guest               | transition to guest
1390  * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1391  * 5.                                   | ret1 = timespec1 + (rdtsc - tsc1)
1392  *                                      | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1393  *
1394  * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1395  *
1396  *      - ret0 < ret1
1397  *      - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1398  *              ...
1399  *      - 0 < N - M => M < N
1400  *
1401  * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1402  * always the case (the difference between two distinct xtime instances
1403  * might be smaller then the difference between corresponding TSC reads,
1404  * when updating guest vcpus pvclock areas).
1405  *
1406  * To avoid that problem, do not allow visibility of distinct
1407  * system_timestamp/tsc_timestamp values simultaneously: use a master
1408  * copy of host monotonic time values. Update that master copy
1409  * in lockstep.
1410  *
1411  * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1412  *
1413  */
1414
1415 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1416 {
1417 #ifdef CONFIG_X86_64
1418         struct kvm_arch *ka = &kvm->arch;
1419         int vclock_mode;
1420         bool host_tsc_clocksource, vcpus_matched;
1421
1422         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1423                         atomic_read(&kvm->online_vcpus));
1424
1425         /*
1426          * If the host uses TSC clock, then passthrough TSC as stable
1427          * to the guest.
1428          */
1429         host_tsc_clocksource = kvm_get_time_and_clockread(
1430                                         &ka->master_kernel_ns,
1431                                         &ka->master_cycle_now);
1432
1433         ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1434
1435         if (ka->use_master_clock)
1436                 atomic_set(&kvm_guest_has_master_clock, 1);
1437
1438         vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1439         trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1440                                         vcpus_matched);
1441 #endif
1442 }
1443
1444 static int kvm_guest_time_update(struct kvm_vcpu *v)
1445 {
1446         unsigned long flags, this_tsc_khz;
1447         struct kvm_vcpu_arch *vcpu = &v->arch;
1448         struct kvm_arch *ka = &v->kvm->arch;
1449         s64 kernel_ns, max_kernel_ns;
1450         u64 tsc_timestamp, host_tsc;
1451         struct pvclock_vcpu_time_info guest_hv_clock;
1452         u8 pvclock_flags;
1453         bool use_master_clock;
1454
1455         kernel_ns = 0;
1456         host_tsc = 0;
1457
1458         /*
1459          * If the host uses TSC clock, then passthrough TSC as stable
1460          * to the guest.
1461          */
1462         spin_lock(&ka->pvclock_gtod_sync_lock);
1463         use_master_clock = ka->use_master_clock;
1464         if (use_master_clock) {
1465                 host_tsc = ka->master_cycle_now;
1466                 kernel_ns = ka->master_kernel_ns;
1467         }
1468         spin_unlock(&ka->pvclock_gtod_sync_lock);
1469
1470         /* Keep irq disabled to prevent changes to the clock */
1471         local_irq_save(flags);
1472         this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1473         if (unlikely(this_tsc_khz == 0)) {
1474                 local_irq_restore(flags);
1475                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1476                 return 1;
1477         }
1478         if (!use_master_clock) {
1479                 host_tsc = native_read_tsc();
1480                 kernel_ns = get_kernel_ns();
1481         }
1482
1483         tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1484
1485         /*
1486          * We may have to catch up the TSC to match elapsed wall clock
1487          * time for two reasons, even if kvmclock is used.
1488          *   1) CPU could have been running below the maximum TSC rate
1489          *   2) Broken TSC compensation resets the base at each VCPU
1490          *      entry to avoid unknown leaps of TSC even when running
1491          *      again on the same CPU.  This may cause apparent elapsed
1492          *      time to disappear, and the guest to stand still or run
1493          *      very slowly.
1494          */
1495         if (vcpu->tsc_catchup) {
1496                 u64 tsc = compute_guest_tsc(v, kernel_ns);
1497                 if (tsc > tsc_timestamp) {
1498                         adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1499                         tsc_timestamp = tsc;
1500                 }
1501         }
1502
1503         local_irq_restore(flags);
1504
1505         if (!vcpu->pv_time_enabled)
1506                 return 0;
1507
1508         /*
1509          * Time as measured by the TSC may go backwards when resetting the base
1510          * tsc_timestamp.  The reason for this is that the TSC resolution is
1511          * higher than the resolution of the other clock scales.  Thus, many
1512          * possible measurments of the TSC correspond to one measurement of any
1513          * other clock, and so a spread of values is possible.  This is not a
1514          * problem for the computation of the nanosecond clock; with TSC rates
1515          * around 1GHZ, there can only be a few cycles which correspond to one
1516          * nanosecond value, and any path through this code will inevitably
1517          * take longer than that.  However, with the kernel_ns value itself,
1518          * the precision may be much lower, down to HZ granularity.  If the
1519          * first sampling of TSC against kernel_ns ends in the low part of the
1520          * range, and the second in the high end of the range, we can get:
1521          *
1522          * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1523          *
1524          * As the sampling errors potentially range in the thousands of cycles,
1525          * it is possible such a time value has already been observed by the
1526          * guest.  To protect against this, we must compute the system time as
1527          * observed by the guest and ensure the new system time is greater.
1528          */
1529         max_kernel_ns = 0;
1530         if (vcpu->hv_clock.tsc_timestamp) {
1531                 max_kernel_ns = vcpu->last_guest_tsc -
1532                                 vcpu->hv_clock.tsc_timestamp;
1533                 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1534                                     vcpu->hv_clock.tsc_to_system_mul,
1535                                     vcpu->hv_clock.tsc_shift);
1536                 max_kernel_ns += vcpu->last_kernel_ns;
1537         }
1538
1539         if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1540                 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1541                                    &vcpu->hv_clock.tsc_shift,
1542                                    &vcpu->hv_clock.tsc_to_system_mul);
1543                 vcpu->hw_tsc_khz = this_tsc_khz;
1544         }
1545
1546         /* with a master <monotonic time, tsc value> tuple,
1547          * pvclock clock reads always increase at the (scaled) rate
1548          * of guest TSC - no need to deal with sampling errors.
1549          */
1550         if (!use_master_clock) {
1551                 if (max_kernel_ns > kernel_ns)
1552                         kernel_ns = max_kernel_ns;
1553         }
1554         /* With all the info we got, fill in the values */
1555         vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1556         vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1557         vcpu->last_kernel_ns = kernel_ns;
1558         vcpu->last_guest_tsc = tsc_timestamp;
1559
1560         /*
1561          * The interface expects us to write an even number signaling that the
1562          * update is finished. Since the guest won't see the intermediate
1563          * state, we just increase by 2 at the end.
1564          */
1565         vcpu->hv_clock.version += 2;
1566
1567         if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1568                 &guest_hv_clock, sizeof(guest_hv_clock))))
1569                 return 0;
1570
1571         /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1572         pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1573
1574         if (vcpu->pvclock_set_guest_stopped_request) {
1575                 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1576                 vcpu->pvclock_set_guest_stopped_request = false;
1577         }
1578
1579         /* If the host uses TSC clocksource, then it is stable */
1580         if (use_master_clock)
1581                 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1582
1583         vcpu->hv_clock.flags = pvclock_flags;
1584
1585         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1586                                 &vcpu->hv_clock,
1587                                 sizeof(vcpu->hv_clock));
1588         return 0;
1589 }
1590
1591 static bool msr_mtrr_valid(unsigned msr)
1592 {
1593         switch (msr) {
1594         case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1595         case MSR_MTRRfix64K_00000:
1596         case MSR_MTRRfix16K_80000:
1597         case MSR_MTRRfix16K_A0000:
1598         case MSR_MTRRfix4K_C0000:
1599         case MSR_MTRRfix4K_C8000:
1600         case MSR_MTRRfix4K_D0000:
1601         case MSR_MTRRfix4K_D8000:
1602         case MSR_MTRRfix4K_E0000:
1603         case MSR_MTRRfix4K_E8000:
1604         case MSR_MTRRfix4K_F0000:
1605         case MSR_MTRRfix4K_F8000:
1606         case MSR_MTRRdefType:
1607         case MSR_IA32_CR_PAT:
1608                 return true;
1609         case 0x2f8:
1610                 return true;
1611         }
1612         return false;
1613 }
1614
1615 static bool valid_pat_type(unsigned t)
1616 {
1617         return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1618 }
1619
1620 static bool valid_mtrr_type(unsigned t)
1621 {
1622         return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1623 }
1624
1625 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1626 {
1627         int i;
1628
1629         if (!msr_mtrr_valid(msr))
1630                 return false;
1631
1632         if (msr == MSR_IA32_CR_PAT) {
1633                 for (i = 0; i < 8; i++)
1634                         if (!valid_pat_type((data >> (i * 8)) & 0xff))
1635                                 return false;
1636                 return true;
1637         } else if (msr == MSR_MTRRdefType) {
1638                 if (data & ~0xcff)
1639                         return false;
1640                 return valid_mtrr_type(data & 0xff);
1641         } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1642                 for (i = 0; i < 8 ; i++)
1643                         if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1644                                 return false;
1645                 return true;
1646         }
1647
1648         /* variable MTRRs */
1649         return valid_mtrr_type(data & 0xff);
1650 }
1651
1652 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1653 {
1654         u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1655
1656         if (!mtrr_valid(vcpu, msr, data))
1657                 return 1;
1658
1659         if (msr == MSR_MTRRdefType) {
1660                 vcpu->arch.mtrr_state.def_type = data;
1661                 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1662         } else if (msr == MSR_MTRRfix64K_00000)
1663                 p[0] = data;
1664         else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1665                 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1666         else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1667                 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1668         else if (msr == MSR_IA32_CR_PAT)
1669                 vcpu->arch.pat = data;
1670         else {  /* Variable MTRRs */
1671                 int idx, is_mtrr_mask;
1672                 u64 *pt;
1673
1674                 idx = (msr - 0x200) / 2;
1675                 is_mtrr_mask = msr - 0x200 - 2 * idx;
1676                 if (!is_mtrr_mask)
1677                         pt =
1678                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1679                 else
1680                         pt =
1681                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1682                 *pt = data;
1683         }
1684
1685         kvm_mmu_reset_context(vcpu);
1686         return 0;
1687 }
1688
1689 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1690 {
1691         u64 mcg_cap = vcpu->arch.mcg_cap;
1692         unsigned bank_num = mcg_cap & 0xff;
1693
1694         switch (msr) {
1695         case MSR_IA32_MCG_STATUS:
1696                 vcpu->arch.mcg_status = data;
1697                 break;
1698         case MSR_IA32_MCG_CTL:
1699                 if (!(mcg_cap & MCG_CTL_P))
1700                         return 1;
1701                 if (data != 0 && data != ~(u64)0)
1702                         return -1;
1703                 vcpu->arch.mcg_ctl = data;
1704                 break;
1705         default:
1706                 if (msr >= MSR_IA32_MC0_CTL &&
1707                     msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1708                         u32 offset = msr - MSR_IA32_MC0_CTL;
1709                         /* only 0 or all 1s can be written to IA32_MCi_CTL
1710                          * some Linux kernels though clear bit 10 in bank 4 to
1711                          * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1712                          * this to avoid an uncatched #GP in the guest
1713                          */
1714                         if ((offset & 0x3) == 0 &&
1715                             data != 0 && (data | (1 << 10)) != ~(u64)0)
1716                                 return -1;
1717                         vcpu->arch.mce_banks[offset] = data;
1718                         break;
1719                 }
1720                 return 1;
1721         }
1722         return 0;
1723 }
1724
1725 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1726 {
1727         struct kvm *kvm = vcpu->kvm;
1728         int lm = is_long_mode(vcpu);
1729         u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1730                 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1731         u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1732                 : kvm->arch.xen_hvm_config.blob_size_32;
1733         u32 page_num = data & ~PAGE_MASK;
1734         u64 page_addr = data & PAGE_MASK;
1735         u8 *page;
1736         int r;
1737
1738         r = -E2BIG;
1739         if (page_num >= blob_size)
1740                 goto out;
1741         r = -ENOMEM;
1742         page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1743         if (IS_ERR(page)) {
1744                 r = PTR_ERR(page);
1745                 goto out;
1746         }
1747         if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1748                 goto out_free;
1749         r = 0;
1750 out_free:
1751         kfree(page);
1752 out:
1753         return r;
1754 }
1755
1756 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1757 {
1758         return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1759 }
1760
1761 static bool kvm_hv_msr_partition_wide(u32 msr)
1762 {
1763         bool r = false;
1764         switch (msr) {
1765         case HV_X64_MSR_GUEST_OS_ID:
1766         case HV_X64_MSR_HYPERCALL:
1767                 r = true;
1768                 break;
1769         }
1770
1771         return r;
1772 }
1773
1774 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1775 {
1776         struct kvm *kvm = vcpu->kvm;
1777
1778         switch (msr) {
1779         case HV_X64_MSR_GUEST_OS_ID:
1780                 kvm->arch.hv_guest_os_id = data;
1781                 /* setting guest os id to zero disables hypercall page */
1782                 if (!kvm->arch.hv_guest_os_id)
1783                         kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1784                 break;
1785         case HV_X64_MSR_HYPERCALL: {
1786                 u64 gfn;
1787                 unsigned long addr;
1788                 u8 instructions[4];
1789
1790                 /* if guest os id is not set hypercall should remain disabled */
1791                 if (!kvm->arch.hv_guest_os_id)
1792                         break;
1793                 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1794                         kvm->arch.hv_hypercall = data;
1795                         break;
1796                 }
1797                 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1798                 addr = gfn_to_hva(kvm, gfn);
1799                 if (kvm_is_error_hva(addr))
1800                         return 1;
1801                 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1802                 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1803                 if (__copy_to_user((void __user *)addr, instructions, 4))
1804                         return 1;
1805                 kvm->arch.hv_hypercall = data;
1806                 break;
1807         }
1808         default:
1809                 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1810                             "data 0x%llx\n", msr, data);
1811                 return 1;
1812         }
1813         return 0;
1814 }
1815
1816 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1817 {
1818         switch (msr) {
1819         case HV_X64_MSR_APIC_ASSIST_PAGE: {
1820                 unsigned long addr;
1821
1822                 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1823                         vcpu->arch.hv_vapic = data;
1824                         break;
1825                 }
1826                 addr = gfn_to_hva(vcpu->kvm, data >>
1827                                   HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1828                 if (kvm_is_error_hva(addr))
1829                         return 1;
1830                 if (__clear_user((void __user *)addr, PAGE_SIZE))
1831                         return 1;
1832                 vcpu->arch.hv_vapic = data;
1833                 break;
1834         }
1835         case HV_X64_MSR_EOI:
1836                 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1837         case HV_X64_MSR_ICR:
1838                 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1839         case HV_X64_MSR_TPR:
1840                 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1841         default:
1842                 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1843                             "data 0x%llx\n", msr, data);
1844                 return 1;
1845         }
1846
1847         return 0;
1848 }
1849
1850 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1851 {
1852         gpa_t gpa = data & ~0x3f;
1853
1854         /* Bits 2:5 are reserved, Should be zero */
1855         if (data & 0x3c)
1856                 return 1;
1857
1858         vcpu->arch.apf.msr_val = data;
1859
1860         if (!(data & KVM_ASYNC_PF_ENABLED)) {
1861                 kvm_clear_async_pf_completion_queue(vcpu);
1862                 kvm_async_pf_hash_reset(vcpu);
1863                 return 0;
1864         }
1865
1866         if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1867                                         sizeof(u32)))
1868                 return 1;
1869
1870         vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1871         kvm_async_pf_wakeup_all(vcpu);
1872         return 0;
1873 }
1874
1875 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1876 {
1877         vcpu->arch.pv_time_enabled = false;
1878 }
1879
1880 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1881 {
1882         u64 delta;
1883
1884         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1885                 return;
1886
1887         delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1888         vcpu->arch.st.last_steal = current->sched_info.run_delay;
1889         vcpu->arch.st.accum_steal = delta;
1890 }
1891
1892 static void record_steal_time(struct kvm_vcpu *vcpu)
1893 {
1894         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1895                 return;
1896
1897         if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1898                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1899                 return;
1900
1901         vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1902         vcpu->arch.st.steal.version += 2;
1903         vcpu->arch.st.accum_steal = 0;
1904
1905         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1906                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1907 }
1908
1909 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1910 {
1911         bool pr = false;
1912         u32 msr = msr_info->index;
1913         u64 data = msr_info->data;
1914
1915         switch (msr) {
1916         case MSR_AMD64_NB_CFG:
1917         case MSR_IA32_UCODE_REV:
1918         case MSR_IA32_UCODE_WRITE:
1919         case MSR_VM_HSAVE_PA:
1920         case MSR_AMD64_PATCH_LOADER:
1921         case MSR_AMD64_BU_CFG2:
1922                 break;
1923
1924         case MSR_EFER:
1925                 return set_efer(vcpu, data);
1926         case MSR_K7_HWCR:
1927                 data &= ~(u64)0x40;     /* ignore flush filter disable */
1928                 data &= ~(u64)0x100;    /* ignore ignne emulation enable */
1929                 data &= ~(u64)0x8;      /* ignore TLB cache disable */
1930                 if (data != 0) {
1931                         vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1932                                     data);
1933                         return 1;
1934                 }
1935                 break;
1936         case MSR_FAM10H_MMIO_CONF_BASE:
1937                 if (data != 0) {
1938                         vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1939                                     "0x%llx\n", data);
1940                         return 1;
1941                 }
1942                 break;
1943         case MSR_IA32_DEBUGCTLMSR:
1944                 if (!data) {
1945                         /* We support the non-activated case already */
1946                         break;
1947                 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1948                         /* Values other than LBR and BTF are vendor-specific,
1949                            thus reserved and should throw a #GP */
1950                         return 1;
1951                 }
1952                 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1953                             __func__, data);
1954                 break;
1955         case 0x200 ... 0x2ff:
1956                 return set_msr_mtrr(vcpu, msr, data);
1957         case MSR_IA32_APICBASE:
1958                 kvm_set_apic_base(vcpu, data);
1959                 break;
1960         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1961                 return kvm_x2apic_msr_write(vcpu, msr, data);
1962         case MSR_IA32_TSCDEADLINE:
1963                 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1964                 break;
1965         case MSR_IA32_TSC_ADJUST:
1966                 if (guest_cpuid_has_tsc_adjust(vcpu)) {
1967                         if (!msr_info->host_initiated) {
1968                                 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
1969                                 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
1970                         }
1971                         vcpu->arch.ia32_tsc_adjust_msr = data;
1972                 }
1973                 break;
1974         case MSR_IA32_MISC_ENABLE:
1975                 vcpu->arch.ia32_misc_enable_msr = data;
1976                 break;
1977         case MSR_KVM_WALL_CLOCK_NEW:
1978         case MSR_KVM_WALL_CLOCK:
1979                 vcpu->kvm->arch.wall_clock = data;
1980                 kvm_write_wall_clock(vcpu->kvm, data);
1981                 break;
1982         case MSR_KVM_SYSTEM_TIME_NEW:
1983         case MSR_KVM_SYSTEM_TIME: {
1984                 u64 gpa_offset;
1985                 kvmclock_reset(vcpu);
1986
1987                 vcpu->arch.time = data;
1988                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1989
1990                 /* we verify if the enable bit is set... */
1991                 if (!(data & 1))
1992                         break;
1993
1994                 gpa_offset = data & ~(PAGE_MASK | 1);
1995
1996                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1997                      &vcpu->arch.pv_time, data & ~1ULL,
1998                      sizeof(struct pvclock_vcpu_time_info)))
1999                         vcpu->arch.pv_time_enabled = false;
2000                 else
2001                         vcpu->arch.pv_time_enabled = true;
2002
2003                 break;
2004         }
2005         case MSR_KVM_ASYNC_PF_EN:
2006                 if (kvm_pv_enable_async_pf(vcpu, data))
2007                         return 1;
2008                 break;
2009         case MSR_KVM_STEAL_TIME:
2010
2011                 if (unlikely(!sched_info_on()))
2012                         return 1;
2013
2014                 if (data & KVM_STEAL_RESERVED_MASK)
2015                         return 1;
2016
2017                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2018                                                 data & KVM_STEAL_VALID_BITS,
2019                                                 sizeof(struct kvm_steal_time)))
2020                         return 1;
2021
2022                 vcpu->arch.st.msr_val = data;
2023
2024                 if (!(data & KVM_MSR_ENABLED))
2025                         break;
2026
2027                 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2028
2029                 preempt_disable();
2030                 accumulate_steal_time(vcpu);
2031                 preempt_enable();
2032
2033                 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2034
2035                 break;
2036         case MSR_KVM_PV_EOI_EN:
2037                 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2038                         return 1;
2039                 break;
2040
2041         case MSR_IA32_MCG_CTL:
2042         case MSR_IA32_MCG_STATUS:
2043         case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2044                 return set_msr_mce(vcpu, msr, data);
2045
2046         /* Performance counters are not protected by a CPUID bit,
2047          * so we should check all of them in the generic path for the sake of
2048          * cross vendor migration.
2049          * Writing a zero into the event select MSRs disables them,
2050          * which we perfectly emulate ;-). Any other value should be at least
2051          * reported, some guests depend on them.
2052          */
2053         case MSR_K7_EVNTSEL0:
2054         case MSR_K7_EVNTSEL1:
2055         case MSR_K7_EVNTSEL2:
2056         case MSR_K7_EVNTSEL3:
2057                 if (data != 0)
2058                         vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2059                                     "0x%x data 0x%llx\n", msr, data);
2060                 break;
2061         /* at least RHEL 4 unconditionally writes to the perfctr registers,
2062          * so we ignore writes to make it happy.
2063          */
2064         case MSR_K7_PERFCTR0:
2065         case MSR_K7_PERFCTR1:
2066         case MSR_K7_PERFCTR2:
2067         case MSR_K7_PERFCTR3:
2068                 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2069                             "0x%x data 0x%llx\n", msr, data);
2070                 break;
2071         case MSR_P6_PERFCTR0:
2072         case MSR_P6_PERFCTR1:
2073                 pr = true;
2074         case MSR_P6_EVNTSEL0:
2075         case MSR_P6_EVNTSEL1:
2076                 if (kvm_pmu_msr(vcpu, msr))
2077                         return kvm_pmu_set_msr(vcpu, msr_info);
2078
2079                 if (pr || data != 0)
2080                         vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2081                                     "0x%x data 0x%llx\n", msr, data);
2082                 break;
2083         case MSR_K7_CLK_CTL:
2084                 /*
2085                  * Ignore all writes to this no longer documented MSR.
2086                  * Writes are only relevant for old K7 processors,
2087                  * all pre-dating SVM, but a recommended workaround from
2088                  * AMD for these chips. It is possible to specify the
2089                  * affected processor models on the command line, hence
2090                  * the need to ignore the workaround.
2091                  */
2092                 break;
2093         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2094                 if (kvm_hv_msr_partition_wide(msr)) {
2095                         int r;
2096                         mutex_lock(&vcpu->kvm->lock);
2097                         r = set_msr_hyperv_pw(vcpu, msr, data);
2098                         mutex_unlock(&vcpu->kvm->lock);
2099                         return r;
2100                 } else
2101                         return set_msr_hyperv(vcpu, msr, data);
2102                 break;
2103         case MSR_IA32_BBL_CR_CTL3:
2104                 /* Drop writes to this legacy MSR -- see rdmsr
2105                  * counterpart for further detail.
2106                  */
2107                 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2108                 break;
2109         case MSR_AMD64_OSVW_ID_LENGTH:
2110                 if (!guest_cpuid_has_osvw(vcpu))
2111                         return 1;
2112                 vcpu->arch.osvw.length = data;
2113                 break;
2114         case MSR_AMD64_OSVW_STATUS:
2115                 if (!guest_cpuid_has_osvw(vcpu))
2116                         return 1;
2117                 vcpu->arch.osvw.status = data;
2118                 break;
2119         default:
2120                 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2121                         return xen_hvm_config(vcpu, data);
2122                 if (kvm_pmu_msr(vcpu, msr))
2123                         return kvm_pmu_set_msr(vcpu, msr_info);
2124                 if (!ignore_msrs) {
2125                         vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2126                                     msr, data);
2127                         return 1;
2128                 } else {
2129                         vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2130                                     msr, data);
2131                         break;
2132                 }
2133         }
2134         return 0;
2135 }
2136 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2137
2138
2139 /*
2140  * Reads an msr value (of 'msr_index') into 'pdata'.
2141  * Returns 0 on success, non-0 otherwise.
2142  * Assumes vcpu_load() was already called.
2143  */
2144 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2145 {
2146         return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2147 }
2148
2149 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2150 {
2151         u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2152
2153         if (!msr_mtrr_valid(msr))
2154                 return 1;
2155
2156         if (msr == MSR_MTRRdefType)
2157                 *pdata = vcpu->arch.mtrr_state.def_type +
2158                          (vcpu->arch.mtrr_state.enabled << 10);
2159         else if (msr == MSR_MTRRfix64K_00000)
2160                 *pdata = p[0];
2161         else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2162                 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2163         else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2164                 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2165         else if (msr == MSR_IA32_CR_PAT)
2166                 *pdata = vcpu->arch.pat;
2167         else {  /* Variable MTRRs */
2168                 int idx, is_mtrr_mask;
2169                 u64 *pt;
2170
2171                 idx = (msr - 0x200) / 2;
2172                 is_mtrr_mask = msr - 0x200 - 2 * idx;
2173                 if (!is_mtrr_mask)
2174                         pt =
2175                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2176                 else
2177                         pt =
2178                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2179                 *pdata = *pt;
2180         }
2181
2182         return 0;
2183 }
2184
2185 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2186 {
2187         u64 data;
2188         u64 mcg_cap = vcpu->arch.mcg_cap;
2189         unsigned bank_num = mcg_cap & 0xff;
2190
2191         switch (msr) {
2192         case MSR_IA32_P5_MC_ADDR:
2193         case MSR_IA32_P5_MC_TYPE:
2194                 data = 0;
2195                 break;
2196         case MSR_IA32_MCG_CAP:
2197                 data = vcpu->arch.mcg_cap;
2198                 break;
2199         case MSR_IA32_MCG_CTL:
2200                 if (!(mcg_cap & MCG_CTL_P))
2201                         return 1;
2202                 data = vcpu->arch.mcg_ctl;
2203                 break;
2204         case MSR_IA32_MCG_STATUS:
2205                 data = vcpu->arch.mcg_status;
2206                 break;
2207         default:
2208                 if (msr >= MSR_IA32_MC0_CTL &&
2209                     msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2210                         u32 offset = msr - MSR_IA32_MC0_CTL;
2211                         data = vcpu->arch.mce_banks[offset];
2212                         break;
2213                 }
2214                 return 1;
2215         }
2216         *pdata = data;
2217         return 0;
2218 }
2219
2220 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2221 {
2222         u64 data = 0;
2223         struct kvm *kvm = vcpu->kvm;
2224
2225         switch (msr) {
2226         case HV_X64_MSR_GUEST_OS_ID:
2227                 data = kvm->arch.hv_guest_os_id;
2228                 break;
2229         case HV_X64_MSR_HYPERCALL:
2230                 data = kvm->arch.hv_hypercall;
2231                 break;
2232         default:
2233                 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2234                 return 1;
2235         }
2236
2237         *pdata = data;
2238         return 0;
2239 }
2240
2241 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2242 {
2243         u64 data = 0;
2244
2245         switch (msr) {
2246         case HV_X64_MSR_VP_INDEX: {
2247                 int r;
2248                 struct kvm_vcpu *v;
2249                 kvm_for_each_vcpu(r, v, vcpu->kvm)
2250                         if (v == vcpu)
2251                                 data = r;
2252                 break;
2253         }
2254         case HV_X64_MSR_EOI:
2255                 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2256         case HV_X64_MSR_ICR:
2257                 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2258         case HV_X64_MSR_TPR:
2259                 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
2260         case HV_X64_MSR_APIC_ASSIST_PAGE:
2261                 data = vcpu->arch.hv_vapic;
2262                 break;
2263         default:
2264                 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2265                 return 1;
2266         }
2267         *pdata = data;
2268         return 0;
2269 }
2270
2271 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2272 {
2273         u64 data;
2274
2275         switch (msr) {
2276         case MSR_IA32_PLATFORM_ID:
2277         case MSR_IA32_EBL_CR_POWERON:
2278         case MSR_IA32_DEBUGCTLMSR:
2279         case MSR_IA32_LASTBRANCHFROMIP:
2280         case MSR_IA32_LASTBRANCHTOIP:
2281         case MSR_IA32_LASTINTFROMIP:
2282         case MSR_IA32_LASTINTTOIP:
2283         case MSR_K8_SYSCFG:
2284         case MSR_K7_HWCR:
2285         case MSR_VM_HSAVE_PA:
2286         case MSR_K7_EVNTSEL0:
2287         case MSR_K7_PERFCTR0:
2288         case MSR_K8_INT_PENDING_MSG:
2289         case MSR_AMD64_NB_CFG:
2290         case MSR_FAM10H_MMIO_CONF_BASE:
2291         case MSR_AMD64_BU_CFG2:
2292                 data = 0;
2293                 break;
2294         case MSR_P6_PERFCTR0:
2295         case MSR_P6_PERFCTR1:
2296         case MSR_P6_EVNTSEL0:
2297         case MSR_P6_EVNTSEL1:
2298                 if (kvm_pmu_msr(vcpu, msr))
2299                         return kvm_pmu_get_msr(vcpu, msr, pdata);
2300                 data = 0;
2301                 break;
2302         case MSR_IA32_UCODE_REV:
2303                 data = 0x100000000ULL;
2304                 break;
2305         case MSR_MTRRcap:
2306                 data = 0x500 | KVM_NR_VAR_MTRR;
2307                 break;
2308         case 0x200 ... 0x2ff:
2309                 return get_msr_mtrr(vcpu, msr, pdata);
2310         case 0xcd: /* fsb frequency */
2311                 data = 3;
2312                 break;
2313                 /*
2314                  * MSR_EBC_FREQUENCY_ID
2315                  * Conservative value valid for even the basic CPU models.
2316                  * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2317                  * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2318                  * and 266MHz for model 3, or 4. Set Core Clock
2319                  * Frequency to System Bus Frequency Ratio to 1 (bits
2320                  * 31:24) even though these are only valid for CPU
2321                  * models > 2, however guests may end up dividing or
2322                  * multiplying by zero otherwise.
2323                  */
2324         case MSR_EBC_FREQUENCY_ID:
2325                 data = 1 << 24;
2326                 break;
2327         case MSR_IA32_APICBASE:
2328                 data = kvm_get_apic_base(vcpu);
2329                 break;
2330         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2331                 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2332                 break;
2333         case MSR_IA32_TSCDEADLINE:
2334                 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2335                 break;
2336         case MSR_IA32_TSC_ADJUST:
2337                 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2338                 break;
2339         case MSR_IA32_MISC_ENABLE:
2340                 data = vcpu->arch.ia32_misc_enable_msr;
2341                 break;
2342         case MSR_IA32_PERF_STATUS:
2343                 /* TSC increment by tick */
2344                 data = 1000ULL;
2345                 /* CPU multiplier */
2346                 data |= (((uint64_t)4ULL) << 40);
2347                 break;
2348         case MSR_EFER:
2349                 data = vcpu->arch.efer;
2350                 break;
2351         case MSR_KVM_WALL_CLOCK:
2352         case MSR_KVM_WALL_CLOCK_NEW:
2353                 data = vcpu->kvm->arch.wall_clock;
2354                 break;
2355         case MSR_KVM_SYSTEM_TIME:
2356         case MSR_KVM_SYSTEM_TIME_NEW:
2357                 data = vcpu->arch.time;
2358                 break;
2359         case MSR_KVM_ASYNC_PF_EN:
2360                 data = vcpu->arch.apf.msr_val;
2361                 break;
2362         case MSR_KVM_STEAL_TIME:
2363                 data = vcpu->arch.st.msr_val;
2364                 break;
2365         case MSR_KVM_PV_EOI_EN:
2366                 data = vcpu->arch.pv_eoi.msr_val;
2367                 break;
2368         case MSR_IA32_P5_MC_ADDR:
2369         case MSR_IA32_P5_MC_TYPE:
2370         case MSR_IA32_MCG_CAP:
2371         case MSR_IA32_MCG_CTL:
2372         case MSR_IA32_MCG_STATUS:
2373         case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2374                 return get_msr_mce(vcpu, msr, pdata);
2375         case MSR_K7_CLK_CTL:
2376                 /*
2377                  * Provide expected ramp-up count for K7. All other
2378                  * are set to zero, indicating minimum divisors for
2379                  * every field.
2380                  *
2381                  * This prevents guest kernels on AMD host with CPU
2382                  * type 6, model 8 and higher from exploding due to
2383                  * the rdmsr failing.
2384                  */
2385                 data = 0x20000000;
2386                 break;
2387         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2388                 if (kvm_hv_msr_partition_wide(msr)) {
2389                         int r;
2390                         mutex_lock(&vcpu->kvm->lock);
2391                         r = get_msr_hyperv_pw(vcpu, msr, pdata);
2392                         mutex_unlock(&vcpu->kvm->lock);
2393                         return r;
2394                 } else
2395                         return get_msr_hyperv(vcpu, msr, pdata);
2396                 break;
2397         case MSR_IA32_BBL_CR_CTL3:
2398                 /* This legacy MSR exists but isn't fully documented in current
2399                  * silicon.  It is however accessed by winxp in very narrow
2400                  * scenarios where it sets bit #19, itself documented as
2401                  * a "reserved" bit.  Best effort attempt to source coherent
2402                  * read data here should the balance of the register be
2403                  * interpreted by the guest:
2404                  *
2405                  * L2 cache control register 3: 64GB range, 256KB size,
2406                  * enabled, latency 0x1, configured
2407                  */
2408                 data = 0xbe702111;
2409                 break;
2410         case MSR_AMD64_OSVW_ID_LENGTH:
2411                 if (!guest_cpuid_has_osvw(vcpu))
2412                         return 1;
2413                 data = vcpu->arch.osvw.length;
2414                 break;
2415         case MSR_AMD64_OSVW_STATUS:
2416                 if (!guest_cpuid_has_osvw(vcpu))
2417                         return 1;
2418                 data = vcpu->arch.osvw.status;
2419                 break;
2420         default:
2421                 if (kvm_pmu_msr(vcpu, msr))
2422                         return kvm_pmu_get_msr(vcpu, msr, pdata);
2423                 if (!ignore_msrs) {
2424                         vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2425                         return 1;
2426                 } else {
2427                         vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2428                         data = 0;
2429                 }
2430                 break;
2431         }
2432         *pdata = data;
2433         return 0;
2434 }
2435 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2436
2437 /*
2438  * Read or write a bunch of msrs. All parameters are kernel addresses.
2439  *
2440  * @return number of msrs set successfully.
2441  */
2442 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2443                     struct kvm_msr_entry *entries,
2444                     int (*do_msr)(struct kvm_vcpu *vcpu,
2445                                   unsigned index, u64 *data))
2446 {
2447         int i, idx;
2448
2449         idx = srcu_read_lock(&vcpu->kvm->srcu);
2450         for (i = 0; i < msrs->nmsrs; ++i)
2451                 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2452                         break;
2453         srcu_read_unlock(&vcpu->kvm->srcu, idx);
2454
2455         return i;
2456 }
2457
2458 /*
2459  * Read or write a bunch of msrs. Parameters are user addresses.
2460  *
2461  * @return number of msrs set successfully.
2462  */
2463 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2464                   int (*do_msr)(struct kvm_vcpu *vcpu,
2465                                 unsigned index, u64 *data),
2466                   int writeback)
2467 {
2468         struct kvm_msrs msrs;
2469         struct kvm_msr_entry *entries;
2470         int r, n;
2471         unsigned size;
2472
2473         r = -EFAULT;
2474         if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2475                 goto out;
2476
2477         r = -E2BIG;
2478         if (msrs.nmsrs >= MAX_IO_MSRS)
2479                 goto out;
2480
2481         size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2482         entries = memdup_user(user_msrs->entries, size);
2483         if (IS_ERR(entries)) {
2484                 r = PTR_ERR(entries);
2485                 goto out;
2486         }
2487
2488         r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2489         if (r < 0)
2490                 goto out_free;
2491
2492         r = -EFAULT;
2493         if (writeback && copy_to_user(user_msrs->entries, entries, size))
2494                 goto out_free;
2495
2496         r = n;
2497
2498 out_free:
2499         kfree(entries);
2500 out:
2501         return r;
2502 }
2503
2504 int kvm_dev_ioctl_check_extension(long ext)
2505 {
2506         int r;
2507
2508         switch (ext) {
2509         case KVM_CAP_IRQCHIP:
2510         case KVM_CAP_HLT:
2511         case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2512         case KVM_CAP_SET_TSS_ADDR:
2513         case KVM_CAP_EXT_CPUID:
2514         case KVM_CAP_CLOCKSOURCE:
2515         case KVM_CAP_PIT:
2516         case KVM_CAP_NOP_IO_DELAY:
2517         case KVM_CAP_MP_STATE:
2518         case KVM_CAP_SYNC_MMU:
2519         case KVM_CAP_USER_NMI:
2520         case KVM_CAP_REINJECT_CONTROL:
2521         case KVM_CAP_IRQ_INJECT_STATUS:
2522         case KVM_CAP_IRQFD:
2523         case KVM_CAP_IOEVENTFD:
2524         case KVM_CAP_PIT2:
2525         case KVM_CAP_PIT_STATE2:
2526         case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2527         case KVM_CAP_XEN_HVM:
2528         case KVM_CAP_ADJUST_CLOCK:
2529         case KVM_CAP_VCPU_EVENTS:
2530         case KVM_CAP_HYPERV:
2531         case KVM_CAP_HYPERV_VAPIC:
2532         case KVM_CAP_HYPERV_SPIN:
2533         case KVM_CAP_PCI_SEGMENT:
2534         case KVM_CAP_DEBUGREGS:
2535         case KVM_CAP_X86_ROBUST_SINGLESTEP:
2536         case KVM_CAP_XSAVE:
2537         case KVM_CAP_ASYNC_PF:
2538         case KVM_CAP_GET_TSC_KHZ:
2539         case KVM_CAP_KVMCLOCK_CTRL:
2540         case KVM_CAP_READONLY_MEM:
2541 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2542         case KVM_CAP_ASSIGN_DEV_IRQ:
2543         case KVM_CAP_PCI_2_3:
2544 #endif
2545                 r = 1;
2546                 break;
2547         case KVM_CAP_COALESCED_MMIO:
2548                 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2549                 break;
2550         case KVM_CAP_VAPIC:
2551                 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2552                 break;
2553         case KVM_CAP_NR_VCPUS:
2554                 r = KVM_SOFT_MAX_VCPUS;
2555                 break;
2556         case KVM_CAP_MAX_VCPUS:
2557                 r = KVM_MAX_VCPUS;
2558                 break;
2559         case KVM_CAP_NR_MEMSLOTS:
2560                 r = KVM_USER_MEM_SLOTS;
2561                 break;
2562         case KVM_CAP_PV_MMU:    /* obsolete */
2563                 r = 0;
2564                 break;
2565 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2566         case KVM_CAP_IOMMU:
2567                 r = iommu_present(&pci_bus_type);
2568                 break;
2569 #endif
2570         case KVM_CAP_MCE:
2571                 r = KVM_MAX_MCE_BANKS;
2572                 break;
2573         case KVM_CAP_XCRS:
2574                 r = cpu_has_xsave;
2575                 break;
2576         case KVM_CAP_TSC_CONTROL:
2577                 r = kvm_has_tsc_control;
2578                 break;
2579         case KVM_CAP_TSC_DEADLINE_TIMER:
2580                 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2581                 break;
2582         default:
2583                 r = 0;
2584                 break;
2585         }
2586         return r;
2587
2588 }
2589
2590 long kvm_arch_dev_ioctl(struct file *filp,
2591                         unsigned int ioctl, unsigned long arg)
2592 {
2593         void __user *argp = (void __user *)arg;
2594         long r;
2595
2596         switch (ioctl) {
2597         case KVM_GET_MSR_INDEX_LIST: {
2598                 struct kvm_msr_list __user *user_msr_list = argp;
2599                 struct kvm_msr_list msr_list;
2600                 unsigned n;
2601
2602                 r = -EFAULT;
2603                 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2604                         goto out;
2605                 n = msr_list.nmsrs;
2606                 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2607                 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2608                         goto out;
2609                 r = -E2BIG;
2610                 if (n < msr_list.nmsrs)
2611                         goto out;
2612                 r = -EFAULT;
2613                 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2614                                  num_msrs_to_save * sizeof(u32)))
2615                         goto out;
2616                 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2617                                  &emulated_msrs,
2618                                  ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2619                         goto out;
2620                 r = 0;
2621                 break;
2622         }
2623         case KVM_GET_SUPPORTED_CPUID: {
2624                 struct kvm_cpuid2 __user *cpuid_arg = argp;
2625                 struct kvm_cpuid2 cpuid;
2626
2627                 r = -EFAULT;
2628                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2629                         goto out;
2630                 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
2631                                                       cpuid_arg->entries);
2632                 if (r)
2633                         goto out;
2634
2635                 r = -EFAULT;
2636                 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2637                         goto out;
2638                 r = 0;
2639                 break;
2640         }
2641         case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2642                 u64 mce_cap;
2643
2644                 mce_cap = KVM_MCE_CAP_SUPPORTED;
2645                 r = -EFAULT;
2646                 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2647                         goto out;
2648                 r = 0;
2649                 break;
2650         }
2651         default:
2652                 r = -EINVAL;
2653         }
2654 out:
2655         return r;
2656 }
2657
2658 static void wbinvd_ipi(void *garbage)
2659 {
2660         wbinvd();
2661 }
2662
2663 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2664 {
2665         return vcpu->kvm->arch.iommu_domain &&
2666                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2667 }
2668
2669 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2670 {
2671         /* Address WBINVD may be executed by guest */
2672         if (need_emulate_wbinvd(vcpu)) {
2673                 if (kvm_x86_ops->has_wbinvd_exit())
2674                         cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2675                 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2676                         smp_call_function_single(vcpu->cpu,
2677                                         wbinvd_ipi, NULL, 1);
2678         }
2679
2680         kvm_x86_ops->vcpu_load(vcpu, cpu);
2681
2682         /* Apply any externally detected TSC adjustments (due to suspend) */
2683         if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2684                 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2685                 vcpu->arch.tsc_offset_adjustment = 0;
2686                 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2687         }
2688
2689         if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2690                 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2691                                 native_read_tsc() - vcpu->arch.last_host_tsc;
2692                 if (tsc_delta < 0)
2693                         mark_tsc_unstable("KVM discovered backwards TSC");
2694                 if (check_tsc_unstable()) {
2695                         u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2696                                                 vcpu->arch.last_guest_tsc);
2697                         kvm_x86_ops->write_tsc_offset(vcpu, offset);
2698                         vcpu->arch.tsc_catchup = 1;
2699                 }
2700                 /*
2701                  * On a host with synchronized TSC, there is no need to update
2702                  * kvmclock on vcpu->cpu migration
2703                  */
2704                 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2705                         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2706                 if (vcpu->cpu != cpu)
2707                         kvm_migrate_timers(vcpu);
2708                 vcpu->cpu = cpu;
2709         }
2710
2711         accumulate_steal_time(vcpu);
2712         kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2713 }
2714
2715 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2716 {
2717         kvm_x86_ops->vcpu_put(vcpu);
2718         kvm_put_guest_fpu(vcpu);
2719         vcpu->arch.last_host_tsc = native_read_tsc();
2720 }
2721
2722 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2723                                     struct kvm_lapic_state *s)
2724 {
2725         kvm_x86_ops->sync_pir_to_irr(vcpu);
2726         memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2727
2728         return 0;
2729 }
2730
2731 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2732                                     struct kvm_lapic_state *s)
2733 {
2734         kvm_apic_post_state_restore(vcpu, s);
2735         update_cr8_intercept(vcpu);
2736
2737         return 0;
2738 }
2739
2740 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2741                                     struct kvm_interrupt *irq)
2742 {
2743         if (irq->irq >= KVM_NR_INTERRUPTS)
2744                 return -EINVAL;
2745         if (irqchip_in_kernel(vcpu->kvm))
2746                 return -ENXIO;
2747
2748         kvm_queue_interrupt(vcpu, irq->irq, false);
2749         kvm_make_request(KVM_REQ_EVENT, vcpu);
2750
2751         return 0;
2752 }
2753
2754 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2755 {
2756         kvm_inject_nmi(vcpu);
2757
2758         return 0;
2759 }
2760
2761 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2762                                            struct kvm_tpr_access_ctl *tac)
2763 {
2764         if (tac->flags)
2765                 return -EINVAL;
2766         vcpu->arch.tpr_access_reporting = !!tac->enabled;
2767         return 0;
2768 }
2769
2770 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2771                                         u64 mcg_cap)
2772 {
2773         int r;
2774         unsigned bank_num = mcg_cap & 0xff, bank;
2775
2776         r = -EINVAL;
2777         if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2778                 goto out;
2779         if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2780                 goto out;
2781         r = 0;
2782         vcpu->arch.mcg_cap = mcg_cap;
2783         /* Init IA32_MCG_CTL to all 1s */
2784         if (mcg_cap & MCG_CTL_P)
2785                 vcpu->arch.mcg_ctl = ~(u64)0;
2786         /* Init IA32_MCi_CTL to all 1s */
2787         for (bank = 0; bank < bank_num; bank++)
2788                 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2789 out:
2790         return r;
2791 }
2792
2793 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2794                                       struct kvm_x86_mce *mce)
2795 {
2796         u64 mcg_cap = vcpu->arch.mcg_cap;
2797         unsigned bank_num = mcg_cap & 0xff;
2798         u64 *banks = vcpu->arch.mce_banks;
2799
2800         if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2801                 return -EINVAL;
2802         /*
2803          * if IA32_MCG_CTL is not all 1s, the uncorrected error
2804          * reporting is disabled
2805          */
2806         if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2807             vcpu->arch.mcg_ctl != ~(u64)0)
2808                 return 0;
2809         banks += 4 * mce->bank;
2810         /*
2811          * if IA32_MCi_CTL is not all 1s, the uncorrected error
2812          * reporting is disabled for the bank
2813          */
2814         if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2815                 return 0;
2816         if (mce->status & MCI_STATUS_UC) {
2817                 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2818                     !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2819                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2820                         return 0;
2821                 }
2822                 if (banks[1] & MCI_STATUS_VAL)
2823                         mce->status |= MCI_STATUS_OVER;
2824                 banks[2] = mce->addr;
2825                 banks[3] = mce->misc;
2826                 vcpu->arch.mcg_status = mce->mcg_status;
2827                 banks[1] = mce->status;
2828                 kvm_queue_exception(vcpu, MC_VECTOR);
2829         } else if (!(banks[1] & MCI_STATUS_VAL)
2830                    || !(banks[1] & MCI_STATUS_UC)) {
2831                 if (banks[1] & MCI_STATUS_VAL)
2832                         mce->status |= MCI_STATUS_OVER;
2833                 banks[2] = mce->addr;
2834                 banks[3] = mce->misc;
2835                 banks[1] = mce->status;
2836         } else
2837                 banks[1] |= MCI_STATUS_OVER;
2838         return 0;
2839 }
2840
2841 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2842                                                struct kvm_vcpu_events *events)
2843 {
2844         process_nmi(vcpu);
2845         events->exception.injected =
2846                 vcpu->arch.exception.pending &&
2847                 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2848         events->exception.nr = vcpu->arch.exception.nr;
2849         events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2850         events->exception.pad = 0;
2851         events->exception.error_code = vcpu->arch.exception.error_code;
2852
2853         events->interrupt.injected =
2854                 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2855         events->interrupt.nr = vcpu->arch.interrupt.nr;
2856         events->interrupt.soft = 0;
2857         events->interrupt.shadow =
2858                 kvm_x86_ops->get_interrupt_shadow(vcpu,
2859                         KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2860
2861         events->nmi.injected = vcpu->arch.nmi_injected;
2862         events->nmi.pending = vcpu->arch.nmi_pending != 0;
2863         events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2864         events->nmi.pad = 0;
2865
2866         events->sipi_vector = 0; /* never valid when reporting to user space */
2867
2868         events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2869                          | KVM_VCPUEVENT_VALID_SHADOW);
2870         memset(&events->reserved, 0, sizeof(events->reserved));
2871 }
2872
2873 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2874                                               struct kvm_vcpu_events *events)
2875 {
2876         if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2877                               | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2878                               | KVM_VCPUEVENT_VALID_SHADOW))
2879                 return -EINVAL;
2880
2881         process_nmi(vcpu);
2882         vcpu->arch.exception.pending = events->exception.injected;
2883         vcpu->arch.exception.nr = events->exception.nr;
2884         vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2885         vcpu->arch.exception.error_code = events->exception.error_code;
2886
2887         vcpu->arch.interrupt.pending = events->interrupt.injected;
2888         vcpu->arch.interrupt.nr = events->interrupt.nr;
2889         vcpu->arch.interrupt.soft = events->interrupt.soft;
2890         if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2891                 kvm_x86_ops->set_interrupt_shadow(vcpu,
2892                                                   events->interrupt.shadow);
2893
2894         vcpu->arch.nmi_injected = events->nmi.injected;
2895         if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2896                 vcpu->arch.nmi_pending = events->nmi.pending;
2897         kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2898
2899         if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2900             kvm_vcpu_has_lapic(vcpu))
2901                 vcpu->arch.apic->sipi_vector = events->sipi_vector;
2902
2903         kvm_make_request(KVM_REQ_EVENT, vcpu);
2904
2905         return 0;
2906 }
2907
2908 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2909                                              struct kvm_debugregs *dbgregs)
2910 {
2911         memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2912         dbgregs->dr6 = vcpu->arch.dr6;
2913         dbgregs->dr7 = vcpu->arch.dr7;
2914         dbgregs->flags = 0;
2915         memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
2916 }
2917
2918 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2919                                             struct kvm_debugregs *dbgregs)
2920 {
2921         if (dbgregs->flags)
2922                 return -EINVAL;
2923
2924         memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2925         vcpu->arch.dr6 = dbgregs->dr6;
2926         vcpu->arch.dr7 = dbgregs->dr7;
2927
2928         return 0;
2929 }
2930
2931 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2932                                          struct kvm_xsave *guest_xsave)
2933 {
2934         if (cpu_has_xsave)
2935                 memcpy(guest_xsave->region,
2936                         &vcpu->arch.guest_fpu.state->xsave,
2937                         xstate_size);
2938         else {
2939                 memcpy(guest_xsave->region,
2940                         &vcpu->arch.guest_fpu.state->fxsave,
2941                         sizeof(struct i387_fxsave_struct));
2942                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2943                         XSTATE_FPSSE;
2944         }
2945 }
2946
2947 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2948                                         struct kvm_xsave *guest_xsave)
2949 {
2950         u64 xstate_bv =
2951                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2952
2953         if (cpu_has_xsave)
2954                 memcpy(&vcpu->arch.guest_fpu.state->xsave,
2955                         guest_xsave->region, xstate_size);
2956         else {
2957                 if (xstate_bv & ~XSTATE_FPSSE)
2958                         return -EINVAL;
2959                 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2960                         guest_xsave->region, sizeof(struct i387_fxsave_struct));
2961         }
2962         return 0;
2963 }
2964
2965 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2966                                         struct kvm_xcrs *guest_xcrs)
2967 {
2968         if (!cpu_has_xsave) {
2969                 guest_xcrs->nr_xcrs = 0;
2970                 return;
2971         }
2972
2973         guest_xcrs->nr_xcrs = 1;
2974         guest_xcrs->flags = 0;
2975         guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2976         guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2977 }
2978
2979 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2980                                        struct kvm_xcrs *guest_xcrs)
2981 {
2982         int i, r = 0;
2983
2984         if (!cpu_has_xsave)
2985                 return -EINVAL;
2986
2987         if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2988                 return -EINVAL;
2989
2990         for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2991                 /* Only support XCR0 currently */
2992                 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2993                         r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2994                                 guest_xcrs->xcrs[0].value);
2995                         break;
2996                 }
2997         if (r)
2998                 r = -EINVAL;
2999         return r;
3000 }
3001
3002 /*
3003  * kvm_set_guest_paused() indicates to the guest kernel that it has been
3004  * stopped by the hypervisor.  This function will be called from the host only.
3005  * EINVAL is returned when the host attempts to set the flag for a guest that
3006  * does not support pv clocks.
3007  */
3008 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3009 {
3010         if (!vcpu->arch.pv_time_enabled)
3011                 return -EINVAL;
3012         vcpu->arch.pvclock_set_guest_stopped_request = true;
3013         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3014         return 0;
3015 }
3016
3017 long kvm_arch_vcpu_ioctl(struct file *filp,
3018                          unsigned int ioctl, unsigned long arg)
3019 {
3020         struct kvm_vcpu *vcpu = filp->private_data;
3021         void __user *argp = (void __user *)arg;
3022         int r;
3023         union {
3024                 struct kvm_lapic_state *lapic;
3025                 struct kvm_xsave *xsave;
3026                 struct kvm_xcrs *xcrs;
3027                 void *buffer;
3028         } u;
3029
3030         u.buffer = NULL;
3031         switch (ioctl) {
3032         case KVM_GET_LAPIC: {
3033                 r = -EINVAL;
3034                 if (!vcpu->arch.apic)
3035                         goto out;
3036                 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3037
3038                 r = -ENOMEM;
3039                 if (!u.lapic)
3040                         goto out;
3041                 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3042                 if (r)
3043                         goto out;
3044                 r = -EFAULT;
3045                 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3046                         goto out;
3047                 r = 0;
3048                 break;
3049         }
3050         case KVM_SET_LAPIC: {
3051                 r = -EINVAL;
3052                 if (!vcpu->arch.apic)
3053                         goto out;
3054                 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3055                 if (IS_ERR(u.lapic))
3056                         return PTR_ERR(u.lapic);
3057
3058                 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3059                 break;
3060         }
3061         case KVM_INTERRUPT: {
3062                 struct kvm_interrupt irq;
3063
3064                 r = -EFAULT;
3065                 if (copy_from_user(&irq, argp, sizeof irq))
3066                         goto out;
3067                 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3068                 break;
3069         }
3070         case KVM_NMI: {
3071                 r = kvm_vcpu_ioctl_nmi(vcpu);
3072                 break;
3073         }
3074         case KVM_SET_CPUID: {
3075                 struct kvm_cpuid __user *cpuid_arg = argp;
3076                 struct kvm_cpuid cpuid;
3077
3078                 r = -EFAULT;
3079                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3080                         goto out;
3081                 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3082                 break;
3083         }
3084         case KVM_SET_CPUID2: {
3085                 struct kvm_cpuid2 __user *cpuid_arg = argp;
3086                 struct kvm_cpuid2 cpuid;
3087
3088                 r = -EFAULT;
3089                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3090                         goto out;
3091                 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3092                                               cpuid_arg->entries);
3093                 break;
3094         }
3095         case KVM_GET_CPUID2: {
3096                 struct kvm_cpuid2 __user *cpuid_arg = argp;
3097                 struct kvm_cpuid2 cpuid;
3098
3099                 r = -EFAULT;
3100                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3101                         goto out;
3102                 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3103                                               cpuid_arg->entries);
3104                 if (r)
3105                         goto out;
3106                 r = -EFAULT;
3107                 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3108                         goto out;
3109                 r = 0;
3110                 break;
3111         }
3112         case KVM_GET_MSRS:
3113                 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3114                 break;
3115         case KVM_SET_MSRS:
3116                 r = msr_io(vcpu, argp, do_set_msr, 0);
3117                 break;
3118         case KVM_TPR_ACCESS_REPORTING: {
3119                 struct kvm_tpr_access_ctl tac;
3120
3121                 r = -EFAULT;
3122                 if (copy_from_user(&tac, argp, sizeof tac))
3123                         goto out;
3124                 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3125                 if (r)
3126                         goto out;
3127                 r = -EFAULT;
3128                 if (copy_to_user(argp, &tac, sizeof tac))
3129                         goto out;
3130                 r = 0;
3131                 break;
3132         };
3133         case KVM_SET_VAPIC_ADDR: {
3134                 struct kvm_vapic_addr va;
3135
3136                 r = -EINVAL;
3137                 if (!irqchip_in_kernel(vcpu->kvm))
3138                         goto out;
3139                 r = -EFAULT;
3140                 if (copy_from_user(&va, argp, sizeof va))
3141                         goto out;
3142                 r = 0;
3143                 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3144                 break;
3145         }
3146         case KVM_X86_SETUP_MCE: {
3147                 u64 mcg_cap;
3148
3149                 r = -EFAULT;
3150                 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3151                         goto out;
3152                 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3153                 break;
3154         }
3155         case KVM_X86_SET_MCE: {
3156                 struct kvm_x86_mce mce;
3157
3158                 r = -EFAULT;
3159                 if (copy_from_user(&mce, argp, sizeof mce))
3160                         goto out;
3161                 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3162                 break;
3163         }
3164         case KVM_GET_VCPU_EVENTS: {
3165                 struct kvm_vcpu_events events;
3166
3167                 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3168
3169                 r = -EFAULT;
3170                 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3171                         break;
3172                 r = 0;
3173                 break;
3174         }
3175         case KVM_SET_VCPU_EVENTS: {
3176                 struct kvm_vcpu_events events;
3177
3178                 r = -EFAULT;
3179                 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3180                         break;
3181
3182                 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3183                 break;
3184         }
3185         case KVM_GET_DEBUGREGS: {
3186                 struct kvm_debugregs dbgregs;
3187
3188                 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3189
3190                 r = -EFAULT;
3191                 if (copy_to_user(argp, &dbgregs,
3192                                  sizeof(struct kvm_debugregs)))
3193                         break;
3194                 r = 0;
3195                 break;
3196         }
3197         case KVM_SET_DEBUGREGS: {
3198                 struct kvm_debugregs dbgregs;
3199
3200                 r = -EFAULT;
3201                 if (copy_from_user(&dbgregs, argp,
3202                                    sizeof(struct kvm_debugregs)))
3203                         break;
3204
3205                 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3206                 break;
3207         }
3208         case KVM_GET_XSAVE: {
3209                 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3210                 r = -ENOMEM;
3211                 if (!u.xsave)
3212                         break;
3213
3214                 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3215
3216                 r = -EFAULT;
3217                 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3218                         break;
3219                 r = 0;
3220                 break;
3221         }
3222         case KVM_SET_XSAVE: {
3223                 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3224                 if (IS_ERR(u.xsave))
3225                         return PTR_ERR(u.xsave);
3226
3227                 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3228                 break;
3229         }
3230         case KVM_GET_XCRS: {
3231                 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3232                 r = -ENOMEM;
3233                 if (!u.xcrs)
3234                         break;
3235
3236                 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3237
3238                 r = -EFAULT;
3239                 if (copy_to_user(argp, u.xcrs,
3240                                  sizeof(struct kvm_xcrs)))
3241                         break;
3242                 r = 0;
3243                 break;
3244         }
3245         case KVM_SET_XCRS: {
3246                 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3247                 if (IS_ERR(u.xcrs))
3248                         return PTR_ERR(u.xcrs);
3249
3250                 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3251                 break;
3252         }
3253         case KVM_SET_TSC_KHZ: {
3254                 u32 user_tsc_khz;
3255
3256                 r = -EINVAL;
3257                 user_tsc_khz = (u32)arg;
3258
3259                 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3260                         goto out;
3261
3262                 if (user_tsc_khz == 0)
3263                         user_tsc_khz = tsc_khz;
3264
3265                 kvm_set_tsc_khz(vcpu, user_tsc_khz);
3266
3267                 r = 0;
3268                 goto out;
3269         }
3270         case KVM_GET_TSC_KHZ: {
3271                 r = vcpu->arch.virtual_tsc_khz;
3272                 goto out;
3273         }
3274         case KVM_KVMCLOCK_CTRL: {
3275                 r = kvm_set_guest_paused(vcpu);
3276                 goto out;
3277         }
3278         default:
3279                 r = -EINVAL;
3280         }
3281 out:
3282         kfree(u.buffer);
3283         return r;
3284 }
3285
3286 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3287 {
3288         return VM_FAULT_SIGBUS;
3289 }
3290
3291 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3292 {
3293         int ret;
3294
3295         if (addr > (unsigned int)(-3 * PAGE_SIZE))
3296                 return -EINVAL;
3297         ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3298         return ret;
3299 }
3300
3301 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3302                                               u64 ident_addr)
3303 {
3304         kvm->arch.ept_identity_map_addr = ident_addr;
3305         return 0;
3306 }
3307
3308 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3309                                           u32 kvm_nr_mmu_pages)
3310 {
3311         if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3312                 return -EINVAL;
3313
3314         mutex_lock(&kvm->slots_lock);
3315
3316         kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3317         kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3318
3319         mutex_unlock(&kvm->slots_lock);
3320         return 0;
3321 }
3322
3323 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3324 {
3325         return kvm->arch.n_max_mmu_pages;
3326 }
3327
3328 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3329 {
3330         int r;
3331
3332         r = 0;
3333         switch (chip->chip_id) {
3334         case KVM_IRQCHIP_PIC_MASTER:
3335                 memcpy(&chip->chip.pic,
3336                         &pic_irqchip(kvm)->pics[0],
3337                         sizeof(struct kvm_pic_state));
3338                 break;
3339         case KVM_IRQCHIP_PIC_SLAVE:
3340                 memcpy(&chip->chip.pic,
3341                         &pic_irqchip(kvm)->pics[1],
3342                         sizeof(struct kvm_pic_state));
3343                 break;
3344         case KVM_IRQCHIP_IOAPIC:
3345                 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3346                 break;
3347         default:
3348                 r = -EINVAL;
3349                 break;
3350         }
3351         return r;
3352 }
3353
3354 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3355 {
3356         int r;
3357
3358         r = 0;
3359         switch (chip->chip_id) {
3360         case KVM_IRQCHIP_PIC_MASTER:
3361                 spin_lock(&pic_irqchip(kvm)->lock);
3362                 memcpy(&pic_irqchip(kvm)->pics[0],
3363                         &chip->chip.pic,
3364                         sizeof(struct kvm_pic_state));
3365                 spin_unlock(&pic_irqchip(kvm)->lock);
3366                 break;
3367         case KVM_IRQCHIP_PIC_SLAVE:
3368                 spin_lock(&pic_irqchip(kvm)->lock);
3369                 memcpy(&pic_irqchip(kvm)->pics[1],
3370                         &chip->chip.pic,
3371                         sizeof(struct kvm_pic_state));
3372                 spin_unlock(&pic_irqchip(kvm)->lock);
3373                 break;
3374         case KVM_IRQCHIP_IOAPIC:
3375                 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3376                 break;
3377         default:
3378                 r = -EINVAL;
3379                 break;
3380         }
3381         kvm_pic_update_irq(pic_irqchip(kvm));
3382         return r;
3383 }
3384
3385 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3386 {
3387         int r = 0;
3388
3389         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3390         memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3391         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3392         return r;
3393 }
3394
3395 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3396 {
3397         int r = 0;
3398
3399         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3400         memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3401         kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3402         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3403         return r;
3404 }
3405
3406 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3407 {
3408         int r = 0;
3409
3410         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3411         memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3412                 sizeof(ps->channels));
3413         ps->flags = kvm->arch.vpit->pit_state.flags;
3414         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3415         memset(&ps->reserved, 0, sizeof(ps->reserved));
3416         return r;
3417 }
3418
3419 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3420 {
3421         int r = 0, start = 0;
3422         u32 prev_legacy, cur_legacy;
3423         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3424         prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3425         cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3426         if (!prev_legacy && cur_legacy)
3427                 start = 1;
3428         memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3429                sizeof(kvm->arch.vpit->pit_state.channels));
3430         kvm->arch.vpit->pit_state.flags = ps->flags;
3431         kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3432         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3433         return r;
3434 }
3435
3436 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3437                                  struct kvm_reinject_control *control)
3438 {
3439         if (!kvm->arch.vpit)
3440                 return -ENXIO;
3441         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3442         kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3443         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3444         return 0;
3445 }
3446
3447 /**
3448  * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3449  * @kvm: kvm instance
3450  * @log: slot id and address to which we copy the log
3451  *
3452  * We need to keep it in mind that VCPU threads can write to the bitmap
3453  * concurrently.  So, to avoid losing data, we keep the following order for
3454  * each bit:
3455  *
3456  *   1. Take a snapshot of the bit and clear it if needed.
3457  *   2. Write protect the corresponding page.
3458  *   3. Flush TLB's if needed.
3459  *   4. Copy the snapshot to the userspace.
3460  *
3461  * Between 2 and 3, the guest may write to the page using the remaining TLB
3462  * entry.  This is not a problem because the page will be reported dirty at
3463  * step 4 using the snapshot taken before and step 3 ensures that successive
3464  * writes will be logged for the next call.
3465  */
3466 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3467 {
3468         int r;
3469         struct kvm_memory_slot *memslot;
3470         unsigned long n, i;
3471         unsigned long *dirty_bitmap;
3472         unsigned long *dirty_bitmap_buffer;
3473         bool is_dirty = false;
3474
3475         mutex_lock(&kvm->slots_lock);
3476
3477         r = -EINVAL;
3478         if (log->slot >= KVM_USER_MEM_SLOTS)
3479                 goto out;
3480
3481         memslot = id_to_memslot(kvm->memslots, log->slot);
3482
3483         dirty_bitmap = memslot->dirty_bitmap;
3484         r = -ENOENT;
3485         if (!dirty_bitmap)
3486                 goto out;
3487
3488         n = kvm_dirty_bitmap_bytes(memslot);
3489
3490         dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3491         memset(dirty_bitmap_buffer, 0, n);
3492
3493         spin_lock(&kvm->mmu_lock);
3494
3495         for (i = 0; i < n / sizeof(long); i++) {
3496                 unsigned long mask;
3497                 gfn_t offset;
3498
3499                 if (!dirty_bitmap[i])
3500                         continue;
3501
3502                 is_dirty = true;
3503
3504                 mask = xchg(&dirty_bitmap[i], 0);
3505                 dirty_bitmap_buffer[i] = mask;
3506
3507                 offset = i * BITS_PER_LONG;
3508                 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
3509         }
3510         if (is_dirty)
3511                 kvm_flush_remote_tlbs(kvm);
3512
3513         spin_unlock(&kvm->mmu_lock);
3514
3515         r = -EFAULT;
3516         if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3517                 goto out;
3518
3519         r = 0;
3520 out:
3521         mutex_unlock(&kvm->slots_lock);
3522         return r;
3523 }
3524
3525 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3526                         bool line_status)
3527 {
3528         if (!irqchip_in_kernel(kvm))
3529                 return -ENXIO;
3530
3531         irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3532                                         irq_event->irq, irq_event->level,
3533                                         line_status);
3534         return 0;
3535 }
3536
3537 long kvm_arch_vm_ioctl(struct file *filp,
3538                        unsigned int ioctl, unsigned long arg)
3539 {
3540         struct kvm *kvm = filp->private_data;
3541         void __user *argp = (void __user *)arg;
3542         int r = -ENOTTY;
3543         /*
3544          * This union makes it completely explicit to gcc-3.x
3545          * that these two variables' stack usage should be
3546          * combined, not added together.
3547          */
3548         union {
3549                 struct kvm_pit_state ps;
3550                 struct kvm_pit_state2 ps2;
3551                 struct kvm_pit_config pit_config;
3552         } u;
3553
3554         switch (ioctl) {
3555         case KVM_SET_TSS_ADDR:
3556                 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3557                 break;
3558         case KVM_SET_IDENTITY_MAP_ADDR: {
3559                 u64 ident_addr;
3560
3561                 r = -EFAULT;
3562                 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3563                         goto out;
3564                 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3565                 break;
3566         }
3567         case KVM_SET_NR_MMU_PAGES:
3568                 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3569                 break;
3570         case KVM_GET_NR_MMU_PAGES:
3571                 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3572                 break;
3573         case KVM_CREATE_IRQCHIP: {
3574                 struct kvm_pic *vpic;
3575
3576                 mutex_lock(&kvm->lock);
3577                 r = -EEXIST;
3578                 if (kvm->arch.vpic)
3579                         goto create_irqchip_unlock;
3580                 r = -EINVAL;
3581                 if (atomic_read(&kvm->online_vcpus))
3582                         goto create_irqchip_unlock;
3583                 r = -ENOMEM;
3584                 vpic = kvm_create_pic(kvm);
3585                 if (vpic) {
3586                         r = kvm_ioapic_init(kvm);
3587                         if (r) {
3588                                 mutex_lock(&kvm->slots_lock);
3589                                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3590                                                           &vpic->dev_master);
3591                                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3592                                                           &vpic->dev_slave);
3593                                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3594                                                           &vpic->dev_eclr);
3595                                 mutex_unlock(&kvm->slots_lock);
3596                                 kfree(vpic);
3597                                 goto create_irqchip_unlock;
3598                         }
3599                 } else
3600                         goto create_irqchip_unlock;
3601                 smp_wmb();
3602                 kvm->arch.vpic = vpic;
3603                 smp_wmb();
3604                 r = kvm_setup_default_irq_routing(kvm);
3605                 if (r) {
3606                         mutex_lock(&kvm->slots_lock);
3607                         mutex_lock(&kvm->irq_lock);
3608                         kvm_ioapic_destroy(kvm);
3609                         kvm_destroy_pic(kvm);
3610                         mutex_unlock(&kvm->irq_lock);
3611                         mutex_unlock(&kvm->slots_lock);
3612                 }
3613         create_irqchip_unlock:
3614                 mutex_unlock(&kvm->lock);
3615                 break;
3616         }
3617         case KVM_CREATE_PIT:
3618                 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3619                 goto create_pit;
3620         case KVM_CREATE_PIT2:
3621                 r = -EFAULT;
3622                 if (copy_from_user(&u.pit_config, argp,
3623                                    sizeof(struct kvm_pit_config)))
3624                         goto out;
3625         create_pit:
3626                 mutex_lock(&kvm->slots_lock);
3627                 r = -EEXIST;
3628                 if (kvm->arch.vpit)
3629                         goto create_pit_unlock;
3630                 r = -ENOMEM;
3631                 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3632                 if (kvm->arch.vpit)
3633                         r = 0;
3634         create_pit_unlock:
3635                 mutex_unlock(&kvm->slots_lock);
3636                 break;
3637         case KVM_GET_IRQCHIP: {
3638                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3639                 struct kvm_irqchip *chip;
3640
3641                 chip = memdup_user(argp, sizeof(*chip));
3642                 if (IS_ERR(chip)) {
3643                         r = PTR_ERR(chip);
3644                         goto out;
3645                 }
3646
3647                 r = -ENXIO;
3648                 if (!irqchip_in_kernel(kvm))
3649                         goto get_irqchip_out;
3650                 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3651                 if (r)
3652                         goto get_irqchip_out;
3653                 r = -EFAULT;
3654                 if (copy_to_user(argp, chip, sizeof *chip))
3655                         goto get_irqchip_out;
3656                 r = 0;
3657         get_irqchip_out:
3658                 kfree(chip);
3659                 break;
3660         }
3661         case KVM_SET_IRQCHIP: {
3662                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3663                 struct kvm_irqchip *chip;
3664
3665                 chip = memdup_user(argp, sizeof(*chip));
3666                 if (IS_ERR(chip)) {
3667                         r = PTR_ERR(chip);
3668                         goto out;
3669                 }
3670
3671                 r = -ENXIO;
3672                 if (!irqchip_in_kernel(kvm))
3673                         goto set_irqchip_out;
3674                 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3675                 if (r)
3676                         goto set_irqchip_out;
3677                 r = 0;
3678         set_irqchip_out:
3679                 kfree(chip);
3680                 break;
3681         }
3682         case KVM_GET_PIT: {
3683                 r = -EFAULT;
3684                 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3685                         goto out;
3686                 r = -ENXIO;
3687                 if (!kvm->arch.vpit)
3688                         goto out;
3689                 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3690                 if (r)
3691                         goto out;
3692                 r = -EFAULT;
3693                 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3694                         goto out;
3695                 r = 0;
3696                 break;
3697         }
3698         case KVM_SET_PIT: {
3699                 r = -EFAULT;
3700                 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3701                         goto out;
3702                 r = -ENXIO;
3703                 if (!kvm->arch.vpit)
3704                         goto out;
3705                 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3706                 break;
3707         }
3708         case KVM_GET_PIT2: {
3709                 r = -ENXIO;
3710                 if (!kvm->arch.vpit)
3711                         goto out;
3712                 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3713                 if (r)
3714                         goto out;
3715                 r = -EFAULT;
3716                 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3717                         goto out;
3718                 r = 0;
3719                 break;
3720         }
3721         case KVM_SET_PIT2: {
3722                 r = -EFAULT;
3723                 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3724                         goto out;
3725                 r = -ENXIO;
3726                 if (!kvm->arch.vpit)
3727                         goto out;
3728                 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3729                 break;
3730         }
3731         case KVM_REINJECT_CONTROL: {
3732                 struct kvm_reinject_control control;
3733                 r =  -EFAULT;
3734                 if (copy_from_user(&control, argp, sizeof(control)))
3735                         goto out;
3736                 r = kvm_vm_ioctl_reinject(kvm, &control);
3737                 break;
3738         }
3739         case KVM_XEN_HVM_CONFIG: {
3740                 r = -EFAULT;
3741                 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3742                                    sizeof(struct kvm_xen_hvm_config)))
3743                         goto out;
3744                 r = -EINVAL;
3745                 if (kvm->arch.xen_hvm_config.flags)
3746                         goto out;
3747                 r = 0;
3748                 break;
3749         }
3750         case KVM_SET_CLOCK: {
3751                 struct kvm_clock_data user_ns;
3752                 u64 now_ns;
3753                 s64 delta;
3754
3755                 r = -EFAULT;
3756                 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3757                         goto out;
3758
3759                 r = -EINVAL;
3760                 if (user_ns.flags)
3761                         goto out;
3762
3763                 r = 0;
3764                 local_irq_disable();
3765                 now_ns = get_kernel_ns();
3766                 delta = user_ns.clock - now_ns;
3767                 local_irq_enable();
3768                 kvm->arch.kvmclock_offset = delta;
3769                 break;
3770         }
3771         case KVM_GET_CLOCK: {
3772                 struct kvm_clock_data user_ns;
3773                 u64 now_ns;
3774
3775                 local_irq_disable();
3776                 now_ns = get_kernel_ns();
3777                 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3778                 local_irq_enable();
3779                 user_ns.flags = 0;
3780                 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3781
3782                 r = -EFAULT;
3783                 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3784                         goto out;
3785                 r = 0;
3786                 break;
3787         }
3788
3789         default:
3790                 ;
3791         }
3792 out:
3793         return r;
3794 }
3795
3796 static void kvm_init_msr_list(void)
3797 {
3798         u32 dummy[2];
3799         unsigned i, j;
3800
3801         /* skip the first msrs in the list. KVM-specific */
3802         for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3803                 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3804                         continue;
3805                 if (j < i)
3806                         msrs_to_save[j] = msrs_to_save[i];
3807                 j++;
3808         }
3809         num_msrs_to_save = j;
3810 }
3811
3812 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3813                            const void *v)
3814 {
3815         int handled = 0;
3816         int n;
3817
3818         do {
3819                 n = min(len, 8);
3820                 if (!(vcpu->arch.apic &&
3821                       !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3822                     && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3823                         break;
3824                 handled += n;
3825                 addr += n;
3826                 len -= n;
3827                 v += n;
3828         } while (len);
3829
3830         return handled;
3831 }
3832
3833 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3834 {
3835         int handled = 0;
3836         int n;
3837
3838         do {
3839                 n = min(len, 8);
3840                 if (!(vcpu->arch.apic &&
3841                       !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3842                     && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3843                         break;
3844                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3845                 handled += n;
3846                 addr += n;
3847                 len -= n;
3848                 v += n;
3849         } while (len);
3850
3851         return handled;
3852 }
3853
3854 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3855                         struct kvm_segment *var, int seg)
3856 {
3857         kvm_x86_ops->set_segment(vcpu, var, seg);
3858 }
3859
3860 void kvm_get_segment(struct kvm_vcpu *vcpu,
3861                      struct kvm_segment *var, int seg)
3862 {
3863         kvm_x86_ops->get_segment(vcpu, var, seg);
3864 }
3865
3866 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3867 {
3868         gpa_t t_gpa;
3869         struct x86_exception exception;
3870
3871         BUG_ON(!mmu_is_nested(vcpu));
3872
3873         /* NPT walks are always user-walks */
3874         access |= PFERR_USER_MASK;
3875         t_gpa  = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
3876
3877         return t_gpa;
3878 }
3879
3880 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3881                               struct x86_exception *exception)
3882 {
3883         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3884         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3885 }
3886
3887  gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3888                                 struct x86_exception *exception)
3889 {
3890         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3891         access |= PFERR_FETCH_MASK;
3892         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3893 }
3894
3895 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3896                                struct x86_exception *exception)
3897 {
3898         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3899         access |= PFERR_WRITE_MASK;
3900         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3901 }
3902
3903 /* uses this to access any guest's mapped memory without checking CPL */
3904 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3905                                 struct x86_exception *exception)
3906 {
3907         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
3908 }
3909
3910 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3911                                       struct kvm_vcpu *vcpu, u32 access,
3912                                       struct x86_exception *exception)
3913 {
3914         void *data = val;
3915         int r = X86EMUL_CONTINUE;
3916
3917         while (bytes) {
3918                 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3919                                                             exception);
3920                 unsigned offset = addr & (PAGE_SIZE-1);
3921                 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
3922                 int ret;
3923
3924                 if (gpa == UNMAPPED_GVA)
3925                         return X86EMUL_PROPAGATE_FAULT;
3926                 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
3927                 if (ret < 0) {
3928                         r = X86EMUL_IO_NEEDED;
3929                         goto out;
3930                 }
3931
3932                 bytes -= toread;
3933                 data += toread;
3934                 addr += toread;
3935         }
3936 out:
3937         return r;
3938 }
3939
3940 /* used for instruction fetching */
3941 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3942                                 gva_t addr, void *val, unsigned int bytes,
3943                                 struct x86_exception *exception)
3944 {
3945         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3946         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3947
3948         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3949                                           access | PFERR_FETCH_MASK,
3950                                           exception);
3951 }
3952
3953 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
3954                                gva_t addr, void *val, unsigned int bytes,
3955                                struct x86_exception *exception)
3956 {
3957         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3958         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3959
3960         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3961                                           exception);
3962 }
3963 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
3964
3965 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3966                                       gva_t addr, void *val, unsigned int bytes,
3967                                       struct x86_exception *exception)
3968 {
3969         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3970         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
3971 }
3972
3973 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3974                                        gva_t addr, void *val,
3975                                        unsigned int bytes,
3976                                        struct x86_exception *exception)
3977 {
3978         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3979         void *data = val;
3980         int r = X86EMUL_CONTINUE;
3981
3982         while (bytes) {
3983                 gpa_t gpa =  vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3984                                                              PFERR_WRITE_MASK,
3985                                                              exception);
3986                 unsigned offset = addr & (PAGE_SIZE-1);
3987                 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3988                 int ret;
3989
3990                 if (gpa == UNMAPPED_GVA)
3991                         return X86EMUL_PROPAGATE_FAULT;
3992                 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3993                 if (ret < 0) {
3994                         r = X86EMUL_IO_NEEDED;
3995                         goto out;
3996                 }
3997
3998                 bytes -= towrite;
3999                 data += towrite;
4000                 addr += towrite;
4001         }
4002 out:
4003         return r;
4004 }
4005 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4006
4007 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4008                                 gpa_t *gpa, struct x86_exception *exception,
4009                                 bool write)
4010 {
4011         u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4012                 | (write ? PFERR_WRITE_MASK : 0);
4013
4014         if (vcpu_match_mmio_gva(vcpu, gva)
4015             && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
4016                 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4017                                         (gva & (PAGE_SIZE - 1));
4018                 trace_vcpu_match_mmio(gva, *gpa, write, false);
4019                 return 1;
4020         }
4021
4022         *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4023
4024         if (*gpa == UNMAPPED_GVA)
4025                 return -1;
4026
4027         /* For APIC access vmexit */
4028         if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4029                 return 1;
4030
4031         if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4032                 trace_vcpu_match_mmio(gva, *gpa, write, true);
4033                 return 1;
4034         }
4035
4036         return 0;
4037 }
4038
4039 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4040                         const void *val, int bytes)
4041 {
4042         int ret;
4043
4044         ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
4045         if (ret < 0)
4046                 return 0;
4047         kvm_mmu_pte_write(vcpu, gpa, val, bytes);
4048         return 1;
4049 }
4050
4051 struct read_write_emulator_ops {
4052         int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4053                                   int bytes);
4054         int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4055                                   void *val, int bytes);
4056         int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4057                                int bytes, void *val);
4058         int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4059                                     void *val, int bytes);
4060         bool write;
4061 };
4062
4063 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4064 {
4065         if (vcpu->mmio_read_completed) {
4066                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4067                                vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4068                 vcpu->mmio_read_completed = 0;
4069                 return 1;
4070         }
4071
4072         return 0;
4073 }
4074
4075 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4076                         void *val, int bytes)
4077 {
4078         return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4079 }
4080
4081 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4082                          void *val, int bytes)
4083 {
4084         return emulator_write_phys(vcpu, gpa, val, bytes);
4085 }
4086
4087 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4088 {
4089         trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4090         return vcpu_mmio_write(vcpu, gpa, bytes, val);
4091 }
4092
4093 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4094                           void *val, int bytes)
4095 {
4096         trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4097         return X86EMUL_IO_NEEDED;
4098 }
4099
4100 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4101                            void *val, int bytes)
4102 {
4103         struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4104
4105         memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4106         return X86EMUL_CONTINUE;
4107 }
4108
4109 static const struct read_write_emulator_ops read_emultor = {
4110         .read_write_prepare = read_prepare,
4111         .read_write_emulate = read_emulate,
4112         .read_write_mmio = vcpu_mmio_read,
4113         .read_write_exit_mmio = read_exit_mmio,
4114 };
4115
4116 static const struct read_write_emulator_ops write_emultor = {
4117         .read_write_emulate = write_emulate,
4118         .read_write_mmio = write_mmio,
4119         .read_write_exit_mmio = write_exit_mmio,
4120         .write = true,
4121 };
4122
4123 static int emulator_read_write_onepage(unsigned long addr, void *val,
4124                                        unsigned int bytes,
4125                                        struct x86_exception *exception,
4126                                        struct kvm_vcpu *vcpu,
4127                                        const struct read_write_emulator_ops *ops)
4128 {
4129         gpa_t gpa;
4130         int handled, ret;
4131         bool write = ops->write;
4132         struct kvm_mmio_fragment *frag;
4133
4134         ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4135
4136         if (ret < 0)
4137                 return X86EMUL_PROPAGATE_FAULT;
4138
4139         /* For APIC access vmexit */
4140         if (ret)
4141                 goto mmio;
4142
4143         if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4144                 return X86EMUL_CONTINUE;
4145
4146 mmio:
4147         /*
4148          * Is this MMIO handled locally?
4149          */
4150         handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4151         if (handled == bytes)
4152                 return X86EMUL_CONTINUE;
4153
4154         gpa += handled;
4155         bytes -= handled;
4156         val += handled;
4157
4158         WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4159         frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4160         frag->gpa = gpa;
4161         frag->data = val;
4162         frag->len = bytes;
4163         return X86EMUL_CONTINUE;
4164 }
4165
4166 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4167                         void *val, unsigned int bytes,
4168                         struct x86_exception *exception,
4169                         const struct read_write_emulator_ops *ops)
4170 {
4171         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4172         gpa_t gpa;
4173         int rc;
4174
4175         if (ops->read_write_prepare &&
4176                   ops->read_write_prepare(vcpu, val, bytes))
4177                 return X86EMUL_CONTINUE;
4178
4179         vcpu->mmio_nr_fragments = 0;
4180
4181         /* Crossing a page boundary? */
4182         if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4183                 int now;
4184
4185                 now = -addr & ~PAGE_MASK;
4186                 rc = emulator_read_write_onepage(addr, val, now, exception,
4187                                                  vcpu, ops);
4188
4189                 if (rc != X86EMUL_CONTINUE)
4190                         return rc;
4191                 addr += now;
4192                 val += now;
4193                 bytes -= now;
4194         }
4195
4196         rc = emulator_read_write_onepage(addr, val, bytes, exception,
4197                                          vcpu, ops);
4198         if (rc != X86EMUL_CONTINUE)
4199                 return rc;
4200
4201         if (!vcpu->mmio_nr_fragments)
4202                 return rc;
4203
4204         gpa = vcpu->mmio_fragments[0].gpa;
4205
4206         vcpu->mmio_needed = 1;
4207         vcpu->mmio_cur_fragment = 0;
4208
4209         vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4210         vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4211         vcpu->run->exit_reason = KVM_EXIT_MMIO;
4212         vcpu->run->mmio.phys_addr = gpa;
4213
4214         return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4215 }
4216
4217 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4218                                   unsigned long addr,
4219                                   void *val,
4220                                   unsigned int bytes,
4221                                   struct x86_exception *exception)
4222 {
4223         return emulator_read_write(ctxt, addr, val, bytes,
4224                                    exception, &read_emultor);
4225 }
4226
4227 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4228                             unsigned long addr,
4229                             const void *val,
4230                             unsigned int bytes,
4231                             struct x86_exception *exception)
4232 {
4233         return emulator_read_write(ctxt, addr, (void *)val, bytes,
4234                                    exception, &write_emultor);
4235 }
4236
4237 #define CMPXCHG_TYPE(t, ptr, old, new) \
4238         (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4239
4240 #ifdef CONFIG_X86_64
4241 #  define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4242 #else
4243 #  define CMPXCHG64(ptr, old, new) \
4244         (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4245 #endif
4246
4247 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4248                                      unsigned long addr,
4249                                      const void *old,
4250                                      const void *new,
4251                                      unsigned int bytes,
4252                                      struct x86_exception *exception)
4253 {
4254         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4255         gpa_t gpa;
4256         struct page *page;
4257         char *kaddr;
4258         bool exchanged;
4259
4260         /* guests cmpxchg8b have to be emulated atomically */
4261         if (bytes > 8 || (bytes & (bytes - 1)))
4262                 goto emul_write;
4263
4264         gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4265
4266         if (gpa == UNMAPPED_GVA ||
4267             (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4268                 goto emul_write;
4269
4270         if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4271                 goto emul_write;
4272
4273         page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4274         if (is_error_page(page))
4275                 goto emul_write;
4276
4277         kaddr = kmap_atomic(page);
4278         kaddr += offset_in_page(gpa);
4279         switch (bytes) {
4280         case 1:
4281                 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4282                 break;
4283         case 2:
4284                 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4285                 break;
4286         case 4:
4287                 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4288                 break;
4289         case 8:
4290                 exchanged = CMPXCHG64(kaddr, old, new);
4291                 break;
4292         default:
4293                 BUG();
4294         }
4295         kunmap_atomic(kaddr);
4296         kvm_release_page_dirty(page);
4297
4298         if (!exchanged)
4299                 return X86EMUL_CMPXCHG_FAILED;
4300
4301         kvm_mmu_pte_write(vcpu, gpa, new, bytes);
4302
4303         return X86EMUL_CONTINUE;
4304
4305 emul_write:
4306         printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4307
4308         return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4309 }
4310
4311 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4312 {
4313         /* TODO: String I/O for in kernel device */
4314         int r;
4315
4316         if (vcpu->arch.pio.in)
4317                 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4318                                     vcpu->arch.pio.size, pd);
4319         else
4320                 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4321                                      vcpu->arch.pio.port, vcpu->arch.pio.size,
4322                                      pd);
4323         return r;
4324 }
4325
4326 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4327                                unsigned short port, void *val,
4328                                unsigned int count, bool in)
4329 {
4330         trace_kvm_pio(!in, port, size, count);
4331
4332         vcpu->arch.pio.port = port;
4333         vcpu->arch.pio.in = in;
4334         vcpu->arch.pio.count  = count;
4335         vcpu->arch.pio.size = size;
4336
4337         if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4338                 vcpu->arch.pio.count = 0;
4339                 return 1;
4340         }
4341
4342         vcpu->run->exit_reason = KVM_EXIT_IO;
4343         vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4344         vcpu->run->io.size = size;
4345         vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4346         vcpu->run->io.count = count;
4347         vcpu->run->io.port = port;
4348
4349         return 0;
4350 }
4351
4352 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4353                                     int size, unsigned short port, void *val,
4354                                     unsigned int count)
4355 {
4356         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4357         int ret;
4358
4359         if (vcpu->arch.pio.count)
4360                 goto data_avail;
4361
4362         ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4363         if (ret) {
4364 data_avail:
4365                 memcpy(val, vcpu->arch.pio_data, size * count);
4366                 vcpu->arch.pio.count = 0;
4367                 return 1;
4368         }
4369
4370         return 0;
4371 }
4372
4373 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4374                                      int size, unsigned short port,
4375                                      const void *val, unsigned int count)
4376 {
4377         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4378
4379         memcpy(vcpu->arch.pio_data, val, size * count);
4380         return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4381 }
4382
4383 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4384 {
4385         return kvm_x86_ops->get_segment_base(vcpu, seg);
4386 }
4387
4388 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4389 {
4390         kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4391 }
4392
4393 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4394 {
4395         if (!need_emulate_wbinvd(vcpu))
4396                 return X86EMUL_CONTINUE;
4397
4398         if (kvm_x86_ops->has_wbinvd_exit()) {
4399                 int cpu = get_cpu();
4400
4401                 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4402                 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4403                                 wbinvd_ipi, NULL, 1);
4404                 put_cpu();
4405                 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4406         } else
4407                 wbinvd();
4408         return X86EMUL_CONTINUE;
4409 }
4410 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4411
4412 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4413 {
4414         kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4415 }
4416
4417 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
4418 {
4419         return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4420 }
4421
4422 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
4423 {
4424
4425         return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4426 }
4427
4428 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4429 {
4430         return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4431 }
4432
4433 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4434 {
4435         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4436         unsigned long value;
4437
4438         switch (cr) {
4439         case 0:
4440                 value = kvm_read_cr0(vcpu);
4441                 break;
4442         case 2:
4443                 value = vcpu->arch.cr2;
4444                 break;
4445         case 3:
4446                 value = kvm_read_cr3(vcpu);
4447                 break;
4448         case 4:
4449                 value = kvm_read_cr4(vcpu);
4450                 break;
4451         case 8:
4452                 value = kvm_get_cr8(vcpu);
4453                 break;
4454         default:
4455                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4456                 return 0;
4457         }
4458
4459         return value;
4460 }
4461
4462 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4463 {
4464         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4465         int res = 0;
4466
4467         switch (cr) {
4468         case 0:
4469                 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4470                 break;
4471         case 2:
4472                 vcpu->arch.cr2 = val;
4473                 break;
4474         case 3:
4475                 res = kvm_set_cr3(vcpu, val);
4476                 break;
4477         case 4:
4478                 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4479                 break;
4480         case 8:
4481                 res = kvm_set_cr8(vcpu, val);
4482                 break;
4483         default:
4484                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4485                 res = -1;
4486         }
4487
4488         return res;
4489 }
4490
4491 static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4492 {
4493         kvm_set_rflags(emul_to_vcpu(ctxt), val);
4494 }
4495
4496 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4497 {
4498         return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4499 }
4500
4501 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4502 {
4503         kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4504 }
4505
4506 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4507 {
4508         kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4509 }
4510
4511 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4512 {
4513         kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4514 }
4515
4516 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4517 {
4518         kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4519 }
4520
4521 static unsigned long emulator_get_cached_segment_base(
4522         struct x86_emulate_ctxt *ctxt, int seg)
4523 {
4524         return get_segment_base(emul_to_vcpu(ctxt), seg);
4525 }
4526
4527 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4528                                  struct desc_struct *desc, u32 *base3,
4529                                  int seg)
4530 {
4531         struct kvm_segment var;
4532
4533         kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4534         *selector = var.selector;
4535
4536         if (var.unusable) {
4537                 memset(desc, 0, sizeof(*desc));
4538                 return false;
4539         }
4540
4541         if (var.g)
4542                 var.limit >>= 12;
4543         set_desc_limit(desc, var.limit);
4544         set_desc_base(desc, (unsigned long)var.base);
4545 #ifdef CONFIG_X86_64
4546         if (base3)
4547                 *base3 = var.base >> 32;
4548 #endif
4549         desc->type = var.type;
4550         desc->s = var.s;
4551         desc->dpl = var.dpl;
4552         desc->p = var.present;
4553         desc->avl = var.avl;
4554         desc->l = var.l;
4555         desc->d = var.db;
4556         desc->g = var.g;
4557
4558         return true;
4559 }
4560
4561 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4562                                  struct desc_struct *desc, u32 base3,
4563                                  int seg)
4564 {
4565         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4566         struct kvm_segment var;
4567
4568         var.selector = selector;
4569         var.base = get_desc_base(desc);
4570 #ifdef CONFIG_X86_64
4571         var.base |= ((u64)base3) << 32;
4572 #endif
4573         var.limit = get_desc_limit(desc);
4574         if (desc->g)
4575                 var.limit = (var.limit << 12) | 0xfff;
4576         var.type = desc->type;
4577         var.present = desc->p;
4578         var.dpl = desc->dpl;
4579         var.db = desc->d;
4580         var.s = desc->s;
4581         var.l = desc->l;
4582         var.g = desc->g;
4583         var.avl = desc->avl;
4584         var.present = desc->p;
4585         var.unusable = !var.present;
4586         var.padding = 0;
4587
4588         kvm_set_segment(vcpu, &var, seg);
4589         return;
4590 }
4591
4592 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4593                             u32 msr_index, u64 *pdata)
4594 {
4595         return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4596 }
4597
4598 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4599                             u32 msr_index, u64 data)
4600 {
4601         struct msr_data msr;
4602
4603         msr.data = data;
4604         msr.index = msr_index;
4605         msr.host_initiated = false;
4606         return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4607 }
4608
4609 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4610                              u32 pmc, u64 *pdata)
4611 {
4612         return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4613 }
4614
4615 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4616 {
4617         emul_to_vcpu(ctxt)->arch.halt_request = 1;
4618 }
4619
4620 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4621 {
4622         preempt_disable();
4623         kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4624         /*
4625          * CR0.TS may reference the host fpu state, not the guest fpu state,
4626          * so it may be clear at this point.
4627          */
4628         clts();
4629 }
4630
4631 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4632 {
4633         preempt_enable();
4634 }
4635
4636 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4637                               struct x86_instruction_info *info,
4638                               enum x86_intercept_stage stage)
4639 {
4640         return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4641 }
4642
4643 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4644                                u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4645 {
4646         kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4647 }
4648
4649 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4650 {
4651         return kvm_register_read(emul_to_vcpu(ctxt), reg);
4652 }
4653
4654 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4655 {
4656         kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4657 }
4658
4659 static const struct x86_emulate_ops emulate_ops = {
4660         .read_gpr            = emulator_read_gpr,
4661         .write_gpr           = emulator_write_gpr,
4662         .read_std            = kvm_read_guest_virt_system,
4663         .write_std           = kvm_write_guest_virt_system,
4664         .fetch               = kvm_fetch_guest_virt,
4665         .read_emulated       = emulator_read_emulated,
4666         .write_emulated      = emulator_write_emulated,
4667         .cmpxchg_emulated    = emulator_cmpxchg_emulated,
4668         .invlpg              = emulator_invlpg,
4669         .pio_in_emulated     = emulator_pio_in_emulated,
4670         .pio_out_emulated    = emulator_pio_out_emulated,
4671         .get_segment         = emulator_get_segment,
4672         .set_segment         = emulator_set_segment,
4673         .get_cached_segment_base = emulator_get_cached_segment_base,
4674         .get_gdt             = emulator_get_gdt,
4675         .get_idt             = emulator_get_idt,
4676         .set_gdt             = emulator_set_gdt,
4677         .set_idt             = emulator_set_idt,
4678         .get_cr              = emulator_get_cr,
4679         .set_cr              = emulator_set_cr,
4680         .set_rflags          = emulator_set_rflags,
4681         .cpl                 = emulator_get_cpl,
4682         .get_dr              = emulator_get_dr,
4683         .set_dr              = emulator_set_dr,
4684         .set_msr             = emulator_set_msr,
4685         .get_msr             = emulator_get_msr,
4686         .read_pmc            = emulator_read_pmc,
4687         .halt                = emulator_halt,
4688         .wbinvd              = emulator_wbinvd,
4689         .fix_hypercall       = emulator_fix_hypercall,
4690         .get_fpu             = emulator_get_fpu,
4691         .put_fpu             = emulator_put_fpu,
4692         .intercept           = emulator_intercept,
4693         .get_cpuid           = emulator_get_cpuid,
4694 };
4695
4696 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4697 {
4698         u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4699         /*
4700          * an sti; sti; sequence only disable interrupts for the first
4701          * instruction. So, if the last instruction, be it emulated or
4702          * not, left the system with the INT_STI flag enabled, it
4703          * means that the last instruction is an sti. We should not
4704          * leave the flag on in this case. The same goes for mov ss
4705          */
4706         if (!(int_shadow & mask))
4707                 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4708 }
4709
4710 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4711 {
4712         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4713         if (ctxt->exception.vector == PF_VECTOR)
4714                 kvm_propagate_fault(vcpu, &ctxt->exception);
4715         else if (ctxt->exception.error_code_valid)
4716                 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4717                                       ctxt->exception.error_code);
4718         else
4719                 kvm_queue_exception(vcpu, ctxt->exception.vector);
4720 }
4721
4722 static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4723 {
4724         memset(&ctxt->twobyte, 0,
4725                (void *)&ctxt->_regs - (void *)&ctxt->twobyte);
4726
4727         ctxt->fetch.start = 0;
4728         ctxt->fetch.end = 0;
4729         ctxt->io_read.pos = 0;
4730         ctxt->io_read.end = 0;
4731         ctxt->mem_read.pos = 0;
4732         ctxt->mem_read.end = 0;
4733 }
4734
4735 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4736 {
4737         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4738         int cs_db, cs_l;
4739
4740         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4741
4742         ctxt->eflags = kvm_get_rflags(vcpu);
4743         ctxt->eip = kvm_rip_read(vcpu);
4744         ctxt->mode = (!is_protmode(vcpu))               ? X86EMUL_MODE_REAL :
4745                      (ctxt->eflags & X86_EFLAGS_VM)     ? X86EMUL_MODE_VM86 :
4746                      cs_l                               ? X86EMUL_MODE_PROT64 :
4747                      cs_db                              ? X86EMUL_MODE_PROT32 :
4748                                                           X86EMUL_MODE_PROT16;
4749         ctxt->guest_mode = is_guest_mode(vcpu);
4750
4751         init_decode_cache(ctxt);
4752         vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4753 }
4754
4755 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4756 {
4757         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4758         int ret;
4759
4760         init_emulate_ctxt(vcpu);
4761
4762         ctxt->op_bytes = 2;
4763         ctxt->ad_bytes = 2;
4764         ctxt->_eip = ctxt->eip + inc_eip;
4765         ret = emulate_int_real(ctxt, irq);
4766
4767         if (ret != X86EMUL_CONTINUE)
4768                 return EMULATE_FAIL;
4769
4770         ctxt->eip = ctxt->_eip;
4771         kvm_rip_write(vcpu, ctxt->eip);
4772         kvm_set_rflags(vcpu, ctxt->eflags);
4773
4774         if (irq == NMI_VECTOR)
4775                 vcpu->arch.nmi_pending = 0;
4776         else
4777                 vcpu->arch.interrupt.pending = false;
4778
4779         return EMULATE_DONE;
4780 }
4781 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4782
4783 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4784 {
4785         int r = EMULATE_DONE;
4786
4787         ++vcpu->stat.insn_emulation_fail;
4788         trace_kvm_emulate_insn_failed(vcpu);
4789         if (!is_guest_mode(vcpu)) {
4790                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4791                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4792                 vcpu->run->internal.ndata = 0;
4793                 r = EMULATE_FAIL;
4794         }
4795         kvm_queue_exception(vcpu, UD_VECTOR);
4796
4797         return r;
4798 }
4799
4800 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
4801                                   bool write_fault_to_shadow_pgtable,
4802                                   int emulation_type)
4803 {
4804         gpa_t gpa = cr2;
4805         pfn_t pfn;
4806
4807         if (emulation_type & EMULTYPE_NO_REEXECUTE)
4808                 return false;
4809
4810         if (!vcpu->arch.mmu.direct_map) {
4811                 /*
4812                  * Write permission should be allowed since only
4813                  * write access need to be emulated.
4814                  */
4815                 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4816
4817                 /*
4818                  * If the mapping is invalid in guest, let cpu retry
4819                  * it to generate fault.
4820                  */
4821                 if (gpa == UNMAPPED_GVA)
4822                         return true;
4823         }
4824
4825         /*
4826          * Do not retry the unhandleable instruction if it faults on the
4827          * readonly host memory, otherwise it will goto a infinite loop:
4828          * retry instruction -> write #PF -> emulation fail -> retry
4829          * instruction -> ...
4830          */
4831         pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
4832
4833         /*
4834          * If the instruction failed on the error pfn, it can not be fixed,
4835          * report the error to userspace.
4836          */
4837         if (is_error_noslot_pfn(pfn))
4838                 return false;
4839
4840         kvm_release_pfn_clean(pfn);
4841
4842         /* The instructions are well-emulated on direct mmu. */
4843         if (vcpu->arch.mmu.direct_map) {
4844                 unsigned int indirect_shadow_pages;
4845
4846                 spin_lock(&vcpu->kvm->mmu_lock);
4847                 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4848                 spin_unlock(&vcpu->kvm->mmu_lock);
4849
4850                 if (indirect_shadow_pages)
4851                         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4852
4853                 return true;
4854         }
4855
4856         /*
4857          * if emulation was due to access to shadowed page table
4858          * and it failed try to unshadow page and re-enter the
4859          * guest to let CPU execute the instruction.
4860          */
4861         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4862
4863         /*
4864          * If the access faults on its page table, it can not
4865          * be fixed by unprotecting shadow page and it should
4866          * be reported to userspace.
4867          */
4868         return !write_fault_to_shadow_pgtable;
4869 }
4870
4871 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4872                               unsigned long cr2,  int emulation_type)
4873 {
4874         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4875         unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4876
4877         last_retry_eip = vcpu->arch.last_retry_eip;
4878         last_retry_addr = vcpu->arch.last_retry_addr;
4879
4880         /*
4881          * If the emulation is caused by #PF and it is non-page_table
4882          * writing instruction, it means the VM-EXIT is caused by shadow
4883          * page protected, we can zap the shadow page and retry this
4884          * instruction directly.
4885          *
4886          * Note: if the guest uses a non-page-table modifying instruction
4887          * on the PDE that points to the instruction, then we will unmap
4888          * the instruction and go to an infinite loop. So, we cache the
4889          * last retried eip and the last fault address, if we meet the eip
4890          * and the address again, we can break out of the potential infinite
4891          * loop.
4892          */
4893         vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4894
4895         if (!(emulation_type & EMULTYPE_RETRY))
4896                 return false;
4897
4898         if (x86_page_table_writing_insn(ctxt))
4899                 return false;
4900
4901         if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4902                 return false;
4903
4904         vcpu->arch.last_retry_eip = ctxt->eip;
4905         vcpu->arch.last_retry_addr = cr2;
4906
4907         if (!vcpu->arch.mmu.direct_map)
4908                 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4909
4910         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4911
4912         return true;
4913 }
4914
4915 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
4916 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
4917
4918 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4919                             unsigned long cr2,
4920                             int emulation_type,
4921                             void *insn,
4922                             int insn_len)
4923 {
4924         int r;
4925         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4926         bool writeback = true;
4927         bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
4928
4929         /*
4930          * Clear write_fault_to_shadow_pgtable here to ensure it is
4931          * never reused.
4932          */
4933         vcpu->arch.write_fault_to_shadow_pgtable = false;
4934         kvm_clear_exception_queue(vcpu);
4935
4936         if (!(emulation_type & EMULTYPE_NO_DECODE)) {
4937                 init_emulate_ctxt(vcpu);
4938                 ctxt->interruptibility = 0;
4939                 ctxt->have_exception = false;
4940                 ctxt->perm_ok = false;
4941
4942                 ctxt->only_vendor_specific_insn
4943                         = emulation_type & EMULTYPE_TRAP_UD;
4944
4945                 r = x86_decode_insn(ctxt, insn, insn_len);
4946
4947                 trace_kvm_emulate_insn_start(vcpu);
4948                 ++vcpu->stat.insn_emulation;
4949                 if (r != EMULATION_OK)  {
4950                         if (emulation_type & EMULTYPE_TRAP_UD)
4951                                 return EMULATE_FAIL;
4952                         if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
4953                                                 emulation_type))
4954                                 return EMULATE_DONE;
4955                         if (emulation_type & EMULTYPE_SKIP)
4956                                 return EMULATE_FAIL;
4957                         return handle_emulation_failure(vcpu);
4958                 }
4959         }
4960
4961         if (emulation_type & EMULTYPE_SKIP) {
4962                 kvm_rip_write(vcpu, ctxt->_eip);
4963                 return EMULATE_DONE;
4964         }
4965
4966         if (retry_instruction(ctxt, cr2, emulation_type))
4967                 return EMULATE_DONE;
4968
4969         /* this is needed for vmware backdoor interface to work since it
4970            changes registers values  during IO operation */
4971         if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4972                 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4973                 emulator_invalidate_register_cache(ctxt);
4974         }
4975
4976 restart:
4977         r = x86_emulate_insn(ctxt);
4978
4979         if (r == EMULATION_INTERCEPTED)
4980                 return EMULATE_DONE;
4981
4982         if (r == EMULATION_FAILED) {
4983                 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
4984                                         emulation_type))
4985                         return EMULATE_DONE;
4986
4987                 return handle_emulation_failure(vcpu);
4988         }
4989
4990         if (ctxt->have_exception) {
4991                 inject_emulated_exception(vcpu);
4992                 r = EMULATE_DONE;
4993         } else if (vcpu->arch.pio.count) {
4994                 if (!vcpu->arch.pio.in)
4995                         vcpu->arch.pio.count = 0;
4996                 else {
4997                         writeback = false;
4998                         vcpu->arch.complete_userspace_io = complete_emulated_pio;
4999                 }
5000                 r = EMULATE_DO_MMIO;
5001         } else if (vcpu->mmio_needed) {
5002                 if (!vcpu->mmio_is_write)
5003                         writeback = false;
5004                 r = EMULATE_DO_MMIO;
5005                 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5006         } else if (r == EMULATION_RESTART)
5007                 goto restart;
5008         else
5009                 r = EMULATE_DONE;
5010
5011         if (writeback) {
5012                 toggle_interruptibility(vcpu, ctxt->interruptibility);
5013                 kvm_set_rflags(vcpu, ctxt->eflags);
5014                 kvm_make_request(KVM_REQ_EVENT, vcpu);
5015                 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5016                 kvm_rip_write(vcpu, ctxt->eip);
5017         } else
5018                 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5019
5020         return r;
5021 }
5022 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5023
5024 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5025 {
5026         unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5027         int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5028                                             size, port, &val, 1);
5029         /* do not return to emulator after return from userspace */
5030         vcpu->arch.pio.count = 0;
5031         return ret;
5032 }
5033 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5034
5035 static void tsc_bad(void *info)
5036 {
5037         __this_cpu_write(cpu_tsc_khz, 0);
5038 }
5039
5040 static void tsc_khz_changed(void *data)
5041 {
5042         struct cpufreq_freqs *freq = data;
5043         unsigned long khz = 0;
5044
5045         if (data)
5046                 khz = freq->new;
5047         else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5048                 khz = cpufreq_quick_get(raw_smp_processor_id());
5049         if (!khz)
5050                 khz = tsc_khz;
5051         __this_cpu_write(cpu_tsc_khz, khz);
5052 }
5053
5054 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5055                                      void *data)
5056 {
5057         struct cpufreq_freqs *freq = data;
5058         struct kvm *kvm;
5059         struct kvm_vcpu *vcpu;
5060         int i, send_ipi = 0;
5061
5062         /*
5063          * We allow guests to temporarily run on slowing clocks,
5064          * provided we notify them after, or to run on accelerating
5065          * clocks, provided we notify them before.  Thus time never
5066          * goes backwards.
5067          *
5068          * However, we have a problem.  We can't atomically update
5069          * the frequency of a given CPU from this function; it is
5070          * merely a notifier, which can be called from any CPU.
5071          * Changing the TSC frequency at arbitrary points in time
5072          * requires a recomputation of local variables related to
5073          * the TSC for each VCPU.  We must flag these local variables
5074          * to be updated and be sure the update takes place with the
5075          * new frequency before any guests proceed.
5076          *
5077          * Unfortunately, the combination of hotplug CPU and frequency
5078          * change creates an intractable locking scenario; the order
5079          * of when these callouts happen is undefined with respect to
5080          * CPU hotplug, and they can race with each other.  As such,
5081          * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5082          * undefined; you can actually have a CPU frequency change take
5083          * place in between the computation of X and the setting of the
5084          * variable.  To protect against this problem, all updates of
5085          * the per_cpu tsc_khz variable are done in an interrupt
5086          * protected IPI, and all callers wishing to update the value
5087          * must wait for a synchronous IPI to complete (which is trivial
5088          * if the caller is on the CPU already).  This establishes the
5089          * necessary total order on variable updates.
5090          *
5091          * Note that because a guest time update may take place
5092          * anytime after the setting of the VCPU's request bit, the
5093          * correct TSC value must be set before the request.  However,
5094          * to ensure the update actually makes it to any guest which
5095          * starts running in hardware virtualization between the set
5096          * and the acquisition of the spinlock, we must also ping the
5097          * CPU after setting the request bit.
5098          *
5099          */
5100
5101         if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5102                 return 0;
5103         if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5104                 return 0;
5105
5106         smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5107
5108         raw_spin_lock(&kvm_lock);
5109         list_for_each_entry(kvm, &vm_list, vm_list) {
5110                 kvm_for_each_vcpu(i, vcpu, kvm) {
5111                         if (vcpu->cpu != freq->cpu)
5112                                 continue;
5113                         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5114                         if (vcpu->cpu != smp_processor_id())
5115                                 send_ipi = 1;
5116                 }
5117         }
5118         raw_spin_unlock(&kvm_lock);
5119
5120         if (freq->old < freq->new && send_ipi) {
5121                 /*
5122                  * We upscale the frequency.  Must make the guest
5123                  * doesn't see old kvmclock values while running with
5124                  * the new frequency, otherwise we risk the guest sees
5125                  * time go backwards.
5126                  *
5127                  * In case we update the frequency for another cpu
5128                  * (which might be in guest context) send an interrupt
5129                  * to kick the cpu out of guest context.  Next time
5130                  * guest context is entered kvmclock will be updated,
5131                  * so the guest will not see stale values.
5132                  */
5133                 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5134         }
5135         return 0;
5136 }
5137
5138 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5139         .notifier_call  = kvmclock_cpufreq_notifier
5140 };
5141
5142 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5143                                         unsigned long action, void *hcpu)
5144 {
5145         unsigned int cpu = (unsigned long)hcpu;
5146
5147         switch (action) {
5148                 case CPU_ONLINE:
5149                 case CPU_DOWN_FAILED:
5150                         smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5151                         break;
5152                 case CPU_DOWN_PREPARE:
5153                         smp_call_function_single(cpu, tsc_bad, NULL, 1);
5154                         break;
5155         }
5156         return NOTIFY_OK;
5157 }
5158
5159 static struct notifier_block kvmclock_cpu_notifier_block = {
5160         .notifier_call  = kvmclock_cpu_notifier,
5161         .priority = -INT_MAX
5162 };
5163
5164 static void kvm_timer_init(void)
5165 {
5166         int cpu;
5167
5168         max_tsc_khz = tsc_khz;
5169         register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5170         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5171 #ifdef CONFIG_CPU_FREQ
5172                 struct cpufreq_policy policy;
5173                 memset(&policy, 0, sizeof(policy));
5174                 cpu = get_cpu();
5175                 cpufreq_get_policy(&policy, cpu);
5176                 if (policy.cpuinfo.max_freq)
5177                         max_tsc_khz = policy.cpuinfo.max_freq;
5178                 put_cpu();
5179 #endif
5180                 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5181                                           CPUFREQ_TRANSITION_NOTIFIER);
5182         }
5183         pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5184         for_each_online_cpu(cpu)
5185                 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5186 }
5187
5188 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5189
5190 int kvm_is_in_guest(void)
5191 {
5192         return __this_cpu_read(current_vcpu) != NULL;
5193 }
5194
5195 static int kvm_is_user_mode(void)
5196 {
5197         int user_mode = 3;
5198
5199         if (__this_cpu_read(current_vcpu))
5200                 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5201
5202         return user_mode != 0;
5203 }
5204
5205 static unsigned long kvm_get_guest_ip(void)
5206 {
5207         unsigned long ip = 0;
5208
5209         if (__this_cpu_read(current_vcpu))
5210                 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5211
5212         return ip;
5213 }
5214
5215 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5216         .is_in_guest            = kvm_is_in_guest,
5217         .is_user_mode           = kvm_is_user_mode,
5218         .get_guest_ip           = kvm_get_guest_ip,
5219 };
5220
5221 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5222 {
5223         __this_cpu_write(current_vcpu, vcpu);
5224 }
5225 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5226
5227 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5228 {
5229         __this_cpu_write(current_vcpu, NULL);
5230 }
5231 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5232
5233 static void kvm_set_mmio_spte_mask(void)
5234 {
5235         u64 mask;
5236         int maxphyaddr = boot_cpu_data.x86_phys_bits;
5237
5238         /*
5239          * Set the reserved bits and the present bit of an paging-structure
5240          * entry to generate page fault with PFER.RSV = 1.
5241          */
5242         mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
5243         mask |= 1ull;
5244
5245 #ifdef CONFIG_X86_64
5246         /*
5247          * If reserved bit is not supported, clear the present bit to disable
5248          * mmio page fault.
5249          */
5250         if (maxphyaddr == 52)
5251                 mask &= ~1ull;
5252 #endif
5253
5254         kvm_mmu_set_mmio_spte_mask(mask);
5255 }
5256
5257 #ifdef CONFIG_X86_64
5258 static void pvclock_gtod_update_fn(struct work_struct *work)
5259 {
5260         struct kvm *kvm;
5261
5262         struct kvm_vcpu *vcpu;
5263         int i;
5264
5265         raw_spin_lock(&kvm_lock);
5266         list_for_each_entry(kvm, &vm_list, vm_list)
5267                 kvm_for_each_vcpu(i, vcpu, kvm)
5268                         set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5269         atomic_set(&kvm_guest_has_master_clock, 0);
5270         raw_spin_unlock(&kvm_lock);
5271 }
5272
5273 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5274
5275 /*
5276  * Notification about pvclock gtod data update.
5277  */
5278 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5279                                void *priv)
5280 {
5281         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5282         struct timekeeper *tk = priv;
5283
5284         update_pvclock_gtod(tk);
5285
5286         /* disable master clock if host does not trust, or does not
5287          * use, TSC clocksource
5288          */
5289         if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5290             atomic_read(&kvm_guest_has_master_clock) != 0)
5291                 queue_work(system_long_wq, &pvclock_gtod_work);
5292
5293         return 0;
5294 }
5295
5296 static struct notifier_block pvclock_gtod_notifier = {
5297         .notifier_call = pvclock_gtod_notify,
5298 };
5299 #endif
5300
5301 int kvm_arch_init(void *opaque)
5302 {
5303         int r;
5304         struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
5305
5306         if (kvm_x86_ops) {
5307                 printk(KERN_ERR "kvm: already loaded the other module\n");
5308                 r = -EEXIST;
5309                 goto out;
5310         }
5311
5312         if (!ops->cpu_has_kvm_support()) {
5313                 printk(KERN_ERR "kvm: no hardware support\n");
5314                 r = -EOPNOTSUPP;
5315                 goto out;
5316         }
5317         if (ops->disabled_by_bios()) {
5318                 printk(KERN_ERR "kvm: disabled by bios\n");
5319                 r = -EOPNOTSUPP;
5320                 goto out;
5321         }
5322
5323         r = -ENOMEM;
5324         shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5325         if (!shared_msrs) {
5326                 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5327                 goto out;
5328         }
5329
5330         r = kvm_mmu_module_init();
5331         if (r)
5332                 goto out_free_percpu;
5333
5334         kvm_set_mmio_spte_mask();
5335         kvm_init_msr_list();
5336
5337         kvm_x86_ops = ops;
5338         kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5339                         PT_DIRTY_MASK, PT64_NX_MASK, 0);
5340
5341         kvm_timer_init();
5342
5343         perf_register_guest_info_callbacks(&kvm_guest_cbs);
5344
5345         if (cpu_has_xsave)
5346                 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5347
5348         kvm_lapic_init();
5349 #ifdef CONFIG_X86_64
5350         pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5351 #endif
5352
5353         return 0;
5354
5355 out_free_percpu:
5356         free_percpu(shared_msrs);
5357 out:
5358         return r;
5359 }
5360
5361 void kvm_arch_exit(void)
5362 {
5363         perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5364
5365         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5366                 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5367                                             CPUFREQ_TRANSITION_NOTIFIER);
5368         unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5369 #ifdef CONFIG_X86_64
5370         pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5371 #endif
5372         kvm_x86_ops = NULL;
5373         kvm_mmu_module_exit();
5374         free_percpu(shared_msrs);
5375 }
5376
5377 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5378 {
5379         ++vcpu->stat.halt_exits;
5380         if (irqchip_in_kernel(vcpu->kvm)) {
5381                 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5382                 return 1;
5383         } else {
5384                 vcpu->run->exit_reason = KVM_EXIT_HLT;
5385                 return 0;
5386         }
5387 }
5388 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5389
5390 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5391 {
5392         u64 param, ingpa, outgpa, ret;
5393         uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5394         bool fast, longmode;
5395         int cs_db, cs_l;
5396
5397         /*
5398          * hypercall generates UD from non zero cpl and real mode
5399          * per HYPER-V spec
5400          */
5401         if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
5402                 kvm_queue_exception(vcpu, UD_VECTOR);
5403                 return 0;
5404         }
5405
5406         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5407         longmode = is_long_mode(vcpu) && cs_l == 1;
5408
5409         if (!longmode) {
5410                 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5411                         (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5412                 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5413                         (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5414                 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5415                         (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
5416         }
5417 #ifdef CONFIG_X86_64
5418         else {
5419                 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5420                 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5421                 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5422         }
5423 #endif
5424
5425         code = param & 0xffff;
5426         fast = (param >> 16) & 0x1;
5427         rep_cnt = (param >> 32) & 0xfff;
5428         rep_idx = (param >> 48) & 0xfff;
5429
5430         trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5431
5432         switch (code) {
5433         case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5434                 kvm_vcpu_on_spin(vcpu);
5435                 break;
5436         default:
5437                 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5438                 break;
5439         }
5440
5441         ret = res | (((u64)rep_done & 0xfff) << 32);
5442         if (longmode) {
5443                 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5444         } else {
5445                 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5446                 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5447         }
5448
5449         return 1;
5450 }
5451
5452 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5453 {
5454         unsigned long nr, a0, a1, a2, a3, ret;
5455         int r = 1;
5456
5457         if (kvm_hv_hypercall_enabled(vcpu->kvm))
5458                 return kvm_hv_hypercall(vcpu);
5459
5460         nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5461         a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5462         a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5463         a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5464         a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5465
5466         trace_kvm_hypercall(nr, a0, a1, a2, a3);
5467
5468         if (!is_long_mode(vcpu)) {
5469                 nr &= 0xFFFFFFFF;
5470                 a0 &= 0xFFFFFFFF;
5471                 a1 &= 0xFFFFFFFF;
5472                 a2 &= 0xFFFFFFFF;
5473                 a3 &= 0xFFFFFFFF;
5474         }
5475
5476         if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5477                 ret = -KVM_EPERM;
5478                 goto out;
5479         }
5480
5481         switch (nr) {
5482         case KVM_HC_VAPIC_POLL_IRQ:
5483                 ret = 0;
5484                 break;
5485         default:
5486                 ret = -KVM_ENOSYS;
5487                 break;
5488         }
5489 out:
5490         kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5491         ++vcpu->stat.hypercalls;
5492         return r;
5493 }
5494 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5495
5496 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5497 {
5498         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5499         char instruction[3];
5500         unsigned long rip = kvm_rip_read(vcpu);
5501
5502         /*
5503          * Blow out the MMU to ensure that no other VCPU has an active mapping
5504          * to ensure that the updated hypercall appears atomically across all
5505          * VCPUs.
5506          */
5507         kvm_mmu_zap_all(vcpu->kvm);
5508
5509         kvm_x86_ops->patch_hypercall(vcpu, instruction);
5510
5511         return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5512 }
5513
5514 /*
5515  * Check if userspace requested an interrupt window, and that the
5516  * interrupt window is open.
5517  *
5518  * No need to exit to userspace if we already have an interrupt queued.
5519  */
5520 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5521 {
5522         return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5523                 vcpu->run->request_interrupt_window &&
5524                 kvm_arch_interrupt_allowed(vcpu));
5525 }
5526
5527 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5528 {
5529         struct kvm_run *kvm_run = vcpu->run;
5530
5531         kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5532         kvm_run->cr8 = kvm_get_cr8(vcpu);
5533         kvm_run->apic_base = kvm_get_apic_base(vcpu);
5534         if (irqchip_in_kernel(vcpu->kvm))
5535                 kvm_run->ready_for_interrupt_injection = 1;
5536         else
5537                 kvm_run->ready_for_interrupt_injection =
5538                         kvm_arch_interrupt_allowed(vcpu) &&
5539                         !kvm_cpu_has_interrupt(vcpu) &&
5540                         !kvm_event_needs_reinjection(vcpu);
5541 }
5542
5543 static int vapic_enter(struct kvm_vcpu *vcpu)
5544 {
5545         struct kvm_lapic *apic = vcpu->arch.apic;
5546         struct page *page;
5547
5548         if (!apic || !apic->vapic_addr)
5549                 return 0;
5550
5551         page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5552         if (is_error_page(page))
5553                 return -EFAULT;
5554
5555         vcpu->arch.apic->vapic_page = page;
5556         return 0;
5557 }
5558
5559 static void vapic_exit(struct kvm_vcpu *vcpu)
5560 {
5561         struct kvm_lapic *apic = vcpu->arch.apic;
5562         int idx;
5563
5564         if (!apic || !apic->vapic_addr)
5565                 return;
5566
5567         idx = srcu_read_lock(&vcpu->kvm->srcu);
5568         kvm_release_page_dirty(apic->vapic_page);
5569         mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5570         srcu_read_unlock(&vcpu->kvm->srcu, idx);
5571 }
5572
5573 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5574 {
5575         int max_irr, tpr;
5576
5577         if (!kvm_x86_ops->update_cr8_intercept)
5578                 return;
5579
5580         if (!vcpu->arch.apic)
5581                 return;
5582
5583         if (!vcpu->arch.apic->vapic_addr)
5584                 max_irr = kvm_lapic_find_highest_irr(vcpu);
5585         else
5586                 max_irr = -1;
5587
5588         if (max_irr != -1)
5589                 max_irr >>= 4;
5590
5591         tpr = kvm_lapic_get_cr8(vcpu);
5592
5593         kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5594 }
5595
5596 static void inject_pending_event(struct kvm_vcpu *vcpu)
5597 {
5598         /* try to reinject previous events if any */
5599         if (vcpu->arch.exception.pending) {
5600                 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5601                                         vcpu->arch.exception.has_error_code,
5602                                         vcpu->arch.exception.error_code);
5603                 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5604                                           vcpu->arch.exception.has_error_code,
5605                                           vcpu->arch.exception.error_code,
5606                                           vcpu->arch.exception.reinject);
5607                 return;
5608         }
5609
5610         if (vcpu->arch.nmi_injected) {
5611                 kvm_x86_ops->set_nmi(vcpu);
5612                 return;
5613         }
5614
5615         if (vcpu->arch.interrupt.pending) {
5616                 kvm_x86_ops->set_irq(vcpu);
5617                 return;
5618         }
5619
5620         /* try to inject new event if pending */
5621         if (vcpu->arch.nmi_pending) {
5622                 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5623                         --vcpu->arch.nmi_pending;
5624                         vcpu->arch.nmi_injected = true;
5625                         kvm_x86_ops->set_nmi(vcpu);
5626                 }
5627         } else if (kvm_cpu_has_injectable_intr(vcpu)) {
5628                 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5629                         kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5630                                             false);
5631                         kvm_x86_ops->set_irq(vcpu);
5632                 }
5633         }
5634 }
5635
5636 static void process_nmi(struct kvm_vcpu *vcpu)
5637 {
5638         unsigned limit = 2;
5639
5640         /*
5641          * x86 is limited to one NMI running, and one NMI pending after it.
5642          * If an NMI is already in progress, limit further NMIs to just one.
5643          * Otherwise, allow two (and we'll inject the first one immediately).
5644          */
5645         if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5646                 limit = 1;
5647
5648         vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5649         vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5650         kvm_make_request(KVM_REQ_EVENT, vcpu);
5651 }
5652
5653 static void kvm_gen_update_masterclock(struct kvm *kvm)
5654 {
5655 #ifdef CONFIG_X86_64
5656         int i;
5657         struct kvm_vcpu *vcpu;
5658         struct kvm_arch *ka = &kvm->arch;
5659
5660         spin_lock(&ka->pvclock_gtod_sync_lock);
5661         kvm_make_mclock_inprogress_request(kvm);
5662         /* no guest entries from this point */
5663         pvclock_update_vm_gtod_copy(kvm);
5664
5665         kvm_for_each_vcpu(i, vcpu, kvm)
5666                 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
5667
5668         /* guest entries allowed */
5669         kvm_for_each_vcpu(i, vcpu, kvm)
5670                 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
5671
5672         spin_unlock(&ka->pvclock_gtod_sync_lock);
5673 #endif
5674 }
5675
5676 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
5677 {
5678         u64 eoi_exit_bitmap[4];
5679         u32 tmr[8];
5680
5681         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5682                 return;
5683
5684         memset(eoi_exit_bitmap, 0, 32);
5685         memset(tmr, 0, 32);
5686
5687         kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
5688         kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
5689         kvm_apic_update_tmr(vcpu, tmr);
5690 }
5691
5692 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
5693 {
5694         int r;
5695         bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
5696                 vcpu->run->request_interrupt_window;
5697         bool req_immediate_exit = false;
5698
5699         if (vcpu->requests) {
5700                 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
5701                         kvm_mmu_unload(vcpu);
5702                 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
5703                         __kvm_migrate_timers(vcpu);
5704                 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5705                         kvm_gen_update_masterclock(vcpu->kvm);
5706                 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5707                         r = kvm_guest_time_update(vcpu);
5708                         if (unlikely(r))
5709                                 goto out;
5710                 }
5711                 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
5712                         kvm_mmu_sync_roots(vcpu);
5713                 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
5714                         kvm_x86_ops->tlb_flush(vcpu);
5715                 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
5716                         vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
5717                         r = 0;
5718                         goto out;
5719                 }
5720                 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
5721                         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5722                         r = 0;
5723                         goto out;
5724                 }
5725                 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
5726                         vcpu->fpu_active = 0;
5727                         kvm_x86_ops->fpu_deactivate(vcpu);
5728                 }
5729                 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5730                         /* Page is swapped out. Do synthetic halt */
5731                         vcpu->arch.apf.halted = true;
5732                         r = 1;
5733                         goto out;
5734                 }
5735                 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5736                         record_steal_time(vcpu);
5737                 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5738                         process_nmi(vcpu);
5739                 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5740                         kvm_handle_pmu_event(vcpu);
5741                 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5742                         kvm_deliver_pmi(vcpu);
5743                 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
5744                         vcpu_scan_ioapic(vcpu);
5745         }
5746
5747         if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5748                 kvm_apic_accept_events(vcpu);
5749                 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
5750                         r = 1;
5751                         goto out;
5752                 }
5753
5754                 inject_pending_event(vcpu);
5755
5756                 /* enable NMI/IRQ window open exits if needed */
5757                 if (vcpu->arch.nmi_pending)
5758                         req_immediate_exit =
5759                                 kvm_x86_ops->enable_nmi_window(vcpu) != 0;
5760                 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
5761                         req_immediate_exit =
5762                                 kvm_x86_ops->enable_irq_window(vcpu) != 0;
5763
5764                 if (kvm_lapic_enabled(vcpu)) {
5765                         /*
5766                          * Update architecture specific hints for APIC
5767                          * virtual interrupt delivery.
5768                          */
5769                         if (kvm_x86_ops->hwapic_irr_update)
5770                                 kvm_x86_ops->hwapic_irr_update(vcpu,
5771                                         kvm_lapic_find_highest_irr(vcpu));
5772                         update_cr8_intercept(vcpu);
5773                         kvm_lapic_sync_to_vapic(vcpu);
5774                 }
5775         }
5776
5777         r = kvm_mmu_reload(vcpu);
5778         if (unlikely(r)) {
5779                 goto cancel_injection;
5780         }
5781
5782         preempt_disable();
5783
5784         kvm_x86_ops->prepare_guest_switch(vcpu);
5785         if (vcpu->fpu_active)
5786                 kvm_load_guest_fpu(vcpu);
5787         kvm_load_guest_xcr0(vcpu);
5788
5789         vcpu->mode = IN_GUEST_MODE;
5790
5791         /* We should set ->mode before check ->requests,
5792          * see the comment in make_all_cpus_request.
5793          */
5794         smp_mb();
5795
5796         local_irq_disable();
5797
5798         if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
5799             || need_resched() || signal_pending(current)) {
5800                 vcpu->mode = OUTSIDE_GUEST_MODE;
5801                 smp_wmb();
5802                 local_irq_enable();
5803                 preempt_enable();
5804                 r = 1;
5805                 goto cancel_injection;
5806         }
5807
5808         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5809
5810         if (req_immediate_exit)
5811                 smp_send_reschedule(vcpu->cpu);
5812
5813         kvm_guest_enter();
5814
5815         if (unlikely(vcpu->arch.switch_db_regs)) {
5816                 set_debugreg(0, 7);
5817                 set_debugreg(vcpu->arch.eff_db[0], 0);
5818                 set_debugreg(vcpu->arch.eff_db[1], 1);
5819                 set_debugreg(vcpu->arch.eff_db[2], 2);
5820                 set_debugreg(vcpu->arch.eff_db[3], 3);
5821         }
5822
5823         trace_kvm_entry(vcpu->vcpu_id);
5824         kvm_x86_ops->run(vcpu);
5825
5826         /*
5827          * If the guest has used debug registers, at least dr7
5828          * will be disabled while returning to the host.
5829          * If we don't have active breakpoints in the host, we don't
5830          * care about the messed up debug address registers. But if
5831          * we have some of them active, restore the old state.
5832          */
5833         if (hw_breakpoint_active())
5834                 hw_breakpoint_restore();
5835
5836         vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
5837                                                            native_read_tsc());
5838
5839         vcpu->mode = OUTSIDE_GUEST_MODE;
5840         smp_wmb();
5841
5842         /* Interrupt is enabled by handle_external_intr() */
5843         kvm_x86_ops->handle_external_intr(vcpu);
5844
5845         ++vcpu->stat.exits;
5846
5847         /*
5848          * We must have an instruction between local_irq_enable() and
5849          * kvm_guest_exit(), so the timer interrupt isn't delayed by
5850          * the interrupt shadow.  The stat.exits increment will do nicely.
5851          * But we need to prevent reordering, hence this barrier():
5852          */
5853         barrier();
5854
5855         kvm_guest_exit();
5856
5857         preempt_enable();
5858
5859         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5860
5861         /*
5862          * Profile KVM exit RIPs:
5863          */
5864         if (unlikely(prof_on == KVM_PROFILING)) {
5865                 unsigned long rip = kvm_rip_read(vcpu);
5866                 profile_hit(KVM_PROFILING, (void *)rip);
5867         }
5868
5869         if (unlikely(vcpu->arch.tsc_always_catchup))
5870                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5871
5872         if (vcpu->arch.apic_attention)
5873                 kvm_lapic_sync_from_vapic(vcpu);
5874
5875         r = kvm_x86_ops->handle_exit(vcpu);
5876         return r;
5877
5878 cancel_injection:
5879         kvm_x86_ops->cancel_injection(vcpu);
5880         if (unlikely(vcpu->arch.apic_attention))
5881                 kvm_lapic_sync_from_vapic(vcpu);
5882 out:
5883         return r;
5884 }
5885
5886
5887 static int __vcpu_run(struct kvm_vcpu *vcpu)
5888 {
5889         int r;
5890         struct kvm *kvm = vcpu->kvm;
5891
5892         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5893         r = vapic_enter(vcpu);
5894         if (r) {
5895                 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5896                 return r;
5897         }
5898
5899         r = 1;
5900         while (r > 0) {
5901                 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5902                     !vcpu->arch.apf.halted)
5903                         r = vcpu_enter_guest(vcpu);
5904                 else {
5905                         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5906                         kvm_vcpu_block(vcpu);
5907                         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5908                         if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
5909                                 kvm_apic_accept_events(vcpu);
5910                                 switch(vcpu->arch.mp_state) {
5911                                 case KVM_MP_STATE_HALTED:
5912                                         vcpu->arch.mp_state =
5913                                                 KVM_MP_STATE_RUNNABLE;
5914                                 case KVM_MP_STATE_RUNNABLE:
5915                                         vcpu->arch.apf.halted = false;
5916                                         break;
5917                                 case KVM_MP_STATE_INIT_RECEIVED:
5918                                         break;
5919                                 default:
5920                                         r = -EINTR;
5921                                         break;
5922                                 }
5923                         }
5924                 }
5925
5926                 if (r <= 0)
5927                         break;
5928
5929                 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5930                 if (kvm_cpu_has_pending_timer(vcpu))
5931                         kvm_inject_pending_timer_irqs(vcpu);
5932
5933                 if (dm_request_for_irq_injection(vcpu)) {
5934                         r = -EINTR;
5935                         vcpu->run->exit_reason = KVM_EXIT_INTR;
5936                         ++vcpu->stat.request_irq_exits;
5937                 }
5938
5939                 kvm_check_async_pf_completion(vcpu);
5940
5941                 if (signal_pending(current)) {
5942                         r = -EINTR;
5943                         vcpu->run->exit_reason = KVM_EXIT_INTR;
5944                         ++vcpu->stat.signal_exits;
5945                 }
5946                 if (need_resched()) {
5947                         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5948                         kvm_resched(vcpu);
5949                         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5950                 }
5951         }
5952
5953         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5954
5955         vapic_exit(vcpu);
5956
5957         return r;
5958 }
5959
5960 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
5961 {
5962         int r;
5963         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5964         r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5965         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5966         if (r != EMULATE_DONE)
5967                 return 0;
5968         return 1;
5969 }
5970
5971 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
5972 {
5973         BUG_ON(!vcpu->arch.pio.count);
5974
5975         return complete_emulated_io(vcpu);
5976 }
5977
5978 /*
5979  * Implements the following, as a state machine:
5980  *
5981  * read:
5982  *   for each fragment
5983  *     for each mmio piece in the fragment
5984  *       write gpa, len
5985  *       exit
5986  *       copy data
5987  *   execute insn
5988  *
5989  * write:
5990  *   for each fragment
5991  *     for each mmio piece in the fragment
5992  *       write gpa, len
5993  *       copy data
5994  *       exit
5995  */
5996 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5997 {
5998         struct kvm_run *run = vcpu->run;
5999         struct kvm_mmio_fragment *frag;
6000         unsigned len;
6001
6002         BUG_ON(!vcpu->mmio_needed);
6003
6004         /* Complete previous fragment */
6005         frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6006         len = min(8u, frag->len);
6007         if (!vcpu->mmio_is_write)
6008                 memcpy(frag->data, run->mmio.data, len);
6009
6010         if (frag->len <= 8) {
6011                 /* Switch to the next fragment. */
6012                 frag++;
6013                 vcpu->mmio_cur_fragment++;
6014         } else {
6015                 /* Go forward to the next mmio piece. */
6016                 frag->data += len;
6017                 frag->gpa += len;
6018                 frag->len -= len;
6019         }
6020
6021         if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
6022                 vcpu->mmio_needed = 0;
6023                 if (vcpu->mmio_is_write)
6024                         return 1;
6025                 vcpu->mmio_read_completed = 1;
6026                 return complete_emulated_io(vcpu);
6027         }
6028
6029         run->exit_reason = KVM_EXIT_MMIO;
6030         run->mmio.phys_addr = frag->gpa;
6031         if (vcpu->mmio_is_write)
6032                 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6033         run->mmio.len = min(8u, frag->len);
6034         run->mmio.is_write = vcpu->mmio_is_write;
6035         vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6036         return 0;
6037 }
6038
6039
6040 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6041 {
6042         int r;
6043         sigset_t sigsaved;
6044
6045         if (!tsk_used_math(current) && init_fpu(current))
6046                 return -ENOMEM;
6047
6048         if (vcpu->sigset_active)
6049                 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6050
6051         if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6052                 kvm_vcpu_block(vcpu);
6053                 kvm_apic_accept_events(vcpu);
6054                 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6055                 r = -EAGAIN;
6056                 goto out;
6057         }
6058
6059         /* re-sync apic's tpr */
6060         if (!irqchip_in_kernel(vcpu->kvm)) {
6061                 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6062                         r = -EINVAL;
6063                         goto out;
6064                 }
6065         }
6066
6067         if (unlikely(vcpu->arch.complete_userspace_io)) {
6068                 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6069                 vcpu->arch.complete_userspace_io = NULL;
6070                 r = cui(vcpu);
6071                 if (r <= 0)
6072                         goto out;
6073         } else
6074                 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6075
6076         r = __vcpu_run(vcpu);
6077
6078 out:
6079         post_kvm_run_save(vcpu);
6080         if (vcpu->sigset_active)
6081                 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6082
6083         return r;
6084 }
6085
6086 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6087 {
6088         if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6089                 /*
6090                  * We are here if userspace calls get_regs() in the middle of
6091                  * instruction emulation. Registers state needs to be copied
6092                  * back from emulation context to vcpu. Userspace shouldn't do
6093                  * that usually, but some bad designed PV devices (vmware
6094                  * backdoor interface) need this to work
6095                  */
6096                 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6097                 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6098         }
6099         regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6100         regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6101         regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6102         regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6103         regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6104         regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6105         regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6106         regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6107 #ifdef CONFIG_X86_64
6108         regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6109         regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6110         regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6111         regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6112         regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6113         regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6114         regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6115         regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6116 #endif
6117
6118         regs->rip = kvm_rip_read(vcpu);
6119         regs->rflags = kvm_get_rflags(vcpu);
6120
6121         return 0;
6122 }
6123
6124 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6125 {
6126         vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6127         vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6128
6129         kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6130         kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6131         kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6132         kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6133         kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6134         kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6135         kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6136         kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6137 #ifdef CONFIG_X86_64
6138         kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6139         kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6140         kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6141         kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6142         kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6143         kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6144         kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6145         kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6146 #endif
6147
6148         kvm_rip_write(vcpu, regs->rip);
6149         kvm_set_rflags(vcpu, regs->rflags);
6150
6151         vcpu->arch.exception.pending = false;
6152
6153         kvm_make_request(KVM_REQ_EVENT, vcpu);
6154
6155         return 0;
6156 }
6157
6158 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6159 {
6160         struct kvm_segment cs;
6161
6162         kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6163         *db = cs.db;
6164         *l = cs.l;
6165 }
6166 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6167
6168 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6169                                   struct kvm_sregs *sregs)
6170 {
6171         struct desc_ptr dt;
6172
6173         kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6174         kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6175         kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6176         kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6177         kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6178         kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6179
6180         kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6181         kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6182
6183         kvm_x86_ops->get_idt(vcpu, &dt);
6184         sregs->idt.limit = dt.size;
6185         sregs->idt.base = dt.address;
6186         kvm_x86_ops->get_gdt(vcpu, &dt);
6187         sregs->gdt.limit = dt.size;
6188         sregs->gdt.base = dt.address;
6189
6190         sregs->cr0 = kvm_read_cr0(vcpu);
6191         sregs->cr2 = vcpu->arch.cr2;
6192         sregs->cr3 = kvm_read_cr3(vcpu);
6193         sregs->cr4 = kvm_read_cr4(vcpu);
6194         sregs->cr8 = kvm_get_cr8(vcpu);
6195         sregs->efer = vcpu->arch.efer;
6196         sregs->apic_base = kvm_get_apic_base(vcpu);
6197
6198         memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
6199
6200         if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
6201                 set_bit(vcpu->arch.interrupt.nr,
6202                         (unsigned long *)sregs->interrupt_bitmap);
6203
6204         return 0;
6205 }
6206
6207 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6208                                     struct kvm_mp_state *mp_state)
6209 {
6210         kvm_apic_accept_events(vcpu);
6211         mp_state->mp_state = vcpu->arch.mp_state;
6212         return 0;
6213 }
6214
6215 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6216                                     struct kvm_mp_state *mp_state)
6217 {
6218         if (!kvm_vcpu_has_lapic(vcpu) &&
6219             mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6220                 return -EINVAL;
6221
6222         if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6223                 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6224                 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6225         } else
6226                 vcpu->arch.mp_state = mp_state->mp_state;
6227         kvm_make_request(KVM_REQ_EVENT, vcpu);
6228         return 0;
6229 }
6230
6231 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6232                     int reason, bool has_error_code, u32 error_code)
6233 {
6234         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6235         int ret;
6236
6237         init_emulate_ctxt(vcpu);
6238
6239         ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
6240                                    has_error_code, error_code);
6241
6242         if (ret)
6243                 return EMULATE_FAIL;
6244
6245         kvm_rip_write(vcpu, ctxt->eip);
6246         kvm_set_rflags(vcpu, ctxt->eflags);
6247         kvm_make_request(KVM_REQ_EVENT, vcpu);
6248         return EMULATE_DONE;
6249 }
6250 EXPORT_SYMBOL_GPL(kvm_task_switch);
6251
6252 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6253                                   struct kvm_sregs&