KVM: VMX: Continue emulating after batch exhausted
[linux-3.10.git] / arch / x86 / kvm / vmx.c
1 /*
2  * Kernel-based Virtual Machine driver for Linux
3  *
4  * This module enables machines with Intel VT-x extensions to run virtual
5  * machines without emulation or binary translation.
6  *
7  * Copyright (C) 2006 Qumranet, Inc.
8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
9  *
10  * Authors:
11  *   Avi Kivity   <avi@qumranet.com>
12  *   Yaniv Kamay  <yaniv@qumranet.com>
13  *
14  * This work is licensed under the terms of the GNU GPL, version 2.  See
15  * the COPYING file in the top-level directory.
16  *
17  */
18
19 #include "irq.h"
20 #include "mmu.h"
21 #include "cpuid.h"
22
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/mm.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include "kvm_cache_regs.h"
35 #include "x86.h"
36
37 #include <asm/io.h>
38 #include <asm/desc.h>
39 #include <asm/vmx.h>
40 #include <asm/virtext.h>
41 #include <asm/mce.h>
42 #include <asm/i387.h>
43 #include <asm/xcr.h>
44 #include <asm/perf_event.h>
45
46 #include "trace.h"
47
48 #define __ex(x) __kvm_handle_fault_on_reboot(x)
49 #define __ex_clear(x, reg) \
50         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
51
52 MODULE_AUTHOR("Qumranet");
53 MODULE_LICENSE("GPL");
54
55 static const struct x86_cpu_id vmx_cpu_id[] = {
56         X86_FEATURE_MATCH(X86_FEATURE_VMX),
57         {}
58 };
59 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
60
61 static bool __read_mostly enable_vpid = 1;
62 module_param_named(vpid, enable_vpid, bool, 0444);
63
64 static bool __read_mostly flexpriority_enabled = 1;
65 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
66
67 static bool __read_mostly enable_ept = 1;
68 module_param_named(ept, enable_ept, bool, S_IRUGO);
69
70 static bool __read_mostly enable_unrestricted_guest = 1;
71 module_param_named(unrestricted_guest,
72                         enable_unrestricted_guest, bool, S_IRUGO);
73
74 static bool __read_mostly enable_ept_ad_bits = 1;
75 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
76
77 static bool __read_mostly emulate_invalid_guest_state = 0;
78 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
79
80 static bool __read_mostly vmm_exclusive = 1;
81 module_param(vmm_exclusive, bool, S_IRUGO);
82
83 static bool __read_mostly fasteoi = 1;
84 module_param(fasteoi, bool, S_IRUGO);
85
86 /*
87  * If nested=1, nested virtualization is supported, i.e., guests may use
88  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
89  * use VMX instructions.
90  */
91 static bool __read_mostly nested = 0;
92 module_param(nested, bool, S_IRUGO);
93
94 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
95         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
96 #define KVM_GUEST_CR0_MASK                                              \
97         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
98 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
99         (X86_CR0_WP | X86_CR0_NE)
100 #define KVM_VM_CR0_ALWAYS_ON                                            \
101         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
102 #define KVM_CR4_GUEST_OWNED_BITS                                      \
103         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
104          | X86_CR4_OSXMMEXCPT)
105
106 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
107 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
108
109 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
110
111 /*
112  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
113  * ple_gap:    upper bound on the amount of time between two successive
114  *             executions of PAUSE in a loop. Also indicate if ple enabled.
115  *             According to test, this time is usually smaller than 128 cycles.
116  * ple_window: upper bound on the amount of time a guest is allowed to execute
117  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
118  *             less than 2^12 cycles
119  * Time is measured based on a counter that runs at the same rate as the TSC,
120  * refer SDM volume 3b section 21.6.13 & 22.1.3.
121  */
122 #define KVM_VMX_DEFAULT_PLE_GAP    128
123 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
124 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
125 module_param(ple_gap, int, S_IRUGO);
126
127 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
128 module_param(ple_window, int, S_IRUGO);
129
130 #define NR_AUTOLOAD_MSRS 8
131 #define VMCS02_POOL_SIZE 1
132
133 struct vmcs {
134         u32 revision_id;
135         u32 abort;
136         char data[0];
137 };
138
139 /*
140  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
141  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
142  * loaded on this CPU (so we can clear them if the CPU goes down).
143  */
144 struct loaded_vmcs {
145         struct vmcs *vmcs;
146         int cpu;
147         int launched;
148         struct list_head loaded_vmcss_on_cpu_link;
149 };
150
151 struct shared_msr_entry {
152         unsigned index;
153         u64 data;
154         u64 mask;
155 };
156
157 /*
158  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
159  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
160  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
161  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
162  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
163  * More than one of these structures may exist, if L1 runs multiple L2 guests.
164  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
165  * underlying hardware which will be used to run L2.
166  * This structure is packed to ensure that its layout is identical across
167  * machines (necessary for live migration).
168  * If there are changes in this struct, VMCS12_REVISION must be changed.
169  */
170 typedef u64 natural_width;
171 struct __packed vmcs12 {
172         /* According to the Intel spec, a VMCS region must start with the
173          * following two fields. Then follow implementation-specific data.
174          */
175         u32 revision_id;
176         u32 abort;
177
178         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
179         u32 padding[7]; /* room for future expansion */
180
181         u64 io_bitmap_a;
182         u64 io_bitmap_b;
183         u64 msr_bitmap;
184         u64 vm_exit_msr_store_addr;
185         u64 vm_exit_msr_load_addr;
186         u64 vm_entry_msr_load_addr;
187         u64 tsc_offset;
188         u64 virtual_apic_page_addr;
189         u64 apic_access_addr;
190         u64 ept_pointer;
191         u64 guest_physical_address;
192         u64 vmcs_link_pointer;
193         u64 guest_ia32_debugctl;
194         u64 guest_ia32_pat;
195         u64 guest_ia32_efer;
196         u64 guest_ia32_perf_global_ctrl;
197         u64 guest_pdptr0;
198         u64 guest_pdptr1;
199         u64 guest_pdptr2;
200         u64 guest_pdptr3;
201         u64 host_ia32_pat;
202         u64 host_ia32_efer;
203         u64 host_ia32_perf_global_ctrl;
204         u64 padding64[8]; /* room for future expansion */
205         /*
206          * To allow migration of L1 (complete with its L2 guests) between
207          * machines of different natural widths (32 or 64 bit), we cannot have
208          * unsigned long fields with no explict size. We use u64 (aliased
209          * natural_width) instead. Luckily, x86 is little-endian.
210          */
211         natural_width cr0_guest_host_mask;
212         natural_width cr4_guest_host_mask;
213         natural_width cr0_read_shadow;
214         natural_width cr4_read_shadow;
215         natural_width cr3_target_value0;
216         natural_width cr3_target_value1;
217         natural_width cr3_target_value2;
218         natural_width cr3_target_value3;
219         natural_width exit_qualification;
220         natural_width guest_linear_address;
221         natural_width guest_cr0;
222         natural_width guest_cr3;
223         natural_width guest_cr4;
224         natural_width guest_es_base;
225         natural_width guest_cs_base;
226         natural_width guest_ss_base;
227         natural_width guest_ds_base;
228         natural_width guest_fs_base;
229         natural_width guest_gs_base;
230         natural_width guest_ldtr_base;
231         natural_width guest_tr_base;
232         natural_width guest_gdtr_base;
233         natural_width guest_idtr_base;
234         natural_width guest_dr7;
235         natural_width guest_rsp;
236         natural_width guest_rip;
237         natural_width guest_rflags;
238         natural_width guest_pending_dbg_exceptions;
239         natural_width guest_sysenter_esp;
240         natural_width guest_sysenter_eip;
241         natural_width host_cr0;
242         natural_width host_cr3;
243         natural_width host_cr4;
244         natural_width host_fs_base;
245         natural_width host_gs_base;
246         natural_width host_tr_base;
247         natural_width host_gdtr_base;
248         natural_width host_idtr_base;
249         natural_width host_ia32_sysenter_esp;
250         natural_width host_ia32_sysenter_eip;
251         natural_width host_rsp;
252         natural_width host_rip;
253         natural_width paddingl[8]; /* room for future expansion */
254         u32 pin_based_vm_exec_control;
255         u32 cpu_based_vm_exec_control;
256         u32 exception_bitmap;
257         u32 page_fault_error_code_mask;
258         u32 page_fault_error_code_match;
259         u32 cr3_target_count;
260         u32 vm_exit_controls;
261         u32 vm_exit_msr_store_count;
262         u32 vm_exit_msr_load_count;
263         u32 vm_entry_controls;
264         u32 vm_entry_msr_load_count;
265         u32 vm_entry_intr_info_field;
266         u32 vm_entry_exception_error_code;
267         u32 vm_entry_instruction_len;
268         u32 tpr_threshold;
269         u32 secondary_vm_exec_control;
270         u32 vm_instruction_error;
271         u32 vm_exit_reason;
272         u32 vm_exit_intr_info;
273         u32 vm_exit_intr_error_code;
274         u32 idt_vectoring_info_field;
275         u32 idt_vectoring_error_code;
276         u32 vm_exit_instruction_len;
277         u32 vmx_instruction_info;
278         u32 guest_es_limit;
279         u32 guest_cs_limit;
280         u32 guest_ss_limit;
281         u32 guest_ds_limit;
282         u32 guest_fs_limit;
283         u32 guest_gs_limit;
284         u32 guest_ldtr_limit;
285         u32 guest_tr_limit;
286         u32 guest_gdtr_limit;
287         u32 guest_idtr_limit;
288         u32 guest_es_ar_bytes;
289         u32 guest_cs_ar_bytes;
290         u32 guest_ss_ar_bytes;
291         u32 guest_ds_ar_bytes;
292         u32 guest_fs_ar_bytes;
293         u32 guest_gs_ar_bytes;
294         u32 guest_ldtr_ar_bytes;
295         u32 guest_tr_ar_bytes;
296         u32 guest_interruptibility_info;
297         u32 guest_activity_state;
298         u32 guest_sysenter_cs;
299         u32 host_ia32_sysenter_cs;
300         u32 padding32[8]; /* room for future expansion */
301         u16 virtual_processor_id;
302         u16 guest_es_selector;
303         u16 guest_cs_selector;
304         u16 guest_ss_selector;
305         u16 guest_ds_selector;
306         u16 guest_fs_selector;
307         u16 guest_gs_selector;
308         u16 guest_ldtr_selector;
309         u16 guest_tr_selector;
310         u16 host_es_selector;
311         u16 host_cs_selector;
312         u16 host_ss_selector;
313         u16 host_ds_selector;
314         u16 host_fs_selector;
315         u16 host_gs_selector;
316         u16 host_tr_selector;
317 };
318
319 /*
320  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
321  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
322  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
323  */
324 #define VMCS12_REVISION 0x11e57ed0
325
326 /*
327  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
328  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
329  * current implementation, 4K are reserved to avoid future complications.
330  */
331 #define VMCS12_SIZE 0x1000
332
333 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
334 struct vmcs02_list {
335         struct list_head list;
336         gpa_t vmptr;
337         struct loaded_vmcs vmcs02;
338 };
339
340 /*
341  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
342  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
343  */
344 struct nested_vmx {
345         /* Has the level1 guest done vmxon? */
346         bool vmxon;
347
348         /* The guest-physical address of the current VMCS L1 keeps for L2 */
349         gpa_t current_vmptr;
350         /* The host-usable pointer to the above */
351         struct page *current_vmcs12_page;
352         struct vmcs12 *current_vmcs12;
353
354         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
355         struct list_head vmcs02_pool;
356         int vmcs02_num;
357         u64 vmcs01_tsc_offset;
358         /* L2 must run next, and mustn't decide to exit to L1. */
359         bool nested_run_pending;
360         /*
361          * Guest pages referred to in vmcs02 with host-physical pointers, so
362          * we must keep them pinned while L2 runs.
363          */
364         struct page *apic_access_page;
365 };
366
367 struct vcpu_vmx {
368         struct kvm_vcpu       vcpu;
369         unsigned long         host_rsp;
370         u8                    fail;
371         u8                    cpl;
372         bool                  nmi_known_unmasked;
373         u32                   exit_intr_info;
374         u32                   idt_vectoring_info;
375         ulong                 rflags;
376         struct shared_msr_entry *guest_msrs;
377         int                   nmsrs;
378         int                   save_nmsrs;
379 #ifdef CONFIG_X86_64
380         u64                   msr_host_kernel_gs_base;
381         u64                   msr_guest_kernel_gs_base;
382 #endif
383         /*
384          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
385          * non-nested (L1) guest, it always points to vmcs01. For a nested
386          * guest (L2), it points to a different VMCS.
387          */
388         struct loaded_vmcs    vmcs01;
389         struct loaded_vmcs   *loaded_vmcs;
390         bool                  __launched; /* temporary, used in vmx_vcpu_run */
391         struct msr_autoload {
392                 unsigned nr;
393                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
394                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
395         } msr_autoload;
396         struct {
397                 int           loaded;
398                 u16           fs_sel, gs_sel, ldt_sel;
399 #ifdef CONFIG_X86_64
400                 u16           ds_sel, es_sel;
401 #endif
402                 int           gs_ldt_reload_needed;
403                 int           fs_reload_needed;
404         } host_state;
405         struct {
406                 int vm86_active;
407                 ulong save_rflags;
408                 struct kvm_save_segment {
409                         u16 selector;
410                         unsigned long base;
411                         u32 limit;
412                         u32 ar;
413                 } tr, es, ds, fs, gs;
414         } rmode;
415         struct {
416                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
417                 struct kvm_save_segment seg[8];
418         } segment_cache;
419         int vpid;
420         bool emulation_required;
421
422         /* Support for vnmi-less CPUs */
423         int soft_vnmi_blocked;
424         ktime_t entry_time;
425         s64 vnmi_blocked_time;
426         u32 exit_reason;
427
428         bool rdtscp_enabled;
429
430         /* Support for a guest hypervisor (nested VMX) */
431         struct nested_vmx nested;
432 };
433
434 enum segment_cache_field {
435         SEG_FIELD_SEL = 0,
436         SEG_FIELD_BASE = 1,
437         SEG_FIELD_LIMIT = 2,
438         SEG_FIELD_AR = 3,
439
440         SEG_FIELD_NR = 4
441 };
442
443 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
444 {
445         return container_of(vcpu, struct vcpu_vmx, vcpu);
446 }
447
448 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
449 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
450 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
451                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
452
453 static unsigned short vmcs_field_to_offset_table[] = {
454         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
455         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
456         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
457         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
458         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
459         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
460         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
461         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
462         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
463         FIELD(HOST_ES_SELECTOR, host_es_selector),
464         FIELD(HOST_CS_SELECTOR, host_cs_selector),
465         FIELD(HOST_SS_SELECTOR, host_ss_selector),
466         FIELD(HOST_DS_SELECTOR, host_ds_selector),
467         FIELD(HOST_FS_SELECTOR, host_fs_selector),
468         FIELD(HOST_GS_SELECTOR, host_gs_selector),
469         FIELD(HOST_TR_SELECTOR, host_tr_selector),
470         FIELD64(IO_BITMAP_A, io_bitmap_a),
471         FIELD64(IO_BITMAP_B, io_bitmap_b),
472         FIELD64(MSR_BITMAP, msr_bitmap),
473         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
474         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
475         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
476         FIELD64(TSC_OFFSET, tsc_offset),
477         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
478         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
479         FIELD64(EPT_POINTER, ept_pointer),
480         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
481         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
482         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
483         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
484         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
485         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
486         FIELD64(GUEST_PDPTR0, guest_pdptr0),
487         FIELD64(GUEST_PDPTR1, guest_pdptr1),
488         FIELD64(GUEST_PDPTR2, guest_pdptr2),
489         FIELD64(GUEST_PDPTR3, guest_pdptr3),
490         FIELD64(HOST_IA32_PAT, host_ia32_pat),
491         FIELD64(HOST_IA32_EFER, host_ia32_efer),
492         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
493         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
494         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
495         FIELD(EXCEPTION_BITMAP, exception_bitmap),
496         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
497         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
498         FIELD(CR3_TARGET_COUNT, cr3_target_count),
499         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
500         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
501         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
502         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
503         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
504         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
505         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
506         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
507         FIELD(TPR_THRESHOLD, tpr_threshold),
508         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
509         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
510         FIELD(VM_EXIT_REASON, vm_exit_reason),
511         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
512         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
513         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
514         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
515         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
516         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
517         FIELD(GUEST_ES_LIMIT, guest_es_limit),
518         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
519         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
520         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
521         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
522         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
523         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
524         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
525         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
526         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
527         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
528         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
529         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
530         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
531         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
532         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
533         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
534         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
535         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
536         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
537         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
538         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
539         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
540         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
541         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
542         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
543         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
544         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
545         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
546         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
547         FIELD(EXIT_QUALIFICATION, exit_qualification),
548         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
549         FIELD(GUEST_CR0, guest_cr0),
550         FIELD(GUEST_CR3, guest_cr3),
551         FIELD(GUEST_CR4, guest_cr4),
552         FIELD(GUEST_ES_BASE, guest_es_base),
553         FIELD(GUEST_CS_BASE, guest_cs_base),
554         FIELD(GUEST_SS_BASE, guest_ss_base),
555         FIELD(GUEST_DS_BASE, guest_ds_base),
556         FIELD(GUEST_FS_BASE, guest_fs_base),
557         FIELD(GUEST_GS_BASE, guest_gs_base),
558         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
559         FIELD(GUEST_TR_BASE, guest_tr_base),
560         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
561         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
562         FIELD(GUEST_DR7, guest_dr7),
563         FIELD(GUEST_RSP, guest_rsp),
564         FIELD(GUEST_RIP, guest_rip),
565         FIELD(GUEST_RFLAGS, guest_rflags),
566         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
567         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
568         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
569         FIELD(HOST_CR0, host_cr0),
570         FIELD(HOST_CR3, host_cr3),
571         FIELD(HOST_CR4, host_cr4),
572         FIELD(HOST_FS_BASE, host_fs_base),
573         FIELD(HOST_GS_BASE, host_gs_base),
574         FIELD(HOST_TR_BASE, host_tr_base),
575         FIELD(HOST_GDTR_BASE, host_gdtr_base),
576         FIELD(HOST_IDTR_BASE, host_idtr_base),
577         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
578         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
579         FIELD(HOST_RSP, host_rsp),
580         FIELD(HOST_RIP, host_rip),
581 };
582 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
583
584 static inline short vmcs_field_to_offset(unsigned long field)
585 {
586         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
587                 return -1;
588         return vmcs_field_to_offset_table[field];
589 }
590
591 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
592 {
593         return to_vmx(vcpu)->nested.current_vmcs12;
594 }
595
596 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
597 {
598         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
599         if (is_error_page(page)) {
600                 kvm_release_page_clean(page);
601                 return NULL;
602         }
603         return page;
604 }
605
606 static void nested_release_page(struct page *page)
607 {
608         kvm_release_page_dirty(page);
609 }
610
611 static void nested_release_page_clean(struct page *page)
612 {
613         kvm_release_page_clean(page);
614 }
615
616 static u64 construct_eptp(unsigned long root_hpa);
617 static void kvm_cpu_vmxon(u64 addr);
618 static void kvm_cpu_vmxoff(void);
619 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
620 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
621 static void vmx_set_segment(struct kvm_vcpu *vcpu,
622                             struct kvm_segment *var, int seg);
623 static void vmx_get_segment(struct kvm_vcpu *vcpu,
624                             struct kvm_segment *var, int seg);
625
626 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
627 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
628 /*
629  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
630  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
631  */
632 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
633 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
634
635 static unsigned long *vmx_io_bitmap_a;
636 static unsigned long *vmx_io_bitmap_b;
637 static unsigned long *vmx_msr_bitmap_legacy;
638 static unsigned long *vmx_msr_bitmap_longmode;
639
640 static bool cpu_has_load_ia32_efer;
641 static bool cpu_has_load_perf_global_ctrl;
642
643 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
644 static DEFINE_SPINLOCK(vmx_vpid_lock);
645
646 static struct vmcs_config {
647         int size;
648         int order;
649         u32 revision_id;
650         u32 pin_based_exec_ctrl;
651         u32 cpu_based_exec_ctrl;
652         u32 cpu_based_2nd_exec_ctrl;
653         u32 vmexit_ctrl;
654         u32 vmentry_ctrl;
655 } vmcs_config;
656
657 static struct vmx_capability {
658         u32 ept;
659         u32 vpid;
660 } vmx_capability;
661
662 #define VMX_SEGMENT_FIELD(seg)                                  \
663         [VCPU_SREG_##seg] = {                                   \
664                 .selector = GUEST_##seg##_SELECTOR,             \
665                 .base = GUEST_##seg##_BASE,                     \
666                 .limit = GUEST_##seg##_LIMIT,                   \
667                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
668         }
669
670 static struct kvm_vmx_segment_field {
671         unsigned selector;
672         unsigned base;
673         unsigned limit;
674         unsigned ar_bytes;
675 } kvm_vmx_segment_fields[] = {
676         VMX_SEGMENT_FIELD(CS),
677         VMX_SEGMENT_FIELD(DS),
678         VMX_SEGMENT_FIELD(ES),
679         VMX_SEGMENT_FIELD(FS),
680         VMX_SEGMENT_FIELD(GS),
681         VMX_SEGMENT_FIELD(SS),
682         VMX_SEGMENT_FIELD(TR),
683         VMX_SEGMENT_FIELD(LDTR),
684 };
685
686 static u64 host_efer;
687
688 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
689
690 /*
691  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
692  * away by decrementing the array size.
693  */
694 static const u32 vmx_msr_index[] = {
695 #ifdef CONFIG_X86_64
696         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
697 #endif
698         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
699 };
700 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
701
702 static inline bool is_page_fault(u32 intr_info)
703 {
704         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
705                              INTR_INFO_VALID_MASK)) ==
706                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
707 }
708
709 static inline bool is_no_device(u32 intr_info)
710 {
711         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
712                              INTR_INFO_VALID_MASK)) ==
713                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
714 }
715
716 static inline bool is_invalid_opcode(u32 intr_info)
717 {
718         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
719                              INTR_INFO_VALID_MASK)) ==
720                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
721 }
722
723 static inline bool is_external_interrupt(u32 intr_info)
724 {
725         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
726                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
727 }
728
729 static inline bool is_machine_check(u32 intr_info)
730 {
731         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
732                              INTR_INFO_VALID_MASK)) ==
733                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
734 }
735
736 static inline bool cpu_has_vmx_msr_bitmap(void)
737 {
738         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
739 }
740
741 static inline bool cpu_has_vmx_tpr_shadow(void)
742 {
743         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
744 }
745
746 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
747 {
748         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
749 }
750
751 static inline bool cpu_has_secondary_exec_ctrls(void)
752 {
753         return vmcs_config.cpu_based_exec_ctrl &
754                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
755 }
756
757 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
758 {
759         return vmcs_config.cpu_based_2nd_exec_ctrl &
760                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
761 }
762
763 static inline bool cpu_has_vmx_flexpriority(void)
764 {
765         return cpu_has_vmx_tpr_shadow() &&
766                 cpu_has_vmx_virtualize_apic_accesses();
767 }
768
769 static inline bool cpu_has_vmx_ept_execute_only(void)
770 {
771         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
772 }
773
774 static inline bool cpu_has_vmx_eptp_uncacheable(void)
775 {
776         return vmx_capability.ept & VMX_EPTP_UC_BIT;
777 }
778
779 static inline bool cpu_has_vmx_eptp_writeback(void)
780 {
781         return vmx_capability.ept & VMX_EPTP_WB_BIT;
782 }
783
784 static inline bool cpu_has_vmx_ept_2m_page(void)
785 {
786         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
787 }
788
789 static inline bool cpu_has_vmx_ept_1g_page(void)
790 {
791         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
792 }
793
794 static inline bool cpu_has_vmx_ept_4levels(void)
795 {
796         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
797 }
798
799 static inline bool cpu_has_vmx_ept_ad_bits(void)
800 {
801         return vmx_capability.ept & VMX_EPT_AD_BIT;
802 }
803
804 static inline bool cpu_has_vmx_invept_individual_addr(void)
805 {
806         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
807 }
808
809 static inline bool cpu_has_vmx_invept_context(void)
810 {
811         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
812 }
813
814 static inline bool cpu_has_vmx_invept_global(void)
815 {
816         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
817 }
818
819 static inline bool cpu_has_vmx_invvpid_single(void)
820 {
821         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
822 }
823
824 static inline bool cpu_has_vmx_invvpid_global(void)
825 {
826         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
827 }
828
829 static inline bool cpu_has_vmx_ept(void)
830 {
831         return vmcs_config.cpu_based_2nd_exec_ctrl &
832                 SECONDARY_EXEC_ENABLE_EPT;
833 }
834
835 static inline bool cpu_has_vmx_unrestricted_guest(void)
836 {
837         return vmcs_config.cpu_based_2nd_exec_ctrl &
838                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
839 }
840
841 static inline bool cpu_has_vmx_ple(void)
842 {
843         return vmcs_config.cpu_based_2nd_exec_ctrl &
844                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
845 }
846
847 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
848 {
849         return flexpriority_enabled && irqchip_in_kernel(kvm);
850 }
851
852 static inline bool cpu_has_vmx_vpid(void)
853 {
854         return vmcs_config.cpu_based_2nd_exec_ctrl &
855                 SECONDARY_EXEC_ENABLE_VPID;
856 }
857
858 static inline bool cpu_has_vmx_rdtscp(void)
859 {
860         return vmcs_config.cpu_based_2nd_exec_ctrl &
861                 SECONDARY_EXEC_RDTSCP;
862 }
863
864 static inline bool cpu_has_virtual_nmis(void)
865 {
866         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
867 }
868
869 static inline bool cpu_has_vmx_wbinvd_exit(void)
870 {
871         return vmcs_config.cpu_based_2nd_exec_ctrl &
872                 SECONDARY_EXEC_WBINVD_EXITING;
873 }
874
875 static inline bool report_flexpriority(void)
876 {
877         return flexpriority_enabled;
878 }
879
880 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
881 {
882         return vmcs12->cpu_based_vm_exec_control & bit;
883 }
884
885 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
886 {
887         return (vmcs12->cpu_based_vm_exec_control &
888                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
889                 (vmcs12->secondary_vm_exec_control & bit);
890 }
891
892 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
893         struct kvm_vcpu *vcpu)
894 {
895         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
896 }
897
898 static inline bool is_exception(u32 intr_info)
899 {
900         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
901                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
902 }
903
904 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
905 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
906                         struct vmcs12 *vmcs12,
907                         u32 reason, unsigned long qualification);
908
909 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
910 {
911         int i;
912
913         for (i = 0; i < vmx->nmsrs; ++i)
914                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
915                         return i;
916         return -1;
917 }
918
919 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
920 {
921     struct {
922         u64 vpid : 16;
923         u64 rsvd : 48;
924         u64 gva;
925     } operand = { vpid, 0, gva };
926
927     asm volatile (__ex(ASM_VMX_INVVPID)
928                   /* CF==1 or ZF==1 --> rc = -1 */
929                   "; ja 1f ; ud2 ; 1:"
930                   : : "a"(&operand), "c"(ext) : "cc", "memory");
931 }
932
933 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
934 {
935         struct {
936                 u64 eptp, gpa;
937         } operand = {eptp, gpa};
938
939         asm volatile (__ex(ASM_VMX_INVEPT)
940                         /* CF==1 or ZF==1 --> rc = -1 */
941                         "; ja 1f ; ud2 ; 1:\n"
942                         : : "a" (&operand), "c" (ext) : "cc", "memory");
943 }
944
945 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
946 {
947         int i;
948
949         i = __find_msr_index(vmx, msr);
950         if (i >= 0)
951                 return &vmx->guest_msrs[i];
952         return NULL;
953 }
954
955 static void vmcs_clear(struct vmcs *vmcs)
956 {
957         u64 phys_addr = __pa(vmcs);
958         u8 error;
959
960         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
961                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
962                       : "cc", "memory");
963         if (error)
964                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
965                        vmcs, phys_addr);
966 }
967
968 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
969 {
970         vmcs_clear(loaded_vmcs->vmcs);
971         loaded_vmcs->cpu = -1;
972         loaded_vmcs->launched = 0;
973 }
974
975 static void vmcs_load(struct vmcs *vmcs)
976 {
977         u64 phys_addr = __pa(vmcs);
978         u8 error;
979
980         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
981                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
982                         : "cc", "memory");
983         if (error)
984                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
985                        vmcs, phys_addr);
986 }
987
988 static void __loaded_vmcs_clear(void *arg)
989 {
990         struct loaded_vmcs *loaded_vmcs = arg;
991         int cpu = raw_smp_processor_id();
992
993         if (loaded_vmcs->cpu != cpu)
994                 return; /* vcpu migration can race with cpu offline */
995         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
996                 per_cpu(current_vmcs, cpu) = NULL;
997         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
998         loaded_vmcs_init(loaded_vmcs);
999 }
1000
1001 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1002 {
1003         if (loaded_vmcs->cpu != -1)
1004                 smp_call_function_single(
1005                         loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
1006 }
1007
1008 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1009 {
1010         if (vmx->vpid == 0)
1011                 return;
1012
1013         if (cpu_has_vmx_invvpid_single())
1014                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1015 }
1016
1017 static inline void vpid_sync_vcpu_global(void)
1018 {
1019         if (cpu_has_vmx_invvpid_global())
1020                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1021 }
1022
1023 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1024 {
1025         if (cpu_has_vmx_invvpid_single())
1026                 vpid_sync_vcpu_single(vmx);
1027         else
1028                 vpid_sync_vcpu_global();
1029 }
1030
1031 static inline void ept_sync_global(void)
1032 {
1033         if (cpu_has_vmx_invept_global())
1034                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1035 }
1036
1037 static inline void ept_sync_context(u64 eptp)
1038 {
1039         if (enable_ept) {
1040                 if (cpu_has_vmx_invept_context())
1041                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1042                 else
1043                         ept_sync_global();
1044         }
1045 }
1046
1047 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1048 {
1049         if (enable_ept) {
1050                 if (cpu_has_vmx_invept_individual_addr())
1051                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1052                                         eptp, gpa);
1053                 else
1054                         ept_sync_context(eptp);
1055         }
1056 }
1057
1058 static __always_inline unsigned long vmcs_readl(unsigned long field)
1059 {
1060         unsigned long value;
1061
1062         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1063                       : "=a"(value) : "d"(field) : "cc");
1064         return value;
1065 }
1066
1067 static __always_inline u16 vmcs_read16(unsigned long field)
1068 {
1069         return vmcs_readl(field);
1070 }
1071
1072 static __always_inline u32 vmcs_read32(unsigned long field)
1073 {
1074         return vmcs_readl(field);
1075 }
1076
1077 static __always_inline u64 vmcs_read64(unsigned long field)
1078 {
1079 #ifdef CONFIG_X86_64
1080         return vmcs_readl(field);
1081 #else
1082         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1083 #endif
1084 }
1085
1086 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1087 {
1088         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1089                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1090         dump_stack();
1091 }
1092
1093 static void vmcs_writel(unsigned long field, unsigned long value)
1094 {
1095         u8 error;
1096
1097         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1098                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1099         if (unlikely(error))
1100                 vmwrite_error(field, value);
1101 }
1102
1103 static void vmcs_write16(unsigned long field, u16 value)
1104 {
1105         vmcs_writel(field, value);
1106 }
1107
1108 static void vmcs_write32(unsigned long field, u32 value)
1109 {
1110         vmcs_writel(field, value);
1111 }
1112
1113 static void vmcs_write64(unsigned long field, u64 value)
1114 {
1115         vmcs_writel(field, value);
1116 #ifndef CONFIG_X86_64
1117         asm volatile ("");
1118         vmcs_writel(field+1, value >> 32);
1119 #endif
1120 }
1121
1122 static void vmcs_clear_bits(unsigned long field, u32 mask)
1123 {
1124         vmcs_writel(field, vmcs_readl(field) & ~mask);
1125 }
1126
1127 static void vmcs_set_bits(unsigned long field, u32 mask)
1128 {
1129         vmcs_writel(field, vmcs_readl(field) | mask);
1130 }
1131
1132 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1133 {
1134         vmx->segment_cache.bitmask = 0;
1135 }
1136
1137 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1138                                        unsigned field)
1139 {
1140         bool ret;
1141         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1142
1143         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1144                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1145                 vmx->segment_cache.bitmask = 0;
1146         }
1147         ret = vmx->segment_cache.bitmask & mask;
1148         vmx->segment_cache.bitmask |= mask;
1149         return ret;
1150 }
1151
1152 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1153 {
1154         u16 *p = &vmx->segment_cache.seg[seg].selector;
1155
1156         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1157                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1158         return *p;
1159 }
1160
1161 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1162 {
1163         ulong *p = &vmx->segment_cache.seg[seg].base;
1164
1165         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1166                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1167         return *p;
1168 }
1169
1170 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1171 {
1172         u32 *p = &vmx->segment_cache.seg[seg].limit;
1173
1174         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1175                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1176         return *p;
1177 }
1178
1179 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1180 {
1181         u32 *p = &vmx->segment_cache.seg[seg].ar;
1182
1183         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1184                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1185         return *p;
1186 }
1187
1188 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1189 {
1190         u32 eb;
1191
1192         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1193              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1194         if ((vcpu->guest_debug &
1195              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1196             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1197                 eb |= 1u << BP_VECTOR;
1198         if (to_vmx(vcpu)->rmode.vm86_active)
1199                 eb = ~0;
1200         if (enable_ept)
1201                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1202         if (vcpu->fpu_active)
1203                 eb &= ~(1u << NM_VECTOR);
1204
1205         /* When we are running a nested L2 guest and L1 specified for it a
1206          * certain exception bitmap, we must trap the same exceptions and pass
1207          * them to L1. When running L2, we will only handle the exceptions
1208          * specified above if L1 did not want them.
1209          */
1210         if (is_guest_mode(vcpu))
1211                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1212
1213         vmcs_write32(EXCEPTION_BITMAP, eb);
1214 }
1215
1216 static void clear_atomic_switch_msr_special(unsigned long entry,
1217                 unsigned long exit)
1218 {
1219         vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1220         vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1221 }
1222
1223 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1224 {
1225         unsigned i;
1226         struct msr_autoload *m = &vmx->msr_autoload;
1227
1228         switch (msr) {
1229         case MSR_EFER:
1230                 if (cpu_has_load_ia32_efer) {
1231                         clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1232                                         VM_EXIT_LOAD_IA32_EFER);
1233                         return;
1234                 }
1235                 break;
1236         case MSR_CORE_PERF_GLOBAL_CTRL:
1237                 if (cpu_has_load_perf_global_ctrl) {
1238                         clear_atomic_switch_msr_special(
1239                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1240                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1241                         return;
1242                 }
1243                 break;
1244         }
1245
1246         for (i = 0; i < m->nr; ++i)
1247                 if (m->guest[i].index == msr)
1248                         break;
1249
1250         if (i == m->nr)
1251                 return;
1252         --m->nr;
1253         m->guest[i] = m->guest[m->nr];
1254         m->host[i] = m->host[m->nr];
1255         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1256         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1257 }
1258
1259 static void add_atomic_switch_msr_special(unsigned long entry,
1260                 unsigned long exit, unsigned long guest_val_vmcs,
1261                 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1262 {
1263         vmcs_write64(guest_val_vmcs, guest_val);
1264         vmcs_write64(host_val_vmcs, host_val);
1265         vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1266         vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1267 }
1268
1269 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1270                                   u64 guest_val, u64 host_val)
1271 {
1272         unsigned i;
1273         struct msr_autoload *m = &vmx->msr_autoload;
1274
1275         switch (msr) {
1276         case MSR_EFER:
1277                 if (cpu_has_load_ia32_efer) {
1278                         add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1279                                         VM_EXIT_LOAD_IA32_EFER,
1280                                         GUEST_IA32_EFER,
1281                                         HOST_IA32_EFER,
1282                                         guest_val, host_val);
1283                         return;
1284                 }
1285                 break;
1286         case MSR_CORE_PERF_GLOBAL_CTRL:
1287                 if (cpu_has_load_perf_global_ctrl) {
1288                         add_atomic_switch_msr_special(
1289                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1290                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1291                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1292                                         HOST_IA32_PERF_GLOBAL_CTRL,
1293                                         guest_val, host_val);
1294                         return;
1295                 }
1296                 break;
1297         }
1298
1299         for (i = 0; i < m->nr; ++i)
1300                 if (m->guest[i].index == msr)
1301                         break;
1302
1303         if (i == NR_AUTOLOAD_MSRS) {
1304                 printk_once(KERN_WARNING"Not enough mst switch entries. "
1305                                 "Can't add msr %x\n", msr);
1306                 return;
1307         } else if (i == m->nr) {
1308                 ++m->nr;
1309                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1310                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1311         }
1312
1313         m->guest[i].index = msr;
1314         m->guest[i].value = guest_val;
1315         m->host[i].index = msr;
1316         m->host[i].value = host_val;
1317 }
1318
1319 static void reload_tss(void)
1320 {
1321         /*
1322          * VT restores TR but not its size.  Useless.
1323          */
1324         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1325         struct desc_struct *descs;
1326
1327         descs = (void *)gdt->address;
1328         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1329         load_TR_desc();
1330 }
1331
1332 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1333 {
1334         u64 guest_efer;
1335         u64 ignore_bits;
1336
1337         guest_efer = vmx->vcpu.arch.efer;
1338
1339         /*
1340          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1341          * outside long mode
1342          */
1343         ignore_bits = EFER_NX | EFER_SCE;
1344 #ifdef CONFIG_X86_64
1345         ignore_bits |= EFER_LMA | EFER_LME;
1346         /* SCE is meaningful only in long mode on Intel */
1347         if (guest_efer & EFER_LMA)
1348                 ignore_bits &= ~(u64)EFER_SCE;
1349 #endif
1350         guest_efer &= ~ignore_bits;
1351         guest_efer |= host_efer & ignore_bits;
1352         vmx->guest_msrs[efer_offset].data = guest_efer;
1353         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1354
1355         clear_atomic_switch_msr(vmx, MSR_EFER);
1356         /* On ept, can't emulate nx, and must switch nx atomically */
1357         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1358                 guest_efer = vmx->vcpu.arch.efer;
1359                 if (!(guest_efer & EFER_LMA))
1360                         guest_efer &= ~EFER_LME;
1361                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1362                 return false;
1363         }
1364
1365         return true;
1366 }
1367
1368 static unsigned long segment_base(u16 selector)
1369 {
1370         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1371         struct desc_struct *d;
1372         unsigned long table_base;
1373         unsigned long v;
1374
1375         if (!(selector & ~3))
1376                 return 0;
1377
1378         table_base = gdt->address;
1379
1380         if (selector & 4) {           /* from ldt */
1381                 u16 ldt_selector = kvm_read_ldt();
1382
1383                 if (!(ldt_selector & ~3))
1384                         return 0;
1385
1386                 table_base = segment_base(ldt_selector);
1387         }
1388         d = (struct desc_struct *)(table_base + (selector & ~7));
1389         v = get_desc_base(d);
1390 #ifdef CONFIG_X86_64
1391        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1392                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1393 #endif
1394         return v;
1395 }
1396
1397 static inline unsigned long kvm_read_tr_base(void)
1398 {
1399         u16 tr;
1400         asm("str %0" : "=g"(tr));
1401         return segment_base(tr);
1402 }
1403
1404 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1405 {
1406         struct vcpu_vmx *vmx = to_vmx(vcpu);
1407         int i;
1408
1409         if (vmx->host_state.loaded)
1410                 return;
1411
1412         vmx->host_state.loaded = 1;
1413         /*
1414          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1415          * allow segment selectors with cpl > 0 or ti == 1.
1416          */
1417         vmx->host_state.ldt_sel = kvm_read_ldt();
1418         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1419         savesegment(fs, vmx->host_state.fs_sel);
1420         if (!(vmx->host_state.fs_sel & 7)) {
1421                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1422                 vmx->host_state.fs_reload_needed = 0;
1423         } else {
1424                 vmcs_write16(HOST_FS_SELECTOR, 0);
1425                 vmx->host_state.fs_reload_needed = 1;
1426         }
1427         savesegment(gs, vmx->host_state.gs_sel);
1428         if (!(vmx->host_state.gs_sel & 7))
1429                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1430         else {
1431                 vmcs_write16(HOST_GS_SELECTOR, 0);
1432                 vmx->host_state.gs_ldt_reload_needed = 1;
1433         }
1434
1435 #ifdef CONFIG_X86_64
1436         savesegment(ds, vmx->host_state.ds_sel);
1437         savesegment(es, vmx->host_state.es_sel);
1438 #endif
1439
1440 #ifdef CONFIG_X86_64
1441         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1442         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1443 #else
1444         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1445         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1446 #endif
1447
1448 #ifdef CONFIG_X86_64
1449         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1450         if (is_long_mode(&vmx->vcpu))
1451                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1452 #endif
1453         for (i = 0; i < vmx->save_nmsrs; ++i)
1454                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1455                                    vmx->guest_msrs[i].data,
1456                                    vmx->guest_msrs[i].mask);
1457 }
1458
1459 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1460 {
1461         if (!vmx->host_state.loaded)
1462                 return;
1463
1464         ++vmx->vcpu.stat.host_state_reload;
1465         vmx->host_state.loaded = 0;
1466 #ifdef CONFIG_X86_64
1467         if (is_long_mode(&vmx->vcpu))
1468                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1469 #endif
1470         if (vmx->host_state.gs_ldt_reload_needed) {
1471                 kvm_load_ldt(vmx->host_state.ldt_sel);
1472 #ifdef CONFIG_X86_64
1473                 load_gs_index(vmx->host_state.gs_sel);
1474 #else
1475                 loadsegment(gs, vmx->host_state.gs_sel);
1476 #endif
1477         }
1478         if (vmx->host_state.fs_reload_needed)
1479                 loadsegment(fs, vmx->host_state.fs_sel);
1480 #ifdef CONFIG_X86_64
1481         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1482                 loadsegment(ds, vmx->host_state.ds_sel);
1483                 loadsegment(es, vmx->host_state.es_sel);
1484         }
1485 #else
1486         /*
1487          * The sysexit path does not restore ds/es, so we must set them to
1488          * a reasonable value ourselves.
1489          */
1490         loadsegment(ds, __USER_DS);
1491         loadsegment(es, __USER_DS);
1492 #endif
1493         reload_tss();
1494 #ifdef CONFIG_X86_64
1495         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1496 #endif
1497         if (user_has_fpu())
1498                 clts();
1499         load_gdt(&__get_cpu_var(host_gdt));
1500 }
1501
1502 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1503 {
1504         preempt_disable();
1505         __vmx_load_host_state(vmx);
1506         preempt_enable();
1507 }
1508
1509 /*
1510  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1511  * vcpu mutex is already taken.
1512  */
1513 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1514 {
1515         struct vcpu_vmx *vmx = to_vmx(vcpu);
1516         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1517
1518         if (!vmm_exclusive)
1519                 kvm_cpu_vmxon(phys_addr);
1520         else if (vmx->loaded_vmcs->cpu != cpu)
1521                 loaded_vmcs_clear(vmx->loaded_vmcs);
1522
1523         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1524                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1525                 vmcs_load(vmx->loaded_vmcs->vmcs);
1526         }
1527
1528         if (vmx->loaded_vmcs->cpu != cpu) {
1529                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1530                 unsigned long sysenter_esp;
1531
1532                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1533                 local_irq_disable();
1534                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1535                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1536                 local_irq_enable();
1537
1538                 /*
1539                  * Linux uses per-cpu TSS and GDT, so set these when switching
1540                  * processors.
1541                  */
1542                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1543                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1544
1545                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1546                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1547                 vmx->loaded_vmcs->cpu = cpu;
1548         }
1549 }
1550
1551 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1552 {
1553         __vmx_load_host_state(to_vmx(vcpu));
1554         if (!vmm_exclusive) {
1555                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1556                 vcpu->cpu = -1;
1557                 kvm_cpu_vmxoff();
1558         }
1559 }
1560
1561 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1562 {
1563         ulong cr0;
1564
1565         if (vcpu->fpu_active)
1566                 return;
1567         vcpu->fpu_active = 1;
1568         cr0 = vmcs_readl(GUEST_CR0);
1569         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1570         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1571         vmcs_writel(GUEST_CR0, cr0);
1572         update_exception_bitmap(vcpu);
1573         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1574         if (is_guest_mode(vcpu))
1575                 vcpu->arch.cr0_guest_owned_bits &=
1576                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1577         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1578 }
1579
1580 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1581
1582 /*
1583  * Return the cr0 value that a nested guest would read. This is a combination
1584  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1585  * its hypervisor (cr0_read_shadow).
1586  */
1587 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1588 {
1589         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1590                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1591 }
1592 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1593 {
1594         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1595                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1596 }
1597
1598 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1599 {
1600         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1601          * set this *before* calling this function.
1602          */
1603         vmx_decache_cr0_guest_bits(vcpu);
1604         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1605         update_exception_bitmap(vcpu);
1606         vcpu->arch.cr0_guest_owned_bits = 0;
1607         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1608         if (is_guest_mode(vcpu)) {
1609                 /*
1610                  * L1's specified read shadow might not contain the TS bit,
1611                  * so now that we turned on shadowing of this bit, we need to
1612                  * set this bit of the shadow. Like in nested_vmx_run we need
1613                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1614                  * up-to-date here because we just decached cr0.TS (and we'll
1615                  * only update vmcs12->guest_cr0 on nested exit).
1616                  */
1617                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1618                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1619                         (vcpu->arch.cr0 & X86_CR0_TS);
1620                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1621         } else
1622                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1623 }
1624
1625 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1626 {
1627         unsigned long rflags, save_rflags;
1628
1629         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1630                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1631                 rflags = vmcs_readl(GUEST_RFLAGS);
1632                 if (to_vmx(vcpu)->rmode.vm86_active) {
1633                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1634                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1635                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1636                 }
1637                 to_vmx(vcpu)->rflags = rflags;
1638         }
1639         return to_vmx(vcpu)->rflags;
1640 }
1641
1642 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1643 {
1644         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1645         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
1646         to_vmx(vcpu)->rflags = rflags;
1647         if (to_vmx(vcpu)->rmode.vm86_active) {
1648                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1649                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1650         }
1651         vmcs_writel(GUEST_RFLAGS, rflags);
1652 }
1653
1654 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1655 {
1656         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1657         int ret = 0;
1658
1659         if (interruptibility & GUEST_INTR_STATE_STI)
1660                 ret |= KVM_X86_SHADOW_INT_STI;
1661         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1662                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1663
1664         return ret & mask;
1665 }
1666
1667 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1668 {
1669         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1670         u32 interruptibility = interruptibility_old;
1671
1672         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1673
1674         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1675                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1676         else if (mask & KVM_X86_SHADOW_INT_STI)
1677                 interruptibility |= GUEST_INTR_STATE_STI;
1678
1679         if ((interruptibility != interruptibility_old))
1680                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1681 }
1682
1683 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1684 {
1685         unsigned long rip;
1686
1687         rip = kvm_rip_read(vcpu);
1688         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1689         kvm_rip_write(vcpu, rip);
1690
1691         /* skipping an emulated instruction also counts */
1692         vmx_set_interrupt_shadow(vcpu, 0);
1693 }
1694
1695 /*
1696  * KVM wants to inject page-faults which it got to the guest. This function
1697  * checks whether in a nested guest, we need to inject them to L1 or L2.
1698  * This function assumes it is called with the exit reason in vmcs02 being
1699  * a #PF exception (this is the only case in which KVM injects a #PF when L2
1700  * is running).
1701  */
1702 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1703 {
1704         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1705
1706         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1707         if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
1708                 return 0;
1709
1710         nested_vmx_vmexit(vcpu);
1711         return 1;
1712 }
1713
1714 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1715                                 bool has_error_code, u32 error_code,
1716                                 bool reinject)
1717 {
1718         struct vcpu_vmx *vmx = to_vmx(vcpu);
1719         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1720
1721         if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1722                 nested_pf_handled(vcpu))
1723                 return;
1724
1725         if (has_error_code) {
1726                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1727                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1728         }
1729
1730         if (vmx->rmode.vm86_active) {
1731                 int inc_eip = 0;
1732                 if (kvm_exception_is_soft(nr))
1733                         inc_eip = vcpu->arch.event_exit_inst_len;
1734                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1735                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1736                 return;
1737         }
1738
1739         if (kvm_exception_is_soft(nr)) {
1740                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1741                              vmx->vcpu.arch.event_exit_inst_len);
1742                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1743         } else
1744                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1745
1746         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1747 }
1748
1749 static bool vmx_rdtscp_supported(void)
1750 {
1751         return cpu_has_vmx_rdtscp();
1752 }
1753
1754 /*
1755  * Swap MSR entry in host/guest MSR entry array.
1756  */
1757 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1758 {
1759         struct shared_msr_entry tmp;
1760
1761         tmp = vmx->guest_msrs[to];
1762         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1763         vmx->guest_msrs[from] = tmp;
1764 }
1765
1766 /*
1767  * Set up the vmcs to automatically save and restore system
1768  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1769  * mode, as fiddling with msrs is very expensive.
1770  */
1771 static void setup_msrs(struct vcpu_vmx *vmx)
1772 {
1773         int save_nmsrs, index;
1774         unsigned long *msr_bitmap;
1775
1776         save_nmsrs = 0;
1777 #ifdef CONFIG_X86_64
1778         if (is_long_mode(&vmx->vcpu)) {
1779                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1780                 if (index >= 0)
1781                         move_msr_up(vmx, index, save_nmsrs++);
1782                 index = __find_msr_index(vmx, MSR_LSTAR);
1783                 if (index >= 0)
1784                         move_msr_up(vmx, index, save_nmsrs++);
1785                 index = __find_msr_index(vmx, MSR_CSTAR);
1786                 if (index >= 0)
1787                         move_msr_up(vmx, index, save_nmsrs++);
1788                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1789                 if (index >= 0 && vmx->rdtscp_enabled)
1790                         move_msr_up(vmx, index, save_nmsrs++);
1791                 /*
1792                  * MSR_STAR is only needed on long mode guests, and only
1793                  * if efer.sce is enabled.
1794                  */
1795                 index = __find_msr_index(vmx, MSR_STAR);
1796                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1797                         move_msr_up(vmx, index, save_nmsrs++);
1798         }
1799 #endif
1800         index = __find_msr_index(vmx, MSR_EFER);
1801         if (index >= 0 && update_transition_efer(vmx, index))
1802                 move_msr_up(vmx, index, save_nmsrs++);
1803
1804         vmx->save_nmsrs = save_nmsrs;
1805
1806         if (cpu_has_vmx_msr_bitmap()) {
1807                 if (is_long_mode(&vmx->vcpu))
1808                         msr_bitmap = vmx_msr_bitmap_longmode;
1809                 else
1810                         msr_bitmap = vmx_msr_bitmap_legacy;
1811
1812                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1813         }
1814 }
1815
1816 /*
1817  * reads and returns guest's timestamp counter "register"
1818  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1819  */
1820 static u64 guest_read_tsc(void)
1821 {
1822         u64 host_tsc, tsc_offset;
1823
1824         rdtscll(host_tsc);
1825         tsc_offset = vmcs_read64(TSC_OFFSET);
1826         return host_tsc + tsc_offset;
1827 }
1828
1829 /*
1830  * Like guest_read_tsc, but always returns L1's notion of the timestamp
1831  * counter, even if a nested guest (L2) is currently running.
1832  */
1833 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu)
1834 {
1835         u64 host_tsc, tsc_offset;
1836
1837         rdtscll(host_tsc);
1838         tsc_offset = is_guest_mode(vcpu) ?
1839                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1840                 vmcs_read64(TSC_OFFSET);
1841         return host_tsc + tsc_offset;
1842 }
1843
1844 /*
1845  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
1846  * software catchup for faster rates on slower CPUs.
1847  */
1848 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1849 {
1850         if (!scale)
1851                 return;
1852
1853         if (user_tsc_khz > tsc_khz) {
1854                 vcpu->arch.tsc_catchup = 1;
1855                 vcpu->arch.tsc_always_catchup = 1;
1856         } else
1857                 WARN(1, "user requested TSC rate below hardware speed\n");
1858 }
1859
1860 /*
1861  * writes 'offset' into guest's timestamp counter offset register
1862  */
1863 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1864 {
1865         if (is_guest_mode(vcpu)) {
1866                 /*
1867                  * We're here if L1 chose not to trap WRMSR to TSC. According
1868                  * to the spec, this should set L1's TSC; The offset that L1
1869                  * set for L2 remains unchanged, and still needs to be added
1870                  * to the newly set TSC to get L2's TSC.
1871                  */
1872                 struct vmcs12 *vmcs12;
1873                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1874                 /* recalculate vmcs02.TSC_OFFSET: */
1875                 vmcs12 = get_vmcs12(vcpu);
1876                 vmcs_write64(TSC_OFFSET, offset +
1877                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1878                          vmcs12->tsc_offset : 0));
1879         } else {
1880                 vmcs_write64(TSC_OFFSET, offset);
1881         }
1882 }
1883
1884 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1885 {
1886         u64 offset = vmcs_read64(TSC_OFFSET);
1887         vmcs_write64(TSC_OFFSET, offset + adjustment);
1888         if (is_guest_mode(vcpu)) {
1889                 /* Even when running L2, the adjustment needs to apply to L1 */
1890                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1891         }
1892 }
1893
1894 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1895 {
1896         return target_tsc - native_read_tsc();
1897 }
1898
1899 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1900 {
1901         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1902         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1903 }
1904
1905 /*
1906  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1907  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1908  * all guests if the "nested" module option is off, and can also be disabled
1909  * for a single guest by disabling its VMX cpuid bit.
1910  */
1911 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1912 {
1913         return nested && guest_cpuid_has_vmx(vcpu);
1914 }
1915
1916 /*
1917  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1918  * returned for the various VMX controls MSRs when nested VMX is enabled.
1919  * The same values should also be used to verify that vmcs12 control fields are
1920  * valid during nested entry from L1 to L2.
1921  * Each of these control msrs has a low and high 32-bit half: A low bit is on
1922  * if the corresponding bit in the (32-bit) control field *must* be on, and a
1923  * bit in the high half is on if the corresponding bit in the control field
1924  * may be on. See also vmx_control_verify().
1925  * TODO: allow these variables to be modified (downgraded) by module options
1926  * or other means.
1927  */
1928 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1929 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1930 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1931 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1932 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1933 static __init void nested_vmx_setup_ctls_msrs(void)
1934 {
1935         /*
1936          * Note that as a general rule, the high half of the MSRs (bits in
1937          * the control fields which may be 1) should be initialized by the
1938          * intersection of the underlying hardware's MSR (i.e., features which
1939          * can be supported) and the list of features we want to expose -
1940          * because they are known to be properly supported in our code.
1941          * Also, usually, the low half of the MSRs (bits which must be 1) can
1942          * be set to 0, meaning that L1 may turn off any of these bits. The
1943          * reason is that if one of these bits is necessary, it will appear
1944          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1945          * fields of vmcs01 and vmcs02, will turn these bits off - and
1946          * nested_vmx_exit_handled() will not pass related exits to L1.
1947          * These rules have exceptions below.
1948          */
1949
1950         /* pin-based controls */
1951         /*
1952          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1953          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1954          */
1955         nested_vmx_pinbased_ctls_low = 0x16 ;
1956         nested_vmx_pinbased_ctls_high = 0x16 |
1957                 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1958                 PIN_BASED_VIRTUAL_NMIS;
1959
1960         /* exit controls */
1961         nested_vmx_exit_ctls_low = 0;
1962         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
1963 #ifdef CONFIG_X86_64
1964         nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1965 #else
1966         nested_vmx_exit_ctls_high = 0;
1967 #endif
1968
1969         /* entry controls */
1970         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1971                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1972         nested_vmx_entry_ctls_low = 0;
1973         nested_vmx_entry_ctls_high &=
1974                 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1975
1976         /* cpu-based controls */
1977         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1978                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1979         nested_vmx_procbased_ctls_low = 0;
1980         nested_vmx_procbased_ctls_high &=
1981                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1982                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1983                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1984                 CPU_BASED_CR3_STORE_EXITING |
1985 #ifdef CONFIG_X86_64
1986                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1987 #endif
1988                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1989                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1990                 CPU_BASED_RDPMC_EXITING |
1991                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1992         /*
1993          * We can allow some features even when not supported by the
1994          * hardware. For example, L1 can specify an MSR bitmap - and we
1995          * can use it to avoid exits to L1 - even when L0 runs L2
1996          * without MSR bitmaps.
1997          */
1998         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
1999
2000         /* secondary cpu-based controls */
2001         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2002                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2003         nested_vmx_secondary_ctls_low = 0;
2004         nested_vmx_secondary_ctls_high &=
2005                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2006 }
2007
2008 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2009 {
2010         /*
2011          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2012          */
2013         return ((control & high) | low) == control;
2014 }
2015
2016 static inline u64 vmx_control_msr(u32 low, u32 high)
2017 {
2018         return low | ((u64)high << 32);
2019 }
2020
2021 /*
2022  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2023  * also let it use VMX-specific MSRs.
2024  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2025  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2026  * like all other MSRs).
2027  */
2028 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2029 {
2030         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2031                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2032                 /*
2033                  * According to the spec, processors which do not support VMX
2034                  * should throw a #GP(0) when VMX capability MSRs are read.
2035                  */
2036                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2037                 return 1;
2038         }
2039
2040         switch (msr_index) {
2041         case MSR_IA32_FEATURE_CONTROL:
2042                 *pdata = 0;
2043                 break;
2044         case MSR_IA32_VMX_BASIC:
2045                 /*
2046                  * This MSR reports some information about VMX support. We
2047                  * should return information about the VMX we emulate for the
2048                  * guest, and the VMCS structure we give it - not about the
2049                  * VMX support of the underlying hardware.
2050                  */
2051                 *pdata = VMCS12_REVISION |
2052                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2053                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2054                 break;
2055         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2056         case MSR_IA32_VMX_PINBASED_CTLS:
2057                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2058                                         nested_vmx_pinbased_ctls_high);
2059                 break;
2060         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2061         case MSR_IA32_VMX_PROCBASED_CTLS:
2062                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2063                                         nested_vmx_procbased_ctls_high);
2064                 break;
2065         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2066         case MSR_IA32_VMX_EXIT_CTLS:
2067                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2068                                         nested_vmx_exit_ctls_high);
2069                 break;
2070         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2071         case MSR_IA32_VMX_ENTRY_CTLS:
2072                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2073                                         nested_vmx_entry_ctls_high);
2074                 break;
2075         case MSR_IA32_VMX_MISC:
2076                 *pdata = 0;
2077                 break;
2078         /*
2079          * These MSRs specify bits which the guest must keep fixed (on or off)
2080          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2081          * We picked the standard core2 setting.
2082          */
2083 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2084 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2085         case MSR_IA32_VMX_CR0_FIXED0:
2086                 *pdata = VMXON_CR0_ALWAYSON;
2087                 break;
2088         case MSR_IA32_VMX_CR0_FIXED1:
2089                 *pdata = -1ULL;
2090                 break;
2091         case MSR_IA32_VMX_CR4_FIXED0:
2092                 *pdata = VMXON_CR4_ALWAYSON;
2093                 break;
2094         case MSR_IA32_VMX_CR4_FIXED1:
2095                 *pdata = -1ULL;
2096                 break;
2097         case MSR_IA32_VMX_VMCS_ENUM:
2098                 *pdata = 0x1f;
2099                 break;
2100         case MSR_IA32_VMX_PROCBASED_CTLS2:
2101                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2102                                         nested_vmx_secondary_ctls_high);
2103                 break;
2104         case MSR_IA32_VMX_EPT_VPID_CAP:
2105                 /* Currently, no nested ept or nested vpid */
2106                 *pdata = 0;
2107                 break;
2108         default:
2109                 return 0;
2110         }
2111
2112         return 1;
2113 }
2114
2115 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2116 {
2117         if (!nested_vmx_allowed(vcpu))
2118                 return 0;
2119
2120         if (msr_index == MSR_IA32_FEATURE_CONTROL)
2121                 /* TODO: the right thing. */
2122                 return 1;
2123         /*
2124          * No need to treat VMX capability MSRs specially: If we don't handle
2125          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2126          */
2127         return 0;
2128 }
2129
2130 /*
2131  * Reads an msr value (of 'msr_index') into 'pdata'.
2132  * Returns 0 on success, non-0 otherwise.
2133  * Assumes vcpu_load() was already called.
2134  */
2135 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2136 {
2137         u64 data;
2138         struct shared_msr_entry *msr;
2139
2140         if (!pdata) {
2141                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2142                 return -EINVAL;
2143         }
2144
2145         switch (msr_index) {
2146 #ifdef CONFIG_X86_64
2147         case MSR_FS_BASE:
2148                 data = vmcs_readl(GUEST_FS_BASE);
2149                 break;
2150         case MSR_GS_BASE:
2151                 data = vmcs_readl(GUEST_GS_BASE);
2152                 break;
2153         case MSR_KERNEL_GS_BASE:
2154                 vmx_load_host_state(to_vmx(vcpu));
2155                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2156                 break;
2157 #endif
2158         case MSR_EFER:
2159                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2160         case MSR_IA32_TSC:
2161                 data = guest_read_tsc();
2162                 break;
2163         case MSR_IA32_SYSENTER_CS:
2164                 data = vmcs_read32(GUEST_SYSENTER_CS);
2165                 break;
2166         case MSR_IA32_SYSENTER_EIP:
2167                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2168                 break;
2169         case MSR_IA32_SYSENTER_ESP:
2170                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2171                 break;
2172         case MSR_TSC_AUX:
2173                 if (!to_vmx(vcpu)->rdtscp_enabled)
2174                         return 1;
2175                 /* Otherwise falls through */
2176         default:
2177                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2178                         return 0;
2179                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2180                 if (msr) {
2181                         data = msr->data;
2182                         break;
2183                 }
2184                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2185         }
2186
2187         *pdata = data;
2188         return 0;
2189 }
2190
2191 /*
2192  * Writes msr value into into the appropriate "register".
2193  * Returns 0 on success, non-0 otherwise.
2194  * Assumes vcpu_load() was already called.
2195  */
2196 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2197 {
2198         struct vcpu_vmx *vmx = to_vmx(vcpu);
2199         struct shared_msr_entry *msr;
2200         int ret = 0;
2201
2202         switch (msr_index) {
2203         case MSR_EFER:
2204                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2205                 break;
2206 #ifdef CONFIG_X86_64
2207         case MSR_FS_BASE:
2208                 vmx_segment_cache_clear(vmx);
2209                 vmcs_writel(GUEST_FS_BASE, data);
2210                 break;
2211         case MSR_GS_BASE:
2212                 vmx_segment_cache_clear(vmx);
2213                 vmcs_writel(GUEST_GS_BASE, data);
2214                 break;
2215         case MSR_KERNEL_GS_BASE:
2216                 vmx_load_host_state(vmx);
2217                 vmx->msr_guest_kernel_gs_base = data;
2218                 break;
2219 #endif
2220         case MSR_IA32_SYSENTER_CS:
2221                 vmcs_write32(GUEST_SYSENTER_CS, data);
2222                 break;
2223         case MSR_IA32_SYSENTER_EIP:
2224                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2225                 break;
2226         case MSR_IA32_SYSENTER_ESP:
2227                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2228                 break;
2229         case MSR_IA32_TSC:
2230                 kvm_write_tsc(vcpu, data);
2231                 break;
2232         case MSR_IA32_CR_PAT:
2233                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2234                         vmcs_write64(GUEST_IA32_PAT, data);
2235                         vcpu->arch.pat = data;
2236                         break;
2237                 }
2238                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2239                 break;
2240         case MSR_TSC_AUX:
2241                 if (!vmx->rdtscp_enabled)
2242                         return 1;
2243                 /* Check reserved bit, higher 32 bits should be zero */
2244                 if ((data >> 32) != 0)
2245                         return 1;
2246                 /* Otherwise falls through */
2247         default:
2248                 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2249                         break;
2250                 msr = find_msr_entry(vmx, msr_index);
2251                 if (msr) {
2252                         msr->data = data;
2253                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2254                                 preempt_disable();
2255                                 kvm_set_shared_msr(msr->index, msr->data,
2256                                                    msr->mask);
2257                                 preempt_enable();
2258                         }
2259                         break;
2260                 }
2261                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2262         }
2263
2264         return ret;
2265 }
2266
2267 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2268 {
2269         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2270         switch (reg) {
2271         case VCPU_REGS_RSP:
2272                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2273                 break;
2274         case VCPU_REGS_RIP:
2275                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2276                 break;
2277         case VCPU_EXREG_PDPTR:
2278                 if (enable_ept)
2279                         ept_save_pdptrs(vcpu);
2280                 break;
2281         default:
2282                 break;
2283         }
2284 }
2285
2286 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
2287 {
2288         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2289                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2290         else
2291                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2292
2293         update_exception_bitmap(vcpu);
2294 }
2295
2296 static __init int cpu_has_kvm_support(void)
2297 {
2298         return cpu_has_vmx();
2299 }
2300
2301 static __init int vmx_disabled_by_bios(void)
2302 {
2303         u64 msr;
2304
2305         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2306         if (msr & FEATURE_CONTROL_LOCKED) {
2307                 /* launched w/ TXT and VMX disabled */
2308                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2309                         && tboot_enabled())
2310                         return 1;
2311                 /* launched w/o TXT and VMX only enabled w/ TXT */
2312                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2313                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2314                         && !tboot_enabled()) {
2315                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2316                                 "activate TXT before enabling KVM\n");
2317                         return 1;
2318                 }
2319                 /* launched w/o TXT and VMX disabled */
2320                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2321                         && !tboot_enabled())
2322                         return 1;
2323         }
2324
2325         return 0;
2326 }
2327
2328 static void kvm_cpu_vmxon(u64 addr)
2329 {
2330         asm volatile (ASM_VMX_VMXON_RAX
2331                         : : "a"(&addr), "m"(addr)
2332                         : "memory", "cc");
2333 }
2334
2335 static int hardware_enable(void *garbage)
2336 {
2337         int cpu = raw_smp_processor_id();
2338         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2339         u64 old, test_bits;
2340
2341         if (read_cr4() & X86_CR4_VMXE)
2342                 return -EBUSY;
2343
2344         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2345         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2346
2347         test_bits = FEATURE_CONTROL_LOCKED;
2348         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2349         if (tboot_enabled())
2350                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2351
2352         if ((old & test_bits) != test_bits) {
2353                 /* enable and lock */
2354                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2355         }
2356         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2357
2358         if (vmm_exclusive) {
2359                 kvm_cpu_vmxon(phys_addr);
2360                 ept_sync_global();
2361         }
2362
2363         store_gdt(&__get_cpu_var(host_gdt));
2364
2365         return 0;
2366 }
2367
2368 static void vmclear_local_loaded_vmcss(void)
2369 {
2370         int cpu = raw_smp_processor_id();
2371         struct loaded_vmcs *v, *n;
2372
2373         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2374                                  loaded_vmcss_on_cpu_link)
2375                 __loaded_vmcs_clear(v);
2376 }
2377
2378
2379 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2380  * tricks.
2381  */
2382 static void kvm_cpu_vmxoff(void)
2383 {
2384         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2385 }
2386
2387 static void hardware_disable(void *garbage)
2388 {
2389         if (vmm_exclusive) {
2390                 vmclear_local_loaded_vmcss();
2391                 kvm_cpu_vmxoff();
2392         }
2393         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2394 }
2395
2396 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2397                                       u32 msr, u32 *result)
2398 {
2399         u32 vmx_msr_low, vmx_msr_high;
2400         u32 ctl = ctl_min | ctl_opt;
2401
2402         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2403
2404         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2405         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2406
2407         /* Ensure minimum (required) set of control bits are supported. */
2408         if (ctl_min & ~ctl)
2409                 return -EIO;
2410
2411         *result = ctl;
2412         return 0;
2413 }
2414
2415 static __init bool allow_1_setting(u32 msr, u32 ctl)
2416 {
2417         u32 vmx_msr_low, vmx_msr_high;
2418
2419         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2420         return vmx_msr_high & ctl;
2421 }
2422
2423 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2424 {
2425         u32 vmx_msr_low, vmx_msr_high;
2426         u32 min, opt, min2, opt2;
2427         u32 _pin_based_exec_control = 0;
2428         u32 _cpu_based_exec_control = 0;
2429         u32 _cpu_based_2nd_exec_control = 0;
2430         u32 _vmexit_control = 0;
2431         u32 _vmentry_control = 0;
2432
2433         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2434         opt = PIN_BASED_VIRTUAL_NMIS;
2435         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2436                                 &_pin_based_exec_control) < 0)
2437                 return -EIO;
2438
2439         min = CPU_BASED_HLT_EXITING |
2440 #ifdef CONFIG_X86_64
2441               CPU_BASED_CR8_LOAD_EXITING |
2442               CPU_BASED_CR8_STORE_EXITING |
2443 #endif
2444               CPU_BASED_CR3_LOAD_EXITING |
2445               CPU_BASED_CR3_STORE_EXITING |
2446               CPU_BASED_USE_IO_BITMAPS |
2447               CPU_BASED_MOV_DR_EXITING |
2448               CPU_BASED_USE_TSC_OFFSETING |
2449               CPU_BASED_MWAIT_EXITING |
2450               CPU_BASED_MONITOR_EXITING |
2451               CPU_BASED_INVLPG_EXITING |
2452               CPU_BASED_RDPMC_EXITING;
2453
2454         opt = CPU_BASED_TPR_SHADOW |
2455               CPU_BASED_USE_MSR_BITMAPS |
2456               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2457         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2458                                 &_cpu_based_exec_control) < 0)
2459                 return -EIO;
2460 #ifdef CONFIG_X86_64
2461         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2462                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2463                                            ~CPU_BASED_CR8_STORE_EXITING;
2464 #endif
2465         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2466                 min2 = 0;
2467                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2468                         SECONDARY_EXEC_WBINVD_EXITING |
2469                         SECONDARY_EXEC_ENABLE_VPID |
2470                         SECONDARY_EXEC_ENABLE_EPT |
2471                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2472                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2473                         SECONDARY_EXEC_RDTSCP;
2474                 if (adjust_vmx_controls(min2, opt2,
2475                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2476                                         &_cpu_based_2nd_exec_control) < 0)
2477                         return -EIO;
2478         }
2479 #ifndef CONFIG_X86_64
2480         if (!(_cpu_based_2nd_exec_control &
2481                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2482                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2483 #endif
2484         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2485                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2486                    enabled */
2487                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2488                                              CPU_BASED_CR3_STORE_EXITING |
2489                                              CPU_BASED_INVLPG_EXITING);
2490                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2491                       vmx_capability.ept, vmx_capability.vpid);
2492         }
2493
2494         min = 0;
2495 #ifdef CONFIG_X86_64
2496         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2497 #endif
2498         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2499         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2500                                 &_vmexit_control) < 0)
2501                 return -EIO;
2502
2503         min = 0;
2504         opt = VM_ENTRY_LOAD_IA32_PAT;
2505         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2506                                 &_vmentry_control) < 0)
2507                 return -EIO;
2508
2509         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2510
2511         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2512         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2513                 return -EIO;
2514
2515 #ifdef CONFIG_X86_64
2516         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2517         if (vmx_msr_high & (1u<<16))
2518                 return -EIO;
2519 #endif
2520
2521         /* Require Write-Back (WB) memory type for VMCS accesses. */
2522         if (((vmx_msr_high >> 18) & 15) != 6)
2523                 return -EIO;
2524
2525         vmcs_conf->size = vmx_msr_high & 0x1fff;
2526         vmcs_conf->order = get_order(vmcs_config.size);
2527         vmcs_conf->revision_id = vmx_msr_low;
2528
2529         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2530         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2531         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2532         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2533         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2534
2535         cpu_has_load_ia32_efer =
2536                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2537                                 VM_ENTRY_LOAD_IA32_EFER)
2538                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2539                                    VM_EXIT_LOAD_IA32_EFER);
2540
2541         cpu_has_load_perf_global_ctrl =
2542                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2543                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2544                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2545                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2546
2547         /*
2548          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2549          * but due to arrata below it can't be used. Workaround is to use
2550          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2551          *
2552          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2553          *
2554          * AAK155             (model 26)
2555          * AAP115             (model 30)
2556          * AAT100             (model 37)
2557          * BC86,AAY89,BD102   (model 44)
2558          * BA97               (model 46)
2559          *
2560          */
2561         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2562                 switch (boot_cpu_data.x86_model) {
2563                 case 26:
2564                 case 30:
2565                 case 37:
2566                 case 44:
2567                 case 46:
2568                         cpu_has_load_perf_global_ctrl = false;
2569                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2570                                         "does not work properly. Using workaround\n");
2571                         break;
2572                 default:
2573                         break;
2574                 }
2575         }
2576
2577         return 0;
2578 }
2579
2580 static struct vmcs *alloc_vmcs_cpu(int cpu)
2581 {
2582         int node = cpu_to_node(cpu);
2583         struct page *pages;
2584         struct vmcs *vmcs;
2585
2586         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2587         if (!pages)
2588                 return NULL;
2589         vmcs = page_address(pages);
2590         memset(vmcs, 0, vmcs_config.size);
2591         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2592         return vmcs;
2593 }
2594
2595 static struct vmcs *alloc_vmcs(void)
2596 {
2597         return alloc_vmcs_cpu(raw_smp_processor_id());
2598 }
2599
2600 static void free_vmcs(struct vmcs *vmcs)
2601 {
2602         free_pages((unsigned long)vmcs, vmcs_config.order);
2603 }
2604
2605 /*
2606  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2607  */
2608 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2609 {
2610         if (!loaded_vmcs->vmcs)
2611                 return;
2612         loaded_vmcs_clear(loaded_vmcs);
2613         free_vmcs(loaded_vmcs->vmcs);
2614         loaded_vmcs->vmcs = NULL;
2615 }
2616
2617 static void free_kvm_area(void)
2618 {
2619         int cpu;
2620
2621         for_each_possible_cpu(cpu) {
2622                 free_vmcs(per_cpu(vmxarea, cpu));
2623                 per_cpu(vmxarea, cpu) = NULL;
2624         }
2625 }
2626
2627 static __init int alloc_kvm_area(void)
2628 {
2629         int cpu;
2630
2631         for_each_possible_cpu(cpu) {
2632                 struct vmcs *vmcs;
2633
2634                 vmcs = alloc_vmcs_cpu(cpu);
2635                 if (!vmcs) {
2636                         free_kvm_area();
2637                         return -ENOMEM;
2638                 }
2639
2640                 per_cpu(vmxarea, cpu) = vmcs;
2641         }
2642         return 0;
2643 }
2644
2645 static __init int hardware_setup(void)
2646 {
2647         if (setup_vmcs_config(&vmcs_config) < 0)
2648                 return -EIO;
2649
2650         if (boot_cpu_has(X86_FEATURE_NX))
2651                 kvm_enable_efer_bits(EFER_NX);
2652
2653         if (!cpu_has_vmx_vpid())
2654                 enable_vpid = 0;
2655
2656         if (!cpu_has_vmx_ept() ||
2657             !cpu_has_vmx_ept_4levels()) {
2658                 enable_ept = 0;
2659                 enable_unrestricted_guest = 0;
2660                 enable_ept_ad_bits = 0;
2661         }
2662
2663         if (!cpu_has_vmx_ept_ad_bits())
2664                 enable_ept_ad_bits = 0;
2665
2666         if (!cpu_has_vmx_unrestricted_guest())
2667                 enable_unrestricted_guest = 0;
2668
2669         if (!cpu_has_vmx_flexpriority())
2670                 flexpriority_enabled = 0;
2671
2672         if (!cpu_has_vmx_tpr_shadow())
2673                 kvm_x86_ops->update_cr8_intercept = NULL;
2674
2675         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2676                 kvm_disable_largepages();
2677
2678         if (!cpu_has_vmx_ple())
2679                 ple_gap = 0;
2680
2681         if (nested)
2682                 nested_vmx_setup_ctls_msrs();
2683
2684         return alloc_kvm_area();
2685 }
2686
2687 static __exit void hardware_unsetup(void)
2688 {
2689         free_kvm_area();
2690 }
2691
2692 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2693 {
2694         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2695
2696         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
2697                 vmcs_write16(sf->selector, save->selector);
2698                 vmcs_writel(sf->base, save->base);
2699                 vmcs_write32(sf->limit, save->limit);
2700                 vmcs_write32(sf->ar_bytes, save->ar);
2701         } else {
2702                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2703                         << AR_DPL_SHIFT;
2704                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2705         }
2706 }
2707
2708 static void enter_pmode(struct kvm_vcpu *vcpu)
2709 {
2710         unsigned long flags;
2711         struct vcpu_vmx *vmx = to_vmx(vcpu);
2712
2713         vmx->emulation_required = 1;
2714         vmx->rmode.vm86_active = 0;
2715
2716         vmx_segment_cache_clear(vmx);
2717
2718         vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
2719         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2720         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2721         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
2722
2723         flags = vmcs_readl(GUEST_RFLAGS);
2724         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2725         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2726         vmcs_writel(GUEST_RFLAGS, flags);
2727
2728         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2729                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2730
2731         update_exception_bitmap(vcpu);
2732
2733         if (emulate_invalid_guest_state)
2734                 return;
2735
2736         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2737         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2738         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2739         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
2740
2741         vmx_segment_cache_clear(vmx);
2742
2743         vmcs_write16(GUEST_SS_SELECTOR, 0);
2744         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2745
2746         vmcs_write16(GUEST_CS_SELECTOR,
2747                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2748         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2749 }
2750
2751 static gva_t rmode_tss_base(struct kvm *kvm)
2752 {
2753         if (!kvm->arch.tss_addr) {
2754                 struct kvm_memslots *slots;
2755                 struct kvm_memory_slot *slot;
2756                 gfn_t base_gfn;
2757
2758                 slots = kvm_memslots(kvm);
2759                 slot = id_to_memslot(slots, 0);
2760                 base_gfn = slot->base_gfn + slot->npages - 3;
2761
2762                 return base_gfn << PAGE_SHIFT;
2763         }
2764         return kvm->arch.tss_addr;
2765 }
2766
2767 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2768 {
2769         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2770
2771         save->selector = vmcs_read16(sf->selector);
2772         save->base = vmcs_readl(sf->base);
2773         save->limit = vmcs_read32(sf->limit);
2774         save->ar = vmcs_read32(sf->ar_bytes);
2775         vmcs_write16(sf->selector, save->base >> 4);
2776         vmcs_write32(sf->base, save->base & 0xffff0);
2777         vmcs_write32(sf->limit, 0xffff);
2778         vmcs_write32(sf->ar_bytes, 0xf3);
2779         if (save->base & 0xf)
2780                 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2781                             " aligned when entering protected mode (seg=%d)",
2782                             seg);
2783 }
2784
2785 static void enter_rmode(struct kvm_vcpu *vcpu)
2786 {
2787         unsigned long flags;
2788         struct vcpu_vmx *vmx = to_vmx(vcpu);
2789         struct kvm_segment var;
2790
2791         if (enable_unrestricted_guest)
2792                 return;
2793
2794         vmx->emulation_required = 1;
2795         vmx->rmode.vm86_active = 1;
2796
2797         /*
2798          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2799          * vcpu. Call it here with phys address pointing 16M below 4G.
2800          */
2801         if (!vcpu->kvm->arch.tss_addr) {
2802                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2803                              "called before entering vcpu\n");
2804                 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2805                 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2806                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2807         }
2808
2809         vmx_segment_cache_clear(vmx);
2810
2811         vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
2812         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
2813         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2814
2815         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
2816         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2817
2818         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
2819         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2820
2821         flags = vmcs_readl(GUEST_RFLAGS);
2822         vmx->rmode.save_rflags = flags;
2823
2824         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2825
2826         vmcs_writel(GUEST_RFLAGS, flags);
2827         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2828         update_exception_bitmap(vcpu);
2829
2830         if (emulate_invalid_guest_state)
2831                 goto continue_rmode;
2832
2833         vmx_get_segment(vcpu, &var, VCPU_SREG_SS);
2834         vmx_set_segment(vcpu, &var, VCPU_SREG_SS);
2835
2836         vmx_get_segment(vcpu, &var, VCPU_SREG_CS);
2837         vmx_set_segment(vcpu, &var, VCPU_SREG_CS);
2838
2839         vmx_get_segment(vcpu, &var, VCPU_SREG_ES);
2840         vmx_set_segment(vcpu, &var, VCPU_SREG_ES);
2841
2842         vmx_get_segment(vcpu, &var, VCPU_SREG_DS);
2843         vmx_set_segment(vcpu, &var, VCPU_SREG_DS);
2844
2845         vmx_get_segment(vcpu, &var, VCPU_SREG_GS);
2846         vmx_set_segment(vcpu, &var, VCPU_SREG_GS);
2847
2848         vmx_get_segment(vcpu, &var, VCPU_SREG_FS);
2849         vmx_set_segment(vcpu, &var, VCPU_SREG_FS);
2850
2851 continue_rmode:
2852         kvm_mmu_reset_context(vcpu);
2853 }
2854
2855 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2856 {
2857         struct vcpu_vmx *vmx = to_vmx(vcpu);
2858         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2859
2860         if (!msr)
2861                 return;
2862
2863         /*
2864          * Force kernel_gs_base reloading before EFER changes, as control
2865          * of this msr depends on is_long_mode().
2866          */
2867         vmx_load_host_state(to_vmx(vcpu));
2868         vcpu->arch.efer = efer;
2869         if (efer & EFER_LMA) {
2870                 vmcs_write32(VM_ENTRY_CONTROLS,
2871                              vmcs_read32(VM_ENTRY_CONTROLS) |
2872                              VM_ENTRY_IA32E_MODE);
2873                 msr->data = efer;
2874         } else {
2875                 vmcs_write32(VM_ENTRY_CONTROLS,
2876                              vmcs_read32(VM_ENTRY_CONTROLS) &
2877                              ~VM_ENTRY_IA32E_MODE);
2878
2879                 msr->data = efer & ~EFER_LME;
2880         }
2881         setup_msrs(vmx);
2882 }
2883
2884 #ifdef CONFIG_X86_64
2885
2886 static void enter_lmode(struct kvm_vcpu *vcpu)
2887 {
2888         u32 guest_tr_ar;
2889
2890         vmx_segment_cache_clear(to_vmx(vcpu));
2891
2892         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2893         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2894                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2895                                      __func__);
2896                 vmcs_write32(GUEST_TR_AR_BYTES,
2897                              (guest_tr_ar & ~AR_TYPE_MASK)
2898                              | AR_TYPE_BUSY_64_TSS);
2899         }
2900         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2901 }
2902
2903 static void exit_lmode(struct kvm_vcpu *vcpu)
2904 {
2905         vmcs_write32(VM_ENTRY_CONTROLS,
2906                      vmcs_read32(VM_ENTRY_CONTROLS)
2907                      & ~VM_ENTRY_IA32E_MODE);
2908         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2909 }
2910
2911 #endif
2912
2913 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2914 {
2915         vpid_sync_context(to_vmx(vcpu));
2916         if (enable_ept) {
2917                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2918                         return;
2919                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2920         }
2921 }
2922
2923 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2924 {
2925         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2926
2927         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2928         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2929 }
2930
2931 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2932 {
2933         if (enable_ept && is_paging(vcpu))
2934                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2935         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2936 }
2937
2938 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2939 {
2940         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2941
2942         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2943         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2944 }
2945
2946 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2947 {
2948         if (!test_bit(VCPU_EXREG_PDPTR,
2949                       (unsigned long *)&vcpu->arch.regs_dirty))
2950                 return;
2951
2952         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2953                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2954                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2955                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2956                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
2957         }
2958 }
2959
2960 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2961 {
2962         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2963                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2964                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2965                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2966                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2967         }
2968
2969         __set_bit(VCPU_EXREG_PDPTR,
2970                   (unsigned long *)&vcpu->arch.regs_avail);
2971         __set_bit(VCPU_EXREG_PDPTR,
2972                   (unsigned long *)&vcpu->arch.regs_dirty);
2973 }
2974
2975 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2976
2977 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2978                                         unsigned long cr0,
2979                                         struct kvm_vcpu *vcpu)
2980 {
2981         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2982                 vmx_decache_cr3(vcpu);
2983         if (!(cr0 & X86_CR0_PG)) {
2984                 /* From paging/starting to nonpaging */
2985                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2986                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
2987                              (CPU_BASED_CR3_LOAD_EXITING |
2988                               CPU_BASED_CR3_STORE_EXITING));
2989                 vcpu->arch.cr0 = cr0;
2990                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2991         } else if (!is_paging(vcpu)) {
2992                 /* From nonpaging to paging */
2993                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2994                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
2995                              ~(CPU_BASED_CR3_LOAD_EXITING |
2996                                CPU_BASED_CR3_STORE_EXITING));
2997                 vcpu->arch.cr0 = cr0;
2998                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2999         }
3000
3001         if (!(cr0 & X86_CR0_WP))
3002                 *hw_cr0 &= ~X86_CR0_WP;
3003 }
3004
3005 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3006 {
3007         struct vcpu_vmx *vmx = to_vmx(vcpu);
3008         unsigned long hw_cr0;
3009
3010         if (enable_unrestricted_guest)
3011                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
3012                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3013         else
3014                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
3015
3016         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3017                 enter_pmode(vcpu);
3018
3019         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3020                 enter_rmode(vcpu);
3021
3022 #ifdef CONFIG_X86_64
3023         if (vcpu->arch.efer & EFER_LME) {
3024                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3025                         enter_lmode(vcpu);
3026                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3027                         exit_lmode(vcpu);
3028         }
3029 #endif
3030
3031         if (enable_ept)
3032                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3033
3034         if (!vcpu->fpu_active)
3035                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3036
3037         vmcs_writel(CR0_READ_SHADOW, cr0);
3038         vmcs_writel(GUEST_CR0, hw_cr0);
3039         vcpu->arch.cr0 = cr0;
3040         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3041 }
3042
3043 static u64 construct_eptp(unsigned long root_hpa)
3044 {
3045         u64 eptp;
3046
3047         /* TODO write the value reading from MSR */
3048         eptp = VMX_EPT_DEFAULT_MT |
3049                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3050         if (enable_ept_ad_bits)
3051                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3052         eptp |= (root_hpa & PAGE_MASK);
3053
3054         return eptp;
3055 }
3056
3057 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3058 {
3059         unsigned long guest_cr3;
3060         u64 eptp;
3061
3062         guest_cr3 = cr3;
3063         if (enable_ept) {
3064                 eptp = construct_eptp(cr3);
3065                 vmcs_write64(EPT_POINTER, eptp);
3066                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3067                         vcpu->kvm->arch.ept_identity_map_addr;
3068                 ept_load_pdptrs(vcpu);
3069         }
3070
3071         vmx_flush_tlb(vcpu);
3072         vmcs_writel(GUEST_CR3, guest_cr3);
3073 }
3074
3075 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3076 {
3077         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3078                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3079
3080         if (cr4 & X86_CR4_VMXE) {
3081                 /*
3082                  * To use VMXON (and later other VMX instructions), a guest
3083                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3084                  * So basically the check on whether to allow nested VMX
3085                  * is here.
3086                  */
3087                 if (!nested_vmx_allowed(vcpu))
3088                         return 1;
3089         } else if (to_vmx(vcpu)->nested.vmxon)
3090                 return 1;
3091
3092         vcpu->arch.cr4 = cr4;
3093         if (enable_ept) {
3094                 if (!is_paging(vcpu)) {
3095                         hw_cr4 &= ~X86_CR4_PAE;
3096                         hw_cr4 |= X86_CR4_PSE;
3097                 } else if (!(cr4 & X86_CR4_PAE)) {
3098                         hw_cr4 &= ~X86_CR4_PAE;
3099                 }
3100         }
3101
3102         vmcs_writel(CR4_READ_SHADOW, cr4);
3103         vmcs_writel(GUEST_CR4, hw_cr4);
3104         return 0;
3105 }
3106
3107 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3108                             struct kvm_segment *var, int seg)
3109 {
3110         struct vcpu_vmx *vmx = to_vmx(vcpu);
3111         struct kvm_save_segment *save;
3112         u32 ar;
3113
3114         if (vmx->rmode.vm86_active
3115             && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
3116                 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
3117                 || seg == VCPU_SREG_GS)
3118             && !emulate_invalid_guest_state) {
3119                 switch (seg) {
3120                 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
3121                 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
3122                 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
3123                 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
3124                 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
3125                 default: BUG();
3126                 }
3127                 var->selector = save->selector;
3128                 var->base = save->base;
3129                 var->limit = save->limit;
3130                 ar = save->ar;
3131                 if (seg == VCPU_SREG_TR
3132                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3133                         goto use_saved_rmode_seg;
3134         }
3135         var->base = vmx_read_guest_seg_base(vmx, seg);
3136         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3137         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3138         ar = vmx_read_guest_seg_ar(vmx, seg);
3139 use_saved_rmode_seg:
3140         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
3141                 ar = 0;
3142         var->type = ar & 15;
3143         var->s = (ar >> 4) & 1;
3144         var->dpl = (ar >> 5) & 3;
3145         var->present = (ar >> 7) & 1;
3146         var->avl = (ar >> 12) & 1;
3147         var->l = (ar >> 13) & 1;
3148         var->db = (ar >> 14) & 1;
3149         var->g = (ar >> 15) & 1;
3150         var->unusable = (ar >> 16) & 1;
3151 }
3152
3153 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3154 {
3155         struct kvm_segment s;
3156
3157         if (to_vmx(vcpu)->rmode.vm86_active) {
3158                 vmx_get_segment(vcpu, &s, seg);
3159                 return s.base;
3160         }
3161         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3162 }
3163
3164 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
3165 {
3166         if (!is_protmode(vcpu))
3167                 return 0;
3168
3169         if (!is_long_mode(vcpu)
3170             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3171                 return 3;
3172
3173         return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
3174 }
3175
3176 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3177 {
3178         struct vcpu_vmx *vmx = to_vmx(vcpu);
3179
3180         /*
3181          * If we enter real mode with cs.sel & 3 != 0, the normal CPL calculations
3182          * fail; use the cache instead.
3183          */
3184         if (unlikely(vmx->emulation_required && emulate_invalid_guest_state)) {
3185                 return vmx->cpl;
3186         }
3187
3188         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3189                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3190                 vmx->cpl = __vmx_get_cpl(vcpu);
3191         }
3192
3193         return vmx->cpl;
3194 }
3195
3196
3197 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3198 {
3199         u32 ar;
3200
3201         if (var->unusable || !var->present)
3202                 ar = 1 << 16;
3203         else {
3204                 ar = var->type & 15;
3205                 ar |= (var->s & 1) << 4;
3206                 ar |= (var->dpl & 3) << 5;
3207                 ar |= (var->present & 1) << 7;
3208                 ar |= (var->avl & 1) << 12;
3209                 ar |= (var->l & 1) << 13;
3210                 ar |= (var->db & 1) << 14;
3211                 ar |= (var->g & 1) << 15;
3212         }
3213
3214         return ar;
3215 }
3216
3217 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3218                             struct kvm_segment *var, int seg)
3219 {
3220         struct vcpu_vmx *vmx = to_vmx(vcpu);
3221         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3222         u32 ar;
3223
3224         vmx_segment_cache_clear(vmx);
3225
3226         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
3227                 vmcs_write16(sf->selector, var->selector);
3228                 vmx->rmode.tr.selector = var->selector;
3229                 vmx->rmode.tr.base = var->base;
3230                 vmx->rmode.tr.limit = var->limit;
3231                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
3232                 return;
3233         }
3234         vmcs_writel(sf->base, var->base);
3235         vmcs_write32(sf->limit, var->limit);
3236         vmcs_write16(sf->selector, var->selector);
3237         if (vmx->rmode.vm86_active && var->s) {
3238                 /*
3239                  * Hack real-mode segments into vm86 compatibility.
3240                  */
3241                 if (var->base == 0xffff0000 && var->selector == 0xf000)
3242                         vmcs_writel(sf->base, 0xf0000);
3243                 ar = 0xf3;
3244         } else
3245                 ar = vmx_segment_access_rights(var);
3246
3247         /*
3248          *   Fix the "Accessed" bit in AR field of segment registers for older
3249          * qemu binaries.
3250          *   IA32 arch specifies that at the time of processor reset the
3251          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3252          * is setting it to 0 in the usedland code. This causes invalid guest
3253          * state vmexit when "unrestricted guest" mode is turned on.
3254          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3255          * tree. Newer qemu binaries with that qemu fix would not need this
3256          * kvm hack.
3257          */
3258         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3259                 ar |= 0x1; /* Accessed */
3260
3261         vmcs_write32(sf->ar_bytes, ar);
3262         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3263
3264         /*
3265          * Fix segments for real mode guest in hosts that don't have
3266          * "unrestricted_mode" or it was disabled.
3267          * This is done to allow migration of the guests from hosts with
3268          * unrestricted guest like Westmere to older host that don't have
3269          * unrestricted guest like Nehelem.
3270          */
3271         if (!enable_unrestricted_guest && vmx->rmode.vm86_active) {
3272                 switch (seg) {
3273                 case VCPU_SREG_CS:
3274                         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
3275                         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
3276                         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
3277                                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
3278                         vmcs_write16(GUEST_CS_SELECTOR,
3279                                      vmcs_readl(GUEST_CS_BASE) >> 4);
3280                         break;
3281                 case VCPU_SREG_ES:
3282                         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
3283                         break;
3284                 case VCPU_SREG_DS:
3285                         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
3286                         break;
3287                 case VCPU_SREG_GS:
3288                         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
3289                         break;
3290                 case VCPU_SREG_FS:
3291                         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
3292                         break;
3293                 case VCPU_SREG_SS:
3294                         vmcs_write16(GUEST_SS_SELECTOR,
3295                                      vmcs_readl(GUEST_SS_BASE) >> 4);
3296                         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
3297                         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
3298                         break;
3299                 }
3300         }
3301 }
3302
3303 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3304 {
3305         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3306
3307         *db = (ar >> 14) & 1;
3308         *l = (ar >> 13) & 1;
3309 }
3310
3311 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3312 {
3313         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3314         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3315 }
3316
3317 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3318 {
3319         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3320         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3321 }
3322
3323 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3324 {
3325         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3326         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3327 }
3328
3329 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3330 {
3331         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3332         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3333 }
3334
3335 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3336 {
3337         struct kvm_segment var;
3338         u32 ar;
3339
3340         vmx_get_segment(vcpu, &var, seg);
3341         ar = vmx_segment_access_rights(&var);
3342
3343         if (var.base != (var.selector << 4))
3344                 return false;
3345         if (var.limit != 0xffff)
3346                 return false;
3347         if (ar != 0xf3)
3348                 return false;
3349
3350         return true;
3351 }
3352
3353 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3354 {
3355         struct kvm_segment cs;
3356         unsigned int cs_rpl;
3357
3358         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3359         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3360
3361         if (cs.unusable)
3362                 return false;
3363         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3364                 return false;
3365         if (!cs.s)
3366                 return false;
3367         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3368                 if (cs.dpl > cs_rpl)
3369                         return false;
3370         } else {
3371                 if (cs.dpl != cs_rpl)
3372                         return false;
3373         }
3374         if (!cs.present)
3375                 return false;
3376
3377         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3378         return true;
3379 }
3380
3381 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3382 {
3383         struct kvm_segment ss;
3384         unsigned int ss_rpl;
3385
3386         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3387         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3388
3389         if (ss.unusable)
3390                 return true;
3391         if (ss.type != 3 && ss.type != 7)
3392                 return false;
3393         if (!ss.s)
3394                 return false;
3395         if (ss.dpl != ss_rpl) /* DPL != RPL */
3396                 return false;
3397         if (!ss.present)
3398                 return false;
3399
3400         return true;
3401 }
3402
3403 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3404 {
3405         struct kvm_segment var;
3406         unsigned int rpl;
3407
3408         vmx_get_segment(vcpu, &var, seg);
3409         rpl = var.selector & SELECTOR_RPL_MASK;
3410
3411         if (var.unusable)
3412                 return true;
3413         if (!var.s)
3414                 return false;
3415         if (!var.present)
3416                 return false;
3417         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3418                 if (var.dpl < rpl) /* DPL < RPL */
3419                         return false;
3420         }
3421
3422         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3423          * rights flags
3424          */
3425         return true;
3426 }
3427
3428 static bool tr_valid(struct kvm_vcpu *vcpu)
3429 {
3430         struct kvm_segment tr;
3431
3432         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3433
3434         if (tr.unusable)
3435                 return false;
3436         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3437                 return false;
3438         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3439                 return false;
3440         if (!tr.present)
3441                 return false;
3442
3443         return true;
3444 }
3445
3446 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3447 {
3448         struct kvm_segment ldtr;
3449
3450         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3451
3452         if (ldtr.unusable)
3453                 return true;
3454         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3455                 return false;
3456         if (ldtr.type != 2)
3457                 return false;
3458         if (!ldtr.present)
3459                 return false;
3460
3461         return true;
3462 }
3463
3464 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3465 {
3466         struct kvm_segment cs, ss;
3467
3468         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3469         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3470
3471         return ((cs.selector & SELECTOR_RPL_MASK) ==
3472                  (ss.selector & SELECTOR_RPL_MASK));
3473 }
3474
3475 /*
3476  * Check if guest state is valid. Returns true if valid, false if
3477  * not.
3478  * We assume that registers are always usable
3479  */
3480 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3481 {
3482         /* real mode guest state checks */
3483         if (!is_protmode(vcpu)) {
3484                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3485                         return false;
3486                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3487                         return false;
3488                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3489                         return false;
3490                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3491                         return false;
3492                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3493                         return false;
3494                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3495                         return false;
3496         } else {
3497         /* protected mode guest state checks */
3498                 if (!cs_ss_rpl_check(vcpu))
3499                         return false;
3500                 if (!code_segment_valid(vcpu))
3501                         return false;
3502                 if (!stack_segment_valid(vcpu))
3503                         return false;
3504                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3505                         return false;
3506                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3507                         return false;
3508                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3509                         return false;
3510                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3511                         return false;
3512                 if (!tr_valid(vcpu))
3513                         return false;
3514                 if (!ldtr_valid(vcpu))
3515                         return false;
3516         }
3517         /* TODO:
3518          * - Add checks on RIP
3519          * - Add checks on RFLAGS
3520          */
3521
3522         return true;
3523 }
3524
3525 static int init_rmode_tss(struct kvm *kvm)
3526 {
3527         gfn_t fn;
3528         u16 data = 0;
3529         int r, idx, ret = 0;
3530
3531         idx = srcu_read_lock(&kvm->srcu);
3532         fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3533         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3534         if (r < 0)
3535                 goto out;
3536         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3537         r = kvm_write_guest_page(kvm, fn++, &data,
3538                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3539         if (r < 0)
3540                 goto out;
3541         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3542         if (r < 0)
3543                 goto out;
3544         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3545         if (r < 0)
3546                 goto out;
3547         data = ~0;
3548         r = kvm_write_guest_page(kvm, fn, &data,
3549                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3550                                  sizeof(u8));
3551         if (r < 0)
3552                 goto out;
3553
3554         ret = 1;
3555 out:
3556         srcu_read_unlock(&kvm->srcu, idx);
3557         return ret;
3558 }
3559
3560 static int init_rmode_identity_map(struct kvm *kvm)
3561 {
3562         int i, idx, r, ret;
3563         pfn_t identity_map_pfn;
3564         u32 tmp;
3565
3566         if (!enable_ept)
3567                 return 1;
3568         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3569                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3570                         "haven't been allocated!\n");
3571                 return 0;
3572         }
3573         if (likely(kvm->arch.ept_identity_pagetable_done))
3574                 return 1;
3575         ret = 0;
3576         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3577         idx = srcu_read_lock(&kvm->srcu);
3578         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3579         if (r < 0)
3580                 goto out;
3581         /* Set up identity-mapping pagetable for EPT in real mode */
3582         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3583                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3584                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3585                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3586                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3587                 if (r < 0)
3588                         goto out;
3589         }
3590         kvm->arch.ept_identity_pagetable_done = true;
3591         ret = 1;
3592 out:
3593         srcu_read_unlock(&kvm->srcu, idx);
3594         return ret;
3595 }
3596
3597 static void seg_setup(int seg)
3598 {
3599         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3600         unsigned int ar;
3601
3602         vmcs_write16(sf->selector, 0);
3603         vmcs_writel(sf->base, 0);
3604         vmcs_write32(sf->limit, 0xffff);
3605         if (enable_unrestricted_guest) {
3606                 ar = 0x93;
3607                 if (seg == VCPU_SREG_CS)
3608                         ar |= 0x08; /* code segment */
3609         } else
3610                 ar = 0xf3;
3611
3612         vmcs_write32(sf->ar_bytes, ar);
3613 }
3614
3615 static int alloc_apic_access_page(struct kvm *kvm)
3616 {
3617         struct kvm_userspace_memory_region kvm_userspace_mem;
3618         int r = 0;
3619
3620         mutex_lock(&kvm->slots_lock);
3621         if (kvm->arch.apic_access_page)
3622                 goto out;
3623         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3624         kvm_userspace_mem.flags = 0;
3625         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3626         kvm_userspace_mem.memory_size = PAGE_SIZE;
3627         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3628         if (r)
3629                 goto out;
3630
3631         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
3632 out:
3633         mutex_unlock(&kvm->slots_lock);
3634         return r;
3635 }
3636
3637 static int alloc_identity_pagetable(struct kvm *kvm)
3638 {
3639         struct kvm_userspace_memory_region kvm_userspace_mem;
3640         int r = 0;
3641
3642         mutex_lock(&kvm->slots_lock);
3643         if (kvm->arch.ept_identity_pagetable)
3644                 goto out;
3645         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3646         kvm_userspace_mem.flags = 0;
3647         kvm_userspace_mem.guest_phys_addr =
3648                 kvm->arch.ept_identity_map_addr;
3649         kvm_userspace_mem.memory_size = PAGE_SIZE;
3650         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3651         if (r)
3652                 goto out;
3653
3654         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
3655                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3656 out:
3657         mutex_unlock(&kvm->slots_lock);
3658         return r;
3659 }
3660
3661 static void allocate_vpid(struct vcpu_vmx *vmx)
3662 {
3663         int vpid;
3664
3665         vmx->vpid = 0;
3666         if (!enable_vpid)
3667                 return;
3668         spin_lock(&vmx_vpid_lock);
3669         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3670         if (vpid < VMX_NR_VPIDS) {
3671                 vmx->vpid = vpid;
3672                 __set_bit(vpid, vmx_vpid_bitmap);
3673         }
3674         spin_unlock(&vmx_vpid_lock);
3675 }
3676
3677 static void free_vpid(struct vcpu_vmx *vmx)
3678 {
3679         if (!enable_vpid)
3680                 return;
3681         spin_lock(&vmx_vpid_lock);
3682         if (vmx->vpid != 0)
3683                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3684         spin_unlock(&vmx_vpid_lock);
3685 }
3686
3687 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
3688 {
3689         int f = sizeof(unsigned long);
3690
3691         if (!cpu_has_vmx_msr_bitmap())
3692                 return;
3693
3694         /*
3695          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3696          * have the write-low and read-high bitmap offsets the wrong way round.
3697          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3698          */
3699         if (msr <= 0x1fff) {
3700                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3701                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
3702         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3703                 msr &= 0x1fff;
3704                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3705                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
3706         }
3707 }
3708
3709 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3710 {
3711         if (!longmode_only)
3712                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3713         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3714 }
3715
3716 /*
3717  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3718  * will not change in the lifetime of the guest.
3719  * Note that host-state that does change is set elsewhere. E.g., host-state
3720  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3721  */
3722 static void vmx_set_constant_host_state(void)
3723 {
3724         u32 low32, high32;
3725         unsigned long tmpl;
3726         struct desc_ptr dt;
3727
3728         vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS);  /* 22.2.3 */
3729         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
3730         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
3731
3732         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
3733 #ifdef CONFIG_X86_64
3734         /*
3735          * Load null selectors, so we can avoid reloading them in
3736          * __vmx_load_host_state(), in case userspace uses the null selectors
3737          * too (the expected case).
3738          */
3739         vmcs_write16(HOST_DS_SELECTOR, 0);
3740         vmcs_write16(HOST_ES_SELECTOR, 0);
3741 #else
3742         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3743         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3744 #endif
3745         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3746         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
3747
3748         native_store_idt(&dt);
3749         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
3750
3751         asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3752         vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3753
3754         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3755         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3756         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3757         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
3758
3759         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3760                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3761                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3762         }
3763 }
3764
3765 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3766 {
3767         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3768         if (enable_ept)
3769                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3770         if (is_guest_mode(&vmx->vcpu))
3771                 vmx->vcpu.arch.cr4_guest_owned_bits &=
3772                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3773         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3774 }
3775
3776 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3777 {
3778         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3779         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3780                 exec_control &= ~CPU_BASED_TPR_SHADOW;
3781 #ifdef CONFIG_X86_64
3782                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3783                                 CPU_BASED_CR8_LOAD_EXITING;
3784 #endif
3785         }
3786         if (!enable_ept)
3787                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3788                                 CPU_BASED_CR3_LOAD_EXITING  |
3789                                 CPU_BASED_INVLPG_EXITING;
3790         return exec_control;
3791 }
3792
3793 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3794 {
3795         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3796         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3797                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3798         if (vmx->vpid == 0)
3799                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3800         if (!enable_ept) {
3801                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3802                 enable_unrestricted_guest = 0;
3803         }
3804         if (!enable_unrestricted_guest)
3805                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3806         if (!ple_gap)
3807                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3808         return exec_control;
3809 }
3810
3811 static void ept_set_mmio_spte_mask(void)
3812 {
3813         /*
3814          * EPT Misconfigurations can be generated if the value of bits 2:0
3815          * of an EPT paging-structure entry is 110b (write/execute).
3816          * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3817          * spte.
3818          */
3819         kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3820 }
3821
3822 /*
3823  * Sets up the vmcs for emulated real mode.
3824  */
3825 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
3826 {
3827 #ifdef CONFIG_X86_64
3828         unsigned long a;
3829 #endif
3830         int i;
3831
3832         /* I/O */
3833         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3834         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
3835
3836         if (cpu_has_vmx_msr_bitmap())
3837                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
3838
3839         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3840
3841         /* Control */
3842         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3843                 vmcs_config.pin_based_exec_ctrl);
3844
3845         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
3846
3847         if (cpu_has_secondary_exec_ctrls()) {
3848                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3849                                 vmx_secondary_exec_control(vmx));
3850         }
3851
3852         if (ple_gap) {
3853                 vmcs_write32(PLE_GAP, ple_gap);
3854                 vmcs_write32(PLE_WINDOW, ple_window);
3855         }
3856
3857         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3858         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
3859         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
3860
3861         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
3862         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
3863         vmx_set_constant_host_state();
3864 #ifdef CONFIG_X86_64
3865         rdmsrl(MSR_FS_BASE, a);
3866         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3867         rdmsrl(MSR_GS_BASE, a);
3868         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3869 #else
3870         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3871         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3872 #endif
3873
3874         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3875         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
3876         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
3877         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
3878         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
3879
3880         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3881                 u32 msr_low, msr_high;
3882                 u64 host_pat;
3883                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3884                 host_pat = msr_low | ((u64) msr_high << 32);
3885                 /* Write the default value follow host pat */
3886                 vmcs_write64(GUEST_IA32_PAT, host_pat);
3887                 /* Keep arch.pat sync with GUEST_IA32_PAT */
3888                 vmx->vcpu.arch.pat = host_pat;
3889         }
3890
3891         for (i = 0; i < NR_VMX_MSR; ++i) {
3892                 u32 index = vmx_msr_index[i];
3893                 u32 data_low, data_high;
3894                 int j = vmx->nmsrs;
3895
3896                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3897                         continue;
3898                 if (wrmsr_safe(index, data_low, data_high) < 0)
3899                         continue;
3900                 vmx->guest_msrs[j].index = i;
3901                 vmx->guest_msrs[j].data = 0;
3902                 vmx->guest_msrs[j].mask = -1ull;
3903                 ++vmx->nmsrs;
3904         }
3905
3906         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
3907
3908         /* 22.2.1, 20.8.1 */
3909         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3910
3911         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
3912         set_cr4_guest_host_mask(vmx);
3913
3914         kvm_write_tsc(&vmx->vcpu, 0);
3915
3916         return 0;
3917 }
3918
3919 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3920 {
3921         struct vcpu_vmx *vmx = to_vmx(vcpu);
3922         u64 msr;
3923         int ret;
3924
3925         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3926
3927         vmx->rmode.vm86_active = 0;
3928
3929         vmx->soft_vnmi_blocked = 0;
3930
3931         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
3932         kvm_set_cr8(&vmx->vcpu, 0);
3933         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
3934         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3935                 msr |= MSR_IA32_APICBASE_BSP;
3936         kvm_set_apic_base(&vmx->vcpu, msr);
3937
3938         ret = fx_init(&vmx->vcpu);
3939         if (ret != 0)
3940                 goto out;
3941
3942         vmx_segment_cache_clear(vmx);
3943
3944         seg_setup(VCPU_SREG_CS);
3945         /*
3946          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3947          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
3948          */
3949         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
3950                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3951                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3952         } else {
3953                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3954                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
3955         }
3956
3957         seg_setup(VCPU_SREG_DS);
3958         seg_setup(VCPU_SREG_ES);
3959         seg_setup(VCPU_SREG_FS);
3960         seg_setup(VCPU_SREG_GS);
3961         seg_setup(VCPU_SREG_SS);
3962
3963         vmcs_write16(GUEST_TR_SELECTOR, 0);
3964         vmcs_writel(GUEST_TR_BASE, 0);
3965         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3966         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3967
3968         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3969         vmcs_writel(GUEST_LDTR_BASE, 0);
3970         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3971         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3972
3973         vmcs_write32(GUEST_SYSENTER_CS, 0);
3974         vmcs_writel(GUEST_SYSENTER_ESP, 0);
3975         vmcs_writel(GUEST_SYSENTER_EIP, 0);
3976
3977         vmcs_writel(GUEST_RFLAGS, 0x02);
3978         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3979                 kvm_rip_write(vcpu, 0xfff0);
3980         else
3981                 kvm_rip_write(vcpu, 0);
3982         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
3983
3984         vmcs_writel(GUEST_DR7, 0x400);
3985
3986         vmcs_writel(GUEST_GDTR_BASE, 0);
3987         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3988
3989         vmcs_writel(GUEST_IDTR_BASE, 0);
3990         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3991
3992         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3993         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3994         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3995
3996         /* Special registers */
3997         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3998
3999         setup_msrs(vmx);
4000
4001         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4002
4003         if (cpu_has_vmx_tpr_shadow()) {
4004                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4005                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4006                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4007                                      __pa(vmx->vcpu.arch.apic->regs));
4008                 vmcs_write32(TPR_THRESHOLD, 0);
4009         }
4010
4011         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4012                 vmcs_write64(APIC_ACCESS_ADDR,
4013                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
4014
4015         if (vmx->vpid != 0)
4016                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4017
4018         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4019         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
4020         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4021         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
4022         vmx_set_cr4(&vmx->vcpu, 0);
4023         vmx_set_efer(&vmx->vcpu, 0);
4024         vmx_fpu_activate(&vmx->vcpu);
4025         update_exception_bitmap(&vmx->vcpu);
4026
4027         vpid_sync_context(vmx);
4028
4029         ret = 0;
4030
4031         /* HACK: Don't enable emulation on guest boot/reset */
4032         vmx->emulation_required = 0;
4033
4034 out:
4035         return ret;
4036 }
4037
4038 /*
4039  * In nested virtualization, check if L1 asked to exit on external interrupts.
4040  * For most existing hypervisors, this will always return true.
4041  */
4042 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4043 {
4044         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4045                 PIN_BASED_EXT_INTR_MASK;
4046 }
4047
4048 static void enable_irq_window(struct kvm_vcpu *vcpu)
4049 {
4050         u32 cpu_based_vm_exec_control;
4051         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4052                 /*
4053                  * We get here if vmx_interrupt_allowed() said we can't
4054                  * inject to L1 now because L2 must run. Ask L2 to exit
4055                  * right after entry, so we can inject to L1 more promptly.
4056                  */
4057                 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
4058                 return;
4059         }
4060
4061         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4062         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4063         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4064 }
4065
4066 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4067 {
4068         u32 cpu_based_vm_exec_control;
4069
4070         if (!cpu_has_virtual_nmis()) {
4071                 enable_irq_window(vcpu);
4072                 return;
4073         }
4074
4075         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4076                 enable_irq_window(vcpu);
4077                 return;
4078         }
4079         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4080         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4081         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4082 }
4083
4084 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4085 {
4086         struct vcpu_vmx *vmx = to_vmx(vcpu);
4087         uint32_t intr;
4088         int irq = vcpu->arch.interrupt.nr;
4089
4090         trace_kvm_inj_virq(irq);
4091
4092         ++vcpu->stat.irq_injections;
4093         if (vmx->rmode.vm86_active) {
4094                 int inc_eip = 0;
4095                 if (vcpu->arch.interrupt.soft)
4096                         inc_eip = vcpu->arch.event_exit_inst_len;
4097                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4098                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4099                 return;
4100         }
4101         intr = irq | INTR_INFO_VALID_MASK;
4102         if (vcpu->arch.interrupt.soft) {
4103                 intr |= INTR_TYPE_SOFT_INTR;
4104                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4105                              vmx->vcpu.arch.event_exit_inst_len);
4106         } else
4107                 intr |= INTR_TYPE_EXT_INTR;
4108         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4109 }
4110
4111 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4112 {
4113         struct vcpu_vmx *vmx = to_vmx(vcpu);
4114
4115         if (is_guest_mode(vcpu))
4116                 return;
4117
4118         if (!cpu_has_virtual_nmis()) {
4119                 /*
4120                  * Tracking the NMI-blocked state in software is built upon
4121                  * finding the next open IRQ window. This, in turn, depends on
4122                  * well-behaving guests: They have to keep IRQs disabled at
4123                  * least as long as the NMI handler runs. Otherwise we may
4124                  * cause NMI nesting, maybe breaking the guest. But as this is
4125                  * highly unlikely, we can live with the residual risk.
4126                  */
4127                 vmx->soft_vnmi_blocked = 1;
4128                 vmx->vnmi_blocked_time = 0;
4129         }
4130
4131         ++vcpu->stat.nmi_injections;
4132         vmx->nmi_known_unmasked = false;
4133         if (vmx->rmode.vm86_active) {
4134                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4135                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4136                 return;
4137         }
4138         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4139                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4140 }
4141
4142 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4143 {
4144         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4145                 return 0;
4146
4147         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4148                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4149                    | GUEST_INTR_STATE_NMI));
4150 }
4151
4152 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4153 {
4154         if (!cpu_has_virtual_nmis())
4155                 return to_vmx(vcpu)->soft_vnmi_blocked;
4156         if (to_vmx(vcpu)->nmi_known_unmasked)
4157                 return false;
4158         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4159 }
4160
4161 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4162 {
4163         struct vcpu_vmx *vmx = to_vmx(vcpu);
4164
4165         if (!cpu_has_virtual_nmis()) {
4166                 if (vmx->soft_vnmi_blocked != masked) {
4167                         vmx->soft_vnmi_blocked = masked;
4168                         vmx->vnmi_blocked_time = 0;
4169                 }
4170         } else {
4171                 vmx->nmi_known_unmasked = !masked;
4172                 if (masked)
4173                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4174                                       GUEST_INTR_STATE_NMI);
4175                 else
4176                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4177                                         GUEST_INTR_STATE_NMI);
4178         }
4179 }
4180
4181 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4182 {
4183         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4184                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4185                 if (to_vmx(vcpu)->nested.nested_run_pending ||
4186                     (vmcs12->idt_vectoring_info_field &
4187                      VECTORING_INFO_VALID_MASK))
4188                         return 0;
4189                 nested_vmx_vmexit(vcpu);
4190                 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4191                 vmcs12->vm_exit_intr_info = 0;
4192                 /* fall through to normal code, but now in L1, not L2 */
4193         }
4194
4195         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4196                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4197                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4198 }
4199
4200 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4201 {
4202         int ret;
4203         struct kvm_userspace_memory_region tss_mem = {
4204                 .slot = TSS_PRIVATE_MEMSLOT,
4205                 .guest_phys_addr = addr,
4206                 .memory_size = PAGE_SIZE * 3,
4207                 .flags = 0,
4208         };
4209
4210         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
4211         if (ret)
4212                 return ret;
4213         kvm->arch.tss_addr = addr;
4214         if (!init_rmode_tss(kvm))
4215                 return  -ENOMEM;
4216
4217         return 0;
4218 }
4219
4220 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4221                                   int vec, u32 err_code)
4222 {
4223         /*
4224          * Instruction with address size override prefix opcode 0x67
4225          * Cause the #SS fault with 0 error code in VM86 mode.
4226          */
4227         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
4228                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
4229                         return 1;
4230         /*
4231          * Forward all other exceptions that are valid in real mode.
4232          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4233          *        the required debugging infrastructure rework.
4234          */
4235         switch (vec) {
4236         case DB_VECTOR:
4237                 if (vcpu->guest_debug &
4238                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4239                         return 0;
4240                 kvm_queue_exception(vcpu, vec);
4241                 return 1;
4242         case BP_VECTOR:
4243                 /*
4244                  * Update instruction length as we may reinject the exception
4245                  * from user space while in guest debugging mode.
4246                  */
4247                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4248                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4249                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4250                         return 0;
4251                 /* fall through */
4252         case DE_VECTOR:
4253         case OF_VECTOR:
4254         case BR_VECTOR:
4255         case UD_VECTOR:
4256         case DF_VECTOR:
4257         case SS_VECTOR:
4258         case GP_VECTOR:
4259         case MF_VECTOR:
4260                 kvm_queue_exception(vcpu, vec);
4261                 return 1;
4262         }
4263         return 0;
4264 }
4265
4266 /*
4267  * Trigger machine check on the host. We assume all the MSRs are already set up
4268  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4269  * We pass a fake environment to the machine check handler because we want
4270  * the guest to be always treated like user space, no matter what context
4271  * it used internally.
4272  */
4273 static void kvm_machine_check(void)
4274 {
4275 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4276         struct pt_regs regs = {
4277                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4278                 .flags = X86_EFLAGS_IF,
4279         };
4280
4281         do_machine_check(&regs, 0);
4282 #endif
4283 }
4284
4285 static int handle_machine_check(struct kvm_vcpu *vcpu)
4286 {
4287         /* already handled by vcpu_run */
4288         return 1;
4289 }
4290
4291 static int handle_exception(struct kvm_vcpu *vcpu)
4292 {
4293         struct vcpu_vmx *vmx = to_vmx(vcpu);
4294         struct kvm_run *kvm_run = vcpu->run;
4295         u32 intr_info, ex_no, error_code;
4296         unsigned long cr2, rip, dr6;
4297         u32 vect_info;
4298         enum emulation_result er;
4299
4300         vect_info = vmx->idt_vectoring_info;
4301         intr_info = vmx->exit_intr_info;
4302
4303         if (is_machine_check(intr_info))
4304                 return handle_machine_check(vcpu);
4305
4306         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4307             !is_page_fault(intr_info)) {
4308                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4309                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4310                 vcpu->run->internal.ndata = 2;
4311                 vcpu->run->internal.data[0] = vect_info;
4312                 vcpu->run->internal.data[1] = intr_info;
4313                 return 0;
4314         }
4315
4316         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4317                 return 1;  /* already handled by vmx_vcpu_run() */
4318
4319         if (is_no_device(intr_info)) {
4320                 vmx_fpu_activate(vcpu);
4321                 return 1;
4322         }
4323
4324         if (is_invalid_opcode(intr_info)) {
4325                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4326                 if (er != EMULATE_DONE)
4327                         kvm_queue_exception(vcpu, UD_VECTOR);
4328                 return 1;
4329         }
4330
4331         error_code = 0;
4332         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4333                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4334         if (is_page_fault(intr_info)) {
4335                 /* EPT won't cause page fault directly */
4336                 BUG_ON(enable_ept);
4337                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4338                 trace_kvm_page_fault(cr2, error_code);
4339
4340                 if (kvm_event_needs_reinjection(vcpu))
4341                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4342                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4343         }
4344
4345         if (vmx->rmode.vm86_active &&
4346             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
4347                                                                 error_code)) {
4348                 if (vcpu->arch.halt_request) {
4349                         vcpu->arch.halt_request = 0;
4350                         return kvm_emulate_halt(vcpu);
4351                 }
4352                 return 1;
4353         }
4354
4355         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4356         switch (ex_no) {
4357         case DB_VECTOR:
4358                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4359                 if (!(vcpu->guest_debug &
4360                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4361                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4362                         kvm_queue_exception(vcpu, DB_VECTOR);
4363                         return 1;
4364                 }
4365                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4366                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4367                 /* fall through */
4368         case BP_VECTOR:
4369                 /*
4370                  * Update instruction length as we may reinject #BP from
4371                  * user space while in guest debugging mode. Reading it for
4372                  * #DB as well causes no harm, it is not used in that case.
4373                  */
4374                 vmx->vcpu.arch.event_exit_inst_len =
4375                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4376                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4377                 rip = kvm_rip_read(vcpu);
4378                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4379                 kvm_run->debug.arch.exception = ex_no;
4380                 break;
4381         default:
4382                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4383                 kvm_run->ex.exception = ex_no;
4384                 kvm_run->ex.error_code = error_code;
4385                 break;
4386         }
4387         return 0;
4388 }
4389
4390 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4391 {
4392         ++vcpu->stat.irq_exits;
4393         return 1;
4394 }
4395
4396 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4397 {
4398         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4399         return 0;
4400 }
4401
4402 static int handle_io(struct kvm_vcpu *vcpu)
4403 {
4404         unsigned long exit_qualification;
4405         int size, in, string;
4406         unsigned port;
4407
4408         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4409         string = (exit_qualification & 16) != 0;
4410         in = (exit_qualification & 8) != 0;
4411
4412         ++vcpu->stat.io_exits;
4413
4414         if (string || in)
4415                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4416
4417         port = exit_qualification >> 16;
4418         size = (exit_qualification & 7) + 1;
4419         skip_emulated_instruction(vcpu);
4420
4421         return kvm_fast_pio_out(vcpu, size, port);
4422 }
4423
4424 static void
4425 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4426 {
4427         /*
4428          * Patch in the VMCALL instruction:
4429          */
4430         hypercall[0] = 0x0f;
4431         hypercall[1] = 0x01;
4432         hypercall[2] = 0xc1;
4433 }
4434
4435 /* called to set cr0 as approriate for a mov-to-cr0 exit. */
4436 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4437 {
4438         if (to_vmx(vcpu)->nested.vmxon &&
4439             ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4440                 return 1;
4441
4442         if (is_guest_mode(vcpu)) {
4443                 /*
4444                  * We get here when L2 changed cr0 in a way that did not change
4445                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4446                  * but did change L0 shadowed bits. This can currently happen
4447                  * with the TS bit: L0 may want to leave TS on (for lazy fpu
4448                  * loading) while pretending to allow the guest to change it.
4449                  */
4450                 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4451                          (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4452                         return 1;
4453                 vmcs_writel(CR0_READ_SHADOW, val);
4454                 return 0;
4455         } else
4456                 return kvm_set_cr0(vcpu, val);
4457 }
4458
4459 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4460 {
4461         if (is_guest_mode(vcpu)) {
4462                 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4463                          (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4464                         return 1;
4465                 vmcs_writel(CR4_READ_SHADOW, val);
4466                 return 0;
4467         } else
4468                 return kvm_set_cr4(vcpu, val);
4469 }
4470
4471 /* called to set cr0 as approriate for clts instruction exit. */
4472 static void handle_clts(struct kvm_vcpu *vcpu)
4473 {
4474         if (is_guest_mode(vcpu)) {
4475                 /*
4476                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4477                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4478                  * just pretend it's off (also in arch.cr0 for fpu_activate).
4479                  */
4480                 vmcs_writel(CR0_READ_SHADOW,
4481                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4482                 vcpu->arch.cr0 &= ~X86_CR0_TS;
4483         } else
4484                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4485 }
4486
4487 static int handle_cr(struct kvm_vcpu *vcpu)
4488 {
4489         unsigned long exit_qualification, val;
4490         int cr;
4491         int reg;
4492         int err;
4493
4494         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4495         cr = exit_qualification & 15;
4496         reg = (exit_qualification >> 8) & 15;
4497         switch ((exit_qualification >> 4) & 3) {
4498         case 0: /* mov to cr */
4499                 val = kvm_register_read(vcpu, reg);
4500                 trace_kvm_cr_write(cr, val);
4501                 switch (cr) {
4502                 case 0:
4503                         err = handle_set_cr0(vcpu, val);
4504                         kvm_complete_insn_gp(vcpu, err);
4505                         return 1;
4506                 case 3:
4507                         err = kvm_set_cr3(vcpu, val);
4508                         kvm_complete_insn_gp(vcpu, err);
4509                         return 1;
4510                 case 4:
4511                         err = handle_set_cr4(vcpu, val);
4512                         kvm_complete_insn_gp(vcpu, err);
4513                         return 1;
4514                 case 8: {
4515                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4516                                 u8 cr8 = kvm_register_read(vcpu, reg);
4517                                 err = kvm_set_cr8(vcpu, cr8);
4518                                 kvm_complete_insn_gp(vcpu, err);
4519                                 if (irqchip_in_kernel(vcpu->kvm))
4520                                         return 1;
4521                                 if (cr8_prev <= cr8)
4522                                         return 1;
4523                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4524                                 return 0;
4525                         }
4526                 };
4527                 break;
4528         case 2: /* clts */
4529                 handle_clts(vcpu);
4530                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4531                 skip_emulated_instruction(vcpu);
4532                 vmx_fpu_activate(vcpu);
4533                 return 1;
4534         case 1: /*mov from cr*/
4535                 switch (cr) {
4536                 case 3:
4537                         val = kvm_read_cr3(vcpu);
4538                         kvm_register_write(vcpu, reg, val);
4539                         trace_kvm_cr_read(cr, val);
4540                         skip_emulated_instruction(vcpu);
4541                         return 1;
4542                 case 8:
4543                         val = kvm_get_cr8(vcpu);
4544                         kvm_register_write(vcpu, reg, val);
4545                         trace_kvm_cr_read(cr, val);
4546                         skip_emulated_instruction(vcpu);
4547                         return 1;
4548                 }
4549                 break;
4550         case 3: /* lmsw */
4551                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4552                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4553                 kvm_lmsw(vcpu, val);
4554
4555                 skip_emulated_instruction(vcpu);
4556                 return 1;
4557         default:
4558                 break;
4559         }
4560         vcpu->run->exit_reason = 0;
4561         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4562                (int)(exit_qualification >> 4) & 3, cr);
4563         return 0;
4564 }
4565
4566 static int handle_dr(struct kvm_vcpu *vcpu)
4567 {
4568         unsigned long exit_qualification;
4569         int dr, reg;
4570
4571         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4572         if (!kvm_require_cpl(vcpu, 0))
4573                 return 1;
4574         dr = vmcs_readl(GUEST_DR7);
4575         if (dr & DR7_GD) {
4576                 /*
4577                  * As the vm-exit takes precedence over the debug trap, we
4578                  * need to emulate the latter, either for the host or the
4579                  * guest debugging itself.
4580                  */
4581                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4582                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4583                         vcpu->run->debug.arch.dr7 = dr;
4584                         vcpu->run->debug.arch.pc =
4585                                 vmcs_readl(GUEST_CS_BASE) +
4586                                 vmcs_readl(GUEST_RIP);
4587                         vcpu->run->debug.arch.exception = DB_VECTOR;
4588                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4589                         return 0;
4590                 } else {
4591                         vcpu->arch.dr7 &= ~DR7_GD;
4592                         vcpu->arch.dr6 |= DR6_BD;
4593                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4594                         kvm_queue_exception(vcpu, DB_VECTOR);
4595                         return 1;
4596                 }
4597         }
4598
4599         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4600         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4601         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4602         if (exit_qualification & TYPE_MOV_FROM_DR) {
4603                 unsigned long val;
4604                 if (!kvm_get_dr(vcpu, dr, &val))
4605                         kvm_register_write(vcpu, reg, val);
4606         } else
4607                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
4608         skip_emulated_instruction(vcpu);
4609         return 1;
4610 }
4611
4612 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4613 {
4614         vmcs_writel(GUEST_DR7, val);
4615 }
4616
4617 static int handle_cpuid(struct kvm_vcpu *vcpu)
4618 {
4619         kvm_emulate_cpuid(vcpu);
4620         return 1;
4621 }
4622
4623 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4624 {
4625         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4626         u64 data;
4627
4628         if (vmx_get_msr(vcpu, ecx, &data)) {
4629                 trace_kvm_msr_read_ex(ecx);
4630                 kvm_inject_gp(vcpu, 0);
4631                 return 1;
4632         }
4633
4634         trace_kvm_msr_read(ecx, data);
4635
4636         /* FIXME: handling of bits 32:63 of rax, rdx */
4637         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4638         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
4639         skip_emulated_instruction(vcpu);
4640         return 1;
4641 }
4642
4643 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4644 {
4645         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4646         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4647                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4648
4649         if (vmx_set_msr(vcpu, ecx, data) != 0) {
4650                 trace_kvm_msr_write_ex(ecx, data);
4651                 kvm_inject_gp(vcpu, 0);
4652                 return 1;
4653         }
4654
4655         trace_kvm_msr_write(ecx, data);
4656         skip_emulated_instruction(vcpu);
4657         return 1;
4658 }
4659
4660 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4661 {
4662         kvm_make_request(KVM_REQ_EVENT, vcpu);
4663         return 1;
4664 }
4665
4666 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4667 {
4668         u32 cpu_based_vm_exec_control;
4669
4670         /* clear pending irq */
4671         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4672         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4673         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4674
4675         kvm_make_request(KVM_REQ_EVENT, vcpu);
4676
4677         ++vcpu->stat.irq_window_exits;
4678
4679         /*
4680          * If the user space waits to inject interrupts, exit as soon as
4681          * possible
4682          */
4683         if (!irqchip_in_kernel(vcpu->kvm) &&
4684             vcpu->run->request_interrupt_window &&
4685             !kvm_cpu_has_interrupt(vcpu)) {
4686                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
4687                 return 0;
4688         }
4689         return 1;
4690 }
4691
4692 static int handle_halt(struct kvm_vcpu *vcpu)
4693 {
4694         skip_emulated_instruction(vcpu);
4695         return kvm_emulate_halt(vcpu);
4696 }
4697
4698 static int handle_vmcall(struct kvm_vcpu *vcpu)
4699 {
4700         skip_emulated_instruction(vcpu);
4701         kvm_emulate_hypercall(vcpu);
4702         return 1;
4703 }
4704
4705 static int handle_invd(struct kvm_vcpu *vcpu)
4706 {
4707         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4708 }
4709
4710 static int handle_invlpg(struct kvm_vcpu *vcpu)
4711 {
4712         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4713
4714         kvm_mmu_invlpg(vcpu, exit_qualification);
4715         skip_emulated_instruction(vcpu);
4716         return 1;
4717 }
4718
4719 static int handle_rdpmc(struct kvm_vcpu *vcpu)
4720 {
4721         int err;
4722
4723         err = kvm_rdpmc(vcpu);
4724         kvm_complete_insn_gp(vcpu, err);
4725
4726         return 1;
4727 }
4728
4729 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4730 {
4731         skip_emulated_instruction(vcpu);
4732         kvm_emulate_wbinvd(vcpu);
4733         return 1;
4734 }
4735
4736 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4737 {
4738         u64 new_bv = kvm_read_edx_eax(vcpu);
4739         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4740
4741         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4742                 skip_emulated_instruction(vcpu);
4743         return 1;
4744 }
4745
4746 static int handle_apic_access(struct kvm_vcpu *vcpu)
4747 {
4748         if (likely(fasteoi)) {
4749                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4750                 int access_type, offset;
4751
4752                 access_type = exit_qualification & APIC_ACCESS_TYPE;
4753                 offset = exit_qualification & APIC_ACCESS_OFFSET;
4754                 /*
4755                  * Sane guest uses MOV to write EOI, with written value
4756                  * not cared. So make a short-circuit here by avoiding
4757                  * heavy instruction emulation.
4758                  */
4759                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4760                     (offset == APIC_EOI)) {
4761                         kvm_lapic_set_eoi(vcpu);
4762                         skip_emulated_instruction(vcpu);
4763                         return 1;
4764                 }
4765         }
4766         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4767 }
4768
4769 static int handle_task_switch(struct kvm_vcpu *vcpu)
4770 {
4771         struct vcpu_vmx *vmx = to_vmx(vcpu);
4772         unsigned long exit_qualification;
4773         bool has_error_code = false;
4774         u32 error_code = 0;
4775         u16 tss_selector;
4776         int reason, type, idt_v, idt_index;
4777
4778         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4779         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
4780         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
4781
4782         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4783
4784         reason = (u32)exit_qualification >> 30;
4785         if (reason == TASK_SWITCH_GATE && idt_v) {
4786                 switch (type) {
4787                 case INTR_TYPE_NMI_INTR:
4788                         vcpu->arch.nmi_injected = false;
4789                         vmx_set_nmi_mask(vcpu, true);
4790                         break;
4791                 case INTR_TYPE_EXT_INTR:
4792                 case INTR_TYPE_SOFT_INTR:
4793                         kvm_clear_interrupt_queue(vcpu);
4794                         break;
4795                 case INTR_TYPE_HARD_EXCEPTION:
4796                         if (vmx->idt_vectoring_info &
4797                             VECTORING_INFO_DELIVER_CODE_MASK) {
4798                                 has_error_code = true;
4799                                 error_code =
4800                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
4801                         }
4802                         /* fall through */
4803                 case INTR_TYPE_SOFT_EXCEPTION:
4804                         kvm_clear_exception_queue(vcpu);
4805                         break;
4806                 default:
4807                         break;
4808                 }
4809         }
4810         tss_selector = exit_qualification;
4811
4812         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4813                        type != INTR_TYPE_EXT_INTR &&
4814                        type != INTR_TYPE_NMI_INTR))
4815                 skip_emulated_instruction(vcpu);
4816
4817         if (kvm_task_switch(vcpu, tss_selector,
4818                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
4819                             has_error_code, error_code) == EMULATE_FAIL) {
4820                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4821                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4822                 vcpu->run->internal.ndata = 0;
4823                 return 0;
4824         }
4825
4826         /* clear all local breakpoint enable flags */
4827         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4828
4829         /*
4830          * TODO: What about debug traps on tss switch?
4831          *       Are we supposed to inject them and update dr6?
4832          */
4833
4834         return 1;
4835 }
4836
4837 static int handle_ept_violation(struct kvm_vcpu *vcpu)
4838 {
4839         unsigned long exit_qualification;
4840         gpa_t gpa;
4841         int gla_validity;
4842
4843         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4844
4845         if (exit_qualification & (1 << 6)) {
4846                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
4847                 return -EINVAL;
4848         }
4849
4850         gla_validity = (exit_qualification >> 7) & 0x3;
4851         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4852                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4853                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4854                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
4855                         vmcs_readl(GUEST_LINEAR_ADDRESS));
4856                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4857                         (long unsigned int)exit_qualification);
4858                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4859                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
4860                 return 0;
4861         }
4862
4863         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4864         trace_kvm_page_fault(gpa, exit_qualification);
4865         return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
4866 }
4867
4868 static u64 ept_rsvd_mask(u64 spte, int level)
4869 {
4870         int i;
4871         u64 mask = 0;
4872
4873         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4874                 mask |= (1ULL << i);
4875
4876         if (level > 2)
4877                 /* bits 7:3 reserved */
4878                 mask |= 0xf8;
4879         else if (level == 2) {
4880                 if (spte & (1ULL << 7))
4881                         /* 2MB ref, bits 20:12 reserved */
4882                         mask |= 0x1ff000;
4883                 else
4884                         /* bits 6:3 reserved */
4885                         mask |= 0x78;
4886         }
4887
4888         return mask;
4889 }
4890
4891 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4892                                        int level)
4893 {
4894         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4895
4896         /* 010b (write-only) */
4897         WARN_ON((spte & 0x7) == 0x2);
4898
4899         /* 110b (write/execute) */
4900         WARN_ON((spte & 0x7) == 0x6);
4901
4902         /* 100b (execute-only) and value not supported by logical processor */
4903         if (!cpu_has_vmx_ept_execute_only())
4904                 WARN_ON((spte & 0x7) == 0x4);
4905
4906         /* not 000b */
4907         if ((spte & 0x7)) {
4908                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4909
4910                 if (rsvd_bits != 0) {
4911                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4912                                          __func__, rsvd_bits);
4913                         WARN_ON(1);
4914                 }
4915
4916                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4917                         u64 ept_mem_type = (spte & 0x38) >> 3;
4918
4919                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
4920                             ept_mem_type == 7) {
4921                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4922                                                 __func__, ept_mem_type);
4923                                 WARN_ON(1);
4924                         }
4925                 }
4926         }
4927 }
4928
4929 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
4930 {
4931         u64 sptes[4];
4932         int nr_sptes, i, ret;
4933         gpa_t gpa;
4934
4935         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4936
4937         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4938         if (likely(ret == 1))
4939                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4940                                               EMULATE_DONE;
4941         if (unlikely(!ret))
4942                 return 1;
4943
4944         /* It is the real ept misconfig */
4945         printk(KERN_ERR "EPT: Misconfiguration.\n");
4946         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4947
4948         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4949
4950         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4951                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4952
4953         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4954         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
4955
4956         return 0;
4957 }
4958
4959 static int handle_nmi_window(struct kvm_vcpu *vcpu)
4960 {
4961         u32 cpu_based_vm_exec_control;
4962
4963         /* clear pending NMI */
4964         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4965         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4966         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4967         ++vcpu->stat.nmi_window_exits;
4968         kvm_make_request(KVM_REQ_EVENT, vcpu);
4969
4970         return 1;
4971 }
4972
4973 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
4974 {
4975         struct vcpu_vmx *vmx = to_vmx(vcpu);
4976         enum emulation_result err = EMULATE_DONE;
4977         int ret = 1;
4978         u32 cpu_exec_ctrl;
4979         bool intr_window_requested;
4980         unsigned count = 130;
4981
4982         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4983         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
4984
4985         while (!guest_state_valid(vcpu) && count-- != 0) {
4986                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
4987                         return handle_interrupt_window(&vmx->vcpu);
4988
4989                 err = emulate_instruction(vcpu, 0);
4990
4991                 if (err == EMULATE_DO_MMIO) {
4992                         ret = 0;
4993                         goto out;
4994                 }
4995
4996                 if (err != EMULATE_DONE)
4997                         return 0;
4998
4999                 if (signal_pending(current))
5000                         goto out;
5001                 if (need_resched())
5002                         schedule();
5003         }
5004
5005         vmx->emulation_required = !guest_state_valid(vcpu);
5006 out:
5007         return ret;
5008 }
5009
5010 /*
5011  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5012  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5013  */
5014 static int handle_pause(struct kvm_vcpu *vcpu)
5015 {
5016         skip_emulated_instruction(vcpu);
5017         kvm_vcpu_on_spin(vcpu);
5018
5019         return 1;
5020 }
5021
5022 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5023 {
5024         kvm_queue_exception(vcpu, UD_VECTOR);
5025         return 1;
5026 }
5027
5028 /*
5029  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5030  * We could reuse a single VMCS for all the L2 guests, but we also want the
5031  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5032  * allows keeping them loaded on the processor, and in the future will allow
5033  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5034  * every entry if they never change.
5035  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5036  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5037  *
5038  * The following functions allocate and free a vmcs02 in this pool.
5039  */
5040
5041 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5042 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5043 {
5044         struct vmcs02_list *item;
5045         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5046                 if (item->vmptr == vmx->nested.current_vmptr) {
5047                         list_move(&item->list, &vmx->nested.vmcs02_pool);
5048                         return &item->vmcs02;
5049                 }
5050
5051         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5052                 /* Recycle the least recently used VMCS. */
5053                 item = list_entry(vmx->nested.vmcs02_pool.prev,
5054                         struct vmcs02_list, list);
5055                 item->vmptr = vmx->nested.current_vmptr;
5056                 list_move(&item->list, &vmx->nested.vmcs02_pool);
5057                 return &item->vmcs02;
5058         }
5059
5060         /* Create a new VMCS */
5061         item = (struct vmcs02_list *)
5062                 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5063         if (!item)
5064                 return NULL;
5065         item->vmcs02.vmcs = alloc_vmcs();
5066         if (!item->vmcs02.vmcs) {
5067                 kfree(item);
5068                 return NULL;
5069         }
5070         loaded_vmcs_init(&item->vmcs02);
5071         item->vmptr = vmx->nested.current_vmptr;
5072         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5073         vmx->nested.vmcs02_num++;
5074         return &item->vmcs02;
5075 }
5076
5077 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5078 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5079 {
5080         struct vmcs02_list *item;
5081         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5082                 if (item->vmptr == vmptr) {
5083                         free_loaded_vmcs(&item->vmcs02);
5084                         list_del(&item->list);
5085                         kfree(item);
5086                         vmx->nested.vmcs02_num--;
5087                         return;
5088                 }
5089 }
5090
5091 /*
5092  * Free all VMCSs saved for this vcpu, except the one pointed by
5093  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5094  * currently used, if running L2), and vmcs01 when running L2.
5095  */
5096 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5097 {
5098         struct vmcs02_list *item, *n;
5099         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5100                 if (vmx->loaded_vmcs != &item->vmcs02)
5101                         free_loaded_vmcs(&item->vmcs02);
5102                 list_del(&item->list);
5103                 kfree(item);
5104         }
5105         vmx->nested.vmcs02_num = 0;
5106
5107         if (vmx->loaded_vmcs != &vmx->vmcs01)
5108                 free_loaded_vmcs(&vmx->vmcs01);
5109 }
5110
5111 /*
5112  * Emulate the VMXON instruction.
5113  * Currently, we just remember that VMX is active, and do not save or even
5114  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5115  * do not currently need to store anything in that guest-allocated memory
5116  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5117  * argument is different from the VMXON pointer (which the spec says they do).
5118  */
5119 static int handle_vmon(struct kvm_vcpu *vcpu)
5120 {
5121         struct kvm_segment cs;
5122         struct vcpu_vmx *vmx = to_vmx(vcpu);
5123
5124         /* The Intel VMX Instruction Reference lists a bunch of bits that
5125          * are prerequisite to running VMXON, most notably cr4.VMXE must be
5126          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5127          * Otherwise, we should fail with #UD. We test these now:
5128          */
5129         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5130             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5131             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5132                 kvm_queue_exception(vcpu, UD_VECTOR);
5133                 return 1;
5134         }
5135
5136         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5137         if (is_long_mode(vcpu) && !cs.l) {
5138                 kvm_queue_exception(vcpu, UD_VECTOR);
5139                 return 1;
5140         }
5141
5142         if (vmx_get_cpl(vcpu)) {
5143                 kvm_inject_gp(vcpu, 0);
5144                 return 1;
5145         }
5146
5147         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5148         vmx->nested.vmcs02_num = 0;
5149
5150         vmx->nested.vmxon = true;
5151
5152         skip_emulated_instruction(vcpu);
5153         return 1;
5154 }
5155
5156 /*
5157  * Intel's VMX Instruction Reference specifies a common set of prerequisites
5158  * for running VMX instructions (except VMXON, whose prerequisites are
5159  * slightly different). It also specifies what exception to inject otherwise.
5160  */
5161 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5162 {
5163         struct kvm_segment cs;
5164         struct vcpu_vmx *vmx = to_vmx(vcpu);
5165
5166         if (!vmx->nested.vmxon) {
5167                 kvm_queue_exception(vcpu, UD_VECTOR);
5168                 return 0;
5169         }
5170
5171         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5172         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5173             (is_long_mode(vcpu) && !cs.l)) {
5174                 kvm_queue_exception(vcpu, UD_VECTOR);
5175                 return 0;
5176         }
5177
5178         if (vmx_get_cpl(vcpu)) {
5179                 kvm_inject_gp(vcpu, 0);
5180                 return 0;
5181         }
5182
5183         return 1;
5184 }
5185
5186 /*
5187  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5188  * just stops using VMX.
5189  */
5190 static void free_nested(struct vcpu_vmx *vmx)
5191 {
5192         if (!vmx->nested.vmxon)
5193                 return;
5194         vmx->nested.vmxon = false;
5195         if (vmx->nested.current_vmptr != -1ull) {
5196                 kunmap(vmx->nested.current_vmcs12_page);
5197                 nested_release_page(vmx->nested.current_vmcs12_page);
5198                 vmx->nested.current_vmptr = -1ull;
5199                 vmx->nested.current_vmcs12 = NULL;
5200         }
5201         /* Unpin physical memory we referred to in current vmcs02 */
5202         if (vmx->nested.apic_access_page) {
5203                 nested_release_page(vmx->nested.apic_access_page);
5204                 vmx->nested.apic_access_page = 0;
5205         }
5206
5207         nested_free_all_saved_vmcss(vmx);
5208 }
5209
5210 /* Emulate the VMXOFF instruction */
5211 static int handle_vmoff(struct kvm_vcpu *vcpu)
5212 {
5213         if (!nested_vmx_check_permission(vcpu))
5214                 return 1;
5215         free_nested(to_vmx(vcpu));
5216         skip_emulated_instruction(vcpu);
5217         return 1;
5218 }
5219
5220 /*
5221  * Decode the memory-address operand of a vmx instruction, as recorded on an
5222  * exit caused by such an instruction (run by a guest hypervisor).
5223  * On success, returns 0. When the operand is invalid, returns 1 and throws
5224  * #UD or #GP.
5225  */
5226 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5227                                  unsigned long exit_qualification,
5228                                  u32 vmx_instruction_info, gva_t *ret)
5229 {
5230         /*
5231          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5232          * Execution", on an exit, vmx_instruction_info holds most of the
5233          * addressing components of the operand. Only the displacement part
5234          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5235          * For how an actual address is calculated from all these components,
5236          * refer to Vol. 1, "Operand Addressing".
5237          */
5238         int  scaling = vmx_instruction_info & 3;
5239         int  addr_size = (vmx_instruction_info >> 7) & 7;
5240         bool is_reg = vmx_instruction_info & (1u << 10);
5241         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5242         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5243         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5244         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5245         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
5246
5247         if (is_reg) {
5248                 kvm_queue_exception(vcpu, UD_VECTOR);
5249                 return 1;
5250         }
5251
5252         /* Addr = segment_base + offset */
5253         /* offset = base + [index * scale] + displacement */
5254         *ret = vmx_get_segment_base(vcpu, seg_reg);
5255         if (base_is_valid)
5256                 *ret += kvm_register_read(vcpu, base_reg);
5257         if (index_is_valid)
5258                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5259         *ret += exit_qualification; /* holds the displacement */
5260
5261         if (addr_size == 1) /* 32 bit */
5262                 *ret &= 0xffffffff;
5263
5264         /*
5265          * TODO: throw #GP (and return 1) in various cases that the VM*
5266          * instructions require it - e.g., offset beyond segment limit,
5267          * unusable or unreadable/unwritable segment, non-canonical 64-bit
5268          * address, and so on. Currently these are not checked.
5269          */
5270         return 0;
5271 }
5272
5273 /*
5274  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5275  * set the success or error code of an emulated VMX instruction, as specified
5276  * by Vol 2B, VMX Instruction Reference, "Conventions".
5277  */
5278 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5279 {
5280         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5281                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5282                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5283 }
5284
5285 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5286 {
5287         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5288                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5289                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5290                         | X86_EFLAGS_CF);
5291 }
5292
5293 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5294                                         u32 vm_instruction_error)
5295 {
5296         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5297                 /*
5298                  * failValid writes the error number to the current VMCS, which
5299                  * can't be done there isn't a current VMCS.
5300                  */
5301                 nested_vmx_failInvalid(vcpu);
5302                 return;
5303         }
5304         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5305                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5306                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5307                         | X86_EFLAGS_ZF);
5308         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5309 }
5310
5311 /* Emulate the VMCLEAR instruction */
5312 static int handle_vmclear(struct kvm_vcpu *vcpu)
5313 {
5314         struct vcpu_vmx *vmx = to_vmx(vcpu);
5315         gva_t gva;
5316         gpa_t vmptr;
5317         struct vmcs12 *vmcs12;
5318         struct page *page;
5319         struct x86_exception e;
5320
5321         if (!nested_vmx_check_permission(vcpu))
5322                 return 1;
5323
5324         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5325                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5326                 return 1;
5327
5328         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5329                                 sizeof(vmptr), &e)) {
5330                 kvm_inject_page_fault(vcpu, &e);
5331                 return 1;
5332         }
5333
5334         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5335                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5336                 skip_emulated_instruction(vcpu);
5337                 return 1;
5338         }
5339
5340         if (vmptr == vmx->nested.current_vmptr) {
5341                 kunmap(vmx->nested.current_vmcs12_page);
5342                 nested_release_page(vmx->nested.current_vmcs12_page);
5343                 vmx->nested.current_vmptr = -1ull;
5344                 vmx->nested.current_vmcs12 = NULL;
5345         }
5346
5347         page = nested_get_page(vcpu, vmptr);
5348         if (page == NULL) {
5349                 /*
5350                  * For accurate processor emulation, VMCLEAR beyond available
5351                  * physical memory should do nothing at all. However, it is
5352                  * possible that a nested vmx bug, not a guest hypervisor bug,
5353                  * resulted in this case, so let's shut down before doing any
5354                  * more damage:
5355                  */
5356                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5357                 return 1;
5358         }
5359         vmcs12 = kmap(page);
5360         vmcs12->launch_state = 0;
5361         kunmap(page);
5362         nested_release_page(page);
5363
5364         nested_free_vmcs02(vmx, vmptr);
5365
5366         skip_emulated_instruction(vcpu);
5367         nested_vmx_succeed(vcpu);
5368         return 1;
5369 }
5370
5371 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5372
5373 /* Emulate the VMLAUNCH instruction */
5374 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5375 {
5376         return nested_vmx_run(vcpu, true);
5377 }
5378
5379 /* Emulate the VMRESUME instruction */
5380 static int handle_vmresume(struct kvm_vcpu *vcpu)
5381 {
5382
5383         return nested_vmx_run(vcpu, false);
5384 }
5385
5386 enum vmcs_field_type {
5387         VMCS_FIELD_TYPE_U16 = 0,
5388         VMCS_FIELD_TYPE_U64 = 1,
5389         VMCS_FIELD_TYPE_U32 = 2,
5390         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5391 };
5392
5393 static inline int vmcs_field_type(unsigned long field)
5394 {
5395         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
5396                 return VMCS_FIELD_TYPE_U32;
5397         return (field >> 13) & 0x3 ;
5398 }
5399
5400 static inline int vmcs_field_readonly(unsigned long field)
5401 {
5402         return (((field >> 10) & 0x3) == 1);
5403 }
5404
5405 /*
5406  * Read a vmcs12 field. Since these can have varying lengths and we return
5407  * one type, we chose the biggest type (u64) and zero-extend the return value
5408  * to that size. Note that the caller, handle_vmread, might need to use only
5409  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5410  * 64-bit fields are to be returned).
5411  */
5412 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5413                                         unsigned long field, u64 *ret)
5414 {
5415         short offset = vmcs_field_to_offset(field);
5416         char *p;
5417
5418         if (offset < 0)
5419                 return 0;
5420
5421         p = ((char *)(get_vmcs12(vcpu))) + offset;
5422
5423         switch (vmcs_field_type(field)) {
5424         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5425                 *ret = *((natural_width *)p);
5426                 return 1;
5427         case VMCS_FIELD_TYPE_U16:
5428                 *ret = *((u16 *)p);
5429                 return 1;
5430         case VMCS_FIELD_TYPE_U32:
5431                 *ret = *((u32 *)p);
5432                 return 1;
5433         case VMCS_FIELD_TYPE_U64:
5434                 *ret = *((u64 *)p);
5435                 return 1;
5436         default:
5437                 return 0; /* can never happen. */
5438         }
5439 }
5440
5441 /*
5442  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5443  * used before) all generate the same failure when it is missing.
5444  */
5445 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5446 {
5447         struct vcpu_vmx *vmx = to_vmx(vcpu);
5448         if (vmx->nested.current_vmptr == -1ull) {
5449                 nested_vmx_failInvalid(vcpu);
5450                 skip_emulated_instruction(vcpu);
5451                 return 0;
5452         }
5453         return 1;
5454 }
5455
5456 static int handle_vmread(struct kvm_vcpu *vcpu)
5457 {
5458         unsigned long field;
5459         u64 field_value;
5460         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5461         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5462         gva_t gva = 0;
5463
5464         if (!nested_vmx_check_permission(vcpu) ||
5465             !nested_vmx_check_vmcs12(vcpu))
5466                 return 1;
5467
5468         /* Decode instruction info and find the field to read */
5469         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5470         /* Read the field, zero-extended to a u64 field_value */
5471         if (!vmcs12_read_any(vcpu, field, &field_value)) {
5472                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5473                 skip_emulated_instruction(vcpu);
5474                 return 1;
5475         }
5476         /*
5477          * Now copy part of this value to register or memory, as requested.
5478          * Note that the number of bits actually copied is 32 or 64 depending
5479          * on the guest's mode (32 or 64 bit), not on the given field's length.
5480          */
5481         if (vmx_instruction_info & (1u << 10)) {
5482                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5483                         field_value);
5484         } else {
5485                 if (get_vmx_mem_address(vcpu, exit_qualification,
5486                                 vmx_instruction_info, &gva))
5487                         return 1;
5488                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5489                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5490                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5491         }
5492
5493         nested_vmx_succeed(vcpu);
5494         skip_emulated_instruction(vcpu);
5495         return 1;
5496 }
5497
5498
5499 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5500 {
5501         unsigned long field;
5502         gva_t gva;
5503         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5504         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5505         char *p;
5506         short offset;
5507         /* The value to write might be 32 or 64 bits, depending on L1's long
5508          * mode, and eventually we need to write that into a field of several
5509          * possible lengths. The code below first zero-extends the value to 64
5510          * bit (field_value), and then copies only the approriate number of
5511          * bits into the vmcs12 field.
5512          */
5513         u64 field_value = 0;
5514         struct x86_exception e;
5515
5516         if (!nested_vmx_check_permission(vcpu) ||
5517             !nested_vmx_check_vmcs12(vcpu))
5518                 return 1;
5519
5520         if (vmx_instruction_info & (1u << 10))
5521                 field_value = kvm_register_read(vcpu,
5522                         (((vmx_instruction_info) >> 3) & 0xf));
5523         else {
5524                 if (get_vmx_mem_address(vcpu, exit_qualification,
5525                                 vmx_instruction_info, &gva))
5526                         return 1;
5527                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5528                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5529                         kvm_inject_page_fault(vcpu, &e);
5530                         return 1;
5531                 }
5532         }
5533
5534
5535         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5536         if (vmcs_field_readonly(field)) {
5537                 nested_vmx_failValid(vcpu,
5538                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5539                 skip_emulated_instruction(vcpu);
5540                 return 1;
5541         }
5542
5543         offset = vmcs_field_to_offset(field);
5544         if (offset < 0) {
5545                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5546                 skip_emulated_instruction(vcpu);
5547                 return 1;
5548         }
5549         p = ((char *) get_vmcs12(vcpu)) + offset;
5550
5551         switch (vmcs_field_type(field)) {
5552         case VMCS_FIELD_TYPE_U16:
5553                 *(u16 *)p = field_value;
5554                 break;
5555         case VMCS_FIELD_TYPE_U32:
5556                 *(u32 *)p = field_value;
5557                 break;
5558         case VMCS_FIELD_TYPE_U64:
5559                 *(u64 *)p = field_value;
5560                 break;
5561         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5562                 *(natural_width *)p = field_value;
5563                 break;
5564         default:
5565                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5566                 skip_emulated_instruction(vcpu);
5567                 return 1;
5568         }
5569
5570         nested_vmx_succeed(vcpu);
5571         skip_emulated_instruction(vcpu);
5572         return 1;
5573 }
5574
5575 /* Emulate the VMPTRLD instruction */
5576 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5577 {
5578         struct vcpu_vmx *vmx = to_vmx(vcpu);
5579         gva_t gva;
5580         gpa_t vmptr;
5581         struct x86_exception e;
5582
5583         if (!nested_vmx_check_permission(vcpu))
5584                 return 1;
5585
5586         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5587                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5588                 return 1;
5589
5590         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5591                                 sizeof(vmptr), &e)) {
5592                 kvm_inject_page_fault(vcpu, &e);
5593                 return 1;
5594         }
5595
5596         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5597                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5598                 skip_emulated_instruction(vcpu);
5599                 return 1;
5600         }
5601
5602         if (vmx->nested.current_vmptr != vmptr) {
5603                 struct vmcs12 *new_vmcs12;
5604                 struct page *page;
5605                 page = nested_get_page(vcpu, vmptr);
5606                 if (page == NULL) {
5607                         nested_vmx_failInvalid(vcpu);
5608                         skip_emulated_instruction(vcpu);
5609                         return 1;
5610                 }
5611                 new_vmcs12 = kmap(page);
5612                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5613                         kunmap(page);
5614                         nested_release_page_clean(page);
5615                         nested_vmx_failValid(vcpu,
5616                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5617                         skip_emulated_instruction(vcpu);
5618                         return 1;
5619                 }
5620                 if (vmx->nested.current_vmptr != -1ull) {
5621                         kunmap(vmx->nested.current_vmcs12_page);
5622                         nested_release_page(vmx->nested.current_vmcs12_page);
5623                 }
5624
5625                 vmx->nested.current_vmptr = vmptr;
5626                 vmx->nested.current_vmcs12 = new_vmcs12;
5627                 vmx->nested.current_vmcs12_page = page;
5628         }
5629
5630         nested_vmx_succeed(vcpu);
5631         skip_emulated_instruction(vcpu);
5632         return 1;
5633 }
5634
5635 /* Emulate the VMPTRST instruction */
5636 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5637 {
5638         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5639         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5640         gva_t vmcs_gva;
5641         struct x86_exception e;
5642
5643         if (!nested_vmx_check_permission(vcpu))
5644                 return 1;
5645
5646         if (get_vmx_mem_address(vcpu, exit_qualification,
5647                         vmx_instruction_info, &vmcs_gva))
5648                 return 1;
5649         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5650         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5651                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
5652                                  sizeof(u64), &e)) {
5653                 kvm_inject_page_fault(vcpu, &e);
5654                 return 1;
5655         }
5656         nested_vmx_succeed(vcpu);
5657         skip_emulated_instruction(vcpu);
5658         return 1;
5659 }
5660
5661 /*
5662  * The exit handlers return 1 if the exit was handled fully and guest execution
5663  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5664  * to be done to userspace and return 0.
5665  */
5666 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5667         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
5668         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5669         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5670         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5671         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5672         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5673         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5674         [EXIT_REASON_CPUID]                   = handle_cpuid,
5675         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
5676         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
5677         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
5678         [EXIT_REASON_HLT]                     = handle_halt,
5679         [EXIT_REASON_INVD]                    = handle_invd,
5680         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5681         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
5682         [EXIT_REASON_VMCALL]                  = handle_vmcall,
5683         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
5684         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
5685         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
5686         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
5687         [EXIT_REASON_VMREAD]                  = handle_vmread,
5688         [EXIT_REASON_VMRESUME]                = handle_vmresume,
5689         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
5690         [EXIT_REASON_VMOFF]                   = handle_vmoff,
5691         [EXIT_REASON_VMON]                    = handle_vmon,
5692         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5693         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5694         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
5695         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
5696         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5697         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5698         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5699         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5700         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5701         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
5702         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
5703 };
5704
5705 static const int kvm_vmx_max_exit_handlers =
5706         ARRAY_SIZE(kvm_vmx_exit_handlers);
5707
5708 /*
5709  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5710  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5711  * disinterest in the current event (read or write a specific MSR) by using an
5712  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5713  */
5714 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5715         struct vmcs12 *vmcs12, u32 exit_reason)
5716 {
5717         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5718         gpa_t bitmap;
5719
5720         if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5721                 return 1;
5722
5723         /*
5724          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5725          * for the four combinations of read/write and low/high MSR numbers.
5726          * First we need to figure out which of the four to use:
5727          */
5728         bitmap = vmcs12->msr_bitmap;
5729         if (exit_reason == EXIT_REASON_MSR_WRITE)
5730                 bitmap += 2048;
5731         if (msr_index >= 0xc0000000) {
5732                 msr_index -= 0xc0000000;
5733                 bitmap += 1024;
5734         }
5735
5736         /* Then read the msr_index'th bit from this bitmap: */
5737         if (msr_index < 1024*8) {
5738                 unsigned char b;
5739                 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5740                 return 1 & (b >> (msr_index & 7));
5741         } else
5742                 return 1; /* let L1 handle the wrong parameter */
5743 }
5744
5745 /*
5746  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5747  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5748  * intercept (via guest_host_mask etc.) the current event.
5749  */
5750 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5751         struct vmcs12 *vmcs12)
5752 {
5753         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5754         int cr = exit_qualification & 15;
5755         int reg = (exit_qualification >> 8) & 15;
5756         unsigned long val = kvm_register_read(vcpu, reg);
5757
5758         switch ((exit_qualification >> 4) & 3) {
5759         case 0: /* mov to cr */
5760                 switch (cr) {
5761                 case 0:
5762                         if (vmcs12->cr0_guest_host_mask &
5763                             (val ^ vmcs12->cr0_read_shadow))
5764                                 return 1;
5765                         break;
5766                 case 3:
5767                         if ((vmcs12->cr3_target_count >= 1 &&
5768                                         vmcs12->cr3_target_value0 == val) ||
5769                                 (vmcs12->cr3_target_count >= 2 &&
5770                                         vmcs12->cr3_target_value1 == val) ||
5771                                 (vmcs12->cr3_target_count >= 3 &&
5772                                         vmcs12->cr3_target_value2 == val) ||
5773                                 (vmcs12->cr3_target_count >= 4 &&
5774                                         vmcs12->cr3_target_value3 == val))
5775                                 return 0;
5776                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5777                                 return 1;
5778                         break;
5779                 case 4:
5780                         if (vmcs12->cr4_guest_host_mask &
5781                             (vmcs12->cr4_read_shadow ^ val))
5782                                 return 1;
5783                         break;
5784                 case 8:
5785                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5786                                 return 1;
5787                         break;
5788                 }
5789                 break;
5790         case 2: /* clts */
5791                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5792                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
5793                         return 1;
5794                 break;
5795         case 1: /* mov from cr */
5796                 switch (cr) {
5797                 case 3:
5798                         if (vmcs12->cpu_based_vm_exec_control &
5799                             CPU_BASED_CR3_STORE_EXITING)
5800                                 return 1;
5801                         break;
5802                 case 8:
5803                         if (vmcs12->cpu_based_vm_exec_control &
5804                             CPU_BASED_CR8_STORE_EXITING)
5805                                 return 1;
5806                         break;
5807                 }
5808                 break;
5809         case 3: /* lmsw */
5810                 /*
5811                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5812                  * cr0. Other attempted changes are ignored, with no exit.
5813                  */
5814                 if (vmcs12->cr0_guest_host_mask & 0xe &
5815                     (val ^ vmcs12->cr0_read_shadow))
5816                         return 1;
5817                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5818                     !(vmcs12->cr0_read_shadow & 0x1) &&
5819                     (val & 0x1))
5820                         return 1;
5821                 break;
5822         }
5823         return 0;
5824 }
5825
5826 /*
5827  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5828  * should handle it ourselves in L0 (and then continue L2). Only call this
5829  * when in is_guest_mode (L2).
5830  */
5831 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5832 {
5833         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5834         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5835         struct vcpu_vmx *vmx = to_vmx(vcpu);
5836         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5837
5838         if (vmx->nested.nested_run_pending)
5839                 return 0;
5840
5841         if (unlikely(vmx->fail)) {
5842                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5843                                     vmcs_read32(VM_INSTRUCTION_ERROR));
5844                 return 1;
5845         }
5846
5847         switch (exit_reason) {
5848         case EXIT_REASON_EXCEPTION_NMI:
5849                 if (!is_exception(intr_info))
5850                         return 0;
5851                 else if (is_page_fault(intr_info))
5852                         return enable_ept;
5853                 return vmcs12->exception_bitmap &
5854                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5855         case EXIT_REASON_EXTERNAL_INTERRUPT:
5856                 return 0;
5857         case EXIT_REASON_TRIPLE_FAULT:
5858                 return 1;
5859         case EXIT_REASON_PENDING_INTERRUPT:
5860         case EXIT_REASON_NMI_WINDOW:
5861                 /*
5862                  * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5863                  * (aka Interrupt Window Exiting) only when L1 turned it on,
5864                  * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5865                  * Same for NMI Window Exiting.
5866                  */
5867                 return 1;
5868         case EXIT_REASON_TASK_SWITCH:
5869                 return 1;
5870         case EXIT_REASON_CPUID:
5871                 return 1;
5872         case EXIT_REASON_HLT:
5873                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5874         case EXIT_REASON_INVD:
5875                 return 1;
5876         case EXIT_REASON_INVLPG:
5877                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5878         case EXIT_REASON_RDPMC:
5879                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5880         case EXIT_REASON_RDTSC:
5881                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5882         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5883         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5884         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5885         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5886         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5887                 /*
5888                  * VMX instructions trap unconditionally. This allows L1 to
5889                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
5890                  */
5891                 return 1;
5892         case EXIT_REASON_CR_ACCESS:
5893                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5894         case EXIT_REASON_DR_ACCESS:
5895                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5896         case EXIT_REASON_IO_INSTRUCTION:
5897                 /* TODO: support IO bitmaps */
5898                 return 1;
5899         case EXIT_REASON_MSR_READ:
5900         case EXIT_REASON_MSR_WRITE:
5901                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5902         case EXIT_REASON_INVALID_STATE:
5903                 return 1;
5904         case EXIT_REASON_MWAIT_INSTRUCTION:
5905                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5906         case EXIT_REASON_MONITOR_INSTRUCTION:
5907                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5908         case EXIT_REASON_PAUSE_INSTRUCTION:
5909                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5910                         nested_cpu_has2(vmcs12,
5911                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5912         case EXIT_REASON_MCE_DURING_VMENTRY:
5913                 return 0;
5914         case EXIT_REASON_TPR_BELOW_THRESHOLD:
5915                 return 1;
5916         case EXIT_REASON_APIC_ACCESS:
5917                 return nested_cpu_has2(vmcs12,
5918                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5919         case EXIT_REASON_EPT_VIOLATION:
5920         case EXIT_REASON_EPT_MISCONFIG:
5921                 return 0;
5922         case EXIT_REASON_WBINVD:
5923                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5924         case EXIT_REASON_XSETBV:
5925                 return 1;
5926         default:
5927                 return 1;
5928         }
5929 }
5930
5931 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5932 {
5933         *info1 = vmcs_readl(EXIT_QUALIFICATION);
5934         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5935 }
5936
5937 /*
5938  * The guest has exited.  See if we can fix it or if we need userspace
5939  * assistance.
5940  */
5941 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5942 {
5943         struct vcpu_vmx *vmx = to_vmx(vcpu);
5944         u32 exit_reason = vmx->exit_reason;
5945         u32 vectoring_info = vmx->idt_vectoring_info;
5946
5947         /* If guest state is invalid, start emulating */
5948         if (vmx->emulation_required && emulate_invalid_guest_state)
5949                 return handle_invalid_guest_state(vcpu);
5950
5951         /*
5952          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5953          * we did not inject a still-pending event to L1 now because of
5954          * nested_run_pending, we need to re-enable this bit.
5955          */
5956         if (vmx->nested.nested_run_pending)
5957                 kvm_make_request(KVM_REQ_EVENT, vcpu);
5958
5959         if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5960             exit_reason == EXIT_REASON_VMRESUME))
5961                 vmx->nested.nested_run_pending = 1;
5962         else
5963                 vmx->nested.nested_run_pending = 0;
5964
5965         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5966                 nested_vmx_vmexit(vcpu);
5967                 return 1;
5968         }
5969
5970         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5971                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5972                 vcpu->run->fail_entry.hardware_entry_failure_reason
5973                         = exit_reason;
5974                 return 0;
5975         }
5976
5977         if (unlikely(vmx->fail)) {
5978                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5979                 vcpu->run->fail_entry.hardware_entry_failure_reason
5980                         = vmcs_read32(VM_INSTRUCTION_ERROR);
5981                 return 0;
5982         }
5983
5984         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5985                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5986                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
5987                         exit_reason != EXIT_REASON_TASK_SWITCH))
5988                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
5989                        "(0x%x) and exit reason is 0x%x\n",
5990                        __func__, vectoring_info, exit_reason);
5991
5992         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
5993             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
5994                                         get_vmcs12(vcpu), vcpu)))) {
5995                 if (vmx_interrupt_allowed(vcpu)) {
5996                         vmx->soft_vnmi_blocked = 0;
5997                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
5998                            vcpu->arch.nmi_pending) {
5999                         /*
6000                          * This CPU don't support us in finding the end of an
6001                          * NMI-blocked window if the guest runs with IRQs
6002                          * disabled. So we pull the trigger after 1 s of
6003                          * futile waiting, but inform the user about this.
6004                          */
6005                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6006                                "state on VCPU %d after 1 s timeout\n",
6007                                __func__, vcpu->vcpu_id);
6008                         vmx->soft_vnmi_blocked = 0;
6009                 }
6010         }
6011
6012         if (exit_reason < kvm_vmx_max_exit_handlers
6013             && kvm_vmx_exit_handlers[exit_reason])
6014                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6015         else {
6016                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6017                 vcpu->run->hw.hardware_exit_reason = exit_reason;
6018         }
6019         return 0;
6020 }
6021
6022 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6023 {
6024         if (irr == -1 || tpr < irr) {
6025                 vmcs_write32(TPR_THRESHOLD, 0);
6026                 return;
6027         }
6028
6029         vmcs_write32(TPR_THRESHOLD, irr);
6030 }
6031
6032 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
6033 {
6034         u32 exit_intr_info;
6035
6036         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6037               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6038                 return;
6039
6040         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6041         exit_intr_info = vmx->exit_intr_info;
6042
6043         /* Handle machine checks before interrupts are enabled */
6044         if (is_machine_check(exit_intr_info))
6045                 kvm_machine_check();
6046
6047         /* We need to handle NMIs before interrupts are enabled */
6048         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
6049             (exit_intr_info & INTR_INFO_VALID_MASK)) {
6050                 kvm_before_handle_nmi(&vmx->vcpu);
6051                 asm("int $2");
6052                 kvm_after_handle_nmi(&vmx->vcpu);
6053         }
6054 }
6055
6056 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6057 {
6058         u32 exit_intr_info;
6059         bool unblock_nmi;
6060         u8 vector;
6061         bool idtv_info_valid;
6062
6063         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6064
6065         if (cpu_has_virtual_nmis()) {
6066                 if (vmx->nmi_known_unmasked)
6067                         return;
6068                 /*
6069                  * Can't use vmx->exit_intr_info since we're not sure what
6070                  * the exit reason is.
6071                  */
6072                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6073                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6074                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6075                 /*
6076                  * SDM 3: 27.7.1.2 (September 2008)
6077                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
6078                  * a guest IRET fault.
6079                  * SDM 3: 23.2.2 (September 2008)
6080                  * Bit 12 is undefined in any of the following cases:
6081                  *  If the VM exit sets the valid bit in the IDT-vectoring
6082                  *   information field.
6083                  *  If the VM exit is due to a double fault.
6084                  */
6085                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6086                     vector != DF_VECTOR && !idtv_info_valid)
6087                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6088                                       GUEST_INTR_STATE_NMI);
6089                 else
6090                         vmx->nmi_known_unmasked =
6091                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6092                                   & GUEST_INTR_STATE_NMI);
6093         } else if (unlikely(vmx->soft_vnmi_blocked))
6094                 vmx->vnmi_blocked_time +=
6095                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
6096 }
6097
6098 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
6099                                       u32 idt_vectoring_info,
6100                                       int instr_len_field,
6101                                       int error_code_field)
6102 {
6103         u8 vector;
6104         int type;
6105         bool idtv_info_valid;
6106
6107         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6108
6109         vmx->vcpu.arch.nmi_injected = false;
6110         kvm_clear_exception_queue(&vmx->vcpu);
6111         kvm_clear_interrupt_queue(&vmx->vcpu);
6112
6113         if (!idtv_info_valid)
6114                 return;
6115
6116         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6117
6118         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6119         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6120
6121         switch (type) {
6122         case INTR_TYPE_NMI_INTR:
6123                 vmx->vcpu.arch.nmi_injected = true;
6124                 /*
6125                  * SDM 3: 27.7.1.2 (September 2008)
6126                  * Clear bit "block by NMI" before VM entry if a NMI
6127                  * delivery faulted.
6128                  */
6129                 vmx_set_nmi_mask(&vmx->vcpu, false);
6130                 break;
6131         case INTR_TYPE_SOFT_EXCEPTION:
6132                 vmx->vcpu.arch.event_exit_inst_len =
6133                         vmcs_read32(instr_len_field);
6134                 /* fall through */
6135         case INTR_TYPE_HARD_EXCEPTION:
6136                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6137                         u32 err = vmcs_read32(error_code_field);
6138                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
6139                 } else
6140                         kvm_queue_exception(&vmx->vcpu, vector);
6141                 break;
6142         case INTR_TYPE_SOFT_INTR:
6143                 vmx->vcpu.arch.event_exit_inst_len =
6144                         vmcs_read32(instr_len_field);
6145                 /* fall through */
6146         case INTR_TYPE_EXT_INTR:
6147                 kvm_queue_interrupt(&vmx->vcpu, vector,
6148                         type == INTR_TYPE_SOFT_INTR);
6149                 break;
6150         default:
6151                 break;
6152         }
6153 }
6154
6155 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6156 {
6157         if (is_guest_mode(&vmx->vcpu))
6158                 return;
6159         __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6160                                   VM_EXIT_INSTRUCTION_LEN,
6161                                   IDT_VECTORING_ERROR_CODE);
6162 }
6163
6164 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6165 {
6166         if (is_guest_mode(vcpu))
6167                 return;
6168         __vmx_complete_interrupts(to_vmx(vcpu),
6169                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6170                                   VM_ENTRY_INSTRUCTION_LEN,
6171                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6172
6173         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6174 }
6175
6176 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6177 {
6178         int i, nr_msrs;
6179         struct perf_guest_switch_msr *msrs;
6180
6181         msrs = perf_guest_get_msrs(&nr_msrs);
6182
6183         if (!msrs)
6184                 return;
6185
6186         for (i = 0; i < nr_msrs; i++)
6187                 if (msrs[i].host == msrs[i].guest)
6188                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6189                 else
6190                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6191                                         msrs[i].host);
6192 }
6193
6194 #ifdef CONFIG_X86_64
6195 #define R "r"
6196 #define Q "q"
6197 #else
6198 #define R "e"
6199 #define Q "l"
6200 #endif
6201
6202 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6203 {
6204         struct vcpu_vmx *vmx = to_vmx(vcpu);
6205
6206         if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6207                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6208                 if (vmcs12->idt_vectoring_info_field &
6209                                 VECTORING_INFO_VALID_MASK) {
6210                         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6211                                 vmcs12->idt_vectoring_info_field);
6212                         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6213                                 vmcs12->vm_exit_instruction_len);
6214                         if (vmcs12->idt_vectoring_info_field &
6215                                         VECTORING_INFO_DELIVER_CODE_MASK)
6216                                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6217                                         vmcs12->idt_vectoring_error_code);
6218                 }
6219         }
6220
6221         /* Record the guest's net vcpu time for enforced NMI injections. */
6222         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6223                 vmx->entry_time = ktime_get();
6224
6225         /* Don't enter VMX if guest state is invalid, let the exit handler
6226            start emulation until we arrive back to a valid state */
6227         if (vmx->emulation_required && emulate_invalid_guest_state)
6228                 return;
6229
6230         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6231                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6232         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6233                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6234
6235         /* When single-stepping over STI and MOV SS, we must clear the
6236          * corresponding interruptibility bits in the guest state. Otherwise
6237          * vmentry fails as it then expects bit 14 (BS) in pending debug
6238          * exceptions being set, but that's not correct for the guest debugging
6239          * case. */
6240         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6241                 vmx_set_interrupt_shadow(vcpu, 0);
6242
6243         atomic_switch_perf_msrs(vmx);
6244
6245         vmx->__launched = vmx->loaded_vmcs->launched;
6246         asm(
6247                 /* Store host registers */
6248                 "push %%"R"dx; push %%"R"bp;"
6249                 "push %%"R"cx \n\t" /* placeholder for guest rcx */
6250                 "push %%"R"cx \n\t"
6251                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
6252                 "je 1f \n\t"
6253                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
6254                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
6255                 "1: \n\t"
6256                 /* Reload cr2 if changed */
6257                 "mov %c[cr2](%0), %%"R"ax \n\t"
6258                 "mov %%cr2, %%"R"dx \n\t"
6259                 "cmp %%"R"ax, %%"R"dx \n\t"
6260                 "je 2f \n\t"
6261                 "mov %%"R"ax, %%cr2 \n\t"
6262                 "2: \n\t"
6263                 /* Check if vmlaunch of vmresume is needed */
6264                 "cmpl $0, %c[launched](%0) \n\t"
6265                 /* Load guest registers.  Don't clobber flags. */
6266                 "mov %c[rax](%0), %%"R"ax \n\t"
6267                 "mov %c[rbx](%0), %%"R"bx \n\t"
6268                 "mov %c[rdx](%0), %%"R"dx \n\t"
6269                 "mov %c[rsi](%0), %%"R"si \n\t"
6270                 "mov %c[rdi](%0), %%"R"di \n\t"
6271                 "mov %c[rbp](%0), %%"R"bp \n\t"
6272 #ifdef CONFIG_X86_64
6273                 "mov %c[r8](%0),  %%r8  \n\t"
6274                 "mov %c[r9](%0),  %%r9  \n\t"
6275                 "mov %c[r10](%0), %%r10 \n\t"
6276                 "mov %c[r11](%0), %%r11 \n\t"
6277                 "mov %c[r12](%0), %%r12 \n\t"
6278                 "mov %c[r13](%0), %%r13 \n\t"
6279                 "mov %c[r14](%0), %%r14 \n\t"
6280                 "mov %c[r15](%0), %%r15 \n\t"
6281 #endif
6282                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
6283
6284                 /* Enter guest mode */
6285                 "jne .Llaunched \n\t"
6286                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
6287                 "jmp .Lkvm_vmx_return \n\t"
6288                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
6289                 ".Lkvm_vmx_return: "
6290                 /* Save guest registers, load host registers, keep flags */
6291                 "mov %0, %c[wordsize](%%"R"sp) \n\t"
6292                 "pop %0 \n\t"
6293                 "mov %%"R"ax, %c[rax](%0) \n\t"
6294                 "mov %%"R"bx, %c[rbx](%0) \n\t"
6295                 "pop"Q" %c[rcx](%0) \n\t"
6296                 "mov %%"R"dx, %c[rdx](%0) \n\t"
6297                 "mov %%"R"si, %c[rsi](%0) \n\t"
6298                 "mov %%"R"di, %c[rdi](%0) \n\t"
6299                 "mov %%"R"bp, %c[rbp](%0) \n\t"
6300 #ifdef CONFIG_X86_64
6301                 "mov %%r8,  %c[r8](%0) \n\t"
6302                 "mov %%r9,  %c[r9](%0) \n\t"
6303                 "mov %%r10, %c[r10](%0) \n\t"
6304                 "mov %%r11, %c[r11](%0) \n\t"
6305                 "mov %%r12, %c[r12](%0) \n\t"
6306                 "mov %%r13, %c[r13](%0) \n\t"
6307                 "mov %%r14, %c[r14](%0) \n\t"
6308                 "mov %%r15, %c[r15](%0) \n\t"
6309 #endif
6310                 "mov %%cr2, %%"R&quo