2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affilates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/moduleparam.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31 #include <linux/tboot.h>
32 #include "kvm_cache_regs.h"
38 #include <asm/virtext.h>
43 #define __ex(x) __kvm_handle_fault_on_reboot(x)
45 MODULE_AUTHOR("Qumranet");
46 MODULE_LICENSE("GPL");
48 static int __read_mostly bypass_guest_pf = 1;
49 module_param(bypass_guest_pf, bool, S_IRUGO);
51 static int __read_mostly enable_vpid = 1;
52 module_param_named(vpid, enable_vpid, bool, 0444);
54 static int __read_mostly flexpriority_enabled = 1;
55 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
57 static int __read_mostly enable_ept = 1;
58 module_param_named(ept, enable_ept, bool, S_IRUGO);
60 static int __read_mostly enable_unrestricted_guest = 1;
61 module_param_named(unrestricted_guest,
62 enable_unrestricted_guest, bool, S_IRUGO);
64 static int __read_mostly emulate_invalid_guest_state = 0;
65 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
67 static int __read_mostly vmm_exclusive = 1;
68 module_param(vmm_exclusive, bool, S_IRUGO);
70 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
71 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
72 #define KVM_GUEST_CR0_MASK \
73 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
74 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
75 (X86_CR0_WP | X86_CR0_NE)
76 #define KVM_VM_CR0_ALWAYS_ON \
77 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
78 #define KVM_CR4_GUEST_OWNED_BITS \
79 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
82 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
83 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
85 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
88 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
89 * ple_gap: upper bound on the amount of time between two successive
90 * executions of PAUSE in a loop. Also indicate if ple enabled.
91 * According to test, this time is usually small than 41 cycles.
92 * ple_window: upper bound on the amount of time a guest is allowed to execute
93 * in a PAUSE loop. Tests indicate that most spinlocks are held for
94 * less than 2^12 cycles
95 * Time is measured based on a counter that runs at the same rate as the TSC,
96 * refer SDM volume 3b section 21.6.13 & 22.1.3.
98 #define KVM_VMX_DEFAULT_PLE_GAP 41
99 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
100 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
101 module_param(ple_gap, int, S_IRUGO);
103 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
104 module_param(ple_window, int, S_IRUGO);
106 #define NR_AUTOLOAD_MSRS 1
114 struct shared_msr_entry {
121 struct kvm_vcpu vcpu;
122 struct list_head local_vcpus_link;
123 unsigned long host_rsp;
126 u32 idt_vectoring_info;
127 struct shared_msr_entry *guest_msrs;
131 u64 msr_host_kernel_gs_base;
132 u64 msr_guest_kernel_gs_base;
135 struct msr_autoload {
137 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
138 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
142 u16 fs_sel, gs_sel, ldt_sel;
143 int gs_ldt_reload_needed;
144 int fs_reload_needed;
149 struct kvm_save_segment {
154 } tr, es, ds, fs, gs;
162 bool emulation_required;
164 /* Support for vnmi-less CPUs */
165 int soft_vnmi_blocked;
167 s64 vnmi_blocked_time;
173 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
175 return container_of(vcpu, struct vcpu_vmx, vcpu);
178 static int init_rmode(struct kvm *kvm);
179 static u64 construct_eptp(unsigned long root_hpa);
180 static void kvm_cpu_vmxon(u64 addr);
181 static void kvm_cpu_vmxoff(void);
183 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
184 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
185 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
187 static unsigned long *vmx_io_bitmap_a;
188 static unsigned long *vmx_io_bitmap_b;
189 static unsigned long *vmx_msr_bitmap_legacy;
190 static unsigned long *vmx_msr_bitmap_longmode;
192 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
193 static DEFINE_SPINLOCK(vmx_vpid_lock);
195 static struct vmcs_config {
199 u32 pin_based_exec_ctrl;
200 u32 cpu_based_exec_ctrl;
201 u32 cpu_based_2nd_exec_ctrl;
206 static struct vmx_capability {
211 #define VMX_SEGMENT_FIELD(seg) \
212 [VCPU_SREG_##seg] = { \
213 .selector = GUEST_##seg##_SELECTOR, \
214 .base = GUEST_##seg##_BASE, \
215 .limit = GUEST_##seg##_LIMIT, \
216 .ar_bytes = GUEST_##seg##_AR_BYTES, \
219 static struct kvm_vmx_segment_field {
224 } kvm_vmx_segment_fields[] = {
225 VMX_SEGMENT_FIELD(CS),
226 VMX_SEGMENT_FIELD(DS),
227 VMX_SEGMENT_FIELD(ES),
228 VMX_SEGMENT_FIELD(FS),
229 VMX_SEGMENT_FIELD(GS),
230 VMX_SEGMENT_FIELD(SS),
231 VMX_SEGMENT_FIELD(TR),
232 VMX_SEGMENT_FIELD(LDTR),
235 static u64 host_efer;
237 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
240 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
241 * away by decrementing the array size.
243 static const u32 vmx_msr_index[] = {
245 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
247 MSR_EFER, MSR_TSC_AUX, MSR_K6_STAR,
249 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
251 static inline bool is_page_fault(u32 intr_info)
253 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
254 INTR_INFO_VALID_MASK)) ==
255 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
258 static inline bool is_no_device(u32 intr_info)
260 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
261 INTR_INFO_VALID_MASK)) ==
262 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
265 static inline bool is_invalid_opcode(u32 intr_info)
267 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
268 INTR_INFO_VALID_MASK)) ==
269 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
272 static inline bool is_external_interrupt(u32 intr_info)
274 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
275 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
278 static inline bool is_machine_check(u32 intr_info)
280 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
281 INTR_INFO_VALID_MASK)) ==
282 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
285 static inline bool cpu_has_vmx_msr_bitmap(void)
287 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
290 static inline bool cpu_has_vmx_tpr_shadow(void)
292 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
295 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
297 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
300 static inline bool cpu_has_secondary_exec_ctrls(void)
302 return vmcs_config.cpu_based_exec_ctrl &
303 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
306 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
308 return vmcs_config.cpu_based_2nd_exec_ctrl &
309 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
312 static inline bool cpu_has_vmx_flexpriority(void)
314 return cpu_has_vmx_tpr_shadow() &&
315 cpu_has_vmx_virtualize_apic_accesses();
318 static inline bool cpu_has_vmx_ept_execute_only(void)
320 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
323 static inline bool cpu_has_vmx_eptp_uncacheable(void)
325 return vmx_capability.ept & VMX_EPTP_UC_BIT;
328 static inline bool cpu_has_vmx_eptp_writeback(void)
330 return vmx_capability.ept & VMX_EPTP_WB_BIT;
333 static inline bool cpu_has_vmx_ept_2m_page(void)
335 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
338 static inline bool cpu_has_vmx_ept_1g_page(void)
340 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
343 static inline bool cpu_has_vmx_ept_4levels(void)
345 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
348 static inline bool cpu_has_vmx_invept_individual_addr(void)
350 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
353 static inline bool cpu_has_vmx_invept_context(void)
355 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
358 static inline bool cpu_has_vmx_invept_global(void)
360 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
363 static inline bool cpu_has_vmx_invvpid_single(void)
365 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
368 static inline bool cpu_has_vmx_invvpid_global(void)
370 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
373 static inline bool cpu_has_vmx_ept(void)
375 return vmcs_config.cpu_based_2nd_exec_ctrl &
376 SECONDARY_EXEC_ENABLE_EPT;
379 static inline bool cpu_has_vmx_unrestricted_guest(void)
381 return vmcs_config.cpu_based_2nd_exec_ctrl &
382 SECONDARY_EXEC_UNRESTRICTED_GUEST;
385 static inline bool cpu_has_vmx_ple(void)
387 return vmcs_config.cpu_based_2nd_exec_ctrl &
388 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
391 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
393 return flexpriority_enabled && irqchip_in_kernel(kvm);
396 static inline bool cpu_has_vmx_vpid(void)
398 return vmcs_config.cpu_based_2nd_exec_ctrl &
399 SECONDARY_EXEC_ENABLE_VPID;
402 static inline bool cpu_has_vmx_rdtscp(void)
404 return vmcs_config.cpu_based_2nd_exec_ctrl &
405 SECONDARY_EXEC_RDTSCP;
408 static inline bool cpu_has_virtual_nmis(void)
410 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
413 static inline bool report_flexpriority(void)
415 return flexpriority_enabled;
418 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
422 for (i = 0; i < vmx->nmsrs; ++i)
423 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
428 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
434 } operand = { vpid, 0, gva };
436 asm volatile (__ex(ASM_VMX_INVVPID)
437 /* CF==1 or ZF==1 --> rc = -1 */
439 : : "a"(&operand), "c"(ext) : "cc", "memory");
442 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
446 } operand = {eptp, gpa};
448 asm volatile (__ex(ASM_VMX_INVEPT)
449 /* CF==1 or ZF==1 --> rc = -1 */
450 "; ja 1f ; ud2 ; 1:\n"
451 : : "a" (&operand), "c" (ext) : "cc", "memory");
454 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
458 i = __find_msr_index(vmx, msr);
460 return &vmx->guest_msrs[i];
464 static void vmcs_clear(struct vmcs *vmcs)
466 u64 phys_addr = __pa(vmcs);
469 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
470 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
473 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
477 static void vmcs_load(struct vmcs *vmcs)
479 u64 phys_addr = __pa(vmcs);
482 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
483 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
486 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
490 static void __vcpu_clear(void *arg)
492 struct vcpu_vmx *vmx = arg;
493 int cpu = raw_smp_processor_id();
495 if (vmx->vcpu.cpu == cpu)
496 vmcs_clear(vmx->vmcs);
497 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
498 per_cpu(current_vmcs, cpu) = NULL;
499 rdtscll(vmx->vcpu.arch.host_tsc);
500 list_del(&vmx->local_vcpus_link);
505 static void vcpu_clear(struct vcpu_vmx *vmx)
507 if (vmx->vcpu.cpu == -1)
509 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
512 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
517 if (cpu_has_vmx_invvpid_single())
518 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
521 static inline void vpid_sync_vcpu_global(void)
523 if (cpu_has_vmx_invvpid_global())
524 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
527 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
529 if (cpu_has_vmx_invvpid_single())
530 vpid_sync_vcpu_single(vmx);
532 vpid_sync_vcpu_global();
535 static inline void ept_sync_global(void)
537 if (cpu_has_vmx_invept_global())
538 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
541 static inline void ept_sync_context(u64 eptp)
544 if (cpu_has_vmx_invept_context())
545 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
551 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
554 if (cpu_has_vmx_invept_individual_addr())
555 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
558 ept_sync_context(eptp);
562 static unsigned long vmcs_readl(unsigned long field)
566 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
567 : "=a"(value) : "d"(field) : "cc");
571 static u16 vmcs_read16(unsigned long field)
573 return vmcs_readl(field);
576 static u32 vmcs_read32(unsigned long field)
578 return vmcs_readl(field);
581 static u64 vmcs_read64(unsigned long field)
584 return vmcs_readl(field);
586 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
590 static noinline void vmwrite_error(unsigned long field, unsigned long value)
592 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
593 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
597 static void vmcs_writel(unsigned long field, unsigned long value)
601 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
602 : "=q"(error) : "a"(value), "d"(field) : "cc");
604 vmwrite_error(field, value);
607 static void vmcs_write16(unsigned long field, u16 value)
609 vmcs_writel(field, value);
612 static void vmcs_write32(unsigned long field, u32 value)
614 vmcs_writel(field, value);
617 static void vmcs_write64(unsigned long field, u64 value)
619 vmcs_writel(field, value);
620 #ifndef CONFIG_X86_64
622 vmcs_writel(field+1, value >> 32);
626 static void vmcs_clear_bits(unsigned long field, u32 mask)
628 vmcs_writel(field, vmcs_readl(field) & ~mask);
631 static void vmcs_set_bits(unsigned long field, u32 mask)
633 vmcs_writel(field, vmcs_readl(field) | mask);
636 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
640 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
641 (1u << NM_VECTOR) | (1u << DB_VECTOR);
642 if ((vcpu->guest_debug &
643 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
644 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
645 eb |= 1u << BP_VECTOR;
646 if (to_vmx(vcpu)->rmode.vm86_active)
649 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
650 if (vcpu->fpu_active)
651 eb &= ~(1u << NM_VECTOR);
652 vmcs_write32(EXCEPTION_BITMAP, eb);
655 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
658 struct msr_autoload *m = &vmx->msr_autoload;
660 for (i = 0; i < m->nr; ++i)
661 if (m->guest[i].index == msr)
667 m->guest[i] = m->guest[m->nr];
668 m->host[i] = m->host[m->nr];
669 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
670 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
673 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
674 u64 guest_val, u64 host_val)
677 struct msr_autoload *m = &vmx->msr_autoload;
679 for (i = 0; i < m->nr; ++i)
680 if (m->guest[i].index == msr)
685 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
686 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
689 m->guest[i].index = msr;
690 m->guest[i].value = guest_val;
691 m->host[i].index = msr;
692 m->host[i].value = host_val;
695 static void reload_tss(void)
698 * VT restores TR but not its size. Useless.
701 struct desc_struct *descs;
703 native_store_gdt(&gdt);
704 descs = (void *)gdt.address;
705 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
709 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
714 guest_efer = vmx->vcpu.arch.efer;
717 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
720 ignore_bits = EFER_NX | EFER_SCE;
722 ignore_bits |= EFER_LMA | EFER_LME;
723 /* SCE is meaningful only in long mode on Intel */
724 if (guest_efer & EFER_LMA)
725 ignore_bits &= ~(u64)EFER_SCE;
727 guest_efer &= ~ignore_bits;
728 guest_efer |= host_efer & ignore_bits;
729 vmx->guest_msrs[efer_offset].data = guest_efer;
730 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
732 clear_atomic_switch_msr(vmx, MSR_EFER);
733 /* On ept, can't emulate nx, and must switch nx atomically */
734 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
735 guest_efer = vmx->vcpu.arch.efer;
736 if (!(guest_efer & EFER_LMA))
737 guest_efer &= ~EFER_LME;
738 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
745 static unsigned long segment_base(u16 selector)
748 struct desc_struct *d;
749 unsigned long table_base;
752 if (!(selector & ~3))
755 native_store_gdt(&gdt);
756 table_base = gdt.address;
758 if (selector & 4) { /* from ldt */
759 u16 ldt_selector = kvm_read_ldt();
761 if (!(ldt_selector & ~3))
764 table_base = segment_base(ldt_selector);
766 d = (struct desc_struct *)(table_base + (selector & ~7));
767 v = get_desc_base(d);
769 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
770 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
775 static inline unsigned long kvm_read_tr_base(void)
778 asm("str %0" : "=g"(tr));
779 return segment_base(tr);
782 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
784 struct vcpu_vmx *vmx = to_vmx(vcpu);
787 if (vmx->host_state.loaded)
790 vmx->host_state.loaded = 1;
792 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
793 * allow segment selectors with cpl > 0 or ti == 1.
795 vmx->host_state.ldt_sel = kvm_read_ldt();
796 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
797 vmx->host_state.fs_sel = kvm_read_fs();
798 if (!(vmx->host_state.fs_sel & 7)) {
799 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
800 vmx->host_state.fs_reload_needed = 0;
802 vmcs_write16(HOST_FS_SELECTOR, 0);
803 vmx->host_state.fs_reload_needed = 1;
805 vmx->host_state.gs_sel = kvm_read_gs();
806 if (!(vmx->host_state.gs_sel & 7))
807 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
809 vmcs_write16(HOST_GS_SELECTOR, 0);
810 vmx->host_state.gs_ldt_reload_needed = 1;
814 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
815 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
817 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
818 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
822 if (is_long_mode(&vmx->vcpu)) {
823 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
824 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
827 for (i = 0; i < vmx->save_nmsrs; ++i)
828 kvm_set_shared_msr(vmx->guest_msrs[i].index,
829 vmx->guest_msrs[i].data,
830 vmx->guest_msrs[i].mask);
833 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
837 if (!vmx->host_state.loaded)
840 ++vmx->vcpu.stat.host_state_reload;
841 vmx->host_state.loaded = 0;
842 if (vmx->host_state.fs_reload_needed)
843 kvm_load_fs(vmx->host_state.fs_sel);
844 if (vmx->host_state.gs_ldt_reload_needed) {
845 kvm_load_ldt(vmx->host_state.ldt_sel);
847 * If we have to reload gs, we must take care to
848 * preserve our gs base.
850 local_irq_save(flags);
851 kvm_load_gs(vmx->host_state.gs_sel);
853 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
855 local_irq_restore(flags);
859 if (is_long_mode(&vmx->vcpu)) {
860 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
861 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
864 if (current_thread_info()->status & TS_USEDFPU)
868 static void vmx_load_host_state(struct vcpu_vmx *vmx)
871 __vmx_load_host_state(vmx);
876 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
877 * vcpu mutex is already taken.
879 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
881 struct vcpu_vmx *vmx = to_vmx(vcpu);
882 u64 tsc_this, delta, new_offset;
883 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
886 kvm_cpu_vmxon(phys_addr);
887 else if (vcpu->cpu != cpu)
890 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
891 per_cpu(current_vmcs, cpu) = vmx->vmcs;
892 vmcs_load(vmx->vmcs);
895 if (vcpu->cpu != cpu) {
897 unsigned long sysenter_esp;
899 kvm_migrate_timers(vcpu);
900 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
902 list_add(&vmx->local_vcpus_link,
903 &per_cpu(vcpus_on_cpu, cpu));
908 * Linux uses per-cpu TSS and GDT, so set these when switching
911 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
912 native_store_gdt(&dt);
913 vmcs_writel(HOST_GDTR_BASE, dt.address); /* 22.2.4 */
915 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
916 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
919 * Make sure the time stamp counter is monotonous.
922 if (tsc_this < vcpu->arch.host_tsc) {
923 delta = vcpu->arch.host_tsc - tsc_this;
924 new_offset = vmcs_read64(TSC_OFFSET) + delta;
925 vmcs_write64(TSC_OFFSET, new_offset);
930 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
932 __vmx_load_host_state(to_vmx(vcpu));
933 if (!vmm_exclusive) {
934 __vcpu_clear(to_vmx(vcpu));
939 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
943 if (vcpu->fpu_active)
945 vcpu->fpu_active = 1;
946 cr0 = vmcs_readl(GUEST_CR0);
947 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
948 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
949 vmcs_writel(GUEST_CR0, cr0);
950 update_exception_bitmap(vcpu);
951 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
952 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
955 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
957 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
959 vmx_decache_cr0_guest_bits(vcpu);
960 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
961 update_exception_bitmap(vcpu);
962 vcpu->arch.cr0_guest_owned_bits = 0;
963 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
964 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
967 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
969 unsigned long rflags, save_rflags;
971 rflags = vmcs_readl(GUEST_RFLAGS);
972 if (to_vmx(vcpu)->rmode.vm86_active) {
973 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
974 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
975 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
980 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
982 if (to_vmx(vcpu)->rmode.vm86_active) {
983 to_vmx(vcpu)->rmode.save_rflags = rflags;
984 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
986 vmcs_writel(GUEST_RFLAGS, rflags);
989 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
991 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
994 if (interruptibility & GUEST_INTR_STATE_STI)
995 ret |= KVM_X86_SHADOW_INT_STI;
996 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
997 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1002 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1004 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1005 u32 interruptibility = interruptibility_old;
1007 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1009 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1010 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1011 else if (mask & KVM_X86_SHADOW_INT_STI)
1012 interruptibility |= GUEST_INTR_STATE_STI;
1014 if ((interruptibility != interruptibility_old))
1015 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1018 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1022 rip = kvm_rip_read(vcpu);
1023 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1024 kvm_rip_write(vcpu, rip);
1026 /* skipping an emulated instruction also counts */
1027 vmx_set_interrupt_shadow(vcpu, 0);
1030 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1031 bool has_error_code, u32 error_code,
1034 struct vcpu_vmx *vmx = to_vmx(vcpu);
1035 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1037 if (has_error_code) {
1038 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1039 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1042 if (vmx->rmode.vm86_active) {
1043 vmx->rmode.irq.pending = true;
1044 vmx->rmode.irq.vector = nr;
1045 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
1046 if (kvm_exception_is_soft(nr))
1047 vmx->rmode.irq.rip +=
1048 vmx->vcpu.arch.event_exit_inst_len;
1049 intr_info |= INTR_TYPE_SOFT_INTR;
1050 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1051 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
1052 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
1056 if (kvm_exception_is_soft(nr)) {
1057 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1058 vmx->vcpu.arch.event_exit_inst_len);
1059 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1061 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1063 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1066 static bool vmx_rdtscp_supported(void)
1068 return cpu_has_vmx_rdtscp();
1072 * Swap MSR entry in host/guest MSR entry array.
1074 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1076 struct shared_msr_entry tmp;
1078 tmp = vmx->guest_msrs[to];
1079 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1080 vmx->guest_msrs[from] = tmp;
1084 * Set up the vmcs to automatically save and restore system
1085 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1086 * mode, as fiddling with msrs is very expensive.
1088 static void setup_msrs(struct vcpu_vmx *vmx)
1090 int save_nmsrs, index;
1091 unsigned long *msr_bitmap;
1093 vmx_load_host_state(vmx);
1095 #ifdef CONFIG_X86_64
1096 if (is_long_mode(&vmx->vcpu)) {
1097 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1099 move_msr_up(vmx, index, save_nmsrs++);
1100 index = __find_msr_index(vmx, MSR_LSTAR);
1102 move_msr_up(vmx, index, save_nmsrs++);
1103 index = __find_msr_index(vmx, MSR_CSTAR);
1105 move_msr_up(vmx, index, save_nmsrs++);
1106 index = __find_msr_index(vmx, MSR_TSC_AUX);
1107 if (index >= 0 && vmx->rdtscp_enabled)
1108 move_msr_up(vmx, index, save_nmsrs++);
1110 * MSR_K6_STAR is only needed on long mode guests, and only
1111 * if efer.sce is enabled.
1113 index = __find_msr_index(vmx, MSR_K6_STAR);
1114 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1115 move_msr_up(vmx, index, save_nmsrs++);
1118 index = __find_msr_index(vmx, MSR_EFER);
1119 if (index >= 0 && update_transition_efer(vmx, index))
1120 move_msr_up(vmx, index, save_nmsrs++);
1122 vmx->save_nmsrs = save_nmsrs;
1124 if (cpu_has_vmx_msr_bitmap()) {
1125 if (is_long_mode(&vmx->vcpu))
1126 msr_bitmap = vmx_msr_bitmap_longmode;
1128 msr_bitmap = vmx_msr_bitmap_legacy;
1130 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1135 * reads and returns guest's timestamp counter "register"
1136 * guest_tsc = host_tsc + tsc_offset -- 21.3
1138 static u64 guest_read_tsc(void)
1140 u64 host_tsc, tsc_offset;
1143 tsc_offset = vmcs_read64(TSC_OFFSET);
1144 return host_tsc + tsc_offset;
1148 * writes 'guest_tsc' into guest's timestamp counter "register"
1149 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
1151 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
1153 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
1157 * Reads an msr value (of 'msr_index') into 'pdata'.
1158 * Returns 0 on success, non-0 otherwise.
1159 * Assumes vcpu_load() was already called.
1161 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1164 struct shared_msr_entry *msr;
1167 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1171 switch (msr_index) {
1172 #ifdef CONFIG_X86_64
1174 data = vmcs_readl(GUEST_FS_BASE);
1177 data = vmcs_readl(GUEST_GS_BASE);
1179 case MSR_KERNEL_GS_BASE:
1180 vmx_load_host_state(to_vmx(vcpu));
1181 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1185 return kvm_get_msr_common(vcpu, msr_index, pdata);
1187 data = guest_read_tsc();
1189 case MSR_IA32_SYSENTER_CS:
1190 data = vmcs_read32(GUEST_SYSENTER_CS);
1192 case MSR_IA32_SYSENTER_EIP:
1193 data = vmcs_readl(GUEST_SYSENTER_EIP);
1195 case MSR_IA32_SYSENTER_ESP:
1196 data = vmcs_readl(GUEST_SYSENTER_ESP);
1199 if (!to_vmx(vcpu)->rdtscp_enabled)
1201 /* Otherwise falls through */
1203 vmx_load_host_state(to_vmx(vcpu));
1204 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1206 vmx_load_host_state(to_vmx(vcpu));
1210 return kvm_get_msr_common(vcpu, msr_index, pdata);
1218 * Writes msr value into into the appropriate "register".
1219 * Returns 0 on success, non-0 otherwise.
1220 * Assumes vcpu_load() was already called.
1222 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1224 struct vcpu_vmx *vmx = to_vmx(vcpu);
1225 struct shared_msr_entry *msr;
1229 switch (msr_index) {
1231 vmx_load_host_state(vmx);
1232 ret = kvm_set_msr_common(vcpu, msr_index, data);
1234 #ifdef CONFIG_X86_64
1236 vmcs_writel(GUEST_FS_BASE, data);
1239 vmcs_writel(GUEST_GS_BASE, data);
1241 case MSR_KERNEL_GS_BASE:
1242 vmx_load_host_state(vmx);
1243 vmx->msr_guest_kernel_gs_base = data;
1246 case MSR_IA32_SYSENTER_CS:
1247 vmcs_write32(GUEST_SYSENTER_CS, data);
1249 case MSR_IA32_SYSENTER_EIP:
1250 vmcs_writel(GUEST_SYSENTER_EIP, data);
1252 case MSR_IA32_SYSENTER_ESP:
1253 vmcs_writel(GUEST_SYSENTER_ESP, data);
1257 guest_write_tsc(data, host_tsc);
1259 case MSR_IA32_CR_PAT:
1260 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1261 vmcs_write64(GUEST_IA32_PAT, data);
1262 vcpu->arch.pat = data;
1265 ret = kvm_set_msr_common(vcpu, msr_index, data);
1268 if (!vmx->rdtscp_enabled)
1270 /* Check reserved bit, higher 32 bits should be zero */
1271 if ((data >> 32) != 0)
1273 /* Otherwise falls through */
1275 msr = find_msr_entry(vmx, msr_index);
1277 vmx_load_host_state(vmx);
1281 ret = kvm_set_msr_common(vcpu, msr_index, data);
1287 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1289 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1292 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1295 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1297 case VCPU_EXREG_PDPTR:
1299 ept_save_pdptrs(vcpu);
1306 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1308 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1309 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1311 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1313 update_exception_bitmap(vcpu);
1316 static __init int cpu_has_kvm_support(void)
1318 return cpu_has_vmx();
1321 static __init int vmx_disabled_by_bios(void)
1325 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1326 if (msr & FEATURE_CONTROL_LOCKED) {
1327 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1330 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1331 && !tboot_enabled())
1336 /* locked but not enabled */
1339 static void kvm_cpu_vmxon(u64 addr)
1341 asm volatile (ASM_VMX_VMXON_RAX
1342 : : "a"(&addr), "m"(addr)
1346 static int hardware_enable(void *garbage)
1348 int cpu = raw_smp_processor_id();
1349 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1352 if (read_cr4() & X86_CR4_VMXE)
1355 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1356 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1358 test_bits = FEATURE_CONTROL_LOCKED;
1359 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1360 if (tboot_enabled())
1361 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1363 if ((old & test_bits) != test_bits) {
1364 /* enable and lock */
1365 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1367 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1369 if (vmm_exclusive) {
1370 kvm_cpu_vmxon(phys_addr);
1377 static void vmclear_local_vcpus(void)
1379 int cpu = raw_smp_processor_id();
1380 struct vcpu_vmx *vmx, *n;
1382 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1388 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1391 static void kvm_cpu_vmxoff(void)
1393 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1396 static void hardware_disable(void *garbage)
1398 if (vmm_exclusive) {
1399 vmclear_local_vcpus();
1402 write_cr4(read_cr4() & ~X86_CR4_VMXE);
1405 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1406 u32 msr, u32 *result)
1408 u32 vmx_msr_low, vmx_msr_high;
1409 u32 ctl = ctl_min | ctl_opt;
1411 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1413 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1414 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1416 /* Ensure minimum (required) set of control bits are supported. */
1424 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1426 u32 vmx_msr_low, vmx_msr_high;
1427 u32 min, opt, min2, opt2;
1428 u32 _pin_based_exec_control = 0;
1429 u32 _cpu_based_exec_control = 0;
1430 u32 _cpu_based_2nd_exec_control = 0;
1431 u32 _vmexit_control = 0;
1432 u32 _vmentry_control = 0;
1434 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1435 opt = PIN_BASED_VIRTUAL_NMIS;
1436 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1437 &_pin_based_exec_control) < 0)
1440 min = CPU_BASED_HLT_EXITING |
1441 #ifdef CONFIG_X86_64
1442 CPU_BASED_CR8_LOAD_EXITING |
1443 CPU_BASED_CR8_STORE_EXITING |
1445 CPU_BASED_CR3_LOAD_EXITING |
1446 CPU_BASED_CR3_STORE_EXITING |
1447 CPU_BASED_USE_IO_BITMAPS |
1448 CPU_BASED_MOV_DR_EXITING |
1449 CPU_BASED_USE_TSC_OFFSETING |
1450 CPU_BASED_MWAIT_EXITING |
1451 CPU_BASED_MONITOR_EXITING |
1452 CPU_BASED_INVLPG_EXITING;
1453 opt = CPU_BASED_TPR_SHADOW |
1454 CPU_BASED_USE_MSR_BITMAPS |
1455 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1456 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1457 &_cpu_based_exec_control) < 0)
1459 #ifdef CONFIG_X86_64
1460 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1461 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1462 ~CPU_BASED_CR8_STORE_EXITING;
1464 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1466 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1467 SECONDARY_EXEC_WBINVD_EXITING |
1468 SECONDARY_EXEC_ENABLE_VPID |
1469 SECONDARY_EXEC_ENABLE_EPT |
1470 SECONDARY_EXEC_UNRESTRICTED_GUEST |
1471 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1472 SECONDARY_EXEC_RDTSCP;
1473 if (adjust_vmx_controls(min2, opt2,
1474 MSR_IA32_VMX_PROCBASED_CTLS2,
1475 &_cpu_based_2nd_exec_control) < 0)
1478 #ifndef CONFIG_X86_64
1479 if (!(_cpu_based_2nd_exec_control &
1480 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1481 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1483 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1484 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1486 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1487 CPU_BASED_CR3_STORE_EXITING |
1488 CPU_BASED_INVLPG_EXITING);
1489 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1490 vmx_capability.ept, vmx_capability.vpid);
1494 #ifdef CONFIG_X86_64
1495 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1497 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1498 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1499 &_vmexit_control) < 0)
1503 opt = VM_ENTRY_LOAD_IA32_PAT;
1504 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1505 &_vmentry_control) < 0)
1508 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1510 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1511 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1514 #ifdef CONFIG_X86_64
1515 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1516 if (vmx_msr_high & (1u<<16))
1520 /* Require Write-Back (WB) memory type for VMCS accesses. */
1521 if (((vmx_msr_high >> 18) & 15) != 6)
1524 vmcs_conf->size = vmx_msr_high & 0x1fff;
1525 vmcs_conf->order = get_order(vmcs_config.size);
1526 vmcs_conf->revision_id = vmx_msr_low;
1528 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1529 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1530 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1531 vmcs_conf->vmexit_ctrl = _vmexit_control;
1532 vmcs_conf->vmentry_ctrl = _vmentry_control;
1537 static struct vmcs *alloc_vmcs_cpu(int cpu)
1539 int node = cpu_to_node(cpu);
1543 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1546 vmcs = page_address(pages);
1547 memset(vmcs, 0, vmcs_config.size);
1548 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1552 static struct vmcs *alloc_vmcs(void)
1554 return alloc_vmcs_cpu(raw_smp_processor_id());
1557 static void free_vmcs(struct vmcs *vmcs)
1559 free_pages((unsigned long)vmcs, vmcs_config.order);
1562 static void free_kvm_area(void)
1566 for_each_possible_cpu(cpu) {
1567 free_vmcs(per_cpu(vmxarea, cpu));
1568 per_cpu(vmxarea, cpu) = NULL;
1572 static __init int alloc_kvm_area(void)
1576 for_each_possible_cpu(cpu) {
1579 vmcs = alloc_vmcs_cpu(cpu);
1585 per_cpu(vmxarea, cpu) = vmcs;
1590 static __init int hardware_setup(void)
1592 if (setup_vmcs_config(&vmcs_config) < 0)
1595 if (boot_cpu_has(X86_FEATURE_NX))
1596 kvm_enable_efer_bits(EFER_NX);
1598 if (!cpu_has_vmx_vpid())
1601 if (!cpu_has_vmx_ept() ||
1602 !cpu_has_vmx_ept_4levels()) {
1604 enable_unrestricted_guest = 0;
1607 if (!cpu_has_vmx_unrestricted_guest())
1608 enable_unrestricted_guest = 0;
1610 if (!cpu_has_vmx_flexpriority())
1611 flexpriority_enabled = 0;
1613 if (!cpu_has_vmx_tpr_shadow())
1614 kvm_x86_ops->update_cr8_intercept = NULL;
1616 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1617 kvm_disable_largepages();
1619 if (!cpu_has_vmx_ple())
1622 return alloc_kvm_area();
1625 static __exit void hardware_unsetup(void)
1630 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1632 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1634 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1635 vmcs_write16(sf->selector, save->selector);
1636 vmcs_writel(sf->base, save->base);
1637 vmcs_write32(sf->limit, save->limit);
1638 vmcs_write32(sf->ar_bytes, save->ar);
1640 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1642 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1646 static void enter_pmode(struct kvm_vcpu *vcpu)
1648 unsigned long flags;
1649 struct vcpu_vmx *vmx = to_vmx(vcpu);
1651 vmx->emulation_required = 1;
1652 vmx->rmode.vm86_active = 0;
1654 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1655 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1656 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1658 flags = vmcs_readl(GUEST_RFLAGS);
1659 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1660 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1661 vmcs_writel(GUEST_RFLAGS, flags);
1663 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1664 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1666 update_exception_bitmap(vcpu);
1668 if (emulate_invalid_guest_state)
1671 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1672 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1673 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1674 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1676 vmcs_write16(GUEST_SS_SELECTOR, 0);
1677 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1679 vmcs_write16(GUEST_CS_SELECTOR,
1680 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1681 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1684 static gva_t rmode_tss_base(struct kvm *kvm)
1686 if (!kvm->arch.tss_addr) {
1687 struct kvm_memslots *slots;
1690 slots = kvm_memslots(kvm);
1691 base_gfn = kvm->memslots->memslots[0].base_gfn +
1692 kvm->memslots->memslots[0].npages - 3;
1693 return base_gfn << PAGE_SHIFT;
1695 return kvm->arch.tss_addr;
1698 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1700 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1702 save->selector = vmcs_read16(sf->selector);
1703 save->base = vmcs_readl(sf->base);
1704 save->limit = vmcs_read32(sf->limit);
1705 save->ar = vmcs_read32(sf->ar_bytes);
1706 vmcs_write16(sf->selector, save->base >> 4);
1707 vmcs_write32(sf->base, save->base & 0xfffff);
1708 vmcs_write32(sf->limit, 0xffff);
1709 vmcs_write32(sf->ar_bytes, 0xf3);
1712 static void enter_rmode(struct kvm_vcpu *vcpu)
1714 unsigned long flags;
1715 struct vcpu_vmx *vmx = to_vmx(vcpu);
1717 if (enable_unrestricted_guest)
1720 vmx->emulation_required = 1;
1721 vmx->rmode.vm86_active = 1;
1723 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1724 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1726 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1727 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1729 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1730 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1732 flags = vmcs_readl(GUEST_RFLAGS);
1733 vmx->rmode.save_rflags = flags;
1735 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1737 vmcs_writel(GUEST_RFLAGS, flags);
1738 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1739 update_exception_bitmap(vcpu);
1741 if (emulate_invalid_guest_state)
1742 goto continue_rmode;
1744 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1745 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1746 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1748 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1749 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1750 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1751 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1752 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1754 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1755 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1756 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1757 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1760 kvm_mmu_reset_context(vcpu);
1761 init_rmode(vcpu->kvm);
1764 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1766 struct vcpu_vmx *vmx = to_vmx(vcpu);
1767 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1773 * Force kernel_gs_base reloading before EFER changes, as control
1774 * of this msr depends on is_long_mode().
1776 vmx_load_host_state(to_vmx(vcpu));
1777 vcpu->arch.efer = efer;
1778 if (efer & EFER_LMA) {
1779 vmcs_write32(VM_ENTRY_CONTROLS,
1780 vmcs_read32(VM_ENTRY_CONTROLS) |
1781 VM_ENTRY_IA32E_MODE);
1784 vmcs_write32(VM_ENTRY_CONTROLS,
1785 vmcs_read32(VM_ENTRY_CONTROLS) &
1786 ~VM_ENTRY_IA32E_MODE);
1788 msr->data = efer & ~EFER_LME;
1793 #ifdef CONFIG_X86_64
1795 static void enter_lmode(struct kvm_vcpu *vcpu)
1799 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1800 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1801 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1803 vmcs_write32(GUEST_TR_AR_BYTES,
1804 (guest_tr_ar & ~AR_TYPE_MASK)
1805 | AR_TYPE_BUSY_64_TSS);
1807 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
1810 static void exit_lmode(struct kvm_vcpu *vcpu)
1812 vmcs_write32(VM_ENTRY_CONTROLS,
1813 vmcs_read32(VM_ENTRY_CONTROLS)
1814 & ~VM_ENTRY_IA32E_MODE);
1815 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
1820 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1822 vpid_sync_context(to_vmx(vcpu));
1824 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1827 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1829 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1831 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1832 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1835 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1837 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1839 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1840 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
1843 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1845 if (!test_bit(VCPU_EXREG_PDPTR,
1846 (unsigned long *)&vcpu->arch.regs_dirty))
1849 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1850 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1851 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1852 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1853 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1857 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1859 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1860 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1861 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1862 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1863 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1866 __set_bit(VCPU_EXREG_PDPTR,
1867 (unsigned long *)&vcpu->arch.regs_avail);
1868 __set_bit(VCPU_EXREG_PDPTR,
1869 (unsigned long *)&vcpu->arch.regs_dirty);
1872 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1874 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1876 struct kvm_vcpu *vcpu)
1878 if (!(cr0 & X86_CR0_PG)) {
1879 /* From paging/starting to nonpaging */
1880 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1881 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1882 (CPU_BASED_CR3_LOAD_EXITING |
1883 CPU_BASED_CR3_STORE_EXITING));
1884 vcpu->arch.cr0 = cr0;
1885 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1886 } else if (!is_paging(vcpu)) {
1887 /* From nonpaging to paging */
1888 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1889 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1890 ~(CPU_BASED_CR3_LOAD_EXITING |
1891 CPU_BASED_CR3_STORE_EXITING));
1892 vcpu->arch.cr0 = cr0;
1893 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1896 if (!(cr0 & X86_CR0_WP))
1897 *hw_cr0 &= ~X86_CR0_WP;
1900 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1902 struct vcpu_vmx *vmx = to_vmx(vcpu);
1903 unsigned long hw_cr0;
1905 if (enable_unrestricted_guest)
1906 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1907 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1909 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1911 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1914 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1917 #ifdef CONFIG_X86_64
1918 if (vcpu->arch.efer & EFER_LME) {
1919 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1921 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1927 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1929 if (!vcpu->fpu_active)
1930 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
1932 vmcs_writel(CR0_READ_SHADOW, cr0);
1933 vmcs_writel(GUEST_CR0, hw_cr0);
1934 vcpu->arch.cr0 = cr0;
1937 static u64 construct_eptp(unsigned long root_hpa)
1941 /* TODO write the value reading from MSR */
1942 eptp = VMX_EPT_DEFAULT_MT |
1943 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1944 eptp |= (root_hpa & PAGE_MASK);
1949 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1951 unsigned long guest_cr3;
1956 eptp = construct_eptp(cr3);
1957 vmcs_write64(EPT_POINTER, eptp);
1958 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1959 vcpu->kvm->arch.ept_identity_map_addr;
1960 ept_load_pdptrs(vcpu);
1963 vmx_flush_tlb(vcpu);
1964 vmcs_writel(GUEST_CR3, guest_cr3);
1967 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1969 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1970 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1972 vcpu->arch.cr4 = cr4;
1974 if (!is_paging(vcpu)) {
1975 hw_cr4 &= ~X86_CR4_PAE;
1976 hw_cr4 |= X86_CR4_PSE;
1977 } else if (!(cr4 & X86_CR4_PAE)) {
1978 hw_cr4 &= ~X86_CR4_PAE;
1982 vmcs_writel(CR4_READ_SHADOW, cr4);
1983 vmcs_writel(GUEST_CR4, hw_cr4);
1986 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1988 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1990 return vmcs_readl(sf->base);
1993 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1994 struct kvm_segment *var, int seg)
1996 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1999 var->base = vmcs_readl(sf->base);
2000 var->limit = vmcs_read32(sf->limit);
2001 var->selector = vmcs_read16(sf->selector);
2002 ar = vmcs_read32(sf->ar_bytes);
2003 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
2005 var->type = ar & 15;
2006 var->s = (ar >> 4) & 1;
2007 var->dpl = (ar >> 5) & 3;
2008 var->present = (ar >> 7) & 1;
2009 var->avl = (ar >> 12) & 1;
2010 var->l = (ar >> 13) & 1;
2011 var->db = (ar >> 14) & 1;
2012 var->g = (ar >> 15) & 1;
2013 var->unusable = (ar >> 16) & 1;
2016 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2018 if (!is_protmode(vcpu))
2021 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
2024 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2027 static u32 vmx_segment_access_rights(struct kvm_segment *var)
2034 ar = var->type & 15;
2035 ar |= (var->s & 1) << 4;
2036 ar |= (var->dpl & 3) << 5;
2037 ar |= (var->present & 1) << 7;
2038 ar |= (var->avl & 1) << 12;
2039 ar |= (var->l & 1) << 13;
2040 ar |= (var->db & 1) << 14;
2041 ar |= (var->g & 1) << 15;
2043 if (ar == 0) /* a 0 value means unusable */
2044 ar = AR_UNUSABLE_MASK;
2049 static void vmx_set_segment(struct kvm_vcpu *vcpu,
2050 struct kvm_segment *var, int seg)
2052 struct vcpu_vmx *vmx = to_vmx(vcpu);
2053 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2056 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2057 vmx->rmode.tr.selector = var->selector;
2058 vmx->rmode.tr.base = var->base;
2059 vmx->rmode.tr.limit = var->limit;
2060 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
2063 vmcs_writel(sf->base, var->base);
2064 vmcs_write32(sf->limit, var->limit);
2065 vmcs_write16(sf->selector, var->selector);
2066 if (vmx->rmode.vm86_active && var->s) {
2068 * Hack real-mode segments into vm86 compatibility.
2070 if (var->base == 0xffff0000 && var->selector == 0xf000)
2071 vmcs_writel(sf->base, 0xf0000);
2074 ar = vmx_segment_access_rights(var);
2077 * Fix the "Accessed" bit in AR field of segment registers for older
2079 * IA32 arch specifies that at the time of processor reset the
2080 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2081 * is setting it to 0 in the usedland code. This causes invalid guest
2082 * state vmexit when "unrestricted guest" mode is turned on.
2083 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2084 * tree. Newer qemu binaries with that qemu fix would not need this
2087 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2088 ar |= 0x1; /* Accessed */
2090 vmcs_write32(sf->ar_bytes, ar);
2093 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2095 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2097 *db = (ar >> 14) & 1;
2098 *l = (ar >> 13) & 1;
2101 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2103 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2104 dt->address = vmcs_readl(GUEST_IDTR_BASE);
2107 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2109 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2110 vmcs_writel(GUEST_IDTR_BASE, dt->address);
2113 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2115 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2116 dt->address = vmcs_readl(GUEST_GDTR_BASE);
2119 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2121 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2122 vmcs_writel(GUEST_GDTR_BASE, dt->address);
2125 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2127 struct kvm_segment var;
2130 vmx_get_segment(vcpu, &var, seg);
2131 ar = vmx_segment_access_rights(&var);
2133 if (var.base != (var.selector << 4))
2135 if (var.limit != 0xffff)
2143 static bool code_segment_valid(struct kvm_vcpu *vcpu)
2145 struct kvm_segment cs;
2146 unsigned int cs_rpl;
2148 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2149 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2153 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2157 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
2158 if (cs.dpl > cs_rpl)
2161 if (cs.dpl != cs_rpl)
2167 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2171 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2173 struct kvm_segment ss;
2174 unsigned int ss_rpl;
2176 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2177 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2181 if (ss.type != 3 && ss.type != 7)
2185 if (ss.dpl != ss_rpl) /* DPL != RPL */
2193 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2195 struct kvm_segment var;
2198 vmx_get_segment(vcpu, &var, seg);
2199 rpl = var.selector & SELECTOR_RPL_MASK;
2207 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2208 if (var.dpl < rpl) /* DPL < RPL */
2212 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2218 static bool tr_valid(struct kvm_vcpu *vcpu)
2220 struct kvm_segment tr;
2222 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2226 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2228 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2236 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2238 struct kvm_segment ldtr;
2240 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2244 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2254 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2256 struct kvm_segment cs, ss;
2258 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2259 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2261 return ((cs.selector & SELECTOR_RPL_MASK) ==
2262 (ss.selector & SELECTOR_RPL_MASK));
2266 * Check if guest state is valid. Returns true if valid, false if
2268 * We assume that registers are always usable
2270 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2272 /* real mode guest state checks */
2273 if (!is_protmode(vcpu)) {
2274 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2276 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2278 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2280 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2282 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2284 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2287 /* protected mode guest state checks */
2288 if (!cs_ss_rpl_check(vcpu))
2290 if (!code_segment_valid(vcpu))
2292 if (!stack_segment_valid(vcpu))
2294 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2296 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2298 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2300 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2302 if (!tr_valid(vcpu))
2304 if (!ldtr_valid(vcpu))
2308 * - Add checks on RIP
2309 * - Add checks on RFLAGS
2315 static int init_rmode_tss(struct kvm *kvm)
2317 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2322 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2325 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2326 r = kvm_write_guest_page(kvm, fn++, &data,
2327 TSS_IOPB_BASE_OFFSET, sizeof(u16));
2330 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2333 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2337 r = kvm_write_guest_page(kvm, fn, &data,
2338 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2348 static int init_rmode_identity_map(struct kvm *kvm)
2351 pfn_t identity_map_pfn;
2356 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2357 printk(KERN_ERR "EPT: identity-mapping pagetable "
2358 "haven't been allocated!\n");
2361 if (likely(kvm->arch.ept_identity_pagetable_done))
2364 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2365 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2368 /* Set up identity-mapping pagetable for EPT in real mode */
2369 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2370 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2371 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2372 r = kvm_write_guest_page(kvm, identity_map_pfn,
2373 &tmp, i * sizeof(tmp), sizeof(tmp));
2377 kvm->arch.ept_identity_pagetable_done = true;
2383 static void seg_setup(int seg)
2385 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2388 vmcs_write16(sf->selector, 0);
2389 vmcs_writel(sf->base, 0);
2390 vmcs_write32(sf->limit, 0xffff);
2391 if (enable_unrestricted_guest) {
2393 if (seg == VCPU_SREG_CS)
2394 ar |= 0x08; /* code segment */
2398 vmcs_write32(sf->ar_bytes, ar);
2401 static int alloc_apic_access_page(struct kvm *kvm)
2403 struct kvm_userspace_memory_region kvm_userspace_mem;
2406 mutex_lock(&kvm->slots_lock);
2407 if (kvm->arch.apic_access_page)
2409 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2410 kvm_userspace_mem.flags = 0;
2411 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2412 kvm_userspace_mem.memory_size = PAGE_SIZE;
2413 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2417 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2419 mutex_unlock(&kvm->slots_lock);
2423 static int alloc_identity_pagetable(struct kvm *kvm)
2425 struct kvm_userspace_memory_region kvm_userspace_mem;
2428 mutex_lock(&kvm->slots_lock);
2429 if (kvm->arch.ept_identity_pagetable)
2431 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2432 kvm_userspace_mem.flags = 0;
2433 kvm_userspace_mem.guest_phys_addr =
2434 kvm->arch.ept_identity_map_addr;
2435 kvm_userspace_mem.memory_size = PAGE_SIZE;
2436 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2440 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2441 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2443 mutex_unlock(&kvm->slots_lock);
2447 static void allocate_vpid(struct vcpu_vmx *vmx)
2454 spin_lock(&vmx_vpid_lock);
2455 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2456 if (vpid < VMX_NR_VPIDS) {
2458 __set_bit(vpid, vmx_vpid_bitmap);
2460 spin_unlock(&vmx_vpid_lock);
2463 static void free_vpid(struct vcpu_vmx *vmx)
2467 spin_lock(&vmx_vpid_lock);
2469 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2470 spin_unlock(&vmx_vpid_lock);
2473 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2475 int f = sizeof(unsigned long);
2477 if (!cpu_has_vmx_msr_bitmap())
2481 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2482 * have the write-low and read-high bitmap offsets the wrong way round.
2483 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2485 if (msr <= 0x1fff) {
2486 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2487 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2488 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2490 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2491 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2495 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2498 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2499 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2503 * Sets up the vmcs for emulated real mode.
2505 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2507 u32 host_sysenter_cs, msr_low, msr_high;
2509 u64 host_pat, tsc_this, tsc_base;
2513 unsigned long kvm_vmx_return;
2517 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2518 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2520 if (cpu_has_vmx_msr_bitmap())
2521 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2523 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2526 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2527 vmcs_config.pin_based_exec_ctrl);
2529 exec_control = vmcs_config.cpu_based_exec_ctrl;
2530 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2531 exec_control &= ~CPU_BASED_TPR_SHADOW;
2532 #ifdef CONFIG_X86_64
2533 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2534 CPU_BASED_CR8_LOAD_EXITING;
2538 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2539 CPU_BASED_CR3_LOAD_EXITING |
2540 CPU_BASED_INVLPG_EXITING;
2541 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2543 if (cpu_has_secondary_exec_ctrls()) {
2544 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2545 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2547 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2549 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2551 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2552 enable_unrestricted_guest = 0;
2554 if (!enable_unrestricted_guest)
2555 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2557 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2558 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2562 vmcs_write32(PLE_GAP, ple_gap);
2563 vmcs_write32(PLE_WINDOW, ple_window);
2566 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2567 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2568 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2570 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
2571 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2572 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2574 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2575 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2576 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2577 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2578 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
2579 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2580 #ifdef CONFIG_X86_64
2581 rdmsrl(MSR_FS_BASE, a);
2582 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2583 rdmsrl(MSR_GS_BASE, a);
2584 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2586 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2587 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2590 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2592 native_store_idt(&dt);
2593 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
2595 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2596 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2597 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2598 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2599 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2600 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2601 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
2603 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2604 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2605 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2606 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2607 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2608 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2610 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2611 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2612 host_pat = msr_low | ((u64) msr_high << 32);
2613 vmcs_write64(HOST_IA32_PAT, host_pat);
2615 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2616 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2617 host_pat = msr_low | ((u64) msr_high << 32);
2618 /* Write the default value follow host pat */
2619 vmcs_write64(GUEST_IA32_PAT, host_pat);
2620 /* Keep arch.pat sync with GUEST_IA32_PAT */
2621 vmx->vcpu.arch.pat = host_pat;
2624 for (i = 0; i < NR_VMX_MSR; ++i) {
2625 u32 index = vmx_msr_index[i];
2626 u32 data_low, data_high;
2629 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2631 if (wrmsr_safe(index, data_low, data_high) < 0)
2633 vmx->guest_msrs[j].index = i;
2634 vmx->guest_msrs[j].data = 0;
2635 vmx->guest_msrs[j].mask = -1ull;
2639 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2641 /* 22.2.1, 20.8.1 */
2642 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2644 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2645 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
2647 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
2648 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
2650 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2652 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2653 tsc_base = tsc_this;
2655 guest_write_tsc(0, tsc_base);
2660 static int init_rmode(struct kvm *kvm)
2664 idx = srcu_read_lock(&kvm->srcu);
2665 if (!init_rmode_tss(kvm))
2667 if (!init_rmode_identity_map(kvm))
2672 srcu_read_unlock(&kvm->srcu, idx);
2676 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2678 struct vcpu_vmx *vmx = to_vmx(vcpu);
2682 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2683 if (!init_rmode(vmx->vcpu.kvm)) {
2688 vmx->rmode.vm86_active = 0;
2690 vmx->soft_vnmi_blocked = 0;
2692 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2693 kvm_set_cr8(&vmx->vcpu, 0);
2694 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2695 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2696 msr |= MSR_IA32_APICBASE_BSP;
2697 kvm_set_apic_base(&vmx->vcpu, msr);
2699 ret = fx_init(&vmx->vcpu);
2703 seg_setup(VCPU_SREG_CS);
2705 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2706 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2708 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2709 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2710 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2712 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2713 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2716 seg_setup(VCPU_SREG_DS);
2717 seg_setup(VCPU_SREG_ES);
2718 seg_setup(VCPU_SREG_FS);
2719 seg_setup(VCPU_SREG_GS);
2720 seg_setup(VCPU_SREG_SS);
2722 vmcs_write16(GUEST_TR_SELECTOR, 0);
2723 vmcs_writel(GUEST_TR_BASE, 0);
2724 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2725 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2727 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2728 vmcs_writel(GUEST_LDTR_BASE, 0);
2729 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2730 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2732 vmcs_write32(GUEST_SYSENTER_CS, 0);
2733 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2734 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2736 vmcs_writel(GUEST_RFLAGS, 0x02);
2737 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2738 kvm_rip_write(vcpu, 0xfff0);
2740 kvm_rip_write(vcpu, 0);
2741 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2743 vmcs_writel(GUEST_DR7, 0x400);
2745 vmcs_writel(GUEST_GDTR_BASE, 0);
2746 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2748 vmcs_writel(GUEST_IDTR_BASE, 0);
2749 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2751 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2752 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2753 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2755 /* Special registers */
2756 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2760 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2762 if (cpu_has_vmx_tpr_shadow()) {
2763 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2764 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2765 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2766 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2767 vmcs_write32(TPR_THRESHOLD, 0);
2770 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2771 vmcs_write64(APIC_ACCESS_ADDR,
2772 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2775 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2777 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2778 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
2779 vmx_set_cr4(&vmx->vcpu, 0);
2780 vmx_set_efer(&vmx->vcpu, 0);
2781 vmx_fpu_activate(&vmx->vcpu);
2782 update_exception_bitmap(&vmx->vcpu);
2784 vpid_sync_context(vmx);
2788 /* HACK: Don't enable emulation on guest boot/reset */
2789 vmx->emulation_required = 0;
2795 static void enable_irq_window(struct kvm_vcpu *vcpu)
2797 u32 cpu_based_vm_exec_control;
2799 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2800 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2801 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2804 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2806 u32 cpu_based_vm_exec_control;
2808 if (!cpu_has_virtual_nmis()) {
2809 enable_irq_window(vcpu);
2813 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2814 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2815 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2818 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2820 struct vcpu_vmx *vmx = to_vmx(vcpu);
2822 int irq = vcpu->arch.interrupt.nr;
2824 trace_kvm_inj_virq(irq);
2826 ++vcpu->stat.irq_injections;
2827 if (vmx->rmode.vm86_active) {
2828 vmx->rmode.irq.pending = true;
2829 vmx->rmode.irq.vector = irq;
2830 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2831 if (vcpu->arch.interrupt.soft)
2832 vmx->rmode.irq.rip +=
2833 vmx->vcpu.arch.event_exit_inst_len;
2834 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2835 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2836 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2837 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2840 intr = irq | INTR_INFO_VALID_MASK;
2841 if (vcpu->arch.interrupt.soft) {
2842 intr |= INTR_TYPE_SOFT_INTR;
2843 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2844 vmx->vcpu.arch.event_exit_inst_len);
2846 intr |= INTR_TYPE_EXT_INTR;
2847 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2850 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2852 struct vcpu_vmx *vmx = to_vmx(vcpu);
2854 if (!cpu_has_virtual_nmis()) {
2856 * Tracking the NMI-blocked state in software is built upon
2857 * finding the next open IRQ window. This, in turn, depends on
2858 * well-behaving guests: They have to keep IRQs disabled at
2859 * least as long as the NMI handler runs. Otherwise we may
2860 * cause NMI nesting, maybe breaking the guest. But as this is
2861 * highly unlikely, we can live with the residual risk.
2863 vmx->soft_vnmi_blocked = 1;
2864 vmx->vnmi_blocked_time = 0;
2867 ++vcpu->stat.nmi_injections;
2868 if (vmx->rmode.vm86_active) {
2869 vmx->rmode.irq.pending = true;
2870 vmx->rmode.irq.vector = NMI_VECTOR;
2871 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2872 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2873 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2874 INTR_INFO_VALID_MASK);
2875 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2876 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2879 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2880 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2883 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2885 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2888 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2889 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_NMI));
2892 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2894 if (!cpu_has_virtual_nmis())
2895 return to_vmx(vcpu)->soft_vnmi_blocked;
2896 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
2899 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2901 struct vcpu_vmx *vmx = to_vmx(vcpu);
2903 if (!cpu_has_virtual_nmis()) {
2904 if (vmx->soft_vnmi_blocked != masked) {
2905 vmx->soft_vnmi_blocked = masked;
2906 vmx->vnmi_blocked_time = 0;
2910 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2911 GUEST_INTR_STATE_NMI);
2913 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2914 GUEST_INTR_STATE_NMI);
2918 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2920 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2921 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2922 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2925 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2928 struct kvm_userspace_memory_region tss_mem = {
2929 .slot = TSS_PRIVATE_MEMSLOT,
2930 .guest_phys_addr = addr,
2931 .memory_size = PAGE_SIZE * 3,
2935 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2938 kvm->arch.tss_addr = addr;
2942 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2943 int vec, u32 err_code)
2946 * Instruction with address size override prefix opcode 0x67
2947 * Cause the #SS fault with 0 error code in VM86 mode.
2949 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2950 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
2953 * Forward all other exceptions that are valid in real mode.
2954 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2955 * the required debugging infrastructure rework.
2959 if (vcpu->guest_debug &
2960 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2962 kvm_queue_exception(vcpu, vec);
2966 * Update instruction length as we may reinject the exception
2967 * from user space while in guest debugging mode.
2969 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
2970 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2971 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2982 kvm_queue_exception(vcpu, vec);
2989 * Trigger machine check on the host. We assume all the MSRs are already set up
2990 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2991 * We pass a fake environment to the machine check handler because we want
2992 * the guest to be always treated like user space, no matter what context
2993 * it used internally.
2995 static void kvm_machine_check(void)
2997 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2998 struct pt_regs regs = {
2999 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
3000 .flags = X86_EFLAGS_IF,
3003 do_machine_check(®s, 0);
3007 static int handle_machine_check(struct kvm_vcpu *vcpu)
3009 /* already handled by vcpu_run */
3013 static int handle_exception(struct kvm_vcpu *vcpu)
3015 struct vcpu_vmx *vmx = to_vmx(vcpu);
3016 struct kvm_run *kvm_run = vcpu->run;
3017 u32 intr_info, ex_no, error_code;
3018 unsigned long cr2, rip, dr6;
3020 enum emulation_result er;
3022 vect_info = vmx->idt_vectoring_info;
3023 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3025 if (is_machine_check(intr_info))
3026 return handle_machine_check(vcpu);
3028 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
3029 !is_page_fault(intr_info)) {
3030 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3031 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3032 vcpu->run->internal.ndata = 2;
3033 vcpu->run->internal.data[0] = vect_info;
3034 vcpu->run->internal.data[1] = intr_info;
3038 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
3039 return 1; /* already handled by vmx_vcpu_run() */
3041 if (is_no_device(intr_info)) {
3042 vmx_fpu_activate(vcpu);
3046 if (is_invalid_opcode(intr_info)) {
3047 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
3048 if (er != EMULATE_DONE)
3049 kvm_queue_exception(vcpu, UD_VECTOR);
3054 rip = kvm_rip_read(vcpu);
3055 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
3056 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3057 if (is_page_fault(intr_info)) {
3058 /* EPT won't cause page fault directly */
3061 cr2 = vmcs_readl(EXIT_QUALIFICATION);
3062 trace_kvm_page_fault(cr2, error_code);
3064 if (kvm_event_needs_reinjection(vcpu))
3065 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3066 return kvm_mmu_page_fault(vcpu, cr2, error_code);
3069 if (vmx->rmode.vm86_active &&
3070 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
3072 if (vcpu->arch.halt_request) {
3073 vcpu->arch.halt_request = 0;
3074 return kvm_emulate_halt(vcpu);
3079 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
3082 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3083 if (!(vcpu->guest_debug &
3084 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3085 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3086 kvm_queue_exception(vcpu, DB_VECTOR);
3089 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3090 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3094 * Update instruction length as we may reinject #BP from
3095 * user space while in guest debugging mode. Reading it for
3096 * #DB as well causes no harm, it is not used in that case.
3098 vmx->vcpu.arch.event_exit_inst_len =
3099 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3100 kvm_run->exit_reason = KVM_EXIT_DEBUG;
3101 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3102 kvm_run->debug.arch.exception = ex_no;
3105 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3106 kvm_run->ex.exception = ex_no;
3107 kvm_run->ex.error_code = error_code;
3113 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
3115 ++vcpu->stat.irq_exits;
3119 static int handle_triple_fault(struct kvm_vcpu *vcpu)
3121 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
3125 static int handle_io(struct kvm_vcpu *vcpu)
3127 unsigned long exit_qualification;
3128 int size, in, string;
3131 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3132 string = (exit_qualification & 16) != 0;
3133 in = (exit_qualification & 8) != 0;
3135 ++vcpu->stat.io_exits;
3138 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
3140 port = exit_qualification >> 16;
3141 size = (exit_qualification & 7) + 1;
3142 skip_emulated_instruction(vcpu);
3144 return kvm_fast_pio_out(vcpu, size, port);
3148 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3151 * Patch in the VMCALL instruction:
3153 hypercall[0] = 0x0f;
3154 hypercall[1] = 0x01;
3155 hypercall[2] = 0xc1;
3158 static int handle_cr(struct kvm_vcpu *vcpu)
3160 unsigned long exit_qualification, val;
3164 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3165 cr = exit_qualification & 15;
3166 reg = (exit_qualification >> 8) & 15;
3167 switch ((exit_qualification >> 4) & 3) {
3168 case 0: /* mov to cr */
3169 val = kvm_register_read(vcpu, reg);
3170 trace_kvm_cr_write(cr, val);
3173 kvm_set_cr0(vcpu, val);
3174 skip_emulated_instruction(vcpu);
3177 kvm_set_cr3(vcpu, val);
3178 skip_emulated_instruction(vcpu);
3181 kvm_set_cr4(vcpu, val);
3182 skip_emulated_instruction(vcpu);
3185 u8 cr8_prev = kvm_get_cr8(vcpu);
3186 u8 cr8 = kvm_register_read(vcpu, reg);
3187 kvm_set_cr8(vcpu, cr8);
3188 skip_emulated_instruction(vcpu);
3189 if (irqchip_in_kernel(vcpu->kvm))
3191 if (cr8_prev <= cr8)
3193 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
3199 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
3200 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
3201 skip_emulated_instruction(vcpu);
3202 vmx_fpu_activate(vcpu);
3204 case 1: /*mov from cr*/
3207 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
3208 trace_kvm_cr_read(cr, vcpu->arch.cr3);
3209 skip_emulated_instruction(vcpu);
3212 val = kvm_get_cr8(vcpu);
3213 kvm_register_write(vcpu, reg, val);
3214 trace_kvm_cr_read(cr, val);
3215 skip_emulated_instruction(vcpu);
3220 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
3221 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
3222 kvm_lmsw(vcpu, val);
3224 skip_emulated_instruction(vcpu);
3229 vcpu->run->exit_reason = 0;
3230 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
3231 (int)(exit_qualification >> 4) & 3, cr);
3235 static int handle_dr(struct kvm_vcpu *vcpu)
3237 unsigned long exit_qualification;
3240 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3241 if (!kvm_require_cpl(vcpu, 0))
3243 dr = vmcs_readl(GUEST_DR7);
3246 * As the vm-exit takes precedence over the debug trap, we
3247 * need to emulate the latter, either for the host or the
3248 * guest debugging itself.
3250 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3251 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3252 vcpu->run->debug.arch.dr7 = dr;
3253 vcpu->run->debug.arch.pc =
3254 vmcs_readl(GUEST_CS_BASE) +
3255 vmcs_readl(GUEST_RIP);
3256 vcpu->run->debug.arch.exception = DB_VECTOR;
3257 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3260 vcpu->arch.dr7 &= ~DR7_GD;
3261 vcpu->arch.dr6 |= DR6_BD;
3262 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3263 kvm_queue_exception(vcpu, DB_VECTOR);
3268 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3269 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3270 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3271 if (exit_qualification & TYPE_MOV_FROM_DR) {
3273 if (!kvm_get_dr(vcpu, dr, &val))
3274 kvm_register_write(vcpu, reg, val);
3276 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
3277 skip_emulated_instruction(vcpu);
3281 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3283 vmcs_writel(GUEST_DR7, val);
3286 static int handle_cpuid(struct kvm_vcpu *vcpu)
3288 kvm_emulate_cpuid(vcpu);
3292 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3294 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3297 if (vmx_get_msr(vcpu, ecx, &data)) {
3298 trace_kvm_msr_read_ex(ecx);
3299 kvm_inject_gp(vcpu, 0);
3303 trace_kvm_msr_read(ecx, data);
3305 /* FIXME: handling of bits 32:63 of rax, rdx */
3306 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3307 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3308 skip_emulated_instruction(vcpu);
3312 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3314 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3315 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3316 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3318 if (vmx_set_msr(vcpu, ecx, data) != 0) {
3319 trace_kvm_msr_write_ex(ecx, data);
3320 kvm_inject_gp(vcpu, 0);
3324 trace_kvm_msr_write(ecx, data);
3325 skip_emulated_instruction(vcpu);
3329 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3334 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3336 u32 cpu_based_vm_exec_control;
3338 /* clear pending irq */
3339 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3340 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3341 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3343 ++vcpu->stat.irq_window_exits;
3346 * If the user space waits to inject interrupts, exit as soon as
3349 if (!irqchip_in_kernel(vcpu->kvm) &&
3350 vcpu->run->request_interrupt_window &&
3351 !kvm_cpu_has_interrupt(vcpu)) {
3352 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3358 static int handle_halt(struct kvm_vcpu *vcpu)
3360 skip_emulated_instruction(vcpu);
3361 return kvm_emulate_halt(vcpu);
3364 static int handle_vmcall(struct kvm_vcpu *vcpu)
3366 skip_emulated_instruction(vcpu);
3367 kvm_emulate_hypercall(vcpu);
3371 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3373 kvm_queue_exception(vcpu, UD_VECTOR);
3377 static int handle_invlpg(struct kvm_vcpu *vcpu)
3379 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3381 kvm_mmu_invlpg(vcpu, exit_qualification);
3382 skip_emulated_instruction(vcpu);
3386 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3388 skip_emulated_instruction(vcpu);
3389 /* TODO: Add support for VT-d/pass-through device */
3393 static int handle_apic_access(struct kvm_vcpu *vcpu)
3395 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
3398 static int handle_task_switch(struct kvm_vcpu *vcpu)
3400 struct vcpu_vmx *vmx = to_vmx(vcpu);
3401 unsigned long exit_qualification;
3402 bool has_error_code = false;
3405 int reason, type, idt_v;
3407 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3408 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3410 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3412 reason = (u32)exit_qualification >> 30;
3413 if (reason == TASK_SWITCH_GATE && idt_v) {
3415 case INTR_TYPE_NMI_INTR:
3416 vcpu->arch.nmi_injected = false;
3417 if (cpu_has_virtual_nmis())
3418 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3419 GUEST_INTR_STATE_NMI);
3421 case INTR_TYPE_EXT_INTR:
3422 case INTR_TYPE_SOFT_INTR:
3423 kvm_clear_interrupt_queue(vcpu);
3425 case INTR_TYPE_HARD_EXCEPTION:
3426 if (vmx->idt_vectoring_info &
3427 VECTORING_INFO_DELIVER_CODE_MASK) {
3428 has_error_code = true;
3430 vmcs_read32(IDT_VECTORING_ERROR_CODE);
3433 case INTR_TYPE_SOFT_EXCEPTION:
3434 kvm_clear_exception_queue(vcpu);
3440 tss_selector = exit_qualification;
3442 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3443 type != INTR_TYPE_EXT_INTR &&
3444 type != INTR_TYPE_NMI_INTR))
3445 skip_emulated_instruction(vcpu);
3447 if (kvm_task_switch(vcpu, tss_selector, reason,
3448 has_error_code, error_code) == EMULATE_FAIL) {
3449 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3450 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3451 vcpu->run->internal.ndata = 0;
3455 /* clear all local breakpoint enable flags */
3456 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3459 * TODO: What about debug traps on tss switch?
3460 * Are we supposed to inject them and update dr6?
3466 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3468 unsigned long exit_qualification;
3472 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3474 if (exit_qualification & (1 << 6)) {
3475 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3479 gla_validity = (exit_qualification >> 7) & 0x3;
3480 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3481 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3482 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3483 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3484 vmcs_readl(GUEST_LINEAR_ADDRESS));
3485 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3486 (long unsigned int)exit_qualification);
3487 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3488 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3492 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3493 trace_kvm_page_fault(gpa, exit_qualification);
3494 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3497 static u64 ept_rsvd_mask(u64 spte, int level)
3502 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3503 mask |= (1ULL << i);
3506 /* bits 7:3 reserved */
3508 else if (level == 2) {
3509 if (spte & (1ULL << 7))
3510 /* 2MB ref, bits 20:12 reserved */
3513 /* bits 6:3 reserved */
3520 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3523 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3525 /* 010b (write-only) */
3526 WARN_ON((spte & 0x7) == 0x2);
3528 /* 110b (write/execute) */
3529 WARN_ON((spte & 0x7) == 0x6);
3531 /* 100b (execute-only) and value not supported by logical processor */
3532 if (!cpu_has_vmx_ept_execute_only())
3533 WARN_ON((spte & 0x7) == 0x4);
3537 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3539 if (rsvd_bits != 0) {
3540 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3541 __func__, rsvd_bits);
3545 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3546 u64 ept_mem_type = (spte & 0x38) >> 3;
3548 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3549 ept_mem_type == 7) {
3550 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3551 __func__, ept_mem_type);
3558 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3564 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3566 printk(KERN_ERR "EPT: Misconfiguration.\n");
3567 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3569 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3571 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3572 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3574 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3575 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3580 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3582 u32 cpu_based_vm_exec_control;
3584 /* clear pending NMI */
3585 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3586 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3587 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3588 ++vcpu->stat.nmi_window_exits;
3593 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3595 struct vcpu_vmx *vmx = to_vmx(vcpu);
3596 enum emulation_result err = EMULATE_DONE;
3599 while (!guest_state_valid(vcpu)) {
3600 err = emulate_instruction(vcpu, 0, 0, 0);
3602 if (err == EMULATE_DO_MMIO) {
3607 if (err != EMULATE_DONE)
3610 if (signal_pending(current))
3616 vmx->emulation_required = 0;
3622 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3623 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3625 static int handle_pause(struct kvm_vcpu *vcpu)
3627 skip_emulated_instruction(vcpu);
3628 kvm_vcpu_on_spin(vcpu);
3633 static int handle_invalid_op(struct kvm_vcpu *vcpu)
3635 kvm_queue_exception(vcpu, UD_VECTOR);
3640 * The exit handlers return 1 if the exit was handled fully and guest execution
3641 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3642 * to be done to userspace and return 0.
3644 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3645 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3646 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
3647 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
3648 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
3649 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
3650 [EXIT_REASON_CR_ACCESS] = handle_cr,
3651 [EXIT_REASON_DR_ACCESS] = handle_dr,
3652 [EXIT_REASON_CPUID] = handle_cpuid,
3653 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3654 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3655 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3656 [EXIT_REASON_HLT] = handle_halt,
3657 [EXIT_REASON_INVLPG] = handle_invlpg,
3658 [EXIT_REASON_VMCALL] = handle_vmcall,
3659 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3660 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3661 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3662 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3663 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3664 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3665 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3666 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3667 [EXIT_REASON_VMON] = handle_vmx_insn,
3668 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3669 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
3670 [EXIT_REASON_WBINVD] = handle_wbinvd,
3671 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
3672 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
3673 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3674 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
3675 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
3676 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3677 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
3680 static const int kvm_vmx_max_exit_handlers =
3681 ARRAY_SIZE(kvm_vmx_exit_handlers);
3684 * The guest has exited. See if we can fix it or if we need userspace
3687 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3689 struct vcpu_vmx *vmx = to_vmx(vcpu);
3690 u32 exit_reason = vmx->exit_reason;
3691 u32 vectoring_info = vmx->idt_vectoring_info;
3693 trace_kvm_exit(exit_reason, vcpu);
3695 /* If guest state is invalid, start emulating */
3696 if (vmx->emulation_required && emulate_invalid_guest_state)
3697 return handle_invalid_guest_state(vcpu);
3699 /* Access CR3 don't cause VMExit in paging mode, so we need
3700 * to sync with guest real CR3. */
3701 if (enable_ept && is_paging(vcpu))
3702 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3704 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
3705 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3706 vcpu->run->fail_entry.hardware_entry_failure_reason
3711 if (unlikely(vmx->fail)) {
3712 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3713 vcpu->run->fail_entry.hardware_entry_failure_reason
3714 = vmcs_read32(VM_INSTRUCTION_ERROR);
3718 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3719 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3720 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3721 exit_reason != EXIT_REASON_TASK_SWITCH))
3722 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3723 "(0x%x) and exit reason is 0x%x\n",
3724 __func__, vectoring_info, exit_reason);
3726 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3727 if (vmx_interrupt_allowed(vcpu)) {
3728 vmx->soft_vnmi_blocked = 0;
3729 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3730 vcpu->arch.nmi_pending) {
3732 * This CPU don't support us in finding the end of an
3733 * NMI-blocked window if the guest runs with IRQs
3734 * disabled. So we pull the trigger after 1 s of
3735 * futile waiting, but inform the user about this.
3737 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3738 "state on VCPU %d after 1 s timeout\n",
3739 __func__, vcpu->vcpu_id);
3740 vmx->soft_vnmi_blocked = 0;
3744 if (exit_reason < kvm_vmx_max_exit_handlers
3745 && kvm_vmx_exit_handlers[exit_reason])
3746 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3748 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3749 vcpu->run->hw.hardware_exit_reason = exit_reason;
3754 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3756 if (irr == -1 || tpr < irr) {
3757 vmcs_write32(TPR_THRESHOLD, 0);
3761 vmcs_write32(TPR_THRESHOLD, irr);
3764 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3767 u32 idt_vectoring_info = vmx->idt_vectoring_info;
3771 bool idtv_info_valid;
3773 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3775 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3777 /* Handle machine checks before interrupts are enabled */
3778 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3779 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3780 && is_machine_check(exit_intr_info)))
3781 kvm_machine_check();
3783 /* We need to handle NMIs before interrupts are enabled */
3784 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3785 (exit_intr_info & INTR_INFO_VALID_MASK)) {
3786 kvm_before_handle_nmi(&vmx->vcpu);
3788 kvm_after_handle_nmi(&vmx->vcpu);
3791 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3793 if (cpu_has_virtual_nmis()) {
3794 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3795 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3797 * SDM 3: 27.7.1.2 (September 2008)
3798 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3799 * a guest IRET fault.
3800 * SDM 3: 23.2.2 (September 2008)
3801 * Bit 12 is undefined in any of the following cases:
3802 * If the VM exit sets the valid bit in the IDT-vectoring
3803 * information field.
3804 * If the VM exit is due to a double fault.
3806 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3807 vector != DF_VECTOR && !idtv_info_valid)
3808 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3809 GUEST_INTR_STATE_NMI);
3810 } else if (unlikely(vmx->soft_vnmi_blocked))
3811 vmx->vnmi_blocked_time +=
3812 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3814 vmx->vcpu.arch.nmi_injected = false;
3815 kvm_clear_exception_queue(&vmx->vcpu);
3816 kvm_clear_interrupt_queue(&vmx->vcpu);
3818 if (!idtv_info_valid)
3821 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3822 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3825 case INTR_TYPE_NMI_INTR:
3826 vmx->vcpu.arch.nmi_injected = true;
3828 * SDM 3: 27.7.1.2 (September 2008)
3829 * Clear bit "block by NMI" before VM entry if a NMI
3832 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3833 GUEST_INTR_STATE_NMI);
3835 case INTR_TYPE_SOFT_EXCEPTION:
3836 vmx->vcpu.arch.event_exit_inst_len =
3837 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3839 case INTR_TYPE_HARD_EXCEPTION:
3840 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3841 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3842 kvm_queue_exception_e(&vmx->vcpu, vector, err);
3844 kvm_queue_exception(&vmx->vcpu, vector);
3846 case INTR_TYPE_SOFT_INTR:
3847 vmx->vcpu.arch.event_exit_inst_len =
3848 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3850 case INTR_TYPE_EXT_INTR:
3851 kvm_queue_interrupt(&vmx->vcpu, vector,
3852 type == INTR_TYPE_SOFT_INTR);
3860 * Failure to inject an interrupt should give us the information
3861 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3862 * when fetching the interrupt redirection bitmap in the real-mode
3863 * tss, this doesn't happen. So we do it ourselves.
3865 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3867 vmx->rmode.irq.pending = 0;
3868 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3870 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3871 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3872 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3873 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3876 vmx->idt_vectoring_info =
3877 VECTORING_INFO_VALID_MASK
3878 | INTR_TYPE_EXT_INTR
3879 | vmx->rmode.irq.vector;
3882 #ifdef CONFIG_X86_64
3890 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
3892 struct vcpu_vmx *vmx = to_vmx(vcpu);
3894 /* Record the guest's net vcpu time for enforced NMI injections. */
3895 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3896 vmx->entry_time = ktime_get();
3898 /* Don't enter VMX if guest state is invalid, let the exit handler
3899 start emulation until we arrive back to a valid state */
3900 if (vmx->emulation_required && emulate_invalid_guest_state)
3903 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3904 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3905 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3906 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3908 /* When single-stepping over STI and MOV SS, we must clear the
3909 * corresponding interruptibility bits in the guest state. Otherwise
3910 * vmentry fails as it then expects bit 14 (BS) in pending debug
3911 * exceptions being set, but that's not correct for the guest debugging
3913 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3914 vmx_set_interrupt_shadow(vcpu, 0);
3917 /* Store host registers */
3918 "push %%"R"dx; push %%"R"bp;"
3920 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3922 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3923 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3925 /* Reload cr2 if changed */
3926 "mov %c[cr2](%0), %%"R"ax \n\t"
3927 "mov %%cr2, %%"R"dx \n\t"
3928 "cmp %%"R"ax, %%"R"dx \n\t"
3930 "mov %%"R"ax, %%cr2 \n\t"
3932 /* Check if vmlaunch of vmresume is needed */
3933 "cmpl $0, %c[launched](%0) \n\t"
3934 /* Load guest registers. Don't clobber flags. */
3935 "mov %c[rax](%0), %%"R"ax \n\t"
3936 "mov %c[rbx](%0), %%"R"bx \n\t"
3937 "mov %c[rdx](%0), %%"R"dx \n\t"
3938 "mov %c[rsi](%0), %%"R"si \n\t"
3939 "mov %c[rdi](%0), %%"R"di \n\t"
3940 "mov %c[rbp](%0), %%"R"bp \n\t"
3941 #ifdef CONFIG_X86_64
3942 "mov %c[r8](%0), %%r8 \n\t"
3943 "mov %c[r9](%0), %%r9 \n\t"
3944 "mov %c[r10](%0), %%r10 \n\t"
3945 "mov %c[r11](%0), %%r11 \n\t"
3946 "mov %c[r12](%0), %%r12 \n\t"
3947 "mov %c[r13](%0), %%r13 \n\t"
3948 "mov %c[r14](%0), %%r14 \n\t"
3949 "mov %c[r15](%0), %%r15 \n\t"
3951 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3953 /* Enter guest mode */
3954 "jne .Llaunched \n\t"
3955 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3956 "jmp .Lkvm_vmx_return \n\t"
3957 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3958 ".Lkvm_vmx_return: "
3959 /* Save guest registers, load host registers, keep flags */
3960 "xchg %0, (%%"R"sp) \n\t"
3961 "mov %%"R"ax, %c[rax](%0) \n\t"
3962 "mov %%"R"bx, %c[rbx](%0) \n\t"
3963 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3964 "mov %%"R"dx, %c[rdx](%0) \n\t"
3965 "mov %%"R"si, %c[rsi](%0) \n\t"
3966 "mov %%"R"di, %c[rdi](%0) \n\t"
3967 "mov %%"R"bp, %c[rbp](%0) \n\t"
3968 #ifdef CONFIG_X86_64
3969 "mov %%r8, %c[r8](%0) \n\t"
3970 "mov %%r9, %c[r9](%0) \n\t"
3971 "mov %%r10, %c[r10](%0) \n\t"
3972 "mov %%r11, %c[r11](%0) \n\t"
3973 "mov %%r12, %c[r12](%0) \n\t"
3974 "mov %%r13, %c[r13](%0) \n\t"
3975 "mov %%r14, %c[r14](%0) \n\t"
3976 "mov %%r15, %c[r15](%0) \n\t"
3978 "mov %%cr2, %%"R"ax \n\t"
3979 "mov %%"R"ax, %c[cr2](%0) \n\t"
3981 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
3982 "setbe %c[fail](%0) \n\t"
3983 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3984 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3985 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3986 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3987 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3988 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3989 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3990 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3991 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3992 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3993 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3994 #ifdef CONFIG_X86_64
3995 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3996 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3997 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3998 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3999 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4000 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4001 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4002 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
4004 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
4006 , R"bx", R"di", R"si"
4007 #ifdef CONFIG_X86_64
4008 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4012 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
4013 | (1 << VCPU_EXREG_PDPTR));
4014 vcpu->arch.regs_dirty = 0;
4016 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
4017 if (vmx->rmode.irq.pending)
4018 fixup_rmode_irq(vmx);
4020 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
4023 vmx_complete_interrupts(vmx);
4029 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
4031 struct vcpu_vmx *vmx = to_vmx(vcpu);
4035 free_vmcs(vmx->vmcs);
4040 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4042 struct vcpu_vmx *vmx = to_vmx(vcpu);
4045 vmx_free_vmcs(vcpu);
4046 kfree(vmx->guest_msrs);
4047 kvm_vcpu_uninit(vcpu);
4048 kmem_cache_free(kvm_vcpu_cache, vmx);
4051 static inline void vmcs_init(struct vmcs *vmcs)
4053 u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id()));
4056 kvm_cpu_vmxon(phys_addr);
4064 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
4067 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
4071 return ERR_PTR(-ENOMEM);
4075 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4079 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
4080 if (!vmx->guest_msrs) {
4085 vmx->vmcs = alloc_vmcs();
4089 vmcs_init(vmx->vmcs);
4092 vmx_vcpu_load(&vmx->vcpu, cpu);
4093 err = vmx_vcpu_setup(vmx);
4094 vmx_vcpu_put(&vmx->vcpu);
4098 if (vm_need_virtualize_apic_accesses(kvm))
4099 if (alloc_apic_access_page(kvm) != 0)
4103 if (!kvm->arch.ept_identity_map_addr)
4104 kvm->arch.ept_identity_map_addr =
4105 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
4106 if (alloc_identity_pagetable(kvm) != 0)
4113 free_vmcs(vmx->vmcs);
4115 kfree(vmx->guest_msrs);
4117 kvm_vcpu_uninit(&vmx->vcpu);
4120 kmem_cache_free(kvm_vcpu_cache, vmx);
4121 return ERR_PTR(err);
4124 static void __init vmx_check_processor_compat(void *rtn)
4126 struct vmcs_config vmcs_conf;
4129 if (setup_vmcs_config(&vmcs_conf) < 0)
4131 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4132 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4133 smp_processor_id());
4138 static int get_ept_level(void)
4140 return VMX_EPT_DEFAULT_GAW + 1;
4143 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4147 /* For VT-d and EPT combination
4148 * 1. MMIO: always map as UC
4150 * a. VT-d without snooping control feature: can't guarantee the
4151 * result, try to trust guest.
4152 * b. VT-d with snooping control feature: snooping control feature of
4153 * VT-d engine can guarantee the cache correctness. Just set it
4154 * to WB to keep consistent with host. So the same as item 3.
4155 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
4156 * consistent with host MTRR
4159 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
4160 else if (vcpu->kvm->arch.iommu_domain &&
4161 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4162 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4163 VMX_EPT_MT_EPTE_SHIFT;
4165 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
4171 #define _ER(x) { EXIT_REASON_##x, #x }
4173 static const struct trace_print_flags vmx_exit_reasons_str[] = {
4175 _ER(EXTERNAL_INTERRUPT),
4177 _ER(PENDING_INTERRUPT),
4197 _ER(IO_INSTRUCTION),
4200 _ER(MWAIT_INSTRUCTION),
4201 _ER(MONITOR_INSTRUCTION),
4202 _ER(PAUSE_INSTRUCTION),
4203 _ER(MCE_DURING_VMENTRY),
4204 _ER(TPR_BELOW_THRESHOLD),
4214 static int vmx_get_lpage_level(void)
4216 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4217 return PT_DIRECTORY_LEVEL;
4219 /* For shadow and EPT supported 1GB page */
4220 return PT_PDPE_LEVEL;
4223 static inline u32 bit(int bitno)
4225 return 1 << (bitno & 31);
4228 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4230 struct kvm_cpuid_entry2 *best;
4231 struct vcpu_vmx *vmx = to_vmx(vcpu);
4234 vmx->rdtscp_enabled = false;
4235 if (vmx_rdtscp_supported()) {
4236 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4237 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4238 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4239 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4240 vmx->rdtscp_enabled = true;
4242 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4243 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4250 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4254 static struct kvm_x86_ops vmx_x86_ops = {
4255 .cpu_has_kvm_support = cpu_has_kvm_support,
4256 .disabled_by_bios = vmx_disabled_by_bios,
4257 .hardware_setup = hardware_setup,
4258 .hardware_unsetup = hardware_unsetup,
4259 .check_processor_compatibility = vmx_check_processor_compat,
4260 .hardware_enable = hardware_enable,
4261 .hardware_disable = hardware_disable,
4262 .cpu_has_accelerated_tpr = report_flexpriority,
4264 .vcpu_create = vmx_create_vcpu,
4265 .vcpu_free = vmx_free_vcpu,
4266 .vcpu_reset = vmx_vcpu_reset,
4268 .prepare_guest_switch = vmx_save_host_state,
4269 .vcpu_load = vmx_vcpu_load,
4270 .vcpu_put = vmx_vcpu_put,
4272 .set_guest_debug = set_guest_debug,
4273 .get_msr = vmx_get_msr,
4274 .set_msr = vmx_set_msr,
4275 .get_segment_base = vmx_get_segment_base,
4276 .get_segment = vmx_get_segment,
4277 .set_segment = vmx_set_segment,
4278 .get_cpl = vmx_get_cpl,
4279 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4280 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
4281 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4282 .set_cr0 = vmx_set_cr0,
4283 .set_cr3 = vmx_set_cr3,
4284 .set_cr4 = vmx_set_cr4,
4285 .set_efer = vmx_set_efer,
4286 .get_idt = vmx_get_idt,
4287 .set_idt = vmx_set_idt,
4288 .get_gdt = vmx_get_gdt,
4289 .set_gdt = vmx_set_gdt,
4290 .set_dr7 = vmx_set_dr7,
4291 .cache_reg = vmx_cache_reg,
4292 .get_rflags = vmx_get_rflags,
4293 .set_rflags = vmx_set_rflags,
4294 .fpu_activate = vmx_fpu_activate,
4295 .fpu_deactivate = vmx_fpu_deactivate,
4297 .tlb_flush = vmx_flush_tlb,
4299 .run = vmx_vcpu_run,
4300 .handle_exit = vmx_handle_exit,
4301 .skip_emulated_instruction = skip_emulated_instruction,
4302 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4303 .get_interrupt_shadow = vmx_get_interrupt_shadow,
4304 .patch_hypercall = vmx_patch_hypercall,
4305 .set_irq = vmx_inject_irq,
4306 .set_nmi = vmx_inject_nmi,
4307 .queue_exception = vmx_queue_exception,
4308 .interrupt_allowed = vmx_interrupt_allowed,
4309 .nmi_allowed = vmx_nmi_allowed,
4310 .get_nmi_mask = vmx_get_nmi_mask,
4311 .set_nmi_mask = vmx_set_nmi_mask,
4312 .enable_nmi_window = enable_nmi_window,
4313 .enable_irq_window = enable_irq_window,
4314 .update_cr8_intercept = update_cr8_intercept,
4316 .set_tss_addr = vmx_set_tss_addr,
4317 .get_tdp_level = get_ept_level,
4318 .get_mt_mask = vmx_get_mt_mask,
4320 .exit_reasons_str = vmx_exit_reasons_str,
4321 .get_lpage_level = vmx_get_lpage_level,
4323 .cpuid_update = vmx_cpuid_update,
4325 .rdtscp_supported = vmx_rdtscp_supported,
4327 .set_supported_cpuid = vmx_set_supported_cpuid,
4330 static int __init vmx_init(void)
4334 rdmsrl_safe(MSR_EFER, &host_efer);
4336 for (i = 0; i < NR_VMX_MSR; ++i)
4337 kvm_define_shared_msr(i, vmx_msr_index[i]);
4339 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4340 if (!vmx_io_bitmap_a)
4343 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4344 if (!vmx_io_bitmap_b) {
4349 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4350 if (!vmx_msr_bitmap_legacy) {
4355 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4356 if (!vmx_msr_bitmap_longmode) {
4362 * Allow direct access to the PC debug port (it is often used for I/O
4363 * delays, but the vmexits simply slow things down).
4365 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4366 clear_bit(0x80, vmx_io_bitmap_a);
4368 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4370 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4371 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4373 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4375 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4376 __alignof__(struct vcpu_vmx), THIS_MODULE);
4380 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4381 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4382 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4383 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4384 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4385 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4388 bypass_guest_pf = 0;
4389 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
4390 VMX_EPT_WRITABLE_MASK);
4391 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4392 VMX_EPT_EXECUTABLE_MASK);
4397 if (bypass_guest_pf)
4398 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4403 free_page((unsigned long)vmx_msr_bitmap_longmode);
4405 free_page((unsigned long)vmx_msr_bitmap_legacy);
4407 free_page((unsigned long)vmx_io_bitmap_b);
4409 free_page((unsigned long)vmx_io_bitmap_a);
4413 static void __exit vmx_exit(void)
4415 free_page((unsigned long)vmx_msr_bitmap_legacy);
4416 free_page((unsigned long)vmx_msr_bitmap_longmode);
4417 free_page((unsigned long)vmx_io_bitmap_b);
4418 free_page((unsigned long)vmx_io_bitmap_a);
4423 module_init(vmx_init)
4424 module_exit(vmx_exit)