KVM: introduce id_to_memslot function
[linux-3.10.git] / arch / x86 / kvm / vmx.c
1 /*
2  * Kernel-based Virtual Machine driver for Linux
3  *
4  * This module enables machines with Intel VT-x extensions to run virtual
5  * machines without emulation or binary translation.
6  *
7  * Copyright (C) 2006 Qumranet, Inc.
8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
9  *
10  * Authors:
11  *   Avi Kivity   <avi@qumranet.com>
12  *   Yaniv Kamay  <yaniv@qumranet.com>
13  *
14  * This work is licensed under the terms of the GNU GPL, version 2.  See
15  * the COPYING file in the top-level directory.
16  *
17  */
18
19 #include "irq.h"
20 #include "mmu.h"
21
22 #include <linux/kvm_host.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/mm.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/moduleparam.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31 #include <linux/tboot.h>
32 #include "kvm_cache_regs.h"
33 #include "x86.h"
34
35 #include <asm/io.h>
36 #include <asm/desc.h>
37 #include <asm/vmx.h>
38 #include <asm/virtext.h>
39 #include <asm/mce.h>
40 #include <asm/i387.h>
41 #include <asm/xcr.h>
42 #include <asm/perf_event.h>
43
44 #include "trace.h"
45
46 #define __ex(x) __kvm_handle_fault_on_reboot(x)
47 #define __ex_clear(x, reg) \
48         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
49
50 MODULE_AUTHOR("Qumranet");
51 MODULE_LICENSE("GPL");
52
53 static int __read_mostly enable_vpid = 1;
54 module_param_named(vpid, enable_vpid, bool, 0444);
55
56 static int __read_mostly flexpriority_enabled = 1;
57 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
58
59 static int __read_mostly enable_ept = 1;
60 module_param_named(ept, enable_ept, bool, S_IRUGO);
61
62 static int __read_mostly enable_unrestricted_guest = 1;
63 module_param_named(unrestricted_guest,
64                         enable_unrestricted_guest, bool, S_IRUGO);
65
66 static int __read_mostly emulate_invalid_guest_state = 0;
67 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
68
69 static int __read_mostly vmm_exclusive = 1;
70 module_param(vmm_exclusive, bool, S_IRUGO);
71
72 static int __read_mostly yield_on_hlt = 1;
73 module_param(yield_on_hlt, bool, S_IRUGO);
74
75 static int __read_mostly fasteoi = 1;
76 module_param(fasteoi, bool, S_IRUGO);
77
78 /*
79  * If nested=1, nested virtualization is supported, i.e., guests may use
80  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
81  * use VMX instructions.
82  */
83 static int __read_mostly nested = 0;
84 module_param(nested, bool, S_IRUGO);
85
86 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
87         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
88 #define KVM_GUEST_CR0_MASK                                              \
89         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
90 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
91         (X86_CR0_WP | X86_CR0_NE)
92 #define KVM_VM_CR0_ALWAYS_ON                                            \
93         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
94 #define KVM_CR4_GUEST_OWNED_BITS                                      \
95         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
96          | X86_CR4_OSXMMEXCPT)
97
98 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
99 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
100
101 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
102
103 /*
104  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
105  * ple_gap:    upper bound on the amount of time between two successive
106  *             executions of PAUSE in a loop. Also indicate if ple enabled.
107  *             According to test, this time is usually smaller than 128 cycles.
108  * ple_window: upper bound on the amount of time a guest is allowed to execute
109  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
110  *             less than 2^12 cycles
111  * Time is measured based on a counter that runs at the same rate as the TSC,
112  * refer SDM volume 3b section 21.6.13 & 22.1.3.
113  */
114 #define KVM_VMX_DEFAULT_PLE_GAP    128
115 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
116 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
117 module_param(ple_gap, int, S_IRUGO);
118
119 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
120 module_param(ple_window, int, S_IRUGO);
121
122 #define NR_AUTOLOAD_MSRS 8
123 #define VMCS02_POOL_SIZE 1
124
125 struct vmcs {
126         u32 revision_id;
127         u32 abort;
128         char data[0];
129 };
130
131 /*
132  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
133  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
134  * loaded on this CPU (so we can clear them if the CPU goes down).
135  */
136 struct loaded_vmcs {
137         struct vmcs *vmcs;
138         int cpu;
139         int launched;
140         struct list_head loaded_vmcss_on_cpu_link;
141 };
142
143 struct shared_msr_entry {
144         unsigned index;
145         u64 data;
146         u64 mask;
147 };
148
149 /*
150  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
151  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
152  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
153  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
154  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
155  * More than one of these structures may exist, if L1 runs multiple L2 guests.
156  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
157  * underlying hardware which will be used to run L2.
158  * This structure is packed to ensure that its layout is identical across
159  * machines (necessary for live migration).
160  * If there are changes in this struct, VMCS12_REVISION must be changed.
161  */
162 typedef u64 natural_width;
163 struct __packed vmcs12 {
164         /* According to the Intel spec, a VMCS region must start with the
165          * following two fields. Then follow implementation-specific data.
166          */
167         u32 revision_id;
168         u32 abort;
169
170         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
171         u32 padding[7]; /* room for future expansion */
172
173         u64 io_bitmap_a;
174         u64 io_bitmap_b;
175         u64 msr_bitmap;
176         u64 vm_exit_msr_store_addr;
177         u64 vm_exit_msr_load_addr;
178         u64 vm_entry_msr_load_addr;
179         u64 tsc_offset;
180         u64 virtual_apic_page_addr;
181         u64 apic_access_addr;
182         u64 ept_pointer;
183         u64 guest_physical_address;
184         u64 vmcs_link_pointer;
185         u64 guest_ia32_debugctl;
186         u64 guest_ia32_pat;
187         u64 guest_ia32_efer;
188         u64 guest_ia32_perf_global_ctrl;
189         u64 guest_pdptr0;
190         u64 guest_pdptr1;
191         u64 guest_pdptr2;
192         u64 guest_pdptr3;
193         u64 host_ia32_pat;
194         u64 host_ia32_efer;
195         u64 host_ia32_perf_global_ctrl;
196         u64 padding64[8]; /* room for future expansion */
197         /*
198          * To allow migration of L1 (complete with its L2 guests) between
199          * machines of different natural widths (32 or 64 bit), we cannot have
200          * unsigned long fields with no explict size. We use u64 (aliased
201          * natural_width) instead. Luckily, x86 is little-endian.
202          */
203         natural_width cr0_guest_host_mask;
204         natural_width cr4_guest_host_mask;
205         natural_width cr0_read_shadow;
206         natural_width cr4_read_shadow;
207         natural_width cr3_target_value0;
208         natural_width cr3_target_value1;
209         natural_width cr3_target_value2;
210         natural_width cr3_target_value3;
211         natural_width exit_qualification;
212         natural_width guest_linear_address;
213         natural_width guest_cr0;
214         natural_width guest_cr3;
215         natural_width guest_cr4;
216         natural_width guest_es_base;
217         natural_width guest_cs_base;
218         natural_width guest_ss_base;
219         natural_width guest_ds_base;
220         natural_width guest_fs_base;
221         natural_width guest_gs_base;
222         natural_width guest_ldtr_base;
223         natural_width guest_tr_base;
224         natural_width guest_gdtr_base;
225         natural_width guest_idtr_base;
226         natural_width guest_dr7;
227         natural_width guest_rsp;
228         natural_width guest_rip;
229         natural_width guest_rflags;
230         natural_width guest_pending_dbg_exceptions;
231         natural_width guest_sysenter_esp;
232         natural_width guest_sysenter_eip;
233         natural_width host_cr0;
234         natural_width host_cr3;
235         natural_width host_cr4;
236         natural_width host_fs_base;
237         natural_width host_gs_base;
238         natural_width host_tr_base;
239         natural_width host_gdtr_base;
240         natural_width host_idtr_base;
241         natural_width host_ia32_sysenter_esp;
242         natural_width host_ia32_sysenter_eip;
243         natural_width host_rsp;
244         natural_width host_rip;
245         natural_width paddingl[8]; /* room for future expansion */
246         u32 pin_based_vm_exec_control;
247         u32 cpu_based_vm_exec_control;
248         u32 exception_bitmap;
249         u32 page_fault_error_code_mask;
250         u32 page_fault_error_code_match;
251         u32 cr3_target_count;
252         u32 vm_exit_controls;
253         u32 vm_exit_msr_store_count;
254         u32 vm_exit_msr_load_count;
255         u32 vm_entry_controls;
256         u32 vm_entry_msr_load_count;
257         u32 vm_entry_intr_info_field;
258         u32 vm_entry_exception_error_code;
259         u32 vm_entry_instruction_len;
260         u32 tpr_threshold;
261         u32 secondary_vm_exec_control;
262         u32 vm_instruction_error;
263         u32 vm_exit_reason;
264         u32 vm_exit_intr_info;
265         u32 vm_exit_intr_error_code;
266         u32 idt_vectoring_info_field;
267         u32 idt_vectoring_error_code;
268         u32 vm_exit_instruction_len;
269         u32 vmx_instruction_info;
270         u32 guest_es_limit;
271         u32 guest_cs_limit;
272         u32 guest_ss_limit;
273         u32 guest_ds_limit;
274         u32 guest_fs_limit;
275         u32 guest_gs_limit;
276         u32 guest_ldtr_limit;
277         u32 guest_tr_limit;
278         u32 guest_gdtr_limit;
279         u32 guest_idtr_limit;
280         u32 guest_es_ar_bytes;
281         u32 guest_cs_ar_bytes;
282         u32 guest_ss_ar_bytes;
283         u32 guest_ds_ar_bytes;
284         u32 guest_fs_ar_bytes;
285         u32 guest_gs_ar_bytes;
286         u32 guest_ldtr_ar_bytes;
287         u32 guest_tr_ar_bytes;
288         u32 guest_interruptibility_info;
289         u32 guest_activity_state;
290         u32 guest_sysenter_cs;
291         u32 host_ia32_sysenter_cs;
292         u32 padding32[8]; /* room for future expansion */
293         u16 virtual_processor_id;
294         u16 guest_es_selector;
295         u16 guest_cs_selector;
296         u16 guest_ss_selector;
297         u16 guest_ds_selector;
298         u16 guest_fs_selector;
299         u16 guest_gs_selector;
300         u16 guest_ldtr_selector;
301         u16 guest_tr_selector;
302         u16 host_es_selector;
303         u16 host_cs_selector;
304         u16 host_ss_selector;
305         u16 host_ds_selector;
306         u16 host_fs_selector;
307         u16 host_gs_selector;
308         u16 host_tr_selector;
309 };
310
311 /*
312  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
313  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
314  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
315  */
316 #define VMCS12_REVISION 0x11e57ed0
317
318 /*
319  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
320  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
321  * current implementation, 4K are reserved to avoid future complications.
322  */
323 #define VMCS12_SIZE 0x1000
324
325 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
326 struct vmcs02_list {
327         struct list_head list;
328         gpa_t vmptr;
329         struct loaded_vmcs vmcs02;
330 };
331
332 /*
333  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
334  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
335  */
336 struct nested_vmx {
337         /* Has the level1 guest done vmxon? */
338         bool vmxon;
339
340         /* The guest-physical address of the current VMCS L1 keeps for L2 */
341         gpa_t current_vmptr;
342         /* The host-usable pointer to the above */
343         struct page *current_vmcs12_page;
344         struct vmcs12 *current_vmcs12;
345
346         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
347         struct list_head vmcs02_pool;
348         int vmcs02_num;
349         u64 vmcs01_tsc_offset;
350         /* L2 must run next, and mustn't decide to exit to L1. */
351         bool nested_run_pending;
352         /*
353          * Guest pages referred to in vmcs02 with host-physical pointers, so
354          * we must keep them pinned while L2 runs.
355          */
356         struct page *apic_access_page;
357 };
358
359 struct vcpu_vmx {
360         struct kvm_vcpu       vcpu;
361         unsigned long         host_rsp;
362         u8                    fail;
363         u8                    cpl;
364         bool                  nmi_known_unmasked;
365         u32                   exit_intr_info;
366         u32                   idt_vectoring_info;
367         ulong                 rflags;
368         struct shared_msr_entry *guest_msrs;
369         int                   nmsrs;
370         int                   save_nmsrs;
371 #ifdef CONFIG_X86_64
372         u64                   msr_host_kernel_gs_base;
373         u64                   msr_guest_kernel_gs_base;
374 #endif
375         /*
376          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
377          * non-nested (L1) guest, it always points to vmcs01. For a nested
378          * guest (L2), it points to a different VMCS.
379          */
380         struct loaded_vmcs    vmcs01;
381         struct loaded_vmcs   *loaded_vmcs;
382         bool                  __launched; /* temporary, used in vmx_vcpu_run */
383         struct msr_autoload {
384                 unsigned nr;
385                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
386                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
387         } msr_autoload;
388         struct {
389                 int           loaded;
390                 u16           fs_sel, gs_sel, ldt_sel;
391                 int           gs_ldt_reload_needed;
392                 int           fs_reload_needed;
393         } host_state;
394         struct {
395                 int vm86_active;
396                 ulong save_rflags;
397                 struct kvm_save_segment {
398                         u16 selector;
399                         unsigned long base;
400                         u32 limit;
401                         u32 ar;
402                 } tr, es, ds, fs, gs;
403         } rmode;
404         struct {
405                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
406                 struct kvm_save_segment seg[8];
407         } segment_cache;
408         int vpid;
409         bool emulation_required;
410
411         /* Support for vnmi-less CPUs */
412         int soft_vnmi_blocked;
413         ktime_t entry_time;
414         s64 vnmi_blocked_time;
415         u32 exit_reason;
416
417         bool rdtscp_enabled;
418
419         /* Support for a guest hypervisor (nested VMX) */
420         struct nested_vmx nested;
421 };
422
423 enum segment_cache_field {
424         SEG_FIELD_SEL = 0,
425         SEG_FIELD_BASE = 1,
426         SEG_FIELD_LIMIT = 2,
427         SEG_FIELD_AR = 3,
428
429         SEG_FIELD_NR = 4
430 };
431
432 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
433 {
434         return container_of(vcpu, struct vcpu_vmx, vcpu);
435 }
436
437 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
438 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
439 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
440                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
441
442 static unsigned short vmcs_field_to_offset_table[] = {
443         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
444         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
445         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
446         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
447         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
448         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
449         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
450         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
451         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
452         FIELD(HOST_ES_SELECTOR, host_es_selector),
453         FIELD(HOST_CS_SELECTOR, host_cs_selector),
454         FIELD(HOST_SS_SELECTOR, host_ss_selector),
455         FIELD(HOST_DS_SELECTOR, host_ds_selector),
456         FIELD(HOST_FS_SELECTOR, host_fs_selector),
457         FIELD(HOST_GS_SELECTOR, host_gs_selector),
458         FIELD(HOST_TR_SELECTOR, host_tr_selector),
459         FIELD64(IO_BITMAP_A, io_bitmap_a),
460         FIELD64(IO_BITMAP_B, io_bitmap_b),
461         FIELD64(MSR_BITMAP, msr_bitmap),
462         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
463         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
464         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
465         FIELD64(TSC_OFFSET, tsc_offset),
466         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
467         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
468         FIELD64(EPT_POINTER, ept_pointer),
469         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
470         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
471         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
472         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
473         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
474         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
475         FIELD64(GUEST_PDPTR0, guest_pdptr0),
476         FIELD64(GUEST_PDPTR1, guest_pdptr1),
477         FIELD64(GUEST_PDPTR2, guest_pdptr2),
478         FIELD64(GUEST_PDPTR3, guest_pdptr3),
479         FIELD64(HOST_IA32_PAT, host_ia32_pat),
480         FIELD64(HOST_IA32_EFER, host_ia32_efer),
481         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
482         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
483         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
484         FIELD(EXCEPTION_BITMAP, exception_bitmap),
485         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
486         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
487         FIELD(CR3_TARGET_COUNT, cr3_target_count),
488         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
489         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
490         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
491         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
492         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
493         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
494         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
495         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
496         FIELD(TPR_THRESHOLD, tpr_threshold),
497         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
498         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
499         FIELD(VM_EXIT_REASON, vm_exit_reason),
500         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
501         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
502         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
503         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
504         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
505         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
506         FIELD(GUEST_ES_LIMIT, guest_es_limit),
507         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
508         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
509         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
510         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
511         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
512         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
513         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
514         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
515         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
516         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
517         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
518         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
519         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
520         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
521         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
522         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
523         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
524         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
525         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
526         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
527         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
528         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
529         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
530         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
531         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
532         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
533         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
534         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
535         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
536         FIELD(EXIT_QUALIFICATION, exit_qualification),
537         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
538         FIELD(GUEST_CR0, guest_cr0),
539         FIELD(GUEST_CR3, guest_cr3),
540         FIELD(GUEST_CR4, guest_cr4),
541         FIELD(GUEST_ES_BASE, guest_es_base),
542         FIELD(GUEST_CS_BASE, guest_cs_base),
543         FIELD(GUEST_SS_BASE, guest_ss_base),
544         FIELD(GUEST_DS_BASE, guest_ds_base),
545         FIELD(GUEST_FS_BASE, guest_fs_base),
546         FIELD(GUEST_GS_BASE, guest_gs_base),
547         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
548         FIELD(GUEST_TR_BASE, guest_tr_base),
549         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
550         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
551         FIELD(GUEST_DR7, guest_dr7),
552         FIELD(GUEST_RSP, guest_rsp),
553         FIELD(GUEST_RIP, guest_rip),
554         FIELD(GUEST_RFLAGS, guest_rflags),
555         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
556         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
557         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
558         FIELD(HOST_CR0, host_cr0),
559         FIELD(HOST_CR3, host_cr3),
560         FIELD(HOST_CR4, host_cr4),
561         FIELD(HOST_FS_BASE, host_fs_base),
562         FIELD(HOST_GS_BASE, host_gs_base),
563         FIELD(HOST_TR_BASE, host_tr_base),
564         FIELD(HOST_GDTR_BASE, host_gdtr_base),
565         FIELD(HOST_IDTR_BASE, host_idtr_base),
566         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
567         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
568         FIELD(HOST_RSP, host_rsp),
569         FIELD(HOST_RIP, host_rip),
570 };
571 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
572
573 static inline short vmcs_field_to_offset(unsigned long field)
574 {
575         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
576                 return -1;
577         return vmcs_field_to_offset_table[field];
578 }
579
580 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
581 {
582         return to_vmx(vcpu)->nested.current_vmcs12;
583 }
584
585 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
586 {
587         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
588         if (is_error_page(page)) {
589                 kvm_release_page_clean(page);
590                 return NULL;
591         }
592         return page;
593 }
594
595 static void nested_release_page(struct page *page)
596 {
597         kvm_release_page_dirty(page);
598 }
599
600 static void nested_release_page_clean(struct page *page)
601 {
602         kvm_release_page_clean(page);
603 }
604
605 static u64 construct_eptp(unsigned long root_hpa);
606 static void kvm_cpu_vmxon(u64 addr);
607 static void kvm_cpu_vmxoff(void);
608 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
609 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
610
611 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
612 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
613 /*
614  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
615  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
616  */
617 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
618 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
619
620 static unsigned long *vmx_io_bitmap_a;
621 static unsigned long *vmx_io_bitmap_b;
622 static unsigned long *vmx_msr_bitmap_legacy;
623 static unsigned long *vmx_msr_bitmap_longmode;
624
625 static bool cpu_has_load_ia32_efer;
626 static bool cpu_has_load_perf_global_ctrl;
627
628 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
629 static DEFINE_SPINLOCK(vmx_vpid_lock);
630
631 static struct vmcs_config {
632         int size;
633         int order;
634         u32 revision_id;
635         u32 pin_based_exec_ctrl;
636         u32 cpu_based_exec_ctrl;
637         u32 cpu_based_2nd_exec_ctrl;
638         u32 vmexit_ctrl;
639         u32 vmentry_ctrl;
640 } vmcs_config;
641
642 static struct vmx_capability {
643         u32 ept;
644         u32 vpid;
645 } vmx_capability;
646
647 #define VMX_SEGMENT_FIELD(seg)                                  \
648         [VCPU_SREG_##seg] = {                                   \
649                 .selector = GUEST_##seg##_SELECTOR,             \
650                 .base = GUEST_##seg##_BASE,                     \
651                 .limit = GUEST_##seg##_LIMIT,                   \
652                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
653         }
654
655 static struct kvm_vmx_segment_field {
656         unsigned selector;
657         unsigned base;
658         unsigned limit;
659         unsigned ar_bytes;
660 } kvm_vmx_segment_fields[] = {
661         VMX_SEGMENT_FIELD(CS),
662         VMX_SEGMENT_FIELD(DS),
663         VMX_SEGMENT_FIELD(ES),
664         VMX_SEGMENT_FIELD(FS),
665         VMX_SEGMENT_FIELD(GS),
666         VMX_SEGMENT_FIELD(SS),
667         VMX_SEGMENT_FIELD(TR),
668         VMX_SEGMENT_FIELD(LDTR),
669 };
670
671 static u64 host_efer;
672
673 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
674
675 /*
676  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
677  * away by decrementing the array size.
678  */
679 static const u32 vmx_msr_index[] = {
680 #ifdef CONFIG_X86_64
681         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
682 #endif
683         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
684 };
685 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
686
687 static inline bool is_page_fault(u32 intr_info)
688 {
689         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
690                              INTR_INFO_VALID_MASK)) ==
691                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
692 }
693
694 static inline bool is_no_device(u32 intr_info)
695 {
696         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
697                              INTR_INFO_VALID_MASK)) ==
698                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
699 }
700
701 static inline bool is_invalid_opcode(u32 intr_info)
702 {
703         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
704                              INTR_INFO_VALID_MASK)) ==
705                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
706 }
707
708 static inline bool is_external_interrupt(u32 intr_info)
709 {
710         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
711                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
712 }
713
714 static inline bool is_machine_check(u32 intr_info)
715 {
716         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
717                              INTR_INFO_VALID_MASK)) ==
718                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
719 }
720
721 static inline bool cpu_has_vmx_msr_bitmap(void)
722 {
723         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
724 }
725
726 static inline bool cpu_has_vmx_tpr_shadow(void)
727 {
728         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
729 }
730
731 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
732 {
733         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
734 }
735
736 static inline bool cpu_has_secondary_exec_ctrls(void)
737 {
738         return vmcs_config.cpu_based_exec_ctrl &
739                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
740 }
741
742 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
743 {
744         return vmcs_config.cpu_based_2nd_exec_ctrl &
745                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
746 }
747
748 static inline bool cpu_has_vmx_flexpriority(void)
749 {
750         return cpu_has_vmx_tpr_shadow() &&
751                 cpu_has_vmx_virtualize_apic_accesses();
752 }
753
754 static inline bool cpu_has_vmx_ept_execute_only(void)
755 {
756         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
757 }
758
759 static inline bool cpu_has_vmx_eptp_uncacheable(void)
760 {
761         return vmx_capability.ept & VMX_EPTP_UC_BIT;
762 }
763
764 static inline bool cpu_has_vmx_eptp_writeback(void)
765 {
766         return vmx_capability.ept & VMX_EPTP_WB_BIT;
767 }
768
769 static inline bool cpu_has_vmx_ept_2m_page(void)
770 {
771         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
772 }
773
774 static inline bool cpu_has_vmx_ept_1g_page(void)
775 {
776         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
777 }
778
779 static inline bool cpu_has_vmx_ept_4levels(void)
780 {
781         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
782 }
783
784 static inline bool cpu_has_vmx_invept_individual_addr(void)
785 {
786         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
787 }
788
789 static inline bool cpu_has_vmx_invept_context(void)
790 {
791         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
792 }
793
794 static inline bool cpu_has_vmx_invept_global(void)
795 {
796         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
797 }
798
799 static inline bool cpu_has_vmx_invvpid_single(void)
800 {
801         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
802 }
803
804 static inline bool cpu_has_vmx_invvpid_global(void)
805 {
806         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
807 }
808
809 static inline bool cpu_has_vmx_ept(void)
810 {
811         return vmcs_config.cpu_based_2nd_exec_ctrl &
812                 SECONDARY_EXEC_ENABLE_EPT;
813 }
814
815 static inline bool cpu_has_vmx_unrestricted_guest(void)
816 {
817         return vmcs_config.cpu_based_2nd_exec_ctrl &
818                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
819 }
820
821 static inline bool cpu_has_vmx_ple(void)
822 {
823         return vmcs_config.cpu_based_2nd_exec_ctrl &
824                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
825 }
826
827 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
828 {
829         return flexpriority_enabled && irqchip_in_kernel(kvm);
830 }
831
832 static inline bool cpu_has_vmx_vpid(void)
833 {
834         return vmcs_config.cpu_based_2nd_exec_ctrl &
835                 SECONDARY_EXEC_ENABLE_VPID;
836 }
837
838 static inline bool cpu_has_vmx_rdtscp(void)
839 {
840         return vmcs_config.cpu_based_2nd_exec_ctrl &
841                 SECONDARY_EXEC_RDTSCP;
842 }
843
844 static inline bool cpu_has_virtual_nmis(void)
845 {
846         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
847 }
848
849 static inline bool cpu_has_vmx_wbinvd_exit(void)
850 {
851         return vmcs_config.cpu_based_2nd_exec_ctrl &
852                 SECONDARY_EXEC_WBINVD_EXITING;
853 }
854
855 static inline bool report_flexpriority(void)
856 {
857         return flexpriority_enabled;
858 }
859
860 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
861 {
862         return vmcs12->cpu_based_vm_exec_control & bit;
863 }
864
865 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
866 {
867         return (vmcs12->cpu_based_vm_exec_control &
868                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
869                 (vmcs12->secondary_vm_exec_control & bit);
870 }
871
872 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
873         struct kvm_vcpu *vcpu)
874 {
875         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
876 }
877
878 static inline bool is_exception(u32 intr_info)
879 {
880         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
881                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
882 }
883
884 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
885 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
886                         struct vmcs12 *vmcs12,
887                         u32 reason, unsigned long qualification);
888
889 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
890 {
891         int i;
892
893         for (i = 0; i < vmx->nmsrs; ++i)
894                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
895                         return i;
896         return -1;
897 }
898
899 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
900 {
901     struct {
902         u64 vpid : 16;
903         u64 rsvd : 48;
904         u64 gva;
905     } operand = { vpid, 0, gva };
906
907     asm volatile (__ex(ASM_VMX_INVVPID)
908                   /* CF==1 or ZF==1 --> rc = -1 */
909                   "; ja 1f ; ud2 ; 1:"
910                   : : "a"(&operand), "c"(ext) : "cc", "memory");
911 }
912
913 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
914 {
915         struct {
916                 u64 eptp, gpa;
917         } operand = {eptp, gpa};
918
919         asm volatile (__ex(ASM_VMX_INVEPT)
920                         /* CF==1 or ZF==1 --> rc = -1 */
921                         "; ja 1f ; ud2 ; 1:\n"
922                         : : "a" (&operand), "c" (ext) : "cc", "memory");
923 }
924
925 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
926 {
927         int i;
928
929         i = __find_msr_index(vmx, msr);
930         if (i >= 0)
931                 return &vmx->guest_msrs[i];
932         return NULL;
933 }
934
935 static void vmcs_clear(struct vmcs *vmcs)
936 {
937         u64 phys_addr = __pa(vmcs);
938         u8 error;
939
940         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
941                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
942                       : "cc", "memory");
943         if (error)
944                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
945                        vmcs, phys_addr);
946 }
947
948 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
949 {
950         vmcs_clear(loaded_vmcs->vmcs);
951         loaded_vmcs->cpu = -1;
952         loaded_vmcs->launched = 0;
953 }
954
955 static void vmcs_load(struct vmcs *vmcs)
956 {
957         u64 phys_addr = __pa(vmcs);
958         u8 error;
959
960         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
961                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
962                         : "cc", "memory");
963         if (error)
964                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
965                        vmcs, phys_addr);
966 }
967
968 static void __loaded_vmcs_clear(void *arg)
969 {
970         struct loaded_vmcs *loaded_vmcs = arg;
971         int cpu = raw_smp_processor_id();
972
973         if (loaded_vmcs->cpu != cpu)
974                 return; /* vcpu migration can race with cpu offline */
975         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
976                 per_cpu(current_vmcs, cpu) = NULL;
977         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
978         loaded_vmcs_init(loaded_vmcs);
979 }
980
981 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
982 {
983         if (loaded_vmcs->cpu != -1)
984                 smp_call_function_single(
985                         loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
986 }
987
988 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
989 {
990         if (vmx->vpid == 0)
991                 return;
992
993         if (cpu_has_vmx_invvpid_single())
994                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
995 }
996
997 static inline void vpid_sync_vcpu_global(void)
998 {
999         if (cpu_has_vmx_invvpid_global())
1000                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1001 }
1002
1003 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1004 {
1005         if (cpu_has_vmx_invvpid_single())
1006                 vpid_sync_vcpu_single(vmx);
1007         else
1008                 vpid_sync_vcpu_global();
1009 }
1010
1011 static inline void ept_sync_global(void)
1012 {
1013         if (cpu_has_vmx_invept_global())
1014                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1015 }
1016
1017 static inline void ept_sync_context(u64 eptp)
1018 {
1019         if (enable_ept) {
1020                 if (cpu_has_vmx_invept_context())
1021                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1022                 else
1023                         ept_sync_global();
1024         }
1025 }
1026
1027 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1028 {
1029         if (enable_ept) {
1030                 if (cpu_has_vmx_invept_individual_addr())
1031                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1032                                         eptp, gpa);
1033                 else
1034                         ept_sync_context(eptp);
1035         }
1036 }
1037
1038 static __always_inline unsigned long vmcs_readl(unsigned long field)
1039 {
1040         unsigned long value;
1041
1042         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1043                       : "=a"(value) : "d"(field) : "cc");
1044         return value;
1045 }
1046
1047 static __always_inline u16 vmcs_read16(unsigned long field)
1048 {
1049         return vmcs_readl(field);
1050 }
1051
1052 static __always_inline u32 vmcs_read32(unsigned long field)
1053 {
1054         return vmcs_readl(field);
1055 }
1056
1057 static __always_inline u64 vmcs_read64(unsigned long field)
1058 {
1059 #ifdef CONFIG_X86_64
1060         return vmcs_readl(field);
1061 #else
1062         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1063 #endif
1064 }
1065
1066 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1067 {
1068         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1069                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1070         dump_stack();
1071 }
1072
1073 static void vmcs_writel(unsigned long field, unsigned long value)
1074 {
1075         u8 error;
1076
1077         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1078                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1079         if (unlikely(error))
1080                 vmwrite_error(field, value);
1081 }
1082
1083 static void vmcs_write16(unsigned long field, u16 value)
1084 {
1085         vmcs_writel(field, value);
1086 }
1087
1088 static void vmcs_write32(unsigned long field, u32 value)
1089 {
1090         vmcs_writel(field, value);
1091 }
1092
1093 static void vmcs_write64(unsigned long field, u64 value)
1094 {
1095         vmcs_writel(field, value);
1096 #ifndef CONFIG_X86_64
1097         asm volatile ("");
1098         vmcs_writel(field+1, value >> 32);
1099 #endif
1100 }
1101
1102 static void vmcs_clear_bits(unsigned long field, u32 mask)
1103 {
1104         vmcs_writel(field, vmcs_readl(field) & ~mask);
1105 }
1106
1107 static void vmcs_set_bits(unsigned long field, u32 mask)
1108 {
1109         vmcs_writel(field, vmcs_readl(field) | mask);
1110 }
1111
1112 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1113 {
1114         vmx->segment_cache.bitmask = 0;
1115 }
1116
1117 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1118                                        unsigned field)
1119 {
1120         bool ret;
1121         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1122
1123         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1124                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1125                 vmx->segment_cache.bitmask = 0;
1126         }
1127         ret = vmx->segment_cache.bitmask & mask;
1128         vmx->segment_cache.bitmask |= mask;
1129         return ret;
1130 }
1131
1132 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1133 {
1134         u16 *p = &vmx->segment_cache.seg[seg].selector;
1135
1136         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1137                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1138         return *p;
1139 }
1140
1141 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1142 {
1143         ulong *p = &vmx->segment_cache.seg[seg].base;
1144
1145         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1146                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1147         return *p;
1148 }
1149
1150 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1151 {
1152         u32 *p = &vmx->segment_cache.seg[seg].limit;
1153
1154         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1155                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1156         return *p;
1157 }
1158
1159 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1160 {
1161         u32 *p = &vmx->segment_cache.seg[seg].ar;
1162
1163         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1164                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1165         return *p;
1166 }
1167
1168 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1169 {
1170         u32 eb;
1171
1172         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1173              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1174         if ((vcpu->guest_debug &
1175              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1176             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1177                 eb |= 1u << BP_VECTOR;
1178         if (to_vmx(vcpu)->rmode.vm86_active)
1179                 eb = ~0;
1180         if (enable_ept)
1181                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1182         if (vcpu->fpu_active)
1183                 eb &= ~(1u << NM_VECTOR);
1184
1185         /* When we are running a nested L2 guest and L1 specified for it a
1186          * certain exception bitmap, we must trap the same exceptions and pass
1187          * them to L1. When running L2, we will only handle the exceptions
1188          * specified above if L1 did not want them.
1189          */
1190         if (is_guest_mode(vcpu))
1191                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1192
1193         vmcs_write32(EXCEPTION_BITMAP, eb);
1194 }
1195
1196 static void clear_atomic_switch_msr_special(unsigned long entry,
1197                 unsigned long exit)
1198 {
1199         vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1200         vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1201 }
1202
1203 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1204 {
1205         unsigned i;
1206         struct msr_autoload *m = &vmx->msr_autoload;
1207
1208         switch (msr) {
1209         case MSR_EFER:
1210                 if (cpu_has_load_ia32_efer) {
1211                         clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1212                                         VM_EXIT_LOAD_IA32_EFER);
1213                         return;
1214                 }
1215                 break;
1216         case MSR_CORE_PERF_GLOBAL_CTRL:
1217                 if (cpu_has_load_perf_global_ctrl) {
1218                         clear_atomic_switch_msr_special(
1219                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1220                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1221                         return;
1222                 }
1223                 break;
1224         }
1225
1226         for (i = 0; i < m->nr; ++i)
1227                 if (m->guest[i].index == msr)
1228                         break;
1229
1230         if (i == m->nr)
1231                 return;
1232         --m->nr;
1233         m->guest[i] = m->guest[m->nr];
1234         m->host[i] = m->host[m->nr];
1235         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1236         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1237 }
1238
1239 static void add_atomic_switch_msr_special(unsigned long entry,
1240                 unsigned long exit, unsigned long guest_val_vmcs,
1241                 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1242 {
1243         vmcs_write64(guest_val_vmcs, guest_val);
1244         vmcs_write64(host_val_vmcs, host_val);
1245         vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1246         vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1247 }
1248
1249 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1250                                   u64 guest_val, u64 host_val)
1251 {
1252         unsigned i;
1253         struct msr_autoload *m = &vmx->msr_autoload;
1254
1255         switch (msr) {
1256         case MSR_EFER:
1257                 if (cpu_has_load_ia32_efer) {
1258                         add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1259                                         VM_EXIT_LOAD_IA32_EFER,
1260                                         GUEST_IA32_EFER,
1261                                         HOST_IA32_EFER,
1262                                         guest_val, host_val);
1263                         return;
1264                 }
1265                 break;
1266         case MSR_CORE_PERF_GLOBAL_CTRL:
1267                 if (cpu_has_load_perf_global_ctrl) {
1268                         add_atomic_switch_msr_special(
1269                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1270                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1271                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1272                                         HOST_IA32_PERF_GLOBAL_CTRL,
1273                                         guest_val, host_val);
1274                         return;
1275                 }
1276                 break;
1277         }
1278
1279         for (i = 0; i < m->nr; ++i)
1280                 if (m->guest[i].index == msr)
1281                         break;
1282
1283         if (i == NR_AUTOLOAD_MSRS) {
1284                 printk_once(KERN_WARNING"Not enough mst switch entries. "
1285                                 "Can't add msr %x\n", msr);
1286                 return;
1287         } else if (i == m->nr) {
1288                 ++m->nr;
1289                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1290                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1291         }
1292
1293         m->guest[i].index = msr;
1294         m->guest[i].value = guest_val;
1295         m->host[i].index = msr;
1296         m->host[i].value = host_val;
1297 }
1298
1299 static void reload_tss(void)
1300 {
1301         /*
1302          * VT restores TR but not its size.  Useless.
1303          */
1304         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1305         struct desc_struct *descs;
1306
1307         descs = (void *)gdt->address;
1308         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1309         load_TR_desc();
1310 }
1311
1312 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1313 {
1314         u64 guest_efer;
1315         u64 ignore_bits;
1316
1317         guest_efer = vmx->vcpu.arch.efer;
1318
1319         /*
1320          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1321          * outside long mode
1322          */
1323         ignore_bits = EFER_NX | EFER_SCE;
1324 #ifdef CONFIG_X86_64
1325         ignore_bits |= EFER_LMA | EFER_LME;
1326         /* SCE is meaningful only in long mode on Intel */
1327         if (guest_efer & EFER_LMA)
1328                 ignore_bits &= ~(u64)EFER_SCE;
1329 #endif
1330         guest_efer &= ~ignore_bits;
1331         guest_efer |= host_efer & ignore_bits;
1332         vmx->guest_msrs[efer_offset].data = guest_efer;
1333         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1334
1335         clear_atomic_switch_msr(vmx, MSR_EFER);
1336         /* On ept, can't emulate nx, and must switch nx atomically */
1337         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1338                 guest_efer = vmx->vcpu.arch.efer;
1339                 if (!(guest_efer & EFER_LMA))
1340                         guest_efer &= ~EFER_LME;
1341                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1342                 return false;
1343         }
1344
1345         return true;
1346 }
1347
1348 static unsigned long segment_base(u16 selector)
1349 {
1350         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1351         struct desc_struct *d;
1352         unsigned long table_base;
1353         unsigned long v;
1354
1355         if (!(selector & ~3))
1356                 return 0;
1357
1358         table_base = gdt->address;
1359
1360         if (selector & 4) {           /* from ldt */
1361                 u16 ldt_selector = kvm_read_ldt();
1362
1363                 if (!(ldt_selector & ~3))
1364                         return 0;
1365
1366                 table_base = segment_base(ldt_selector);
1367         }
1368         d = (struct desc_struct *)(table_base + (selector & ~7));
1369         v = get_desc_base(d);
1370 #ifdef CONFIG_X86_64
1371        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1372                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1373 #endif
1374         return v;
1375 }
1376
1377 static inline unsigned long kvm_read_tr_base(void)
1378 {
1379         u16 tr;
1380         asm("str %0" : "=g"(tr));
1381         return segment_base(tr);
1382 }
1383
1384 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1385 {
1386         struct vcpu_vmx *vmx = to_vmx(vcpu);
1387         int i;
1388
1389         if (vmx->host_state.loaded)
1390                 return;
1391
1392         vmx->host_state.loaded = 1;
1393         /*
1394          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1395          * allow segment selectors with cpl > 0 or ti == 1.
1396          */
1397         vmx->host_state.ldt_sel = kvm_read_ldt();
1398         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1399         savesegment(fs, vmx->host_state.fs_sel);
1400         if (!(vmx->host_state.fs_sel & 7)) {
1401                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1402                 vmx->host_state.fs_reload_needed = 0;
1403         } else {
1404                 vmcs_write16(HOST_FS_SELECTOR, 0);
1405                 vmx->host_state.fs_reload_needed = 1;
1406         }
1407         savesegment(gs, vmx->host_state.gs_sel);
1408         if (!(vmx->host_state.gs_sel & 7))
1409                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1410         else {
1411                 vmcs_write16(HOST_GS_SELECTOR, 0);
1412                 vmx->host_state.gs_ldt_reload_needed = 1;
1413         }
1414
1415 #ifdef CONFIG_X86_64
1416         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1417         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1418 #else
1419         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1420         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1421 #endif
1422
1423 #ifdef CONFIG_X86_64
1424         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1425         if (is_long_mode(&vmx->vcpu))
1426                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1427 #endif
1428         for (i = 0; i < vmx->save_nmsrs; ++i)
1429                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1430                                    vmx->guest_msrs[i].data,
1431                                    vmx->guest_msrs[i].mask);
1432 }
1433
1434 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1435 {
1436         if (!vmx->host_state.loaded)
1437                 return;
1438
1439         ++vmx->vcpu.stat.host_state_reload;
1440         vmx->host_state.loaded = 0;
1441 #ifdef CONFIG_X86_64
1442         if (is_long_mode(&vmx->vcpu))
1443                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1444 #endif
1445         if (vmx->host_state.gs_ldt_reload_needed) {
1446                 kvm_load_ldt(vmx->host_state.ldt_sel);
1447 #ifdef CONFIG_X86_64
1448                 load_gs_index(vmx->host_state.gs_sel);
1449 #else
1450                 loadsegment(gs, vmx->host_state.gs_sel);
1451 #endif
1452         }
1453         if (vmx->host_state.fs_reload_needed)
1454                 loadsegment(fs, vmx->host_state.fs_sel);
1455         reload_tss();
1456 #ifdef CONFIG_X86_64
1457         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1458 #endif
1459         if (current_thread_info()->status & TS_USEDFPU)
1460                 clts();
1461         load_gdt(&__get_cpu_var(host_gdt));
1462 }
1463
1464 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1465 {
1466         preempt_disable();
1467         __vmx_load_host_state(vmx);
1468         preempt_enable();
1469 }
1470
1471 /*
1472  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1473  * vcpu mutex is already taken.
1474  */
1475 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1476 {
1477         struct vcpu_vmx *vmx = to_vmx(vcpu);
1478         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1479
1480         if (!vmm_exclusive)
1481                 kvm_cpu_vmxon(phys_addr);
1482         else if (vmx->loaded_vmcs->cpu != cpu)
1483                 loaded_vmcs_clear(vmx->loaded_vmcs);
1484
1485         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1486                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1487                 vmcs_load(vmx->loaded_vmcs->vmcs);
1488         }
1489
1490         if (vmx->loaded_vmcs->cpu != cpu) {
1491                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1492                 unsigned long sysenter_esp;
1493
1494                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1495                 local_irq_disable();
1496                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1497                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1498                 local_irq_enable();
1499
1500                 /*
1501                  * Linux uses per-cpu TSS and GDT, so set these when switching
1502                  * processors.
1503                  */
1504                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1505                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1506
1507                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1508                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1509                 vmx->loaded_vmcs->cpu = cpu;
1510         }
1511 }
1512
1513 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1514 {
1515         __vmx_load_host_state(to_vmx(vcpu));
1516         if (!vmm_exclusive) {
1517                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1518                 vcpu->cpu = -1;
1519                 kvm_cpu_vmxoff();
1520         }
1521 }
1522
1523 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1524 {
1525         ulong cr0;
1526
1527         if (vcpu->fpu_active)
1528                 return;
1529         vcpu->fpu_active = 1;
1530         cr0 = vmcs_readl(GUEST_CR0);
1531         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1532         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1533         vmcs_writel(GUEST_CR0, cr0);
1534         update_exception_bitmap(vcpu);
1535         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1536         if (is_guest_mode(vcpu))
1537                 vcpu->arch.cr0_guest_owned_bits &=
1538                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1539         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1540 }
1541
1542 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1543
1544 /*
1545  * Return the cr0 value that a nested guest would read. This is a combination
1546  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1547  * its hypervisor (cr0_read_shadow).
1548  */
1549 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1550 {
1551         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1552                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1553 }
1554 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1555 {
1556         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1557                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1558 }
1559
1560 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1561 {
1562         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1563          * set this *before* calling this function.
1564          */
1565         vmx_decache_cr0_guest_bits(vcpu);
1566         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1567         update_exception_bitmap(vcpu);
1568         vcpu->arch.cr0_guest_owned_bits = 0;
1569         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1570         if (is_guest_mode(vcpu)) {
1571                 /*
1572                  * L1's specified read shadow might not contain the TS bit,
1573                  * so now that we turned on shadowing of this bit, we need to
1574                  * set this bit of the shadow. Like in nested_vmx_run we need
1575                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1576                  * up-to-date here because we just decached cr0.TS (and we'll
1577                  * only update vmcs12->guest_cr0 on nested exit).
1578                  */
1579                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1580                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1581                         (vcpu->arch.cr0 & X86_CR0_TS);
1582                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1583         } else
1584                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1585 }
1586
1587 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1588 {
1589         unsigned long rflags, save_rflags;
1590
1591         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1592                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1593                 rflags = vmcs_readl(GUEST_RFLAGS);
1594                 if (to_vmx(vcpu)->rmode.vm86_active) {
1595                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1596                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1597                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1598                 }
1599                 to_vmx(vcpu)->rflags = rflags;
1600         }
1601         return to_vmx(vcpu)->rflags;
1602 }
1603
1604 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1605 {
1606         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1607         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
1608         to_vmx(vcpu)->rflags = rflags;
1609         if (to_vmx(vcpu)->rmode.vm86_active) {
1610                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1611                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1612         }
1613         vmcs_writel(GUEST_RFLAGS, rflags);
1614 }
1615
1616 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1617 {
1618         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1619         int ret = 0;
1620
1621         if (interruptibility & GUEST_INTR_STATE_STI)
1622                 ret |= KVM_X86_SHADOW_INT_STI;
1623         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1624                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1625
1626         return ret & mask;
1627 }
1628
1629 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1630 {
1631         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1632         u32 interruptibility = interruptibility_old;
1633
1634         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1635
1636         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1637                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1638         else if (mask & KVM_X86_SHADOW_INT_STI)
1639                 interruptibility |= GUEST_INTR_STATE_STI;
1640
1641         if ((interruptibility != interruptibility_old))
1642                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1643 }
1644
1645 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1646 {
1647         unsigned long rip;
1648
1649         rip = kvm_rip_read(vcpu);
1650         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1651         kvm_rip_write(vcpu, rip);
1652
1653         /* skipping an emulated instruction also counts */
1654         vmx_set_interrupt_shadow(vcpu, 0);
1655 }
1656
1657 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1658 {
1659         /* Ensure that we clear the HLT state in the VMCS.  We don't need to
1660          * explicitly skip the instruction because if the HLT state is set, then
1661          * the instruction is already executing and RIP has already been
1662          * advanced. */
1663         if (!yield_on_hlt &&
1664             vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1665                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1666 }
1667
1668 /*
1669  * KVM wants to inject page-faults which it got to the guest. This function
1670  * checks whether in a nested guest, we need to inject them to L1 or L2.
1671  * This function assumes it is called with the exit reason in vmcs02 being
1672  * a #PF exception (this is the only case in which KVM injects a #PF when L2
1673  * is running).
1674  */
1675 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1676 {
1677         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1678
1679         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1680         if (!(vmcs12->exception_bitmap & PF_VECTOR))
1681                 return 0;
1682
1683         nested_vmx_vmexit(vcpu);
1684         return 1;
1685 }
1686
1687 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1688                                 bool has_error_code, u32 error_code,
1689                                 bool reinject)
1690 {
1691         struct vcpu_vmx *vmx = to_vmx(vcpu);
1692         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1693
1694         if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1695                 nested_pf_handled(vcpu))
1696                 return;
1697
1698         if (has_error_code) {
1699                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1700                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1701         }
1702
1703         if (vmx->rmode.vm86_active) {
1704                 int inc_eip = 0;
1705                 if (kvm_exception_is_soft(nr))
1706                         inc_eip = vcpu->arch.event_exit_inst_len;
1707                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1708                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1709                 return;
1710         }
1711
1712         if (kvm_exception_is_soft(nr)) {
1713                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1714                              vmx->vcpu.arch.event_exit_inst_len);
1715                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1716         } else
1717                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1718
1719         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1720         vmx_clear_hlt(vcpu);
1721 }
1722
1723 static bool vmx_rdtscp_supported(void)
1724 {
1725         return cpu_has_vmx_rdtscp();
1726 }
1727
1728 /*
1729  * Swap MSR entry in host/guest MSR entry array.
1730  */
1731 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1732 {
1733         struct shared_msr_entry tmp;
1734
1735         tmp = vmx->guest_msrs[to];
1736         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1737         vmx->guest_msrs[from] = tmp;
1738 }
1739
1740 /*
1741  * Set up the vmcs to automatically save and restore system
1742  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1743  * mode, as fiddling with msrs is very expensive.
1744  */
1745 static void setup_msrs(struct vcpu_vmx *vmx)
1746 {
1747         int save_nmsrs, index;
1748         unsigned long *msr_bitmap;
1749
1750         save_nmsrs = 0;
1751 #ifdef CONFIG_X86_64
1752         if (is_long_mode(&vmx->vcpu)) {
1753                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1754                 if (index >= 0)
1755                         move_msr_up(vmx, index, save_nmsrs++);
1756                 index = __find_msr_index(vmx, MSR_LSTAR);
1757                 if (index >= 0)
1758                         move_msr_up(vmx, index, save_nmsrs++);
1759                 index = __find_msr_index(vmx, MSR_CSTAR);
1760                 if (index >= 0)
1761                         move_msr_up(vmx, index, save_nmsrs++);
1762                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1763                 if (index >= 0 && vmx->rdtscp_enabled)
1764                         move_msr_up(vmx, index, save_nmsrs++);
1765                 /*
1766                  * MSR_STAR is only needed on long mode guests, and only
1767                  * if efer.sce is enabled.
1768                  */
1769                 index = __find_msr_index(vmx, MSR_STAR);
1770                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1771                         move_msr_up(vmx, index, save_nmsrs++);
1772         }
1773 #endif
1774         index = __find_msr_index(vmx, MSR_EFER);
1775         if (index >= 0 && update_transition_efer(vmx, index))
1776                 move_msr_up(vmx, index, save_nmsrs++);
1777
1778         vmx->save_nmsrs = save_nmsrs;
1779
1780         if (cpu_has_vmx_msr_bitmap()) {
1781                 if (is_long_mode(&vmx->vcpu))
1782                         msr_bitmap = vmx_msr_bitmap_longmode;
1783                 else
1784                         msr_bitmap = vmx_msr_bitmap_legacy;
1785
1786                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1787         }
1788 }
1789
1790 /*
1791  * reads and returns guest's timestamp counter "register"
1792  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1793  */
1794 static u64 guest_read_tsc(void)
1795 {
1796         u64 host_tsc, tsc_offset;
1797
1798         rdtscll(host_tsc);
1799         tsc_offset = vmcs_read64(TSC_OFFSET);
1800         return host_tsc + tsc_offset;
1801 }
1802
1803 /*
1804  * Like guest_read_tsc, but always returns L1's notion of the timestamp
1805  * counter, even if a nested guest (L2) is currently running.
1806  */
1807 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu)
1808 {
1809         u64 host_tsc, tsc_offset;
1810
1811         rdtscll(host_tsc);
1812         tsc_offset = is_guest_mode(vcpu) ?
1813                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1814                 vmcs_read64(TSC_OFFSET);
1815         return host_tsc + tsc_offset;
1816 }
1817
1818 /*
1819  * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ
1820  * ioctl. In this case the call-back should update internal vmx state to make
1821  * the changes effective.
1822  */
1823 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1824 {
1825         /* Nothing to do here */
1826 }
1827
1828 /*
1829  * writes 'offset' into guest's timestamp counter offset register
1830  */
1831 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1832 {
1833         if (is_guest_mode(vcpu)) {
1834                 /*
1835                  * We're here if L1 chose not to trap WRMSR to TSC. According
1836                  * to the spec, this should set L1's TSC; The offset that L1
1837                  * set for L2 remains unchanged, and still needs to be added
1838                  * to the newly set TSC to get L2's TSC.
1839                  */
1840                 struct vmcs12 *vmcs12;
1841                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1842                 /* recalculate vmcs02.TSC_OFFSET: */
1843                 vmcs12 = get_vmcs12(vcpu);
1844                 vmcs_write64(TSC_OFFSET, offset +
1845                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1846                          vmcs12->tsc_offset : 0));
1847         } else {
1848                 vmcs_write64(TSC_OFFSET, offset);
1849         }
1850 }
1851
1852 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1853 {
1854         u64 offset = vmcs_read64(TSC_OFFSET);
1855         vmcs_write64(TSC_OFFSET, offset + adjustment);
1856         if (is_guest_mode(vcpu)) {
1857                 /* Even when running L2, the adjustment needs to apply to L1 */
1858                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1859         }
1860 }
1861
1862 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1863 {
1864         return target_tsc - native_read_tsc();
1865 }
1866
1867 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1868 {
1869         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1870         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1871 }
1872
1873 /*
1874  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1875  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1876  * all guests if the "nested" module option is off, and can also be disabled
1877  * for a single guest by disabling its VMX cpuid bit.
1878  */
1879 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1880 {
1881         return nested && guest_cpuid_has_vmx(vcpu);
1882 }
1883
1884 /*
1885  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1886  * returned for the various VMX controls MSRs when nested VMX is enabled.
1887  * The same values should also be used to verify that vmcs12 control fields are
1888  * valid during nested entry from L1 to L2.
1889  * Each of these control msrs has a low and high 32-bit half: A low bit is on
1890  * if the corresponding bit in the (32-bit) control field *must* be on, and a
1891  * bit in the high half is on if the corresponding bit in the control field
1892  * may be on. See also vmx_control_verify().
1893  * TODO: allow these variables to be modified (downgraded) by module options
1894  * or other means.
1895  */
1896 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1897 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1898 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1899 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1900 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1901 static __init void nested_vmx_setup_ctls_msrs(void)
1902 {
1903         /*
1904          * Note that as a general rule, the high half of the MSRs (bits in
1905          * the control fields which may be 1) should be initialized by the
1906          * intersection of the underlying hardware's MSR (i.e., features which
1907          * can be supported) and the list of features we want to expose -
1908          * because they are known to be properly supported in our code.
1909          * Also, usually, the low half of the MSRs (bits which must be 1) can
1910          * be set to 0, meaning that L1 may turn off any of these bits. The
1911          * reason is that if one of these bits is necessary, it will appear
1912          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1913          * fields of vmcs01 and vmcs02, will turn these bits off - and
1914          * nested_vmx_exit_handled() will not pass related exits to L1.
1915          * These rules have exceptions below.
1916          */
1917
1918         /* pin-based controls */
1919         /*
1920          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1921          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1922          */
1923         nested_vmx_pinbased_ctls_low = 0x16 ;
1924         nested_vmx_pinbased_ctls_high = 0x16 |
1925                 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1926                 PIN_BASED_VIRTUAL_NMIS;
1927
1928         /* exit controls */
1929         nested_vmx_exit_ctls_low = 0;
1930         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
1931 #ifdef CONFIG_X86_64
1932         nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1933 #else
1934         nested_vmx_exit_ctls_high = 0;
1935 #endif
1936
1937         /* entry controls */
1938         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1939                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1940         nested_vmx_entry_ctls_low = 0;
1941         nested_vmx_entry_ctls_high &=
1942                 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1943
1944         /* cpu-based controls */
1945         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1946                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1947         nested_vmx_procbased_ctls_low = 0;
1948         nested_vmx_procbased_ctls_high &=
1949                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1950                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1951                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1952                 CPU_BASED_CR3_STORE_EXITING |
1953 #ifdef CONFIG_X86_64
1954                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1955 #endif
1956                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1957                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1958                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1959         /*
1960          * We can allow some features even when not supported by the
1961          * hardware. For example, L1 can specify an MSR bitmap - and we
1962          * can use it to avoid exits to L1 - even when L0 runs L2
1963          * without MSR bitmaps.
1964          */
1965         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
1966
1967         /* secondary cpu-based controls */
1968         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
1969                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
1970         nested_vmx_secondary_ctls_low = 0;
1971         nested_vmx_secondary_ctls_high &=
1972                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1973 }
1974
1975 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
1976 {
1977         /*
1978          * Bits 0 in high must be 0, and bits 1 in low must be 1.
1979          */
1980         return ((control & high) | low) == control;
1981 }
1982
1983 static inline u64 vmx_control_msr(u32 low, u32 high)
1984 {
1985         return low | ((u64)high << 32);
1986 }
1987
1988 /*
1989  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
1990  * also let it use VMX-specific MSRs.
1991  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
1992  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
1993  * like all other MSRs).
1994  */
1995 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1996 {
1997         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
1998                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
1999                 /*
2000                  * According to the spec, processors which do not support VMX
2001                  * should throw a #GP(0) when VMX capability MSRs are read.
2002                  */
2003                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2004                 return 1;
2005         }
2006
2007         switch (msr_index) {
2008         case MSR_IA32_FEATURE_CONTROL:
2009                 *pdata = 0;
2010                 break;
2011         case MSR_IA32_VMX_BASIC:
2012                 /*
2013                  * This MSR reports some information about VMX support. We
2014                  * should return information about the VMX we emulate for the
2015                  * guest, and the VMCS structure we give it - not about the
2016                  * VMX support of the underlying hardware.
2017                  */
2018                 *pdata = VMCS12_REVISION |
2019                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2020                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2021                 break;
2022         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2023         case MSR_IA32_VMX_PINBASED_CTLS:
2024                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2025                                         nested_vmx_pinbased_ctls_high);
2026                 break;
2027         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2028         case MSR_IA32_VMX_PROCBASED_CTLS:
2029                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2030                                         nested_vmx_procbased_ctls_high);
2031                 break;
2032         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2033         case MSR_IA32_VMX_EXIT_CTLS:
2034                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2035                                         nested_vmx_exit_ctls_high);
2036                 break;
2037         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2038         case MSR_IA32_VMX_ENTRY_CTLS:
2039                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2040                                         nested_vmx_entry_ctls_high);
2041                 break;
2042         case MSR_IA32_VMX_MISC:
2043                 *pdata = 0;
2044                 break;
2045         /*
2046          * These MSRs specify bits which the guest must keep fixed (on or off)
2047          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2048          * We picked the standard core2 setting.
2049          */
2050 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2051 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2052         case MSR_IA32_VMX_CR0_FIXED0:
2053                 *pdata = VMXON_CR0_ALWAYSON;
2054                 break;
2055         case MSR_IA32_VMX_CR0_FIXED1:
2056                 *pdata = -1ULL;
2057                 break;
2058         case MSR_IA32_VMX_CR4_FIXED0:
2059                 *pdata = VMXON_CR4_ALWAYSON;
2060                 break;
2061         case MSR_IA32_VMX_CR4_FIXED1:
2062                 *pdata = -1ULL;
2063                 break;
2064         case MSR_IA32_VMX_VMCS_ENUM:
2065                 *pdata = 0x1f;
2066                 break;
2067         case MSR_IA32_VMX_PROCBASED_CTLS2:
2068                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2069                                         nested_vmx_secondary_ctls_high);
2070                 break;
2071         case MSR_IA32_VMX_EPT_VPID_CAP:
2072                 /* Currently, no nested ept or nested vpid */
2073                 *pdata = 0;
2074                 break;
2075         default:
2076                 return 0;
2077         }
2078
2079         return 1;
2080 }
2081
2082 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2083 {
2084         if (!nested_vmx_allowed(vcpu))
2085                 return 0;
2086
2087         if (msr_index == MSR_IA32_FEATURE_CONTROL)
2088                 /* TODO: the right thing. */
2089                 return 1;
2090         /*
2091          * No need to treat VMX capability MSRs specially: If we don't handle
2092          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2093          */
2094         return 0;
2095 }
2096
2097 /*
2098  * Reads an msr value (of 'msr_index') into 'pdata'.
2099  * Returns 0 on success, non-0 otherwise.
2100  * Assumes vcpu_load() was already called.
2101  */
2102 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2103 {
2104         u64 data;
2105         struct shared_msr_entry *msr;
2106
2107         if (!pdata) {
2108                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2109                 return -EINVAL;
2110         }
2111
2112         switch (msr_index) {
2113 #ifdef CONFIG_X86_64
2114         case MSR_FS_BASE:
2115                 data = vmcs_readl(GUEST_FS_BASE);
2116                 break;
2117         case MSR_GS_BASE:
2118                 data = vmcs_readl(GUEST_GS_BASE);
2119                 break;
2120         case MSR_KERNEL_GS_BASE:
2121                 vmx_load_host_state(to_vmx(vcpu));
2122                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2123                 break;
2124 #endif
2125         case MSR_EFER:
2126                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2127         case MSR_IA32_TSC:
2128                 data = guest_read_tsc();
2129                 break;
2130         case MSR_IA32_SYSENTER_CS:
2131                 data = vmcs_read32(GUEST_SYSENTER_CS);
2132                 break;
2133         case MSR_IA32_SYSENTER_EIP:
2134                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2135                 break;
2136         case MSR_IA32_SYSENTER_ESP:
2137                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2138                 break;
2139         case MSR_TSC_AUX:
2140                 if (!to_vmx(vcpu)->rdtscp_enabled)
2141                         return 1;
2142                 /* Otherwise falls through */
2143         default:
2144                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2145                         return 0;
2146                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2147                 if (msr) {
2148                         data = msr->data;
2149                         break;
2150                 }
2151                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2152         }
2153
2154         *pdata = data;
2155         return 0;
2156 }
2157
2158 /*
2159  * Writes msr value into into the appropriate "register".
2160  * Returns 0 on success, non-0 otherwise.
2161  * Assumes vcpu_load() was already called.
2162  */
2163 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2164 {
2165         struct vcpu_vmx *vmx = to_vmx(vcpu);
2166         struct shared_msr_entry *msr;
2167         int ret = 0;
2168
2169         switch (msr_index) {
2170         case MSR_EFER:
2171                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2172                 break;
2173 #ifdef CONFIG_X86_64
2174         case MSR_FS_BASE:
2175                 vmx_segment_cache_clear(vmx);
2176                 vmcs_writel(GUEST_FS_BASE, data);
2177                 break;
2178         case MSR_GS_BASE:
2179                 vmx_segment_cache_clear(vmx);
2180                 vmcs_writel(GUEST_GS_BASE, data);
2181                 break;
2182         case MSR_KERNEL_GS_BASE:
2183                 vmx_load_host_state(vmx);
2184                 vmx->msr_guest_kernel_gs_base = data;
2185                 break;
2186 #endif
2187         case MSR_IA32_SYSENTER_CS:
2188                 vmcs_write32(GUEST_SYSENTER_CS, data);
2189                 break;
2190         case MSR_IA32_SYSENTER_EIP:
2191                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2192                 break;
2193         case MSR_IA32_SYSENTER_ESP:
2194                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2195                 break;
2196         case MSR_IA32_TSC:
2197                 kvm_write_tsc(vcpu, data);
2198                 break;
2199         case MSR_IA32_CR_PAT:
2200                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2201                         vmcs_write64(GUEST_IA32_PAT, data);
2202                         vcpu->arch.pat = data;
2203                         break;
2204                 }
2205                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2206                 break;
2207         case MSR_TSC_AUX:
2208                 if (!vmx->rdtscp_enabled)
2209                         return 1;
2210                 /* Check reserved bit, higher 32 bits should be zero */
2211                 if ((data >> 32) != 0)
2212                         return 1;
2213                 /* Otherwise falls through */
2214         default:
2215                 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2216                         break;
2217                 msr = find_msr_entry(vmx, msr_index);
2218                 if (msr) {
2219                         msr->data = data;
2220                         break;
2221                 }
2222                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2223         }
2224
2225         return ret;
2226 }
2227
2228 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2229 {
2230         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2231         switch (reg) {
2232         case VCPU_REGS_RSP:
2233                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2234                 break;
2235         case VCPU_REGS_RIP:
2236                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2237                 break;
2238         case VCPU_EXREG_PDPTR:
2239                 if (enable_ept)
2240                         ept_save_pdptrs(vcpu);
2241                 break;
2242         default:
2243                 break;
2244         }
2245 }
2246
2247 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
2248 {
2249         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2250                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2251         else
2252                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2253
2254         update_exception_bitmap(vcpu);
2255 }
2256
2257 static __init int cpu_has_kvm_support(void)
2258 {
2259         return cpu_has_vmx();
2260 }
2261
2262 static __init int vmx_disabled_by_bios(void)
2263 {
2264         u64 msr;
2265
2266         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2267         if (msr & FEATURE_CONTROL_LOCKED) {
2268                 /* launched w/ TXT and VMX disabled */
2269                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2270                         && tboot_enabled())
2271                         return 1;
2272                 /* launched w/o TXT and VMX only enabled w/ TXT */
2273                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2274                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2275                         && !tboot_enabled()) {
2276                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2277                                 "activate TXT before enabling KVM\n");
2278                         return 1;
2279                 }
2280                 /* launched w/o TXT and VMX disabled */
2281                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2282                         && !tboot_enabled())
2283                         return 1;
2284         }
2285
2286         return 0;
2287 }
2288
2289 static void kvm_cpu_vmxon(u64 addr)
2290 {
2291         asm volatile (ASM_VMX_VMXON_RAX
2292                         : : "a"(&addr), "m"(addr)
2293                         : "memory", "cc");
2294 }
2295
2296 static int hardware_enable(void *garbage)
2297 {
2298         int cpu = raw_smp_processor_id();
2299         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2300         u64 old, test_bits;
2301
2302         if (read_cr4() & X86_CR4_VMXE)
2303                 return -EBUSY;
2304
2305         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2306         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2307
2308         test_bits = FEATURE_CONTROL_LOCKED;
2309         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2310         if (tboot_enabled())
2311                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2312
2313         if ((old & test_bits) != test_bits) {
2314                 /* enable and lock */
2315                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2316         }
2317         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2318
2319         if (vmm_exclusive) {
2320                 kvm_cpu_vmxon(phys_addr);
2321                 ept_sync_global();
2322         }
2323
2324         store_gdt(&__get_cpu_var(host_gdt));
2325
2326         return 0;
2327 }
2328
2329 static void vmclear_local_loaded_vmcss(void)
2330 {
2331         int cpu = raw_smp_processor_id();
2332         struct loaded_vmcs *v, *n;
2333
2334         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2335                                  loaded_vmcss_on_cpu_link)
2336                 __loaded_vmcs_clear(v);
2337 }
2338
2339
2340 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2341  * tricks.
2342  */
2343 static void kvm_cpu_vmxoff(void)
2344 {
2345         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2346 }
2347
2348 static void hardware_disable(void *garbage)
2349 {
2350         if (vmm_exclusive) {
2351                 vmclear_local_loaded_vmcss();
2352                 kvm_cpu_vmxoff();
2353         }
2354         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2355 }
2356
2357 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2358                                       u32 msr, u32 *result)
2359 {
2360         u32 vmx_msr_low, vmx_msr_high;
2361         u32 ctl = ctl_min | ctl_opt;
2362
2363         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2364
2365         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2366         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2367
2368         /* Ensure minimum (required) set of control bits are supported. */
2369         if (ctl_min & ~ctl)
2370                 return -EIO;
2371
2372         *result = ctl;
2373         return 0;
2374 }
2375
2376 static __init bool allow_1_setting(u32 msr, u32 ctl)
2377 {
2378         u32 vmx_msr_low, vmx_msr_high;
2379
2380         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2381         return vmx_msr_high & ctl;
2382 }
2383
2384 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2385 {
2386         u32 vmx_msr_low, vmx_msr_high;
2387         u32 min, opt, min2, opt2;
2388         u32 _pin_based_exec_control = 0;
2389         u32 _cpu_based_exec_control = 0;
2390         u32 _cpu_based_2nd_exec_control = 0;
2391         u32 _vmexit_control = 0;
2392         u32 _vmentry_control = 0;
2393
2394         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2395         opt = PIN_BASED_VIRTUAL_NMIS;
2396         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2397                                 &_pin_based_exec_control) < 0)
2398                 return -EIO;
2399
2400         min =
2401 #ifdef CONFIG_X86_64
2402               CPU_BASED_CR8_LOAD_EXITING |
2403               CPU_BASED_CR8_STORE_EXITING |
2404 #endif
2405               CPU_BASED_CR3_LOAD_EXITING |
2406               CPU_BASED_CR3_STORE_EXITING |
2407               CPU_BASED_USE_IO_BITMAPS |
2408               CPU_BASED_MOV_DR_EXITING |
2409               CPU_BASED_USE_TSC_OFFSETING |
2410               CPU_BASED_MWAIT_EXITING |
2411               CPU_BASED_MONITOR_EXITING |
2412               CPU_BASED_INVLPG_EXITING;
2413
2414         if (yield_on_hlt)
2415                 min |= CPU_BASED_HLT_EXITING;
2416
2417         opt = CPU_BASED_TPR_SHADOW |
2418               CPU_BASED_USE_MSR_BITMAPS |
2419               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2420         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2421                                 &_cpu_based_exec_control) < 0)
2422                 return -EIO;
2423 #ifdef CONFIG_X86_64
2424         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2425                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2426                                            ~CPU_BASED_CR8_STORE_EXITING;
2427 #endif
2428         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2429                 min2 = 0;
2430                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2431                         SECONDARY_EXEC_WBINVD_EXITING |
2432                         SECONDARY_EXEC_ENABLE_VPID |
2433                         SECONDARY_EXEC_ENABLE_EPT |
2434                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2435                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2436                         SECONDARY_EXEC_RDTSCP;
2437                 if (adjust_vmx_controls(min2, opt2,
2438                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2439                                         &_cpu_based_2nd_exec_control) < 0)
2440                         return -EIO;
2441         }
2442 #ifndef CONFIG_X86_64
2443         if (!(_cpu_based_2nd_exec_control &
2444                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2445                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2446 #endif
2447         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2448                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2449                    enabled */
2450                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2451                                              CPU_BASED_CR3_STORE_EXITING |
2452                                              CPU_BASED_INVLPG_EXITING);
2453                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2454                       vmx_capability.ept, vmx_capability.vpid);
2455         }
2456
2457         min = 0;
2458 #ifdef CONFIG_X86_64
2459         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2460 #endif
2461         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2462         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2463                                 &_vmexit_control) < 0)
2464                 return -EIO;
2465
2466         min = 0;
2467         opt = VM_ENTRY_LOAD_IA32_PAT;
2468         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2469                                 &_vmentry_control) < 0)
2470                 return -EIO;
2471
2472         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2473
2474         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2475         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2476                 return -EIO;
2477
2478 #ifdef CONFIG_X86_64
2479         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2480         if (vmx_msr_high & (1u<<16))
2481                 return -EIO;
2482 #endif
2483
2484         /* Require Write-Back (WB) memory type for VMCS accesses. */
2485         if (((vmx_msr_high >> 18) & 15) != 6)
2486                 return -EIO;
2487
2488         vmcs_conf->size = vmx_msr_high & 0x1fff;
2489         vmcs_conf->order = get_order(vmcs_config.size);
2490         vmcs_conf->revision_id = vmx_msr_low;
2491
2492         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2493         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2494         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2495         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2496         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2497
2498         cpu_has_load_ia32_efer =
2499                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2500                                 VM_ENTRY_LOAD_IA32_EFER)
2501                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2502                                    VM_EXIT_LOAD_IA32_EFER);
2503
2504         cpu_has_load_perf_global_ctrl =
2505                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2506                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2507                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2508                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2509
2510         /*
2511          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2512          * but due to arrata below it can't be used. Workaround is to use
2513          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2514          *
2515          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2516          *
2517          * AAK155             (model 26)
2518          * AAP115             (model 30)
2519          * AAT100             (model 37)
2520          * BC86,AAY89,BD102   (model 44)
2521          * BA97               (model 46)
2522          *
2523          */
2524         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2525                 switch (boot_cpu_data.x86_model) {
2526                 case 26:
2527                 case 30:
2528                 case 37:
2529                 case 44:
2530                 case 46:
2531                         cpu_has_load_perf_global_ctrl = false;
2532                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2533                                         "does not work properly. Using workaround\n");
2534                         break;
2535                 default:
2536                         break;
2537                 }
2538         }
2539
2540         return 0;
2541 }
2542
2543 static struct vmcs *alloc_vmcs_cpu(int cpu)
2544 {
2545         int node = cpu_to_node(cpu);
2546         struct page *pages;
2547         struct vmcs *vmcs;
2548
2549         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2550         if (!pages)
2551                 return NULL;
2552         vmcs = page_address(pages);
2553         memset(vmcs, 0, vmcs_config.size);
2554         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2555         return vmcs;
2556 }
2557
2558 static struct vmcs *alloc_vmcs(void)
2559 {
2560         return alloc_vmcs_cpu(raw_smp_processor_id());
2561 }
2562
2563 static void free_vmcs(struct vmcs *vmcs)
2564 {
2565         free_pages((unsigned long)vmcs, vmcs_config.order);
2566 }
2567
2568 /*
2569  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2570  */
2571 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2572 {
2573         if (!loaded_vmcs->vmcs)
2574                 return;
2575         loaded_vmcs_clear(loaded_vmcs);
2576         free_vmcs(loaded_vmcs->vmcs);
2577         loaded_vmcs->vmcs = NULL;
2578 }
2579
2580 static void free_kvm_area(void)
2581 {
2582         int cpu;
2583
2584         for_each_possible_cpu(cpu) {
2585                 free_vmcs(per_cpu(vmxarea, cpu));
2586                 per_cpu(vmxarea, cpu) = NULL;
2587         }
2588 }
2589
2590 static __init int alloc_kvm_area(void)
2591 {
2592         int cpu;
2593
2594         for_each_possible_cpu(cpu) {
2595                 struct vmcs *vmcs;
2596
2597                 vmcs = alloc_vmcs_cpu(cpu);
2598                 if (!vmcs) {
2599                         free_kvm_area();
2600                         return -ENOMEM;
2601                 }
2602
2603                 per_cpu(vmxarea, cpu) = vmcs;
2604         }
2605         return 0;
2606 }
2607
2608 static __init int hardware_setup(void)
2609 {
2610         if (setup_vmcs_config(&vmcs_config) < 0)
2611                 return -EIO;
2612
2613         if (boot_cpu_has(X86_FEATURE_NX))
2614                 kvm_enable_efer_bits(EFER_NX);
2615
2616         if (!cpu_has_vmx_vpid())
2617                 enable_vpid = 0;
2618
2619         if (!cpu_has_vmx_ept() ||
2620             !cpu_has_vmx_ept_4levels()) {
2621                 enable_ept = 0;
2622                 enable_unrestricted_guest = 0;
2623         }
2624
2625         if (!cpu_has_vmx_unrestricted_guest())
2626                 enable_unrestricted_guest = 0;
2627
2628         if (!cpu_has_vmx_flexpriority())
2629                 flexpriority_enabled = 0;
2630
2631         if (!cpu_has_vmx_tpr_shadow())
2632                 kvm_x86_ops->update_cr8_intercept = NULL;
2633
2634         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2635                 kvm_disable_largepages();
2636
2637         if (!cpu_has_vmx_ple())
2638                 ple_gap = 0;
2639
2640         if (nested)
2641                 nested_vmx_setup_ctls_msrs();
2642
2643         return alloc_kvm_area();
2644 }
2645
2646 static __exit void hardware_unsetup(void)
2647 {
2648         free_kvm_area();
2649 }
2650
2651 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2652 {
2653         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2654
2655         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
2656                 vmcs_write16(sf->selector, save->selector);
2657                 vmcs_writel(sf->base, save->base);
2658                 vmcs_write32(sf->limit, save->limit);
2659                 vmcs_write32(sf->ar_bytes, save->ar);
2660         } else {
2661                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2662                         << AR_DPL_SHIFT;
2663                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2664         }
2665 }
2666
2667 static void enter_pmode(struct kvm_vcpu *vcpu)
2668 {
2669         unsigned long flags;
2670         struct vcpu_vmx *vmx = to_vmx(vcpu);
2671
2672         vmx->emulation_required = 1;
2673         vmx->rmode.vm86_active = 0;
2674
2675         vmx_segment_cache_clear(vmx);
2676
2677         vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
2678         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2679         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2680         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
2681
2682         flags = vmcs_readl(GUEST_RFLAGS);
2683         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2684         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2685         vmcs_writel(GUEST_RFLAGS, flags);
2686
2687         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2688                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2689
2690         update_exception_bitmap(vcpu);
2691
2692         if (emulate_invalid_guest_state)
2693                 return;
2694
2695         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2696         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2697         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2698         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
2699
2700         vmx_segment_cache_clear(vmx);
2701
2702         vmcs_write16(GUEST_SS_SELECTOR, 0);
2703         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2704
2705         vmcs_write16(GUEST_CS_SELECTOR,
2706                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2707         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2708 }
2709
2710 static gva_t rmode_tss_base(struct kvm *kvm)
2711 {
2712         if (!kvm->arch.tss_addr) {
2713                 struct kvm_memslots *slots;
2714                 struct kvm_memory_slot *slot;
2715                 gfn_t base_gfn;
2716
2717                 slots = kvm_memslots(kvm);
2718                 slot = id_to_memslot(slots, 0);
2719                 base_gfn = slot->base_gfn + slot->npages - 3;
2720
2721                 return base_gfn << PAGE_SHIFT;
2722         }
2723         return kvm->arch.tss_addr;
2724 }
2725
2726 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2727 {
2728         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2729
2730         save->selector = vmcs_read16(sf->selector);
2731         save->base = vmcs_readl(sf->base);
2732         save->limit = vmcs_read32(sf->limit);
2733         save->ar = vmcs_read32(sf->ar_bytes);
2734         vmcs_write16(sf->selector, save->base >> 4);
2735         vmcs_write32(sf->base, save->base & 0xffff0);
2736         vmcs_write32(sf->limit, 0xffff);
2737         vmcs_write32(sf->ar_bytes, 0xf3);
2738         if (save->base & 0xf)
2739                 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2740                             " aligned when entering protected mode (seg=%d)",
2741                             seg);
2742 }
2743
2744 static void enter_rmode(struct kvm_vcpu *vcpu)
2745 {
2746         unsigned long flags;
2747         struct vcpu_vmx *vmx = to_vmx(vcpu);
2748
2749         if (enable_unrestricted_guest)
2750                 return;
2751
2752         vmx->emulation_required = 1;
2753         vmx->rmode.vm86_active = 1;
2754
2755         /*
2756          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2757          * vcpu. Call it here with phys address pointing 16M below 4G.
2758          */
2759         if (!vcpu->kvm->arch.tss_addr) {
2760                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2761                              "called before entering vcpu\n");
2762                 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2763                 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2764                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2765         }
2766
2767         vmx_segment_cache_clear(vmx);
2768
2769         vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
2770         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
2771         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2772
2773         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
2774         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2775
2776         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
2777         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2778
2779         flags = vmcs_readl(GUEST_RFLAGS);
2780         vmx->rmode.save_rflags = flags;
2781
2782         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2783
2784         vmcs_writel(GUEST_RFLAGS, flags);
2785         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2786         update_exception_bitmap(vcpu);
2787
2788         if (emulate_invalid_guest_state)
2789                 goto continue_rmode;
2790
2791         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
2792         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
2793         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
2794
2795         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
2796         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
2797         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
2798                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
2799         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
2800
2801         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
2802         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
2803         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
2804         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
2805
2806 continue_rmode:
2807         kvm_mmu_reset_context(vcpu);
2808 }
2809
2810 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2811 {
2812         struct vcpu_vmx *vmx = to_vmx(vcpu);
2813         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2814
2815         if (!msr)
2816                 return;
2817
2818         /*
2819          * Force kernel_gs_base reloading before EFER changes, as control
2820          * of this msr depends on is_long_mode().
2821          */
2822         vmx_load_host_state(to_vmx(vcpu));
2823         vcpu->arch.efer = efer;
2824         if (efer & EFER_LMA) {
2825                 vmcs_write32(VM_ENTRY_CONTROLS,
2826                              vmcs_read32(VM_ENTRY_CONTROLS) |
2827                              VM_ENTRY_IA32E_MODE);
2828                 msr->data = efer;
2829         } else {
2830                 vmcs_write32(VM_ENTRY_CONTROLS,
2831                              vmcs_read32(VM_ENTRY_CONTROLS) &
2832                              ~VM_ENTRY_IA32E_MODE);
2833
2834                 msr->data = efer & ~EFER_LME;
2835         }
2836         setup_msrs(vmx);
2837 }
2838
2839 #ifdef CONFIG_X86_64
2840
2841 static void enter_lmode(struct kvm_vcpu *vcpu)
2842 {
2843         u32 guest_tr_ar;
2844
2845         vmx_segment_cache_clear(to_vmx(vcpu));
2846
2847         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2848         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2849                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2850                                      __func__);
2851                 vmcs_write32(GUEST_TR_AR_BYTES,
2852                              (guest_tr_ar & ~AR_TYPE_MASK)
2853                              | AR_TYPE_BUSY_64_TSS);
2854         }
2855         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2856 }
2857
2858 static void exit_lmode(struct kvm_vcpu *vcpu)
2859 {
2860         vmcs_write32(VM_ENTRY_CONTROLS,
2861                      vmcs_read32(VM_ENTRY_CONTROLS)
2862                      & ~VM_ENTRY_IA32E_MODE);
2863         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2864 }
2865
2866 #endif
2867
2868 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2869 {
2870         vpid_sync_context(to_vmx(vcpu));
2871         if (enable_ept) {
2872                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2873                         return;
2874                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2875         }
2876 }
2877
2878 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2879 {
2880         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2881
2882         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2883         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2884 }
2885
2886 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2887 {
2888         if (enable_ept && is_paging(vcpu))
2889                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2890         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2891 }
2892
2893 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2894 {
2895         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2896
2897         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2898         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2899 }
2900
2901 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2902 {
2903         if (!test_bit(VCPU_EXREG_PDPTR,
2904                       (unsigned long *)&vcpu->arch.regs_dirty))
2905                 return;
2906
2907         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2908                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2909                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2910                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2911                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
2912         }
2913 }
2914
2915 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2916 {
2917         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2918                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2919                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2920                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2921                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2922         }
2923
2924         __set_bit(VCPU_EXREG_PDPTR,
2925                   (unsigned long *)&vcpu->arch.regs_avail);
2926         __set_bit(VCPU_EXREG_PDPTR,
2927                   (unsigned long *)&vcpu->arch.regs_dirty);
2928 }
2929
2930 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2931
2932 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2933                                         unsigned long cr0,
2934                                         struct kvm_vcpu *vcpu)
2935 {
2936         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2937                 vmx_decache_cr3(vcpu);
2938         if (!(cr0 & X86_CR0_PG)) {
2939                 /* From paging/starting to nonpaging */
2940                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2941                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
2942                              (CPU_BASED_CR3_LOAD_EXITING |
2943                               CPU_BASED_CR3_STORE_EXITING));
2944                 vcpu->arch.cr0 = cr0;
2945                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2946         } else if (!is_paging(vcpu)) {
2947                 /* From nonpaging to paging */
2948                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2949                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
2950                              ~(CPU_BASED_CR3_LOAD_EXITING |
2951                                CPU_BASED_CR3_STORE_EXITING));
2952                 vcpu->arch.cr0 = cr0;
2953                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2954         }
2955
2956         if (!(cr0 & X86_CR0_WP))
2957                 *hw_cr0 &= ~X86_CR0_WP;
2958 }
2959
2960 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2961 {
2962         struct vcpu_vmx *vmx = to_vmx(vcpu);
2963         unsigned long hw_cr0;
2964
2965         if (enable_unrestricted_guest)
2966                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2967                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2968         else
2969                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
2970
2971         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2972                 enter_pmode(vcpu);
2973
2974         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2975                 enter_rmode(vcpu);
2976
2977 #ifdef CONFIG_X86_64
2978         if (vcpu->arch.efer & EFER_LME) {
2979                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2980                         enter_lmode(vcpu);
2981                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2982                         exit_lmode(vcpu);
2983         }
2984 #endif
2985
2986         if (enable_ept)
2987                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2988
2989         if (!vcpu->fpu_active)
2990                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
2991
2992         vmcs_writel(CR0_READ_SHADOW, cr0);
2993         vmcs_writel(GUEST_CR0, hw_cr0);
2994         vcpu->arch.cr0 = cr0;
2995         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2996 }
2997
2998 static u64 construct_eptp(unsigned long root_hpa)
2999 {
3000         u64 eptp;
3001
3002         /* TODO write the value reading from MSR */
3003         eptp = VMX_EPT_DEFAULT_MT |
3004                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3005         eptp |= (root_hpa & PAGE_MASK);
3006
3007         return eptp;
3008 }
3009
3010 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3011 {
3012         unsigned long guest_cr3;
3013         u64 eptp;
3014
3015         guest_cr3 = cr3;
3016         if (enable_ept) {
3017                 eptp = construct_eptp(cr3);
3018                 vmcs_write64(EPT_POINTER, eptp);
3019                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3020                         vcpu->kvm->arch.ept_identity_map_addr;
3021                 ept_load_pdptrs(vcpu);
3022         }
3023
3024         vmx_flush_tlb(vcpu);
3025         vmcs_writel(GUEST_CR3, guest_cr3);
3026 }
3027
3028 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3029 {
3030         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3031                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3032
3033         if (cr4 & X86_CR4_VMXE) {
3034                 /*
3035                  * To use VMXON (and later other VMX instructions), a guest
3036                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3037                  * So basically the check on whether to allow nested VMX
3038                  * is here.
3039                  */
3040                 if (!nested_vmx_allowed(vcpu))
3041                         return 1;
3042         } else if (to_vmx(vcpu)->nested.vmxon)
3043                 return 1;
3044
3045         vcpu->arch.cr4 = cr4;
3046         if (enable_ept) {
3047                 if (!is_paging(vcpu)) {
3048                         hw_cr4 &= ~X86_CR4_PAE;
3049                         hw_cr4 |= X86_CR4_PSE;
3050                 } else if (!(cr4 & X86_CR4_PAE)) {
3051                         hw_cr4 &= ~X86_CR4_PAE;
3052                 }
3053         }
3054
3055         vmcs_writel(CR4_READ_SHADOW, cr4);
3056         vmcs_writel(GUEST_CR4, hw_cr4);
3057         return 0;
3058 }
3059
3060 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3061                             struct kvm_segment *var, int seg)
3062 {
3063         struct vcpu_vmx *vmx = to_vmx(vcpu);
3064         struct kvm_save_segment *save;
3065         u32 ar;
3066
3067         if (vmx->rmode.vm86_active
3068             && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
3069                 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
3070                 || seg == VCPU_SREG_GS)
3071             && !emulate_invalid_guest_state) {
3072                 switch (seg) {
3073                 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
3074                 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
3075                 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
3076                 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
3077                 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
3078                 default: BUG();
3079                 }
3080                 var->selector = save->selector;
3081                 var->base = save->base;
3082                 var->limit = save->limit;
3083                 ar = save->ar;
3084                 if (seg == VCPU_SREG_TR
3085                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3086                         goto use_saved_rmode_seg;
3087         }
3088         var->base = vmx_read_guest_seg_base(vmx, seg);
3089         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3090         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3091         ar = vmx_read_guest_seg_ar(vmx, seg);
3092 use_saved_rmode_seg:
3093         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
3094                 ar = 0;
3095         var->type = ar & 15;
3096         var->s = (ar >> 4) & 1;
3097         var->dpl = (ar >> 5) & 3;
3098         var->present = (ar >> 7) & 1;
3099         var->avl = (ar >> 12) & 1;
3100         var->l = (ar >> 13) & 1;
3101         var->db = (ar >> 14) & 1;
3102         var->g = (ar >> 15) & 1;
3103         var->unusable = (ar >> 16) & 1;
3104 }
3105
3106 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3107 {
3108         struct kvm_segment s;
3109
3110         if (to_vmx(vcpu)->rmode.vm86_active) {
3111                 vmx_get_segment(vcpu, &s, seg);
3112                 return s.base;
3113         }
3114         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3115 }
3116
3117 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
3118 {
3119         if (!is_protmode(vcpu))
3120                 return 0;
3121
3122         if (!is_long_mode(vcpu)
3123             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3124                 return 3;
3125
3126         return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
3127 }
3128
3129 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3130 {
3131         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3132                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3133                 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
3134         }
3135         return to_vmx(vcpu)->cpl;
3136 }
3137
3138
3139 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3140 {
3141         u32 ar;
3142
3143         if (var->unusable)
3144                 ar = 1 << 16;
3145         else {
3146                 ar = var->type & 15;
3147                 ar |= (var->s & 1) << 4;
3148                 ar |= (var->dpl & 3) << 5;
3149                 ar |= (var->present & 1) << 7;
3150                 ar |= (var->avl & 1) << 12;
3151                 ar |= (var->l & 1) << 13;
3152                 ar |= (var->db & 1) << 14;
3153                 ar |= (var->g & 1) << 15;
3154         }
3155         if (ar == 0) /* a 0 value means unusable */
3156                 ar = AR_UNUSABLE_MASK;
3157
3158         return ar;
3159 }
3160
3161 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3162                             struct kvm_segment *var, int seg)
3163 {
3164         struct vcpu_vmx *vmx = to_vmx(vcpu);
3165         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3166         u32 ar;
3167
3168         vmx_segment_cache_clear(vmx);
3169
3170         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
3171                 vmcs_write16(sf->selector, var->selector);
3172                 vmx->rmode.tr.selector = var->selector;
3173                 vmx->rmode.tr.base = var->base;
3174                 vmx->rmode.tr.limit = var->limit;
3175                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
3176                 return;
3177         }
3178         vmcs_writel(sf->base, var->base);
3179         vmcs_write32(sf->limit, var->limit);
3180         vmcs_write16(sf->selector, var->selector);
3181         if (vmx->rmode.vm86_active && var->s) {
3182                 /*
3183                  * Hack real-mode segments into vm86 compatibility.
3184                  */
3185                 if (var->base == 0xffff0000 && var->selector == 0xf000)
3186                         vmcs_writel(sf->base, 0xf0000);
3187                 ar = 0xf3;
3188         } else
3189                 ar = vmx_segment_access_rights(var);
3190
3191         /*
3192          *   Fix the "Accessed" bit in AR field of segment registers for older
3193          * qemu binaries.
3194          *   IA32 arch specifies that at the time of processor reset the
3195          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3196          * is setting it to 0 in the usedland code. This causes invalid guest
3197          * state vmexit when "unrestricted guest" mode is turned on.
3198          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3199          * tree. Newer qemu binaries with that qemu fix would not need this
3200          * kvm hack.
3201          */
3202         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3203                 ar |= 0x1; /* Accessed */
3204
3205         vmcs_write32(sf->ar_bytes, ar);
3206         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3207 }
3208
3209 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3210 {
3211         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3212
3213         *db = (ar >> 14) & 1;
3214         *l = (ar >> 13) & 1;
3215 }
3216
3217 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3218 {
3219         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3220         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3221 }
3222
3223 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3224 {
3225         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3226         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3227 }
3228
3229 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3230 {
3231         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3232         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3233 }
3234
3235 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3236 {
3237         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3238         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3239 }
3240
3241 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3242 {
3243         struct kvm_segment var;
3244         u32 ar;
3245
3246         vmx_get_segment(vcpu, &var, seg);
3247         ar = vmx_segment_access_rights(&var);
3248
3249         if (var.base != (var.selector << 4))
3250                 return false;
3251         if (var.limit != 0xffff)
3252                 return false;
3253         if (ar != 0xf3)
3254                 return false;
3255
3256         return true;
3257 }
3258
3259 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3260 {
3261         struct kvm_segment cs;
3262         unsigned int cs_rpl;
3263
3264         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3265         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3266
3267         if (cs.unusable)
3268                 return false;
3269         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3270                 return false;
3271         if (!cs.s)
3272                 return false;
3273         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3274                 if (cs.dpl > cs_rpl)
3275                         return false;
3276         } else {
3277                 if (cs.dpl != cs_rpl)
3278                         return false;
3279         }
3280         if (!cs.present)
3281                 return false;
3282
3283         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3284         return true;
3285 }
3286
3287 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3288 {
3289         struct kvm_segment ss;
3290         unsigned int ss_rpl;
3291
3292         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3293         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3294
3295         if (ss.unusable)
3296                 return true;
3297         if (ss.type != 3 && ss.type != 7)
3298                 return false;
3299         if (!ss.s)
3300                 return false;
3301         if (ss.dpl != ss_rpl) /* DPL != RPL */
3302                 return false;
3303         if (!ss.present)
3304                 return false;
3305
3306         return true;
3307 }
3308
3309 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3310 {
3311         struct kvm_segment var;
3312         unsigned int rpl;
3313
3314         vmx_get_segment(vcpu, &var, seg);
3315         rpl = var.selector & SELECTOR_RPL_MASK;
3316
3317         if (var.unusable)
3318                 return true;
3319         if (!var.s)
3320                 return false;
3321         if (!var.present)
3322                 return false;
3323         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3324                 if (var.dpl < rpl) /* DPL < RPL */
3325                         return false;
3326         }
3327
3328         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3329          * rights flags
3330          */
3331         return true;
3332 }
3333
3334 static bool tr_valid(struct kvm_vcpu *vcpu)
3335 {
3336         struct kvm_segment tr;
3337
3338         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3339
3340         if (tr.unusable)
3341                 return false;
3342         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3343                 return false;
3344         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3345                 return false;
3346         if (!tr.present)
3347                 return false;
3348
3349         return true;
3350 }
3351
3352 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3353 {
3354         struct kvm_segment ldtr;
3355
3356         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3357
3358         if (ldtr.unusable)
3359                 return true;
3360         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3361                 return false;
3362         if (ldtr.type != 2)
3363                 return false;
3364         if (!ldtr.present)
3365                 return false;
3366
3367         return true;
3368 }
3369
3370 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3371 {
3372         struct kvm_segment cs, ss;
3373
3374         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3375         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3376
3377         return ((cs.selector & SELECTOR_RPL_MASK) ==
3378                  (ss.selector & SELECTOR_RPL_MASK));
3379 }
3380
3381 /*
3382  * Check if guest state is valid. Returns true if valid, false if
3383  * not.
3384  * We assume that registers are always usable
3385  */
3386 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3387 {
3388         /* real mode guest state checks */
3389         if (!is_protmode(vcpu)) {
3390                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3391                         return false;
3392                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3393                         return false;
3394                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3395                         return false;
3396                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3397                         return false;
3398                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3399                         return false;
3400                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3401                         return false;
3402         } else {
3403         /* protected mode guest state checks */
3404                 if (!cs_ss_rpl_check(vcpu))
3405                         return false;
3406                 if (!code_segment_valid(vcpu))
3407                         return false;
3408                 if (!stack_segment_valid(vcpu))
3409                         return false;
3410                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3411                         return false;
3412                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3413                         return false;
3414                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3415                         return false;
3416                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3417                         return false;
3418                 if (!tr_valid(vcpu))
3419                         return false;
3420                 if (!ldtr_valid(vcpu))
3421                         return false;
3422         }
3423         /* TODO:
3424          * - Add checks on RIP
3425          * - Add checks on RFLAGS
3426          */
3427
3428         return true;
3429 }
3430
3431 static int init_rmode_tss(struct kvm *kvm)
3432 {
3433         gfn_t fn;
3434         u16 data = 0;
3435         int r, idx, ret = 0;
3436
3437         idx = srcu_read_lock(&kvm->srcu);
3438         fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3439         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3440         if (r < 0)
3441                 goto out;
3442         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3443         r = kvm_write_guest_page(kvm, fn++, &data,
3444                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3445         if (r < 0)
3446                 goto out;
3447         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3448         if (r < 0)
3449                 goto out;
3450         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3451         if (r < 0)
3452                 goto out;
3453         data = ~0;
3454         r = kvm_write_guest_page(kvm, fn, &data,
3455                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3456                                  sizeof(u8));
3457         if (r < 0)
3458                 goto out;
3459
3460         ret = 1;
3461 out:
3462         srcu_read_unlock(&kvm->srcu, idx);
3463         return ret;
3464 }
3465
3466 static int init_rmode_identity_map(struct kvm *kvm)
3467 {
3468         int i, idx, r, ret;
3469         pfn_t identity_map_pfn;
3470         u32 tmp;
3471
3472         if (!enable_ept)
3473                 return 1;
3474         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3475                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3476                         "haven't been allocated!\n");
3477                 return 0;
3478         }
3479         if (likely(kvm->arch.ept_identity_pagetable_done))
3480                 return 1;
3481         ret = 0;
3482         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3483         idx = srcu_read_lock(&kvm->srcu);
3484         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3485         if (r < 0)
3486                 goto out;
3487         /* Set up identity-mapping pagetable for EPT in real mode */
3488         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3489                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3490                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3491                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3492                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3493                 if (r < 0)
3494                         goto out;
3495         }
3496         kvm->arch.ept_identity_pagetable_done = true;
3497         ret = 1;
3498 out:
3499         srcu_read_unlock(&kvm->srcu, idx);
3500         return ret;
3501 }
3502
3503 static void seg_setup(int seg)
3504 {
3505         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3506         unsigned int ar;
3507
3508         vmcs_write16(sf->selector, 0);
3509         vmcs_writel(sf->base, 0);
3510         vmcs_write32(sf->limit, 0xffff);
3511         if (enable_unrestricted_guest) {
3512                 ar = 0x93;
3513                 if (seg == VCPU_SREG_CS)
3514                         ar |= 0x08; /* code segment */
3515         } else
3516                 ar = 0xf3;
3517
3518         vmcs_write32(sf->ar_bytes, ar);
3519 }
3520
3521 static int alloc_apic_access_page(struct kvm *kvm)
3522 {
3523         struct kvm_userspace_memory_region kvm_userspace_mem;
3524         int r = 0;
3525
3526         mutex_lock(&kvm->slots_lock);
3527         if (kvm->arch.apic_access_page)
3528                 goto out;
3529         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3530         kvm_userspace_mem.flags = 0;
3531         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3532         kvm_userspace_mem.memory_size = PAGE_SIZE;
3533         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3534         if (r)
3535                 goto out;
3536
3537         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
3538 out:
3539         mutex_unlock(&kvm->slots_lock);
3540         return r;
3541 }
3542
3543 static int alloc_identity_pagetable(struct kvm *kvm)
3544 {
3545         struct kvm_userspace_memory_region kvm_userspace_mem;
3546         int r = 0;
3547
3548         mutex_lock(&kvm->slots_lock);
3549         if (kvm->arch.ept_identity_pagetable)
3550                 goto out;
3551         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3552         kvm_userspace_mem.flags = 0;
3553         kvm_userspace_mem.guest_phys_addr =
3554                 kvm->arch.ept_identity_map_addr;
3555         kvm_userspace_mem.memory_size = PAGE_SIZE;
3556         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3557         if (r)
3558                 goto out;
3559
3560         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
3561                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3562 out:
3563         mutex_unlock(&kvm->slots_lock);
3564         return r;
3565 }
3566
3567 static void allocate_vpid(struct vcpu_vmx *vmx)
3568 {
3569         int vpid;
3570
3571         vmx->vpid = 0;
3572         if (!enable_vpid)
3573                 return;
3574         spin_lock(&vmx_vpid_lock);
3575         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3576         if (vpid < VMX_NR_VPIDS) {
3577                 vmx->vpid = vpid;
3578                 __set_bit(vpid, vmx_vpid_bitmap);
3579         }
3580         spin_unlock(&vmx_vpid_lock);
3581 }
3582
3583 static void free_vpid(struct vcpu_vmx *vmx)
3584 {
3585         if (!enable_vpid)
3586                 return;
3587         spin_lock(&vmx_vpid_lock);
3588         if (vmx->vpid != 0)
3589                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3590         spin_unlock(&vmx_vpid_lock);
3591 }
3592
3593 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
3594 {
3595         int f = sizeof(unsigned long);
3596
3597         if (!cpu_has_vmx_msr_bitmap())
3598                 return;
3599
3600         /*
3601          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3602          * have the write-low and read-high bitmap offsets the wrong way round.
3603          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3604          */
3605         if (msr <= 0x1fff) {
3606                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3607                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
3608         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3609                 msr &= 0x1fff;
3610                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3611                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
3612         }
3613 }
3614
3615 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3616 {
3617         if (!longmode_only)
3618                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3619         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3620 }
3621
3622 /*
3623  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3624  * will not change in the lifetime of the guest.
3625  * Note that host-state that does change is set elsewhere. E.g., host-state
3626  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3627  */
3628 static void vmx_set_constant_host_state(void)
3629 {
3630         u32 low32, high32;
3631         unsigned long tmpl;
3632         struct desc_ptr dt;
3633
3634         vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS);  /* 22.2.3 */
3635         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
3636         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
3637
3638         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
3639         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3640         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3641         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3642         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
3643
3644         native_store_idt(&dt);
3645         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
3646
3647         asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3648         vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3649
3650         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3651         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3652         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3653         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
3654
3655         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3656                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3657                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3658         }
3659 }
3660
3661 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3662 {
3663         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3664         if (enable_ept)
3665                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3666         if (is_guest_mode(&vmx->vcpu))
3667                 vmx->vcpu.arch.cr4_guest_owned_bits &=
3668                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3669         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3670 }
3671
3672 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3673 {
3674         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3675         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3676                 exec_control &= ~CPU_BASED_TPR_SHADOW;
3677 #ifdef CONFIG_X86_64
3678                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3679                                 CPU_BASED_CR8_LOAD_EXITING;
3680 #endif
3681         }
3682         if (!enable_ept)
3683                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3684                                 CPU_BASED_CR3_LOAD_EXITING  |
3685                                 CPU_BASED_INVLPG_EXITING;
3686         return exec_control;
3687 }
3688
3689 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3690 {
3691         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3692         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3693                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3694         if (vmx->vpid == 0)
3695                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3696         if (!enable_ept) {
3697                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3698                 enable_unrestricted_guest = 0;
3699         }
3700         if (!enable_unrestricted_guest)
3701                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3702         if (!ple_gap)
3703                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3704         return exec_control;
3705 }
3706
3707 static void ept_set_mmio_spte_mask(void)
3708 {
3709         /*
3710          * EPT Misconfigurations can be generated if the value of bits 2:0
3711          * of an EPT paging-structure entry is 110b (write/execute).
3712          * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3713          * spte.
3714          */
3715         kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3716 }
3717
3718 /*
3719  * Sets up the vmcs for emulated real mode.
3720  */
3721 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
3722 {
3723 #ifdef CONFIG_X86_64
3724         unsigned long a;
3725 #endif
3726         int i;
3727
3728         /* I/O */
3729         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3730         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
3731
3732         if (cpu_has_vmx_msr_bitmap())
3733                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
3734
3735         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3736
3737         /* Control */
3738         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3739                 vmcs_config.pin_based_exec_ctrl);
3740
3741         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
3742
3743         if (cpu_has_secondary_exec_ctrls()) {
3744                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3745                                 vmx_secondary_exec_control(vmx));
3746         }
3747
3748         if (ple_gap) {
3749                 vmcs_write32(PLE_GAP, ple_gap);
3750                 vmcs_write32(PLE_WINDOW, ple_window);
3751         }
3752
3753         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3754         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
3755         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
3756
3757         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
3758         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
3759         vmx_set_constant_host_state();
3760 #ifdef CONFIG_X86_64
3761         rdmsrl(MSR_FS_BASE, a);
3762         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3763         rdmsrl(MSR_GS_BASE, a);
3764         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3765 #else
3766         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3767         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3768 #endif
3769
3770         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3771         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
3772         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
3773         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
3774         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
3775
3776         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3777                 u32 msr_low, msr_high;
3778                 u64 host_pat;
3779                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3780                 host_pat = msr_low | ((u64) msr_high << 32);
3781                 /* Write the default value follow host pat */
3782                 vmcs_write64(GUEST_IA32_PAT, host_pat);
3783                 /* Keep arch.pat sync with GUEST_IA32_PAT */
3784                 vmx->vcpu.arch.pat = host_pat;
3785         }
3786
3787         for (i = 0; i < NR_VMX_MSR; ++i) {
3788                 u32 index = vmx_msr_index[i];
3789                 u32 data_low, data_high;
3790                 int j = vmx->nmsrs;
3791
3792                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3793                         continue;
3794                 if (wrmsr_safe(index, data_low, data_high) < 0)
3795                         continue;
3796                 vmx->guest_msrs[j].index = i;
3797                 vmx->guest_msrs[j].data = 0;
3798                 vmx->guest_msrs[j].mask = -1ull;
3799                 ++vmx->nmsrs;
3800         }
3801
3802         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
3803
3804         /* 22.2.1, 20.8.1 */
3805         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3806
3807         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
3808         set_cr4_guest_host_mask(vmx);
3809
3810         kvm_write_tsc(&vmx->vcpu, 0);
3811
3812         return 0;
3813 }
3814
3815 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3816 {
3817         struct vcpu_vmx *vmx = to_vmx(vcpu);
3818         u64 msr;
3819         int ret;
3820
3821         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3822
3823         vmx->rmode.vm86_active = 0;
3824
3825         vmx->soft_vnmi_blocked = 0;
3826
3827         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
3828         kvm_set_cr8(&vmx->vcpu, 0);
3829         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
3830         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3831                 msr |= MSR_IA32_APICBASE_BSP;
3832         kvm_set_apic_base(&vmx->vcpu, msr);
3833
3834         ret = fx_init(&vmx->vcpu);
3835         if (ret != 0)
3836                 goto out;
3837
3838         vmx_segment_cache_clear(vmx);
3839
3840         seg_setup(VCPU_SREG_CS);
3841         /*
3842          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3843          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
3844          */
3845         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
3846                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3847                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3848         } else {
3849                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3850                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
3851         }
3852
3853         seg_setup(VCPU_SREG_DS);
3854         seg_setup(VCPU_SREG_ES);
3855         seg_setup(VCPU_SREG_FS);
3856         seg_setup(VCPU_SREG_GS);
3857         seg_setup(VCPU_SREG_SS);
3858
3859         vmcs_write16(GUEST_TR_SELECTOR, 0);
3860         vmcs_writel(GUEST_TR_BASE, 0);
3861         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3862         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3863
3864         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3865         vmcs_writel(GUEST_LDTR_BASE, 0);
3866         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3867         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3868
3869         vmcs_write32(GUEST_SYSENTER_CS, 0);
3870         vmcs_writel(GUEST_SYSENTER_ESP, 0);
3871         vmcs_writel(GUEST_SYSENTER_EIP, 0);
3872
3873         vmcs_writel(GUEST_RFLAGS, 0x02);
3874         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3875                 kvm_rip_write(vcpu, 0xfff0);
3876         else
3877                 kvm_rip_write(vcpu, 0);
3878         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
3879
3880         vmcs_writel(GUEST_DR7, 0x400);
3881
3882         vmcs_writel(GUEST_GDTR_BASE, 0);
3883         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3884
3885         vmcs_writel(GUEST_IDTR_BASE, 0);
3886         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3887
3888         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3889         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3890         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3891
3892         /* Special registers */
3893         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3894
3895         setup_msrs(vmx);
3896
3897         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
3898
3899         if (cpu_has_vmx_tpr_shadow()) {
3900                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3901                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3902                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
3903                                      __pa(vmx->vcpu.arch.apic->regs));
3904                 vmcs_write32(TPR_THRESHOLD, 0);
3905         }
3906
3907         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3908                 vmcs_write64(APIC_ACCESS_ADDR,
3909                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
3910
3911         if (vmx->vpid != 0)
3912                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3913
3914         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
3915         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
3916         vmx_set_cr4(&vmx->vcpu, 0);
3917         vmx_set_efer(&vmx->vcpu, 0);
3918         vmx_fpu_activate(&vmx->vcpu);
3919         update_exception_bitmap(&vmx->vcpu);
3920
3921         vpid_sync_context(vmx);
3922
3923         ret = 0;
3924
3925         /* HACK: Don't enable emulation on guest boot/reset */
3926         vmx->emulation_required = 0;
3927
3928 out:
3929         return ret;
3930 }
3931
3932 /*
3933  * In nested virtualization, check if L1 asked to exit on external interrupts.
3934  * For most existing hypervisors, this will always return true.
3935  */
3936 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
3937 {
3938         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
3939                 PIN_BASED_EXT_INTR_MASK;
3940 }
3941
3942 static void enable_irq_window(struct kvm_vcpu *vcpu)
3943 {
3944         u32 cpu_based_vm_exec_control;
3945         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
3946                 /*
3947                  * We get here if vmx_interrupt_allowed() said we can't
3948                  * inject to L1 now because L2 must run. Ask L2 to exit
3949                  * right after entry, so we can inject to L1 more promptly.
3950                  */
3951                 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
3952                 return;
3953         }
3954
3955         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3956         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
3957         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3958 }
3959
3960 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3961 {
3962         u32 cpu_based_vm_exec_control;
3963
3964         if (!cpu_has_virtual_nmis()) {
3965                 enable_irq_window(vcpu);
3966                 return;
3967         }
3968
3969         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
3970                 enable_irq_window(vcpu);
3971                 return;
3972         }
3973         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3974         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
3975         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3976 }
3977
3978 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
3979 {
3980         struct vcpu_vmx *vmx = to_vmx(vcpu);
3981         uint32_t intr;
3982         int irq = vcpu->arch.interrupt.nr;
3983
3984         trace_kvm_inj_virq(irq);
3985
3986         ++vcpu->stat.irq_injections;
3987         if (vmx->rmode.vm86_active) {
3988                 int inc_eip = 0;
3989                 if (vcpu->arch.interrupt.soft)
3990                         inc_eip = vcpu->arch.event_exit_inst_len;
3991                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
3992                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3993                 return;
3994         }
3995         intr = irq | INTR_INFO_VALID_MASK;
3996         if (vcpu->arch.interrupt.soft) {
3997                 intr |= INTR_TYPE_SOFT_INTR;
3998                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3999                              vmx->vcpu.arch.event_exit_inst_len);
4000         } else
4001                 intr |= INTR_TYPE_EXT_INTR;
4002         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4003         vmx_clear_hlt(vcpu);
4004 }
4005
4006 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4007 {
4008         struct vcpu_vmx *vmx = to_vmx(vcpu);
4009
4010         if (is_guest_mode(vcpu))
4011                 return;
4012
4013         if (!cpu_has_virtual_nmis()) {
4014                 /*
4015                  * Tracking the NMI-blocked state in software is built upon
4016                  * finding the next open IRQ window. This, in turn, depends on
4017                  * well-behaving guests: They have to keep IRQs disabled at
4018                  * least as long as the NMI handler runs. Otherwise we may
4019                  * cause NMI nesting, maybe breaking the guest. But as this is
4020                  * highly unlikely, we can live with the residual risk.
4021                  */
4022                 vmx->soft_vnmi_blocked = 1;
4023                 vmx->vnmi_blocked_time = 0;
4024         }
4025
4026         ++vcpu->stat.nmi_injections;
4027         vmx->nmi_known_unmasked = false;
4028         if (vmx->rmode.vm86_active) {
4029                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4030                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4031                 return;
4032         }
4033         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4034                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4035         vmx_clear_hlt(vcpu);
4036 }
4037
4038 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4039 {
4040         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4041                 return 0;
4042
4043         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4044                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4045                    | GUEST_INTR_STATE_NMI));
4046 }
4047
4048 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4049 {
4050         if (!cpu_has_virtual_nmis())
4051                 return to_vmx(vcpu)->soft_vnmi_blocked;
4052         if (to_vmx(vcpu)->nmi_known_unmasked)
4053                 return false;
4054         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4055 }
4056
4057 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4058 {
4059         struct vcpu_vmx *vmx = to_vmx(vcpu);
4060
4061         if (!cpu_has_virtual_nmis()) {
4062                 if (vmx->soft_vnmi_blocked != masked) {
4063                         vmx->soft_vnmi_blocked = masked;
4064                         vmx->vnmi_blocked_time = 0;
4065                 }
4066         } else {
4067                 vmx->nmi_known_unmasked = !masked;
4068                 if (masked)
4069                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4070                                       GUEST_INTR_STATE_NMI);
4071                 else
4072                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4073                                         GUEST_INTR_STATE_NMI);
4074         }
4075 }
4076
4077 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4078 {
4079         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4080                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4081                 if (to_vmx(vcpu)->nested.nested_run_pending ||
4082                     (vmcs12->idt_vectoring_info_field &
4083                      VECTORING_INFO_VALID_MASK))
4084                         return 0;
4085                 nested_vmx_vmexit(vcpu);
4086                 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4087                 vmcs12->vm_exit_intr_info = 0;
4088                 /* fall through to normal code, but now in L1, not L2 */
4089         }
4090
4091         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4092                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4093                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4094 }
4095
4096 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4097 {
4098         int ret;
4099         struct kvm_userspace_memory_region tss_mem = {
4100                 .slot = TSS_PRIVATE_MEMSLOT,
4101                 .guest_phys_addr = addr,
4102                 .memory_size = PAGE_SIZE * 3,
4103                 .flags = 0,
4104         };
4105
4106         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
4107         if (ret)
4108                 return ret;
4109         kvm->arch.tss_addr = addr;
4110         if (!init_rmode_tss(kvm))
4111                 return  -ENOMEM;
4112
4113         return 0;
4114 }
4115
4116 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4117                                   int vec, u32 err_code)
4118 {
4119         /*
4120          * Instruction with address size override prefix opcode 0x67
4121          * Cause the #SS fault with 0 error code in VM86 mode.
4122          */
4123         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
4124                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
4125                         return 1;
4126         /*
4127          * Forward all other exceptions that are valid in real mode.
4128          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4129          *        the required debugging infrastructure rework.
4130          */
4131         switch (vec) {
4132         case DB_VECTOR:
4133                 if (vcpu->guest_debug &
4134                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4135                         return 0;
4136                 kvm_queue_exception(vcpu, vec);
4137                 return 1;
4138         case BP_VECTOR:
4139                 /*
4140                  * Update instruction length as we may reinject the exception
4141                  * from user space while in guest debugging mode.
4142                  */
4143                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4144                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4145                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4146                         return 0;
4147                 /* fall through */
4148         case DE_VECTOR:
4149         case OF_VECTOR:
4150         case BR_VECTOR:
4151         case UD_VECTOR:
4152         case DF_VECTOR:
4153         case SS_VECTOR:
4154         case GP_VECTOR:
4155         case MF_VECTOR:
4156                 kvm_queue_exception(vcpu, vec);
4157                 return 1;
4158         }
4159         return 0;
4160 }
4161
4162 /*
4163  * Trigger machine check on the host. We assume all the MSRs are already set up
4164  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4165  * We pass a fake environment to the machine check handler because we want
4166  * the guest to be always treated like user space, no matter what context
4167  * it used internally.
4168  */
4169 static void kvm_machine_check(void)
4170 {
4171 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4172         struct pt_regs regs = {
4173                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4174                 .flags = X86_EFLAGS_IF,
4175         };
4176
4177         do_machine_check(&regs, 0);
4178 #endif
4179 }
4180
4181 static int handle_machine_check(struct kvm_vcpu *vcpu)
4182 {
4183         /* already handled by vcpu_run */
4184         return 1;
4185 }
4186
4187 static int handle_exception(struct kvm_vcpu *vcpu)
4188 {
4189         struct vcpu_vmx *vmx = to_vmx(vcpu);
4190         struct kvm_run *kvm_run = vcpu->run;
4191         u32 intr_info, ex_no, error_code;
4192         unsigned long cr2, rip, dr6;
4193         u32 vect_info;
4194         enum emulation_result er;
4195
4196         vect_info = vmx->idt_vectoring_info;
4197         intr_info = vmx->exit_intr_info;
4198
4199         if (is_machine_check(intr_info))
4200                 return handle_machine_check(vcpu);
4201
4202         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4203             !is_page_fault(intr_info)) {
4204                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4205                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4206                 vcpu->run->internal.ndata = 2;
4207                 vcpu->run->internal.data[0] = vect_info;
4208                 vcpu->run->internal.data[1] = intr_info;
4209                 return 0;
4210         }
4211
4212         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4213                 return 1;  /* already handled by vmx_vcpu_run() */
4214
4215         if (is_no_device(intr_info)) {
4216                 vmx_fpu_activate(vcpu);
4217                 return 1;
4218         }
4219
4220         if (is_invalid_opcode(intr_info)) {
4221                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4222                 if (er != EMULATE_DONE)
4223                         kvm_queue_exception(vcpu, UD_VECTOR);
4224                 return 1;
4225         }
4226
4227         error_code = 0;
4228         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4229                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4230         if (is_page_fault(intr_info)) {
4231                 /* EPT won't cause page fault directly */
4232                 BUG_ON(enable_ept);
4233                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4234                 trace_kvm_page_fault(cr2, error_code);
4235
4236                 if (kvm_event_needs_reinjection(vcpu))
4237                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4238                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4239         }
4240
4241         if (vmx->rmode.vm86_active &&
4242             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
4243                                                                 error_code)) {
4244                 if (vcpu->arch.halt_request) {
4245                         vcpu->arch.halt_request = 0;
4246                         return kvm_emulate_halt(vcpu);
4247                 }
4248                 return 1;
4249         }
4250
4251         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4252         switch (ex_no) {
4253         case DB_VECTOR:
4254                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4255                 if (!(vcpu->guest_debug &
4256                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4257                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4258                         kvm_queue_exception(vcpu, DB_VECTOR);
4259                         return 1;
4260                 }
4261                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4262                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4263                 /* fall through */
4264         case BP_VECTOR:
4265                 /*
4266                  * Update instruction length as we may reinject #BP from
4267                  * user space while in guest debugging mode. Reading it for
4268                  * #DB as well causes no harm, it is not used in that case.
4269                  */
4270                 vmx->vcpu.arch.event_exit_inst_len =
4271                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4272                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4273                 rip = kvm_rip_read(vcpu);
4274                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4275                 kvm_run->debug.arch.exception = ex_no;
4276                 break;
4277         default:
4278                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4279                 kvm_run->ex.exception = ex_no;
4280                 kvm_run->ex.error_code = error_code;
4281                 break;
4282         }
4283         return 0;
4284 }
4285
4286 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4287 {
4288         ++vcpu->stat.irq_exits;
4289         return 1;
4290 }
4291
4292 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4293 {
4294         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4295         return 0;
4296 }
4297
4298 static int handle_io(struct kvm_vcpu *vcpu)
4299 {
4300         unsigned long exit_qualification;
4301         int size, in, string;
4302         unsigned port;
4303
4304         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4305         string = (exit_qualification & 16) != 0;
4306         in = (exit_qualification & 8) != 0;
4307
4308         ++vcpu->stat.io_exits;
4309
4310         if (string || in)
4311                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4312
4313         port = exit_qualification >> 16;
4314         size = (exit_qualification & 7) + 1;
4315         skip_emulated_instruction(vcpu);
4316
4317         return kvm_fast_pio_out(vcpu, size, port);
4318 }
4319
4320 static void
4321 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4322 {
4323         /*
4324          * Patch in the VMCALL instruction:
4325          */
4326         hypercall[0] = 0x0f;
4327         hypercall[1] = 0x01;
4328         hypercall[2] = 0xc1;
4329 }
4330
4331 /* called to set cr0 as approriate for a mov-to-cr0 exit. */
4332 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4333 {
4334         if (to_vmx(vcpu)->nested.vmxon &&
4335             ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4336                 return 1;
4337
4338         if (is_guest_mode(vcpu)) {
4339                 /*
4340                  * We get here when L2 changed cr0 in a way that did not change
4341                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4342                  * but did change L0 shadowed bits. This can currently happen
4343                  * with the TS bit: L0 may want to leave TS on (for lazy fpu
4344                  * loading) while pretending to allow the guest to change it.
4345                  */
4346                 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4347                          (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4348                         return 1;
4349                 vmcs_writel(CR0_READ_SHADOW, val);
4350                 return 0;
4351         } else
4352                 return kvm_set_cr0(vcpu, val);
4353 }
4354
4355 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4356 {
4357         if (is_guest_mode(vcpu)) {
4358                 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4359                          (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4360                         return 1;
4361                 vmcs_writel(CR4_READ_SHADOW, val);
4362                 return 0;
4363         } else
4364                 return kvm_set_cr4(vcpu, val);
4365 }
4366
4367 /* called to set cr0 as approriate for clts instruction exit. */
4368 static void handle_clts(struct kvm_vcpu *vcpu)
4369 {
4370         if (is_guest_mode(vcpu)) {
4371                 /*
4372                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4373                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4374                  * just pretend it's off (also in arch.cr0 for fpu_activate).
4375                  */
4376                 vmcs_writel(CR0_READ_SHADOW,
4377                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4378                 vcpu->arch.cr0 &= ~X86_CR0_TS;
4379         } else
4380                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4381 }
4382
4383 static int handle_cr(struct kvm_vcpu *vcpu)
4384 {
4385         unsigned long exit_qualification, val;
4386         int cr;
4387         int reg;
4388         int err;
4389
4390         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4391         cr = exit_qualification & 15;
4392         reg = (exit_qualification >> 8) & 15;
4393         switch ((exit_qualification >> 4) & 3) {
4394         case 0: /* mov to cr */
4395                 val = kvm_register_read(vcpu, reg);
4396                 trace_kvm_cr_write(cr, val);
4397                 switch (cr) {
4398                 case 0:
4399                         err = handle_set_cr0(vcpu, val);
4400                         kvm_complete_insn_gp(vcpu, err);
4401                         return 1;
4402                 case 3:
4403                         err = kvm_set_cr3(vcpu, val);
4404                         kvm_complete_insn_gp(vcpu, err);
4405                         return 1;
4406                 case 4:
4407                         err = handle_set_cr4(vcpu, val);
4408                         kvm_complete_insn_gp(vcpu, err);
4409                         return 1;
4410                 case 8: {
4411                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4412                                 u8 cr8 = kvm_register_read(vcpu, reg);
4413                                 err = kvm_set_cr8(vcpu, cr8);
4414                                 kvm_complete_insn_gp(vcpu, err);
4415                                 if (irqchip_in_kernel(vcpu->kvm))
4416                                         return 1;
4417                                 if (cr8_prev <= cr8)
4418                                         return 1;
4419                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4420                                 return 0;
4421                         }
4422                 };
4423                 break;
4424         case 2: /* clts */
4425                 handle_clts(vcpu);
4426                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4427                 skip_emulated_instruction(vcpu);
4428                 vmx_fpu_activate(vcpu);
4429                 return 1;
4430         case 1: /*mov from cr*/
4431                 switch (cr) {
4432                 case 3:
4433                         val = kvm_read_cr3(vcpu);
4434                         kvm_register_write(vcpu, reg, val);
4435                         trace_kvm_cr_read(cr, val);
4436                         skip_emulated_instruction(vcpu);
4437                         return 1;
4438                 case 8:
4439                         val = kvm_get_cr8(vcpu);
4440                         kvm_register_write(vcpu, reg, val);
4441                         trace_kvm_cr_read(cr, val);
4442                         skip_emulated_instruction(vcpu);
4443                         return 1;
4444                 }
4445                 break;
4446         case 3: /* lmsw */
4447                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4448                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4449                 kvm_lmsw(vcpu, val);
4450
4451                 skip_emulated_instruction(vcpu);
4452                 return 1;
4453         default:
4454                 break;
4455         }
4456         vcpu->run->exit_reason = 0;
4457         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4458                (int)(exit_qualification >> 4) & 3, cr);
4459         return 0;
4460 }
4461
4462 static int handle_dr(struct kvm_vcpu *vcpu)
4463 {
4464         unsigned long exit_qualification;
4465         int dr, reg;
4466
4467         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4468         if (!kvm_require_cpl(vcpu, 0))
4469                 return 1;
4470         dr = vmcs_readl(GUEST_DR7);
4471         if (dr & DR7_GD) {
4472                 /*
4473                  * As the vm-exit takes precedence over the debug trap, we
4474                  * need to emulate the latter, either for the host or the
4475                  * guest debugging itself.
4476                  */
4477                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4478                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4479                         vcpu->run->debug.arch.dr7 = dr;
4480                         vcpu->run->debug.arch.pc =
4481                                 vmcs_readl(GUEST_CS_BASE) +
4482                                 vmcs_readl(GUEST_RIP);
4483                         vcpu->run->debug.arch.exception = DB_VECTOR;
4484                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4485                         return 0;
4486                 } else {
4487                         vcpu->arch.dr7 &= ~DR7_GD;
4488                         vcpu->arch.dr6 |= DR6_BD;
4489                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4490                         kvm_queue_exception(vcpu, DB_VECTOR);
4491                         return 1;
4492                 }
4493         }
4494
4495         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4496         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4497         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4498         if (exit_qualification & TYPE_MOV_FROM_DR) {
4499                 unsigned long val;
4500                 if (!kvm_get_dr(vcpu, dr, &val))
4501                         kvm_register_write(vcpu, reg, val);
4502         } else
4503                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
4504         skip_emulated_instruction(vcpu);
4505         return 1;
4506 }
4507
4508 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4509 {
4510         vmcs_writel(GUEST_DR7, val);
4511 }
4512
4513 static int handle_cpuid(struct kvm_vcpu *vcpu)
4514 {
4515         kvm_emulate_cpuid(vcpu);
4516         return 1;
4517 }
4518
4519 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4520 {
4521         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4522         u64 data;
4523
4524         if (vmx_get_msr(vcpu, ecx, &data)) {
4525                 trace_kvm_msr_read_ex(ecx);
4526                 kvm_inject_gp(vcpu, 0);
4527                 return 1;
4528         }
4529
4530         trace_kvm_msr_read(ecx, data);
4531
4532         /* FIXME: handling of bits 32:63 of rax, rdx */
4533         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4534         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
4535         skip_emulated_instruction(vcpu);
4536         return 1;
4537 }
4538
4539 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4540 {
4541         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4542         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4543                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4544
4545         if (vmx_set_msr(vcpu, ecx, data) != 0) {
4546                 trace_kvm_msr_write_ex(ecx, data);
4547                 kvm_inject_gp(vcpu, 0);
4548                 return 1;
4549         }
4550
4551         trace_kvm_msr_write(ecx, data);
4552         skip_emulated_instruction(vcpu);
4553         return 1;
4554 }
4555
4556 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4557 {
4558         kvm_make_request(KVM_REQ_EVENT, vcpu);
4559         return 1;
4560 }
4561
4562 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4563 {
4564         u32 cpu_based_vm_exec_control;
4565
4566         /* clear pending irq */
4567         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4568         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4569         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4570
4571         kvm_make_request(KVM_REQ_EVENT, vcpu);
4572
4573         ++vcpu->stat.irq_window_exits;
4574
4575         /*
4576          * If the user space waits to inject interrupts, exit as soon as
4577          * possible
4578          */
4579         if (!irqchip_in_kernel(vcpu->kvm) &&
4580             vcpu->run->request_interrupt_window &&
4581             !kvm_cpu_has_interrupt(vcpu)) {
4582                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
4583                 return 0;
4584         }
4585         return 1;
4586 }
4587
4588 static int handle_halt(struct kvm_vcpu *vcpu)
4589 {
4590         skip_emulated_instruction(vcpu);
4591         return kvm_emulate_halt(vcpu);
4592 }
4593
4594 static int handle_vmcall(struct kvm_vcpu *vcpu)
4595 {
4596         skip_emulated_instruction(vcpu);
4597         kvm_emulate_hypercall(vcpu);
4598         return 1;
4599 }
4600
4601 static int handle_invd(struct kvm_vcpu *vcpu)
4602 {
4603         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4604 }
4605
4606 static int handle_invlpg(struct kvm_vcpu *vcpu)
4607 {
4608         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4609
4610         kvm_mmu_invlpg(vcpu, exit_qualification);
4611         skip_emulated_instruction(vcpu);
4612         return 1;
4613 }
4614
4615 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4616 {
4617         skip_emulated_instruction(vcpu);
4618         kvm_emulate_wbinvd(vcpu);
4619         return 1;
4620 }
4621
4622 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4623 {
4624         u64 new_bv = kvm_read_edx_eax(vcpu);
4625         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4626
4627         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4628                 skip_emulated_instruction(vcpu);
4629         return 1;
4630 }
4631
4632 static int handle_apic_access(struct kvm_vcpu *vcpu)
4633 {
4634         if (likely(fasteoi)) {
4635                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4636                 int access_type, offset;
4637
4638                 access_type = exit_qualification & APIC_ACCESS_TYPE;
4639                 offset = exit_qualification & APIC_ACCESS_OFFSET;
4640                 /*
4641                  * Sane guest uses MOV to write EOI, with written value
4642                  * not cared. So make a short-circuit here by avoiding
4643                  * heavy instruction emulation.
4644                  */
4645                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4646                     (offset == APIC_EOI)) {
4647                         kvm_lapic_set_eoi(vcpu);
4648                         skip_emulated_instruction(vcpu);
4649                         return 1;
4650                 }
4651         }
4652         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4653 }
4654
4655 static int handle_task_switch(struct kvm_vcpu *vcpu)
4656 {
4657         struct vcpu_vmx *vmx = to_vmx(vcpu);
4658         unsigned long exit_qualification;
4659         bool has_error_code = false;
4660         u32 error_code = 0;
4661         u16 tss_selector;
4662         int reason, type, idt_v;
4663
4664         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4665         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
4666
4667         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4668
4669         reason = (u32)exit_qualification >> 30;
4670         if (reason == TASK_SWITCH_GATE && idt_v) {
4671                 switch (type) {
4672                 case INTR_TYPE_NMI_INTR:
4673                         vcpu->arch.nmi_injected = false;
4674                         vmx_set_nmi_mask(vcpu, true);
4675                         break;
4676                 case INTR_TYPE_EXT_INTR:
4677                 case INTR_TYPE_SOFT_INTR:
4678                         kvm_clear_interrupt_queue(vcpu);
4679                         break;
4680                 case INTR_TYPE_HARD_EXCEPTION:
4681                         if (vmx->idt_vectoring_info &
4682                             VECTORING_INFO_DELIVER_CODE_MASK) {
4683                                 has_error_code = true;
4684                                 error_code =
4685                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
4686                         }
4687                         /* fall through */
4688                 case INTR_TYPE_SOFT_EXCEPTION:
4689                         kvm_clear_exception_queue(vcpu);
4690                         break;
4691                 default:
4692                         break;
4693                 }
4694         }
4695         tss_selector = exit_qualification;
4696
4697         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4698                        type != INTR_TYPE_EXT_INTR &&
4699                        type != INTR_TYPE_NMI_INTR))
4700                 skip_emulated_instruction(vcpu);
4701
4702         if (kvm_task_switch(vcpu, tss_selector, reason,
4703                                 has_error_code, error_code) == EMULATE_FAIL) {
4704                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4705                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4706                 vcpu->run->internal.ndata = 0;
4707                 return 0;
4708         }
4709
4710         /* clear all local breakpoint enable flags */
4711         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4712
4713         /*
4714          * TODO: What about debug traps on tss switch?
4715          *       Are we supposed to inject them and update dr6?
4716          */
4717
4718         return 1;
4719 }
4720
4721 static int handle_ept_violation(struct kvm_vcpu *vcpu)
4722 {
4723         unsigned long exit_qualification;
4724         gpa_t gpa;
4725         int gla_validity;
4726
4727         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4728
4729         if (exit_qualification & (1 << 6)) {
4730                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
4731                 return -EINVAL;
4732         }
4733
4734         gla_validity = (exit_qualification >> 7) & 0x3;
4735         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4736                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4737                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4738                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
4739                         vmcs_readl(GUEST_LINEAR_ADDRESS));
4740                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4741                         (long unsigned int)exit_qualification);
4742                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4743                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
4744                 return 0;
4745         }
4746
4747         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4748         trace_kvm_page_fault(gpa, exit_qualification);
4749         return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
4750 }
4751
4752 static u64 ept_rsvd_mask(u64 spte, int level)
4753 {
4754         int i;
4755         u64 mask = 0;
4756
4757         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4758                 mask |= (1ULL << i);
4759
4760         if (level > 2)
4761                 /* bits 7:3 reserved */
4762                 mask |= 0xf8;
4763         else if (level == 2) {
4764                 if (spte & (1ULL << 7))
4765                         /* 2MB ref, bits 20:12 reserved */
4766                         mask |= 0x1ff000;
4767                 else
4768                         /* bits 6:3 reserved */
4769                         mask |= 0x78;
4770         }
4771
4772         return mask;
4773 }
4774
4775 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4776                                        int level)
4777 {
4778         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4779
4780         /* 010b (write-only) */
4781         WARN_ON((spte & 0x7) == 0x2);
4782
4783         /* 110b (write/execute) */
4784         WARN_ON((spte & 0x7) == 0x6);
4785
4786         /* 100b (execute-only) and value not supported by logical processor */
4787         if (!cpu_has_vmx_ept_execute_only())
4788                 WARN_ON((spte & 0x7) == 0x4);
4789
4790         /* not 000b */
4791         if ((spte & 0x7)) {
4792                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4793
4794                 if (rsvd_bits != 0) {
4795                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4796                                          __func__, rsvd_bits);
4797                         WARN_ON(1);
4798                 }
4799
4800                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4801                         u64 ept_mem_type = (spte & 0x38) >> 3;
4802
4803                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
4804                             ept_mem_type == 7) {
4805                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4806                                                 __func__, ept_mem_type);
4807                                 WARN_ON(1);
4808                         }
4809                 }
4810         }
4811 }
4812
4813 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
4814 {
4815         u64 sptes[4];
4816         int nr_sptes, i, ret;
4817         gpa_t gpa;
4818
4819         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4820
4821         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4822         if (likely(ret == 1))
4823                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4824                                               EMULATE_DONE;
4825         if (unlikely(!ret))
4826                 return 1;
4827
4828         /* It is the real ept misconfig */
4829         printk(KERN_ERR "EPT: Misconfiguration.\n");
4830         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4831
4832         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4833
4834         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4835                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4836
4837         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4838         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
4839
4840         return 0;
4841 }
4842
4843 static int handle_nmi_window(struct kvm_vcpu *vcpu)
4844 {
4845         u32 cpu_based_vm_exec_control;
4846
4847         /* clear pending NMI */
4848         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4849         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4850         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4851         ++vcpu->stat.nmi_window_exits;
4852         kvm_make_request(KVM_REQ_EVENT, vcpu);
4853
4854         return 1;
4855 }
4856
4857 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
4858 {
4859         struct vcpu_vmx *vmx = to_vmx(vcpu);
4860         enum emulation_result err = EMULATE_DONE;
4861         int ret = 1;
4862         u32 cpu_exec_ctrl;
4863         bool intr_window_requested;
4864
4865         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4866         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
4867
4868         while (!guest_state_valid(vcpu)) {
4869                 if (intr_window_requested
4870                     && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
4871                         return handle_interrupt_window(&vmx->vcpu);
4872
4873                 err = emulate_instruction(vcpu, 0);
4874
4875                 if (err == EMULATE_DO_MMIO) {
4876                         ret = 0;
4877                         goto out;
4878                 }
4879
4880                 if (err != EMULATE_DONE)
4881                         return 0;
4882
4883                 if (signal_pending(current))
4884                         goto out;
4885                 if (need_resched())
4886                         schedule();
4887         }
4888
4889         vmx->emulation_required = 0;
4890 out:
4891         return ret;
4892 }
4893
4894 /*
4895  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4896  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4897  */
4898 static int handle_pause(struct kvm_vcpu *vcpu)
4899 {
4900         skip_emulated_instruction(vcpu);
4901         kvm_vcpu_on_spin(vcpu);
4902
4903         return 1;
4904 }
4905
4906 static int handle_invalid_op(struct kvm_vcpu *vcpu)
4907 {
4908         kvm_queue_exception(vcpu, UD_VECTOR);
4909         return 1;
4910 }
4911
4912 /*
4913  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
4914  * We could reuse a single VMCS for all the L2 guests, but we also want the
4915  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
4916  * allows keeping them loaded on the processor, and in the future will allow
4917  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
4918  * every entry if they never change.
4919  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
4920  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
4921  *
4922  * The following functions allocate and free a vmcs02 in this pool.
4923  */
4924
4925 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
4926 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
4927 {
4928         struct vmcs02_list *item;
4929         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4930                 if (item->vmptr == vmx->nested.current_vmptr) {
4931                         list_move(&item->list, &vmx->nested.vmcs02_pool);
4932                         return &item->vmcs02;
4933                 }
4934
4935         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
4936                 /* Recycle the least recently used VMCS. */
4937                 item = list_entry(vmx->nested.vmcs02_pool.prev,
4938                         struct vmcs02_list, list);
4939                 item->vmptr = vmx->nested.current_vmptr;
4940                 list_move(&item->list, &vmx->nested.vmcs02_pool);
4941                 return &item->vmcs02;
4942         }
4943
4944         /* Create a new VMCS */
4945         item = (struct vmcs02_list *)
4946                 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
4947         if (!item)
4948                 return NULL;
4949         item->vmcs02.vmcs = alloc_vmcs();
4950         if (!item->vmcs02.vmcs) {
4951                 kfree(item);
4952                 return NULL;
4953         }
4954         loaded_vmcs_init(&item->vmcs02);
4955         item->vmptr = vmx->nested.current_vmptr;
4956         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
4957         vmx->nested.vmcs02_num++;
4958         return &item->vmcs02;
4959 }
4960
4961 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
4962 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
4963 {
4964         struct vmcs02_list *item;
4965         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4966                 if (item->vmptr == vmptr) {
4967                         free_loaded_vmcs(&item->vmcs02);
4968                         list_del(&item->list);
4969                         kfree(item);
4970                         vmx->nested.vmcs02_num--;
4971                         return;
4972                 }
4973 }
4974
4975 /*
4976  * Free all VMCSs saved for this vcpu, except the one pointed by
4977  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
4978  * currently used, if running L2), and vmcs01 when running L2.
4979  */
4980 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
4981 {
4982         struct vmcs02_list *item, *n;
4983         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4984                 if (vmx->loaded_vmcs != &item->vmcs02)
4985                         free_loaded_vmcs(&item->vmcs02);
4986                 list_del(&item->list);
4987                 kfree(item);
4988         }
4989         vmx->nested.vmcs02_num = 0;
4990
4991         if (vmx->loaded_vmcs != &vmx->vmcs01)
4992                 free_loaded_vmcs(&vmx->vmcs01);
4993 }
4994
4995 /*
4996  * Emulate the VMXON instruction.
4997  * Currently, we just remember that VMX is active, and do not save or even
4998  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
4999  * do not currently need to store anything in that guest-allocated memory
5000  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5001  * argument is different from the VMXON pointer (which the spec says they do).
5002  */
5003 static int handle_vmon(struct kvm_vcpu *vcpu)
5004 {
5005         struct kvm_segment cs;
5006         struct vcpu_vmx *vmx = to_vmx(vcpu);
5007
5008         /* The Intel VMX Instruction Reference lists a bunch of bits that
5009          * are prerequisite to running VMXON, most notably cr4.VMXE must be
5010          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5011          * Otherwise, we should fail with #UD. We test these now:
5012          */
5013         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5014             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5015             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5016                 kvm_queue_exception(vcpu, UD_VECTOR);
5017                 return 1;
5018         }
5019
5020         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5021         if (is_long_mode(vcpu) && !cs.l) {
5022                 kvm_queue_exception(vcpu, UD_VECTOR);
5023                 return 1;
5024         }
5025
5026         if (vmx_get_cpl(vcpu)) {
5027                 kvm_inject_gp(vcpu, 0);
5028                 return 1;
5029         }
5030
5031         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5032         vmx->nested.vmcs02_num = 0;
5033
5034         vmx->nested.vmxon = true;
5035
5036         skip_emulated_instruction(vcpu);
5037         return 1;
5038 }
5039
5040 /*
5041  * Intel's VMX Instruction Reference specifies a common set of prerequisites
5042  * for running VMX instructions (except VMXON, whose prerequisites are
5043  * slightly different). It also specifies what exception to inject otherwise.
5044  */
5045 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5046 {
5047         struct kvm_segment cs;
5048         struct vcpu_vmx *vmx = to_vmx(vcpu);
5049
5050         if (!vmx->nested.vmxon) {
5051                 kvm_queue_exception(vcpu, UD_VECTOR);
5052                 return 0;
5053         }
5054
5055         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5056         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5057             (is_long_mode(vcpu) && !cs.l)) {
5058                 kvm_queue_exception(vcpu, UD_VECTOR);
5059                 return 0;
5060         }
5061
5062         if (vmx_get_cpl(vcpu)) {
5063                 kvm_inject_gp(vcpu, 0);
5064                 return 0;
5065         }
5066
5067         return 1;
5068 }
5069
5070 /*
5071  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5072  * just stops using VMX.
5073  */
5074 static void free_nested(struct vcpu_vmx *vmx)
5075 {
5076         if (!vmx->nested.vmxon)
5077                 return;
5078         vmx->nested.vmxon = false;
5079         if (vmx->nested.current_vmptr != -1ull) {
5080                 kunmap(vmx->nested.current_vmcs12_page);
5081                 nested_release_page(vmx->nested.current_vmcs12_page);
5082                 vmx->nested.current_vmptr = -1ull;
5083                 vmx->nested.current_vmcs12 = NULL;
5084         }
5085         /* Unpin physical memory we referred to in current vmcs02 */
5086         if (vmx->nested.apic_access_page) {
5087                 nested_release_page(vmx->nested.apic_access_page);
5088                 vmx->nested.apic_access_page = 0;
5089         }
5090
5091         nested_free_all_saved_vmcss(vmx);
5092 }
5093
5094 /* Emulate the VMXOFF instruction */
5095 static int handle_vmoff(struct kvm_vcpu *vcpu)
5096 {
5097         if (!nested_vmx_check_permission(vcpu))
5098                 return 1;
5099         free_nested(to_vmx(vcpu));
5100         skip_emulated_instruction(vcpu);
5101         return 1;
5102 }
5103
5104 /*
5105  * Decode the memory-address operand of a vmx instruction, as recorded on an
5106  * exit caused by such an instruction (run by a guest hypervisor).
5107  * On success, returns 0. When the operand is invalid, returns 1 and throws
5108  * #UD or #GP.
5109  */
5110 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5111                                  unsigned long exit_qualification,
5112                                  u32 vmx_instruction_info, gva_t *ret)
5113 {
5114         /*
5115          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5116          * Execution", on an exit, vmx_instruction_info holds most of the
5117          * addressing components of the operand. Only the displacement part
5118          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5119          * For how an actual address is calculated from all these components,
5120          * refer to Vol. 1, "Operand Addressing".
5121          */
5122         int  scaling = vmx_instruction_info & 3;
5123         int  addr_size = (vmx_instruction_info >> 7) & 7;
5124         bool is_reg = vmx_instruction_info & (1u << 10);
5125         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5126         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5127         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5128         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5129         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
5130
5131         if (is_reg) {
5132                 kvm_queue_exception(vcpu, UD_VECTOR);
5133                 return 1;
5134         }
5135
5136         /* Addr = segment_base + offset */
5137         /* offset = base + [index * scale] + displacement */
5138         *ret = vmx_get_segment_base(vcpu, seg_reg);
5139         if (base_is_valid)
5140                 *ret += kvm_register_read(vcpu, base_reg);
5141         if (index_is_valid)
5142                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5143         *ret += exit_qualification; /* holds the displacement */
5144
5145         if (addr_size == 1) /* 32 bit */
5146                 *ret &= 0xffffffff;
5147
5148         /*
5149          * TODO: throw #GP (and return 1) in various cases that the VM*
5150          * instructions require it - e.g., offset beyond segment limit,
5151          * unusable or unreadable/unwritable segment, non-canonical 64-bit
5152          * address, and so on. Currently these are not checked.
5153          */
5154         return 0;
5155 }
5156
5157 /*
5158  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5159  * set the success or error code of an emulated VMX instruction, as specified
5160  * by Vol 2B, VMX Instruction Reference, "Conventions".
5161  */
5162 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5163 {
5164         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5165                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5166                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5167 }
5168
5169 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5170 {
5171         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5172                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5173                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5174                         | X86_EFLAGS_CF);
5175 }
5176
5177 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5178                                         u32 vm_instruction_error)
5179 {
5180         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5181                 /*
5182                  * failValid writes the error number to the current VMCS, which
5183                  * can't be done there isn't a current VMCS.
5184                  */
5185                 nested_vmx_failInvalid(vcpu);
5186                 return;
5187         }
5188         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5189                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5190                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5191                         | X86_EFLAGS_ZF);
5192         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5193 }
5194
5195 /* Emulate the VMCLEAR instruction */
5196 static int handle_vmclear(struct kvm_vcpu *vcpu)
5197 {
5198         struct vcpu_vmx *vmx = to_vmx(vcpu);
5199         gva_t gva;
5200         gpa_t vmptr;
5201         struct vmcs12 *vmcs12;
5202         struct page *page;
5203         struct x86_exception e;
5204
5205         if (!nested_vmx_check_permission(vcpu))
5206                 return 1;
5207
5208         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5209                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5210                 return 1;
5211
5212         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5213                                 sizeof(vmptr), &e)) {
5214                 kvm_inject_page_fault(vcpu, &e);
5215                 return 1;
5216         }
5217
5218         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5219                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5220                 skip_emulated_instruction(vcpu);
5221                 return 1;
5222         }
5223
5224         if (vmptr == vmx->nested.current_vmptr) {
5225                 kunmap(vmx->nested.current_vmcs12_page);
5226                 nested_release_page(vmx->nested.current_vmcs12_page);
5227                 vmx->nested.current_vmptr = -1ull;
5228                 vmx->nested.current_vmcs12 = NULL;
5229         }
5230
5231         page = nested_get_page(vcpu, vmptr);
5232         if (page == NULL) {
5233                 /*
5234                  * For accurate processor emulation, VMCLEAR beyond available
5235                  * physical memory should do nothing at all. However, it is
5236                  * possible that a nested vmx bug, not a guest hypervisor bug,
5237                  * resulted in this case, so let's shut down before doing any
5238                  * more damage:
5239                  */
5240                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5241                 return 1;
5242         }
5243         vmcs12 = kmap(page);
5244         vmcs12->launch_state = 0;
5245         kunmap(page);
5246         nested_release_page(page);
5247
5248         nested_free_vmcs02(vmx, vmptr);
5249
5250         skip_emulated_instruction(vcpu);
5251         nested_vmx_succeed(vcpu);
5252         return 1;
5253 }
5254
5255 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5256
5257 /* Emulate the VMLAUNCH instruction */
5258 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5259 {
5260         return nested_vmx_run(vcpu, true);
5261 }
5262
5263 /* Emulate the VMRESUME instruction */
5264 static int handle_vmresume(struct kvm_vcpu *vcpu)
5265 {
5266
5267         return nested_vmx_run(vcpu, false);
5268 }
5269
5270 enum vmcs_field_type {
5271         VMCS_FIELD_TYPE_U16 = 0,
5272         VMCS_FIELD_TYPE_U64 = 1,
5273         VMCS_FIELD_TYPE_U32 = 2,
5274         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5275 };
5276
5277 static inline int vmcs_field_type(unsigned long field)
5278 {
5279         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
5280                 return VMCS_FIELD_TYPE_U32;
5281         return (field >> 13) & 0x3 ;
5282 }
5283
5284 static inline int vmcs_field_readonly(unsigned long field)
5285 {
5286         return (((field >> 10) & 0x3) == 1);
5287 }
5288
5289 /*
5290  * Read a vmcs12 field. Since these can have varying lengths and we return
5291  * one type, we chose the biggest type (u64) and zero-extend the return value
5292  * to that size. Note that the caller, handle_vmread, might need to use only
5293  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5294  * 64-bit fields are to be returned).
5295  */
5296 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5297                                         unsigned long field, u64 *ret)
5298 {
5299         short offset = vmcs_field_to_offset(field);
5300         char *p;
5301
5302         if (offset < 0)
5303                 return 0;
5304
5305         p = ((char *)(get_vmcs12(vcpu))) + offset;
5306
5307         switch (vmcs_field_type(field)) {
5308         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5309                 *ret = *((natural_width *)p);
5310                 return 1;
5311         case VMCS_FIELD_TYPE_U16:
5312                 *ret = *((u16 *)p);
5313                 return 1;
5314         case VMCS_FIELD_TYPE_U32:
5315                 *ret = *((u32 *)p);
5316                 return 1;
5317         case VMCS_FIELD_TYPE_U64:
5318                 *ret = *((u64 *)p);
5319                 return 1;
5320         default:
5321                 return 0; /* can never happen. */
5322         }
5323 }
5324
5325 /*
5326  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5327  * used before) all generate the same failure when it is missing.
5328  */
5329 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5330 {
5331         struct vcpu_vmx *vmx = to_vmx(vcpu);
5332         if (vmx->nested.current_vmptr == -1ull) {
5333                 nested_vmx_failInvalid(vcpu);
5334                 skip_emulated_instruction(vcpu);
5335                 return 0;
5336         }
5337         return 1;
5338 }
5339
5340 static int handle_vmread(struct kvm_vcpu *vcpu)
5341 {
5342         unsigned long field;
5343         u64 field_value;
5344         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5345         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5346         gva_t gva = 0;
5347
5348         if (!nested_vmx_check_permission(vcpu) ||
5349             !nested_vmx_check_vmcs12(vcpu))
5350                 return 1;
5351
5352         /* Decode instruction info and find the field to read */
5353         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5354         /* Read the field, zero-extended to a u64 field_value */
5355         if (!vmcs12_read_any(vcpu, field, &field_value)) {
5356                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5357                 skip_emulated_instruction(vcpu);
5358                 return 1;
5359         }
5360         /*
5361          * Now copy part of this value to register or memory, as requested.
5362          * Note that the number of bits actually copied is 32 or 64 depending
5363          * on the guest's mode (32 or 64 bit), not on the given field's length.
5364          */
5365         if (vmx_instruction_info & (1u << 10)) {
5366                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5367                         field_value);
5368         } else {
5369                 if (get_vmx_mem_address(vcpu, exit_qualification,
5370                                 vmx_instruction_info, &gva))
5371                         return 1;
5372                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5373                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5374                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5375         }
5376
5377         nested_vmx_succeed(vcpu);
5378         skip_emulated_instruction(vcpu);
5379         return 1;
5380 }
5381
5382
5383 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5384 {
5385         unsigned long field;
5386         gva_t gva;
5387         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5388         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5389         char *p;
5390         short offset;
5391         /* The value to write might be 32 or 64 bits, depending on L1's long
5392          * mode, and eventually we need to write that into a field of several
5393          * possible lengths. The code below first zero-extends the value to 64
5394          * bit (field_value), and then copies only the approriate number of
5395          * bits into the vmcs12 field.
5396          */
5397         u64 field_value = 0;
5398         struct x86_exception e;
5399
5400         if (!nested_vmx_check_permission(vcpu) ||
5401             !nested_vmx_check_vmcs12(vcpu))
5402                 return 1;
5403
5404         if (vmx_instruction_info & (1u << 10))
5405                 field_value = kvm_register_read(vcpu,
5406                         (((vmx_instruction_info) >> 3) & 0xf));
5407         else {
5408                 if (get_vmx_mem_address(vcpu, exit_qualification,
5409                                 vmx_instruction_info, &gva))
5410                         return 1;
5411                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5412                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5413                         kvm_inject_page_fault(vcpu, &e);
5414                         return 1;
5415                 }
5416         }
5417
5418
5419         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5420         if (vmcs_field_readonly(field)) {
5421                 nested_vmx_failValid(vcpu,
5422                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5423                 skip_emulated_instruction(vcpu);
5424                 return 1;
5425         }
5426
5427         offset = vmcs_field_to_offset(field);
5428         if (offset < 0) {
5429                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5430                 skip_emulated_instruction(vcpu);
5431                 return 1;
5432         }
5433         p = ((char *) get_vmcs12(vcpu)) + offset;
5434
5435         switch (vmcs_field_type(field)) {
5436         case VMCS_FIELD_TYPE_U16:
5437                 *(u16 *)p = field_value;
5438                 break;
5439         case VMCS_FIELD_TYPE_U32:
5440                 *(u32 *)p = field_value;
5441                 break;
5442         case VMCS_FIELD_TYPE_U64:
5443                 *(u64 *)p = field_value;
5444                 break;
5445         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5446                 *(natural_width *)p = field_value;
5447                 break;
5448         default:
5449                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5450                 skip_emulated_instruction(vcpu);
5451                 return 1;
5452         }
5453
5454         nested_vmx_succeed(vcpu);
5455         skip_emulated_instruction(vcpu);
5456         return 1;
5457 }
5458
5459 /* Emulate the VMPTRLD instruction */
5460 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5461 {
5462         struct vcpu_vmx *vmx = to_vmx(vcpu);
5463         gva_t gva;
5464         gpa_t vmptr;
5465         struct x86_exception e;
5466
5467         if (!nested_vmx_check_permission(vcpu))
5468                 return 1;
5469
5470         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5471                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5472                 return 1;
5473
5474         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5475                                 sizeof(vmptr), &e)) {
5476                 kvm_inject_page_fault(vcpu, &e);
5477                 return 1;
5478         }
5479
5480         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5481                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5482                 skip_emulated_instruction(vcpu);
5483                 return 1;
5484         }
5485
5486         if (vmx->nested.current_vmptr != vmptr) {
5487                 struct vmcs12 *new_vmcs12;
5488                 struct page *page;
5489                 page = nested_get_page(vcpu, vmptr);
5490                 if (page == NULL) {
5491                         nested_vmx_failInvalid(vcpu);
5492                         skip_emulated_instruction(vcpu);
5493                         return 1;
5494                 }
5495                 new_vmcs12 = kmap(page);
5496                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5497                         kunmap(page);
5498                         nested_release_page_clean(page);
5499                         nested_vmx_failValid(vcpu,
5500                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5501                         skip_emulated_instruction(vcpu);
5502                         return 1;
5503                 }
5504                 if (vmx->nested.current_vmptr != -1ull) {
5505                         kunmap(vmx->nested.current_vmcs12_page);
5506                         nested_release_page(vmx->nested.current_vmcs12_page);
5507                 }
5508
5509                 vmx->nested.current_vmptr = vmptr;
5510                 vmx->nested.current_vmcs12 = new_vmcs12;
5511                 vmx->nested.current_vmcs12_page = page;
5512         }
5513
5514         nested_vmx_succeed(vcpu);
5515         skip_emulated_instruction(vcpu);
5516         return 1;
5517 }
5518
5519 /* Emulate the VMPTRST instruction */
5520 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5521 {
5522         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5523         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5524         gva_t vmcs_gva;
5525         struct x86_exception e;
5526
5527         if (!nested_vmx_check_permission(vcpu))
5528                 return 1;
5529
5530         if (get_vmx_mem_address(vcpu, exit_qualification,
5531                         vmx_instruction_info, &vmcs_gva))
5532                 return 1;
5533         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5534         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5535                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
5536                                  sizeof(u64), &e)) {
5537                 kvm_inject_page_fault(vcpu, &e);
5538                 return 1;
5539         }
5540         nested_vmx_succeed(vcpu);
5541         skip_emulated_instruction(vcpu);
5542         return 1;
5543 }
5544
5545 /*
5546  * The exit handlers return 1 if the exit was handled fully and guest execution
5547  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5548  * to be done to userspace and return 0.
5549  */
5550 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5551         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
5552         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5553         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5554         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5555         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5556         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5557         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5558         [EXIT_REASON_CPUID]                   = handle_cpuid,
5559         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
5560         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
5561         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
5562         [EXIT_REASON_HLT]                     = handle_halt,
5563         [EXIT_REASON_INVD]                    = handle_invd,
5564         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5565         [EXIT_REASON_VMCALL]                  = handle_vmcall,
5566         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
5567         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
5568         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
5569         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
5570         [EXIT_REASON_VMREAD]                  = handle_vmread,
5571         [EXIT_REASON_VMRESUME]                = handle_vmresume,
5572         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
5573         [EXIT_REASON_VMOFF]                   = handle_vmoff,
5574         [EXIT_REASON_VMON]                    = handle_vmon,
5575         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5576         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5577         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
5578         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
5579         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5580         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5581         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5582         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5583         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5584         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
5585         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
5586 };
5587
5588 static const int kvm_vmx_max_exit_handlers =
5589         ARRAY_SIZE(kvm_vmx_exit_handlers);
5590
5591 /*
5592  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5593  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5594  * disinterest in the current event (read or write a specific MSR) by using an
5595  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5596  */
5597 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5598         struct vmcs12 *vmcs12, u32 exit_reason)
5599 {
5600         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5601         gpa_t bitmap;
5602
5603         if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5604                 return 1;
5605
5606         /*
5607          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5608          * for the four combinations of read/write and low/high MSR numbers.
5609          * First we need to figure out which of the four to use:
5610          */
5611         bitmap = vmcs12->msr_bitmap;
5612         if (exit_reason == EXIT_REASON_MSR_WRITE)
5613                 bitmap += 2048;
5614         if (msr_index >= 0xc0000000) {
5615                 msr_index -= 0xc0000000;
5616                 bitmap += 1024;
5617         }
5618
5619         /* Then read the msr_index'th bit from this bitmap: */
5620         if (msr_index < 1024*8) {
5621                 unsigned char b;
5622                 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5623                 return 1 & (b >> (msr_index & 7));
5624         } else
5625                 return 1; /* let L1 handle the wrong parameter */
5626 }
5627
5628 /*
5629  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5630  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5631  * intercept (via guest_host_mask etc.) the current event.
5632  */
5633 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5634         struct vmcs12 *vmcs12)
5635 {
5636         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5637         int cr = exit_qualification & 15;
5638         int reg = (exit_qualification >> 8) & 15;
5639         unsigned long val = kvm_register_read(vcpu, reg);
5640
5641         switch ((exit_qualification >> 4) & 3) {
5642         case 0: /* mov to cr */
5643                 switch (cr) {
5644                 case 0:
5645                         if (vmcs12->cr0_guest_host_mask &
5646                             (val ^ vmcs12->cr0_read_shadow))
5647                                 return 1;
5648                         break;
5649                 case 3:
5650                         if ((vmcs12->cr3_target_count >= 1 &&
5651                                         vmcs12->cr3_target_value0 == val) ||
5652                                 (vmcs12->cr3_target_count >= 2 &&
5653                                         vmcs12->cr3_target_value1 == val) ||
5654                                 (vmcs12->cr3_target_count >= 3 &&
5655                                         vmcs12->cr3_target_value2 == val) ||
5656                                 (vmcs12->cr3_target_count >= 4 &&
5657                                         vmcs12->cr3_target_value3 == val))
5658                                 return 0;
5659                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5660                                 return 1;
5661                         break;
5662                 case 4:
5663                         if (vmcs12->cr4_guest_host_mask &
5664                             (vmcs12->cr4_read_shadow ^ val))
5665                                 return 1;
5666                         break;
5667                 case 8:
5668                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5669                                 return 1;
5670                         break;
5671                 }
5672                 break;
5673         case 2: /* clts */
5674                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5675                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
5676                         return 1;
5677                 break;
5678         case 1: /* mov from cr */
5679                 switch (cr) {
5680                 case 3:
5681                         if (vmcs12->cpu_based_vm_exec_control &
5682                             CPU_BASED_CR3_STORE_EXITING)
5683                                 return 1;
5684                         break;
5685                 case 8:
5686                         if (vmcs12->cpu_based_vm_exec_control &
5687                             CPU_BASED_CR8_STORE_EXITING)
5688                                 return 1;
5689                         break;
5690                 }
5691                 break;
5692         case 3: /* lmsw */
5693                 /*
5694                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5695                  * cr0. Other attempted changes are ignored, with no exit.
5696                  */
5697                 if (vmcs12->cr0_guest_host_mask & 0xe &
5698                     (val ^ vmcs12->cr0_read_shadow))
5699                         return 1;
5700                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5701                     !(vmcs12->cr0_read_shadow & 0x1) &&
5702                     (val & 0x1))
5703                         return 1;
5704                 break;
5705         }
5706         return 0;
5707 }
5708
5709 /*
5710  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5711  * should handle it ourselves in L0 (and then continue L2). Only call this
5712  * when in is_guest_mode (L2).
5713  */
5714 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5715 {
5716         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5717         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5718         struct vcpu_vmx *vmx = to_vmx(vcpu);
5719         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5720
5721         if (vmx->nested.nested_run_pending)
5722                 return 0;
5723
5724         if (unlikely(vmx->fail)) {
5725                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5726                                     vmcs_read32(VM_INSTRUCTION_ERROR));
5727                 return 1;
5728         }
5729
5730         switch (exit_reason) {
5731         case EXIT_REASON_EXCEPTION_NMI:
5732                 if (!is_exception(intr_info))
5733                         return 0;
5734                 else if (is_page_fault(intr_info))
5735                         return enable_ept;
5736                 return vmcs12->exception_bitmap &
5737                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5738         case EXIT_REASON_EXTERNAL_INTERRUPT:
5739                 return 0;
5740         case EXIT_REASON_TRIPLE_FAULT:
5741                 return 1;
5742         case EXIT_REASON_PENDING_INTERRUPT:
5743         case EXIT_REASON_NMI_WINDOW:
5744                 /*
5745                  * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5746                  * (aka Interrupt Window Exiting) only when L1 turned it on,
5747                  * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5748                  * Same for NMI Window Exiting.
5749                  */
5750                 return 1;
5751         case EXIT_REASON_TASK_SWITCH:
5752                 return 1;
5753         case EXIT_REASON_CPUID:
5754                 return 1;
5755         case EXIT_REASON_HLT:
5756                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5757         case EXIT_REASON_INVD:
5758                 return 1;
5759         case EXIT_REASON_INVLPG:
5760                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5761         case EXIT_REASON_RDPMC:
5762                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5763         case EXIT_REASON_RDTSC:
5764                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5765         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5766         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5767         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5768         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5769         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5770                 /*
5771                  * VMX instructions trap unconditionally. This allows L1 to
5772                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
5773                  */
5774                 return 1;
5775         case EXIT_REASON_CR_ACCESS:
5776                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5777         case EXIT_REASON_DR_ACCESS:
5778                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5779         case EXIT_REASON_IO_INSTRUCTION:
5780                 /* TODO: support IO bitmaps */
5781                 return 1;
5782         case EXIT_REASON_MSR_READ:
5783         case EXIT_REASON_MSR_WRITE:
5784                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5785         case EXIT_REASON_INVALID_STATE:
5786                 return 1;
5787         case EXIT_REASON_MWAIT_INSTRUCTION:
5788                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5789         case EXIT_REASON_MONITOR_INSTRUCTION:
5790                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5791         case EXIT_REASON_PAUSE_INSTRUCTION:
5792                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5793                         nested_cpu_has2(vmcs12,
5794                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5795         case EXIT_REASON_MCE_DURING_VMENTRY:
5796                 return 0;
5797         case EXIT_REASON_TPR_BELOW_THRESHOLD:
5798                 return 1;
5799         case EXIT_REASON_APIC_ACCESS:
5800                 return nested_cpu_has2(vmcs12,
5801                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5802         case EXIT_REASON_EPT_VIOLATION:
5803         case EXIT_REASON_EPT_MISCONFIG:
5804                 return 0;
5805         case EXIT_REASON_WBINVD:
5806                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5807         case EXIT_REASON_XSETBV:
5808                 return 1;
5809         default:
5810                 return 1;
5811         }
5812 }
5813
5814 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5815 {
5816         *info1 = vmcs_readl(EXIT_QUALIFICATION);
5817         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5818 }
5819
5820 /*
5821  * The guest has exited.  See if we can fix it or if we need userspace
5822  * assistance.
5823  */
5824 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5825 {
5826         struct vcpu_vmx *vmx = to_vmx(vcpu);
5827         u32 exit_reason = vmx->exit_reason;
5828         u32 vectoring_info = vmx->idt_vectoring_info;
5829
5830         /* If guest state is invalid, start emulating */
5831         if (vmx->emulation_required && emulate_invalid_guest_state)
5832                 return handle_invalid_guest_state(vcpu);
5833
5834         /*
5835          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5836          * we did not inject a still-pending event to L1 now because of
5837          * nested_run_pending, we need to re-enable this bit.
5838          */
5839         if (vmx->nested.nested_run_pending)
5840                 kvm_make_request(KVM_REQ_EVENT, vcpu);
5841
5842         if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5843             exit_reason == EXIT_REASON_VMRESUME))
5844                 vmx->nested.nested_run_pending = 1;
5845         else
5846                 vmx->nested.nested_run_pending = 0;
5847
5848         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5849                 nested_vmx_vmexit(vcpu);
5850                 return 1;
5851         }
5852
5853         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5854                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5855                 vcpu->run->fail_entry.hardware_entry_failure_reason
5856                         = exit_reason;
5857                 return 0;
5858         }
5859
5860         if (unlikely(vmx->fail)) {
5861                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5862                 vcpu->run->fail_entry.hardware_entry_failure_reason
5863                         = vmcs_read32(VM_INSTRUCTION_ERROR);
5864                 return 0;
5865         }
5866
5867         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5868                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5869                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
5870                         exit_reason != EXIT_REASON_TASK_SWITCH))
5871                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
5872                        "(0x%x) and exit reason is 0x%x\n",
5873                        __func__, vectoring_info, exit_reason);
5874
5875         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
5876             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
5877                                         get_vmcs12(vcpu), vcpu)))) {
5878                 if (vmx_interrupt_allowed(vcpu)) {
5879                         vmx->soft_vnmi_blocked = 0;
5880                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
5881                            vcpu->arch.nmi_pending) {
5882                         /*
5883                          * This CPU don't support us in finding the end of an
5884                          * NMI-blocked window if the guest runs with IRQs
5885                          * disabled. So we pull the trigger after 1 s of
5886                          * futile waiting, but inform the user about this.
5887                          */
5888                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5889                                "state on VCPU %d after 1 s timeout\n",
5890                                __func__, vcpu->vcpu_id);
5891                         vmx->soft_vnmi_blocked = 0;
5892                 }
5893         }
5894
5895         if (exit_reason < kvm_vmx_max_exit_handlers
5896             && kvm_vmx_exit_handlers[exit_reason])
5897                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5898         else {
5899                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5900                 vcpu->run->hw.hardware_exit_reason = exit_reason;
5901         }
5902         return 0;
5903 }
5904
5905 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5906 {
5907         if (irr == -1 || tpr < irr) {
5908                 vmcs_write32(TPR_THRESHOLD, 0);
5909                 return;
5910         }
5911
5912         vmcs_write32(TPR_THRESHOLD, irr);
5913 }
5914
5915 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
5916 {
5917         u32 exit_intr_info;
5918
5919         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
5920               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
5921                 return;
5922
5923         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5924         exit_intr_info = vmx->exit_intr_info;
5925
5926         /* Handle machine checks before interrupts are enabled */
5927         if (is_machine_check(exit_intr_info))
5928                 kvm_machine_check();
5929
5930         /* We need to handle NMIs before interrupts are enabled */
5931         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
5932             (exit_intr_info & INTR_INFO_VALID_MASK)) {
5933                 kvm_before_handle_nmi(&vmx->vcpu);
5934                 asm("int $2");
5935                 kvm_after_handle_nmi(&vmx->vcpu);
5936         }
5937 }
5938
5939 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
5940 {
5941         u32 exit_intr_info;
5942         bool unblock_nmi;
5943         u8 vector;
5944         bool idtv_info_valid;
5945
5946         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
5947
5948         if (cpu_has_virtual_nmis()) {
5949                 if (vmx->nmi_known_unmasked)
5950                         return;
5951                 /*
5952                  * Can't use vmx->exit_intr_info since we're not sure what
5953                  * the exit reason is.
5954                  */
5955                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5956                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
5957                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
5958                 /*
5959                  * SDM 3: 27.7.1.2 (September 2008)
5960                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
5961                  * a guest IRET fault.
5962                  * SDM 3: 23.2.2 (September 2008)
5963                  * Bit 12 is undefined in any of the following cases:
5964                  *  If the VM exit sets the valid bit in the IDT-vectoring
5965                  *   information field.
5966                  *  If the VM exit is due to a double fault.
5967                  */
5968                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
5969                     vector != DF_VECTOR && !idtv_info_valid)
5970                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5971                                       GUEST_INTR_STATE_NMI);
5972                 else
5973                         vmx->nmi_known_unmasked =
5974                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
5975                                   & GUEST_INTR_STATE_NMI);
5976         } else if (unlikely(vmx->soft_vnmi_blocked))
5977                 vmx->vnmi_blocked_time +=
5978                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
5979 }
5980
5981 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
5982                                       u32 idt_vectoring_info,
5983                                       int instr_len_field,
5984                                       int error_code_field)
5985 {
5986         u8 vector;
5987         int type;
5988         bool idtv_info_valid;
5989
5990         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
5991
5992         vmx->vcpu.arch.nmi_injected = false;
5993         kvm_clear_exception_queue(&vmx->vcpu);
5994         kvm_clear_interrupt_queue(&vmx->vcpu);
5995
5996         if (!idtv_info_valid)
5997                 return;
5998
5999         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6000
6001         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6002         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6003
6004         switch (type) {
6005         case INTR_TYPE_NMI_INTR:
6006                 vmx->vcpu.arch.nmi_injected = true;
6007                 /*
6008                  * SDM 3: 27.7.1.2 (September 2008)
6009                  * Clear bit "block by NMI" before VM entry if a NMI
6010                  * delivery faulted.
6011                  */
6012                 vmx_set_nmi_mask(&vmx->vcpu, false);
6013                 break;
6014         case INTR_TYPE_SOFT_EXCEPTION:
6015                 vmx->vcpu.arch.event_exit_inst_len =
6016                         vmcs_read32(instr_len_field);
6017                 /* fall through */
6018         case INTR_TYPE_HARD_EXCEPTION:
6019                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6020                         u32 err = vmcs_read32(error_code_field);
6021                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
6022                 } else
6023                         kvm_queue_exception(&vmx->vcpu, vector);
6024                 break;
6025         case INTR_TYPE_SOFT_INTR:
6026                 vmx->vcpu.arch.event_exit_inst_len =
6027                         vmcs_read32(instr_len_field);
6028                 /* fall through */
6029         case INTR_TYPE_EXT_INTR:
6030                 kvm_queue_interrupt(&vmx->vcpu, vector,
6031                         type == INTR_TYPE_SOFT_INTR);
6032                 break;
6033         default:
6034                 break;
6035         }
6036 }
6037
6038 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6039 {
6040         if (is_guest_mode(&vmx->vcpu))
6041                 return;
6042         __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6043                                   VM_EXIT_INSTRUCTION_LEN,
6044                                   IDT_VECTORING_ERROR_CODE);
6045 }
6046
6047 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6048 {
6049         if (is_guest_mode(vcpu))
6050                 return;
6051         __vmx_complete_interrupts(to_vmx(vcpu),
6052                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6053                                   VM_ENTRY_INSTRUCTION_LEN,
6054                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6055
6056         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6057 }
6058
6059 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6060 {
6061         int i, nr_msrs;
6062         struct perf_guest_switch_msr *msrs;
6063
6064         msrs = perf_guest_get_msrs(&nr_msrs);
6065
6066         if (!msrs)
6067                 return;
6068
6069         for (i = 0; i < nr_msrs; i++)
6070                 if (msrs[i].host == msrs[i].guest)
6071                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6072                 else
6073                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6074                                         msrs[i].host);
6075 }
6076
6077 #ifdef CONFIG_X86_64
6078 #define R "r"
6079 #define Q "q"
6080 #else
6081 #define R "e"
6082 #define Q "l"
6083 #endif
6084
6085 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6086 {
6087         struct vcpu_vmx *vmx = to_vmx(vcpu);
6088
6089         if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6090                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6091                 if (vmcs12->idt_vectoring_info_field &
6092                                 VECTORING_INFO_VALID_MASK) {
6093                         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6094                                 vmcs12->idt_vectoring_info_field);
6095                         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6096                                 vmcs12->vm_exit_instruction_len);
6097                         if (vmcs12->idt_vectoring_info_field &
6098                                         VECTORING_INFO_DELIVER_CODE_MASK)
6099                                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6100                                         vmcs12->idt_vectoring_error_code);
6101                 }
6102         }
6103
6104         /* Record the guest's net vcpu time for enforced NMI injections. */
6105         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6106                 vmx->entry_time = ktime_get();
6107
6108         /* Don't enter VMX if guest state is invalid, let the exit handler
6109            start emulation until we arrive back to a valid state */
6110         if (vmx->emulation_required && emulate_invalid_guest_state)
6111                 return;
6112
6113         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6114                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6115         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6116                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6117
6118         /* When single-stepping over STI and MOV SS, we must clear the
6119          * corresponding interruptibility bits in the guest state. Otherwise
6120          * vmentry fails as it then expects bit 14 (BS) in pending debug
6121          * exceptions being set, but that's not correct for the guest debugging
6122          * case. */
6123         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6124                 vmx_set_interrupt_shadow(vcpu, 0);
6125
6126         atomic_switch_perf_msrs(vmx);
6127
6128         vmx->__launched = vmx->loaded_vmcs->launched;
6129         asm(
6130                 /* Store host registers */
6131                 "push %%"R"dx; push %%"R"bp;"
6132                 "push %%"R"cx \n\t" /* placeholder for guest rcx */
6133                 "push %%"R"cx \n\t"
6134                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
6135                 "je 1f \n\t"
6136                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
6137                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
6138                 "1: \n\t"
6139                 /* Reload cr2 if changed */
6140                 "mov %c[cr2](%0), %%"R"ax \n\t"
6141                 "mov %%cr2, %%"R"dx \n\t"
6142                 "cmp %%"R"ax, %%"R"dx \n\t"
6143                 "je 2f \n\t"
6144                 "mov %%"R"ax, %%cr2 \n\t"
6145                 "2: \n\t"
6146                 /* Check if vmlaunch of vmresume is needed */
6147                 "cmpl $0, %c[launched](%0) \n\t"
6148                 /* Load guest registers.  Don't clobber flags. */
6149                 "mov %c[rax](%0), %%"R"ax \n\t"
6150                 "mov %c[rbx](%0), %%"R"bx \n\t"
6151                 "mov %c[rdx](%0), %%"R"dx \n\t"
6152                 "mov %c[rsi](%0), %%"R"si \n\t"
6153                 "mov %c[rdi](%0), %%"R"di \n\t"
6154                 "mov %c[rbp](%0), %%"R"bp \n\t"
6155 #ifdef CONFIG_X86_64
6156                 "mov %c[r8](%0),  %%r8  \n\t"
6157                 "mov %c[r9](%0),  %%r9  \n\t"
6158                 "mov %c[r10](%0), %%r10 \n\t"
6159                 "mov %c[r11](%0), %%r11 \n\t"
6160                 "mov %c[r12](%0), %%r12 \n\t"
6161                 "mov %c[r13](%0), %%r13 \n\t"
6162                 "mov %c[r14](%0), %%r14 \n\t"
6163                 "mov %c[r15](%0), %%r15 \n\t"
6164 #endif
6165                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
6166
6167                 /* Enter guest mode */
6168                 "jne .Llaunched \n\t"
6169                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
6170                 "jmp .Lkvm_vmx_return \n\t"
6171                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
6172                 ".Lkvm_vmx_return: "
6173                 /* Save guest registers, load host registers, keep flags */
6174                 "mov %0, %c[wordsize](%%"R"sp) \n\t"
6175                 "pop %0 \n\t"
6176                 "mov %%"R"ax, %c[rax](%0) \n\t"
6177                 "mov %%"R"bx, %c[rbx](%0) \n\t"
6178                 "pop"Q" %c[rcx](%0) \n\t"
6179                 "mov %%"R"dx, %c[rdx](%0) \n\t"
6180                 "mov %%"R"si, %c[rsi](%0) \n\t"
6181                 "mov %%"R"di, %c[rdi](%0) \n\t"
6182                 "mov %%"R"bp, %c[rbp](%0) \n\t"
6183 #ifdef CONFIG_X86_64
6184                 "mov %%r8,  %c[r8](%0) \n\t"
6185                 "mov %%r9,  %c[r9](%0) \n\t"
6186                 "mov %%r10, %c[r10](%0) \n\t"
6187                 "mov %%r11, %c[r11](%0) \n\t"
6188                 "mov %%r12, %c[r12](%0) \n\t"
6189                 "mov %%r13, %c[r13](%0) \n\t"
6190                 "mov %%r14, %c[r14](%0) \n\t"
6191                 "mov %%r15, %c[r15](%0) \n\t"
6192 #endif
6193                 "mov %%cr2, %%"R"ax   \n\t"
6194                 "mov %%"R"ax, %c[cr2](%0) \n\t"
6195
6196                 "pop  %%"R"bp; pop  %%"R"dx \n\t"
6197                 "setbe %c[fail](%0) \n\t"
6198               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
6199                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
6200                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
6201                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
6202                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6203                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6204                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6205                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6206                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6207                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6208                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
6209 #ifdef CONFIG_X86_64
6210                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6211                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6212                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6213                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6214                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6215                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6216                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6217                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6218 #endif
6219                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6220                 [wordsize]"i"(sizeof(ulong))
6221               : "cc", "memory"
6222                 , R"ax", R"bx", R"di", R"si"
6223 #ifdef CONFIG_X86_64
6224                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6225 #endif
6226               );
6227
6228         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6229                                   | (1 << VCPU_EXREG_RFLAGS)
6230                                   | (1 << VCPU_EXREG_CPL)
6231                                   | (1 << VCPU_EXREG_PDPTR)
6232                                   | (1 << VCPU_EXREG_SEGMENTS)
6233                                   | (1 << VCPU_EXREG_CR3));
6234         vcpu->arch.regs_dirty = 0;
6235
6236         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6237
6238         if (is_guest_mode(vcpu)) {
6239                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6240                 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6241                 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6242                         vmcs12->idt_vectoring_error_code =
6243                                 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6244                         vmcs12->vm_exit_instruction_len =
6245                                 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6246                 }
6247         }
6248
6249         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
6250         vmx->loaded_vmcs->launched = 1;
6251
6252         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
6253         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
6254
6255         vmx_complete_atomic_exit(vmx);
6256         vmx_recover_nmi_blocking(vmx);
6257         vmx_complete_interrupts(vmx);
6258 }
6259
6260 #undef R
6261 #undef Q
6262
6263 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6264 {
6265         struct vcpu_vmx *vmx = to_vmx(vcpu);
6266
6267         free_vpid(vmx);
6268         free_nested(vmx);
6269         free_loaded_vmcs(vmx->loaded_vmcs);
6270         kfree(vmx->guest_msrs);
6271         kvm_vcpu_uninit(vcpu);
6272         kmem_cache_free(kvm_vcpu_cache, vmx);
6273 }
6274
6275 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6276 {
6277         int err;
6278         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
6279         int cpu;
6280
6281         if (!vmx)
6282                 return ERR_PTR(-ENOMEM);
6283
6284         allocate_vpid(vmx);
6285
6286         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6287         if (err)
6288                 goto free_vcpu;
6289
6290         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
6291         err = -ENOMEM;
6292         if (!vmx->guest_msrs) {
6293                 goto uninit_vcpu;
6294         }
6295
6296         vmx->loaded_vmcs = &vmx->vmcs01;
6297         vmx->loaded_vmcs->vmcs = alloc_vmcs();
6298         if (!vmx->loaded_vmcs->vmcs)
6299                 goto free_msrs;
6300         if (!vmm_exclusive)
6301                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6302         loaded_vmcs_init(vmx->loaded_vmcs);
6303         if (!vmm_exclusive)
6304                 kvm_cpu_vmxoff();
6305
6306         cpu = get_cpu();
6307         vmx_vcpu_load(&vmx->vcpu, cpu);
6308         vmx->vcpu.cpu = cpu;
6309         err = vmx_vcpu_setup(vmx);
6310         vmx_vcpu_put(&vmx->vcpu);