KVM: nVMX: Correct handling of exception injection
[linux-3.10.git] / arch / x86 / kvm / vmx.c
1 /*
2  * Kernel-based Virtual Machine driver for Linux
3  *
4  * This module enables machines with Intel VT-x extensions to run virtual
5  * machines without emulation or binary translation.
6  *
7  * Copyright (C) 2006 Qumranet, Inc.
8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
9  *
10  * Authors:
11  *   Avi Kivity   <avi@qumranet.com>
12  *   Yaniv Kamay  <yaniv@qumranet.com>
13  *
14  * This work is licensed under the terms of the GNU GPL, version 2.  See
15  * the COPYING file in the top-level directory.
16  *
17  */
18
19 #include "irq.h"
20 #include "mmu.h"
21
22 #include <linux/kvm_host.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/mm.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/moduleparam.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31 #include <linux/tboot.h>
32 #include "kvm_cache_regs.h"
33 #include "x86.h"
34
35 #include <asm/io.h>
36 #include <asm/desc.h>
37 #include <asm/vmx.h>
38 #include <asm/virtext.h>
39 #include <asm/mce.h>
40 #include <asm/i387.h>
41 #include <asm/xcr.h>
42
43 #include "trace.h"
44
45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
46 #define __ex_clear(x, reg) \
47         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
48
49 MODULE_AUTHOR("Qumranet");
50 MODULE_LICENSE("GPL");
51
52 static int __read_mostly bypass_guest_pf = 1;
53 module_param(bypass_guest_pf, bool, S_IRUGO);
54
55 static int __read_mostly enable_vpid = 1;
56 module_param_named(vpid, enable_vpid, bool, 0444);
57
58 static int __read_mostly flexpriority_enabled = 1;
59 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
60
61 static int __read_mostly enable_ept = 1;
62 module_param_named(ept, enable_ept, bool, S_IRUGO);
63
64 static int __read_mostly enable_unrestricted_guest = 1;
65 module_param_named(unrestricted_guest,
66                         enable_unrestricted_guest, bool, S_IRUGO);
67
68 static int __read_mostly emulate_invalid_guest_state = 0;
69 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
70
71 static int __read_mostly vmm_exclusive = 1;
72 module_param(vmm_exclusive, bool, S_IRUGO);
73
74 static int __read_mostly yield_on_hlt = 1;
75 module_param(yield_on_hlt, bool, S_IRUGO);
76
77 /*
78  * If nested=1, nested virtualization is supported, i.e., guests may use
79  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
80  * use VMX instructions.
81  */
82 static int __read_mostly nested = 0;
83 module_param(nested, bool, S_IRUGO);
84
85 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
86         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
87 #define KVM_GUEST_CR0_MASK                                              \
88         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
89 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
90         (X86_CR0_WP | X86_CR0_NE)
91 #define KVM_VM_CR0_ALWAYS_ON                                            \
92         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
93 #define KVM_CR4_GUEST_OWNED_BITS                                      \
94         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
95          | X86_CR4_OSXMMEXCPT)
96
97 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
98 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
99
100 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
101
102 /*
103  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
104  * ple_gap:    upper bound on the amount of time between two successive
105  *             executions of PAUSE in a loop. Also indicate if ple enabled.
106  *             According to test, this time is usually smaller than 128 cycles.
107  * ple_window: upper bound on the amount of time a guest is allowed to execute
108  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
109  *             less than 2^12 cycles
110  * Time is measured based on a counter that runs at the same rate as the TSC,
111  * refer SDM volume 3b section 21.6.13 & 22.1.3.
112  */
113 #define KVM_VMX_DEFAULT_PLE_GAP    128
114 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
115 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
116 module_param(ple_gap, int, S_IRUGO);
117
118 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
119 module_param(ple_window, int, S_IRUGO);
120
121 #define NR_AUTOLOAD_MSRS 1
122 #define VMCS02_POOL_SIZE 1
123
124 struct vmcs {
125         u32 revision_id;
126         u32 abort;
127         char data[0];
128 };
129
130 /*
131  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
132  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
133  * loaded on this CPU (so we can clear them if the CPU goes down).
134  */
135 struct loaded_vmcs {
136         struct vmcs *vmcs;
137         int cpu;
138         int launched;
139         struct list_head loaded_vmcss_on_cpu_link;
140 };
141
142 struct shared_msr_entry {
143         unsigned index;
144         u64 data;
145         u64 mask;
146 };
147
148 /*
149  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
150  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
151  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
152  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
153  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
154  * More than one of these structures may exist, if L1 runs multiple L2 guests.
155  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
156  * underlying hardware which will be used to run L2.
157  * This structure is packed to ensure that its layout is identical across
158  * machines (necessary for live migration).
159  * If there are changes in this struct, VMCS12_REVISION must be changed.
160  */
161 typedef u64 natural_width;
162 struct __packed vmcs12 {
163         /* According to the Intel spec, a VMCS region must start with the
164          * following two fields. Then follow implementation-specific data.
165          */
166         u32 revision_id;
167         u32 abort;
168
169         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
170         u32 padding[7]; /* room for future expansion */
171
172         u64 io_bitmap_a;
173         u64 io_bitmap_b;
174         u64 msr_bitmap;
175         u64 vm_exit_msr_store_addr;
176         u64 vm_exit_msr_load_addr;
177         u64 vm_entry_msr_load_addr;
178         u64 tsc_offset;
179         u64 virtual_apic_page_addr;
180         u64 apic_access_addr;
181         u64 ept_pointer;
182         u64 guest_physical_address;
183         u64 vmcs_link_pointer;
184         u64 guest_ia32_debugctl;
185         u64 guest_ia32_pat;
186         u64 guest_ia32_efer;
187         u64 guest_ia32_perf_global_ctrl;
188         u64 guest_pdptr0;
189         u64 guest_pdptr1;
190         u64 guest_pdptr2;
191         u64 guest_pdptr3;
192         u64 host_ia32_pat;
193         u64 host_ia32_efer;
194         u64 host_ia32_perf_global_ctrl;
195         u64 padding64[8]; /* room for future expansion */
196         /*
197          * To allow migration of L1 (complete with its L2 guests) between
198          * machines of different natural widths (32 or 64 bit), we cannot have
199          * unsigned long fields with no explict size. We use u64 (aliased
200          * natural_width) instead. Luckily, x86 is little-endian.
201          */
202         natural_width cr0_guest_host_mask;
203         natural_width cr4_guest_host_mask;
204         natural_width cr0_read_shadow;
205         natural_width cr4_read_shadow;
206         natural_width cr3_target_value0;
207         natural_width cr3_target_value1;
208         natural_width cr3_target_value2;
209         natural_width cr3_target_value3;
210         natural_width exit_qualification;
211         natural_width guest_linear_address;
212         natural_width guest_cr0;
213         natural_width guest_cr3;
214         natural_width guest_cr4;
215         natural_width guest_es_base;
216         natural_width guest_cs_base;
217         natural_width guest_ss_base;
218         natural_width guest_ds_base;
219         natural_width guest_fs_base;
220         natural_width guest_gs_base;
221         natural_width guest_ldtr_base;
222         natural_width guest_tr_base;
223         natural_width guest_gdtr_base;
224         natural_width guest_idtr_base;
225         natural_width guest_dr7;
226         natural_width guest_rsp;
227         natural_width guest_rip;
228         natural_width guest_rflags;
229         natural_width guest_pending_dbg_exceptions;
230         natural_width guest_sysenter_esp;
231         natural_width guest_sysenter_eip;
232         natural_width host_cr0;
233         natural_width host_cr3;
234         natural_width host_cr4;
235         natural_width host_fs_base;
236         natural_width host_gs_base;
237         natural_width host_tr_base;
238         natural_width host_gdtr_base;
239         natural_width host_idtr_base;
240         natural_width host_ia32_sysenter_esp;
241         natural_width host_ia32_sysenter_eip;
242         natural_width host_rsp;
243         natural_width host_rip;
244         natural_width paddingl[8]; /* room for future expansion */
245         u32 pin_based_vm_exec_control;
246         u32 cpu_based_vm_exec_control;
247         u32 exception_bitmap;
248         u32 page_fault_error_code_mask;
249         u32 page_fault_error_code_match;
250         u32 cr3_target_count;
251         u32 vm_exit_controls;
252         u32 vm_exit_msr_store_count;
253         u32 vm_exit_msr_load_count;
254         u32 vm_entry_controls;
255         u32 vm_entry_msr_load_count;
256         u32 vm_entry_intr_info_field;
257         u32 vm_entry_exception_error_code;
258         u32 vm_entry_instruction_len;
259         u32 tpr_threshold;
260         u32 secondary_vm_exec_control;
261         u32 vm_instruction_error;
262         u32 vm_exit_reason;
263         u32 vm_exit_intr_info;
264         u32 vm_exit_intr_error_code;
265         u32 idt_vectoring_info_field;
266         u32 idt_vectoring_error_code;
267         u32 vm_exit_instruction_len;
268         u32 vmx_instruction_info;
269         u32 guest_es_limit;
270         u32 guest_cs_limit;
271         u32 guest_ss_limit;
272         u32 guest_ds_limit;
273         u32 guest_fs_limit;
274         u32 guest_gs_limit;
275         u32 guest_ldtr_limit;
276         u32 guest_tr_limit;
277         u32 guest_gdtr_limit;
278         u32 guest_idtr_limit;
279         u32 guest_es_ar_bytes;
280         u32 guest_cs_ar_bytes;
281         u32 guest_ss_ar_bytes;
282         u32 guest_ds_ar_bytes;
283         u32 guest_fs_ar_bytes;
284         u32 guest_gs_ar_bytes;
285         u32 guest_ldtr_ar_bytes;
286         u32 guest_tr_ar_bytes;
287         u32 guest_interruptibility_info;
288         u32 guest_activity_state;
289         u32 guest_sysenter_cs;
290         u32 host_ia32_sysenter_cs;
291         u32 padding32[8]; /* room for future expansion */
292         u16 virtual_processor_id;
293         u16 guest_es_selector;
294         u16 guest_cs_selector;
295         u16 guest_ss_selector;
296         u16 guest_ds_selector;
297         u16 guest_fs_selector;
298         u16 guest_gs_selector;
299         u16 guest_ldtr_selector;
300         u16 guest_tr_selector;
301         u16 host_es_selector;
302         u16 host_cs_selector;
303         u16 host_ss_selector;
304         u16 host_ds_selector;
305         u16 host_fs_selector;
306         u16 host_gs_selector;
307         u16 host_tr_selector;
308 };
309
310 /*
311  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
312  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
313  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
314  */
315 #define VMCS12_REVISION 0x11e57ed0
316
317 /*
318  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
319  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
320  * current implementation, 4K are reserved to avoid future complications.
321  */
322 #define VMCS12_SIZE 0x1000
323
324 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
325 struct vmcs02_list {
326         struct list_head list;
327         gpa_t vmptr;
328         struct loaded_vmcs vmcs02;
329 };
330
331 /*
332  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
333  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
334  */
335 struct nested_vmx {
336         /* Has the level1 guest done vmxon? */
337         bool vmxon;
338
339         /* The guest-physical address of the current VMCS L1 keeps for L2 */
340         gpa_t current_vmptr;
341         /* The host-usable pointer to the above */
342         struct page *current_vmcs12_page;
343         struct vmcs12 *current_vmcs12;
344
345         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
346         struct list_head vmcs02_pool;
347         int vmcs02_num;
348         u64 vmcs01_tsc_offset;
349         /* L2 must run next, and mustn't decide to exit to L1. */
350         bool nested_run_pending;
351         /*
352          * Guest pages referred to in vmcs02 with host-physical pointers, so
353          * we must keep them pinned while L2 runs.
354          */
355         struct page *apic_access_page;
356 };
357
358 struct vcpu_vmx {
359         struct kvm_vcpu       vcpu;
360         unsigned long         host_rsp;
361         u8                    fail;
362         u8                    cpl;
363         bool                  nmi_known_unmasked;
364         u32                   exit_intr_info;
365         u32                   idt_vectoring_info;
366         ulong                 rflags;
367         struct shared_msr_entry *guest_msrs;
368         int                   nmsrs;
369         int                   save_nmsrs;
370 #ifdef CONFIG_X86_64
371         u64                   msr_host_kernel_gs_base;
372         u64                   msr_guest_kernel_gs_base;
373 #endif
374         /*
375          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
376          * non-nested (L1) guest, it always points to vmcs01. For a nested
377          * guest (L2), it points to a different VMCS.
378          */
379         struct loaded_vmcs    vmcs01;
380         struct loaded_vmcs   *loaded_vmcs;
381         bool                  __launched; /* temporary, used in vmx_vcpu_run */
382         struct msr_autoload {
383                 unsigned nr;
384                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
385                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
386         } msr_autoload;
387         struct {
388                 int           loaded;
389                 u16           fs_sel, gs_sel, ldt_sel;
390                 int           gs_ldt_reload_needed;
391                 int           fs_reload_needed;
392         } host_state;
393         struct {
394                 int vm86_active;
395                 ulong save_rflags;
396                 struct kvm_save_segment {
397                         u16 selector;
398                         unsigned long base;
399                         u32 limit;
400                         u32 ar;
401                 } tr, es, ds, fs, gs;
402         } rmode;
403         struct {
404                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
405                 struct kvm_save_segment seg[8];
406         } segment_cache;
407         int vpid;
408         bool emulation_required;
409
410         /* Support for vnmi-less CPUs */
411         int soft_vnmi_blocked;
412         ktime_t entry_time;
413         s64 vnmi_blocked_time;
414         u32 exit_reason;
415
416         bool rdtscp_enabled;
417
418         /* Support for a guest hypervisor (nested VMX) */
419         struct nested_vmx nested;
420 };
421
422 enum segment_cache_field {
423         SEG_FIELD_SEL = 0,
424         SEG_FIELD_BASE = 1,
425         SEG_FIELD_LIMIT = 2,
426         SEG_FIELD_AR = 3,
427
428         SEG_FIELD_NR = 4
429 };
430
431 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
432 {
433         return container_of(vcpu, struct vcpu_vmx, vcpu);
434 }
435
436 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
437 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
438 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
439                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
440
441 static unsigned short vmcs_field_to_offset_table[] = {
442         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
443         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
444         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
445         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
446         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
447         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
448         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
449         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
450         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
451         FIELD(HOST_ES_SELECTOR, host_es_selector),
452         FIELD(HOST_CS_SELECTOR, host_cs_selector),
453         FIELD(HOST_SS_SELECTOR, host_ss_selector),
454         FIELD(HOST_DS_SELECTOR, host_ds_selector),
455         FIELD(HOST_FS_SELECTOR, host_fs_selector),
456         FIELD(HOST_GS_SELECTOR, host_gs_selector),
457         FIELD(HOST_TR_SELECTOR, host_tr_selector),
458         FIELD64(IO_BITMAP_A, io_bitmap_a),
459         FIELD64(IO_BITMAP_B, io_bitmap_b),
460         FIELD64(MSR_BITMAP, msr_bitmap),
461         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
462         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
463         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
464         FIELD64(TSC_OFFSET, tsc_offset),
465         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
466         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
467         FIELD64(EPT_POINTER, ept_pointer),
468         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
469         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
470         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
471         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
472         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
473         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
474         FIELD64(GUEST_PDPTR0, guest_pdptr0),
475         FIELD64(GUEST_PDPTR1, guest_pdptr1),
476         FIELD64(GUEST_PDPTR2, guest_pdptr2),
477         FIELD64(GUEST_PDPTR3, guest_pdptr3),
478         FIELD64(HOST_IA32_PAT, host_ia32_pat),
479         FIELD64(HOST_IA32_EFER, host_ia32_efer),
480         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
481         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
482         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
483         FIELD(EXCEPTION_BITMAP, exception_bitmap),
484         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
485         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
486         FIELD(CR3_TARGET_COUNT, cr3_target_count),
487         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
488         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
489         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
490         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
491         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
492         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
493         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
494         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
495         FIELD(TPR_THRESHOLD, tpr_threshold),
496         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
497         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
498         FIELD(VM_EXIT_REASON, vm_exit_reason),
499         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
500         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
501         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
502         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
503         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
504         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
505         FIELD(GUEST_ES_LIMIT, guest_es_limit),
506         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
507         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
508         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
509         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
510         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
511         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
512         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
513         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
514         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
515         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
516         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
517         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
518         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
519         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
520         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
521         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
522         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
523         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
524         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
525         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
526         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
527         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
528         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
529         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
530         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
531         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
532         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
533         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
534         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
535         FIELD(EXIT_QUALIFICATION, exit_qualification),
536         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
537         FIELD(GUEST_CR0, guest_cr0),
538         FIELD(GUEST_CR3, guest_cr3),
539         FIELD(GUEST_CR4, guest_cr4),
540         FIELD(GUEST_ES_BASE, guest_es_base),
541         FIELD(GUEST_CS_BASE, guest_cs_base),
542         FIELD(GUEST_SS_BASE, guest_ss_base),
543         FIELD(GUEST_DS_BASE, guest_ds_base),
544         FIELD(GUEST_FS_BASE, guest_fs_base),
545         FIELD(GUEST_GS_BASE, guest_gs_base),
546         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
547         FIELD(GUEST_TR_BASE, guest_tr_base),
548         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
549         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
550         FIELD(GUEST_DR7, guest_dr7),
551         FIELD(GUEST_RSP, guest_rsp),
552         FIELD(GUEST_RIP, guest_rip),
553         FIELD(GUEST_RFLAGS, guest_rflags),
554         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
555         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
556         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
557         FIELD(HOST_CR0, host_cr0),
558         FIELD(HOST_CR3, host_cr3),
559         FIELD(HOST_CR4, host_cr4),
560         FIELD(HOST_FS_BASE, host_fs_base),
561         FIELD(HOST_GS_BASE, host_gs_base),
562         FIELD(HOST_TR_BASE, host_tr_base),
563         FIELD(HOST_GDTR_BASE, host_gdtr_base),
564         FIELD(HOST_IDTR_BASE, host_idtr_base),
565         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
566         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
567         FIELD(HOST_RSP, host_rsp),
568         FIELD(HOST_RIP, host_rip),
569 };
570 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
571
572 static inline short vmcs_field_to_offset(unsigned long field)
573 {
574         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
575                 return -1;
576         return vmcs_field_to_offset_table[field];
577 }
578
579 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
580 {
581         return to_vmx(vcpu)->nested.current_vmcs12;
582 }
583
584 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
585 {
586         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
587         if (is_error_page(page)) {
588                 kvm_release_page_clean(page);
589                 return NULL;
590         }
591         return page;
592 }
593
594 static void nested_release_page(struct page *page)
595 {
596         kvm_release_page_dirty(page);
597 }
598
599 static void nested_release_page_clean(struct page *page)
600 {
601         kvm_release_page_clean(page);
602 }
603
604 static u64 construct_eptp(unsigned long root_hpa);
605 static void kvm_cpu_vmxon(u64 addr);
606 static void kvm_cpu_vmxoff(void);
607 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
608 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
609
610 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
611 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
612 /*
613  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
614  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
615  */
616 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
617 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
618
619 static unsigned long *vmx_io_bitmap_a;
620 static unsigned long *vmx_io_bitmap_b;
621 static unsigned long *vmx_msr_bitmap_legacy;
622 static unsigned long *vmx_msr_bitmap_longmode;
623
624 static bool cpu_has_load_ia32_efer;
625
626 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
627 static DEFINE_SPINLOCK(vmx_vpid_lock);
628
629 static struct vmcs_config {
630         int size;
631         int order;
632         u32 revision_id;
633         u32 pin_based_exec_ctrl;
634         u32 cpu_based_exec_ctrl;
635         u32 cpu_based_2nd_exec_ctrl;
636         u32 vmexit_ctrl;
637         u32 vmentry_ctrl;
638 } vmcs_config;
639
640 static struct vmx_capability {
641         u32 ept;
642         u32 vpid;
643 } vmx_capability;
644
645 #define VMX_SEGMENT_FIELD(seg)                                  \
646         [VCPU_SREG_##seg] = {                                   \
647                 .selector = GUEST_##seg##_SELECTOR,             \
648                 .base = GUEST_##seg##_BASE,                     \
649                 .limit = GUEST_##seg##_LIMIT,                   \
650                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
651         }
652
653 static struct kvm_vmx_segment_field {
654         unsigned selector;
655         unsigned base;
656         unsigned limit;
657         unsigned ar_bytes;
658 } kvm_vmx_segment_fields[] = {
659         VMX_SEGMENT_FIELD(CS),
660         VMX_SEGMENT_FIELD(DS),
661         VMX_SEGMENT_FIELD(ES),
662         VMX_SEGMENT_FIELD(FS),
663         VMX_SEGMENT_FIELD(GS),
664         VMX_SEGMENT_FIELD(SS),
665         VMX_SEGMENT_FIELD(TR),
666         VMX_SEGMENT_FIELD(LDTR),
667 };
668
669 static u64 host_efer;
670
671 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
672
673 /*
674  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
675  * away by decrementing the array size.
676  */
677 static const u32 vmx_msr_index[] = {
678 #ifdef CONFIG_X86_64
679         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
680 #endif
681         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
682 };
683 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
684
685 static inline bool is_page_fault(u32 intr_info)
686 {
687         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
688                              INTR_INFO_VALID_MASK)) ==
689                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
690 }
691
692 static inline bool is_no_device(u32 intr_info)
693 {
694         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
695                              INTR_INFO_VALID_MASK)) ==
696                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
697 }
698
699 static inline bool is_invalid_opcode(u32 intr_info)
700 {
701         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
702                              INTR_INFO_VALID_MASK)) ==
703                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
704 }
705
706 static inline bool is_external_interrupt(u32 intr_info)
707 {
708         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
709                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
710 }
711
712 static inline bool is_machine_check(u32 intr_info)
713 {
714         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
715                              INTR_INFO_VALID_MASK)) ==
716                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
717 }
718
719 static inline bool cpu_has_vmx_msr_bitmap(void)
720 {
721         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
722 }
723
724 static inline bool cpu_has_vmx_tpr_shadow(void)
725 {
726         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
727 }
728
729 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
730 {
731         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
732 }
733
734 static inline bool cpu_has_secondary_exec_ctrls(void)
735 {
736         return vmcs_config.cpu_based_exec_ctrl &
737                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
738 }
739
740 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
741 {
742         return vmcs_config.cpu_based_2nd_exec_ctrl &
743                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
744 }
745
746 static inline bool cpu_has_vmx_flexpriority(void)
747 {
748         return cpu_has_vmx_tpr_shadow() &&
749                 cpu_has_vmx_virtualize_apic_accesses();
750 }
751
752 static inline bool cpu_has_vmx_ept_execute_only(void)
753 {
754         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
755 }
756
757 static inline bool cpu_has_vmx_eptp_uncacheable(void)
758 {
759         return vmx_capability.ept & VMX_EPTP_UC_BIT;
760 }
761
762 static inline bool cpu_has_vmx_eptp_writeback(void)
763 {
764         return vmx_capability.ept & VMX_EPTP_WB_BIT;
765 }
766
767 static inline bool cpu_has_vmx_ept_2m_page(void)
768 {
769         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
770 }
771
772 static inline bool cpu_has_vmx_ept_1g_page(void)
773 {
774         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
775 }
776
777 static inline bool cpu_has_vmx_ept_4levels(void)
778 {
779         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
780 }
781
782 static inline bool cpu_has_vmx_invept_individual_addr(void)
783 {
784         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
785 }
786
787 static inline bool cpu_has_vmx_invept_context(void)
788 {
789         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
790 }
791
792 static inline bool cpu_has_vmx_invept_global(void)
793 {
794         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
795 }
796
797 static inline bool cpu_has_vmx_invvpid_single(void)
798 {
799         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
800 }
801
802 static inline bool cpu_has_vmx_invvpid_global(void)
803 {
804         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
805 }
806
807 static inline bool cpu_has_vmx_ept(void)
808 {
809         return vmcs_config.cpu_based_2nd_exec_ctrl &
810                 SECONDARY_EXEC_ENABLE_EPT;
811 }
812
813 static inline bool cpu_has_vmx_unrestricted_guest(void)
814 {
815         return vmcs_config.cpu_based_2nd_exec_ctrl &
816                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
817 }
818
819 static inline bool cpu_has_vmx_ple(void)
820 {
821         return vmcs_config.cpu_based_2nd_exec_ctrl &
822                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
823 }
824
825 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
826 {
827         return flexpriority_enabled && irqchip_in_kernel(kvm);
828 }
829
830 static inline bool cpu_has_vmx_vpid(void)
831 {
832         return vmcs_config.cpu_based_2nd_exec_ctrl &
833                 SECONDARY_EXEC_ENABLE_VPID;
834 }
835
836 static inline bool cpu_has_vmx_rdtscp(void)
837 {
838         return vmcs_config.cpu_based_2nd_exec_ctrl &
839                 SECONDARY_EXEC_RDTSCP;
840 }
841
842 static inline bool cpu_has_virtual_nmis(void)
843 {
844         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
845 }
846
847 static inline bool cpu_has_vmx_wbinvd_exit(void)
848 {
849         return vmcs_config.cpu_based_2nd_exec_ctrl &
850                 SECONDARY_EXEC_WBINVD_EXITING;
851 }
852
853 static inline bool report_flexpriority(void)
854 {
855         return flexpriority_enabled;
856 }
857
858 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
859 {
860         return vmcs12->cpu_based_vm_exec_control & bit;
861 }
862
863 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
864 {
865         return (vmcs12->cpu_based_vm_exec_control &
866                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
867                 (vmcs12->secondary_vm_exec_control & bit);
868 }
869
870 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
871         struct kvm_vcpu *vcpu)
872 {
873         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
874 }
875
876 static inline bool is_exception(u32 intr_info)
877 {
878         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
879                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
880 }
881
882 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
883 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
884                         struct vmcs12 *vmcs12,
885                         u32 reason, unsigned long qualification);
886
887 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
888 {
889         int i;
890
891         for (i = 0; i < vmx->nmsrs; ++i)
892                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
893                         return i;
894         return -1;
895 }
896
897 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
898 {
899     struct {
900         u64 vpid : 16;
901         u64 rsvd : 48;
902         u64 gva;
903     } operand = { vpid, 0, gva };
904
905     asm volatile (__ex(ASM_VMX_INVVPID)
906                   /* CF==1 or ZF==1 --> rc = -1 */
907                   "; ja 1f ; ud2 ; 1:"
908                   : : "a"(&operand), "c"(ext) : "cc", "memory");
909 }
910
911 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
912 {
913         struct {
914                 u64 eptp, gpa;
915         } operand = {eptp, gpa};
916
917         asm volatile (__ex(ASM_VMX_INVEPT)
918                         /* CF==1 or ZF==1 --> rc = -1 */
919                         "; ja 1f ; ud2 ; 1:\n"
920                         : : "a" (&operand), "c" (ext) : "cc", "memory");
921 }
922
923 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
924 {
925         int i;
926
927         i = __find_msr_index(vmx, msr);
928         if (i >= 0)
929                 return &vmx->guest_msrs[i];
930         return NULL;
931 }
932
933 static void vmcs_clear(struct vmcs *vmcs)
934 {
935         u64 phys_addr = __pa(vmcs);
936         u8 error;
937
938         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
939                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
940                       : "cc", "memory");
941         if (error)
942                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
943                        vmcs, phys_addr);
944 }
945
946 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
947 {
948         vmcs_clear(loaded_vmcs->vmcs);
949         loaded_vmcs->cpu = -1;
950         loaded_vmcs->launched = 0;
951 }
952
953 static void vmcs_load(struct vmcs *vmcs)
954 {
955         u64 phys_addr = __pa(vmcs);
956         u8 error;
957
958         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
959                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
960                         : "cc", "memory");
961         if (error)
962                 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
963                        vmcs, phys_addr);
964 }
965
966 static void __loaded_vmcs_clear(void *arg)
967 {
968         struct loaded_vmcs *loaded_vmcs = arg;
969         int cpu = raw_smp_processor_id();
970
971         if (loaded_vmcs->cpu != cpu)
972                 return; /* vcpu migration can race with cpu offline */
973         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
974                 per_cpu(current_vmcs, cpu) = NULL;
975         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
976         loaded_vmcs_init(loaded_vmcs);
977 }
978
979 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
980 {
981         if (loaded_vmcs->cpu != -1)
982                 smp_call_function_single(
983                         loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
984 }
985
986 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
987 {
988         if (vmx->vpid == 0)
989                 return;
990
991         if (cpu_has_vmx_invvpid_single())
992                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
993 }
994
995 static inline void vpid_sync_vcpu_global(void)
996 {
997         if (cpu_has_vmx_invvpid_global())
998                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
999 }
1000
1001 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1002 {
1003         if (cpu_has_vmx_invvpid_single())
1004                 vpid_sync_vcpu_single(vmx);
1005         else
1006                 vpid_sync_vcpu_global();
1007 }
1008
1009 static inline void ept_sync_global(void)
1010 {
1011         if (cpu_has_vmx_invept_global())
1012                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1013 }
1014
1015 static inline void ept_sync_context(u64 eptp)
1016 {
1017         if (enable_ept) {
1018                 if (cpu_has_vmx_invept_context())
1019                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1020                 else
1021                         ept_sync_global();
1022         }
1023 }
1024
1025 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1026 {
1027         if (enable_ept) {
1028                 if (cpu_has_vmx_invept_individual_addr())
1029                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1030                                         eptp, gpa);
1031                 else
1032                         ept_sync_context(eptp);
1033         }
1034 }
1035
1036 static __always_inline unsigned long vmcs_readl(unsigned long field)
1037 {
1038         unsigned long value;
1039
1040         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1041                       : "=a"(value) : "d"(field) : "cc");
1042         return value;
1043 }
1044
1045 static __always_inline u16 vmcs_read16(unsigned long field)
1046 {
1047         return vmcs_readl(field);
1048 }
1049
1050 static __always_inline u32 vmcs_read32(unsigned long field)
1051 {
1052         return vmcs_readl(field);
1053 }
1054
1055 static __always_inline u64 vmcs_read64(unsigned long field)
1056 {
1057 #ifdef CONFIG_X86_64
1058         return vmcs_readl(field);
1059 #else
1060         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1061 #endif
1062 }
1063
1064 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1065 {
1066         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1067                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1068         dump_stack();
1069 }
1070
1071 static void vmcs_writel(unsigned long field, unsigned long value)
1072 {
1073         u8 error;
1074
1075         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1076                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1077         if (unlikely(error))
1078                 vmwrite_error(field, value);
1079 }
1080
1081 static void vmcs_write16(unsigned long field, u16 value)
1082 {
1083         vmcs_writel(field, value);
1084 }
1085
1086 static void vmcs_write32(unsigned long field, u32 value)
1087 {
1088         vmcs_writel(field, value);
1089 }
1090
1091 static void vmcs_write64(unsigned long field, u64 value)
1092 {
1093         vmcs_writel(field, value);
1094 #ifndef CONFIG_X86_64
1095         asm volatile ("");
1096         vmcs_writel(field+1, value >> 32);
1097 #endif
1098 }
1099
1100 static void vmcs_clear_bits(unsigned long field, u32 mask)
1101 {
1102         vmcs_writel(field, vmcs_readl(field) & ~mask);
1103 }
1104
1105 static void vmcs_set_bits(unsigned long field, u32 mask)
1106 {
1107         vmcs_writel(field, vmcs_readl(field) | mask);
1108 }
1109
1110 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1111 {
1112         vmx->segment_cache.bitmask = 0;
1113 }
1114
1115 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1116                                        unsigned field)
1117 {
1118         bool ret;
1119         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1120
1121         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1122                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1123                 vmx->segment_cache.bitmask = 0;
1124         }
1125         ret = vmx->segment_cache.bitmask & mask;
1126         vmx->segment_cache.bitmask |= mask;
1127         return ret;
1128 }
1129
1130 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1131 {
1132         u16 *p = &vmx->segment_cache.seg[seg].selector;
1133
1134         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1135                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1136         return *p;
1137 }
1138
1139 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1140 {
1141         ulong *p = &vmx->segment_cache.seg[seg].base;
1142
1143         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1144                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1145         return *p;
1146 }
1147
1148 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1149 {
1150         u32 *p = &vmx->segment_cache.seg[seg].limit;
1151
1152         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1153                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1154         return *p;
1155 }
1156
1157 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1158 {
1159         u32 *p = &vmx->segment_cache.seg[seg].ar;
1160
1161         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1162                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1163         return *p;
1164 }
1165
1166 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1167 {
1168         u32 eb;
1169
1170         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1171              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1172         if ((vcpu->guest_debug &
1173              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1174             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1175                 eb |= 1u << BP_VECTOR;
1176         if (to_vmx(vcpu)->rmode.vm86_active)
1177                 eb = ~0;
1178         if (enable_ept)
1179                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1180         if (vcpu->fpu_active)
1181                 eb &= ~(1u << NM_VECTOR);
1182         vmcs_write32(EXCEPTION_BITMAP, eb);
1183 }
1184
1185 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1186 {
1187         unsigned i;
1188         struct msr_autoload *m = &vmx->msr_autoload;
1189
1190         if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
1191                 vmcs_clear_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
1192                 vmcs_clear_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
1193                 return;
1194         }
1195
1196         for (i = 0; i < m->nr; ++i)
1197                 if (m->guest[i].index == msr)
1198                         break;
1199
1200         if (i == m->nr)
1201                 return;
1202         --m->nr;
1203         m->guest[i] = m->guest[m->nr];
1204         m->host[i] = m->host[m->nr];
1205         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1206         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1207 }
1208
1209 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1210                                   u64 guest_val, u64 host_val)
1211 {
1212         unsigned i;
1213         struct msr_autoload *m = &vmx->msr_autoload;
1214
1215         if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
1216                 vmcs_write64(GUEST_IA32_EFER, guest_val);
1217                 vmcs_write64(HOST_IA32_EFER, host_val);
1218                 vmcs_set_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
1219                 vmcs_set_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
1220                 return;
1221         }
1222
1223         for (i = 0; i < m->nr; ++i)
1224                 if (m->guest[i].index == msr)
1225                         break;
1226
1227         if (i == m->nr) {
1228                 ++m->nr;
1229                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1230                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1231         }
1232
1233         m->guest[i].index = msr;
1234         m->guest[i].value = guest_val;
1235         m->host[i].index = msr;
1236         m->host[i].value = host_val;
1237 }
1238
1239 static void reload_tss(void)
1240 {
1241         /*
1242          * VT restores TR but not its size.  Useless.
1243          */
1244         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1245         struct desc_struct *descs;
1246
1247         descs = (void *)gdt->address;
1248         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1249         load_TR_desc();
1250 }
1251
1252 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1253 {
1254         u64 guest_efer;
1255         u64 ignore_bits;
1256
1257         guest_efer = vmx->vcpu.arch.efer;
1258
1259         /*
1260          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1261          * outside long mode
1262          */
1263         ignore_bits = EFER_NX | EFER_SCE;
1264 #ifdef CONFIG_X86_64
1265         ignore_bits |= EFER_LMA | EFER_LME;
1266         /* SCE is meaningful only in long mode on Intel */
1267         if (guest_efer & EFER_LMA)
1268                 ignore_bits &= ~(u64)EFER_SCE;
1269 #endif
1270         guest_efer &= ~ignore_bits;
1271         guest_efer |= host_efer & ignore_bits;
1272         vmx->guest_msrs[efer_offset].data = guest_efer;
1273         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1274
1275         clear_atomic_switch_msr(vmx, MSR_EFER);
1276         /* On ept, can't emulate nx, and must switch nx atomically */
1277         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1278                 guest_efer = vmx->vcpu.arch.efer;
1279                 if (!(guest_efer & EFER_LMA))
1280                         guest_efer &= ~EFER_LME;
1281                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1282                 return false;
1283         }
1284
1285         return true;
1286 }
1287
1288 static unsigned long segment_base(u16 selector)
1289 {
1290         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1291         struct desc_struct *d;
1292         unsigned long table_base;
1293         unsigned long v;
1294
1295         if (!(selector & ~3))
1296                 return 0;
1297
1298         table_base = gdt->address;
1299
1300         if (selector & 4) {           /* from ldt */
1301                 u16 ldt_selector = kvm_read_ldt();
1302
1303                 if (!(ldt_selector & ~3))
1304                         return 0;
1305
1306                 table_base = segment_base(ldt_selector);
1307         }
1308         d = (struct desc_struct *)(table_base + (selector & ~7));
1309         v = get_desc_base(d);
1310 #ifdef CONFIG_X86_64
1311        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1312                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1313 #endif
1314         return v;
1315 }
1316
1317 static inline unsigned long kvm_read_tr_base(void)
1318 {
1319         u16 tr;
1320         asm("str %0" : "=g"(tr));
1321         return segment_base(tr);
1322 }
1323
1324 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1325 {
1326         struct vcpu_vmx *vmx = to_vmx(vcpu);
1327         int i;
1328
1329         if (vmx->host_state.loaded)
1330                 return;
1331
1332         vmx->host_state.loaded = 1;
1333         /*
1334          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1335          * allow segment selectors with cpl > 0 or ti == 1.
1336          */
1337         vmx->host_state.ldt_sel = kvm_read_ldt();
1338         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1339         savesegment(fs, vmx->host_state.fs_sel);
1340         if (!(vmx->host_state.fs_sel & 7)) {
1341                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1342                 vmx->host_state.fs_reload_needed = 0;
1343         } else {
1344                 vmcs_write16(HOST_FS_SELECTOR, 0);
1345                 vmx->host_state.fs_reload_needed = 1;
1346         }
1347         savesegment(gs, vmx->host_state.gs_sel);
1348         if (!(vmx->host_state.gs_sel & 7))
1349                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1350         else {
1351                 vmcs_write16(HOST_GS_SELECTOR, 0);
1352                 vmx->host_state.gs_ldt_reload_needed = 1;
1353         }
1354
1355 #ifdef CONFIG_X86_64
1356         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1357         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1358 #else
1359         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1360         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1361 #endif
1362
1363 #ifdef CONFIG_X86_64
1364         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1365         if (is_long_mode(&vmx->vcpu))
1366                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1367 #endif
1368         for (i = 0; i < vmx->save_nmsrs; ++i)
1369                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1370                                    vmx->guest_msrs[i].data,
1371                                    vmx->guest_msrs[i].mask);
1372 }
1373
1374 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1375 {
1376         if (!vmx->host_state.loaded)
1377                 return;
1378
1379         ++vmx->vcpu.stat.host_state_reload;
1380         vmx->host_state.loaded = 0;
1381 #ifdef CONFIG_X86_64
1382         if (is_long_mode(&vmx->vcpu))
1383                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1384 #endif
1385         if (vmx->host_state.gs_ldt_reload_needed) {
1386                 kvm_load_ldt(vmx->host_state.ldt_sel);
1387 #ifdef CONFIG_X86_64
1388                 load_gs_index(vmx->host_state.gs_sel);
1389 #else
1390                 loadsegment(gs, vmx->host_state.gs_sel);
1391 #endif
1392         }
1393         if (vmx->host_state.fs_reload_needed)
1394                 loadsegment(fs, vmx->host_state.fs_sel);
1395         reload_tss();
1396 #ifdef CONFIG_X86_64
1397         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1398 #endif
1399         if (current_thread_info()->status & TS_USEDFPU)
1400                 clts();
1401         load_gdt(&__get_cpu_var(host_gdt));
1402 }
1403
1404 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1405 {
1406         preempt_disable();
1407         __vmx_load_host_state(vmx);
1408         preempt_enable();
1409 }
1410
1411 /*
1412  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1413  * vcpu mutex is already taken.
1414  */
1415 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1416 {
1417         struct vcpu_vmx *vmx = to_vmx(vcpu);
1418         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1419
1420         if (!vmm_exclusive)
1421                 kvm_cpu_vmxon(phys_addr);
1422         else if (vmx->loaded_vmcs->cpu != cpu)
1423                 loaded_vmcs_clear(vmx->loaded_vmcs);
1424
1425         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1426                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1427                 vmcs_load(vmx->loaded_vmcs->vmcs);
1428         }
1429
1430         if (vmx->loaded_vmcs->cpu != cpu) {
1431                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1432                 unsigned long sysenter_esp;
1433
1434                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1435                 local_irq_disable();
1436                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1437                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1438                 local_irq_enable();
1439
1440                 /*
1441                  * Linux uses per-cpu TSS and GDT, so set these when switching
1442                  * processors.
1443                  */
1444                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1445                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1446
1447                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1448                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1449                 vmx->loaded_vmcs->cpu = cpu;
1450         }
1451 }
1452
1453 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1454 {
1455         __vmx_load_host_state(to_vmx(vcpu));
1456         if (!vmm_exclusive) {
1457                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1458                 vcpu->cpu = -1;
1459                 kvm_cpu_vmxoff();
1460         }
1461 }
1462
1463 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1464 {
1465         ulong cr0;
1466
1467         if (vcpu->fpu_active)
1468                 return;
1469         vcpu->fpu_active = 1;
1470         cr0 = vmcs_readl(GUEST_CR0);
1471         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1472         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1473         vmcs_writel(GUEST_CR0, cr0);
1474         update_exception_bitmap(vcpu);
1475         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1476         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1477 }
1478
1479 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1480
1481 /*
1482  * Return the cr0 value that a nested guest would read. This is a combination
1483  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1484  * its hypervisor (cr0_read_shadow).
1485  */
1486 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1487 {
1488         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1489                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1490 }
1491 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1492 {
1493         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1494                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1495 }
1496
1497 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1498 {
1499         vmx_decache_cr0_guest_bits(vcpu);
1500         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1501         update_exception_bitmap(vcpu);
1502         vcpu->arch.cr0_guest_owned_bits = 0;
1503         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1504         vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1505 }
1506
1507 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1508 {
1509         unsigned long rflags, save_rflags;
1510
1511         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1512                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1513                 rflags = vmcs_readl(GUEST_RFLAGS);
1514                 if (to_vmx(vcpu)->rmode.vm86_active) {
1515                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1516                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1517                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1518                 }
1519                 to_vmx(vcpu)->rflags = rflags;
1520         }
1521         return to_vmx(vcpu)->rflags;
1522 }
1523
1524 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1525 {
1526         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1527         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
1528         to_vmx(vcpu)->rflags = rflags;
1529         if (to_vmx(vcpu)->rmode.vm86_active) {
1530                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1531                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1532         }
1533         vmcs_writel(GUEST_RFLAGS, rflags);
1534 }
1535
1536 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1537 {
1538         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1539         int ret = 0;
1540
1541         if (interruptibility & GUEST_INTR_STATE_STI)
1542                 ret |= KVM_X86_SHADOW_INT_STI;
1543         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1544                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1545
1546         return ret & mask;
1547 }
1548
1549 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1550 {
1551         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1552         u32 interruptibility = interruptibility_old;
1553
1554         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1555
1556         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1557                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1558         else if (mask & KVM_X86_SHADOW_INT_STI)
1559                 interruptibility |= GUEST_INTR_STATE_STI;
1560
1561         if ((interruptibility != interruptibility_old))
1562                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1563 }
1564
1565 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1566 {
1567         unsigned long rip;
1568
1569         rip = kvm_rip_read(vcpu);
1570         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1571         kvm_rip_write(vcpu, rip);
1572
1573         /* skipping an emulated instruction also counts */
1574         vmx_set_interrupt_shadow(vcpu, 0);
1575 }
1576
1577 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1578 {
1579         /* Ensure that we clear the HLT state in the VMCS.  We don't need to
1580          * explicitly skip the instruction because if the HLT state is set, then
1581          * the instruction is already executing and RIP has already been
1582          * advanced. */
1583         if (!yield_on_hlt &&
1584             vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1585                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1586 }
1587
1588 /*
1589  * KVM wants to inject page-faults which it got to the guest. This function
1590  * checks whether in a nested guest, we need to inject them to L1 or L2.
1591  * This function assumes it is called with the exit reason in vmcs02 being
1592  * a #PF exception (this is the only case in which KVM injects a #PF when L2
1593  * is running).
1594  */
1595 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1596 {
1597         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1598
1599         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1600         if (!(vmcs12->exception_bitmap & PF_VECTOR))
1601                 return 0;
1602
1603         nested_vmx_vmexit(vcpu);
1604         return 1;
1605 }
1606
1607 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1608                                 bool has_error_code, u32 error_code,
1609                                 bool reinject)
1610 {
1611         struct vcpu_vmx *vmx = to_vmx(vcpu);
1612         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1613
1614         if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1615                 nested_pf_handled(vcpu))
1616                 return;
1617
1618         if (has_error_code) {
1619                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1620                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1621         }
1622
1623         if (vmx->rmode.vm86_active) {
1624                 int inc_eip = 0;
1625                 if (kvm_exception_is_soft(nr))
1626                         inc_eip = vcpu->arch.event_exit_inst_len;
1627                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1628                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1629                 return;
1630         }
1631
1632         if (kvm_exception_is_soft(nr)) {
1633                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1634                              vmx->vcpu.arch.event_exit_inst_len);
1635                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1636         } else
1637                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1638
1639         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1640         vmx_clear_hlt(vcpu);
1641 }
1642
1643 static bool vmx_rdtscp_supported(void)
1644 {
1645         return cpu_has_vmx_rdtscp();
1646 }
1647
1648 /*
1649  * Swap MSR entry in host/guest MSR entry array.
1650  */
1651 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1652 {
1653         struct shared_msr_entry tmp;
1654
1655         tmp = vmx->guest_msrs[to];
1656         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1657         vmx->guest_msrs[from] = tmp;
1658 }
1659
1660 /*
1661  * Set up the vmcs to automatically save and restore system
1662  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1663  * mode, as fiddling with msrs is very expensive.
1664  */
1665 static void setup_msrs(struct vcpu_vmx *vmx)
1666 {
1667         int save_nmsrs, index;
1668         unsigned long *msr_bitmap;
1669
1670         vmx_load_host_state(vmx);
1671         save_nmsrs = 0;
1672 #ifdef CONFIG_X86_64
1673         if (is_long_mode(&vmx->vcpu)) {
1674                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1675                 if (index >= 0)
1676                         move_msr_up(vmx, index, save_nmsrs++);
1677                 index = __find_msr_index(vmx, MSR_LSTAR);
1678                 if (index >= 0)
1679                         move_msr_up(vmx, index, save_nmsrs++);
1680                 index = __find_msr_index(vmx, MSR_CSTAR);
1681                 if (index >= 0)
1682                         move_msr_up(vmx, index, save_nmsrs++);
1683                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1684                 if (index >= 0 && vmx->rdtscp_enabled)
1685                         move_msr_up(vmx, index, save_nmsrs++);
1686                 /*
1687                  * MSR_STAR is only needed on long mode guests, and only
1688                  * if efer.sce is enabled.
1689                  */
1690                 index = __find_msr_index(vmx, MSR_STAR);
1691                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1692                         move_msr_up(vmx, index, save_nmsrs++);
1693         }
1694 #endif
1695         index = __find_msr_index(vmx, MSR_EFER);
1696         if (index >= 0 && update_transition_efer(vmx, index))
1697                 move_msr_up(vmx, index, save_nmsrs++);
1698
1699         vmx->save_nmsrs = save_nmsrs;
1700
1701         if (cpu_has_vmx_msr_bitmap()) {
1702                 if (is_long_mode(&vmx->vcpu))
1703                         msr_bitmap = vmx_msr_bitmap_longmode;
1704                 else
1705                         msr_bitmap = vmx_msr_bitmap_legacy;
1706
1707                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1708         }
1709 }
1710
1711 /*
1712  * reads and returns guest's timestamp counter "register"
1713  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1714  */
1715 static u64 guest_read_tsc(void)
1716 {
1717         u64 host_tsc, tsc_offset;
1718
1719         rdtscll(host_tsc);
1720         tsc_offset = vmcs_read64(TSC_OFFSET);
1721         return host_tsc + tsc_offset;
1722 }
1723
1724 /*
1725  * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ
1726  * ioctl. In this case the call-back should update internal vmx state to make
1727  * the changes effective.
1728  */
1729 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1730 {
1731         /* Nothing to do here */
1732 }
1733
1734 /*
1735  * writes 'offset' into guest's timestamp counter offset register
1736  */
1737 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1738 {
1739         vmcs_write64(TSC_OFFSET, offset);
1740 }
1741
1742 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1743 {
1744         u64 offset = vmcs_read64(TSC_OFFSET);
1745         vmcs_write64(TSC_OFFSET, offset + adjustment);
1746 }
1747
1748 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1749 {
1750         return target_tsc - native_read_tsc();
1751 }
1752
1753 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1754 {
1755         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1756         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1757 }
1758
1759 /*
1760  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1761  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1762  * all guests if the "nested" module option is off, and can also be disabled
1763  * for a single guest by disabling its VMX cpuid bit.
1764  */
1765 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1766 {
1767         return nested && guest_cpuid_has_vmx(vcpu);
1768 }
1769
1770 /*
1771  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1772  * returned for the various VMX controls MSRs when nested VMX is enabled.
1773  * The same values should also be used to verify that vmcs12 control fields are
1774  * valid during nested entry from L1 to L2.
1775  * Each of these control msrs has a low and high 32-bit half: A low bit is on
1776  * if the corresponding bit in the (32-bit) control field *must* be on, and a
1777  * bit in the high half is on if the corresponding bit in the control field
1778  * may be on. See also vmx_control_verify().
1779  * TODO: allow these variables to be modified (downgraded) by module options
1780  * or other means.
1781  */
1782 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1783 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1784 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1785 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1786 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1787 static __init void nested_vmx_setup_ctls_msrs(void)
1788 {
1789         /*
1790          * Note that as a general rule, the high half of the MSRs (bits in
1791          * the control fields which may be 1) should be initialized by the
1792          * intersection of the underlying hardware's MSR (i.e., features which
1793          * can be supported) and the list of features we want to expose -
1794          * because they are known to be properly supported in our code.
1795          * Also, usually, the low half of the MSRs (bits which must be 1) can
1796          * be set to 0, meaning that L1 may turn off any of these bits. The
1797          * reason is that if one of these bits is necessary, it will appear
1798          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1799          * fields of vmcs01 and vmcs02, will turn these bits off - and
1800          * nested_vmx_exit_handled() will not pass related exits to L1.
1801          * These rules have exceptions below.
1802          */
1803
1804         /* pin-based controls */
1805         /*
1806          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1807          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1808          */
1809         nested_vmx_pinbased_ctls_low = 0x16 ;
1810         nested_vmx_pinbased_ctls_high = 0x16 |
1811                 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1812                 PIN_BASED_VIRTUAL_NMIS;
1813
1814         /* exit controls */
1815         nested_vmx_exit_ctls_low = 0;
1816         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
1817 #ifdef CONFIG_X86_64
1818         nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1819 #else
1820         nested_vmx_exit_ctls_high = 0;
1821 #endif
1822
1823         /* entry controls */
1824         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1825                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1826         nested_vmx_entry_ctls_low = 0;
1827         nested_vmx_entry_ctls_high &=
1828                 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1829
1830         /* cpu-based controls */
1831         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1832                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1833         nested_vmx_procbased_ctls_low = 0;
1834         nested_vmx_procbased_ctls_high &=
1835                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1836                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1837                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1838                 CPU_BASED_CR3_STORE_EXITING |
1839 #ifdef CONFIG_X86_64
1840                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1841 #endif
1842                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1843                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1844                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1845         /*
1846          * We can allow some features even when not supported by the
1847          * hardware. For example, L1 can specify an MSR bitmap - and we
1848          * can use it to avoid exits to L1 - even when L0 runs L2
1849          * without MSR bitmaps.
1850          */
1851         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
1852
1853         /* secondary cpu-based controls */
1854         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
1855                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
1856         nested_vmx_secondary_ctls_low = 0;
1857         nested_vmx_secondary_ctls_high &=
1858                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1859 }
1860
1861 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
1862 {
1863         /*
1864          * Bits 0 in high must be 0, and bits 1 in low must be 1.
1865          */
1866         return ((control & high) | low) == control;
1867 }
1868
1869 static inline u64 vmx_control_msr(u32 low, u32 high)
1870 {
1871         return low | ((u64)high << 32);
1872 }
1873
1874 /*
1875  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
1876  * also let it use VMX-specific MSRs.
1877  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
1878  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
1879  * like all other MSRs).
1880  */
1881 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1882 {
1883         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
1884                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
1885                 /*
1886                  * According to the spec, processors which do not support VMX
1887                  * should throw a #GP(0) when VMX capability MSRs are read.
1888                  */
1889                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
1890                 return 1;
1891         }
1892
1893         switch (msr_index) {
1894         case MSR_IA32_FEATURE_CONTROL:
1895                 *pdata = 0;
1896                 break;
1897         case MSR_IA32_VMX_BASIC:
1898                 /*
1899                  * This MSR reports some information about VMX support. We
1900                  * should return information about the VMX we emulate for the
1901                  * guest, and the VMCS structure we give it - not about the
1902                  * VMX support of the underlying hardware.
1903                  */
1904                 *pdata = VMCS12_REVISION |
1905                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
1906                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
1907                 break;
1908         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
1909         case MSR_IA32_VMX_PINBASED_CTLS:
1910                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
1911                                         nested_vmx_pinbased_ctls_high);
1912                 break;
1913         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
1914         case MSR_IA32_VMX_PROCBASED_CTLS:
1915                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
1916                                         nested_vmx_procbased_ctls_high);
1917                 break;
1918         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
1919         case MSR_IA32_VMX_EXIT_CTLS:
1920                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
1921                                         nested_vmx_exit_ctls_high);
1922                 break;
1923         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
1924         case MSR_IA32_VMX_ENTRY_CTLS:
1925                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
1926                                         nested_vmx_entry_ctls_high);
1927                 break;
1928         case MSR_IA32_VMX_MISC:
1929                 *pdata = 0;
1930                 break;
1931         /*
1932          * These MSRs specify bits which the guest must keep fixed (on or off)
1933          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
1934          * We picked the standard core2 setting.
1935          */
1936 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
1937 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
1938         case MSR_IA32_VMX_CR0_FIXED0:
1939                 *pdata = VMXON_CR0_ALWAYSON;
1940                 break;
1941         case MSR_IA32_VMX_CR0_FIXED1:
1942                 *pdata = -1ULL;
1943                 break;
1944         case MSR_IA32_VMX_CR4_FIXED0:
1945                 *pdata = VMXON_CR4_ALWAYSON;
1946                 break;
1947         case MSR_IA32_VMX_CR4_FIXED1:
1948                 *pdata = -1ULL;
1949                 break;
1950         case MSR_IA32_VMX_VMCS_ENUM:
1951                 *pdata = 0x1f;
1952                 break;
1953         case MSR_IA32_VMX_PROCBASED_CTLS2:
1954                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
1955                                         nested_vmx_secondary_ctls_high);
1956                 break;
1957         case MSR_IA32_VMX_EPT_VPID_CAP:
1958                 /* Currently, no nested ept or nested vpid */
1959                 *pdata = 0;
1960                 break;
1961         default:
1962                 return 0;
1963         }
1964
1965         return 1;
1966 }
1967
1968 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1969 {
1970         if (!nested_vmx_allowed(vcpu))
1971                 return 0;
1972
1973         if (msr_index == MSR_IA32_FEATURE_CONTROL)
1974                 /* TODO: the right thing. */
1975                 return 1;
1976         /*
1977          * No need to treat VMX capability MSRs specially: If we don't handle
1978          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
1979          */
1980         return 0;
1981 }
1982
1983 /*
1984  * Reads an msr value (of 'msr_index') into 'pdata'.
1985  * Returns 0 on success, non-0 otherwise.
1986  * Assumes vcpu_load() was already called.
1987  */
1988 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1989 {
1990         u64 data;
1991         struct shared_msr_entry *msr;
1992
1993         if (!pdata) {
1994                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1995                 return -EINVAL;
1996         }
1997
1998         switch (msr_index) {
1999 #ifdef CONFIG_X86_64
2000         case MSR_FS_BASE:
2001                 data = vmcs_readl(GUEST_FS_BASE);
2002                 break;
2003         case MSR_GS_BASE:
2004                 data = vmcs_readl(GUEST_GS_BASE);
2005                 break;
2006         case MSR_KERNEL_GS_BASE:
2007                 vmx_load_host_state(to_vmx(vcpu));
2008                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2009                 break;
2010 #endif
2011         case MSR_EFER:
2012                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2013         case MSR_IA32_TSC:
2014                 data = guest_read_tsc();
2015                 break;
2016         case MSR_IA32_SYSENTER_CS:
2017                 data = vmcs_read32(GUEST_SYSENTER_CS);
2018                 break;
2019         case MSR_IA32_SYSENTER_EIP:
2020                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2021                 break;
2022         case MSR_IA32_SYSENTER_ESP:
2023                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2024                 break;
2025         case MSR_TSC_AUX:
2026                 if (!to_vmx(vcpu)->rdtscp_enabled)
2027                         return 1;
2028                 /* Otherwise falls through */
2029         default:
2030                 vmx_load_host_state(to_vmx(vcpu));
2031                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2032                         return 0;
2033                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2034                 if (msr) {
2035                         vmx_load_host_state(to_vmx(vcpu));
2036                         data = msr->data;
2037                         break;
2038                 }
2039                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2040         }
2041
2042         *pdata = data;
2043         return 0;
2044 }
2045
2046 /*
2047  * Writes msr value into into the appropriate "register".
2048  * Returns 0 on success, non-0 otherwise.
2049  * Assumes vcpu_load() was already called.
2050  */
2051 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2052 {
2053         struct vcpu_vmx *vmx = to_vmx(vcpu);
2054         struct shared_msr_entry *msr;
2055         int ret = 0;
2056
2057         switch (msr_index) {
2058         case MSR_EFER:
2059                 vmx_load_host_state(vmx);
2060                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2061                 break;
2062 #ifdef CONFIG_X86_64
2063         case MSR_FS_BASE:
2064                 vmx_segment_cache_clear(vmx);
2065                 vmcs_writel(GUEST_FS_BASE, data);
2066                 break;
2067         case MSR_GS_BASE:
2068                 vmx_segment_cache_clear(vmx);
2069                 vmcs_writel(GUEST_GS_BASE, data);
2070                 break;
2071         case MSR_KERNEL_GS_BASE:
2072                 vmx_load_host_state(vmx);
2073                 vmx->msr_guest_kernel_gs_base = data;
2074                 break;
2075 #endif
2076         case MSR_IA32_SYSENTER_CS:
2077                 vmcs_write32(GUEST_SYSENTER_CS, data);
2078                 break;
2079         case MSR_IA32_SYSENTER_EIP:
2080                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2081                 break;
2082         case MSR_IA32_SYSENTER_ESP:
2083                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2084                 break;
2085         case MSR_IA32_TSC:
2086                 kvm_write_tsc(vcpu, data);
2087                 break;
2088         case MSR_IA32_CR_PAT:
2089                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2090                         vmcs_write64(GUEST_IA32_PAT, data);
2091                         vcpu->arch.pat = data;
2092                         break;
2093                 }
2094                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2095                 break;
2096         case MSR_TSC_AUX:
2097                 if (!vmx->rdtscp_enabled)
2098                         return 1;
2099                 /* Check reserved bit, higher 32 bits should be zero */
2100                 if ((data >> 32) != 0)
2101                         return 1;
2102                 /* Otherwise falls through */
2103         default:
2104                 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2105                         break;
2106                 msr = find_msr_entry(vmx, msr_index);
2107                 if (msr) {
2108                         vmx_load_host_state(vmx);
2109                         msr->data = data;
2110                         break;
2111                 }
2112                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2113         }
2114
2115         return ret;
2116 }
2117
2118 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2119 {
2120         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2121         switch (reg) {
2122         case VCPU_REGS_RSP:
2123                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2124                 break;
2125         case VCPU_REGS_RIP:
2126                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2127                 break;
2128         case VCPU_EXREG_PDPTR:
2129                 if (enable_ept)
2130                         ept_save_pdptrs(vcpu);
2131                 break;
2132         default:
2133                 break;
2134         }
2135 }
2136
2137 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
2138 {
2139         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2140                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2141         else
2142                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2143
2144         update_exception_bitmap(vcpu);
2145 }
2146
2147 static __init int cpu_has_kvm_support(void)
2148 {
2149         return cpu_has_vmx();
2150 }
2151
2152 static __init int vmx_disabled_by_bios(void)
2153 {
2154         u64 msr;
2155
2156         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2157         if (msr & FEATURE_CONTROL_LOCKED) {
2158                 /* launched w/ TXT and VMX disabled */
2159                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2160                         && tboot_enabled())
2161                         return 1;
2162                 /* launched w/o TXT and VMX only enabled w/ TXT */
2163                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2164                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2165                         && !tboot_enabled()) {
2166                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2167                                 "activate TXT before enabling KVM\n");
2168                         return 1;
2169                 }
2170                 /* launched w/o TXT and VMX disabled */
2171                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2172                         && !tboot_enabled())
2173                         return 1;
2174         }
2175
2176         return 0;
2177 }
2178
2179 static void kvm_cpu_vmxon(u64 addr)
2180 {
2181         asm volatile (ASM_VMX_VMXON_RAX
2182                         : : "a"(&addr), "m"(addr)
2183                         : "memory", "cc");
2184 }
2185
2186 static int hardware_enable(void *garbage)
2187 {
2188         int cpu = raw_smp_processor_id();
2189         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2190         u64 old, test_bits;
2191
2192         if (read_cr4() & X86_CR4_VMXE)
2193                 return -EBUSY;
2194
2195         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2196         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2197
2198         test_bits = FEATURE_CONTROL_LOCKED;
2199         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2200         if (tboot_enabled())
2201                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2202
2203         if ((old & test_bits) != test_bits) {
2204                 /* enable and lock */
2205                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2206         }
2207         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2208
2209         if (vmm_exclusive) {
2210                 kvm_cpu_vmxon(phys_addr);
2211                 ept_sync_global();
2212         }
2213
2214         store_gdt(&__get_cpu_var(host_gdt));
2215
2216         return 0;
2217 }
2218
2219 static void vmclear_local_loaded_vmcss(void)
2220 {
2221         int cpu = raw_smp_processor_id();
2222         struct loaded_vmcs *v, *n;
2223
2224         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2225                                  loaded_vmcss_on_cpu_link)
2226                 __loaded_vmcs_clear(v);
2227 }
2228
2229
2230 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2231  * tricks.
2232  */
2233 static void kvm_cpu_vmxoff(void)
2234 {
2235         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2236 }
2237
2238 static void hardware_disable(void *garbage)
2239 {
2240         if (vmm_exclusive) {
2241                 vmclear_local_loaded_vmcss();
2242                 kvm_cpu_vmxoff();
2243         }
2244         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2245 }
2246
2247 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2248                                       u32 msr, u32 *result)
2249 {
2250         u32 vmx_msr_low, vmx_msr_high;
2251         u32 ctl = ctl_min | ctl_opt;
2252
2253         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2254
2255         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2256         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2257
2258         /* Ensure minimum (required) set of control bits are supported. */
2259         if (ctl_min & ~ctl)
2260                 return -EIO;
2261
2262         *result = ctl;
2263         return 0;
2264 }
2265
2266 static __init bool allow_1_setting(u32 msr, u32 ctl)
2267 {
2268         u32 vmx_msr_low, vmx_msr_high;
2269
2270         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2271         return vmx_msr_high & ctl;
2272 }
2273
2274 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2275 {
2276         u32 vmx_msr_low, vmx_msr_high;
2277         u32 min, opt, min2, opt2;
2278         u32 _pin_based_exec_control = 0;
2279         u32 _cpu_based_exec_control = 0;
2280         u32 _cpu_based_2nd_exec_control = 0;
2281         u32 _vmexit_control = 0;
2282         u32 _vmentry_control = 0;
2283
2284         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2285         opt = PIN_BASED_VIRTUAL_NMIS;
2286         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2287                                 &_pin_based_exec_control) < 0)
2288                 return -EIO;
2289
2290         min =
2291 #ifdef CONFIG_X86_64
2292               CPU_BASED_CR8_LOAD_EXITING |
2293               CPU_BASED_CR8_STORE_EXITING |
2294 #endif
2295               CPU_BASED_CR3_LOAD_EXITING |
2296               CPU_BASED_CR3_STORE_EXITING |
2297               CPU_BASED_USE_IO_BITMAPS |
2298               CPU_BASED_MOV_DR_EXITING |
2299               CPU_BASED_USE_TSC_OFFSETING |
2300               CPU_BASED_MWAIT_EXITING |
2301               CPU_BASED_MONITOR_EXITING |
2302               CPU_BASED_INVLPG_EXITING;
2303
2304         if (yield_on_hlt)
2305                 min |= CPU_BASED_HLT_EXITING;
2306
2307         opt = CPU_BASED_TPR_SHADOW |
2308               CPU_BASED_USE_MSR_BITMAPS |
2309               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2310         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2311                                 &_cpu_based_exec_control) < 0)
2312                 return -EIO;
2313 #ifdef CONFIG_X86_64
2314         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2315                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2316                                            ~CPU_BASED_CR8_STORE_EXITING;
2317 #endif
2318         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2319                 min2 = 0;
2320                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2321                         SECONDARY_EXEC_WBINVD_EXITING |
2322                         SECONDARY_EXEC_ENABLE_VPID |
2323                         SECONDARY_EXEC_ENABLE_EPT |
2324                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2325                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2326                         SECONDARY_EXEC_RDTSCP;
2327                 if (adjust_vmx_controls(min2, opt2,
2328                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2329                                         &_cpu_based_2nd_exec_control) < 0)
2330                         return -EIO;
2331         }
2332 #ifndef CONFIG_X86_64
2333         if (!(_cpu_based_2nd_exec_control &
2334                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2335                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2336 #endif
2337         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2338                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2339                    enabled */
2340                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2341                                              CPU_BASED_CR3_STORE_EXITING |
2342                                              CPU_BASED_INVLPG_EXITING);
2343                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2344                       vmx_capability.ept, vmx_capability.vpid);
2345         }
2346
2347         min = 0;
2348 #ifdef CONFIG_X86_64
2349         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2350 #endif
2351         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2352         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2353                                 &_vmexit_control) < 0)
2354                 return -EIO;
2355
2356         min = 0;
2357         opt = VM_ENTRY_LOAD_IA32_PAT;
2358         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2359                                 &_vmentry_control) < 0)
2360                 return -EIO;
2361
2362         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2363
2364         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2365         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2366                 return -EIO;
2367
2368 #ifdef CONFIG_X86_64
2369         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2370         if (vmx_msr_high & (1u<<16))
2371                 return -EIO;
2372 #endif
2373
2374         /* Require Write-Back (WB) memory type for VMCS accesses. */
2375         if (((vmx_msr_high >> 18) & 15) != 6)
2376                 return -EIO;
2377
2378         vmcs_conf->size = vmx_msr_high & 0x1fff;
2379         vmcs_conf->order = get_order(vmcs_config.size);
2380         vmcs_conf->revision_id = vmx_msr_low;
2381
2382         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2383         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2384         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2385         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2386         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2387
2388         cpu_has_load_ia32_efer =
2389                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2390                                 VM_ENTRY_LOAD_IA32_EFER)
2391                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2392                                    VM_EXIT_LOAD_IA32_EFER);
2393
2394         return 0;
2395 }
2396
2397 static struct vmcs *alloc_vmcs_cpu(int cpu)
2398 {
2399         int node = cpu_to_node(cpu);
2400         struct page *pages;
2401         struct vmcs *vmcs;
2402
2403         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2404         if (!pages)
2405                 return NULL;
2406         vmcs = page_address(pages);
2407         memset(vmcs, 0, vmcs_config.size);
2408         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2409         return vmcs;
2410 }
2411
2412 static struct vmcs *alloc_vmcs(void)
2413 {
2414         return alloc_vmcs_cpu(raw_smp_processor_id());
2415 }
2416
2417 static void free_vmcs(struct vmcs *vmcs)
2418 {
2419         free_pages((unsigned long)vmcs, vmcs_config.order);
2420 }
2421
2422 /*
2423  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2424  */
2425 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2426 {
2427         if (!loaded_vmcs->vmcs)
2428                 return;
2429         loaded_vmcs_clear(loaded_vmcs);
2430         free_vmcs(loaded_vmcs->vmcs);
2431         loaded_vmcs->vmcs = NULL;
2432 }
2433
2434 static void free_kvm_area(void)
2435 {
2436         int cpu;
2437
2438         for_each_possible_cpu(cpu) {
2439                 free_vmcs(per_cpu(vmxarea, cpu));
2440                 per_cpu(vmxarea, cpu) = NULL;
2441         }
2442 }
2443
2444 static __init int alloc_kvm_area(void)
2445 {
2446         int cpu;
2447
2448         for_each_possible_cpu(cpu) {
2449                 struct vmcs *vmcs;
2450
2451                 vmcs = alloc_vmcs_cpu(cpu);
2452                 if (!vmcs) {
2453                         free_kvm_area();
2454                         return -ENOMEM;
2455                 }
2456
2457                 per_cpu(vmxarea, cpu) = vmcs;
2458         }
2459         return 0;
2460 }
2461
2462 static __init int hardware_setup(void)
2463 {
2464         if (setup_vmcs_config(&vmcs_config) < 0)
2465                 return -EIO;
2466
2467         if (boot_cpu_has(X86_FEATURE_NX))
2468                 kvm_enable_efer_bits(EFER_NX);
2469
2470         if (!cpu_has_vmx_vpid())
2471                 enable_vpid = 0;
2472
2473         if (!cpu_has_vmx_ept() ||
2474             !cpu_has_vmx_ept_4levels()) {
2475                 enable_ept = 0;
2476                 enable_unrestricted_guest = 0;
2477         }
2478
2479         if (!cpu_has_vmx_unrestricted_guest())
2480                 enable_unrestricted_guest = 0;
2481
2482         if (!cpu_has_vmx_flexpriority())
2483                 flexpriority_enabled = 0;
2484
2485         if (!cpu_has_vmx_tpr_shadow())
2486                 kvm_x86_ops->update_cr8_intercept = NULL;
2487
2488         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2489                 kvm_disable_largepages();
2490
2491         if (!cpu_has_vmx_ple())
2492                 ple_gap = 0;
2493
2494         if (nested)
2495                 nested_vmx_setup_ctls_msrs();
2496
2497         return alloc_kvm_area();
2498 }
2499
2500 static __exit void hardware_unsetup(void)
2501 {
2502         free_kvm_area();
2503 }
2504
2505 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2506 {
2507         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2508
2509         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
2510                 vmcs_write16(sf->selector, save->selector);
2511                 vmcs_writel(sf->base, save->base);
2512                 vmcs_write32(sf->limit, save->limit);
2513                 vmcs_write32(sf->ar_bytes, save->ar);
2514         } else {
2515                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2516                         << AR_DPL_SHIFT;
2517                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2518         }
2519 }
2520
2521 static void enter_pmode(struct kvm_vcpu *vcpu)
2522 {
2523         unsigned long flags;
2524         struct vcpu_vmx *vmx = to_vmx(vcpu);
2525
2526         vmx->emulation_required = 1;
2527         vmx->rmode.vm86_active = 0;
2528
2529         vmx_segment_cache_clear(vmx);
2530
2531         vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
2532         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2533         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2534         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
2535
2536         flags = vmcs_readl(GUEST_RFLAGS);
2537         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2538         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2539         vmcs_writel(GUEST_RFLAGS, flags);
2540
2541         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2542                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2543
2544         update_exception_bitmap(vcpu);
2545
2546         if (emulate_invalid_guest_state)
2547                 return;
2548
2549         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2550         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2551         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2552         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
2553
2554         vmx_segment_cache_clear(vmx);
2555
2556         vmcs_write16(GUEST_SS_SELECTOR, 0);
2557         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2558
2559         vmcs_write16(GUEST_CS_SELECTOR,
2560                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2561         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2562 }
2563
2564 static gva_t rmode_tss_base(struct kvm *kvm)
2565 {
2566         if (!kvm->arch.tss_addr) {
2567                 struct kvm_memslots *slots;
2568                 gfn_t base_gfn;
2569
2570                 slots = kvm_memslots(kvm);
2571                 base_gfn = slots->memslots[0].base_gfn +
2572                                  kvm->memslots->memslots[0].npages - 3;
2573                 return base_gfn << PAGE_SHIFT;
2574         }
2575         return kvm->arch.tss_addr;
2576 }
2577
2578 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2579 {
2580         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2581
2582         save->selector = vmcs_read16(sf->selector);
2583         save->base = vmcs_readl(sf->base);
2584         save->limit = vmcs_read32(sf->limit);
2585         save->ar = vmcs_read32(sf->ar_bytes);
2586         vmcs_write16(sf->selector, save->base >> 4);
2587         vmcs_write32(sf->base, save->base & 0xffff0);
2588         vmcs_write32(sf->limit, 0xffff);
2589         vmcs_write32(sf->ar_bytes, 0xf3);
2590         if (save->base & 0xf)
2591                 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2592                             " aligned when entering protected mode (seg=%d)",
2593                             seg);
2594 }
2595
2596 static void enter_rmode(struct kvm_vcpu *vcpu)
2597 {
2598         unsigned long flags;
2599         struct vcpu_vmx *vmx = to_vmx(vcpu);
2600
2601         if (enable_unrestricted_guest)
2602                 return;
2603
2604         vmx->emulation_required = 1;
2605         vmx->rmode.vm86_active = 1;
2606
2607         /*
2608          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2609          * vcpu. Call it here with phys address pointing 16M below 4G.
2610          */
2611         if (!vcpu->kvm->arch.tss_addr) {
2612                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2613                              "called before entering vcpu\n");
2614                 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2615                 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2616                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2617         }
2618
2619         vmx_segment_cache_clear(vmx);
2620
2621         vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
2622         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
2623         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2624
2625         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
2626         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2627
2628         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
2629         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2630
2631         flags = vmcs_readl(GUEST_RFLAGS);
2632         vmx->rmode.save_rflags = flags;
2633
2634         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2635
2636         vmcs_writel(GUEST_RFLAGS, flags);
2637         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2638         update_exception_bitmap(vcpu);
2639
2640         if (emulate_invalid_guest_state)
2641                 goto continue_rmode;
2642
2643         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
2644         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
2645         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
2646
2647         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
2648         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
2649         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
2650                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
2651         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
2652
2653         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
2654         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
2655         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
2656         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
2657
2658 continue_rmode:
2659         kvm_mmu_reset_context(vcpu);
2660 }
2661
2662 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2663 {
2664         struct vcpu_vmx *vmx = to_vmx(vcpu);
2665         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2666
2667         if (!msr)
2668                 return;
2669
2670         /*
2671          * Force kernel_gs_base reloading before EFER changes, as control
2672          * of this msr depends on is_long_mode().
2673          */
2674         vmx_load_host_state(to_vmx(vcpu));
2675         vcpu->arch.efer = efer;
2676         if (efer & EFER_LMA) {
2677                 vmcs_write32(VM_ENTRY_CONTROLS,
2678                              vmcs_read32(VM_ENTRY_CONTROLS) |
2679                              VM_ENTRY_IA32E_MODE);
2680                 msr->data = efer;
2681         } else {
2682                 vmcs_write32(VM_ENTRY_CONTROLS,
2683                              vmcs_read32(VM_ENTRY_CONTROLS) &
2684                              ~VM_ENTRY_IA32E_MODE);
2685
2686                 msr->data = efer & ~EFER_LME;
2687         }
2688         setup_msrs(vmx);
2689 }
2690
2691 #ifdef CONFIG_X86_64
2692
2693 static void enter_lmode(struct kvm_vcpu *vcpu)
2694 {
2695         u32 guest_tr_ar;
2696
2697         vmx_segment_cache_clear(to_vmx(vcpu));
2698
2699         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2700         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2701                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
2702                        __func__);
2703                 vmcs_write32(GUEST_TR_AR_BYTES,
2704                              (guest_tr_ar & ~AR_TYPE_MASK)
2705                              | AR_TYPE_BUSY_64_TSS);
2706         }
2707         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2708 }
2709
2710 static void exit_lmode(struct kvm_vcpu *vcpu)
2711 {
2712         vmcs_write32(VM_ENTRY_CONTROLS,
2713                      vmcs_read32(VM_ENTRY_CONTROLS)
2714                      & ~VM_ENTRY_IA32E_MODE);
2715         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2716 }
2717
2718 #endif
2719
2720 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2721 {
2722         vpid_sync_context(to_vmx(vcpu));
2723         if (enable_ept) {
2724                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2725                         return;
2726                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2727         }
2728 }
2729
2730 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2731 {
2732         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2733
2734         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2735         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2736 }
2737
2738 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2739 {
2740         if (enable_ept && is_paging(vcpu))
2741                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2742         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2743 }
2744
2745 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2746 {
2747         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2748
2749         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2750         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2751 }
2752
2753 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2754 {
2755         if (!test_bit(VCPU_EXREG_PDPTR,
2756                       (unsigned long *)&vcpu->arch.regs_dirty))
2757                 return;
2758
2759         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2760                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2761                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2762                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2763                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
2764         }
2765 }
2766
2767 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2768 {
2769         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2770                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2771                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2772                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2773                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2774         }
2775
2776         __set_bit(VCPU_EXREG_PDPTR,
2777                   (unsigned long *)&vcpu->arch.regs_avail);
2778         __set_bit(VCPU_EXREG_PDPTR,
2779                   (unsigned long *)&vcpu->arch.regs_dirty);
2780 }
2781
2782 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2783
2784 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2785                                         unsigned long cr0,
2786                                         struct kvm_vcpu *vcpu)
2787 {
2788         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2789                 vmx_decache_cr3(vcpu);
2790         if (!(cr0 & X86_CR0_PG)) {
2791                 /* From paging/starting to nonpaging */
2792                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2793                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
2794                              (CPU_BASED_CR3_LOAD_EXITING |
2795                               CPU_BASED_CR3_STORE_EXITING));
2796                 vcpu->arch.cr0 = cr0;
2797                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2798         } else if (!is_paging(vcpu)) {
2799                 /* From nonpaging to paging */
2800                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2801                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
2802                              ~(CPU_BASED_CR3_LOAD_EXITING |
2803                                CPU_BASED_CR3_STORE_EXITING));
2804                 vcpu->arch.cr0 = cr0;
2805                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2806         }
2807
2808         if (!(cr0 & X86_CR0_WP))
2809                 *hw_cr0 &= ~X86_CR0_WP;
2810 }
2811
2812 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2813 {
2814         struct vcpu_vmx *vmx = to_vmx(vcpu);
2815         unsigned long hw_cr0;
2816
2817         if (enable_unrestricted_guest)
2818                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2819                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2820         else
2821                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
2822
2823         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2824                 enter_pmode(vcpu);
2825
2826         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2827                 enter_rmode(vcpu);
2828
2829 #ifdef CONFIG_X86_64
2830         if (vcpu->arch.efer & EFER_LME) {
2831                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2832                         enter_lmode(vcpu);
2833                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2834                         exit_lmode(vcpu);
2835         }
2836 #endif
2837
2838         if (enable_ept)
2839                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2840
2841         if (!vcpu->fpu_active)
2842                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
2843
2844         vmcs_writel(CR0_READ_SHADOW, cr0);
2845         vmcs_writel(GUEST_CR0, hw_cr0);
2846         vcpu->arch.cr0 = cr0;
2847         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2848 }
2849
2850 static u64 construct_eptp(unsigned long root_hpa)
2851 {
2852         u64 eptp;
2853
2854         /* TODO write the value reading from MSR */
2855         eptp = VMX_EPT_DEFAULT_MT |
2856                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
2857         eptp |= (root_hpa & PAGE_MASK);
2858
2859         return eptp;
2860 }
2861
2862 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2863 {
2864         unsigned long guest_cr3;
2865         u64 eptp;
2866
2867         guest_cr3 = cr3;
2868         if (enable_ept) {
2869                 eptp = construct_eptp(cr3);
2870                 vmcs_write64(EPT_POINTER, eptp);
2871                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
2872                         vcpu->kvm->arch.ept_identity_map_addr;
2873                 ept_load_pdptrs(vcpu);
2874         }
2875
2876         vmx_flush_tlb(vcpu);
2877         vmcs_writel(GUEST_CR3, guest_cr3);
2878 }
2879
2880 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2881 {
2882         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
2883                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
2884
2885         if (cr4 & X86_CR4_VMXE) {
2886                 /*
2887                  * To use VMXON (and later other VMX instructions), a guest
2888                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
2889                  * So basically the check on whether to allow nested VMX
2890                  * is here.
2891                  */
2892                 if (!nested_vmx_allowed(vcpu))
2893                         return 1;
2894         } else if (to_vmx(vcpu)->nested.vmxon)
2895                 return 1;
2896
2897         vcpu->arch.cr4 = cr4;
2898         if (enable_ept) {
2899                 if (!is_paging(vcpu)) {
2900                         hw_cr4 &= ~X86_CR4_PAE;
2901                         hw_cr4 |= X86_CR4_PSE;
2902                 } else if (!(cr4 & X86_CR4_PAE)) {
2903                         hw_cr4 &= ~X86_CR4_PAE;
2904                 }
2905         }
2906
2907         vmcs_writel(CR4_READ_SHADOW, cr4);
2908         vmcs_writel(GUEST_CR4, hw_cr4);
2909         return 0;
2910 }
2911
2912 static void vmx_get_segment(struct kvm_vcpu *vcpu,
2913                             struct kvm_segment *var, int seg)
2914 {
2915         struct vcpu_vmx *vmx = to_vmx(vcpu);
2916         struct kvm_save_segment *save;
2917         u32 ar;
2918
2919         if (vmx->rmode.vm86_active
2920             && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
2921                 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
2922                 || seg == VCPU_SREG_GS)
2923             && !emulate_invalid_guest_state) {
2924                 switch (seg) {
2925                 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
2926                 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
2927                 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
2928                 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
2929                 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
2930                 default: BUG();
2931                 }
2932                 var->selector = save->selector;
2933                 var->base = save->base;
2934                 var->limit = save->limit;
2935                 ar = save->ar;
2936                 if (seg == VCPU_SREG_TR
2937                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
2938                         goto use_saved_rmode_seg;
2939         }
2940         var->base = vmx_read_guest_seg_base(vmx, seg);
2941         var->limit = vmx_read_guest_seg_limit(vmx, seg);
2942         var->selector = vmx_read_guest_seg_selector(vmx, seg);
2943         ar = vmx_read_guest_seg_ar(vmx, seg);
2944 use_saved_rmode_seg:
2945         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
2946                 ar = 0;
2947         var->type = ar & 15;
2948         var->s = (ar >> 4) & 1;
2949         var->dpl = (ar >> 5) & 3;
2950         var->present = (ar >> 7) & 1;
2951         var->avl = (ar >> 12) & 1;
2952         var->l = (ar >> 13) & 1;
2953         var->db = (ar >> 14) & 1;
2954         var->g = (ar >> 15) & 1;
2955         var->unusable = (ar >> 16) & 1;
2956 }
2957
2958 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2959 {
2960         struct kvm_segment s;
2961
2962         if (to_vmx(vcpu)->rmode.vm86_active) {
2963                 vmx_get_segment(vcpu, &s, seg);
2964                 return s.base;
2965         }
2966         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
2967 }
2968
2969 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
2970 {
2971         if (!is_protmode(vcpu))
2972                 return 0;
2973
2974         if (!is_long_mode(vcpu)
2975             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2976                 return 3;
2977
2978         return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
2979 }
2980
2981 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2982 {
2983         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
2984                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2985                 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
2986         }
2987         return to_vmx(vcpu)->cpl;
2988 }
2989
2990
2991 static u32 vmx_segment_access_rights(struct kvm_segment *var)
2992 {
2993         u32 ar;
2994
2995         if (var->unusable)
2996                 ar = 1 << 16;
2997         else {
2998                 ar = var->type & 15;
2999                 ar |= (var->s & 1) << 4;
3000                 ar |= (var->dpl & 3) << 5;
3001                 ar |= (var->present & 1) << 7;
3002                 ar |= (var->avl & 1) << 12;
3003                 ar |= (var->l & 1) << 13;
3004                 ar |= (var->db & 1) << 14;
3005                 ar |= (var->g & 1) << 15;
3006         }
3007         if (ar == 0) /* a 0 value means unusable */
3008                 ar = AR_UNUSABLE_MASK;
3009
3010         return ar;
3011 }
3012
3013 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3014                             struct kvm_segment *var, int seg)
3015 {
3016         struct vcpu_vmx *vmx = to_vmx(vcpu);
3017         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3018         u32 ar;
3019
3020         vmx_segment_cache_clear(vmx);
3021
3022         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
3023                 vmcs_write16(sf->selector, var->selector);
3024                 vmx->rmode.tr.selector = var->selector;
3025                 vmx->rmode.tr.base = var->base;
3026                 vmx->rmode.tr.limit = var->limit;
3027                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
3028                 return;
3029         }
3030         vmcs_writel(sf->base, var->base);
3031         vmcs_write32(sf->limit, var->limit);
3032         vmcs_write16(sf->selector, var->selector);
3033         if (vmx->rmode.vm86_active && var->s) {
3034                 /*
3035                  * Hack real-mode segments into vm86 compatibility.
3036                  */
3037                 if (var->base == 0xffff0000 && var->selector == 0xf000)
3038                         vmcs_writel(sf->base, 0xf0000);
3039                 ar = 0xf3;
3040         } else
3041                 ar = vmx_segment_access_rights(var);
3042
3043         /*
3044          *   Fix the "Accessed" bit in AR field of segment registers for older
3045          * qemu binaries.
3046          *   IA32 arch specifies that at the time of processor reset the
3047          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3048          * is setting it to 0 in the usedland code. This causes invalid guest
3049          * state vmexit when "unrestricted guest" mode is turned on.
3050          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3051          * tree. Newer qemu binaries with that qemu fix would not need this
3052          * kvm hack.
3053          */
3054         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3055                 ar |= 0x1; /* Accessed */
3056
3057         vmcs_write32(sf->ar_bytes, ar);
3058         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3059 }
3060
3061 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3062 {
3063         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3064
3065         *db = (ar >> 14) & 1;
3066         *l = (ar >> 13) & 1;
3067 }
3068
3069 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3070 {
3071         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3072         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3073 }
3074
3075 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3076 {
3077         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3078         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3079 }
3080
3081 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3082 {
3083         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3084         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3085 }
3086
3087 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3088 {
3089         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3090         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3091 }
3092
3093 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3094 {
3095         struct kvm_segment var;
3096         u32 ar;
3097
3098         vmx_get_segment(vcpu, &var, seg);
3099         ar = vmx_segment_access_rights(&var);
3100
3101         if (var.base != (var.selector << 4))
3102                 return false;
3103         if (var.limit != 0xffff)
3104                 return false;
3105         if (ar != 0xf3)
3106                 return false;
3107
3108         return true;
3109 }
3110
3111 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3112 {
3113         struct kvm_segment cs;
3114         unsigned int cs_rpl;
3115
3116         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3117         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3118
3119         if (cs.unusable)
3120                 return false;
3121         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3122                 return false;
3123         if (!cs.s)
3124                 return false;
3125         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3126                 if (cs.dpl > cs_rpl)
3127                         return false;
3128         } else {
3129                 if (cs.dpl != cs_rpl)
3130                         return false;
3131         }
3132         if (!cs.present)
3133                 return false;
3134
3135         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3136         return true;
3137 }
3138
3139 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3140 {
3141         struct kvm_segment ss;
3142         unsigned int ss_rpl;
3143
3144         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3145         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3146
3147         if (ss.unusable)
3148                 return true;
3149         if (ss.type != 3 && ss.type != 7)
3150                 return false;
3151         if (!ss.s)
3152                 return false;
3153         if (ss.dpl != ss_rpl) /* DPL != RPL */
3154                 return false;
3155         if (!ss.present)
3156                 return false;
3157
3158         return true;
3159 }
3160
3161 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3162 {
3163         struct kvm_segment var;
3164         unsigned int rpl;
3165
3166         vmx_get_segment(vcpu, &var, seg);
3167         rpl = var.selector & SELECTOR_RPL_MASK;
3168
3169         if (var.unusable)
3170                 return true;
3171         if (!var.s)
3172                 return false;
3173         if (!var.present)
3174                 return false;
3175         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3176                 if (var.dpl < rpl) /* DPL < RPL */
3177                         return false;
3178         }
3179
3180         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3181          * rights flags
3182          */
3183         return true;
3184 }
3185
3186 static bool tr_valid(struct kvm_vcpu *vcpu)
3187 {
3188         struct kvm_segment tr;
3189
3190         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3191
3192         if (tr.unusable)
3193                 return false;
3194         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3195                 return false;
3196         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3197                 return false;
3198         if (!tr.present)
3199                 return false;
3200
3201         return true;
3202 }
3203
3204 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3205 {
3206         struct kvm_segment ldtr;
3207
3208         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3209
3210         if (ldtr.unusable)
3211                 return true;
3212         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3213                 return false;
3214         if (ldtr.type != 2)
3215                 return false;
3216         if (!ldtr.present)
3217                 return false;
3218
3219         return true;
3220 }
3221
3222 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3223 {
3224         struct kvm_segment cs, ss;
3225
3226         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3227         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3228
3229         return ((cs.selector & SELECTOR_RPL_MASK) ==
3230                  (ss.selector & SELECTOR_RPL_MASK));
3231 }
3232
3233 /*
3234  * Check if guest state is valid. Returns true if valid, false if
3235  * not.
3236  * We assume that registers are always usable
3237  */
3238 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3239 {
3240         /* real mode guest state checks */
3241         if (!is_protmode(vcpu)) {
3242                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3243                         return false;
3244                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3245                         return false;
3246                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3247                         return false;
3248                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3249                         return false;
3250                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3251                         return false;
3252                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3253                         return false;
3254         } else {
3255         /* protected mode guest state checks */
3256                 if (!cs_ss_rpl_check(vcpu))
3257                         return false;
3258                 if (!code_segment_valid(vcpu))
3259                         return false;
3260                 if (!stack_segment_valid(vcpu))
3261                         return false;
3262                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3263                         return false;
3264                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3265                         return false;
3266                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3267                         return false;
3268                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3269                         return false;
3270                 if (!tr_valid(vcpu))
3271                         return false;
3272                 if (!ldtr_valid(vcpu))
3273                         return false;
3274         }
3275         /* TODO:
3276          * - Add checks on RIP
3277          * - Add checks on RFLAGS
3278          */
3279
3280         return true;
3281 }
3282
3283 static int init_rmode_tss(struct kvm *kvm)
3284 {
3285         gfn_t fn;
3286         u16 data = 0;
3287         int r, idx, ret = 0;
3288
3289         idx = srcu_read_lock(&kvm->srcu);
3290         fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3291         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3292         if (r < 0)
3293                 goto out;
3294         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3295         r = kvm_write_guest_page(kvm, fn++, &data,
3296                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3297         if (r < 0)
3298                 goto out;
3299         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3300         if (r < 0)
3301                 goto out;
3302         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3303         if (r < 0)
3304                 goto out;
3305         data = ~0;
3306         r = kvm_write_guest_page(kvm, fn, &data,
3307                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3308                                  sizeof(u8));
3309         if (r < 0)
3310                 goto out;
3311
3312         ret = 1;
3313 out:
3314         srcu_read_unlock(&kvm->srcu, idx);
3315         return ret;
3316 }
3317
3318 static int init_rmode_identity_map(struct kvm *kvm)
3319 {
3320         int i, idx, r, ret;
3321         pfn_t identity_map_pfn;
3322         u32 tmp;
3323
3324         if (!enable_ept)
3325                 return 1;
3326         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3327                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3328                         "haven't been allocated!\n");
3329                 return 0;
3330         }
3331         if (likely(kvm->arch.ept_identity_pagetable_done))
3332                 return 1;
3333         ret = 0;
3334         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3335         idx = srcu_read_lock(&kvm->srcu);
3336         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3337         if (r < 0)
3338                 goto out;
3339         /* Set up identity-mapping pagetable for EPT in real mode */
3340         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3341                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3342                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3343                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3344                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3345                 if (r < 0)
3346                         goto out;
3347         }
3348         kvm->arch.ept_identity_pagetable_done = true;
3349         ret = 1;
3350 out:
3351         srcu_read_unlock(&kvm->srcu, idx);
3352         return ret;
3353 }
3354
3355 static void seg_setup(int seg)
3356 {
3357         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3358         unsigned int ar;
3359
3360         vmcs_write16(sf->selector, 0);
3361         vmcs_writel(sf->base, 0);
3362         vmcs_write32(sf->limit, 0xffff);
3363         if (enable_unrestricted_guest) {
3364                 ar = 0x93;
3365                 if (seg == VCPU_SREG_CS)
3366                         ar |= 0x08; /* code segment */
3367         } else
3368                 ar = 0xf3;
3369
3370         vmcs_write32(sf->ar_bytes, ar);
3371 }
3372
3373 static int alloc_apic_access_page(struct kvm *kvm)
3374 {
3375         struct kvm_userspace_memory_region kvm_userspace_mem;
3376         int r = 0;
3377
3378         mutex_lock(&kvm->slots_lock);
3379         if (kvm->arch.apic_access_page)
3380                 goto out;
3381         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3382         kvm_userspace_mem.flags = 0;
3383         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3384         kvm_userspace_mem.memory_size = PAGE_SIZE;
3385         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3386         if (r)
3387                 goto out;
3388
3389         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
3390 out:
3391         mutex_unlock(&kvm->slots_lock);
3392         return r;
3393 }
3394
3395 static int alloc_identity_pagetable(struct kvm *kvm)
3396 {
3397         struct kvm_userspace_memory_region kvm_userspace_mem;
3398         int r = 0;
3399
3400         mutex_lock(&kvm->slots_lock);
3401         if (kvm->arch.ept_identity_pagetable)
3402                 goto out;
3403         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3404         kvm_userspace_mem.flags = 0;
3405         kvm_userspace_mem.guest_phys_addr =
3406                 kvm->arch.ept_identity_map_addr;
3407         kvm_userspace_mem.memory_size = PAGE_SIZE;
3408         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3409         if (r)
3410                 goto out;
3411
3412         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
3413                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3414 out:
3415         mutex_unlock(&kvm->slots_lock);
3416         return r;
3417 }
3418
3419 static void allocate_vpid(struct vcpu_vmx *vmx)
3420 {
3421         int vpid;
3422
3423         vmx->vpid = 0;
3424         if (!enable_vpid)
3425                 return;
3426         spin_lock(&vmx_vpid_lock);
3427         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3428         if (vpid < VMX_NR_VPIDS) {
3429                 vmx->vpid = vpid;
3430                 __set_bit(vpid, vmx_vpid_bitmap);
3431         }
3432         spin_unlock(&vmx_vpid_lock);
3433 }
3434
3435 static void free_vpid(struct vcpu_vmx *vmx)
3436 {
3437         if (!enable_vpid)
3438                 return;
3439         spin_lock(&vmx_vpid_lock);
3440         if (vmx->vpid != 0)
3441                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3442         spin_unlock(&vmx_vpid_lock);
3443 }
3444
3445 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
3446 {
3447         int f = sizeof(unsigned long);
3448
3449         if (!cpu_has_vmx_msr_bitmap())
3450                 return;
3451
3452         /*
3453          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3454          * have the write-low and read-high bitmap offsets the wrong way round.
3455          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3456          */
3457         if (msr <= 0x1fff) {
3458                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3459                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
3460         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3461                 msr &= 0x1fff;
3462                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3463                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
3464         }
3465 }
3466
3467 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3468 {
3469         if (!longmode_only)
3470                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3471         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3472 }
3473
3474 /*
3475  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3476  * will not change in the lifetime of the guest.
3477  * Note that host-state that does change is set elsewhere. E.g., host-state
3478  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3479  */
3480 static void vmx_set_constant_host_state(void)
3481 {
3482         u32 low32, high32;
3483         unsigned long tmpl;
3484         struct desc_ptr dt;
3485
3486         vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS);  /* 22.2.3 */
3487         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
3488         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
3489
3490         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
3491         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3492         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3493         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3494         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
3495
3496         native_store_idt(&dt);
3497         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
3498
3499         asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3500         vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3501
3502         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3503         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3504         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3505         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
3506
3507         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3508                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3509                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3510         }
3511 }
3512
3513 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3514 {
3515         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3516         if (enable_ept)
3517                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3518         if (is_guest_mode(&vmx->vcpu))
3519                 vmx->vcpu.arch.cr4_guest_owned_bits &=
3520                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3521         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3522 }
3523
3524 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3525 {
3526         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3527         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3528                 exec_control &= ~CPU_BASED_TPR_SHADOW;
3529 #ifdef CONFIG_X86_64
3530                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3531                                 CPU_BASED_CR8_LOAD_EXITING;
3532 #endif
3533         }
3534         if (!enable_ept)
3535                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3536                                 CPU_BASED_CR3_LOAD_EXITING  |
3537                                 CPU_BASED_INVLPG_EXITING;
3538         return exec_control;
3539 }
3540
3541 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3542 {
3543         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3544         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3545                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3546         if (vmx->vpid == 0)
3547                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3548         if (!enable_ept) {
3549                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3550                 enable_unrestricted_guest = 0;
3551         }
3552         if (!enable_unrestricted_guest)
3553                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3554         if (!ple_gap)
3555                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3556         return exec_control;
3557 }
3558
3559 /*
3560  * Sets up the vmcs for emulated real mode.
3561  */
3562 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
3563 {
3564         unsigned long a;
3565         int i;
3566
3567         /* I/O */
3568         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3569         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
3570
3571         if (cpu_has_vmx_msr_bitmap())
3572                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
3573
3574         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3575
3576         /* Control */
3577         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3578                 vmcs_config.pin_based_exec_ctrl);
3579
3580         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
3581
3582         if (cpu_has_secondary_exec_ctrls()) {
3583                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3584                                 vmx_secondary_exec_control(vmx));
3585         }
3586
3587         if (ple_gap) {
3588                 vmcs_write32(PLE_GAP, ple_gap);
3589                 vmcs_write32(PLE_WINDOW, ple_window);
3590         }
3591
3592         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
3593         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
3594         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
3595
3596         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
3597         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
3598         vmx_set_constant_host_state();
3599 #ifdef CONFIG_X86_64
3600         rdmsrl(MSR_FS_BASE, a);
3601         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3602         rdmsrl(MSR_GS_BASE, a);
3603         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3604 #else
3605         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3606         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3607 #endif
3608
3609         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3610         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
3611         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
3612         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
3613         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
3614
3615         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3616                 u32 msr_low, msr_high;
3617                 u64 host_pat;
3618                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3619                 host_pat = msr_low | ((u64) msr_high << 32);
3620                 /* Write the default value follow host pat */
3621                 vmcs_write64(GUEST_IA32_PAT, host_pat);
3622                 /* Keep arch.pat sync with GUEST_IA32_PAT */
3623                 vmx->vcpu.arch.pat = host_pat;
3624         }
3625
3626         for (i = 0; i < NR_VMX_MSR; ++i) {
3627                 u32 index = vmx_msr_index[i];
3628                 u32 data_low, data_high;
3629                 int j = vmx->nmsrs;
3630
3631                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3632                         continue;
3633                 if (wrmsr_safe(index, data_low, data_high) < 0)
3634                         continue;
3635                 vmx->guest_msrs[j].index = i;
3636                 vmx->guest_msrs[j].data = 0;
3637                 vmx->guest_msrs[j].mask = -1ull;
3638                 ++vmx->nmsrs;
3639         }
3640
3641         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
3642
3643         /* 22.2.1, 20.8.1 */
3644         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3645
3646         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
3647         set_cr4_guest_host_mask(vmx);
3648
3649         kvm_write_tsc(&vmx->vcpu, 0);
3650
3651         return 0;
3652 }
3653
3654 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3655 {
3656         struct vcpu_vmx *vmx = to_vmx(vcpu);
3657         u64 msr;
3658         int ret;
3659
3660         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3661
3662         vmx->rmode.vm86_active = 0;
3663
3664         vmx->soft_vnmi_blocked = 0;
3665
3666         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
3667         kvm_set_cr8(&vmx->vcpu, 0);
3668         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
3669         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3670                 msr |= MSR_IA32_APICBASE_BSP;
3671         kvm_set_apic_base(&vmx->vcpu, msr);
3672
3673         ret = fx_init(&vmx->vcpu);
3674         if (ret != 0)
3675                 goto out;
3676
3677         vmx_segment_cache_clear(vmx);
3678
3679         seg_setup(VCPU_SREG_CS);
3680         /*
3681          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3682          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
3683          */
3684         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
3685                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3686                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3687         } else {
3688                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3689                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
3690         }
3691
3692         seg_setup(VCPU_SREG_DS);
3693         seg_setup(VCPU_SREG_ES);
3694         seg_setup(VCPU_SREG_FS);
3695         seg_setup(VCPU_SREG_GS);
3696         seg_setup(VCPU_SREG_SS);
3697
3698         vmcs_write16(GUEST_TR_SELECTOR, 0);
3699         vmcs_writel(GUEST_TR_BASE, 0);
3700         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3701         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3702
3703         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3704         vmcs_writel(GUEST_LDTR_BASE, 0);
3705         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3706         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3707
3708         vmcs_write32(GUEST_SYSENTER_CS, 0);
3709         vmcs_writel(GUEST_SYSENTER_ESP, 0);
3710         vmcs_writel(GUEST_SYSENTER_EIP, 0);
3711
3712         vmcs_writel(GUEST_RFLAGS, 0x02);
3713         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3714                 kvm_rip_write(vcpu, 0xfff0);
3715         else
3716                 kvm_rip_write(vcpu, 0);
3717         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
3718
3719         vmcs_writel(GUEST_DR7, 0x400);
3720
3721         vmcs_writel(GUEST_GDTR_BASE, 0);
3722         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3723
3724         vmcs_writel(GUEST_IDTR_BASE, 0);
3725         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3726
3727         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3728         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3729         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3730
3731         /* Special registers */
3732         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3733
3734         setup_msrs(vmx);
3735
3736         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
3737
3738         if (cpu_has_vmx_tpr_shadow()) {
3739                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3740                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3741                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
3742                                      __pa(vmx->vcpu.arch.apic->regs));
3743                 vmcs_write32(TPR_THRESHOLD, 0);
3744         }
3745
3746         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3747                 vmcs_write64(APIC_ACCESS_ADDR,
3748                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
3749
3750         if (vmx->vpid != 0)
3751                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3752
3753         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
3754         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
3755         vmx_set_cr4(&vmx->vcpu, 0);
3756         vmx_set_efer(&vmx->vcpu, 0);
3757         vmx_fpu_activate(&vmx->vcpu);
3758         update_exception_bitmap(&vmx->vcpu);
3759
3760         vpid_sync_context(vmx);
3761
3762         ret = 0;
3763
3764         /* HACK: Don't enable emulation on guest boot/reset */
3765         vmx->emulation_required = 0;
3766
3767 out:
3768         return ret;
3769 }
3770
3771 /*
3772  * In nested virtualization, check if L1 asked to exit on external interrupts.
3773  * For most existing hypervisors, this will always return true.
3774  */
3775 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
3776 {
3777         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
3778                 PIN_BASED_EXT_INTR_MASK;
3779 }
3780
3781 static void enable_irq_window(struct kvm_vcpu *vcpu)
3782 {
3783         u32 cpu_based_vm_exec_control;
3784         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
3785                 /* We can get here when nested_run_pending caused
3786                  * vmx_interrupt_allowed() to return false. In this case, do
3787                  * nothing - the interrupt will be injected later.
3788                  */
3789                 return;
3790
3791         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3792         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
3793         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3794 }
3795
3796 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3797 {
3798         u32 cpu_based_vm_exec_control;
3799
3800         if (!cpu_has_virtual_nmis()) {
3801                 enable_irq_window(vcpu);
3802                 return;
3803         }
3804
3805         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
3806                 enable_irq_window(vcpu);
3807                 return;
3808         }
3809         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3810         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
3811         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3812 }
3813
3814 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
3815 {
3816         struct vcpu_vmx *vmx = to_vmx(vcpu);
3817         uint32_t intr;
3818         int irq = vcpu->arch.interrupt.nr;
3819
3820         trace_kvm_inj_virq(irq);
3821
3822         ++vcpu->stat.irq_injections;
3823         if (vmx->rmode.vm86_active) {
3824                 int inc_eip = 0;
3825                 if (vcpu->arch.interrupt.soft)
3826                         inc_eip = vcpu->arch.event_exit_inst_len;
3827                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
3828                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3829                 return;
3830         }
3831         intr = irq | INTR_INFO_VALID_MASK;
3832         if (vcpu->arch.interrupt.soft) {
3833                 intr |= INTR_TYPE_SOFT_INTR;
3834                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3835                              vmx->vcpu.arch.event_exit_inst_len);
3836         } else
3837                 intr |= INTR_TYPE_EXT_INTR;
3838         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
3839         vmx_clear_hlt(vcpu);
3840 }
3841
3842 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
3843 {
3844         struct vcpu_vmx *vmx = to_vmx(vcpu);
3845
3846         if (is_guest_mode(vcpu))
3847                 return;
3848
3849         if (!cpu_has_virtual_nmis()) {
3850                 /*
3851                  * Tracking the NMI-blocked state in software is built upon
3852                  * finding the next open IRQ window. This, in turn, depends on
3853                  * well-behaving guests: They have to keep IRQs disabled at
3854                  * least as long as the NMI handler runs. Otherwise we may
3855                  * cause NMI nesting, maybe breaking the guest. But as this is
3856                  * highly unlikely, we can live with the residual risk.
3857                  */
3858                 vmx->soft_vnmi_blocked = 1;
3859                 vmx->vnmi_blocked_time = 0;
3860         }
3861
3862         ++vcpu->stat.nmi_injections;
3863         vmx->nmi_known_unmasked = false;
3864         if (vmx->rmode.vm86_active) {
3865                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
3866                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3867                 return;
3868         }
3869         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
3870                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
3871         vmx_clear_hlt(vcpu);
3872 }
3873
3874 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
3875 {
3876         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
3877                 return 0;
3878
3879         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3880                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
3881                    | GUEST_INTR_STATE_NMI));
3882 }
3883
3884 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
3885 {
3886         if (!cpu_has_virtual_nmis())
3887                 return to_vmx(vcpu)->soft_vnmi_blocked;
3888         if (to_vmx(vcpu)->nmi_known_unmasked)
3889                 return false;
3890         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3891 }
3892
3893 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3894 {
3895         struct vcpu_vmx *vmx = to_vmx(vcpu);
3896
3897         if (!cpu_has_virtual_nmis()) {
3898                 if (vmx->soft_vnmi_blocked != masked) {
3899                         vmx->soft_vnmi_blocked = masked;
3900                         vmx->vnmi_blocked_time = 0;
3901                 }
3902         } else {
3903                 vmx->nmi_known_unmasked = !masked;
3904                 if (masked)
3905                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3906                                       GUEST_INTR_STATE_NMI);
3907                 else
3908                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3909                                         GUEST_INTR_STATE_NMI);
3910         }
3911 }
3912
3913 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
3914 {
3915         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
3916                 struct vmcs12 *vmcs12;
3917                 if (to_vmx(vcpu)->nested.nested_run_pending)
3918                         return 0;
3919                 nested_vmx_vmexit(vcpu);
3920                 vmcs12 = get_vmcs12(vcpu);
3921                 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
3922                 vmcs12->vm_exit_intr_info = 0;
3923                 /* fall through to normal code, but now in L1, not L2 */
3924         }
3925
3926         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
3927                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3928                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
3929 }
3930
3931 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
3932 {
3933         int ret;
3934         struct kvm_userspace_memory_region tss_mem = {
3935                 .slot = TSS_PRIVATE_MEMSLOT,
3936                 .guest_phys_addr = addr,
3937                 .memory_size = PAGE_SIZE * 3,
3938                 .flags = 0,
3939         };
3940
3941         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
3942         if (ret)
3943                 return ret;
3944         kvm->arch.tss_addr = addr;
3945         if (!init_rmode_tss(kvm))
3946                 return  -ENOMEM;
3947
3948         return 0;
3949 }
3950
3951 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
3952                                   int vec, u32 err_code)
3953 {
3954         /*
3955          * Instruction with address size override prefix opcode 0x67
3956          * Cause the #SS fault with 0 error code in VM86 mode.
3957          */
3958         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
3959                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
3960                         return 1;
3961         /*
3962          * Forward all other exceptions that are valid in real mode.
3963          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
3964          *        the required debugging infrastructure rework.
3965          */
3966         switch (vec) {
3967         case DB_VECTOR:
3968                 if (vcpu->guest_debug &
3969                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
3970                         return 0;
3971                 kvm_queue_exception(vcpu, vec);
3972                 return 1;
3973         case BP_VECTOR:
3974                 /*
3975                  * Update instruction length as we may reinject the exception
3976                  * from user space while in guest debugging mode.
3977                  */
3978                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
3979                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3980                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
3981                         return 0;
3982                 /* fall through */
3983         case DE_VECTOR:
3984         case OF_VECTOR:
3985         case BR_VECTOR:
3986         case UD_VECTOR:
3987         case DF_VECTOR:
3988         case SS_VECTOR:
3989         case GP_VECTOR:
3990         case MF_VECTOR:
3991                 kvm_queue_exception(vcpu, vec);
3992                 return 1;
3993         }
3994         return 0;
3995 }
3996
3997 /*
3998  * Trigger machine check on the host. We assume all the MSRs are already set up
3999  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4000  * We pass a fake environment to the machine check handler because we want
4001  * the guest to be always treated like user space, no matter what context
4002  * it used internally.
4003  */
4004 static void kvm_machine_check(void)
4005 {
4006 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4007         struct pt_regs regs = {
4008                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4009                 .flags = X86_EFLAGS_IF,
4010         };
4011
4012         do_machine_check(&regs, 0);
4013 #endif
4014 }
4015
4016 static int handle_machine_check(struct kvm_vcpu *vcpu)
4017 {
4018         /* already handled by vcpu_run */
4019         return 1;
4020 }
4021
4022 static int handle_exception(struct kvm_vcpu *vcpu)
4023 {
4024         struct vcpu_vmx *vmx = to_vmx(vcpu);
4025         struct kvm_run *kvm_run = vcpu->run;
4026         u32 intr_info, ex_no, error_code;
4027         unsigned long cr2, rip, dr6;
4028         u32 vect_info;
4029         enum emulation_result er;
4030
4031         vect_info = vmx->idt_vectoring_info;
4032         intr_info = vmx->exit_intr_info;
4033
4034         if (is_machine_check(intr_info))
4035                 return handle_machine_check(vcpu);
4036
4037         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4038             !is_page_fault(intr_info)) {
4039                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4040                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4041                 vcpu->run->internal.ndata = 2;
4042                 vcpu->run->internal.data[0] = vect_info;
4043                 vcpu->run->internal.data[1] = intr_info;
4044                 return 0;
4045         }
4046
4047         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4048                 return 1;  /* already handled by vmx_vcpu_run() */
4049
4050         if (is_no_device(intr_info)) {
4051                 vmx_fpu_activate(vcpu);
4052                 return 1;
4053         }
4054
4055         if (is_invalid_opcode(intr_info)) {
4056                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4057                 if (er != EMULATE_DONE)
4058                         kvm_queue_exception(vcpu, UD_VECTOR);
4059                 return 1;
4060         }
4061
4062         error_code = 0;
4063         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4064                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4065         if (is_page_fault(intr_info)) {
4066                 /* EPT won't cause page fault directly */
4067                 if (enable_ept)
4068                         BUG();
4069                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4070                 trace_kvm_page_fault(cr2, error_code);
4071
4072                 if (kvm_event_needs_reinjection(vcpu))
4073                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4074                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4075         }
4076
4077         if (vmx->rmode.vm86_active &&
4078             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
4079                                                                 error_code)) {
4080                 if (vcpu->arch.halt_request) {
4081                         vcpu->arch.halt_request = 0;
4082                         return kvm_emulate_halt(vcpu);
4083                 }
4084                 return 1;
4085         }
4086
4087         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4088         switch (ex_no) {
4089         case DB_VECTOR:
4090                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4091                 if (!(vcpu->guest_debug &
4092                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4093                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4094                         kvm_queue_exception(vcpu, DB_VECTOR);
4095                         return 1;
4096                 }
4097                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4098                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4099                 /* fall through */
4100         case BP_VECTOR:
4101                 /*
4102                  * Update instruction length as we may reinject #BP from
4103                  * user space while in guest debugging mode. Reading it for
4104                  * #DB as well causes no harm, it is not used in that case.
4105                  */
4106                 vmx->vcpu.arch.event_exit_inst_len =
4107                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4108                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4109                 rip = kvm_rip_read(vcpu);
4110                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4111                 kvm_run->debug.arch.exception = ex_no;
4112                 break;
4113         default:
4114                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4115                 kvm_run->ex.exception = ex_no;
4116                 kvm_run->ex.error_code = error_code;
4117                 break;
4118         }
4119         return 0;
4120 }
4121
4122 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4123 {
4124         ++vcpu->stat.irq_exits;
4125         return 1;
4126 }
4127
4128 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4129 {
4130         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4131         return 0;
4132 }
4133
4134 static int handle_io(struct kvm_vcpu *vcpu)
4135 {
4136         unsigned long exit_qualification;
4137         int size, in, string;
4138         unsigned port;
4139
4140         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4141         string = (exit_qualification & 16) != 0;
4142         in = (exit_qualification & 8) != 0;
4143
4144         ++vcpu->stat.io_exits;
4145
4146         if (string || in)
4147                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4148
4149         port = exit_qualification >> 16;
4150         size = (exit_qualification & 7) + 1;
4151         skip_emulated_instruction(vcpu);
4152
4153         return kvm_fast_pio_out(vcpu, size, port);
4154 }
4155
4156 static void
4157 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4158 {
4159         /*
4160          * Patch in the VMCALL instruction:
4161          */
4162         hypercall[0] = 0x0f;
4163         hypercall[1] = 0x01;
4164         hypercall[2] = 0xc1;
4165 }
4166
4167 static int handle_cr(struct kvm_vcpu *vcpu)
4168 {
4169         unsigned long exit_qualification, val;
4170         int cr;
4171         int reg;
4172         int err;
4173
4174         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4175         cr = exit_qualification & 15;
4176         reg = (exit_qualification >> 8) & 15;
4177         switch ((exit_qualification >> 4) & 3) {
4178         case 0: /* mov to cr */
4179                 val = kvm_register_read(vcpu, reg);
4180                 trace_kvm_cr_write(cr, val);
4181                 switch (cr) {
4182                 case 0:
4183                         err = kvm_set_cr0(vcpu, val);
4184                         kvm_complete_insn_gp(vcpu, err);
4185                         return 1;
4186                 case 3:
4187                         err = kvm_set_cr3(vcpu, val);
4188                         kvm_complete_insn_gp(vcpu, err);
4189                         return 1;
4190                 case 4:
4191                         err = kvm_set_cr4(vcpu, val);
4192                         kvm_complete_insn_gp(vcpu, err);
4193                         return 1;
4194                 case 8: {
4195                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4196                                 u8 cr8 = kvm_register_read(vcpu, reg);
4197                                 err = kvm_set_cr8(vcpu, cr8);
4198                                 kvm_complete_insn_gp(vcpu, err);
4199                                 if (irqchip_in_kernel(vcpu->kvm))
4200                                         return 1;
4201                                 if (cr8_prev <= cr8)
4202                                         return 1;
4203                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4204                                 return 0;
4205                         }
4206                 };
4207                 break;
4208         case 2: /* clts */
4209                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4210                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4211                 skip_emulated_instruction(vcpu);
4212                 vmx_fpu_activate(vcpu);
4213                 return 1;
4214         case 1: /*mov from cr*/
4215                 switch (cr) {
4216                 case 3:
4217                         val = kvm_read_cr3(vcpu);
4218                         kvm_register_write(vcpu, reg, val);
4219                         trace_kvm_cr_read(cr, val);
4220                         skip_emulated_instruction(vcpu);
4221                         return 1;
4222                 case 8:
4223                         val = kvm_get_cr8(vcpu);
4224                         kvm_register_write(vcpu, reg, val);
4225                         trace_kvm_cr_read(cr, val);
4226                         skip_emulated_instruction(vcpu);
4227                         return 1;
4228                 }
4229                 break;
4230         case 3: /* lmsw */
4231                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4232                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4233                 kvm_lmsw(vcpu, val);
4234
4235                 skip_emulated_instruction(vcpu);
4236                 return 1;
4237         default:
4238                 break;
4239         }
4240         vcpu->run->exit_reason = 0;
4241         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4242                (int)(exit_qualification >> 4) & 3, cr);
4243         return 0;
4244 }
4245
4246 static int handle_dr(struct kvm_vcpu *vcpu)
4247 {
4248         unsigned long exit_qualification;
4249         int dr, reg;
4250
4251         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4252         if (!kvm_require_cpl(vcpu, 0))
4253                 return 1;
4254         dr = vmcs_readl(GUEST_DR7);
4255         if (dr & DR7_GD) {
4256                 /*
4257                  * As the vm-exit takes precedence over the debug trap, we
4258                  * need to emulate the latter, either for the host or the
4259                  * guest debugging itself.
4260                  */
4261                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4262                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4263                         vcpu->run->debug.arch.dr7 = dr;
4264                         vcpu->run->debug.arch.pc =
4265                                 vmcs_readl(GUEST_CS_BASE) +
4266                                 vmcs_readl(GUEST_RIP);
4267                         vcpu->run->debug.arch.exception = DB_VECTOR;
4268                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4269                         return 0;
4270                 } else {
4271                         vcpu->arch.dr7 &= ~DR7_GD;
4272                         vcpu->arch.dr6 |= DR6_BD;
4273                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4274                         kvm_queue_exception(vcpu, DB_VECTOR);
4275                         return 1;
4276                 }
4277         }
4278
4279         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4280         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4281         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4282         if (exit_qualification & TYPE_MOV_FROM_DR) {
4283                 unsigned long val;
4284                 if (!kvm_get_dr(vcpu, dr, &val))
4285                         kvm_register_write(vcpu, reg, val);
4286         } else
4287                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
4288         skip_emulated_instruction(vcpu);
4289         return 1;
4290 }
4291
4292 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4293 {
4294         vmcs_writel(GUEST_DR7, val);
4295 }
4296
4297 static int handle_cpuid(struct kvm_vcpu *vcpu)
4298 {
4299         kvm_emulate_cpuid(vcpu);
4300         return 1;
4301 }
4302
4303 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4304 {
4305         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4306         u64 data;
4307
4308         if (vmx_get_msr(vcpu, ecx, &data)) {
4309                 trace_kvm_msr_read_ex(ecx);
4310                 kvm_inject_gp(vcpu, 0);
4311                 return 1;
4312         }
4313
4314         trace_kvm_msr_read(ecx, data);
4315
4316         /* FIXME: handling of bits 32:63 of rax, rdx */
4317         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4318         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
4319         skip_emulated_instruction(vcpu);
4320         return 1;
4321 }
4322
4323 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4324 {
4325         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4326         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4327                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4328
4329         if (vmx_set_msr(vcpu, ecx, data) != 0) {
4330                 trace_kvm_msr_write_ex(ecx, data);
4331                 kvm_inject_gp(vcpu, 0);
4332                 return 1;
4333         }
4334
4335         trace_kvm_msr_write(ecx, data);
4336         skip_emulated_instruction(vcpu);
4337         return 1;
4338 }
4339
4340 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4341 {
4342         kvm_make_request(KVM_REQ_EVENT, vcpu);
4343         return 1;
4344 }
4345
4346 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4347 {
4348         u32 cpu_based_vm_exec_control;
4349
4350         /* clear pending irq */
4351         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4352         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4353         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4354
4355         kvm_make_request(KVM_REQ_EVENT, vcpu);
4356
4357         ++vcpu->stat.irq_window_exits;
4358
4359         /*
4360          * If the user space waits to inject interrupts, exit as soon as
4361          * possible
4362          */
4363         if (!irqchip_in_kernel(vcpu->kvm) &&
4364             vcpu->run->request_interrupt_window &&
4365             !kvm_cpu_has_interrupt(vcpu)) {
4366                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
4367                 return 0;
4368         }
4369         return 1;
4370 }
4371
4372 static int handle_halt(struct kvm_vcpu *vcpu)
4373 {
4374         skip_emulated_instruction(vcpu);
4375         return kvm_emulate_halt(vcpu);
4376 }
4377
4378 static int handle_vmcall(struct kvm_vcpu *vcpu)
4379 {
4380         skip_emulated_instruction(vcpu);
4381         kvm_emulate_hypercall(vcpu);
4382         return 1;
4383 }
4384
4385 static int handle_invd(struct kvm_vcpu *vcpu)
4386 {
4387         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4388 }
4389
4390 static int handle_invlpg(struct kvm_vcpu *vcpu)
4391 {
4392         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4393
4394         kvm_mmu_invlpg(vcpu, exit_qualification);
4395         skip_emulated_instruction(vcpu);
4396         return 1;
4397 }
4398
4399 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4400 {
4401         skip_emulated_instruction(vcpu);
4402         kvm_emulate_wbinvd(vcpu);
4403         return 1;
4404 }
4405
4406 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4407 {
4408         u64 new_bv = kvm_read_edx_eax(vcpu);
4409         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4410
4411         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4412                 skip_emulated_instruction(vcpu);
4413         return 1;
4414 }
4415
4416 static int handle_apic_access(struct kvm_vcpu *vcpu)
4417 {
4418         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4419 }
4420
4421 static int handle_task_switch(struct kvm_vcpu *vcpu)
4422 {
4423         struct vcpu_vmx *vmx = to_vmx(vcpu);
4424         unsigned long exit_qualification;
4425         bool has_error_code = false;
4426         u32 error_code = 0;
4427         u16 tss_selector;
4428         int reason, type, idt_v;
4429
4430         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4431         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
4432
4433         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4434
4435         reason = (u32)exit_qualification >> 30;
4436         if (reason == TASK_SWITCH_GATE && idt_v) {
4437                 switch (type) {
4438                 case INTR_TYPE_NMI_INTR:
4439                         vcpu->arch.nmi_injected = false;
4440                         vmx_set_nmi_mask(vcpu, true);
4441                         break;
4442                 case INTR_TYPE_EXT_INTR:
4443                 case INTR_TYPE_SOFT_INTR:
4444                         kvm_clear_interrupt_queue(vcpu);
4445                         break;
4446                 case INTR_TYPE_HARD_EXCEPTION:
4447                         if (vmx->idt_vectoring_info &
4448                             VECTORING_INFO_DELIVER_CODE_MASK) {
4449                                 has_error_code = true;
4450                                 error_code =
4451                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
4452                         }
4453                         /* fall through */
4454                 case INTR_TYPE_SOFT_EXCEPTION:
4455                         kvm_clear_exception_queue(vcpu);
4456                         break;
4457                 default:
4458                         break;
4459                 }
4460         }
4461         tss_selector = exit_qualification;
4462
4463         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4464                        type != INTR_TYPE_EXT_INTR &&
4465                        type != INTR_TYPE_NMI_INTR))
4466                 skip_emulated_instruction(vcpu);
4467
4468         if (kvm_task_switch(vcpu, tss_selector, reason,
4469                                 has_error_code, error_code) == EMULATE_FAIL) {
4470                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4471                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4472                 vcpu->run->internal.ndata = 0;
4473                 return 0;
4474         }
4475
4476         /* clear all local breakpoint enable flags */
4477         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4478
4479         /*
4480          * TODO: What about debug traps on tss switch?
4481          *       Are we supposed to inject them and update dr6?
4482          */
4483
4484         return 1;
4485 }
4486
4487 static int handle_ept_violation(struct kvm_vcpu *vcpu)
4488 {
4489         unsigned long exit_qualification;
4490         gpa_t gpa;
4491         int gla_validity;
4492
4493         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4494
4495         if (exit_qualification & (1 << 6)) {
4496                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
4497                 return -EINVAL;
4498         }
4499
4500         gla_validity = (exit_qualification >> 7) & 0x3;
4501         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4502                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4503                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4504                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
4505                         vmcs_readl(GUEST_LINEAR_ADDRESS));
4506                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4507                         (long unsigned int)exit_qualification);
4508                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4509                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
4510                 return 0;
4511         }
4512
4513         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4514         trace_kvm_page_fault(gpa, exit_qualification);
4515         return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
4516 }
4517
4518 static u64 ept_rsvd_mask(u64 spte, int level)
4519 {
4520         int i;
4521         u64 mask = 0;
4522
4523         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4524                 mask |= (1ULL << i);
4525
4526         if (level > 2)
4527                 /* bits 7:3 reserved */
4528                 mask |= 0xf8;
4529         else if (level == 2) {
4530                 if (spte & (1ULL << 7))
4531                         /* 2MB ref, bits 20:12 reserved */
4532                         mask |= 0x1ff000;
4533                 else
4534                         /* bits 6:3 reserved */
4535                         mask |= 0x78;
4536         }
4537
4538         return mask;
4539 }
4540
4541 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4542                                        int level)
4543 {
4544         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4545
4546         /* 010b (write-only) */
4547         WARN_ON((spte & 0x7) == 0x2);
4548
4549         /* 110b (write/execute) */
4550         WARN_ON((spte & 0x7) == 0x6);
4551
4552         /* 100b (execute-only) and value not supported by logical processor */
4553         if (!cpu_has_vmx_ept_execute_only())
4554                 WARN_ON((spte & 0x7) == 0x4);
4555
4556         /* not 000b */
4557         if ((spte & 0x7)) {
4558                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4559
4560                 if (rsvd_bits != 0) {
4561                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4562                                          __func__, rsvd_bits);
4563                         WARN_ON(1);
4564                 }
4565
4566                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4567                         u64 ept_mem_type = (spte & 0x38) >> 3;
4568
4569                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
4570                             ept_mem_type == 7) {
4571                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4572                                                 __func__, ept_mem_type);
4573                                 WARN_ON(1);
4574                         }
4575                 }
4576         }
4577 }
4578
4579 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
4580 {
4581         u64 sptes[4];
4582         int nr_sptes, i;
4583         gpa_t gpa;
4584
4585         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4586
4587         printk(KERN_ERR "EPT: Misconfiguration.\n");
4588         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4589
4590         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4591
4592         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4593                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4594
4595         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4596         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
4597
4598         return 0;
4599 }
4600
4601 static int handle_nmi_window(struct kvm_vcpu *vcpu)
4602 {
4603         u32 cpu_based_vm_exec_control;
4604
4605         /* clear pending NMI */
4606         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4607         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4608         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4609         ++vcpu->stat.nmi_window_exits;
4610         kvm_make_request(KVM_REQ_EVENT, vcpu);
4611
4612         return 1;
4613 }
4614
4615 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
4616 {
4617         struct vcpu_vmx *vmx = to_vmx(vcpu);
4618         enum emulation_result err = EMULATE_DONE;
4619         int ret = 1;
4620         u32 cpu_exec_ctrl;
4621         bool intr_window_requested;
4622
4623         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4624         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
4625
4626         while (!guest_state_valid(vcpu)) {
4627                 if (intr_window_requested
4628                     && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
4629                         return handle_interrupt_window(&vmx->vcpu);
4630
4631                 err = emulate_instruction(vcpu, 0);
4632
4633                 if (err == EMULATE_DO_MMIO) {
4634                         ret = 0;
4635                         goto out;
4636                 }
4637
4638                 if (err != EMULATE_DONE)
4639                         return 0;
4640
4641                 if (signal_pending(current))
4642                         goto out;
4643                 if (need_resched())
4644                         schedule();
4645         }
4646
4647         vmx->emulation_required = 0;
4648 out:
4649         return ret;
4650 }
4651
4652 /*
4653  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4654  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4655  */
4656 static int handle_pause(struct kvm_vcpu *vcpu)
4657 {
4658         skip_emulated_instruction(vcpu);
4659         kvm_vcpu_on_spin(vcpu);
4660
4661         return 1;
4662 }
4663
4664 static int handle_invalid_op(struct kvm_vcpu *vcpu)
4665 {
4666         kvm_queue_exception(vcpu, UD_VECTOR);
4667         return 1;
4668 }
4669
4670 /*
4671  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
4672  * We could reuse a single VMCS for all the L2 guests, but we also want the
4673  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
4674  * allows keeping them loaded on the processor, and in the future will allow
4675  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
4676  * every entry if they never change.
4677  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
4678  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
4679  *
4680  * The following functions allocate and free a vmcs02 in this pool.
4681  */
4682
4683 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
4684 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
4685 {
4686         struct vmcs02_list *item;
4687         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4688                 if (item->vmptr == vmx->nested.current_vmptr) {
4689                         list_move(&item->list, &vmx->nested.vmcs02_pool);
4690                         return &item->vmcs02;
4691                 }
4692
4693         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
4694                 /* Recycle the least recently used VMCS. */
4695                 item = list_entry(vmx->nested.vmcs02_pool.prev,
4696                         struct vmcs02_list, list);
4697                 item->vmptr = vmx->nested.current_vmptr;
4698                 list_move(&item->list, &vmx->nested.vmcs02_pool);
4699                 return &item->vmcs02;
4700         }
4701
4702         /* Create a new VMCS */
4703         item = (struct vmcs02_list *)
4704                 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
4705         if (!item)
4706                 return NULL;
4707         item->vmcs02.vmcs = alloc_vmcs();
4708         if (!item->vmcs02.vmcs) {
4709                 kfree(item);
4710                 return NULL;
4711         }
4712         loaded_vmcs_init(&item->vmcs02);
4713         item->vmptr = vmx->nested.current_vmptr;
4714         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
4715         vmx->nested.vmcs02_num++;
4716         return &item->vmcs02;
4717 }
4718
4719 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
4720 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
4721 {
4722         struct vmcs02_list *item;
4723         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4724                 if (item->vmptr == vmptr) {
4725                         free_loaded_vmcs(&item->vmcs02);
4726                         list_del(&item->list);
4727                         kfree(item);
4728                         vmx->nested.vmcs02_num--;
4729                         return;
4730                 }
4731 }
4732
4733 /*
4734  * Free all VMCSs saved for this vcpu, except the one pointed by
4735  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
4736  * currently used, if running L2), and vmcs01 when running L2.
4737  */
4738 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
4739 {
4740         struct vmcs02_list *item, *n;
4741         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4742                 if (vmx->loaded_vmcs != &item->vmcs02)
4743                         free_loaded_vmcs(&item->vmcs02);
4744                 list_del(&item->list);
4745                 kfree(item);
4746         }
4747         vmx->nested.vmcs02_num = 0;
4748
4749         if (vmx->loaded_vmcs != &vmx->vmcs01)
4750                 free_loaded_vmcs(&vmx->vmcs01);
4751 }
4752
4753 /*
4754  * Emulate the VMXON instruction.
4755  * Currently, we just remember that VMX is active, and do not save or even
4756  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
4757  * do not currently need to store anything in that guest-allocated memory
4758  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
4759  * argument is different from the VMXON pointer (which the spec says they do).
4760  */
4761 static int handle_vmon(struct kvm_vcpu *vcpu)
4762 {
4763         struct kvm_segment cs;
4764         struct vcpu_vmx *vmx = to_vmx(vcpu);
4765
4766         /* The Intel VMX Instruction Reference lists a bunch of bits that
4767          * are prerequisite to running VMXON, most notably cr4.VMXE must be
4768          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
4769          * Otherwise, we should fail with #UD. We test these now:
4770          */
4771         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
4772             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
4773             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4774                 kvm_queue_exception(vcpu, UD_VECTOR);
4775                 return 1;
4776         }
4777
4778         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4779         if (is_long_mode(vcpu) && !cs.l) {
4780                 kvm_queue_exception(vcpu, UD_VECTOR);
4781                 return 1;
4782         }
4783
4784         if (vmx_get_cpl(vcpu)) {
4785                 kvm_inject_gp(vcpu, 0);
4786                 return 1;
4787         }
4788
4789         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
4790         vmx->nested.vmcs02_num = 0;
4791
4792         vmx->nested.vmxon = true;
4793
4794         skip_emulated_instruction(vcpu);
4795         return 1;
4796 }
4797
4798 /*
4799  * Intel's VMX Instruction Reference specifies a common set of prerequisites
4800  * for running VMX instructions (except VMXON, whose prerequisites are
4801  * slightly different). It also specifies what exception to inject otherwise.
4802  */
4803 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
4804 {
4805         struct kvm_segment cs;
4806         struct vcpu_vmx *vmx = to_vmx(vcpu);
4807
4808         if (!vmx->nested.vmxon) {
4809                 kvm_queue_exception(vcpu, UD_VECTOR);
4810                 return 0;
4811         }
4812
4813         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4814         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
4815             (is_long_mode(vcpu) && !cs.l)) {
4816                 kvm_queue_exception(vcpu, UD_VECTOR);
4817                 return 0;
4818         }
4819
4820         if (vmx_get_cpl(vcpu)) {
4821                 kvm_inject_gp(vcpu, 0);
4822                 return 0;
4823         }
4824
4825         return 1;
4826 }
4827
4828 /*
4829  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
4830  * just stops using VMX.
4831  */
4832 static void free_nested(struct vcpu_vmx *vmx)
4833 {
4834         if (!vmx->nested.vmxon)
4835                 return;
4836         vmx->nested.vmxon = false;
4837         if (vmx->nested.current_vmptr != -1ull) {
4838                 kunmap(vmx->nested.current_vmcs12_page);
4839                 nested_release_page(vmx->nested.current_vmcs12_page);
4840                 vmx->nested.current_vmptr = -1ull;
4841                 vmx->nested.current_vmcs12 = NULL;
4842         }
4843         /* Unpin physical memory we referred to in current vmcs02 */
4844         if (vmx->nested.apic_access_page) {
4845                 nested_release_page(vmx->nested.apic_access_page);
4846                 vmx->nested.apic_access_page = 0;
4847         }
4848
4849         nested_free_all_saved_vmcss(vmx);
4850 }
4851
4852 /* Emulate the VMXOFF instruction */
4853 static int handle_vmoff(struct kvm_vcpu *vcpu)
4854 {
4855         if (!nested_vmx_check_permission(vcpu))
4856                 return 1;
4857         free_nested(to_vmx(vcpu));
4858         skip_emulated_instruction(vcpu);
4859         return 1;
4860 }
4861
4862 /*
4863  * Decode the memory-address operand of a vmx instruction, as recorded on an
4864  * exit caused by such an instruction (run by a guest hypervisor).
4865  * On success, returns 0. When the operand is invalid, returns 1 and throws
4866  * #UD or #GP.
4867  */
4868 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
4869                                  unsigned long exit_qualification,
4870                                  u32 vmx_instruction_info, gva_t *ret)
4871 {
4872         /*
4873          * According to Vol. 3B, "Information for VM Exits Due to Instruction
4874          * Execution", on an exit, vmx_instruction_info holds most of the
4875          * addressing components of the operand. Only the displacement part
4876          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
4877          * For how an actual address is calculated from all these components,
4878          * refer to Vol. 1, "Operand Addressing".
4879          */
4880         int  scaling = vmx_instruction_info & 3;
4881         int  addr_size = (vmx_instruction_info >> 7) & 7;
4882         bool is_reg = vmx_instruction_info & (1u << 10);
4883         int  seg_reg = (vmx_instruction_info >> 15) & 7;
4884         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
4885         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
4886         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
4887         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
4888
4889         if (is_reg) {
4890                 kvm_queue_exception(vcpu, UD_VECTOR);
4891                 return 1;
4892         }
4893
4894         /* Addr = segment_base + offset */
4895         /* offset = base + [index * scale] + displacement */
4896         *ret = vmx_get_segment_base(vcpu, seg_reg);
4897         if (base_is_valid)
4898                 *ret += kvm_register_read(vcpu, base_reg);
4899         if (index_is_valid)
4900                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
4901         *ret += exit_qualification; /* holds the displacement */
4902
4903         if (addr_size == 1) /* 32 bit */
4904                 *ret &= 0xffffffff;
4905
4906         /*
4907          * TODO: throw #GP (and return 1) in various cases that the VM*
4908          * instructions require it - e.g., offset beyond segment limit,
4909          * unusable or unreadable/unwritable segment, non-canonical 64-bit
4910          * address, and so on. Currently these are not checked.
4911          */
4912         return 0;
4913 }
4914
4915 /*
4916  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
4917  * set the success or error code of an emulated VMX instruction, as specified
4918  * by Vol 2B, VMX Instruction Reference, "Conventions".
4919  */
4920 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
4921 {
4922         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
4923                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
4924                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
4925 }
4926
4927 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
4928 {
4929         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
4930                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
4931                             X86_EFLAGS_SF | X86_EFLAGS_OF))
4932                         | X86_EFLAGS_CF);
4933 }
4934
4935 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
4936                                         u32 vm_instruction_error)
4937 {
4938         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
4939                 /*
4940                  * failValid writes the error number to the current VMCS, which
4941                  * can't be done there isn't a current VMCS.
4942                  */
4943                 nested_vmx_failInvalid(vcpu);
4944                 return;
4945         }
4946         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
4947                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
4948                             X86_EFLAGS_SF | X86_EFLAGS_OF))
4949                         | X86_EFLAGS_ZF);
4950         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
4951 }
4952
4953 /* Emulate the VMCLEAR instruction */
4954 static int handle_vmclear(struct kvm_vcpu *vcpu)
4955 {
4956         struct vcpu_vmx *vmx = to_vmx(vcpu);
4957         gva_t gva;
4958         gpa_t vmptr;
4959         struct vmcs12 *vmcs12;
4960         struct page *page;
4961         struct x86_exception e;
4962
4963         if (!nested_vmx_check_permission(vcpu))
4964                 return 1;
4965
4966         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
4967                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
4968                 return 1;
4969
4970         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
4971                                 sizeof(vmptr), &e)) {
4972                 kvm_inject_page_fault(vcpu, &e);
4973                 return 1;
4974         }
4975
4976         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
4977                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
4978                 skip_emulated_instruction(vcpu);
4979                 return 1;
4980         }
4981
4982         if (vmptr == vmx->nested.current_vmptr) {
4983                 kunmap(vmx->nested.current_vmcs12_page);
4984                 nested_release_page(vmx->nested.current_vmcs12_page);
4985                 vmx->nested.current_vmptr = -1ull;
4986                 vmx->nested.current_vmcs12 = NULL;
4987         }
4988
4989         page = nested_get_page(vcpu, vmptr);
4990         if (page == NULL) {
4991                 /*
4992                  * For accurate processor emulation, VMCLEAR beyond available
4993                  * physical memory should do nothing at all. However, it is
4994                  * possible that a nested vmx bug, not a guest hypervisor bug,
4995                  * resulted in this case, so let's shut down before doing any
4996                  * more damage:
4997                  */
4998                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4999                 return 1;
5000         }
5001         vmcs12 = kmap(page);
5002         vmcs12->launch_state = 0;
5003         kunmap(page);
5004         nested_release_page(page);
5005
5006         nested_free_vmcs02(vmx, vmptr);
5007
5008         skip_emulated_instruction(vcpu);
5009         nested_vmx_succeed(vcpu);
5010         return 1;
5011 }
5012
5013 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5014
5015 /* Emulate the VMLAUNCH instruction */
5016 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5017 {
5018         return nested_vmx_run(vcpu, true);
5019 }
5020
5021 /* Emulate the VMRESUME instruction */
5022 static int handle_vmresume(struct kvm_vcpu *vcpu)
5023 {
5024
5025         return nested_vmx_run(vcpu, false);
5026 }
5027
5028 enum vmcs_field_type {
5029         VMCS_FIELD_TYPE_U16 = 0,
5030         VMCS_FIELD_TYPE_U64 = 1,
5031         VMCS_FIELD_TYPE_U32 = 2,
5032         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5033 };
5034
5035 static inline int vmcs_field_type(unsigned long field)
5036 {
5037         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
5038                 return VMCS_FIELD_TYPE_U32;
5039         return (field >> 13) & 0x3 ;
5040 }
5041
5042 static inline int vmcs_field_readonly(unsigned long field)
5043 {
5044         return (((field >> 10) & 0x3) == 1);
5045 }
5046
5047 /*
5048  * Read a vmcs12 field. Since these can have varying lengths and we return
5049  * one type, we chose the biggest type (u64) and zero-extend the return value
5050  * to that size. Note that the caller, handle_vmread, might need to use only
5051  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5052  * 64-bit fields are to be returned).
5053  */
5054 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5055                                         unsigned long field, u64 *ret)
5056 {
5057         short offset = vmcs_field_to_offset(field);
5058         char *p;
5059
5060         if (offset < 0)
5061                 return 0;
5062
5063         p = ((char *)(get_vmcs12(vcpu))) + offset;
5064
5065         switch (vmcs_field_type(field)) {
5066         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5067                 *ret = *((natural_width *)p);
5068                 return 1;
5069         case VMCS_FIELD_TYPE_U16:
5070                 *ret = *((u16 *)p);
5071                 return 1;
5072         case VMCS_FIELD_TYPE_U32:
5073                 *ret = *((u32 *)p);
5074                 return 1;
5075         case VMCS_FIELD_TYPE_U64:
5076                 *ret = *((u64 *)p);
5077                 return 1;
5078         default:
5079                 return 0; /* can never happen. */
5080         }
5081 }
5082
5083 /*
5084  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5085  * used before) all generate the same failure when it is missing.
5086  */
5087 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5088 {
5089         struct vcpu_vmx *vmx = to_vmx(vcpu);
5090         if (vmx->nested.current_vmptr == -1ull) {
5091                 nested_vmx_failInvalid(vcpu);
5092                 skip_emulated_instruction(vcpu);
5093                 return 0;
5094         }
5095         return 1;
5096 }
5097
5098 static int handle_vmread(struct kvm_vcpu *vcpu)
5099 {
5100         unsigned long field;
5101         u64 field_value;
5102         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5103         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5104         gva_t gva = 0;
5105
5106         if (!nested_vmx_check_permission(vcpu) ||
5107             !nested_vmx_check_vmcs12(vcpu))
5108                 return 1;
5109
5110         /* Decode instruction info and find the field to read */
5111         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5112         /* Read the field, zero-extended to a u64 field_value */
5113         if (!vmcs12_read_any(vcpu, field, &field_value)) {
5114                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5115                 skip_emulated_instruction(vcpu);
5116                 return 1;
5117         }
5118         /*
5119          * Now copy part of this value to register or memory, as requested.
5120          * Note that the number of bits actually copied is 32 or 64 depending
5121          * on the guest's mode (32 or 64 bit), not on the given field's length.
5122          */
5123         if (vmx_instruction_info & (1u << 10)) {
5124                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5125                         field_value);
5126         } else {
5127                 if (get_vmx_mem_address(vcpu, exit_qualification,
5128                                 vmx_instruction_info, &gva))
5129                         return 1;
5130                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5131                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5132                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5133         }
5134
5135         nested_vmx_succeed(vcpu);
5136         skip_emulated_instruction(vcpu);
5137         return 1;
5138 }
5139
5140
5141 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5142 {
5143         unsigned long field;
5144         gva_t gva;
5145         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5146         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5147         char *p;
5148         short offset;
5149         /* The value to write might be 32 or 64 bits, depending on L1's long
5150          * mode, and eventually we need to write that into a field of several
5151          * possible lengths. The code below first zero-extends the value to 64
5152          * bit (field_value), and then copies only the approriate number of
5153          * bits into the vmcs12 field.
5154          */
5155         u64 field_value = 0;
5156         struct x86_exception e;
5157
5158         if (!nested_vmx_check_permission(vcpu) ||
5159             !nested_vmx_check_vmcs12(vcpu))
5160                 return 1;
5161
5162         if (vmx_instruction_info & (1u << 10))
5163                 field_value = kvm_register_read(vcpu,
5164                         (((vmx_instruction_info) >> 3) & 0xf));
5165         else {
5166                 if (get_vmx_mem_address(vcpu, exit_qualification,
5167                                 vmx_instruction_info, &gva))
5168                         return 1;
5169                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5170                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5171                         kvm_inject_page_fault(vcpu, &e);
5172                         return 1;
5173                 }
5174         }
5175
5176
5177         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5178         if (vmcs_field_readonly(field)) {
5179                 nested_vmx_failValid(vcpu,
5180                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5181                 skip_emulated_instruction(vcpu);
5182                 return 1;
5183         }
5184
5185         offset = vmcs_field_to_offset(field);
5186         if (offset < 0) {
5187                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5188                 skip_emulated_instruction(vcpu);
5189                 return 1;
5190         }
5191         p = ((char *) get_vmcs12(vcpu)) + offset;
5192
5193         switch (vmcs_field_type(field)) {
5194         case VMCS_FIELD_TYPE_U16:
5195                 *(u16 *)p = field_value;
5196                 break;
5197         case VMCS_FIELD_TYPE_U32:
5198                 *(u32 *)p = field_value;
5199                 break;
5200         case VMCS_FIELD_TYPE_U64:
5201                 *(u64 *)p = field_value;
5202                 break;
5203         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5204                 *(natural_width *)p = field_value;
5205                 break;
5206         default:
5207                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5208                 skip_emulated_instruction(vcpu);
5209                 return 1;
5210         }
5211
5212         nested_vmx_succeed(vcpu);
5213         skip_emulated_instruction(vcpu);
5214         return 1;
5215 }
5216
5217 /* Emulate the VMPTRLD instruction */
5218 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5219 {
5220         struct vcpu_vmx *vmx = to_vmx(vcpu);
5221         gva_t gva;
5222         gpa_t vmptr;
5223         struct x86_exception e;
5224
5225         if (!nested_vmx_check_permission(vcpu))
5226                 return 1;
5227
5228         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5229                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5230                 return 1;
5231
5232         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5233                                 sizeof(vmptr), &e)) {
5234                 kvm_inject_page_fault(vcpu, &e);
5235                 return 1;
5236         }
5237
5238         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5239                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5240                 skip_emulated_instruction(vcpu);
5241                 return 1;
5242         }
5243
5244         if (vmx->nested.current_vmptr != vmptr) {
5245                 struct vmcs12 *new_vmcs12;
5246                 struct page *page;
5247                 page = nested_get_page(vcpu, vmptr);
5248                 if (page == NULL) {
5249                         nested_vmx_failInvalid(vcpu);
5250                         skip_emulated_instruction(vcpu);
5251                         return 1;
5252                 }
5253                 new_vmcs12 = kmap(page);
5254                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5255                         kunmap(page);
5256                         nested_release_page_clean(page);
5257                         nested_vmx_failValid(vcpu,
5258                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5259                         skip_emulated_instruction(vcpu);
5260                         return 1;
5261                 }
5262                 if (vmx->nested.current_vmptr != -1ull) {
5263                         kunmap(vmx->nested.current_vmcs12_page);
5264                         nested_release_page(vmx->nested.current_vmcs12_page);
5265                 }
5266
5267                 vmx->nested.current_vmptr = vmptr;
5268                 vmx->nested.current_vmcs12 = new_vmcs12;
5269                 vmx->nested.current_vmcs12_page = page;
5270         }
5271
5272         nested_vmx_succeed(vcpu);
5273         skip_emulated_instruction(vcpu);
5274         return 1;
5275 }
5276
5277 /* Emulate the VMPTRST instruction */
5278 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5279 {
5280         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5281         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5282         gva_t vmcs_gva;
5283         struct x86_exception e;
5284
5285         if (!nested_vmx_check_permission(vcpu))
5286                 return 1;
5287
5288         if (get_vmx_mem_address(vcpu, exit_qualification,
5289                         vmx_instruction_info, &vmcs_gva))
5290                 return 1;
5291         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5292         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5293                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
5294                                  sizeof(u64), &e)) {
5295                 kvm_inject_page_fault(vcpu, &e);
5296                 return 1;
5297         }
5298         nested_vmx_succeed(vcpu);
5299         skip_emulated_instruction(vcpu);
5300         return 1;
5301 }
5302
5303 /*
5304  * The exit handlers return 1 if the exit was handled fully and guest execution
5305  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5306  * to be done to userspace and return 0.
5307  */
5308 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5309         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
5310         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5311         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5312         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5313         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5314         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5315         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5316         [EXIT_REASON_CPUID]                   = handle_cpuid,
5317         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
5318         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
5319         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
5320         [EXIT_REASON_HLT]                     = handle_halt,
5321         [EXIT_REASON_INVD]                    = handle_invd,
5322         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5323         [EXIT_REASON_VMCALL]                  = handle_vmcall,
5324         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
5325         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
5326         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
5327         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
5328         [EXIT_REASON_VMREAD]                  = handle_vmread,
5329         [EXIT_REASON_VMRESUME]                = handle_vmresume,
5330         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
5331         [EXIT_REASON_VMOFF]                   = handle_vmoff,
5332         [EXIT_REASON_VMON]                    = handle_vmon,
5333         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5334         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5335         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
5336         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
5337         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5338         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5339         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5340         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5341         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5342         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
5343         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
5344 };
5345
5346 static const int kvm_vmx_max_exit_handlers =
5347         ARRAY_SIZE(kvm_vmx_exit_handlers);
5348
5349 /*
5350  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5351  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5352  * disinterest in the current event (read or write a specific MSR) by using an
5353  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5354  */
5355 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5356         struct vmcs12 *vmcs12, u32 exit_reason)
5357 {
5358         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5359         gpa_t bitmap;
5360
5361         if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5362                 return 1;
5363
5364         /*
5365          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5366          * for the four combinations of read/write and low/high MSR numbers.
5367          * First we need to figure out which of the four to use:
5368          */
5369         bitmap = vmcs12->msr_bitmap;
5370         if (exit_reason == EXIT_REASON_MSR_WRITE)
5371                 bitmap += 2048;
5372         if (msr_index >= 0xc0000000) {
5373                 msr_index -= 0xc0000000;
5374                 bitmap += 1024;
5375         }
5376
5377         /* Then read the msr_index'th bit from this bitmap: */
5378         if (msr_index < 1024*8) {
5379                 unsigned char b;
5380                 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5381                 return 1 & (b >> (msr_index & 7));
5382         } else
5383                 return 1; /* let L1 handle the wrong parameter */
5384 }
5385
5386 /*
5387  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5388  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5389  * intercept (via guest_host_mask etc.) the current event.
5390  */
5391 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5392         struct vmcs12 *vmcs12)
5393 {
5394         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5395         int cr = exit_qualification & 15;
5396         int reg = (exit_qualification >> 8) & 15;
5397         unsigned long val = kvm_register_read(vcpu, reg);
5398
5399         switch ((exit_qualification >> 4) & 3) {
5400         case 0: /* mov to cr */
5401                 switch (cr) {
5402                 case 0:
5403                         if (vmcs12->cr0_guest_host_mask &
5404                             (val ^ vmcs12->cr0_read_shadow))
5405                                 return 1;
5406                         break;
5407                 case 3:
5408                         if ((vmcs12->cr3_target_count >= 1 &&
5409                                         vmcs12->cr3_target_value0 == val) ||
5410                                 (vmcs12->cr3_target_count >= 2 &&
5411                                         vmcs12->cr3_target_value1 == val) ||
5412                                 (vmcs12->cr3_target_count >= 3 &&
5413                                         vmcs12->cr3_target_value2 == val) ||
5414                                 (vmcs12->cr3_target_count >= 4 &&
5415                                         vmcs12->cr3_target_value3 == val))
5416                                 return 0;
5417                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5418                                 return 1;
5419                         break;
5420                 case 4:
5421                         if (vmcs12->cr4_guest_host_mask &
5422                             (vmcs12->cr4_read_shadow ^ val))
5423                                 return 1;
5424                         break;
5425                 case 8:
5426                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5427                                 return 1;
5428                         break;
5429                 }
5430                 break;
5431         case 2: /* clts */
5432                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5433                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
5434                         return 1;
5435                 break;
5436         case 1: /* mov from cr */
5437                 switch (cr) {
5438                 case 3:
5439                         if (vmcs12->cpu_based_vm_exec_control &
5440                             CPU_BASED_CR3_STORE_EXITING)
5441                                 return 1;
5442                         break;
5443                 case 8:
5444                         if (vmcs12->cpu_based_vm_exec_control &
5445                             CPU_BASED_CR8_STORE_EXITING)
5446                                 return 1;
5447                         break;
5448                 }
5449                 break;
5450         case 3: /* lmsw */
5451                 /*
5452                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5453                  * cr0. Other attempted changes are ignored, with no exit.
5454                  */
5455                 if (vmcs12->cr0_guest_host_mask & 0xe &
5456                     (val ^ vmcs12->cr0_read_shadow))
5457                         return 1;
5458                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5459                     !(vmcs12->cr0_read_shadow & 0x1) &&
5460                     (val & 0x1))
5461                         return 1;
5462                 break;
5463         }
5464         return 0;
5465 }
5466
5467 /*
5468  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5469  * should handle it ourselves in L0 (and then continue L2). Only call this
5470  * when in is_guest_mode (L2).
5471  */
5472 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5473 {
5474         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5475         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5476         struct vcpu_vmx *vmx = to_vmx(vcpu);
5477         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5478
5479         if (vmx->nested.nested_run_pending)
5480                 return 0;
5481
5482         if (unlikely(vmx->fail)) {
5483                 printk(KERN_INFO "%s failed vm entry %x\n",
5484                        __func__, vmcs_read32(VM_INSTRUCTION_ERROR));
5485                 return 1;
5486         }
5487
5488         switch (exit_reason) {
5489         case EXIT_REASON_EXCEPTION_NMI:
5490                 if (!is_exception(intr_info))
5491                         return 0;
5492                 else if (is_page_fault(intr_info))
5493                         return enable_ept;
5494                 return vmcs12->exception_bitmap &
5495                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5496         case EXIT_REASON_EXTERNAL_INTERRUPT:
5497                 return 0;
5498         case EXIT_REASON_TRIPLE_FAULT:
5499                 return 1;
5500         case EXIT_REASON_PENDING_INTERRUPT:
5501         case EXIT_REASON_NMI_WINDOW:
5502                 /*
5503                  * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5504                  * (aka Interrupt Window Exiting) only when L1 turned it on,
5505                  * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5506                  * Same for NMI Window Exiting.
5507                  */
5508                 return 1;
5509         case EXIT_REASON_TASK_SWITCH:
5510                 return 1;
5511         case EXIT_REASON_CPUID:
5512                 return 1;
5513         case EXIT_REASON_HLT:
5514                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5515         case EXIT_REASON_INVD:
5516                 return 1;
5517         case EXIT_REASON_INVLPG:
5518                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5519         case EXIT_REASON_RDPMC:
5520                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5521         case EXIT_REASON_RDTSC:
5522                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5523         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5524         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5525         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5526         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5527         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5528                 /*
5529                  * VMX instructions trap unconditionally. This allows L1 to
5530                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
5531                  */
5532                 return 1;
5533         case EXIT_REASON_CR_ACCESS:
5534                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5535         case EXIT_REASON_DR_ACCESS:
5536                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5537         case EXIT_REASON_IO_INSTRUCTION:
5538                 /* TODO: support IO bitmaps */
5539                 return 1;
5540         case EXIT_REASON_MSR_READ:
5541         case EXIT_REASON_MSR_WRITE:
5542                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5543         case EXIT_REASON_INVALID_STATE:
5544                 return 1;
5545         case EXIT_REASON_MWAIT_INSTRUCTION:
5546                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5547         case EXIT_REASON_MONITOR_INSTRUCTION:
5548                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5549         case EXIT_REASON_PAUSE_INSTRUCTION:
5550                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5551                         nested_cpu_has2(vmcs12,
5552                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5553         case EXIT_REASON_MCE_DURING_VMENTRY:
5554                 return 0;
5555         case EXIT_REASON_TPR_BELOW_THRESHOLD:
5556                 return 1;
5557         case EXIT_REASON_APIC_ACCESS:
5558                 return nested_cpu_has2(vmcs12,
5559                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5560         case EXIT_REASON_EPT_VIOLATION:
5561         case EXIT_REASON_EPT_MISCONFIG:
5562                 return 0;
5563         case EXIT_REASON_WBINVD:
5564                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5565         case EXIT_REASON_XSETBV:
5566                 return 1;
5567         default:
5568                 return 1;
5569         }
5570 }
5571
5572 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5573 {
5574         *info1 = vmcs_readl(EXIT_QUALIFICATION);
5575         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5576 }
5577
5578 /*
5579  * The guest has exited.  See if we can fix it or if we need userspace
5580  * assistance.
5581  */
5582 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5583 {
5584         struct vcpu_vmx *vmx = to_vmx(vcpu);
5585         u32 exit_reason = vmx->exit_reason;
5586         u32 vectoring_info = vmx->idt_vectoring_info;
5587
5588         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
5589
5590         /* If guest state is invalid, start emulating */
5591         if (vmx->emulation_required && emulate_invalid_guest_state)
5592                 return handle_invalid_guest_state(vcpu);
5593
5594         /*
5595          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5596          * we did not inject a still-pending event to L1 now because of
5597          * nested_run_pending, we need to re-enable this bit.
5598          */
5599         if (vmx->nested.nested_run_pending)
5600                 kvm_make_request(KVM_REQ_EVENT, vcpu);
5601
5602         if (exit_reason == EXIT_REASON_VMLAUNCH ||
5603             exit_reason == EXIT_REASON_VMRESUME)
5604                 vmx->nested.nested_run_pending = 1;
5605         else
5606                 vmx->nested.nested_run_pending = 0;
5607
5608         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5609                 nested_vmx_vmexit(vcpu);
5610                 return 1;
5611         }
5612
5613         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5614                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5615                 vcpu->run->fail_entry.hardware_entry_failure_reason
5616                         = exit_reason;
5617                 return 0;
5618         }
5619
5620         if (unlikely(vmx->fail)) {
5621                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5622                 vcpu->run->fail_entry.hardware_entry_failure_reason
5623                         = vmcs_read32(VM_INSTRUCTION_ERROR);
5624                 return 0;
5625         }
5626
5627         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5628                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5629                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
5630                         exit_reason != EXIT_REASON_TASK_SWITCH))
5631                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
5632                        "(0x%x) and exit reason is 0x%x\n",
5633                        __func__, vectoring_info, exit_reason);
5634
5635         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
5636             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
5637                                         get_vmcs12(vcpu), vcpu)))) {
5638                 if (vmx_interrupt_allowed(vcpu)) {
5639                         vmx->soft_vnmi_blocked = 0;
5640                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
5641                            vcpu->arch.nmi_pending) {
5642                         /*
5643                          * This CPU don't support us in finding the end of an
5644                          * NMI-blocked window if the guest runs with IRQs
5645                          * disabled. So we pull the trigger after 1 s of
5646                          * futile waiting, but inform the user about this.
5647                          */
5648                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5649                                "state on VCPU %d after 1 s timeout\n",
5650                                __func__, vcpu->vcpu_id);
5651                         vmx->soft_vnmi_blocked = 0;
5652                 }
5653         }
5654
5655         if (exit_reason < kvm_vmx_max_exit_handlers
5656             && kvm_vmx_exit_handlers[exit_reason])
5657                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5658         else {
5659                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5660                 vcpu->run->hw.hardware_exit_reason = exit_reason;
5661         }
5662         return 0;
5663 }
5664
5665 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5666 {
5667         if (irr == -1 || tpr < irr) {
5668                 vmcs_write32(TPR_THRESHOLD, 0);
5669                 return;
5670         }
5671
5672         vmcs_write32(TPR_THRESHOLD, irr);
5673 }
5674
5675 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
5676 {
5677         u32 exit_intr_info;
5678
5679         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
5680               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
5681                 return;
5682
5683         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5684         exit_intr_info = vmx->exit_intr_info;
5685
5686         /* Handle machine checks before interrupts are enabled */
5687         if (is_machine_check(exit_intr_info))
5688                 kvm_machine_check();
5689
5690         /* We need to handle NMIs before interrupts are enabled */
5691         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
5692             (exit_intr_info & INTR_INFO_VALID_MASK)) {
5693                 kvm_before_handle_nmi(&vmx->vcpu);
5694                 asm("int $2");
5695                 kvm_after_handle_nmi(&vmx->vcpu);
5696         }
5697 }
5698
5699 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
5700 {
5701         u32 exit_intr_info;
5702         bool unblock_nmi;
5703         u8 vector;
5704         bool idtv_info_valid;
5705
5706         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
5707
5708         if (cpu_has_virtual_nmis()) {
5709                 if (vmx->nmi_known_unmasked)
5710                         return;
5711                 /*
5712                  * Can't use vmx->exit_intr_info since we're not sure what
5713                  * the exit reason is.
5714                  */
5715                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5716                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
5717                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
5718                 /*
5719                  * SDM 3: 27.7.1.2 (September 2008)
5720                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
5721                  * a guest IRET fault.
5722                  * SDM 3: 23.2.2 (September 2008)
5723                  * Bit 12 is undefined in any of the following cases:
5724                  *  If the VM exit sets the valid bit in the IDT-vectoring
5725                  *   information field.
5726                  *  If the VM exit is due to a double fault.
5727                  */
5728                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
5729                     vector != DF_VECTOR && !idtv_info_valid)
5730                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5731                                       GUEST_INTR_STATE_NMI);
5732                 else
5733                         vmx->nmi_known_unmasked =
5734                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
5735                                   & GUEST_INTR_STATE_NMI);
5736         } else if (unlikely(vmx->soft_vnmi_blocked))
5737                 vmx->vnmi_blocked_time +=
5738                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
5739 }
5740
5741 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
5742                                       u32 idt_vectoring_info,
5743                                       int instr_len_field,
5744                                       int error_code_field)
5745 {
5746         u8 vector;
5747         int type;
5748         bool idtv_info_valid;
5749
5750         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
5751
5752         vmx->vcpu.arch.nmi_injected = false;
5753         kvm_clear_exception_queue(&vmx->vcpu);
5754         kvm_clear_interrupt_queue(&vmx->vcpu);
5755
5756         if (!idtv_info_valid)
5757                 return;
5758
5759         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5760
5761         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
5762         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
5763
5764         switch (type) {
5765         case INTR_TYPE_NMI_INTR:
5766                 vmx->vcpu.arch.nmi_injected = true;
5767                 /*
5768                  * SDM 3: 27.7.1.2 (September 2008)
5769                  * Clear bit "block by NMI" before VM entry if a NMI
5770                  * delivery faulted.
5771                  */
5772                 vmx_set_nmi_mask(&vmx->vcpu, false);
5773                 break;
5774         case INTR_TYPE_SOFT_EXCEPTION:
5775                 vmx->vcpu.arch.event_exit_inst_len =
5776                         vmcs_read32(instr_len_field);
5777                 /* fall through */
5778         case INTR_TYPE_HARD_EXCEPTION:
5779                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
5780                         u32 err = vmcs_read32(error_code_field);
5781                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
5782                 } else
5783                         kvm_queue_exception(&vmx->vcpu, vector);
5784                 break;
5785         case INTR_TYPE_SOFT_INTR:
5786                 vmx->vcpu.arch.event_exit_inst_len =
5787                         vmcs_read32(instr_len_field);
5788                 /* fall through */
5789         case INTR_TYPE_EXT_INTR:
5790                 kvm_queue_interrupt(&vmx->vcpu, vector,
5791                         type == INTR_TYPE_SOFT_INTR);
5792                 break;
5793         default:
5794                 break;
5795         }
5796 }
5797
5798 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
5799 {
5800         __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
5801                                   VM_EXIT_INSTRUCTION_LEN,
5802                                   IDT_VECTORING_ERROR_CODE);
5803 }
5804
5805 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
5806 {
5807         __vmx_complete_interrupts(to_vmx(vcpu),
5808                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5809                                   VM_ENTRY_INSTRUCTION_LEN,
5810                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
5811
5812         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
5813 }
5814
5815 #ifdef CONFIG_X86_64
5816 #define R "r"
5817 #define Q "q"
5818 #else
5819 #define R "e"
5820 #define Q "l"
5821 #endif
5822
5823 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
5824 {
5825         struct vcpu_vmx *vmx = to_vmx(vcpu);
5826
5827         /* Record the guest's net vcpu time for enforced NMI injections. */
5828         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
5829                 vmx->entry_time = ktime_get();
5830
5831         /* Don't enter VMX if guest state is invalid, let the exit handler
5832            start emulation until we arrive back to a valid state */
5833         if (vmx->emulation_required && emulate_invalid_guest_state)
5834                 return;
5835
5836         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
5837                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
5838         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
5839                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
5840
5841         /* When single-stepping over STI and MOV SS, we must clear the
5842          * corresponding interruptibility bits in the guest state. Otherwise
5843          * vmentry fails as it then expects bit 14 (BS) in pending debug
5844          * exceptions being set, but that's not correct for the guest debugging
5845          * case. */
5846         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5847                 vmx_set_interrupt_shadow(vcpu, 0);
5848
5849         vmx->__launched = vmx->loaded_vmcs->launched;
5850         asm(
5851                 /* Store host registers */
5852                 "push %%"R"dx; push %%"R"bp;"
5853                 "push %%"R"cx \n\t" /* placeholder for guest rcx */
5854                 "push %%"R"cx \n\t"
5855                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
5856                 "je 1f \n\t"
5857                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
5858                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
5859                 "1: \n\t"
5860                 /* Reload cr2 if changed */
5861                 "mov %c[cr2](%0), %%"R"ax \n\t"
5862                 "mov %%cr2, %%"R"dx \n\t"
5863                 "cmp %%"R"ax, %%"R"dx \n\t"
5864                 "je 2f \n\t"
5865                 "mov %%"R"ax, %%cr2 \n\t"
5866                 "2: \n\t"
5867                 /* Check if vmlaunch of vmresume is needed */
5868                 "cmpl $0, %c[launched](%0) \n\t"
5869                 /* Load guest registers.  Don't clobber flags. */
5870                 "mov %c[rax](%0), %%"R"ax \n\t"
5871                 "mov %c[rbx](%0), %%"R"bx \n\t"
5872                 "mov %c[rdx](%0), %%"R"dx \n\t"
5873                 "mov %c[rsi](%0), %%"R"si \n\t"
5874                 "mov %c[rdi](%0), %%"R"di \n\t"
5875                 "mov %c[rbp](%0), %%"R"bp \n\t"
5876 #ifdef CONFIG_X86_64
5877                 "mov %c[r8](%0),  %%r8  \n\t"
5878                 "mov %c[r9](%0),  %%r9  \n\t"
5879                 "mov %c[r10](%0), %%r10 \n\t"
5880                 "mov %c[r11](%0), %%r11 \n\t"
5881                 "mov %c[r12](%0), %%r12 \n\t"
5882                 "mov %c[r13](%0), %%r13 \n\t"
5883                 "mov %c[r14](%0), %%r14 \n\t"
5884                 "mov %c[r15](%0), %%r15 \n\t"
5885 #endif
5886                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
5887
5888                 /* Enter guest mode */
5889                 "jne .Llaunched \n\t"
5890                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
5891                 "jmp .Lkvm_vmx_return \n\t"
5892                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
5893                 ".Lkvm_vmx_return: "
5894                 /* Save guest registers, load host registers, keep flags */
5895                 "mov %0, %c[wordsize](%%"R"sp) \n\t"
5896                 "pop %0 \n\t"
5897                 "mov %%"R"ax, %c[rax](%0) \n\t"
5898                 "mov %%"R"bx, %c[rbx](%0) \n\t"
5899                 "pop"Q" %c[rcx](%0) \n\t"
5900                 "mov %%"R"dx, %c[rdx](%0) \n\t"
5901                 "mov %%"R"si, %c[rsi](%0) \n\t"
5902                 "mov %%"R"di, %c[rdi](%0) \n\t"
5903                 "mov %%"R"bp, %c[rbp](%0) \n\t"
5904 #ifdef CONFIG_X86_64
5905                 "mov %%r8,  %c[r8](%0) \n\t"
5906                 "mov %%r9,  %c[r9](%0) \n\t"
5907                 "mov %%r10, %c[r10](%0) \n\t"
5908                 "mov %%r11, %c[r11](%0) \n\t"
5909                 "mov %%r12, %c[r12](%0) \n\t"
5910                 "mov %%r13, %c[r13](%0) \n\t"
5911                 "mov %%r14, %c[r14](%0) \n\t"
5912                 "mov %%r15, %c[r15](%0) \n\t"
5913 #endif
5914                 "mov %%cr2, %%"R"ax   \n\t"
5915                 "mov %%"R"ax, %c[cr2](%0) \n\t"
5916
5917                 "pop  %%"R"bp; pop  %%"R"dx \n\t"
5918                 "setbe %c[fail](%0) \n\t"
5919               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
5920                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
5921                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
5922                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
5923                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
5924                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
5925                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
5926                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
5927                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
5928                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
5929                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
5930 #ifdef CONFIG_X86_64
5931                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
5932                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
5933                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
5934                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
5935                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
5936                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
5937                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
5938                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
5939 #endif
5940                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
5941                 [wordsize]"i"(sizeof(ulong))
5942               : "cc", "memory"
5943                 , R"ax", R"bx", R"di", R"si"
5944 #ifdef CONFIG_X86_64
5945                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
5946 #endif
5947               );
5948
5949         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
5950                                   | (1 << VCPU_EXREG_RFLAGS)
5951                                   | (1 << VCPU_EXREG_CPL)
5952                                   | (1 << VCPU_EXREG_PDPTR)
5953                                   | (1 << VCPU_EXREG_SEGMENTS)
5954                                   | (1 << VCPU_EXREG_CR3));
5955         vcpu->arch.regs_dirty = 0;
5956
5957         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
5958
5959         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
5960         vmx->loaded_vmcs->launched = 1;
5961
5962         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
5963
5964         vmx_complete_atomic_exit(vmx);
5965         vmx_recover_nmi_blocking(vmx);
5966         vmx_complete_interrupts(vmx);
5967 }
5968
5969 #undef R
5970 #undef Q
5971
5972 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
5973 {
5974         struct vcpu_vmx *vmx = to_vmx(vcpu);
5975
5976         free_vpid(vmx);
5977         free_nested(vmx);
5978         free_loaded_vmcs(vmx->loaded_vmcs);
5979         kfree(vmx->guest_msrs);
5980         kvm_vcpu_uninit(vcpu);
5981         kmem_cache_free(kvm_vcpu_cache, vmx);
5982 }
5983
5984 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
5985 {
5986         int err;
5987         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
5988         int cpu;
5989
5990         if (!vmx)
5991                 return ERR_PTR(-ENOMEM);
5992
5993         allocate_vpid(vmx);
5994
5995         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
5996         if (err)
5997                 goto free_vcpu;
5998
5999         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
6000         err = -ENOMEM;
6001         if (!vmx->guest_msrs) {
6002                 goto uninit_vcpu;
6003         }
6004
6005         vmx->loaded_vmcs = &vmx->vmcs01;
6006         vmx->loaded_vmcs->vmcs = alloc_vmcs();
6007         if (!vmx->loaded_vmcs->vmcs)
6008                 goto free_msrs;
6009         if (!vmm_exclusive)
6010                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6011         loaded_vmcs_init(vmx->loaded_vmcs);
6012         if (!vmm_exclusive)
6013                 kvm_cpu_vmxoff();
6014
6015         cpu = get_cpu();
6016         vmx_vcpu_load(&vmx->vcpu, cpu);
6017         vmx->vcpu.cpu = cpu;
6018         err = vmx_vcpu_setup(vmx);
6019         vmx_vcpu_put(&vmx->vcpu);
6020         put_cpu();
6021         if (err)
6022                 goto free_vmcs;
6023         if (vm_need_virtualize_apic_accesses(kvm))
6024                 err = alloc_apic_access_page(kvm);
6025                 if (err)
6026                         goto free_vmcs;
6027
6028         if (enable_ept) {
6029                 if (!kvm->arch.ept_identity_map_addr)
6030                         kvm->arch.ept_identity_map_addr =
6031                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
6032                 err = -ENOMEM;
6033                 if (alloc_identity_pagetable(kvm) != 0)
6034                         goto free_vmcs;
6035                 if (!init_rmode_identity_map(kvm))
6036                         goto free_vmcs;
6037         }
6038
6039         vmx->nested.current_vmptr = -1ull;
6040         vmx->nested.current_vmcs12 = NULL;
6041
6042         return &vmx->vcpu;
6043
6044 free_vmcs:
6045         free_vmcs(vmx->loaded_vmcs->vmcs);
6046 free_msrs:
6047         kfree(vmx->guest_msrs);
6048 uninit_vcpu:
6049         kvm_vcpu_uninit(&vmx->vcpu);
6050 free_vcpu:
6051         free_vpid(vmx);
6052         kmem_cache_free(kvm_vcpu_cache, vmx);
6053         return ERR_PTR(err);
6054 }
6055
6056 static void __init vmx_check_processor_compat(void *rtn)
6057 {
6058         struct vmcs_config vmcs_conf;
6059
6060         *(int *)rtn = 0;
6061         if (setup_vmcs_config(&vmcs_conf) < 0)
6062                 *(int *)rtn = -EIO;
6063         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6064                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6065                                 smp_processor_id());
6066                 *(int *)rtn = -EIO;
6067         }
6068 }
6069
6070 static int get_ept_level(void)
6071 {
6072         return VMX_EPT_DEFAULT_GAW + 1;
6073 }
6074
6075 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6076 {
6077         u64 ret;
6078
6079         /* For VT-d and EPT combination
6080          * 1. MMIO: always map as UC
6081          * 2. EPT with VT-d:
6082          *   a. VT-d without snooping control feature: can't guarantee the
6083          *      result, try to trust guest.
6084          *   b. VT-d with snooping control feature: snooping control feature of
6085          *      VT-d engine can guarantee the cache correctness. Just set it
6086          *      to WB to keep consistent with host. So the same as item 3.
6087          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6088          *    consistent with host MTRR
6089          */
6090         if (is_mmio)
6091                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
6092         else if (vcpu->kvm->arch.iommu_domain &&
6093                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6094                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6095                       VMX_EPT_MT_EPTE_SHIFT;
6096         else
6097                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
6098                         | VMX_EPT_IPAT_BIT;
6099
6100         return ret;
6101 }
6102
6103 #define _ER(x) { EXIT_REASON_##x, #x }
6104
6105 static const struct trace_print_flags vmx_exit_reasons_str[] = {
6106         _ER(EXCEPTION_NMI),
6107         _ER(EXTERNAL_INTERRUPT),
6108         _ER(TRIPLE_FAULT),
6109         _ER(PENDING_INTERRUPT),
6110         _ER(NMI_WINDOW),
6111         _ER(TASK_SWITCH),
6112         _ER(CPUID),
6113         _ER(HLT),
6114         _ER(INVLPG),
6115         _ER(RDPMC),
6116         _ER(RDTSC),
6117         _ER(VMCALL),
6118         _ER(VMCLEAR),
6119         _ER(VMLAUNCH),
6120         _ER(VMPTRLD),
6121         _ER(VMPTRST),
6122         _ER(VMREAD),
6123         _ER(VMRESUME),
6124         _ER(VMWRITE),
6125         _ER(VMOFF),
6126         _ER(VMON),
6127         _ER(CR_ACCESS),
6128         _ER(DR_ACCESS),
6129         _ER(IO_INSTRUCTION),
6130         _ER(MSR_READ),
6131         _ER(MSR_WRITE),
6132         _ER(MWAIT_INSTRUCTION),
6133         _ER(MONITOR_INSTRUCTION),
6134         _ER(PAUSE_INSTRUCTION),
6135         _ER(MCE_DURING_VMENTRY),
6136         _ER(TPR_BELOW_THRESHOLD),
6137         _ER(APIC_ACCESS),
6138         _ER(EPT_VIOLATION),
6139         _ER(EPT_MISCONFIG),
6140         _ER(WBINVD),
6141         { -1, NULL }
6142 };
6143
6144 #undef _ER
6145
6146 static int vmx_get_lpage_level(void)
6147 {
6148         if (enable_ept && !cpu_has_vmx_ept_1g_page())
6149                 return PT_DIRECTORY_LEVEL;
6150         else
6151                 /* For shadow and EPT supported 1GB page */
6152                 return PT_PDPE_LEVEL;
6153 }
6154
6155 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6156 {
6157         struct kvm_cpuid_entry2 *best;
6158         struct vcpu_vmx *vmx = to_vmx(vcpu);
6159         u32 exec_control;
6160
6161         vmx->rdtscp_enabled = false;
6162         if (vmx_rdtscp_supported()) {
6163                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6164                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6165                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6166                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6167                                 vmx->rdtscp_enabled = true;
6168                         else {
6169                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6170                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6171                                                 exec_control);
6172                         }
6173                 }
6174         }
6175 }
6176
6177 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6178 {
6179 }
6180
6181 /*
6182  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6183  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6184  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6185  * guest in a way that will both be appropriate to L1's requests, and our
6186  * needs. In addition to modifying the active vmcs (which is vmcs02), this
6187  * function also has additional necessary side-effects, like setting various
6188  * vcpu->arch fields.
6189  */
6190 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6191 {
6192         struct vcpu_vmx *vmx = to_vmx(vcpu);
6193         u32 exec_control;
6194
6195         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6196         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6197         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6198         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6199         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6200         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6201         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6202         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6203         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6204         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6205         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6206         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6207         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6208         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6209         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6210         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6211         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6212         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6213         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6214         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6215         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6216         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6217         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6218         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6219         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6220         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6221         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6222         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6223         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6224         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6225         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6226         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6227         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6228         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6229         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6230         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6231
6232         vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6233         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6234                 vmcs12->vm_entry_intr_info_field);
6235         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6236                 vmcs12->vm_entry_exception_error_code);
6237         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6238                 vmcs12->vm_entry_instruction_len);
6239         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6240                 vmcs12->guest_interruptibility_info);
6241         vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6242         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6243         vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6244         vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6245         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6246                 vmcs12->guest_pending_dbg_exceptions);
6247         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6248         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6249
6250         vmcs_write64(VMCS_LINK_POINTER, -1ull);
6251
6252         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6253                 (vmcs_config.pin_based_exec_ctrl |
6254                  vmcs12->pin_based_vm_exec_control));
6255
6256         /*
6257          * Whether page-faults are trapped is determined by a combination of
6258          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6259          * If enable_ept, L0 doesn't care about page faults and we should
6260          * set all of these to L1's desires. However, if !enable_ept, L0 does
6261          * care about (at least some) page faults, and because it is not easy
6262          * (if at all possible?) to merge L0 and L1's desires, we simply ask
6263          * to exit on each and every L2 page fault. This is done by setting
6264          * MASK=MATCH=0 and (see below) EB.PF=1.
6265          * Note that below we don't need special code to set EB.PF beyond the
6266          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6267          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6268          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6269          *
6270          * A problem with this approach (when !enable_ept) is that L1 may be
6271          * injected with more page faults than it asked for. This could have
6272          * caused problems, but in practice existing hypervisors don't care.
6273          * To fix this, we will need to emulate the PFEC checking (on the L1
6274          * page tables), using walk_addr(), when injecting PFs to L1.
6275          */
6276         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6277                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6278         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6279                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6280
6281         if (cpu_has_secondary_exec_ctrls()) {
6282                 u32 exec_control = vmx_secondary_exec_control(vmx);
6283                 if (!vmx->rdtscp_enabled)
6284                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
6285                 /* Take the following fields only from vmcs12 */
6286                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6287                 if (nested_cpu_has(vmcs12,
6288                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6289                         exec_control |= vmcs12->secondary_vm_exec_control;
6290
6291                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6292                         /*
6293                          * Translate L1 physical address to host physical
6294                          * address for vmcs02. Keep the page pinned, so this
6295                          * physical address remains valid. We keep a reference
6296                          * to it so we can release it later.
6297                          */
6298                         if (vmx->nested.apic_access_page) /* shouldn't happen */
6299                                 nested_release_page(vmx->nested.apic_access_page);
6300                         vmx->nested.apic_access_page =
6301                                 nested_get_page(vcpu, vmcs12->apic_access_addr);
6302                         /*
6303                          * If translation failed, no matter: This feature asks
6304                          * to exit when accessing the given address, and if it
6305                          * can never be accessed, this feature won't do
6306                          * anything anyway.
6307                          */
6308                         if (!vmx->nested.apic_access_page)
6309                                 exec_control &=
6310                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6311                         else
6312                                 vmcs_write64(APIC_ACCESS_ADDR,
6313                                   page_to_phys(vmx->nested.apic_access_page));
6314                 }
6315
6316                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6317         }
6318
6319
6320         /*
6321          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6322          * Some constant fields are set here by vmx_set_constant_host_state().
6323          * Other fields are different per CPU, and will be set later when
6324          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6325          */
6326         vmx_set_constant_host_state();
6327
6328         /*
6329          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6330          * entry, but only if the current (host) sp changed from the value
6331          * we wrote last (vmx->host_rsp). This cache is no longer relevant
6332          * if we switch vmcs, and rather than hold a separate cache per vmcs,
6333          * here we just force the write to happen on entry.
6334          */
6335         vmx->host_rsp = 0;
6336
6337         exec_control = vmx_exec_control(vmx); /* L0's desires */
6338         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6339         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6340         exec_control &= ~CPU_BASED_TPR_SHADOW;