KVM: VMX: mark unusable segment as nonpresent
[linux-3.10.git] / arch / x86 / kvm / vmx.c
1 /*
2  * Kernel-based Virtual Machine driver for Linux
3  *
4  * This module enables machines with Intel VT-x extensions to run virtual
5  * machines without emulation or binary translation.
6  *
7  * Copyright (C) 2006 Qumranet, Inc.
8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
9  *
10  * Authors:
11  *   Avi Kivity   <avi@qumranet.com>
12  *   Yaniv Kamay  <yaniv@qumranet.com>
13  *
14  * This work is licensed under the terms of the GNU GPL, version 2.  See
15  * the COPYING file in the top-level directory.
16  *
17  */
18
19 #include "irq.h"
20 #include "mmu.h"
21 #include "cpuid.h"
22
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/mm.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include "kvm_cache_regs.h"
35 #include "x86.h"
36
37 #include <asm/io.h>
38 #include <asm/desc.h>
39 #include <asm/vmx.h>
40 #include <asm/virtext.h>
41 #include <asm/mce.h>
42 #include <asm/i387.h>
43 #include <asm/xcr.h>
44 #include <asm/perf_event.h>
45 #include <asm/kexec.h>
46
47 #include "trace.h"
48
49 #define __ex(x) __kvm_handle_fault_on_reboot(x)
50 #define __ex_clear(x, reg) \
51         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
52
53 MODULE_AUTHOR("Qumranet");
54 MODULE_LICENSE("GPL");
55
56 static const struct x86_cpu_id vmx_cpu_id[] = {
57         X86_FEATURE_MATCH(X86_FEATURE_VMX),
58         {}
59 };
60 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
61
62 static bool __read_mostly enable_vpid = 1;
63 module_param_named(vpid, enable_vpid, bool, 0444);
64
65 static bool __read_mostly flexpriority_enabled = 1;
66 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
67
68 static bool __read_mostly enable_ept = 1;
69 module_param_named(ept, enable_ept, bool, S_IRUGO);
70
71 static bool __read_mostly enable_unrestricted_guest = 1;
72 module_param_named(unrestricted_guest,
73                         enable_unrestricted_guest, bool, S_IRUGO);
74
75 static bool __read_mostly enable_ept_ad_bits = 1;
76 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
77
78 static bool __read_mostly emulate_invalid_guest_state = true;
79 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
80
81 static bool __read_mostly vmm_exclusive = 1;
82 module_param(vmm_exclusive, bool, S_IRUGO);
83
84 static bool __read_mostly fasteoi = 1;
85 module_param(fasteoi, bool, S_IRUGO);
86
87 static bool __read_mostly enable_apicv = 1;
88 module_param(enable_apicv, bool, S_IRUGO);
89
90 static bool __read_mostly enable_shadow_vmcs = 1;
91 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
92 /*
93  * If nested=1, nested virtualization is supported, i.e., guests may use
94  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
95  * use VMX instructions.
96  */
97 static bool __read_mostly nested = 0;
98 module_param(nested, bool, S_IRUGO);
99
100 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
101 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
102 #define KVM_VM_CR0_ALWAYS_ON                                            \
103         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
104 #define KVM_CR4_GUEST_OWNED_BITS                                      \
105         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
106          | X86_CR4_OSXMMEXCPT)
107
108 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
109 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
110
111 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
112
113 /*
114  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
115  * ple_gap:    upper bound on the amount of time between two successive
116  *             executions of PAUSE in a loop. Also indicate if ple enabled.
117  *             According to test, this time is usually smaller than 128 cycles.
118  * ple_window: upper bound on the amount of time a guest is allowed to execute
119  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
120  *             less than 2^12 cycles
121  * Time is measured based on a counter that runs at the same rate as the TSC,
122  * refer SDM volume 3b section 21.6.13 & 22.1.3.
123  */
124 #define KVM_VMX_DEFAULT_PLE_GAP    128
125 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
126 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
127 module_param(ple_gap, int, S_IRUGO);
128
129 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
130 module_param(ple_window, int, S_IRUGO);
131
132 extern const ulong vmx_return;
133
134 #define NR_AUTOLOAD_MSRS 8
135 #define VMCS02_POOL_SIZE 1
136
137 struct vmcs {
138         u32 revision_id;
139         u32 abort;
140         char data[0];
141 };
142
143 /*
144  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
145  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
146  * loaded on this CPU (so we can clear them if the CPU goes down).
147  */
148 struct loaded_vmcs {
149         struct vmcs *vmcs;
150         int cpu;
151         int launched;
152         struct list_head loaded_vmcss_on_cpu_link;
153 };
154
155 struct shared_msr_entry {
156         unsigned index;
157         u64 data;
158         u64 mask;
159 };
160
161 /*
162  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
163  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
164  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
165  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
166  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
167  * More than one of these structures may exist, if L1 runs multiple L2 guests.
168  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
169  * underlying hardware which will be used to run L2.
170  * This structure is packed to ensure that its layout is identical across
171  * machines (necessary for live migration).
172  * If there are changes in this struct, VMCS12_REVISION must be changed.
173  */
174 typedef u64 natural_width;
175 struct __packed vmcs12 {
176         /* According to the Intel spec, a VMCS region must start with the
177          * following two fields. Then follow implementation-specific data.
178          */
179         u32 revision_id;
180         u32 abort;
181
182         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
183         u32 padding[7]; /* room for future expansion */
184
185         u64 io_bitmap_a;
186         u64 io_bitmap_b;
187         u64 msr_bitmap;
188         u64 vm_exit_msr_store_addr;
189         u64 vm_exit_msr_load_addr;
190         u64 vm_entry_msr_load_addr;
191         u64 tsc_offset;
192         u64 virtual_apic_page_addr;
193         u64 apic_access_addr;
194         u64 ept_pointer;
195         u64 guest_physical_address;
196         u64 vmcs_link_pointer;
197         u64 guest_ia32_debugctl;
198         u64 guest_ia32_pat;
199         u64 guest_ia32_efer;
200         u64 guest_ia32_perf_global_ctrl;
201         u64 guest_pdptr0;
202         u64 guest_pdptr1;
203         u64 guest_pdptr2;
204         u64 guest_pdptr3;
205         u64 host_ia32_pat;
206         u64 host_ia32_efer;
207         u64 host_ia32_perf_global_ctrl;
208         u64 padding64[8]; /* room for future expansion */
209         /*
210          * To allow migration of L1 (complete with its L2 guests) between
211          * machines of different natural widths (32 or 64 bit), we cannot have
212          * unsigned long fields with no explict size. We use u64 (aliased
213          * natural_width) instead. Luckily, x86 is little-endian.
214          */
215         natural_width cr0_guest_host_mask;
216         natural_width cr4_guest_host_mask;
217         natural_width cr0_read_shadow;
218         natural_width cr4_read_shadow;
219         natural_width cr3_target_value0;
220         natural_width cr3_target_value1;
221         natural_width cr3_target_value2;
222         natural_width cr3_target_value3;
223         natural_width exit_qualification;
224         natural_width guest_linear_address;
225         natural_width guest_cr0;
226         natural_width guest_cr3;
227         natural_width guest_cr4;
228         natural_width guest_es_base;
229         natural_width guest_cs_base;
230         natural_width guest_ss_base;
231         natural_width guest_ds_base;
232         natural_width guest_fs_base;
233         natural_width guest_gs_base;
234         natural_width guest_ldtr_base;
235         natural_width guest_tr_base;
236         natural_width guest_gdtr_base;
237         natural_width guest_idtr_base;
238         natural_width guest_dr7;
239         natural_width guest_rsp;
240         natural_width guest_rip;
241         natural_width guest_rflags;
242         natural_width guest_pending_dbg_exceptions;
243         natural_width guest_sysenter_esp;
244         natural_width guest_sysenter_eip;
245         natural_width host_cr0;
246         natural_width host_cr3;
247         natural_width host_cr4;
248         natural_width host_fs_base;
249         natural_width host_gs_base;
250         natural_width host_tr_base;
251         natural_width host_gdtr_base;
252         natural_width host_idtr_base;
253         natural_width host_ia32_sysenter_esp;
254         natural_width host_ia32_sysenter_eip;
255         natural_width host_rsp;
256         natural_width host_rip;
257         natural_width paddingl[8]; /* room for future expansion */
258         u32 pin_based_vm_exec_control;
259         u32 cpu_based_vm_exec_control;
260         u32 exception_bitmap;
261         u32 page_fault_error_code_mask;
262         u32 page_fault_error_code_match;
263         u32 cr3_target_count;
264         u32 vm_exit_controls;
265         u32 vm_exit_msr_store_count;
266         u32 vm_exit_msr_load_count;
267         u32 vm_entry_controls;
268         u32 vm_entry_msr_load_count;
269         u32 vm_entry_intr_info_field;
270         u32 vm_entry_exception_error_code;
271         u32 vm_entry_instruction_len;
272         u32 tpr_threshold;
273         u32 secondary_vm_exec_control;
274         u32 vm_instruction_error;
275         u32 vm_exit_reason;
276         u32 vm_exit_intr_info;
277         u32 vm_exit_intr_error_code;
278         u32 idt_vectoring_info_field;
279         u32 idt_vectoring_error_code;
280         u32 vm_exit_instruction_len;
281         u32 vmx_instruction_info;
282         u32 guest_es_limit;
283         u32 guest_cs_limit;
284         u32 guest_ss_limit;
285         u32 guest_ds_limit;
286         u32 guest_fs_limit;
287         u32 guest_gs_limit;
288         u32 guest_ldtr_limit;
289         u32 guest_tr_limit;
290         u32 guest_gdtr_limit;
291         u32 guest_idtr_limit;
292         u32 guest_es_ar_bytes;
293         u32 guest_cs_ar_bytes;
294         u32 guest_ss_ar_bytes;
295         u32 guest_ds_ar_bytes;
296         u32 guest_fs_ar_bytes;
297         u32 guest_gs_ar_bytes;
298         u32 guest_ldtr_ar_bytes;
299         u32 guest_tr_ar_bytes;
300         u32 guest_interruptibility_info;
301         u32 guest_activity_state;
302         u32 guest_sysenter_cs;
303         u32 host_ia32_sysenter_cs;
304         u32 vmx_preemption_timer_value;
305         u32 padding32[7]; /* room for future expansion */
306         u16 virtual_processor_id;
307         u16 guest_es_selector;
308         u16 guest_cs_selector;
309         u16 guest_ss_selector;
310         u16 guest_ds_selector;
311         u16 guest_fs_selector;
312         u16 guest_gs_selector;
313         u16 guest_ldtr_selector;
314         u16 guest_tr_selector;
315         u16 host_es_selector;
316         u16 host_cs_selector;
317         u16 host_ss_selector;
318         u16 host_ds_selector;
319         u16 host_fs_selector;
320         u16 host_gs_selector;
321         u16 host_tr_selector;
322 };
323
324 /*
325  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
326  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
327  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
328  */
329 #define VMCS12_REVISION 0x11e57ed0
330
331 /*
332  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
333  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
334  * current implementation, 4K are reserved to avoid future complications.
335  */
336 #define VMCS12_SIZE 0x1000
337
338 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
339 struct vmcs02_list {
340         struct list_head list;
341         gpa_t vmptr;
342         struct loaded_vmcs vmcs02;
343 };
344
345 /*
346  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
347  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
348  */
349 struct nested_vmx {
350         /* Has the level1 guest done vmxon? */
351         bool vmxon;
352
353         /* The guest-physical address of the current VMCS L1 keeps for L2 */
354         gpa_t current_vmptr;
355         /* The host-usable pointer to the above */
356         struct page *current_vmcs12_page;
357         struct vmcs12 *current_vmcs12;
358         struct vmcs *current_shadow_vmcs;
359         /*
360          * Indicates if the shadow vmcs must be updated with the
361          * data hold by vmcs12
362          */
363         bool sync_shadow_vmcs;
364
365         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
366         struct list_head vmcs02_pool;
367         int vmcs02_num;
368         u64 vmcs01_tsc_offset;
369         /* L2 must run next, and mustn't decide to exit to L1. */
370         bool nested_run_pending;
371         /*
372          * Guest pages referred to in vmcs02 with host-physical pointers, so
373          * we must keep them pinned while L2 runs.
374          */
375         struct page *apic_access_page;
376 };
377
378 #define POSTED_INTR_ON  0
379 /* Posted-Interrupt Descriptor */
380 struct pi_desc {
381         u32 pir[8];     /* Posted interrupt requested */
382         u32 control;    /* bit 0 of control is outstanding notification bit */
383         u32 rsvd[7];
384 } __aligned(64);
385
386 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
387 {
388         return test_and_set_bit(POSTED_INTR_ON,
389                         (unsigned long *)&pi_desc->control);
390 }
391
392 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
393 {
394         return test_and_clear_bit(POSTED_INTR_ON,
395                         (unsigned long *)&pi_desc->control);
396 }
397
398 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
399 {
400         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
401 }
402
403 struct vcpu_vmx {
404         struct kvm_vcpu       vcpu;
405         unsigned long         host_rsp;
406         u8                    fail;
407         u8                    cpl;
408         bool                  nmi_known_unmasked;
409         u32                   exit_intr_info;
410         u32                   idt_vectoring_info;
411         ulong                 rflags;
412         struct shared_msr_entry *guest_msrs;
413         int                   nmsrs;
414         int                   save_nmsrs;
415         unsigned long         host_idt_base;
416 #ifdef CONFIG_X86_64
417         u64                   msr_host_kernel_gs_base;
418         u64                   msr_guest_kernel_gs_base;
419 #endif
420         /*
421          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
422          * non-nested (L1) guest, it always points to vmcs01. For a nested
423          * guest (L2), it points to a different VMCS.
424          */
425         struct loaded_vmcs    vmcs01;
426         struct loaded_vmcs   *loaded_vmcs;
427         bool                  __launched; /* temporary, used in vmx_vcpu_run */
428         struct msr_autoload {
429                 unsigned nr;
430                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
431                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
432         } msr_autoload;
433         struct {
434                 int           loaded;
435                 u16           fs_sel, gs_sel, ldt_sel;
436 #ifdef CONFIG_X86_64
437                 u16           ds_sel, es_sel;
438 #endif
439                 int           gs_ldt_reload_needed;
440                 int           fs_reload_needed;
441         } host_state;
442         struct {
443                 int vm86_active;
444                 ulong save_rflags;
445                 struct kvm_segment segs[8];
446         } rmode;
447         struct {
448                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
449                 struct kvm_save_segment {
450                         u16 selector;
451                         unsigned long base;
452                         u32 limit;
453                         u32 ar;
454                 } seg[8];
455         } segment_cache;
456         int vpid;
457         bool emulation_required;
458
459         /* Support for vnmi-less CPUs */
460         int soft_vnmi_blocked;
461         ktime_t entry_time;
462         s64 vnmi_blocked_time;
463         u32 exit_reason;
464
465         bool rdtscp_enabled;
466
467         /* Posted interrupt descriptor */
468         struct pi_desc pi_desc;
469
470         /* Support for a guest hypervisor (nested VMX) */
471         struct nested_vmx nested;
472 };
473
474 enum segment_cache_field {
475         SEG_FIELD_SEL = 0,
476         SEG_FIELD_BASE = 1,
477         SEG_FIELD_LIMIT = 2,
478         SEG_FIELD_AR = 3,
479
480         SEG_FIELD_NR = 4
481 };
482
483 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
484 {
485         return container_of(vcpu, struct vcpu_vmx, vcpu);
486 }
487
488 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
489 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
490 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
491                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
492
493
494 static const unsigned long shadow_read_only_fields[] = {
495         /*
496          * We do NOT shadow fields that are modified when L0
497          * traps and emulates any vmx instruction (e.g. VMPTRLD,
498          * VMXON...) executed by L1.
499          * For example, VM_INSTRUCTION_ERROR is read
500          * by L1 if a vmx instruction fails (part of the error path).
501          * Note the code assumes this logic. If for some reason
502          * we start shadowing these fields then we need to
503          * force a shadow sync when L0 emulates vmx instructions
504          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
505          * by nested_vmx_failValid)
506          */
507         VM_EXIT_REASON,
508         VM_EXIT_INTR_INFO,
509         VM_EXIT_INSTRUCTION_LEN,
510         IDT_VECTORING_INFO_FIELD,
511         IDT_VECTORING_ERROR_CODE,
512         VM_EXIT_INTR_ERROR_CODE,
513         EXIT_QUALIFICATION,
514         GUEST_LINEAR_ADDRESS,
515         GUEST_PHYSICAL_ADDRESS
516 };
517 static const int max_shadow_read_only_fields =
518         ARRAY_SIZE(shadow_read_only_fields);
519
520 static const unsigned long shadow_read_write_fields[] = {
521         GUEST_RIP,
522         GUEST_RSP,
523         GUEST_CR0,
524         GUEST_CR3,
525         GUEST_CR4,
526         GUEST_INTERRUPTIBILITY_INFO,
527         GUEST_RFLAGS,
528         GUEST_CS_SELECTOR,
529         GUEST_CS_AR_BYTES,
530         GUEST_CS_LIMIT,
531         GUEST_CS_BASE,
532         GUEST_ES_BASE,
533         CR0_GUEST_HOST_MASK,
534         CR0_READ_SHADOW,
535         CR4_READ_SHADOW,
536         TSC_OFFSET,
537         EXCEPTION_BITMAP,
538         CPU_BASED_VM_EXEC_CONTROL,
539         VM_ENTRY_EXCEPTION_ERROR_CODE,
540         VM_ENTRY_INTR_INFO_FIELD,
541         VM_ENTRY_INSTRUCTION_LEN,
542         VM_ENTRY_EXCEPTION_ERROR_CODE,
543         HOST_FS_BASE,
544         HOST_GS_BASE,
545         HOST_FS_SELECTOR,
546         HOST_GS_SELECTOR
547 };
548 static const int max_shadow_read_write_fields =
549         ARRAY_SIZE(shadow_read_write_fields);
550
551 static const unsigned short vmcs_field_to_offset_table[] = {
552         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
553         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
554         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
555         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
556         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
557         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
558         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
559         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
560         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
561         FIELD(HOST_ES_SELECTOR, host_es_selector),
562         FIELD(HOST_CS_SELECTOR, host_cs_selector),
563         FIELD(HOST_SS_SELECTOR, host_ss_selector),
564         FIELD(HOST_DS_SELECTOR, host_ds_selector),
565         FIELD(HOST_FS_SELECTOR, host_fs_selector),
566         FIELD(HOST_GS_SELECTOR, host_gs_selector),
567         FIELD(HOST_TR_SELECTOR, host_tr_selector),
568         FIELD64(IO_BITMAP_A, io_bitmap_a),
569         FIELD64(IO_BITMAP_B, io_bitmap_b),
570         FIELD64(MSR_BITMAP, msr_bitmap),
571         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
572         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
573         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
574         FIELD64(TSC_OFFSET, tsc_offset),
575         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
576         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
577         FIELD64(EPT_POINTER, ept_pointer),
578         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
579         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
580         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
581         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
582         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
583         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
584         FIELD64(GUEST_PDPTR0, guest_pdptr0),
585         FIELD64(GUEST_PDPTR1, guest_pdptr1),
586         FIELD64(GUEST_PDPTR2, guest_pdptr2),
587         FIELD64(GUEST_PDPTR3, guest_pdptr3),
588         FIELD64(HOST_IA32_PAT, host_ia32_pat),
589         FIELD64(HOST_IA32_EFER, host_ia32_efer),
590         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
591         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
592         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
593         FIELD(EXCEPTION_BITMAP, exception_bitmap),
594         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
595         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
596         FIELD(CR3_TARGET_COUNT, cr3_target_count),
597         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
598         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
599         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
600         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
601         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
602         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
603         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
604         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
605         FIELD(TPR_THRESHOLD, tpr_threshold),
606         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
607         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
608         FIELD(VM_EXIT_REASON, vm_exit_reason),
609         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
610         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
611         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
612         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
613         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
614         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
615         FIELD(GUEST_ES_LIMIT, guest_es_limit),
616         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
617         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
618         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
619         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
620         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
621         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
622         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
623         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
624         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
625         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
626         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
627         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
628         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
629         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
630         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
631         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
632         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
633         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
634         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
635         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
636         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
637         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
638         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
639         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
640         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
641         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
642         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
643         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
644         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
645         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
646         FIELD(EXIT_QUALIFICATION, exit_qualification),
647         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
648         FIELD(GUEST_CR0, guest_cr0),
649         FIELD(GUEST_CR3, guest_cr3),
650         FIELD(GUEST_CR4, guest_cr4),
651         FIELD(GUEST_ES_BASE, guest_es_base),
652         FIELD(GUEST_CS_BASE, guest_cs_base),
653         FIELD(GUEST_SS_BASE, guest_ss_base),
654         FIELD(GUEST_DS_BASE, guest_ds_base),
655         FIELD(GUEST_FS_BASE, guest_fs_base),
656         FIELD(GUEST_GS_BASE, guest_gs_base),
657         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
658         FIELD(GUEST_TR_BASE, guest_tr_base),
659         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
660         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
661         FIELD(GUEST_DR7, guest_dr7),
662         FIELD(GUEST_RSP, guest_rsp),
663         FIELD(GUEST_RIP, guest_rip),
664         FIELD(GUEST_RFLAGS, guest_rflags),
665         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
666         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
667         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
668         FIELD(HOST_CR0, host_cr0),
669         FIELD(HOST_CR3, host_cr3),
670         FIELD(HOST_CR4, host_cr4),
671         FIELD(HOST_FS_BASE, host_fs_base),
672         FIELD(HOST_GS_BASE, host_gs_base),
673         FIELD(HOST_TR_BASE, host_tr_base),
674         FIELD(HOST_GDTR_BASE, host_gdtr_base),
675         FIELD(HOST_IDTR_BASE, host_idtr_base),
676         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
677         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
678         FIELD(HOST_RSP, host_rsp),
679         FIELD(HOST_RIP, host_rip),
680 };
681 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
682
683 static inline short vmcs_field_to_offset(unsigned long field)
684 {
685         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
686                 return -1;
687         return vmcs_field_to_offset_table[field];
688 }
689
690 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
691 {
692         return to_vmx(vcpu)->nested.current_vmcs12;
693 }
694
695 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
696 {
697         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
698         if (is_error_page(page))
699                 return NULL;
700
701         return page;
702 }
703
704 static void nested_release_page(struct page *page)
705 {
706         kvm_release_page_dirty(page);
707 }
708
709 static void nested_release_page_clean(struct page *page)
710 {
711         kvm_release_page_clean(page);
712 }
713
714 static u64 construct_eptp(unsigned long root_hpa);
715 static void kvm_cpu_vmxon(u64 addr);
716 static void kvm_cpu_vmxoff(void);
717 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
718 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
719 static void vmx_set_segment(struct kvm_vcpu *vcpu,
720                             struct kvm_segment *var, int seg);
721 static void vmx_get_segment(struct kvm_vcpu *vcpu,
722                             struct kvm_segment *var, int seg);
723 static bool guest_state_valid(struct kvm_vcpu *vcpu);
724 static u32 vmx_segment_access_rights(struct kvm_segment *var);
725 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
726 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
727 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
728
729 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
730 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
731 /*
732  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
733  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
734  */
735 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
736 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
737
738 static unsigned long *vmx_io_bitmap_a;
739 static unsigned long *vmx_io_bitmap_b;
740 static unsigned long *vmx_msr_bitmap_legacy;
741 static unsigned long *vmx_msr_bitmap_longmode;
742 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
743 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
744 static unsigned long *vmx_vmread_bitmap;
745 static unsigned long *vmx_vmwrite_bitmap;
746
747 static bool cpu_has_load_ia32_efer;
748 static bool cpu_has_load_perf_global_ctrl;
749
750 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
751 static DEFINE_SPINLOCK(vmx_vpid_lock);
752
753 static struct vmcs_config {
754         int size;
755         int order;
756         u32 revision_id;
757         u32 pin_based_exec_ctrl;
758         u32 cpu_based_exec_ctrl;
759         u32 cpu_based_2nd_exec_ctrl;
760         u32 vmexit_ctrl;
761         u32 vmentry_ctrl;
762 } vmcs_config;
763
764 static struct vmx_capability {
765         u32 ept;
766         u32 vpid;
767 } vmx_capability;
768
769 #define VMX_SEGMENT_FIELD(seg)                                  \
770         [VCPU_SREG_##seg] = {                                   \
771                 .selector = GUEST_##seg##_SELECTOR,             \
772                 .base = GUEST_##seg##_BASE,                     \
773                 .limit = GUEST_##seg##_LIMIT,                   \
774                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
775         }
776
777 static const struct kvm_vmx_segment_field {
778         unsigned selector;
779         unsigned base;
780         unsigned limit;
781         unsigned ar_bytes;
782 } kvm_vmx_segment_fields[] = {
783         VMX_SEGMENT_FIELD(CS),
784         VMX_SEGMENT_FIELD(DS),
785         VMX_SEGMENT_FIELD(ES),
786         VMX_SEGMENT_FIELD(FS),
787         VMX_SEGMENT_FIELD(GS),
788         VMX_SEGMENT_FIELD(SS),
789         VMX_SEGMENT_FIELD(TR),
790         VMX_SEGMENT_FIELD(LDTR),
791 };
792
793 static u64 host_efer;
794
795 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
796
797 /*
798  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
799  * away by decrementing the array size.
800  */
801 static const u32 vmx_msr_index[] = {
802 #ifdef CONFIG_X86_64
803         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
804 #endif
805         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
806 };
807 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
808
809 static inline bool is_page_fault(u32 intr_info)
810 {
811         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
812                              INTR_INFO_VALID_MASK)) ==
813                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
814 }
815
816 static inline bool is_no_device(u32 intr_info)
817 {
818         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
819                              INTR_INFO_VALID_MASK)) ==
820                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
821 }
822
823 static inline bool is_invalid_opcode(u32 intr_info)
824 {
825         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
826                              INTR_INFO_VALID_MASK)) ==
827                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
828 }
829
830 static inline bool is_external_interrupt(u32 intr_info)
831 {
832         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
833                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
834 }
835
836 static inline bool is_machine_check(u32 intr_info)
837 {
838         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
839                              INTR_INFO_VALID_MASK)) ==
840                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
841 }
842
843 static inline bool cpu_has_vmx_msr_bitmap(void)
844 {
845         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
846 }
847
848 static inline bool cpu_has_vmx_tpr_shadow(void)
849 {
850         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
851 }
852
853 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
854 {
855         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
856 }
857
858 static inline bool cpu_has_secondary_exec_ctrls(void)
859 {
860         return vmcs_config.cpu_based_exec_ctrl &
861                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
862 }
863
864 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
865 {
866         return vmcs_config.cpu_based_2nd_exec_ctrl &
867                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
868 }
869
870 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
871 {
872         return vmcs_config.cpu_based_2nd_exec_ctrl &
873                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
874 }
875
876 static inline bool cpu_has_vmx_apic_register_virt(void)
877 {
878         return vmcs_config.cpu_based_2nd_exec_ctrl &
879                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
880 }
881
882 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
883 {
884         return vmcs_config.cpu_based_2nd_exec_ctrl &
885                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
886 }
887
888 static inline bool cpu_has_vmx_posted_intr(void)
889 {
890         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
891 }
892
893 static inline bool cpu_has_vmx_apicv(void)
894 {
895         return cpu_has_vmx_apic_register_virt() &&
896                 cpu_has_vmx_virtual_intr_delivery() &&
897                 cpu_has_vmx_posted_intr();
898 }
899
900 static inline bool cpu_has_vmx_flexpriority(void)
901 {
902         return cpu_has_vmx_tpr_shadow() &&
903                 cpu_has_vmx_virtualize_apic_accesses();
904 }
905
906 static inline bool cpu_has_vmx_ept_execute_only(void)
907 {
908         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
909 }
910
911 static inline bool cpu_has_vmx_eptp_uncacheable(void)
912 {
913         return vmx_capability.ept & VMX_EPTP_UC_BIT;
914 }
915
916 static inline bool cpu_has_vmx_eptp_writeback(void)
917 {
918         return vmx_capability.ept & VMX_EPTP_WB_BIT;
919 }
920
921 static inline bool cpu_has_vmx_ept_2m_page(void)
922 {
923         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
924 }
925
926 static inline bool cpu_has_vmx_ept_1g_page(void)
927 {
928         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
929 }
930
931 static inline bool cpu_has_vmx_ept_4levels(void)
932 {
933         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
934 }
935
936 static inline bool cpu_has_vmx_ept_ad_bits(void)
937 {
938         return vmx_capability.ept & VMX_EPT_AD_BIT;
939 }
940
941 static inline bool cpu_has_vmx_invept_context(void)
942 {
943         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
944 }
945
946 static inline bool cpu_has_vmx_invept_global(void)
947 {
948         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
949 }
950
951 static inline bool cpu_has_vmx_invvpid_single(void)
952 {
953         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
954 }
955
956 static inline bool cpu_has_vmx_invvpid_global(void)
957 {
958         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
959 }
960
961 static inline bool cpu_has_vmx_ept(void)
962 {
963         return vmcs_config.cpu_based_2nd_exec_ctrl &
964                 SECONDARY_EXEC_ENABLE_EPT;
965 }
966
967 static inline bool cpu_has_vmx_unrestricted_guest(void)
968 {
969         return vmcs_config.cpu_based_2nd_exec_ctrl &
970                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
971 }
972
973 static inline bool cpu_has_vmx_ple(void)
974 {
975         return vmcs_config.cpu_based_2nd_exec_ctrl &
976                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
977 }
978
979 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
980 {
981         return flexpriority_enabled && irqchip_in_kernel(kvm);
982 }
983
984 static inline bool cpu_has_vmx_vpid(void)
985 {
986         return vmcs_config.cpu_based_2nd_exec_ctrl &
987                 SECONDARY_EXEC_ENABLE_VPID;
988 }
989
990 static inline bool cpu_has_vmx_rdtscp(void)
991 {
992         return vmcs_config.cpu_based_2nd_exec_ctrl &
993                 SECONDARY_EXEC_RDTSCP;
994 }
995
996 static inline bool cpu_has_vmx_invpcid(void)
997 {
998         return vmcs_config.cpu_based_2nd_exec_ctrl &
999                 SECONDARY_EXEC_ENABLE_INVPCID;
1000 }
1001
1002 static inline bool cpu_has_virtual_nmis(void)
1003 {
1004         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1005 }
1006
1007 static inline bool cpu_has_vmx_wbinvd_exit(void)
1008 {
1009         return vmcs_config.cpu_based_2nd_exec_ctrl &
1010                 SECONDARY_EXEC_WBINVD_EXITING;
1011 }
1012
1013 static inline bool cpu_has_vmx_shadow_vmcs(void)
1014 {
1015         u64 vmx_msr;
1016         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1017         /* check if the cpu supports writing r/o exit information fields */
1018         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1019                 return false;
1020
1021         return vmcs_config.cpu_based_2nd_exec_ctrl &
1022                 SECONDARY_EXEC_SHADOW_VMCS;
1023 }
1024
1025 static inline bool report_flexpriority(void)
1026 {
1027         return flexpriority_enabled;
1028 }
1029
1030 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1031 {
1032         return vmcs12->cpu_based_vm_exec_control & bit;
1033 }
1034
1035 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1036 {
1037         return (vmcs12->cpu_based_vm_exec_control &
1038                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1039                 (vmcs12->secondary_vm_exec_control & bit);
1040 }
1041
1042 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
1043         struct kvm_vcpu *vcpu)
1044 {
1045         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1046 }
1047
1048 static inline bool is_exception(u32 intr_info)
1049 {
1050         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1051                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1052 }
1053
1054 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
1055 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1056                         struct vmcs12 *vmcs12,
1057                         u32 reason, unsigned long qualification);
1058
1059 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1060 {
1061         int i;
1062
1063         for (i = 0; i < vmx->nmsrs; ++i)
1064                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1065                         return i;
1066         return -1;
1067 }
1068
1069 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1070 {
1071     struct {
1072         u64 vpid : 16;
1073         u64 rsvd : 48;
1074         u64 gva;
1075     } operand = { vpid, 0, gva };
1076
1077     asm volatile (__ex(ASM_VMX_INVVPID)
1078                   /* CF==1 or ZF==1 --> rc = -1 */
1079                   "; ja 1f ; ud2 ; 1:"
1080                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1081 }
1082
1083 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1084 {
1085         struct {
1086                 u64 eptp, gpa;
1087         } operand = {eptp, gpa};
1088
1089         asm volatile (__ex(ASM_VMX_INVEPT)
1090                         /* CF==1 or ZF==1 --> rc = -1 */
1091                         "; ja 1f ; ud2 ; 1:\n"
1092                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1093 }
1094
1095 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1096 {
1097         int i;
1098
1099         i = __find_msr_index(vmx, msr);
1100         if (i >= 0)
1101                 return &vmx->guest_msrs[i];
1102         return NULL;
1103 }
1104
1105 static void vmcs_clear(struct vmcs *vmcs)
1106 {
1107         u64 phys_addr = __pa(vmcs);
1108         u8 error;
1109
1110         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1111                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1112                       : "cc", "memory");
1113         if (error)
1114                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1115                        vmcs, phys_addr);
1116 }
1117
1118 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1119 {
1120         vmcs_clear(loaded_vmcs->vmcs);
1121         loaded_vmcs->cpu = -1;
1122         loaded_vmcs->launched = 0;
1123 }
1124
1125 static void vmcs_load(struct vmcs *vmcs)
1126 {
1127         u64 phys_addr = __pa(vmcs);
1128         u8 error;
1129
1130         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1131                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1132                         : "cc", "memory");
1133         if (error)
1134                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1135                        vmcs, phys_addr);
1136 }
1137
1138 #ifdef CONFIG_KEXEC
1139 /*
1140  * This bitmap is used to indicate whether the vmclear
1141  * operation is enabled on all cpus. All disabled by
1142  * default.
1143  */
1144 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1145
1146 static inline void crash_enable_local_vmclear(int cpu)
1147 {
1148         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1149 }
1150
1151 static inline void crash_disable_local_vmclear(int cpu)
1152 {
1153         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1154 }
1155
1156 static inline int crash_local_vmclear_enabled(int cpu)
1157 {
1158         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1159 }
1160
1161 static void crash_vmclear_local_loaded_vmcss(void)
1162 {
1163         int cpu = raw_smp_processor_id();
1164         struct loaded_vmcs *v;
1165
1166         if (!crash_local_vmclear_enabled(cpu))
1167                 return;
1168
1169         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1170                             loaded_vmcss_on_cpu_link)
1171                 vmcs_clear(v->vmcs);
1172 }
1173 #else
1174 static inline void crash_enable_local_vmclear(int cpu) { }
1175 static inline void crash_disable_local_vmclear(int cpu) { }
1176 #endif /* CONFIG_KEXEC */
1177
1178 static void __loaded_vmcs_clear(void *arg)
1179 {
1180         struct loaded_vmcs *loaded_vmcs = arg;
1181         int cpu = raw_smp_processor_id();
1182
1183         if (loaded_vmcs->cpu != cpu)
1184                 return; /* vcpu migration can race with cpu offline */
1185         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1186                 per_cpu(current_vmcs, cpu) = NULL;
1187         crash_disable_local_vmclear(cpu);
1188         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1189
1190         /*
1191          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1192          * is before setting loaded_vmcs->vcpu to -1 which is done in
1193          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1194          * then adds the vmcs into percpu list before it is deleted.
1195          */
1196         smp_wmb();
1197
1198         loaded_vmcs_init(loaded_vmcs);
1199         crash_enable_local_vmclear(cpu);
1200 }
1201
1202 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1203 {
1204         int cpu = loaded_vmcs->cpu;
1205
1206         if (cpu != -1)
1207                 smp_call_function_single(cpu,
1208                          __loaded_vmcs_clear, loaded_vmcs, 1);
1209 }
1210
1211 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1212 {
1213         if (vmx->vpid == 0)
1214                 return;
1215
1216         if (cpu_has_vmx_invvpid_single())
1217                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1218 }
1219
1220 static inline void vpid_sync_vcpu_global(void)
1221 {
1222         if (cpu_has_vmx_invvpid_global())
1223                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1224 }
1225
1226 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1227 {
1228         if (cpu_has_vmx_invvpid_single())
1229                 vpid_sync_vcpu_single(vmx);
1230         else
1231                 vpid_sync_vcpu_global();
1232 }
1233
1234 static inline void ept_sync_global(void)
1235 {
1236         if (cpu_has_vmx_invept_global())
1237                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1238 }
1239
1240 static inline void ept_sync_context(u64 eptp)
1241 {
1242         if (enable_ept) {
1243                 if (cpu_has_vmx_invept_context())
1244                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1245                 else
1246                         ept_sync_global();
1247         }
1248 }
1249
1250 static __always_inline unsigned long vmcs_readl(unsigned long field)
1251 {
1252         unsigned long value;
1253
1254         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1255                       : "=a"(value) : "d"(field) : "cc");
1256         return value;
1257 }
1258
1259 static __always_inline u16 vmcs_read16(unsigned long field)
1260 {
1261         return vmcs_readl(field);
1262 }
1263
1264 static __always_inline u32 vmcs_read32(unsigned long field)
1265 {
1266         return vmcs_readl(field);
1267 }
1268
1269 static __always_inline u64 vmcs_read64(unsigned long field)
1270 {
1271 #ifdef CONFIG_X86_64
1272         return vmcs_readl(field);
1273 #else
1274         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1275 #endif
1276 }
1277
1278 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1279 {
1280         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1281                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1282         dump_stack();
1283 }
1284
1285 static void vmcs_writel(unsigned long field, unsigned long value)
1286 {
1287         u8 error;
1288
1289         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1290                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1291         if (unlikely(error))
1292                 vmwrite_error(field, value);
1293 }
1294
1295 static void vmcs_write16(unsigned long field, u16 value)
1296 {
1297         vmcs_writel(field, value);
1298 }
1299
1300 static void vmcs_write32(unsigned long field, u32 value)
1301 {
1302         vmcs_writel(field, value);
1303 }
1304
1305 static void vmcs_write64(unsigned long field, u64 value)
1306 {
1307         vmcs_writel(field, value);
1308 #ifndef CONFIG_X86_64
1309         asm volatile ("");
1310         vmcs_writel(field+1, value >> 32);
1311 #endif
1312 }
1313
1314 static void vmcs_clear_bits(unsigned long field, u32 mask)
1315 {
1316         vmcs_writel(field, vmcs_readl(field) & ~mask);
1317 }
1318
1319 static void vmcs_set_bits(unsigned long field, u32 mask)
1320 {
1321         vmcs_writel(field, vmcs_readl(field) | mask);
1322 }
1323
1324 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1325 {
1326         vmx->segment_cache.bitmask = 0;
1327 }
1328
1329 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1330                                        unsigned field)
1331 {
1332         bool ret;
1333         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1334
1335         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1336                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1337                 vmx->segment_cache.bitmask = 0;
1338         }
1339         ret = vmx->segment_cache.bitmask & mask;
1340         vmx->segment_cache.bitmask |= mask;
1341         return ret;
1342 }
1343
1344 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1345 {
1346         u16 *p = &vmx->segment_cache.seg[seg].selector;
1347
1348         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1349                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1350         return *p;
1351 }
1352
1353 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1354 {
1355         ulong *p = &vmx->segment_cache.seg[seg].base;
1356
1357         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1358                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1359         return *p;
1360 }
1361
1362 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1363 {
1364         u32 *p = &vmx->segment_cache.seg[seg].limit;
1365
1366         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1367                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1368         return *p;
1369 }
1370
1371 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1372 {
1373         u32 *p = &vmx->segment_cache.seg[seg].ar;
1374
1375         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1376                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1377         return *p;
1378 }
1379
1380 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1381 {
1382         u32 eb;
1383
1384         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1385              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1386         if ((vcpu->guest_debug &
1387              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1388             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1389                 eb |= 1u << BP_VECTOR;
1390         if (to_vmx(vcpu)->rmode.vm86_active)
1391                 eb = ~0;
1392         if (enable_ept)
1393                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1394         if (vcpu->fpu_active)
1395                 eb &= ~(1u << NM_VECTOR);
1396
1397         /* When we are running a nested L2 guest and L1 specified for it a
1398          * certain exception bitmap, we must trap the same exceptions and pass
1399          * them to L1. When running L2, we will only handle the exceptions
1400          * specified above if L1 did not want them.
1401          */
1402         if (is_guest_mode(vcpu))
1403                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1404
1405         vmcs_write32(EXCEPTION_BITMAP, eb);
1406 }
1407
1408 static void clear_atomic_switch_msr_special(unsigned long entry,
1409                 unsigned long exit)
1410 {
1411         vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1412         vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1413 }
1414
1415 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1416 {
1417         unsigned i;
1418         struct msr_autoload *m = &vmx->msr_autoload;
1419
1420         switch (msr) {
1421         case MSR_EFER:
1422                 if (cpu_has_load_ia32_efer) {
1423                         clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1424                                         VM_EXIT_LOAD_IA32_EFER);
1425                         return;
1426                 }
1427                 break;
1428         case MSR_CORE_PERF_GLOBAL_CTRL:
1429                 if (cpu_has_load_perf_global_ctrl) {
1430                         clear_atomic_switch_msr_special(
1431                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1432                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1433                         return;
1434                 }
1435                 break;
1436         }
1437
1438         for (i = 0; i < m->nr; ++i)
1439                 if (m->guest[i].index == msr)
1440                         break;
1441
1442         if (i == m->nr)
1443                 return;
1444         --m->nr;
1445         m->guest[i] = m->guest[m->nr];
1446         m->host[i] = m->host[m->nr];
1447         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1448         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1449 }
1450
1451 static void add_atomic_switch_msr_special(unsigned long entry,
1452                 unsigned long exit, unsigned long guest_val_vmcs,
1453                 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1454 {
1455         vmcs_write64(guest_val_vmcs, guest_val);
1456         vmcs_write64(host_val_vmcs, host_val);
1457         vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1458         vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1459 }
1460
1461 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1462                                   u64 guest_val, u64 host_val)
1463 {
1464         unsigned i;
1465         struct msr_autoload *m = &vmx->msr_autoload;
1466
1467         switch (msr) {
1468         case MSR_EFER:
1469                 if (cpu_has_load_ia32_efer) {
1470                         add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1471                                         VM_EXIT_LOAD_IA32_EFER,
1472                                         GUEST_IA32_EFER,
1473                                         HOST_IA32_EFER,
1474                                         guest_val, host_val);
1475                         return;
1476                 }
1477                 break;
1478         case MSR_CORE_PERF_GLOBAL_CTRL:
1479                 if (cpu_has_load_perf_global_ctrl) {
1480                         add_atomic_switch_msr_special(
1481                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1482                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1483                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1484                                         HOST_IA32_PERF_GLOBAL_CTRL,
1485                                         guest_val, host_val);
1486                         return;
1487                 }
1488                 break;
1489         }
1490
1491         for (i = 0; i < m->nr; ++i)
1492                 if (m->guest[i].index == msr)
1493                         break;
1494
1495         if (i == NR_AUTOLOAD_MSRS) {
1496                 printk_once(KERN_WARNING"Not enough mst switch entries. "
1497                                 "Can't add msr %x\n", msr);
1498                 return;
1499         } else if (i == m->nr) {
1500                 ++m->nr;
1501                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1502                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1503         }
1504
1505         m->guest[i].index = msr;
1506         m->guest[i].value = guest_val;
1507         m->host[i].index = msr;
1508         m->host[i].value = host_val;
1509 }
1510
1511 static void reload_tss(void)
1512 {
1513         /*
1514          * VT restores TR but not its size.  Useless.
1515          */
1516         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1517         struct desc_struct *descs;
1518
1519         descs = (void *)gdt->address;
1520         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1521         load_TR_desc();
1522 }
1523
1524 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1525 {
1526         u64 guest_efer;
1527         u64 ignore_bits;
1528
1529         guest_efer = vmx->vcpu.arch.efer;
1530
1531         /*
1532          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1533          * outside long mode
1534          */
1535         ignore_bits = EFER_NX | EFER_SCE;
1536 #ifdef CONFIG_X86_64
1537         ignore_bits |= EFER_LMA | EFER_LME;
1538         /* SCE is meaningful only in long mode on Intel */
1539         if (guest_efer & EFER_LMA)
1540                 ignore_bits &= ~(u64)EFER_SCE;
1541 #endif
1542         guest_efer &= ~ignore_bits;
1543         guest_efer |= host_efer & ignore_bits;
1544         vmx->guest_msrs[efer_offset].data = guest_efer;
1545         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1546
1547         clear_atomic_switch_msr(vmx, MSR_EFER);
1548         /* On ept, can't emulate nx, and must switch nx atomically */
1549         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1550                 guest_efer = vmx->vcpu.arch.efer;
1551                 if (!(guest_efer & EFER_LMA))
1552                         guest_efer &= ~EFER_LME;
1553                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1554                 return false;
1555         }
1556
1557         return true;
1558 }
1559
1560 static unsigned long segment_base(u16 selector)
1561 {
1562         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1563         struct desc_struct *d;
1564         unsigned long table_base;
1565         unsigned long v;
1566
1567         if (!(selector & ~3))
1568                 return 0;
1569
1570         table_base = gdt->address;
1571
1572         if (selector & 4) {           /* from ldt */
1573                 u16 ldt_selector = kvm_read_ldt();
1574
1575                 if (!(ldt_selector & ~3))
1576                         return 0;
1577
1578                 table_base = segment_base(ldt_selector);
1579         }
1580         d = (struct desc_struct *)(table_base + (selector & ~7));
1581         v = get_desc_base(d);
1582 #ifdef CONFIG_X86_64
1583        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1584                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1585 #endif
1586         return v;
1587 }
1588
1589 static inline unsigned long kvm_read_tr_base(void)
1590 {
1591         u16 tr;
1592         asm("str %0" : "=g"(tr));
1593         return segment_base(tr);
1594 }
1595
1596 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1597 {
1598         struct vcpu_vmx *vmx = to_vmx(vcpu);
1599         int i;
1600
1601         if (vmx->host_state.loaded)
1602                 return;
1603
1604         vmx->host_state.loaded = 1;
1605         /*
1606          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1607          * allow segment selectors with cpl > 0 or ti == 1.
1608          */
1609         vmx->host_state.ldt_sel = kvm_read_ldt();
1610         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1611         savesegment(fs, vmx->host_state.fs_sel);
1612         if (!(vmx->host_state.fs_sel & 7)) {
1613                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1614                 vmx->host_state.fs_reload_needed = 0;
1615         } else {
1616                 vmcs_write16(HOST_FS_SELECTOR, 0);
1617                 vmx->host_state.fs_reload_needed = 1;
1618         }
1619         savesegment(gs, vmx->host_state.gs_sel);
1620         if (!(vmx->host_state.gs_sel & 7))
1621                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1622         else {
1623                 vmcs_write16(HOST_GS_SELECTOR, 0);
1624                 vmx->host_state.gs_ldt_reload_needed = 1;
1625         }
1626
1627 #ifdef CONFIG_X86_64
1628         savesegment(ds, vmx->host_state.ds_sel);
1629         savesegment(es, vmx->host_state.es_sel);
1630 #endif
1631
1632 #ifdef CONFIG_X86_64
1633         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1634         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1635 #else
1636         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1637         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1638 #endif
1639
1640 #ifdef CONFIG_X86_64
1641         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1642         if (is_long_mode(&vmx->vcpu))
1643                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1644 #endif
1645         for (i = 0; i < vmx->save_nmsrs; ++i)
1646                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1647                                    vmx->guest_msrs[i].data,
1648                                    vmx->guest_msrs[i].mask);
1649 }
1650
1651 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1652 {
1653         if (!vmx->host_state.loaded)
1654                 return;
1655
1656         ++vmx->vcpu.stat.host_state_reload;
1657         vmx->host_state.loaded = 0;
1658 #ifdef CONFIG_X86_64
1659         if (is_long_mode(&vmx->vcpu))
1660                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1661 #endif
1662         if (vmx->host_state.gs_ldt_reload_needed) {
1663                 kvm_load_ldt(vmx->host_state.ldt_sel);
1664 #ifdef CONFIG_X86_64
1665                 load_gs_index(vmx->host_state.gs_sel);
1666 #else
1667                 loadsegment(gs, vmx->host_state.gs_sel);
1668 #endif
1669         }
1670         if (vmx->host_state.fs_reload_needed)
1671                 loadsegment(fs, vmx->host_state.fs_sel);
1672 #ifdef CONFIG_X86_64
1673         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1674                 loadsegment(ds, vmx->host_state.ds_sel);
1675                 loadsegment(es, vmx->host_state.es_sel);
1676         }
1677 #endif
1678         reload_tss();
1679 #ifdef CONFIG_X86_64
1680         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1681 #endif
1682         /*
1683          * If the FPU is not active (through the host task or
1684          * the guest vcpu), then restore the cr0.TS bit.
1685          */
1686         if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1687                 stts();
1688         load_gdt(&__get_cpu_var(host_gdt));
1689 }
1690
1691 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1692 {
1693         preempt_disable();
1694         __vmx_load_host_state(vmx);
1695         preempt_enable();
1696 }
1697
1698 /*
1699  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1700  * vcpu mutex is already taken.
1701  */
1702 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1703 {
1704         struct vcpu_vmx *vmx = to_vmx(vcpu);
1705         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1706
1707         if (!vmm_exclusive)
1708                 kvm_cpu_vmxon(phys_addr);
1709         else if (vmx->loaded_vmcs->cpu != cpu)
1710                 loaded_vmcs_clear(vmx->loaded_vmcs);
1711
1712         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1713                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1714                 vmcs_load(vmx->loaded_vmcs->vmcs);
1715         }
1716
1717         if (vmx->loaded_vmcs->cpu != cpu) {
1718                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1719                 unsigned long sysenter_esp;
1720
1721                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1722                 local_irq_disable();
1723                 crash_disable_local_vmclear(cpu);
1724
1725                 /*
1726                  * Read loaded_vmcs->cpu should be before fetching
1727                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1728                  * See the comments in __loaded_vmcs_clear().
1729                  */
1730                 smp_rmb();
1731
1732                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1733                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1734                 crash_enable_local_vmclear(cpu);
1735                 local_irq_enable();
1736
1737                 /*
1738                  * Linux uses per-cpu TSS and GDT, so set these when switching
1739                  * processors.
1740                  */
1741                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1742                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1743
1744                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1745                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1746                 vmx->loaded_vmcs->cpu = cpu;
1747         }
1748 }
1749
1750 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1751 {
1752         __vmx_load_host_state(to_vmx(vcpu));
1753         if (!vmm_exclusive) {
1754                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1755                 vcpu->cpu = -1;
1756                 kvm_cpu_vmxoff();
1757         }
1758 }
1759
1760 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1761 {
1762         ulong cr0;
1763
1764         if (vcpu->fpu_active)
1765                 return;
1766         vcpu->fpu_active = 1;
1767         cr0 = vmcs_readl(GUEST_CR0);
1768         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1769         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1770         vmcs_writel(GUEST_CR0, cr0);
1771         update_exception_bitmap(vcpu);
1772         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1773         if (is_guest_mode(vcpu))
1774                 vcpu->arch.cr0_guest_owned_bits &=
1775                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1776         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1777 }
1778
1779 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1780
1781 /*
1782  * Return the cr0 value that a nested guest would read. This is a combination
1783  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1784  * its hypervisor (cr0_read_shadow).
1785  */
1786 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1787 {
1788         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1789                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1790 }
1791 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1792 {
1793         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1794                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1795 }
1796
1797 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1798 {
1799         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1800          * set this *before* calling this function.
1801          */
1802         vmx_decache_cr0_guest_bits(vcpu);
1803         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1804         update_exception_bitmap(vcpu);
1805         vcpu->arch.cr0_guest_owned_bits = 0;
1806         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1807         if (is_guest_mode(vcpu)) {
1808                 /*
1809                  * L1's specified read shadow might not contain the TS bit,
1810                  * so now that we turned on shadowing of this bit, we need to
1811                  * set this bit of the shadow. Like in nested_vmx_run we need
1812                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1813                  * up-to-date here because we just decached cr0.TS (and we'll
1814                  * only update vmcs12->guest_cr0 on nested exit).
1815                  */
1816                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1817                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1818                         (vcpu->arch.cr0 & X86_CR0_TS);
1819                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1820         } else
1821                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1822 }
1823
1824 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1825 {
1826         unsigned long rflags, save_rflags;
1827
1828         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1829                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1830                 rflags = vmcs_readl(GUEST_RFLAGS);
1831                 if (to_vmx(vcpu)->rmode.vm86_active) {
1832                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1833                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1834                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1835                 }
1836                 to_vmx(vcpu)->rflags = rflags;
1837         }
1838         return to_vmx(vcpu)->rflags;
1839 }
1840
1841 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1842 {
1843         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1844         to_vmx(vcpu)->rflags = rflags;
1845         if (to_vmx(vcpu)->rmode.vm86_active) {
1846                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1847                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1848         }
1849         vmcs_writel(GUEST_RFLAGS, rflags);
1850 }
1851
1852 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1853 {
1854         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1855         int ret = 0;
1856
1857         if (interruptibility & GUEST_INTR_STATE_STI)
1858                 ret |= KVM_X86_SHADOW_INT_STI;
1859         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1860                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1861
1862         return ret & mask;
1863 }
1864
1865 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1866 {
1867         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1868         u32 interruptibility = interruptibility_old;
1869
1870         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1871
1872         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1873                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1874         else if (mask & KVM_X86_SHADOW_INT_STI)
1875                 interruptibility |= GUEST_INTR_STATE_STI;
1876
1877         if ((interruptibility != interruptibility_old))
1878                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1879 }
1880
1881 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1882 {
1883         unsigned long rip;
1884
1885         rip = kvm_rip_read(vcpu);
1886         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1887         kvm_rip_write(vcpu, rip);
1888
1889         /* skipping an emulated instruction also counts */
1890         vmx_set_interrupt_shadow(vcpu, 0);
1891 }
1892
1893 /*
1894  * KVM wants to inject page-faults which it got to the guest. This function
1895  * checks whether in a nested guest, we need to inject them to L1 or L2.
1896  * This function assumes it is called with the exit reason in vmcs02 being
1897  * a #PF exception (this is the only case in which KVM injects a #PF when L2
1898  * is running).
1899  */
1900 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1901 {
1902         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1903
1904         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1905         if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
1906                 return 0;
1907
1908         nested_vmx_vmexit(vcpu);
1909         return 1;
1910 }
1911
1912 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1913                                 bool has_error_code, u32 error_code,
1914                                 bool reinject)
1915 {
1916         struct vcpu_vmx *vmx = to_vmx(vcpu);
1917         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1918
1919         if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1920             !vmx->nested.nested_run_pending && nested_pf_handled(vcpu))
1921                 return;
1922
1923         if (has_error_code) {
1924                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1925                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1926         }
1927
1928         if (vmx->rmode.vm86_active) {
1929                 int inc_eip = 0;
1930                 if (kvm_exception_is_soft(nr))
1931                         inc_eip = vcpu->arch.event_exit_inst_len;
1932                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1933                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1934                 return;
1935         }
1936
1937         if (kvm_exception_is_soft(nr)) {
1938                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1939                              vmx->vcpu.arch.event_exit_inst_len);
1940                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1941         } else
1942                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1943
1944         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1945 }
1946
1947 static bool vmx_rdtscp_supported(void)
1948 {
1949         return cpu_has_vmx_rdtscp();
1950 }
1951
1952 static bool vmx_invpcid_supported(void)
1953 {
1954         return cpu_has_vmx_invpcid() && enable_ept;
1955 }
1956
1957 /*
1958  * Swap MSR entry in host/guest MSR entry array.
1959  */
1960 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1961 {
1962         struct shared_msr_entry tmp;
1963
1964         tmp = vmx->guest_msrs[to];
1965         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1966         vmx->guest_msrs[from] = tmp;
1967 }
1968
1969 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
1970 {
1971         unsigned long *msr_bitmap;
1972
1973         if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
1974                 if (is_long_mode(vcpu))
1975                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
1976                 else
1977                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
1978         } else {
1979                 if (is_long_mode(vcpu))
1980                         msr_bitmap = vmx_msr_bitmap_longmode;
1981                 else
1982                         msr_bitmap = vmx_msr_bitmap_legacy;
1983         }
1984
1985         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1986 }
1987
1988 /*
1989  * Set up the vmcs to automatically save and restore system
1990  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1991  * mode, as fiddling with msrs is very expensive.
1992  */
1993 static void setup_msrs(struct vcpu_vmx *vmx)
1994 {
1995         int save_nmsrs, index;
1996
1997         save_nmsrs = 0;
1998 #ifdef CONFIG_X86_64
1999         if (is_long_mode(&vmx->vcpu)) {
2000                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2001                 if (index >= 0)
2002                         move_msr_up(vmx, index, save_nmsrs++);
2003                 index = __find_msr_index(vmx, MSR_LSTAR);
2004                 if (index >= 0)
2005                         move_msr_up(vmx, index, save_nmsrs++);
2006                 index = __find_msr_index(vmx, MSR_CSTAR);
2007                 if (index >= 0)
2008                         move_msr_up(vmx, index, save_nmsrs++);
2009                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2010                 if (index >= 0 && vmx->rdtscp_enabled)
2011                         move_msr_up(vmx, index, save_nmsrs++);
2012                 /*
2013                  * MSR_STAR is only needed on long mode guests, and only
2014                  * if efer.sce is enabled.
2015                  */
2016                 index = __find_msr_index(vmx, MSR_STAR);
2017                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2018                         move_msr_up(vmx, index, save_nmsrs++);
2019         }
2020 #endif
2021         index = __find_msr_index(vmx, MSR_EFER);
2022         if (index >= 0 && update_transition_efer(vmx, index))
2023                 move_msr_up(vmx, index, save_nmsrs++);
2024
2025         vmx->save_nmsrs = save_nmsrs;
2026
2027         if (cpu_has_vmx_msr_bitmap())
2028                 vmx_set_msr_bitmap(&vmx->vcpu);
2029 }
2030
2031 /*
2032  * reads and returns guest's timestamp counter "register"
2033  * guest_tsc = host_tsc + tsc_offset    -- 21.3
2034  */
2035 static u64 guest_read_tsc(void)
2036 {
2037         u64 host_tsc, tsc_offset;
2038
2039         rdtscll(host_tsc);
2040         tsc_offset = vmcs_read64(TSC_OFFSET);
2041         return host_tsc + tsc_offset;
2042 }
2043
2044 /*
2045  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2046  * counter, even if a nested guest (L2) is currently running.
2047  */
2048 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2049 {
2050         u64 tsc_offset;
2051
2052         tsc_offset = is_guest_mode(vcpu) ?
2053                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2054                 vmcs_read64(TSC_OFFSET);
2055         return host_tsc + tsc_offset;
2056 }
2057
2058 /*
2059  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
2060  * software catchup for faster rates on slower CPUs.
2061  */
2062 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2063 {
2064         if (!scale)
2065                 return;
2066
2067         if (user_tsc_khz > tsc_khz) {
2068                 vcpu->arch.tsc_catchup = 1;
2069                 vcpu->arch.tsc_always_catchup = 1;
2070         } else
2071                 WARN(1, "user requested TSC rate below hardware speed\n");
2072 }
2073
2074 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2075 {
2076         return vmcs_read64(TSC_OFFSET);
2077 }
2078
2079 /*
2080  * writes 'offset' into guest's timestamp counter offset register
2081  */
2082 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2083 {
2084         if (is_guest_mode(vcpu)) {
2085                 /*
2086                  * We're here if L1 chose not to trap WRMSR to TSC. According
2087                  * to the spec, this should set L1's TSC; The offset that L1
2088                  * set for L2 remains unchanged, and still needs to be added
2089                  * to the newly set TSC to get L2's TSC.
2090                  */
2091                 struct vmcs12 *vmcs12;
2092                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2093                 /* recalculate vmcs02.TSC_OFFSET: */
2094                 vmcs12 = get_vmcs12(vcpu);
2095                 vmcs_write64(TSC_OFFSET, offset +
2096                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2097                          vmcs12->tsc_offset : 0));
2098         } else {
2099                 vmcs_write64(TSC_OFFSET, offset);
2100         }
2101 }
2102
2103 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2104 {
2105         u64 offset = vmcs_read64(TSC_OFFSET);
2106         vmcs_write64(TSC_OFFSET, offset + adjustment);
2107         if (is_guest_mode(vcpu)) {
2108                 /* Even when running L2, the adjustment needs to apply to L1 */
2109                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2110         }
2111 }
2112
2113 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2114 {
2115         return target_tsc - native_read_tsc();
2116 }
2117
2118 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2119 {
2120         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2121         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2122 }
2123
2124 /*
2125  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2126  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2127  * all guests if the "nested" module option is off, and can also be disabled
2128  * for a single guest by disabling its VMX cpuid bit.
2129  */
2130 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2131 {
2132         return nested && guest_cpuid_has_vmx(vcpu);
2133 }
2134
2135 /*
2136  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2137  * returned for the various VMX controls MSRs when nested VMX is enabled.
2138  * The same values should also be used to verify that vmcs12 control fields are
2139  * valid during nested entry from L1 to L2.
2140  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2141  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2142  * bit in the high half is on if the corresponding bit in the control field
2143  * may be on. See also vmx_control_verify().
2144  * TODO: allow these variables to be modified (downgraded) by module options
2145  * or other means.
2146  */
2147 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2148 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2149 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2150 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2151 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2152 static u32 nested_vmx_misc_low, nested_vmx_misc_high;
2153 static __init void nested_vmx_setup_ctls_msrs(void)
2154 {
2155         /*
2156          * Note that as a general rule, the high half of the MSRs (bits in
2157          * the control fields which may be 1) should be initialized by the
2158          * intersection of the underlying hardware's MSR (i.e., features which
2159          * can be supported) and the list of features we want to expose -
2160          * because they are known to be properly supported in our code.
2161          * Also, usually, the low half of the MSRs (bits which must be 1) can
2162          * be set to 0, meaning that L1 may turn off any of these bits. The
2163          * reason is that if one of these bits is necessary, it will appear
2164          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2165          * fields of vmcs01 and vmcs02, will turn these bits off - and
2166          * nested_vmx_exit_handled() will not pass related exits to L1.
2167          * These rules have exceptions below.
2168          */
2169
2170         /* pin-based controls */
2171         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2172               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
2173         /*
2174          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2175          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2176          */
2177         nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2178         nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
2179                 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
2180                 PIN_BASED_VMX_PREEMPTION_TIMER;
2181         nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2182
2183         /*
2184          * Exit controls
2185          * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2186          * 17 must be 1.
2187          */
2188         nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2189         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
2190 #ifdef CONFIG_X86_64
2191         nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
2192 #else
2193         nested_vmx_exit_ctls_high = 0;
2194 #endif
2195         nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2196
2197         /* entry controls */
2198         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2199                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2200         /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2201         nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2202         nested_vmx_entry_ctls_high &=
2203                 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
2204         nested_vmx_entry_ctls_high |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2205
2206         /* cpu-based controls */
2207         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2208                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2209         nested_vmx_procbased_ctls_low = 0;
2210         nested_vmx_procbased_ctls_high &=
2211                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2212                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2213                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2214                 CPU_BASED_CR3_STORE_EXITING |
2215 #ifdef CONFIG_X86_64
2216                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2217 #endif
2218                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2219                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2220                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2221                 CPU_BASED_PAUSE_EXITING |
2222                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2223         /*
2224          * We can allow some features even when not supported by the
2225          * hardware. For example, L1 can specify an MSR bitmap - and we
2226          * can use it to avoid exits to L1 - even when L0 runs L2
2227          * without MSR bitmaps.
2228          */
2229         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2230
2231         /* secondary cpu-based controls */
2232         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2233                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2234         nested_vmx_secondary_ctls_low = 0;
2235         nested_vmx_secondary_ctls_high &=
2236                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2237                 SECONDARY_EXEC_WBINVD_EXITING;
2238
2239         /* miscellaneous data */
2240         rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
2241         nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
2242                 VMX_MISC_SAVE_EFER_LMA;
2243         nested_vmx_misc_high = 0;
2244 }
2245
2246 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2247 {
2248         /*
2249          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2250          */
2251         return ((control & high) | low) == control;
2252 }
2253
2254 static inline u64 vmx_control_msr(u32 low, u32 high)
2255 {
2256         return low | ((u64)high << 32);
2257 }
2258
2259 /*
2260  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2261  * also let it use VMX-specific MSRs.
2262  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2263  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2264  * like all other MSRs).
2265  */
2266 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2267 {
2268         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2269                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2270                 /*
2271                  * According to the spec, processors which do not support VMX
2272                  * should throw a #GP(0) when VMX capability MSRs are read.
2273                  */
2274                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2275                 return 1;
2276         }
2277
2278         switch (msr_index) {
2279         case MSR_IA32_FEATURE_CONTROL:
2280                 *pdata = 0;
2281                 break;
2282         case MSR_IA32_VMX_BASIC:
2283                 /*
2284                  * This MSR reports some information about VMX support. We
2285                  * should return information about the VMX we emulate for the
2286                  * guest, and the VMCS structure we give it - not about the
2287                  * VMX support of the underlying hardware.
2288                  */
2289                 *pdata = VMCS12_REVISION |
2290                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2291                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2292                 break;
2293         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2294         case MSR_IA32_VMX_PINBASED_CTLS:
2295                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2296                                         nested_vmx_pinbased_ctls_high);
2297                 break;
2298         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2299         case MSR_IA32_VMX_PROCBASED_CTLS:
2300                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2301                                         nested_vmx_procbased_ctls_high);
2302                 break;
2303         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2304         case MSR_IA32_VMX_EXIT_CTLS:
2305                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2306                                         nested_vmx_exit_ctls_high);
2307                 break;
2308         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2309         case MSR_IA32_VMX_ENTRY_CTLS:
2310                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2311                                         nested_vmx_entry_ctls_high);
2312                 break;
2313         case MSR_IA32_VMX_MISC:
2314                 *pdata = vmx_control_msr(nested_vmx_misc_low,
2315                                          nested_vmx_misc_high);
2316                 break;
2317         /*
2318          * These MSRs specify bits which the guest must keep fixed (on or off)
2319          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2320          * We picked the standard core2 setting.
2321          */
2322 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2323 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2324         case MSR_IA32_VMX_CR0_FIXED0:
2325                 *pdata = VMXON_CR0_ALWAYSON;
2326                 break;
2327         case MSR_IA32_VMX_CR0_FIXED1:
2328                 *pdata = -1ULL;
2329                 break;
2330         case MSR_IA32_VMX_CR4_FIXED0:
2331                 *pdata = VMXON_CR4_ALWAYSON;
2332                 break;
2333         case MSR_IA32_VMX_CR4_FIXED1:
2334                 *pdata = -1ULL;
2335                 break;
2336         case MSR_IA32_VMX_VMCS_ENUM:
2337                 *pdata = 0x1f;
2338                 break;
2339         case MSR_IA32_VMX_PROCBASED_CTLS2:
2340                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2341                                         nested_vmx_secondary_ctls_high);
2342                 break;
2343         case MSR_IA32_VMX_EPT_VPID_CAP:
2344                 /* Currently, no nested ept or nested vpid */
2345                 *pdata = 0;
2346                 break;
2347         default:
2348                 return 0;
2349         }
2350
2351         return 1;
2352 }
2353
2354 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2355 {
2356         if (!nested_vmx_allowed(vcpu))
2357                 return 0;
2358
2359         if (msr_index == MSR_IA32_FEATURE_CONTROL)
2360                 /* TODO: the right thing. */
2361                 return 1;
2362         /*
2363          * No need to treat VMX capability MSRs specially: If we don't handle
2364          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2365          */
2366         return 0;
2367 }
2368
2369 /*
2370  * Reads an msr value (of 'msr_index') into 'pdata'.
2371  * Returns 0 on success, non-0 otherwise.
2372  * Assumes vcpu_load() was already called.
2373  */
2374 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2375 {
2376         u64 data;
2377         struct shared_msr_entry *msr;
2378
2379         if (!pdata) {
2380                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2381                 return -EINVAL;
2382         }
2383
2384         switch (msr_index) {
2385 #ifdef CONFIG_X86_64
2386         case MSR_FS_BASE:
2387                 data = vmcs_readl(GUEST_FS_BASE);
2388                 break;
2389         case MSR_GS_BASE:
2390                 data = vmcs_readl(GUEST_GS_BASE);
2391                 break;
2392         case MSR_KERNEL_GS_BASE:
2393                 vmx_load_host_state(to_vmx(vcpu));
2394                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2395                 break;
2396 #endif
2397         case MSR_EFER:
2398                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2399         case MSR_IA32_TSC:
2400                 data = guest_read_tsc();
2401                 break;
2402         case MSR_IA32_SYSENTER_CS:
2403                 data = vmcs_read32(GUEST_SYSENTER_CS);
2404                 break;
2405         case MSR_IA32_SYSENTER_EIP:
2406                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2407                 break;
2408         case MSR_IA32_SYSENTER_ESP:
2409                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2410                 break;
2411         case MSR_TSC_AUX:
2412                 if (!to_vmx(vcpu)->rdtscp_enabled)
2413                         return 1;
2414                 /* Otherwise falls through */
2415         default:
2416                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2417                         return 0;
2418                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2419                 if (msr) {
2420                         data = msr->data;
2421                         break;
2422                 }
2423                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2424         }
2425
2426         *pdata = data;
2427         return 0;
2428 }
2429
2430 /*
2431  * Writes msr value into into the appropriate "register".
2432  * Returns 0 on success, non-0 otherwise.
2433  * Assumes vcpu_load() was already called.
2434  */
2435 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2436 {
2437         struct vcpu_vmx *vmx = to_vmx(vcpu);
2438         struct shared_msr_entry *msr;
2439         int ret = 0;
2440         u32 msr_index = msr_info->index;
2441         u64 data = msr_info->data;
2442
2443         switch (msr_index) {
2444         case MSR_EFER:
2445                 ret = kvm_set_msr_common(vcpu, msr_info);
2446                 break;
2447 #ifdef CONFIG_X86_64
2448         case MSR_FS_BASE:
2449                 vmx_segment_cache_clear(vmx);
2450                 vmcs_writel(GUEST_FS_BASE, data);
2451                 break;
2452         case MSR_GS_BASE:
2453                 vmx_segment_cache_clear(vmx);
2454                 vmcs_writel(GUEST_GS_BASE, data);
2455                 break;
2456         case MSR_KERNEL_GS_BASE:
2457                 vmx_load_host_state(vmx);
2458                 vmx->msr_guest_kernel_gs_base = data;
2459                 break;
2460 #endif
2461         case MSR_IA32_SYSENTER_CS:
2462                 vmcs_write32(GUEST_SYSENTER_CS, data);
2463                 break;
2464         case MSR_IA32_SYSENTER_EIP:
2465                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2466                 break;
2467         case MSR_IA32_SYSENTER_ESP:
2468                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2469                 break;
2470         case MSR_IA32_TSC:
2471                 kvm_write_tsc(vcpu, msr_info);
2472                 break;
2473         case MSR_IA32_CR_PAT:
2474                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2475                         vmcs_write64(GUEST_IA32_PAT, data);
2476                         vcpu->arch.pat = data;
2477                         break;
2478                 }
2479                 ret = kvm_set_msr_common(vcpu, msr_info);
2480                 break;
2481         case MSR_IA32_TSC_ADJUST:
2482                 ret = kvm_set_msr_common(vcpu, msr_info);
2483                 break;
2484         case MSR_TSC_AUX:
2485                 if (!vmx->rdtscp_enabled)
2486                         return 1;
2487                 /* Check reserved bit, higher 32 bits should be zero */
2488                 if ((data >> 32) != 0)
2489                         return 1;
2490                 /* Otherwise falls through */
2491         default:
2492                 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2493                         break;
2494                 msr = find_msr_entry(vmx, msr_index);
2495                 if (msr) {
2496                         msr->data = data;
2497                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2498                                 preempt_disable();
2499                                 kvm_set_shared_msr(msr->index, msr->data,
2500                                                    msr->mask);
2501                                 preempt_enable();
2502                         }
2503                         break;
2504                 }
2505                 ret = kvm_set_msr_common(vcpu, msr_info);
2506         }
2507
2508         return ret;
2509 }
2510
2511 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2512 {
2513         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2514         switch (reg) {
2515         case VCPU_REGS_RSP:
2516                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2517                 break;
2518         case VCPU_REGS_RIP:
2519                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2520                 break;
2521         case VCPU_EXREG_PDPTR:
2522                 if (enable_ept)
2523                         ept_save_pdptrs(vcpu);
2524                 break;
2525         default:
2526                 break;
2527         }
2528 }
2529
2530 static __init int cpu_has_kvm_support(void)
2531 {
2532         return cpu_has_vmx();
2533 }
2534
2535 static __init int vmx_disabled_by_bios(void)
2536 {
2537         u64 msr;
2538
2539         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2540         if (msr & FEATURE_CONTROL_LOCKED) {
2541                 /* launched w/ TXT and VMX disabled */
2542                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2543                         && tboot_enabled())
2544                         return 1;
2545                 /* launched w/o TXT and VMX only enabled w/ TXT */
2546                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2547                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2548                         && !tboot_enabled()) {
2549                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2550                                 "activate TXT before enabling KVM\n");
2551                         return 1;
2552                 }
2553                 /* launched w/o TXT and VMX disabled */
2554                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2555                         && !tboot_enabled())
2556                         return 1;
2557         }
2558
2559         return 0;
2560 }
2561
2562 static void kvm_cpu_vmxon(u64 addr)
2563 {
2564         asm volatile (ASM_VMX_VMXON_RAX
2565                         : : "a"(&addr), "m"(addr)
2566                         : "memory", "cc");
2567 }
2568
2569 static int hardware_enable(void *garbage)
2570 {
2571         int cpu = raw_smp_processor_id();
2572         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2573         u64 old, test_bits;
2574
2575         if (read_cr4() & X86_CR4_VMXE)
2576                 return -EBUSY;
2577
2578         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2579
2580         /*
2581          * Now we can enable the vmclear operation in kdump
2582          * since the loaded_vmcss_on_cpu list on this cpu
2583          * has been initialized.
2584          *
2585          * Though the cpu is not in VMX operation now, there
2586          * is no problem to enable the vmclear operation
2587          * for the loaded_vmcss_on_cpu list is empty!
2588          */
2589         crash_enable_local_vmclear(cpu);
2590
2591         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2592
2593         test_bits = FEATURE_CONTROL_LOCKED;
2594         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2595         if (tboot_enabled())
2596                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2597
2598         if ((old & test_bits) != test_bits) {
2599                 /* enable and lock */
2600                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2601         }
2602         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2603
2604         if (vmm_exclusive) {
2605                 kvm_cpu_vmxon(phys_addr);
2606                 ept_sync_global();
2607         }
2608
2609         native_store_gdt(&__get_cpu_var(host_gdt));
2610
2611         return 0;
2612 }
2613
2614 static void vmclear_local_loaded_vmcss(void)
2615 {
2616         int cpu = raw_smp_processor_id();
2617         struct loaded_vmcs *v, *n;
2618
2619         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2620                                  loaded_vmcss_on_cpu_link)
2621                 __loaded_vmcs_clear(v);
2622 }
2623
2624
2625 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2626  * tricks.
2627  */
2628 static void kvm_cpu_vmxoff(void)
2629 {
2630         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2631 }
2632
2633 static void hardware_disable(void *garbage)
2634 {
2635         if (vmm_exclusive) {
2636                 vmclear_local_loaded_vmcss();
2637                 kvm_cpu_vmxoff();
2638         }
2639         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2640 }
2641
2642 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2643                                       u32 msr, u32 *result)
2644 {
2645         u32 vmx_msr_low, vmx_msr_high;
2646         u32 ctl = ctl_min | ctl_opt;
2647
2648         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2649
2650         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2651         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2652
2653         /* Ensure minimum (required) set of control bits are supported. */
2654         if (ctl_min & ~ctl)
2655                 return -EIO;
2656
2657         *result = ctl;
2658         return 0;
2659 }
2660
2661 static __init bool allow_1_setting(u32 msr, u32 ctl)
2662 {
2663         u32 vmx_msr_low, vmx_msr_high;
2664
2665         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2666         return vmx_msr_high & ctl;
2667 }
2668
2669 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2670 {
2671         u32 vmx_msr_low, vmx_msr_high;
2672         u32 min, opt, min2, opt2;
2673         u32 _pin_based_exec_control = 0;
2674         u32 _cpu_based_exec_control = 0;
2675         u32 _cpu_based_2nd_exec_control = 0;
2676         u32 _vmexit_control = 0;
2677         u32 _vmentry_control = 0;
2678
2679         min = CPU_BASED_HLT_EXITING |
2680 #ifdef CONFIG_X86_64
2681               CPU_BASED_CR8_LOAD_EXITING |
2682               CPU_BASED_CR8_STORE_EXITING |
2683 #endif
2684               CPU_BASED_CR3_LOAD_EXITING |
2685               CPU_BASED_CR3_STORE_EXITING |
2686               CPU_BASED_USE_IO_BITMAPS |
2687               CPU_BASED_MOV_DR_EXITING |
2688               CPU_BASED_USE_TSC_OFFSETING |
2689               CPU_BASED_MWAIT_EXITING |
2690               CPU_BASED_MONITOR_EXITING |
2691               CPU_BASED_INVLPG_EXITING |
2692               CPU_BASED_RDPMC_EXITING;
2693
2694         opt = CPU_BASED_TPR_SHADOW |
2695               CPU_BASED_USE_MSR_BITMAPS |
2696               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2697         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2698                                 &_cpu_based_exec_control) < 0)
2699                 return -EIO;
2700 #ifdef CONFIG_X86_64
2701         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2702                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2703                                            ~CPU_BASED_CR8_STORE_EXITING;
2704 #endif
2705         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2706                 min2 = 0;
2707                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2708                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2709                         SECONDARY_EXEC_WBINVD_EXITING |
2710                         SECONDARY_EXEC_ENABLE_VPID |
2711                         SECONDARY_EXEC_ENABLE_EPT |
2712                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2713                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2714                         SECONDARY_EXEC_RDTSCP |
2715                         SECONDARY_EXEC_ENABLE_INVPCID |
2716                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2717                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2718                         SECONDARY_EXEC_SHADOW_VMCS;
2719                 if (adjust_vmx_controls(min2, opt2,
2720                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2721                                         &_cpu_based_2nd_exec_control) < 0)
2722                         return -EIO;
2723         }
2724 #ifndef CONFIG_X86_64
2725         if (!(_cpu_based_2nd_exec_control &
2726                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2727                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2728 #endif
2729
2730         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2731                 _cpu_based_2nd_exec_control &= ~(
2732                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2733                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2734                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2735
2736         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2737                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2738                    enabled */
2739                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2740                                              CPU_BASED_CR3_STORE_EXITING |
2741                                              CPU_BASED_INVLPG_EXITING);
2742                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2743                       vmx_capability.ept, vmx_capability.vpid);
2744         }
2745
2746         min = 0;
2747 #ifdef CONFIG_X86_64
2748         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2749 #endif
2750         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2751                 VM_EXIT_ACK_INTR_ON_EXIT;
2752         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2753                                 &_vmexit_control) < 0)
2754                 return -EIO;
2755
2756         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2757         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2758         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2759                                 &_pin_based_exec_control) < 0)
2760                 return -EIO;
2761
2762         if (!(_cpu_based_2nd_exec_control &
2763                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2764                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2765                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2766
2767         min = 0;
2768         opt = VM_ENTRY_LOAD_IA32_PAT;
2769         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2770                                 &_vmentry_control) < 0)
2771                 return -EIO;
2772
2773         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2774
2775         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2776         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2777                 return -EIO;
2778
2779 #ifdef CONFIG_X86_64
2780         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2781         if (vmx_msr_high & (1u<<16))
2782                 return -EIO;
2783 #endif
2784
2785         /* Require Write-Back (WB) memory type for VMCS accesses. */
2786         if (((vmx_msr_high >> 18) & 15) != 6)
2787                 return -EIO;
2788
2789         vmcs_conf->size = vmx_msr_high & 0x1fff;
2790         vmcs_conf->order = get_order(vmcs_config.size);
2791         vmcs_conf->revision_id = vmx_msr_low;
2792
2793         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2794         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2795         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2796         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2797         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2798
2799         cpu_has_load_ia32_efer =
2800                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2801                                 VM_ENTRY_LOAD_IA32_EFER)
2802                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2803                                    VM_EXIT_LOAD_IA32_EFER);
2804
2805         cpu_has_load_perf_global_ctrl =
2806                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2807                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2808                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2809                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2810
2811         /*
2812          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2813          * but due to arrata below it can't be used. Workaround is to use
2814          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2815          *
2816          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2817          *
2818          * AAK155             (model 26)
2819          * AAP115             (model 30)
2820          * AAT100             (model 37)
2821          * BC86,AAY89,BD102   (model 44)
2822          * BA97               (model 46)
2823          *
2824          */
2825         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2826                 switch (boot_cpu_data.x86_model) {
2827                 case 26:
2828                 case 30:
2829                 case 37:
2830                 case 44:
2831                 case 46:
2832                         cpu_has_load_perf_global_ctrl = false;
2833                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2834                                         "does not work properly. Using workaround\n");
2835                         break;
2836                 default:
2837                         break;
2838                 }
2839         }
2840
2841         return 0;
2842 }
2843
2844 static struct vmcs *alloc_vmcs_cpu(int cpu)
2845 {
2846         int node = cpu_to_node(cpu);
2847         struct page *pages;
2848         struct vmcs *vmcs;
2849
2850         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2851         if (!pages)
2852                 return NULL;
2853         vmcs = page_address(pages);
2854         memset(vmcs, 0, vmcs_config.size);
2855         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2856         return vmcs;
2857 }
2858
2859 static struct vmcs *alloc_vmcs(void)
2860 {
2861         return alloc_vmcs_cpu(raw_smp_processor_id());
2862 }
2863
2864 static void free_vmcs(struct vmcs *vmcs)
2865 {
2866         free_pages((unsigned long)vmcs, vmcs_config.order);
2867 }
2868
2869 /*
2870  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2871  */
2872 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2873 {
2874         if (!loaded_vmcs->vmcs)
2875                 return;
2876         loaded_vmcs_clear(loaded_vmcs);
2877         free_vmcs(loaded_vmcs->vmcs);
2878         loaded_vmcs->vmcs = NULL;
2879 }
2880
2881 static void free_kvm_area(void)
2882 {
2883         int cpu;
2884
2885         for_each_possible_cpu(cpu) {
2886                 free_vmcs(per_cpu(vmxarea, cpu));
2887                 per_cpu(vmxarea, cpu) = NULL;
2888         }
2889 }
2890
2891 static __init int alloc_kvm_area(void)
2892 {
2893         int cpu;
2894
2895         for_each_possible_cpu(cpu) {
2896                 struct vmcs *vmcs;
2897
2898                 vmcs = alloc_vmcs_cpu(cpu);
2899                 if (!vmcs) {
2900                         free_kvm_area();
2901                         return -ENOMEM;
2902                 }
2903
2904                 per_cpu(vmxarea, cpu) = vmcs;
2905         }
2906         return 0;
2907 }
2908
2909 static __init int hardware_setup(void)
2910 {
2911         if (setup_vmcs_config(&vmcs_config) < 0)
2912                 return -EIO;
2913
2914         if (boot_cpu_has(X86_FEATURE_NX))
2915                 kvm_enable_efer_bits(EFER_NX);
2916
2917         if (!cpu_has_vmx_vpid())
2918                 enable_vpid = 0;
2919         if (!cpu_has_vmx_shadow_vmcs())
2920                 enable_shadow_vmcs = 0;
2921
2922         if (!cpu_has_vmx_ept() ||
2923             !cpu_has_vmx_ept_4levels()) {
2924                 enable_ept = 0;
2925                 enable_unrestricted_guest = 0;
2926                 enable_ept_ad_bits = 0;
2927         }
2928
2929         if (!cpu_has_vmx_ept_ad_bits())
2930                 enable_ept_ad_bits = 0;
2931
2932         if (!cpu_has_vmx_unrestricted_guest())
2933                 enable_unrestricted_guest = 0;
2934
2935         if (!cpu_has_vmx_flexpriority())
2936                 flexpriority_enabled = 0;
2937
2938         if (!cpu_has_vmx_tpr_shadow())
2939                 kvm_x86_ops->update_cr8_intercept = NULL;
2940
2941         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2942                 kvm_disable_largepages();
2943
2944         if (!cpu_has_vmx_ple())
2945                 ple_gap = 0;
2946
2947         if (!cpu_has_vmx_apicv())
2948                 enable_apicv = 0;
2949
2950         if (enable_apicv)
2951                 kvm_x86_ops->update_cr8_intercept = NULL;
2952         else {
2953                 kvm_x86_ops->hwapic_irr_update = NULL;
2954                 kvm_x86_ops->deliver_posted_interrupt = NULL;
2955                 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
2956         }
2957
2958         if (nested)
2959                 nested_vmx_setup_ctls_msrs();
2960
2961         return alloc_kvm_area();
2962 }
2963
2964 static __exit void hardware_unsetup(void)
2965 {
2966         free_kvm_area();
2967 }
2968
2969 static bool emulation_required(struct kvm_vcpu *vcpu)
2970 {
2971         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2972 }
2973
2974 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2975                 struct kvm_segment *save)
2976 {
2977         if (!emulate_invalid_guest_state) {
2978                 /*
2979                  * CS and SS RPL should be equal during guest entry according
2980                  * to VMX spec, but in reality it is not always so. Since vcpu
2981                  * is in the middle of the transition from real mode to
2982                  * protected mode it is safe to assume that RPL 0 is a good
2983                  * default value.
2984                  */
2985                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2986                         save->selector &= ~SELECTOR_RPL_MASK;
2987                 save->dpl = save->selector & SELECTOR_RPL_MASK;
2988                 save->s = 1;
2989         }
2990         vmx_set_segment(vcpu, save, seg);
2991 }
2992
2993 static void enter_pmode(struct kvm_vcpu *vcpu)
2994 {
2995         unsigned long flags;
2996         struct vcpu_vmx *vmx = to_vmx(vcpu);
2997
2998         /*
2999          * Update real mode segment cache. It may be not up-to-date if sement
3000          * register was written while vcpu was in a guest mode.
3001          */
3002         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3003         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3004         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3005         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3006         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3007         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3008
3009         vmx->rmode.vm86_active = 0;
3010
3011         vmx_segment_cache_clear(vmx);
3012
3013         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3014
3015         flags = vmcs_readl(GUEST_RFLAGS);
3016         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3017         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3018         vmcs_writel(GUEST_RFLAGS, flags);
3019
3020         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3021                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3022
3023         update_exception_bitmap(vcpu);
3024
3025         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3026         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3027         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3028         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3029         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3030         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3031
3032         /* CPL is always 0 when CPU enters protected mode */
3033         __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3034         vmx->cpl = 0;
3035 }
3036
3037 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3038 {
3039         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3040         struct kvm_segment var = *save;
3041
3042         var.dpl = 0x3;
3043         if (seg == VCPU_SREG_CS)
3044                 var.type = 0x3;
3045
3046         if (!emulate_invalid_guest_state) {
3047                 var.selector = var.base >> 4;
3048                 var.base = var.base & 0xffff0;
3049                 var.limit = 0xffff;
3050                 var.g = 0;
3051                 var.db = 0;
3052                 var.present = 1;
3053                 var.s = 1;
3054                 var.l = 0;
3055                 var.unusable = 0;
3056                 var.type = 0x3;
3057                 var.avl = 0;
3058                 if (save->base & 0xf)
3059                         printk_once(KERN_WARNING "kvm: segment base is not "
3060                                         "paragraph aligned when entering "
3061                                         "protected mode (seg=%d)", seg);
3062         }
3063
3064         vmcs_write16(sf->selector, var.selector);
3065         vmcs_write32(sf->base, var.base);
3066         vmcs_write32(sf->limit, var.limit);
3067         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3068 }
3069
3070 static void enter_rmode(struct kvm_vcpu *vcpu)
3071 {
3072         unsigned long flags;
3073         struct vcpu_vmx *vmx = to_vmx(vcpu);
3074
3075         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3076         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3077         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3078         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3079         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3080         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3081         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3082
3083         vmx->rmode.vm86_active = 1;
3084
3085         /*
3086          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3087          * vcpu. Warn the user that an update is overdue.
3088          */
3089         if (!vcpu->kvm->arch.tss_addr)
3090                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3091                              "called before entering vcpu\n");
3092
3093         vmx_segment_cache_clear(vmx);
3094
3095         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3096         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3097         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3098
3099         flags = vmcs_readl(GUEST_RFLAGS);
3100         vmx->rmode.save_rflags = flags;
3101
3102         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3103
3104         vmcs_writel(GUEST_RFLAGS, flags);
3105         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3106         update_exception_bitmap(vcpu);
3107
3108         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3109         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3110         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3111         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3112         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3113         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3114
3115         kvm_mmu_reset_context(vcpu);
3116 }
3117
3118 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3119 {
3120         struct vcpu_vmx *vmx = to_vmx(vcpu);
3121         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3122
3123         if (!msr)
3124                 return;
3125
3126         /*
3127          * Force kernel_gs_base reloading before EFER changes, as control
3128          * of this msr depends on is_long_mode().
3129          */
3130         vmx_load_host_state(to_vmx(vcpu));
3131         vcpu->arch.efer = efer;
3132         if (efer & EFER_LMA) {
3133                 vmcs_write32(VM_ENTRY_CONTROLS,
3134                              vmcs_read32(VM_ENTRY_CONTROLS) |
3135                              VM_ENTRY_IA32E_MODE);
3136                 msr->data = efer;
3137         } else {
3138                 vmcs_write32(VM_ENTRY_CONTROLS,
3139                              vmcs_read32(VM_ENTRY_CONTROLS) &
3140                              ~VM_ENTRY_IA32E_MODE);
3141
3142                 msr->data = efer & ~EFER_LME;
3143         }
3144         setup_msrs(vmx);
3145 }
3146
3147 #ifdef CONFIG_X86_64
3148
3149 static void enter_lmode(struct kvm_vcpu *vcpu)
3150 {
3151         u32 guest_tr_ar;
3152
3153         vmx_segment_cache_clear(to_vmx(vcpu));
3154
3155         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3156         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3157                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3158                                      __func__);
3159                 vmcs_write32(GUEST_TR_AR_BYTES,
3160                              (guest_tr_ar & ~AR_TYPE_MASK)
3161                              | AR_TYPE_BUSY_64_TSS);
3162         }
3163         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3164 }
3165
3166 static void exit_lmode(struct kvm_vcpu *vcpu)
3167 {
3168         vmcs_write32(VM_ENTRY_CONTROLS,
3169                      vmcs_read32(VM_ENTRY_CONTROLS)
3170                      & ~VM_ENTRY_IA32E_MODE);
3171         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3172 }
3173
3174 #endif
3175
3176 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3177 {
3178         vpid_sync_context(to_vmx(vcpu));
3179         if (enable_ept) {
3180                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3181                         return;
3182                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3183         }
3184 }
3185
3186 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3187 {
3188         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3189
3190         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3191         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3192 }
3193
3194 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3195 {
3196         if (enable_ept && is_paging(vcpu))
3197                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3198         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3199 }
3200
3201 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3202 {
3203         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3204
3205         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3206         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3207 }
3208
3209 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3210 {
3211         if (!test_bit(VCPU_EXREG_PDPTR,
3212                       (unsigned long *)&vcpu->arch.regs_dirty))
3213                 return;
3214
3215         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3216                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3217                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3218                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3219                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
3220         }
3221 }
3222
3223 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3224 {
3225         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3226                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3227                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3228                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3229                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3230         }
3231
3232         __set_bit(VCPU_EXREG_PDPTR,
3233                   (unsigned long *)&vcpu->arch.regs_avail);
3234         __set_bit(VCPU_EXREG_PDPTR,
3235                   (unsigned long *)&vcpu->arch.regs_dirty);
3236 }
3237
3238 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3239
3240 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3241                                         unsigned long cr0,
3242                                         struct kvm_vcpu *vcpu)
3243 {
3244         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3245                 vmx_decache_cr3(vcpu);
3246         if (!(cr0 & X86_CR0_PG)) {
3247                 /* From paging/starting to nonpaging */
3248                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3249                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3250                              (CPU_BASED_CR3_LOAD_EXITING |
3251                               CPU_BASED_CR3_STORE_EXITING));
3252                 vcpu->arch.cr0 = cr0;
3253                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3254         } else if (!is_paging(vcpu)) {
3255                 /* From nonpaging to paging */
3256                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3257                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3258                              ~(CPU_BASED_CR3_LOAD_EXITING |
3259                                CPU_BASED_CR3_STORE_EXITING));
3260                 vcpu->arch.cr0 = cr0;
3261                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3262         }
3263
3264         if (!(cr0 & X86_CR0_WP))
3265                 *hw_cr0 &= ~X86_CR0_WP;
3266 }
3267
3268 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3269 {
3270         struct vcpu_vmx *vmx = to_vmx(vcpu);
3271         unsigned long hw_cr0;
3272
3273         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3274         if (enable_unrestricted_guest)
3275                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3276         else {
3277                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3278
3279                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3280                         enter_pmode(vcpu);
3281
3282                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3283                         enter_rmode(vcpu);
3284         }
3285
3286 #ifdef CONFIG_X86_64
3287         if (vcpu->arch.efer & EFER_LME) {
3288                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3289                         enter_lmode(vcpu);
3290                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3291                         exit_lmode(vcpu);
3292         }
3293 #endif
3294
3295         if (enable_ept)
3296                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3297
3298         if (!vcpu->fpu_active)
3299                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3300
3301         vmcs_writel(CR0_READ_SHADOW, cr0);
3302         vmcs_writel(GUEST_CR0, hw_cr0);
3303         vcpu->arch.cr0 = cr0;
3304
3305         /* depends on vcpu->arch.cr0 to be set to a new value */
3306         vmx->emulation_required = emulation_required(vcpu);
3307 }
3308
3309 static u64 construct_eptp(unsigned long root_hpa)
3310 {
3311         u64 eptp;
3312
3313         /* TODO write the value reading from MSR */
3314         eptp = VMX_EPT_DEFAULT_MT |
3315                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3316         if (enable_ept_ad_bits)
3317                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3318         eptp |= (root_hpa & PAGE_MASK);
3319
3320         return eptp;
3321 }
3322
3323 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3324 {
3325         unsigned long guest_cr3;
3326         u64 eptp;
3327
3328         guest_cr3 = cr3;
3329         if (enable_ept) {
3330                 eptp = construct_eptp(cr3);
3331                 vmcs_write64(EPT_POINTER, eptp);
3332                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3333                         vcpu->kvm->arch.ept_identity_map_addr;
3334                 ept_load_pdptrs(vcpu);
3335         }
3336
3337         vmx_flush_tlb(vcpu);
3338         vmcs_writel(GUEST_CR3, guest_cr3);
3339 }
3340
3341 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3342 {
3343         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3344                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3345
3346         if (cr4 & X86_CR4_VMXE) {
3347                 /*
3348                  * To use VMXON (and later other VMX instructions), a guest
3349                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3350                  * So basically the check on whether to allow nested VMX
3351                  * is here.
3352                  */
3353                 if (!nested_vmx_allowed(vcpu))
3354                         return 1;
3355         }
3356         if (to_vmx(vcpu)->nested.vmxon &&
3357             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3358                 return 1;
3359
3360         vcpu->arch.cr4 = cr4;
3361         if (enable_ept) {
3362                 if (!is_paging(vcpu)) {
3363                         hw_cr4 &= ~X86_CR4_PAE;
3364                         hw_cr4 |= X86_CR4_PSE;
3365                         /*
3366                          * SMEP is disabled if CPU is in non-paging mode in
3367                          * hardware. However KVM always uses paging mode to
3368                          * emulate guest non-paging mode with TDP.
3369                          * To emulate this behavior, SMEP needs to be manually
3370                          * disabled when guest switches to non-paging mode.
3371                          */
3372                         hw_cr4 &= ~X86_CR4_SMEP;
3373                 } else if (!(cr4 & X86_CR4_PAE)) {
3374                         hw_cr4 &= ~X86_CR4_PAE;
3375                 }
3376         }
3377
3378         vmcs_writel(CR4_READ_SHADOW, cr4);
3379         vmcs_writel(GUEST_CR4, hw_cr4);
3380         return 0;
3381 }
3382
3383 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3384                             struct kvm_segment *var, int seg)
3385 {
3386         struct vcpu_vmx *vmx = to_vmx(vcpu);
3387         u32 ar;
3388
3389         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3390                 *var = vmx->rmode.segs[seg];
3391                 if (seg == VCPU_SREG_TR
3392                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3393                         return;
3394                 var->base = vmx_read_guest_seg_base(vmx, seg);
3395                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3396                 return;
3397         }
3398         var->base = vmx_read_guest_seg_base(vmx, seg);
3399         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3400         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3401         ar = vmx_read_guest_seg_ar(vmx, seg);
3402         var->unusable = (ar >> 16) & 1;
3403         var->type = ar & 15;
3404         var->s = (ar >> 4) & 1;
3405         var->dpl = (ar >> 5) & 3;
3406         /*
3407          * Some userspaces do not preserve unusable property. Since usable
3408          * segment has to be present according to VMX spec we can use present
3409          * property to amend userspace bug by making unusable segment always
3410          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3411          * segment as unusable.
3412          */
3413         var->present = !var->unusable;
3414         var->avl = (ar >> 12) & 1;
3415         var->l = (ar >> 13) & 1;
3416         var->db = (ar >> 14) & 1;
3417         var->g = (ar >> 15) & 1;
3418 }
3419
3420 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3421 {
3422         struct kvm_segment s;
3423
3424         if (to_vmx(vcpu)->rmode.vm86_active) {
3425                 vmx_get_segment(vcpu, &s, seg);
3426                 return s.base;
3427         }
3428         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3429 }
3430
3431 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3432 {
3433         struct vcpu_vmx *vmx = to_vmx(vcpu);
3434
3435         if (!is_protmode(vcpu))
3436                 return 0;
3437
3438         if (!is_long_mode(vcpu)
3439             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3440                 return 3;
3441
3442         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3443                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3444                 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
3445         }
3446
3447         return vmx->cpl;
3448 }
3449
3450
3451 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3452 {
3453         u32 ar;
3454
3455         if (var->unusable || !var->present)
3456                 ar = 1 << 16;
3457         else {
3458                 ar = var->type & 15;
3459                 ar |= (var->s & 1) << 4;
3460                 ar |= (var->dpl & 3) << 5;
3461                 ar |= (var->present & 1) << 7;
3462                 ar |= (var->avl & 1) << 12;
3463                 ar |= (var->l & 1) << 13;
3464                 ar |= (var->db & 1) << 14;
3465                 ar |= (var->g & 1) << 15;
3466         }
3467
3468         return ar;
3469 }
3470
3471 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3472                             struct kvm_segment *var, int seg)
3473 {
3474         struct vcpu_vmx *vmx = to_vmx(vcpu);
3475         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3476
3477         vmx_segment_cache_clear(vmx);
3478         if (seg == VCPU_SREG_CS)
3479                 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3480
3481         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3482                 vmx->rmode.segs[seg] = *var;
3483                 if (seg == VCPU_SREG_TR)
3484                         vmcs_write16(sf->selector, var->selector);
3485                 else if (var->s)
3486                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3487                 goto out;
3488         }
3489
3490         vmcs_writel(sf->base, var->base);
3491         vmcs_write32(sf->limit, var->limit);
3492         vmcs_write16(sf->selector, var->selector);
3493
3494         /*
3495          *   Fix the "Accessed" bit in AR field of segment registers for older
3496          * qemu binaries.
3497          *   IA32 arch specifies that at the time of processor reset the
3498          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3499          * is setting it to 0 in the userland code. This causes invalid guest
3500          * state vmexit when "unrestricted guest" mode is turned on.
3501          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3502          * tree. Newer qemu binaries with that qemu fix would not need this
3503          * kvm hack.
3504          */
3505         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3506                 var->type |= 0x1; /* Accessed */
3507
3508         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3509
3510 out:
3511         vmx->emulation_required |= emulation_required(vcpu);
3512 }
3513
3514 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3515 {
3516         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3517
3518         *db = (ar >> 14) & 1;
3519         *l = (ar >> 13) & 1;
3520 }
3521
3522 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3523 {
3524         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3525         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3526 }
3527
3528 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3529 {
3530         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3531         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3532 }
3533
3534 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3535 {
3536         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3537         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3538 }
3539
3540 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3541 {
3542         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3543         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3544 }
3545
3546 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3547 {
3548         struct kvm_segment var;
3549         u32 ar;
3550
3551         vmx_get_segment(vcpu, &var, seg);
3552         var.dpl = 0x3;
3553         if (seg == VCPU_SREG_CS)
3554                 var.type = 0x3;
3555         ar = vmx_segment_access_rights(&var);
3556
3557         if (var.base != (var.selector << 4))
3558                 return false;
3559         if (var.limit != 0xffff)
3560                 return false;
3561         if (ar != 0xf3)
3562                 return false;
3563
3564         return true;
3565 }
3566
3567 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3568 {
3569         struct kvm_segment cs;
3570         unsigned int cs_rpl;
3571
3572         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3573         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3574
3575         if (cs.unusable)
3576                 return false;
3577         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3578                 return false;
3579         if (!cs.s)
3580                 return false;
3581         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3582                 if (cs.dpl > cs_rpl)
3583                         return false;
3584         } else {
3585                 if (cs.dpl != cs_rpl)
3586                         return false;
3587         }
3588         if (!cs.present)
3589                 return false;
3590
3591         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3592         return true;
3593 }
3594
3595 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3596 {
3597         struct kvm_segment ss;
3598         unsigned int ss_rpl;
3599
3600         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3601         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3602
3603         if (ss.unusable)
3604                 return true;
3605         if (ss.type != 3 && ss.type != 7)
3606                 return false;
3607         if (!ss.s)
3608                 return false;
3609         if (ss.dpl != ss_rpl) /* DPL != RPL */
3610                 return false;
3611         if (!ss.present)
3612                 return false;
3613
3614         return true;
3615 }
3616
3617 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3618 {
3619         struct kvm_segment var;
3620         unsigned int rpl;
3621
3622         vmx_get_segment(vcpu, &var, seg);
3623         rpl = var.selector & SELECTOR_RPL_MASK;
3624
3625         if (var.unusable)
3626                 return true;
3627         if (!var.s)
3628                 return false;
3629         if (!var.present)
3630                 return false;
3631         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3632                 if (var.dpl < rpl) /* DPL < RPL */
3633                         return false;
3634         }
3635
3636         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3637          * rights flags
3638          */
3639         return true;
3640 }
3641
3642 static bool tr_valid(struct kvm_vcpu *vcpu)
3643 {
3644         struct kvm_segment tr;
3645
3646         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3647
3648         if (tr.unusable)
3649                 return false;
3650         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3651                 return false;
3652         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3653                 return false;
3654         if (!tr.present)
3655                 return false;
3656
3657         return true;
3658 }
3659
3660 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3661 {
3662         struct kvm_segment ldtr;
3663
3664         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3665
3666         if (ldtr.unusable)
3667                 return true;
3668         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3669                 return false;
3670         if (ldtr.type != 2)
3671                 return false;
3672         if (!ldtr.present)
3673                 return false;
3674
3675         return true;
3676 }
3677
3678 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3679 {
3680         struct kvm_segment cs, ss;
3681
3682         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3683         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3684
3685         return ((cs.selector & SELECTOR_RPL_MASK) ==
3686                  (ss.selector & SELECTOR_RPL_MASK));
3687 }
3688
3689 /*
3690  * Check if guest state is valid. Returns true if valid, false if
3691  * not.
3692  * We assume that registers are always usable
3693  */
3694 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3695 {
3696         if (enable_unrestricted_guest)
3697                 return true;
3698
3699         /* real mode guest state checks */
3700         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3701                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3702                         return false;
3703                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3704                         return false;
3705                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3706                         return false;
3707                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3708                         return false;
3709                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3710                         return false;
3711                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3712                         return false;
3713         } else {
3714         /* protected mode guest state checks */
3715                 if (!cs_ss_rpl_check(vcpu))
3716                         return false;
3717                 if (!code_segment_valid(vcpu))
3718                         return false;
3719                 if (!stack_segment_valid(vcpu))
3720                         return false;
3721                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3722                         return false;
3723                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3724                         return false;
3725                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3726                         return false;
3727                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3728                         return false;
3729                 if (!tr_valid(vcpu))
3730                         return false;
3731                 if (!ldtr_valid(vcpu))
3732                         return false;
3733         }
3734         /* TODO:
3735          * - Add checks on RIP
3736          * - Add checks on RFLAGS
3737          */
3738
3739         return true;
3740 }
3741
3742 static int init_rmode_tss(struct kvm *kvm)
3743 {
3744         gfn_t fn;
3745         u16 data = 0;
3746         int r, idx, ret = 0;
3747
3748         idx = srcu_read_lock(&kvm->srcu);
3749         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
3750         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3751         if (r < 0)
3752                 goto out;
3753         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3754         r = kvm_write_guest_page(kvm, fn++, &data,
3755                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3756         if (r < 0)
3757                 goto out;
3758         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3759         if (r < 0)
3760                 goto out;
3761         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3762         if (r < 0)
3763                 goto out;
3764         data = ~0;
3765         r = kvm_write_guest_page(kvm, fn, &data,
3766                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3767                                  sizeof(u8));
3768         if (r < 0)
3769                 goto out;
3770
3771         ret = 1;
3772 out:
3773         srcu_read_unlock(&kvm->srcu, idx);
3774         return ret;
3775 }
3776
3777 static int init_rmode_identity_map(struct kvm *kvm)
3778 {
3779         int i, idx, r, ret;
3780         pfn_t identity_map_pfn;
3781         u32 tmp;
3782
3783         if (!enable_ept)
3784                 return 1;
3785         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3786                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3787                         "haven't been allocated!\n");
3788                 return 0;
3789         }
3790         if (likely(kvm->arch.ept_identity_pagetable_done))
3791                 return 1;
3792         ret = 0;
3793         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3794         idx = srcu_read_lock(&kvm->srcu);
3795         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3796         if (r < 0)
3797                 goto out;
3798         /* Set up identity-mapping pagetable for EPT in real mode */
3799         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3800                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3801                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3802                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3803                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3804                 if (r < 0)
3805                         goto out;
3806         }
3807         kvm->arch.ept_identity_pagetable_done = true;
3808         ret = 1;
3809 out:
3810         srcu_read_unlock(&kvm->srcu, idx);
3811         return ret;
3812 }
3813
3814 static void seg_setup(int seg)
3815 {
3816         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3817         unsigned int ar;
3818
3819         vmcs_write16(sf->selector, 0);
3820         vmcs_writel(sf->base, 0);
3821         vmcs_write32(sf->limit, 0xffff);
3822         ar = 0x93;
3823         if (seg == VCPU_SREG_CS)
3824                 ar |= 0x08; /* code segment */
3825
3826         vmcs_write32(sf->ar_bytes, ar);
3827 }
3828
3829 static int alloc_apic_access_page(struct kvm *kvm)
3830 {
3831         struct page *page;
3832         struct kvm_userspace_memory_region kvm_userspace_mem;
3833         int r = 0;
3834
3835         mutex_lock(&kvm->slots_lock);
3836         if (kvm->arch.apic_access_page)
3837                 goto out;
3838         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3839         kvm_userspace_mem.flags = 0;
3840         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3841         kvm_userspace_mem.memory_size = PAGE_SIZE;
3842         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3843         if (r)
3844                 goto out;
3845
3846         page = gfn_to_page(kvm, 0xfee00);
3847         if (is_error_page(page)) {
3848                 r = -EFAULT;
3849                 goto out;
3850         }
3851
3852         kvm->arch.apic_access_page = page;
3853 out:
3854         mutex_unlock(&kvm->slots_lock);
3855         return r;
3856 }
3857
3858 static int alloc_identity_pagetable(struct kvm *kvm)
3859 {
3860         struct page *page;
3861         struct kvm_userspace_memory_region kvm_userspace_mem;
3862         int r = 0;
3863
3864         mutex_lock(&kvm->slots_lock);
3865         if (kvm->arch.ept_identity_pagetable)
3866                 goto out;
3867         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3868         kvm_userspace_mem.flags = 0;
3869         kvm_userspace_mem.guest_phys_addr =
3870                 kvm->arch.ept_identity_map_addr;
3871         kvm_userspace_mem.memory_size = PAGE_SIZE;
3872         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3873         if (r)
3874                 goto out;
3875
3876         page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3877         if (is_error_page(page)) {
3878                 r = -EFAULT;
3879                 goto out;
3880         }
3881
3882         kvm->arch.ept_identity_pagetable = page;
3883 out:
3884         mutex_unlock(&kvm->slots_lock);
3885         return r;
3886 }
3887
3888 static void allocate_vpid(struct vcpu_vmx *vmx)
3889 {
3890         int vpid;
3891
3892         vmx->vpid = 0;
3893         if (!enable_vpid)
3894                 return;
3895         spin_lock(&vmx_vpid_lock);
3896         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3897         if (vpid < VMX_NR_VPIDS) {
3898                 vmx->vpid = vpid;
3899                 __set_bit(vpid, vmx_vpid_bitmap);
3900         }
3901         spin_unlock(&vmx_vpid_lock);
3902 }
3903
3904 static void free_vpid(struct vcpu_vmx *vmx)
3905 {
3906         if (!enable_vpid)
3907                 return;
3908         spin_lock(&vmx_vpid_lock);
3909         if (vmx->vpid != 0)
3910                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3911         spin_unlock(&vmx_vpid_lock);
3912 }
3913
3914 #define MSR_TYPE_R      1
3915 #define MSR_TYPE_W      2
3916 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3917                                                 u32 msr, int type)
3918 {
3919         int f = sizeof(unsigned long);
3920
3921         if (!cpu_has_vmx_msr_bitmap())
3922                 return;
3923
3924         /*
3925          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3926          * have the write-low and read-high bitmap offsets the wrong way round.
3927          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3928          */
3929         if (msr <= 0x1fff) {
3930                 if (type & MSR_TYPE_R)
3931                         /* read-low */
3932                         __clear_bit(msr, msr_bitmap + 0x000 / f);
3933
3934                 if (type & MSR_TYPE_W)
3935                         /* write-low */
3936                         __clear_bit(msr, msr_bitmap + 0x800 / f);
3937
3938         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3939                 msr &= 0x1fff;
3940                 if (type & MSR_TYPE_R)
3941                         /* read-high */
3942                         __clear_bit(msr, msr_bitmap + 0x400 / f);
3943
3944                 if (type & MSR_TYPE_W)
3945                         /* write-high */
3946                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
3947
3948         }
3949 }
3950
3951 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3952                                                 u32 msr, int type)
3953 {
3954         int f = sizeof(unsigned long);
3955
3956         if (!cpu_has_vmx_msr_bitmap())
3957                 return;
3958
3959         /*
3960          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3961          * have the write-low and read-high bitmap offsets the wrong way round.
3962          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3963          */
3964         if (msr <= 0x1fff) {
3965                 if (type & MSR_TYPE_R)
3966                         /* read-low */
3967                         __set_bit(msr, msr_bitmap + 0x000 / f);
3968
3969                 if (type & MSR_TYPE_W)
3970                         /* write-low */
3971                         __set_bit(msr, msr_bitmap + 0x800 / f);
3972
3973         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3974                 msr &= 0x1fff;
3975                 if (type & MSR_TYPE_R)
3976                         /* read-high */
3977                         __set_bit(msr, msr_bitmap + 0x400 / f);
3978
3979                 if (type & MSR_TYPE_W)
3980                         /* write-high */
3981                         __set_bit(msr, msr_bitmap + 0xc00 / f);
3982
3983         }
3984 }
3985
3986 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3987 {
3988         if (!longmode_only)
3989                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
3990                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
3991         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
3992                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
3993 }
3994
3995 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
3996 {
3997         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3998                         msr, MSR_TYPE_R);
3999         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4000                         msr, MSR_TYPE_R);
4001 }
4002
4003 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4004 {
4005         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4006                         msr, MSR_TYPE_R);
4007         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4008                         msr, MSR_TYPE_R);
4009 }
4010
4011 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4012 {
4013         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4014                         msr, MSR_TYPE_W);
4015         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4016                         msr, MSR_TYPE_W);
4017 }
4018
4019 static int vmx_vm_has_apicv(struct kvm *kvm)
4020 {
4021         return enable_apicv && irqchip_in_kernel(kvm);
4022 }
4023
4024 /*
4025  * Send interrupt to vcpu via posted interrupt way.
4026  * 1. If target vcpu is running(non-root mode), send posted interrupt
4027  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4028  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4029  * interrupt from PIR in next vmentry.
4030  */
4031 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4032 {
4033         struct vcpu_vmx *vmx = to_vmx(vcpu);
4034         int r;
4035
4036         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4037                 return;
4038
4039         r = pi_test_and_set_on(&vmx->pi_desc);
4040         kvm_make_request(KVM_REQ_EVENT, vcpu);
4041 #ifdef CONFIG_SMP
4042         if (!r && (vcpu->mode == IN_GUEST_MODE))
4043                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4044                                 POSTED_INTR_VECTOR);
4045         else
4046 #endif
4047                 kvm_vcpu_kick(vcpu);
4048 }
4049
4050 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4051 {
4052         struct vcpu_vmx *vmx = to_vmx(vcpu);
4053
4054         if (!pi_test_and_clear_on(&vmx->pi_desc))
4055                 return;
4056
4057         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4058 }
4059
4060 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4061 {
4062         return;
4063 }
4064
4065 /*
4066  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4067  * will not change in the lifetime of the guest.
4068  * Note that host-state that does change is set elsewhere. E.g., host-state
4069  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4070  */
4071 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4072 {
4073         u32 low32, high32;
4074         unsigned long tmpl;
4075         struct desc_ptr dt;
4076
4077         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4078         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
4079         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4080
4081         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4082 #ifdef CONFIG_X86_64
4083         /*
4084          * Load null selectors, so we can avoid reloading them in
4085          * __vmx_load_host_state(), in case userspace uses the null selectors
4086          * too (the expected case).
4087          */
4088         vmcs_write16(HOST_DS_SELECTOR, 0);
4089         vmcs_write16(HOST_ES_SELECTOR, 0);
4090 #else
4091         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4092         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4093 #endif
4094         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4095         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4096
4097         native_store_idt(&dt);
4098         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4099         vmx->host_idt_base = dt.address;
4100
4101         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4102
4103         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4104         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4105         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4106         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4107
4108         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4109                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4110                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4111         }
4112 }
4113
4114 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4115 {
4116         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4117         if (enable_ept)
4118                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4119         if (is_guest_mode(&vmx->vcpu))
4120                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4121                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4122         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4123 }
4124
4125 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4126 {
4127         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4128
4129         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4130                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4131         return pin_based_exec_ctrl;
4132 }
4133
4134 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4135 {
4136         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4137         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4138                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4139 #ifdef CONFIG_X86_64
4140                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4141                                 CPU_BASED_CR8_LOAD_EXITING;
4142 #endif
4143         }
4144         if (!enable_ept)
4145                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4146                                 CPU_BASED_CR3_LOAD_EXITING  |
4147                                 CPU_BASED_INVLPG_EXITING;
4148         return exec_control;
4149 }
4150
4151 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4152 {
4153         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4154         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4155                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4156         if (vmx->vpid == 0)
4157                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4158         if (!enable_ept) {
4159                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4160                 enable_unrestricted_guest = 0;
4161                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4162                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4163         }
4164         if (!enable_unrestricted_guest)
4165                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4166         if (!ple_gap)
4167                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4168         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4169                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4170                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4171         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4172         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4173            (handle_vmptrld).
4174            We can NOT enable shadow_vmcs here because we don't have yet
4175            a current VMCS12
4176         */
4177         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4178         return exec_control;
4179 }
4180
4181 static void ept_set_mmio_spte_mask(void)
4182 {
4183         /*
4184          * EPT Misconfigurations can be generated if the value of bits 2:0
4185          * of an EPT paging-structure entry is 110b (write/execute).
4186          * Also, magic bits (0xffull << 49) is set to quickly identify mmio
4187          * spte.
4188          */
4189         kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
4190 }
4191
4192 /*
4193  * Sets up the vmcs for emulated real mode.
4194  */
4195 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4196 {
4197 #ifdef CONFIG_X86_64
4198         unsigned long a;
4199 #endif
4200         int i;
4201
4202         /* I/O */
4203         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4204         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4205
4206         if (enable_shadow_vmcs) {
4207                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4208                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4209         }
4210         if (cpu_has_vmx_msr_bitmap())
4211                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4212
4213         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4214
4215         /* Control */
4216         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4217
4218         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4219
4220         if (cpu_has_secondary_exec_ctrls()) {
4221                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4222                                 vmx_secondary_exec_control(vmx));
4223         }
4224
4225         if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
4226                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4227                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4228                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4229                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4230
4231                 vmcs_write16(GUEST_INTR_STATUS, 0);
4232
4233                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4234                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4235         }
4236
4237         if (ple_gap) {
4238                 vmcs_write32(PLE_GAP, ple_gap);
4239                 vmcs_write32(PLE_WINDOW, ple_window);
4240         }
4241
4242         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4243         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4244         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4245
4246         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4247         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4248         vmx_set_constant_host_state(vmx);
4249 #ifdef CONFIG_X86_64
4250         rdmsrl(MSR_FS_BASE, a);
4251         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4252         rdmsrl(MSR_GS_BASE, a);
4253         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4254 #else
4255         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4256         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4257 #endif
4258
4259         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4260         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4261         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4262         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4263         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4264
4265         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4266                 u32 msr_low, msr_high;
4267                 u64 host_pat;
4268                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4269                 host_pat = msr_low | ((u64) msr_high << 32);
4270                 /* Write the default value follow host pat */
4271                 vmcs_write64(GUEST_IA32_PAT, host_pat);
4272                 /* Keep arch.pat sync with GUEST_IA32_PAT */
4273                 vmx->vcpu.arch.pat = host_pat;
4274         }
4275
4276         for (i = 0; i < NR_VMX_MSR; ++i) {
4277                 u32 index = vmx_msr_index[i];
4278                 u32 data_low, data_high;
4279                 int j = vmx->nmsrs;
4280
4281                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4282                         continue;
4283                 if (wrmsr_safe(index, data_low, data_high) < 0)
4284                         continue;
4285                 vmx->guest_msrs[j].index = i;
4286                 vmx->guest_msrs[j].data = 0;
4287                 vmx->guest_msrs[j].mask = -1ull;
4288                 ++vmx->nmsrs;
4289         }
4290
4291         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
4292
4293         /* 22.2.1, 20.8.1 */
4294         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
4295
4296         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4297         set_cr4_guest_host_mask(vmx);
4298
4299         return 0;
4300 }
4301
4302 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4303 {
4304         struct vcpu_vmx *vmx = to_vmx(vcpu);
4305         u64 msr;
4306
4307         vmx->rmode.vm86_active = 0;
4308
4309         vmx->soft_vnmi_blocked = 0;
4310
4311         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4312         kvm_set_cr8(&vmx->vcpu, 0);
4313         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
4314         if (kvm_vcpu_is_bsp(&vmx->vcpu))
4315                 msr |= MSR_IA32_APICBASE_BSP;
4316         kvm_set_apic_base(&vmx->vcpu, msr);
4317
4318         vmx_segment_cache_clear(vmx);
4319
4320         seg_setup(VCPU_SREG_CS);
4321         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4322         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4323
4324         seg_setup(VCPU_SREG_DS);
4325         seg_setup(VCPU_SREG_ES);
4326         seg_setup(VCPU_SREG_FS);
4327         seg_setup(VCPU_SREG_GS);
4328         seg_setup(VCPU_SREG_SS);
4329
4330         vmcs_write16(GUEST_TR_SELECTOR, 0);
4331         vmcs_writel(GUEST_TR_BASE, 0);
4332         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4333         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4334
4335         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4336         vmcs_writel(GUEST_LDTR_BASE, 0);
4337         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4338         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4339
4340         vmcs_write32(GUEST_SYSENTER_CS, 0);
4341         vmcs_writel(GUEST_SYSENTER_ESP, 0);
4342         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4343
4344         vmcs_writel(GUEST_RFLAGS, 0x02);
4345         kvm_rip_write(vcpu, 0xfff0);
4346
4347         vmcs_writel(GUEST_GDTR_BASE, 0);
4348         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4349
4350         vmcs_writel(GUEST_IDTR_BASE, 0);
4351         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4352
4353         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4354         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4355         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4356
4357         /* Special registers */
4358         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4359
4360         setup_msrs(vmx);
4361
4362         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4363
4364         if (cpu_has_vmx_tpr_shadow()) {
4365                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4366                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4367                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4368                                      __pa(vmx->vcpu.arch.apic->regs));
4369                 vmcs_write32(TPR_THRESHOLD, 0);
4370         }
4371
4372         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4373                 vmcs_write64(APIC_ACCESS_ADDR,
4374                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
4375
4376         if (vmx_vm_has_apicv(vcpu->kvm))
4377                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4378
4379         if (vmx->vpid != 0)
4380                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4381
4382         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4383         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4384         vmx_set_cr4(&vmx->vcpu, 0);
4385         vmx_set_efer(&vmx->vcpu, 0);
4386         vmx_fpu_activate(&vmx->vcpu);
4387         update_exception_bitmap(&vmx->vcpu);
4388
4389         vpid_sync_context(vmx);
4390 }
4391
4392 /*
4393  * In nested virtualization, check if L1 asked to exit on external interrupts.
4394  * For most existing hypervisors, this will always return true.
4395  */
4396 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4397 {
4398         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4399                 PIN_BASED_EXT_INTR_MASK;
4400 }
4401
4402 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4403 {
4404         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4405                 PIN_BASED_NMI_EXITING;
4406 }
4407
4408 static int enable_irq_window(struct kvm_vcpu *vcpu)
4409 {
4410         u32 cpu_based_vm_exec_control;
4411
4412         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4413                 /*
4414                  * We get here if vmx_interrupt_allowed() said we can't
4415                  * inject to L1 now because L2 must run. The caller will have
4416                  * to make L2 exit right after entry, so we can inject to L1
4417                  * more promptly.
4418                  */
4419                 return -EBUSY;
4420
4421         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4422         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4423         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4424         return 0;
4425 }
4426
4427 static int enable_nmi_window(struct kvm_vcpu *vcpu)
4428 {
4429         u32 cpu_based_vm_exec_control;
4430
4431         if (!cpu_has_virtual_nmis())
4432                 return enable_irq_window(vcpu);
4433
4434         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI)
4435                 return enable_irq_window(vcpu);
4436
4437         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4438         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4439         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4440         return 0;
4441 }
4442
4443 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4444 {
4445         struct vcpu_vmx *vmx = to_vmx(vcpu);
4446         uint32_t intr;
4447         int irq = vcpu->arch.interrupt.nr;
4448
4449         trace_kvm_inj_virq(irq);
4450
4451         ++vcpu->stat.irq_injections;
4452         if (vmx->rmode.vm86_active) {
4453                 int inc_eip = 0;
4454                 if (vcpu->arch.interrupt.soft)
4455                         inc_eip = vcpu->arch.event_exit_inst_len;
4456                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4457                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4458                 return;
4459         }
4460         intr = irq | INTR_INFO_VALID_MASK;
4461         if (vcpu->arch.interrupt.soft) {
4462                 intr |= INTR_TYPE_SOFT_INTR;
4463                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4464                              vmx->vcpu.arch.event_exit_inst_len);
4465         } else
4466                 intr |= INTR_TYPE_EXT_INTR;
4467         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4468 }
4469
4470 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4471 {
4472         struct vcpu_vmx *vmx = to_vmx(vcpu);
4473
4474         if (is_guest_mode(vcpu))
4475                 return;
4476
4477         if (!cpu_has_virtual_nmis()) {
4478                 /*
4479                  * Tracking the NMI-blocked state in software is built upon
4480                  * finding the next open IRQ window. This, in turn, depends on
4481                  * well-behaving guests: They have to keep IRQs disabled at
4482                  * least as long as the NMI handler runs. Otherwise we may
4483                  * cause NMI nesting, maybe breaking the guest. But as this is
4484                  * highly unlikely, we can live with the residual risk.
4485                  */
4486                 vmx->soft_vnmi_blocked = 1;
4487                 vmx->vnmi_blocked_time = 0;
4488         }
4489
4490         ++vcpu->stat.nmi_injections;
4491         vmx->nmi_known_unmasked = false;
4492         if (vmx->rmode.vm86_active) {
4493                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4494                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4495                 return;
4496         }
4497         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4498                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4499 }
4500
4501 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4502 {
4503         if (!cpu_has_virtual_nmis())
4504                 return to_vmx(vcpu)->soft_vnmi_blocked;
4505         if (to_vmx(vcpu)->nmi_known_unmasked)
4506                 return false;
4507         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4508 }
4509
4510 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4511 {
4512         struct vcpu_vmx *vmx = to_vmx(vcpu);
4513
4514         if (!cpu_has_virtual_nmis()) {
4515                 if (vmx->soft_vnmi_blocked != masked) {
4516                         vmx->soft_vnmi_blocked = masked;
4517                         vmx->vnmi_blocked_time = 0;
4518                 }
4519         } else {
4520                 vmx->nmi_known_unmasked = !masked;
4521                 if (masked)
4522                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4523                                       GUEST_INTR_STATE_NMI);
4524                 else
4525                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4526                                         GUEST_INTR_STATE_NMI);
4527         }
4528 }
4529
4530 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4531 {
4532         if (is_guest_mode(vcpu)) {
4533                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4534
4535                 if (to_vmx(vcpu)->nested.nested_run_pending)
4536                         return 0;
4537                 if (nested_exit_on_nmi(vcpu)) {
4538                         nested_vmx_vmexit(vcpu);
4539                         vmcs12->vm_exit_reason = EXIT_REASON_EXCEPTION_NMI;
4540                         vmcs12->vm_exit_intr_info = NMI_VECTOR |
4541                                 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK;
4542                         /*
4543                          * The NMI-triggered VM exit counts as injection:
4544                          * clear this one and block further NMIs.
4545                          */
4546                         vcpu->arch.nmi_pending = 0;
4547                         vmx_set_nmi_mask(vcpu, true);
4548                         return 0;
4549                 }
4550         }
4551
4552         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4553                 return 0;
4554
4555         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4556                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4557                    | GUEST_INTR_STATE_NMI));
4558 }
4559
4560 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4561 {
4562         if (is_guest_mode(vcpu)) {
4563                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4564
4565                 if (to_vmx(vcpu)->nested.nested_run_pending)
4566                         return 0;
4567                 if (nested_exit_on_intr(vcpu)) {
4568                         nested_vmx_vmexit(vcpu);
4569                         vmcs12->vm_exit_reason =
4570                                 EXIT_REASON_EXTERNAL_INTERRUPT;
4571                         vmcs12->vm_exit_intr_info = 0;
4572                         /*
4573                          * fall through to normal code, but now in L1, not L2
4574                          */
4575                 }
4576         }
4577
4578         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4579                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4580                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4581 }
4582
4583 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4584 {
4585         int ret;
4586         struct kvm_userspace_memory_region tss_mem = {
4587                 .slot = TSS_PRIVATE_MEMSLOT,
4588                 .guest_phys_addr = addr,
4589                 .memory_size = PAGE_SIZE * 3,
4590                 .flags = 0,
4591         };
4592
4593         ret = kvm_set_memory_region(kvm, &tss_mem);
4594         if (ret)
4595                 return ret;
4596         kvm->arch.tss_addr = addr;
4597         if (!init_rmode_tss(kvm))
4598                 return  -ENOMEM;
4599
4600         return 0;
4601 }
4602
4603 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4604 {
4605         switch (vec) {
4606         case BP_VECTOR:
4607                 /*
4608                  * Update instruction length as we may reinject the exception
4609                  * from user space while in guest debugging mode.
4610                  */
4611                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4612                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4613                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4614                         return false;
4615                 /* fall through */
4616         case DB_VECTOR:
4617                 if (vcpu->guest_debug &
4618                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4619                         return false;
4620                 /* fall through */
4621         case DE_VECTOR:
4622         case OF_VECTOR:
4623         case BR_VECTOR:
4624         case UD_VECTOR:
4625         case DF_VECTOR:
4626         case SS_VECTOR:
4627         case GP_VECTOR:
4628         case MF_VECTOR:
4629                 return true;
4630         break;
4631         }
4632         return false;
4633 }
4634
4635 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4636                                   int vec, u32 err_code)
4637 {
4638         /*
4639          * Instruction with address size override prefix opcode 0x67
4640          * Cause the #SS fault with 0 error code in VM86 mode.
4641          */
4642         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4643                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4644                         if (vcpu->arch.halt_request) {
4645                                 vcpu->arch.halt_request = 0;
4646                                 return kvm_emulate_halt(vcpu);
4647                         }
4648                         return 1;
4649                 }
4650                 return 0;
4651         }
4652
4653         /*
4654          * Forward all other exceptions that are valid in real mode.
4655          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4656          *        the required debugging infrastructure rework.
4657          */
4658         kvm_queue_exception(vcpu, vec);
4659         return 1;
4660 }
4661
4662 /*
4663  * Trigger machine check on the host. We assume all the MSRs are already set up
4664  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4665  * We pass a fake environment to the machine check handler because we want
4666  * the guest to be always treated like user space, no matter what context
4667  * it used internally.
4668  */
4669 static void kvm_machine_check(void)
4670 {
4671 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4672         struct pt_regs regs = {
4673                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4674                 .flags = X86_EFLAGS_IF,
4675         };
4676
4677         do_machine_check(&regs, 0);
4678 #endif
4679 }
4680
4681 static int handle_machine_check(struct kvm_vcpu *vcpu)
4682 {
4683         /* already handled by vcpu_run */
4684         return 1;
4685 }
4686
4687 static int handle_exception(struct kvm_vcpu *vcpu)
4688 {
4689         struct vcpu_vmx *vmx = to_vmx(vcpu);
4690         struct kvm_run *kvm_run = vcpu->run;
4691         u32 intr_info, ex_no, error_code;
4692         unsigned long cr2, rip, dr6;
4693         u32 vect_info;
4694         enum emulation_result er;
4695
4696         vect_info = vmx->idt_vectoring_info;
4697         intr_info = vmx->exit_intr_info;
4698
4699         if (is_machine_check(intr_info))
4700                 return handle_machine_check(vcpu);
4701
4702         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4703                 return 1;  /* already handled by vmx_vcpu_run() */
4704
4705         if (is_no_device(intr_info)) {
4706                 vmx_fpu_activate(vcpu);
4707                 return 1;
4708         }
4709
4710         if (is_invalid_opcode(intr_info)) {
4711                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4712                 if (er != EMULATE_DONE)
4713                         kvm_queue_exception(vcpu, UD_VECTOR);
4714                 return 1;
4715         }
4716
4717         error_code = 0;
4718         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4719                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4720
4721         /*
4722          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4723          * MMIO, it is better to report an internal error.
4724          * See the comments in vmx_handle_exit.
4725          */
4726         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4727             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4728                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4729                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4730                 vcpu->run->internal.ndata = 2;
4731                 vcpu->run->internal.data[0] = vect_info;
4732                 vcpu->run->internal.data[1] = intr_info;
4733                 return 0;
4734         }
4735
4736         if (is_page_fault(intr_info)) {
4737                 /* EPT won't cause page fault directly */
4738                 BUG_ON(enable_ept);
4739                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4740                 trace_kvm_page_fault(cr2, error_code);
4741
4742                 if (kvm_event_needs_reinjection(vcpu))
4743                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4744                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4745         }
4746
4747         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4748
4749         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4750                 return handle_rmode_exception(vcpu, ex_no, error_code);
4751
4752         switch (ex_no) {
4753         case DB_VECTOR:
4754                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4755                 if (!(vcpu->guest_debug &
4756                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4757                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4758                         kvm_queue_exception(vcpu, DB_VECTOR);
4759                         return 1;
4760                 }
4761                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4762                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4763                 /* fall through */
4764         case BP_VECTOR:
4765                 /*
4766                  * Update instruction length as we may reinject #BP from
4767                  * user space while in guest debugging mode. Reading it for
4768                  * #DB as well causes no harm, it is not used in that case.
4769                  */
4770                 vmx->vcpu.arch.event_exit_inst_len =
4771                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4772                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4773                 rip = kvm_rip_read(vcpu);
4774                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4775                 kvm_run->debug.arch.exception = ex_no;
4776                 break;
4777         default:
4778                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4779                 kvm_run->ex.exception = ex_no;
4780                 kvm_run->ex.error_code = error_code;
4781                 break;
4782         }
4783         return 0;
4784 }
4785
4786 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4787 {
4788         ++vcpu->stat.irq_exits;
4789         return 1;
4790 }
4791
4792 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4793 {
4794         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4795         return 0;
4796 }
4797
4798 static int handle_io(struct kvm_vcpu *vcpu)
4799 {
4800         unsigned long exit_qualification;
4801         int size, in, string;
4802         unsigned port;
4803
4804         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4805         string = (exit_qualification & 16) != 0;
4806         in = (exit_qualification & 8) != 0;
4807
4808         ++vcpu->stat.io_exits;
4809
4810         if (string || in)
4811                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4812
4813         port = exit_qualification >> 16;
4814         size = (exit_qualification & 7) + 1;
4815         skip_emulated_instruction(vcpu);
4816
4817         return kvm_fast_pio_out(vcpu, size, port);
4818 }
4819
4820 static void
4821 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4822 {
4823         /*
4824          * Patch in the VMCALL instruction:
4825          */
4826         hypercall[0] = 0x0f;
4827         hypercall[1] = 0x01;
4828         hypercall[2] = 0xc1;
4829 }
4830
4831 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4832 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4833 {
4834         if (is_guest_mode(vcpu)) {
4835                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4836                 unsigned long orig_val = val;
4837
4838                 /*
4839                  * We get here when L2 changed cr0 in a way that did not change
4840                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4841                  * but did change L0 shadowed bits. So we first calculate the
4842                  * effective cr0 value that L1 would like to write into the
4843                  * hardware. It consists of the L2-owned bits from the new
4844                  * value combined with the L1-owned bits from L1's guest_cr0.
4845                  */
4846                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4847                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4848
4849                 /* TODO: will have to take unrestricted guest mode into
4850                  * account */
4851                 if ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON)
4852                         return 1;
4853
4854                 if (kvm_set_cr0(vcpu, val))
4855                         return 1;
4856                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4857                 return 0;
4858         } else {
4859                 if (to_vmx(vcpu)->nested.vmxon &&
4860                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4861                         return 1;
4862                 return kvm_set_cr0(vcpu, val);
4863         }
4864 }
4865
4866 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4867 {
4868         if (is_guest_mode(vcpu)) {
4869                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4870                 unsigned long orig_val = val;
4871
4872                 /* analogously to handle_set_cr0 */
4873                 val = (val & ~vmcs12->cr4_guest_host_mask) |
4874                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4875                 if (kvm_set_cr4(vcpu, val))
4876                         return 1;
4877                 vmcs_writel(CR4_READ_SHADOW, orig_val);
4878                 return 0;
4879         } else
4880                 return kvm_set_cr4(vcpu, val);
4881 }
4882
4883 /* called to set cr0 as approriate for clts instruction exit. */
4884 static void handle_clts(struct kvm_vcpu *vcpu)
4885 {
4886         if (is_guest_mode(vcpu)) {
4887                 /*
4888                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4889                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4890                  * just pretend it's off (also in arch.cr0 for fpu_activate).
4891                  */
4892                 vmcs_writel(CR0_READ_SHADOW,
4893                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4894                 vcpu->arch.cr0 &= ~X86_CR0_TS;
4895         } else
4896                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4897 }
4898
4899 static int handle_cr(struct kvm_vcpu *vcpu)
4900 {
4901         unsigned long exit_qualification, val;
4902         int cr;
4903         int reg;
4904         int err;
4905
4906         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4907         cr = exit_qualification & 15;
4908         reg = (exit_qualification >> 8) & 15;
4909         switch ((exit_qualification >> 4) & 3) {
4910         case 0: /* mov to cr */
4911                 val = kvm_register_read(vcpu, reg);
4912                 trace_kvm_cr_write(cr, val);
4913                 switch (cr) {
4914                 case 0:
4915                         err = handle_set_cr0(vcpu, val);
4916                         kvm_complete_insn_gp(vcpu, err);
4917                         return 1;
4918                 case 3:
4919                         err = kvm_set_cr3(vcpu, val);
4920                         kvm_complete_insn_gp(vcpu, err);
4921                         return 1;
4922                 case 4:
4923                         err = handle_set_cr4(vcpu, val);
4924                         kvm_complete_insn_gp(vcpu, err);
4925                         return 1;
4926                 case 8: {
4927                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4928                                 u8 cr8 = kvm_register_read(vcpu, reg);
4929                                 err = kvm_set_cr8(vcpu, cr8);
4930                                 kvm_complete_insn_gp(vcpu, err);
4931                                 if (irqchip_in_kernel(vcpu->kvm))
4932                                         return 1;
4933                                 if (cr8_prev <= cr8)
4934                                         return 1;
4935                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4936                                 return 0;
4937                         }
4938                 }
4939                 break;
4940         case 2: /* clts */
4941                 handle_clts(vcpu);
4942                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4943                 skip_emulated_instruction(vcpu);
4944                 vmx_fpu_activate(vcpu);
4945                 return 1;
4946         case 1: /*mov from cr*/
4947                 switch (cr) {
4948                 case 3:
4949                         val = kvm_read_cr3(vcpu);
4950                         kvm_register_write(vcpu, reg, val);
4951                         trace_kvm_cr_read(cr, val);
4952                         skip_emulated_instruction(vcpu);
4953                         return 1;
4954                 case 8:
4955                         val = kvm_get_cr8(vcpu);
4956                         kvm_register_write(vcpu, reg, val);
4957                         trace_kvm_cr_read(cr, val);
4958                         skip_emulated_instruction(vcpu);
4959                         return 1;
4960                 }
4961                 break;
4962         case 3: /* lmsw */
4963                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4964                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4965                 kvm_lmsw(vcpu, val);
4966
4967                 skip_emulated_instruction(vcpu);
4968                 return 1;
4969         default:
4970                 break;
4971         }
4972         vcpu->run->exit_reason = 0;
4973         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4974                (int)(exit_qualification >> 4) & 3, cr);
4975         return 0;
4976 }
4977
4978 static int handle_dr(struct kvm_vcpu *vcpu)
4979 {
4980         unsigned long exit_qualification;
4981         int dr, reg;
4982
4983         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4984         if (!kvm_require_cpl(vcpu, 0))
4985                 return 1;
4986         dr = vmcs_readl(GUEST_DR7);
4987         if (dr & DR7_GD) {
4988                 /*
4989                  * As the vm-exit takes precedence over the debug trap, we
4990                  * need to emulate the latter, either for the host or the
4991                  * guest debugging itself.
4992                  */
4993                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4994                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4995                         vcpu->run->debug.arch.dr7 = dr;
4996                         vcpu->run->debug.arch.pc =
4997                                 vmcs_readl(GUEST_CS_BASE) +
4998                                 vmcs_readl(GUEST_RIP);
4999                         vcpu->run->debug.arch.exception = DB_VECTOR;
5000                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5001                         return 0;
5002                 } else {
5003                         vcpu->arch.dr7 &= ~DR7_GD;
5004                         vcpu->arch.dr6 |= DR6_BD;
5005                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5006                         kvm_queue_exception(vcpu, DB_VECTOR);
5007                         return 1;
5008                 }
5009         }
5010
5011         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5012         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5013         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5014         if (exit_qualification & TYPE_MOV_FROM_DR) {
5015                 unsigned long val;
5016                 if (!kvm_get_dr(vcpu, dr, &val))
5017                         kvm_register_write(vcpu, reg, val);
5018         } else
5019                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
5020         skip_emulated_instruction(vcpu);
5021         return 1;
5022 }
5023
5024 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5025 {
5026         vmcs_writel(GUEST_DR7, val);
5027 }
5028
5029 static int handle_cpuid(struct kvm_vcpu *vcpu)
5030 {
5031         kvm_emulate_cpuid(vcpu);
5032         return 1;
5033 }
5034
5035 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5036 {
5037         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5038         u64 data;
5039
5040         if (vmx_get_msr(vcpu, ecx, &data)) {
5041                 trace_kvm_msr_read_ex(ecx);
5042                 kvm_inject_gp(vcpu, 0);
5043                 return 1;
5044         }
5045
5046         trace_kvm_msr_read(ecx, data);
5047
5048         /* FIXME: handling of bits 32:63 of rax, rdx */
5049         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5050         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
5051         skip_emulated_instruction(vcpu);
5052         return 1;
5053 }
5054
5055 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5056 {
5057         struct msr_data msr;
5058         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5059         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5060                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5061
5062         msr.data = data;
5063         msr.index = ecx;
5064         msr.host_initiated = false;
5065         if (vmx_set_msr(vcpu, &msr) != 0) {
5066                 trace_kvm_msr_write_ex(ecx, data);
5067                 kvm_inject_gp(vcpu, 0);
5068                 return 1;
5069         }
5070
5071         trace_kvm_msr_write(ecx, data);
5072         skip_emulated_instruction(vcpu);
5073         return 1;
5074 }
5075
5076 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5077 {
5078         kvm_make_request(KVM_REQ_EVENT, vcpu);
5079         return 1;
5080 }
5081
5082 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5083 {
5084         u32 cpu_based_vm_exec_control;
5085
5086         /* clear pending irq */
5087         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5088         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5089         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5090
5091         kvm_make_request(KVM_REQ_EVENT, vcpu);
5092
5093         ++vcpu->stat.irq_window_exits;
5094
5095         /*
5096          * If the user space waits to inject interrupts, exit as soon as
5097          * possible
5098          */
5099         if (!irqchip_in_kernel(vcpu->kvm) &&
5100             vcpu->run->request_interrupt_window &&
5101             !kvm_cpu_has_interrupt(vcpu)) {
5102                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
5103                 return 0;
5104         }
5105         return 1;
5106 }
5107
5108 static int handle_halt(struct kvm_vcpu *vcpu)
5109 {
5110         skip_emulated_instruction(vcpu);
5111         return kvm_emulate_halt(vcpu);
5112 }
5113
5114 static int handle_vmcall(struct kvm_vcpu *vcpu)
5115 {
5116         skip_emulated_instruction(vcpu);
5117         kvm_emulate_hypercall(vcpu);
5118         return 1;
5119 }
5120
5121 static int handle_invd(struct kvm_vcpu *vcpu)
5122 {
5123         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5124 }
5125
5126 static int handle_invlpg(struct kvm_vcpu *vcpu)
5127 {
5128         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5129
5130         kvm_mmu_invlpg(vcpu, exit_qualification);
5131         skip_emulated_instruction(vcpu);
5132         return 1;
5133 }
5134
5135 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5136 {
5137         int err;
5138
5139         err = kvm_rdpmc(vcpu);
5140         kvm_complete_insn_gp(vcpu, err);
5141
5142         return 1;
5143 }
5144
5145 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5146 {
5147         skip_emulated_instruction(vcpu);
5148         kvm_emulate_wbinvd(vcpu);
5149         return 1;
5150 }
5151
5152 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5153 {
5154         u64 new_bv = kvm_read_edx_eax(vcpu);
5155         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5156
5157         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5158                 skip_emulated_instruction(vcpu);
5159         return 1;
5160 }
5161
5162 static int handle_apic_access(struct kvm_vcpu *vcpu)
5163 {
5164         if (likely(fasteoi)) {
5165                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5166                 int access_type, offset;
5167
5168                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5169                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5170                 /*
5171                  * Sane guest uses MOV to write EOI, with written value
5172                  * not cared. So make a short-circuit here by avoiding
5173                  * heavy instruction emulation.
5174                  */
5175                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5176                     (offset == APIC_EOI)) {
5177                         kvm_lapic_set_eoi(vcpu);
5178                         skip_emulated_instruction(vcpu);
5179                         return 1;
5180                 }
5181         }
5182         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5183 }
5184
5185 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5186 {
5187         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5188         int vector = exit_qualification & 0xff;
5189
5190         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5191         kvm_apic_set_eoi_accelerated(vcpu, vector);
5192         return 1;
5193 }
5194
5195 static int handle_apic_write(struct kvm_vcpu *vcpu)
5196 {
5197         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5198         u32 offset = exit_qualification & 0xfff;
5199
5200         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5201         kvm_apic_write_nodecode(vcpu, offset);
5202         return 1;
5203 }
5204
5205 static int handle_task_switch(struct kvm_vcpu *vcpu)
5206 {
5207         struct vcpu_vmx *vmx = to_vmx(vcpu);
5208         unsigned long exit_qualification;
5209         bool has_error_code = false;
5210         u32 error_code = 0;
5211         u16 tss_selector;
5212         int reason, type, idt_v, idt_index;
5213
5214         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5215         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5216         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5217
5218         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5219
5220         reason = (u32)exit_qualification >> 30;
5221         if (reason == TASK_SWITCH_GATE && idt_v) {
5222                 switch (type) {
5223                 case INTR_TYPE_NMI_INTR:
5224                         vcpu->arch.nmi_injected = false;
5225                         vmx_set_nmi_mask(vcpu, true);
5226                         break;
5227                 case INTR_TYPE_EXT_INTR:
5228                 case INTR_TYPE_SOFT_INTR:
5229                         kvm_clear_interrupt_queue(vcpu);
5230                         break;
5231                 case INTR_TYPE_HARD_EXCEPTION:
5232                         if (vmx->idt_vectoring_info &
5233                             VECTORING_INFO_DELIVER_CODE_MASK) {
5234                                 has_error_code = true;
5235                                 error_code =
5236                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5237                         }
5238                         /* fall through */
5239                 case INTR_TYPE_SOFT_EXCEPTION:
5240                         kvm_clear_exception_queue(vcpu);
5241                         break;
5242                 default:
5243                         break;
5244                 }
5245         }
5246         tss_selector = exit_qualification;
5247
5248         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5249                        type != INTR_TYPE_EXT_INTR &&
5250                        type != INTR_TYPE_NMI_INTR))
5251                 skip_emulated_instruction(vcpu);
5252
5253         if (kvm_task_switch(vcpu, tss_selector,
5254                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5255                             has_error_code, error_code) == EMULATE_FAIL) {
5256                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5257                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5258                 vcpu->run->internal.ndata = 0;
5259                 return 0;
5260         }
5261
5262         /* clear all local breakpoint enable flags */
5263         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5264
5265         /*
5266          * TODO: What about debug traps on tss switch?
5267          *       Are we supposed to inject them and update dr6?
5268          */
5269
5270         return 1;
5271 }
5272
5273 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5274 {
5275         unsigned long exit_qualification;
5276         gpa_t gpa;
5277         u32 error_code;
5278         int gla_validity;
5279
5280         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5281
5282         gla_validity = (exit_qualification >> 7) & 0x3;
5283         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5284                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5285                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5286                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5287                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5288                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5289                         (long unsigned int)exit_qualification);
5290                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5291                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5292                 return 0;
5293         }
5294
5295         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5296         trace_kvm_page_fault(gpa, exit_qualification);
5297
5298         /* It is a write fault? */
5299         error_code = exit_qualification & (1U << 1);
5300         /* ept page table is present? */
5301         error_code |= (exit_qualification >> 3) & 0x1;
5302
5303         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5304 }
5305
5306 static u64 ept_rsvd_mask(u64 spte, int level)
5307 {
5308         int i;
5309         u64 mask = 0;
5310
5311         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5312                 mask |= (1ULL << i);
5313
5314         if (level > 2)
5315                 /* bits 7:3 reserved */
5316                 mask |= 0xf8;
5317         else if (level == 2) {
5318                 if (spte & (1ULL << 7))
5319                         /* 2MB ref, bits 20:12 reserved */
5320                         mask |= 0x1ff000;
5321                 else
5322                         /* bits 6:3 reserved */
5323                         mask |= 0x78;
5324         }
5325
5326         return mask;
5327 }
5328
5329 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5330                                        int level)
5331 {
5332         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5333
5334         /* 010b (write-only) */
5335         WARN_ON((spte & 0x7) == 0x2);
5336
5337         /* 110b (write/execute) */
5338         WARN_ON((spte & 0x7) == 0x6);
5339
5340         /* 100b (execute-only) and value not supported by logical processor */
5341         if (!cpu_has_vmx_ept_execute_only())
5342                 WARN_ON((spte & 0x7) == 0x4);
5343
5344         /* not 000b */
5345         if ((spte & 0x7)) {
5346                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5347
5348                 if (rsvd_bits != 0) {
5349                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5350                                          __func__, rsvd_bits);
5351                         WARN_ON(1);
5352                 }
5353
5354                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5355                         u64 ept_mem_type = (spte & 0x38) >> 3;
5356
5357                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
5358                             ept_mem_type == 7) {
5359                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5360                                                 __func__, ept_mem_type);
5361                                 WARN_ON(1);
5362                         }
5363                 }
5364         }
5365 }
5366
5367 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5368 {
5369         u64 sptes[4];
5370         int nr_sptes, i, ret;
5371         gpa_t gpa;
5372
5373         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5374
5375         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5376         if (likely(ret == 1))
5377                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5378                                               EMULATE_DONE;
5379         if (unlikely(!ret))
5380                 return 1;
5381
5382         /* It is the real ept misconfig */
5383         printk(KERN_ERR "EPT: Misconfiguration.\n");
5384         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5385
5386         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5387
5388         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5389                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5390
5391         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5392         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5393
5394         return 0;
5395 }
5396
5397 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5398 {
5399         u32 cpu_based_vm_exec_control;
5400
5401         /* clear pending NMI */
5402         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5403         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5404         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5405         ++vcpu->stat.nmi_window_exits;
5406         kvm_make_request(KVM_REQ_EVENT, vcpu);
5407
5408         return 1;
5409 }
5410
5411 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5412 {
5413         struct vcpu_vmx *vmx = to_vmx(vcpu);
5414         enum emulation_result err = EMULATE_DONE;
5415         int ret = 1;
5416         u32 cpu_exec_ctrl;
5417         bool intr_window_requested;
5418         unsigned count = 130;
5419
5420         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5421         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5422
5423         while (!guest_state_valid(vcpu) && count-- != 0) {
5424                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5425                         return handle_interrupt_window(&vmx->vcpu);
5426
5427                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5428                         return 1;
5429
5430                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5431
5432                 if (err == EMULATE_DO_MMIO) {
5433                         ret = 0;
5434                         goto out;
5435                 }
5436
5437                 if (err != EMULATE_DONE) {
5438                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5439                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5440                         vcpu->run->internal.ndata = 0;
5441                         return 0;
5442                 }
5443
5444                 if (vcpu->arch.halt_request) {
5445                         vcpu->arch.halt_request = 0;
5446                         ret = kvm_emulate_halt(vcpu);
5447                         goto out;
5448                 }
5449
5450                 if (signal_pending(current))
5451                         goto out;
5452                 if (need_resched())
5453                         schedule();
5454         }
5455
5456         vmx->emulation_required = emulation_required(vcpu);
5457 out:
5458         return ret;
5459 }
5460
5461 /*
5462  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5463  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5464  */
5465 static int handle_pause(struct kvm_vcpu *vcpu)
5466 {
5467         skip_emulated_instruction(vcpu);
5468         kvm_vcpu_on_spin(vcpu);
5469
5470         return 1;
5471 }
5472
5473 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5474 {
5475         kvm_queue_exception(vcpu, UD_VECTOR);
5476         return 1;
5477 }
5478
5479 /*
5480  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5481  * We could reuse a single VMCS for all the L2 guests, but we also want the
5482  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5483  * allows keeping them loaded on the processor, and in the future will allow
5484  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5485  * every entry if they never change.
5486  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5487  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5488  *
5489  * The following functions allocate and free a vmcs02 in this pool.
5490  */
5491
5492 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5493 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5494 {
5495         struct vmcs02_list *item;
5496         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5497                 if (item->vmptr == vmx->nested.current_vmptr) {
5498                         list_move(&item->list, &vmx->nested.vmcs02_pool);
5499                         return &item->vmcs02;
5500                 }
5501
5502         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5503                 /* Recycle the least recently used VMCS. */
5504                 item = list_entry(vmx->nested.vmcs02_pool.prev,
5505                         struct vmcs02_list, list);
5506                 item->vmptr = vmx->nested.current_vmptr;
5507                 list_move(&item->list, &vmx->nested.vmcs02_pool);
5508                 return &item->vmcs02;
5509         }
5510
5511         /* Create a new VMCS */
5512         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5513         if (!item)
5514                 return NULL;
5515         item->vmcs02.vmcs = alloc_vmcs();
5516         if (!item->vmcs02.vmcs) {
5517                 kfree(item);
5518                 return NULL;
5519         }
5520         loaded_vmcs_init(&item->vmcs02);
5521         item->vmptr = vmx->nested.current_vmptr;
5522         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5523         vmx->nested.vmcs02_num++;
5524         return &item->vmcs02;
5525 }
5526
5527 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5528 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5529 {
5530         struct vmcs02_list *item;
5531         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5532                 if (item->vmptr == vmptr) {
5533                         free_loaded_vmcs(&item->vmcs02);
5534                         list_del(&item->list);
5535                         kfree(item);
5536                         vmx->nested.vmcs02_num--;
5537                         return;
5538                 }
5539 }
5540
5541 /*
5542  * Free all VMCSs saved for this vcpu, except the one pointed by
5543  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5544  * currently used, if running L2), and vmcs01 when running L2.
5545  */
5546 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5547 {
5548         struct vmcs02_list *item, *n;
5549         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5550                 if (vmx->loaded_vmcs != &item->vmcs02)
5551                         free_loaded_vmcs(&item->vmcs02);
5552                 list_del(&item->list);
5553                 kfree(item);
5554         }
5555         vmx->nested.vmcs02_num = 0;
5556
5557         if (vmx->loaded_vmcs != &vmx->vmcs01)
5558                 free_loaded_vmcs(&vmx->vmcs01);
5559 }
5560
5561 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5562                                  u32 vm_instruction_error);
5563
5564 /*
5565  * Emulate the VMXON instruction.
5566  * Currently, we just remember that VMX is active, and do not save or even
5567  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5568  * do not currently need to store anything in that guest-allocated memory
5569  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5570  * argument is different from the VMXON pointer (which the spec says they do).
5571  */
5572 static int handle_vmon(struct kvm_vcpu *vcpu)
5573 {
5574         struct kvm_segment cs;
5575         struct vcpu_vmx *vmx = to_vmx(vcpu);
5576         struct vmcs *shadow_vmcs;
5577
5578         /* The Intel VMX Instruction Reference lists a bunch of bits that
5579          * are prerequisite to running VMXON, most notably cr4.VMXE must be
5580          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5581          * Otherwise, we should fail with #UD. We test these now:
5582          */
5583         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5584             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5585             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5586                 kvm_queue_exception(vcpu, UD_VECTOR);
5587                 return 1;
5588         }
5589
5590         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5591         if (is_long_mode(vcpu) && !cs.l) {
5592                 kvm_queue_exception(vcpu, UD_VECTOR);
5593                 return 1;
5594         }
5595
5596         if (vmx_get_cpl(vcpu)) {
5597                 kvm_inject_gp(vcpu, 0);
5598                 return 1;
5599         }
5600         if (vmx->nested.vmxon) {
5601                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5602                 skip_emulated_instruction(vcpu);
5603                 return 1;
5604         }
5605         if (enable_shadow_vmcs) {
5606                 shadow_vmcs = alloc_vmcs();
5607                 if (!shadow_vmcs)
5608                         return -ENOMEM;
5609                 /* mark vmcs as shadow */
5610                 shadow_vmcs->revision_id |= (1u << 31);
5611                 /* init shadow vmcs */
5612                 vmcs_clear(shadow_vmcs);
5613                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5614         }
5615
5616         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5617         vmx->nested.vmcs02_num = 0;
5618
5619         vmx->nested.vmxon = true;
5620
5621         skip_emulated_instruction(vcpu);
5622         return 1;
5623 }
5624
5625 /*
5626  * Intel's VMX Instruction Reference specifies a common set of prerequisites
5627  * for running VMX instructions (except VMXON, whose prerequisites are
5628  * slightly different). It also specifies what exception to inject otherwise.
5629  */
5630 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5631 {
5632         struct kvm_segment cs;
5633         struct vcpu_vmx *vmx = to_vmx(vcpu);
5634
5635         if (!vmx->nested.vmxon) {
5636                 kvm_queue_exception(vcpu, UD_VECTOR);
5637                 return 0;
5638         }
5639
5640         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5641         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5642             (is_long_mode(vcpu) && !cs.l)) {
5643                 kvm_queue_exception(vcpu, UD_VECTOR);
5644                 return 0;
5645         }
5646
5647         if (vmx_get_cpl(vcpu)) {
5648                 kvm_inject_gp(vcpu, 0);
5649                 return 0;
5650         }
5651
5652         return 1;
5653 }
5654
5655 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5656 {
5657         u32 exec_control;
5658         if (enable_shadow_vmcs) {
5659                 if (vmx->nested.current_vmcs12 != NULL) {
5660                         /* copy to memory all shadowed fields in case
5661                            they were modified */
5662                         copy_shadow_to_vmcs12(vmx);
5663                         vmx->nested.sync_shadow_vmcs = false;
5664                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5665                         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5666                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5667                         vmcs_write64(VMCS_LINK_POINTER, -1ull);
5668                 }
5669         }
5670         kunmap(vmx->nested.current_vmcs12_page);
5671         nested_release_page(vmx->nested.current_vmcs12_page);
5672 }
5673
5674 /*
5675  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5676  * just stops using VMX.
5677  */
5678 static void free_nested(struct vcpu_vmx *vmx)
5679 {
5680         if (!vmx->nested.vmxon)
5681                 return;
5682         vmx->nested.vmxon = false;
5683         if (vmx->nested.current_vmptr != -1ull) {
5684                 nested_release_vmcs12(vmx);
5685                 vmx->nested.current_vmptr = -1ull;
5686                 vmx->nested.current_vmcs12 = NULL;
5687         }
5688         if (enable_shadow_vmcs)
5689                 free_vmcs(vmx->nested.current_shadow_vmcs);
5690         /* Unpin physical memory we referred to in current vmcs02 */
5691         if (vmx->nested.apic_access_page) {
5692                 nested_release_page(vmx->nested.apic_access_page);
5693                 vmx->nested.apic_access_page = 0;
5694         }
5695
5696         nested_free_all_saved_vmcss(vmx);
5697 }
5698
5699 /* Emulate the VMXOFF instruction */
5700 static int handle_vmoff(struct kvm_vcpu *vcpu)
5701 {
5702         if (!nested_vmx_check_permission(vcpu))
5703                 return 1;
5704         free_nested(to_vmx(vcpu));
5705         skip_emulated_instruction(vcpu);
5706         return 1;
5707 }
5708
5709 /*
5710  * Decode the memory-address operand of a vmx instruction, as recorded on an
5711  * exit caused by such an instruction (run by a guest hypervisor).
5712  * On success, returns 0. When the operand is invalid, returns 1 and throws
5713  * #UD or #GP.
5714  */
5715 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5716                                  unsigned long exit_qualification,
5717                                  u32 vmx_instruction_info, gva_t *ret)
5718 {
5719         /*
5720          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5721          * Execution", on an exit, vmx_instruction_info holds most of the
5722          * addressing components of the operand. Only the displacement part
5723          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5724          * For how an actual address is calculated from all these components,
5725          * refer to Vol. 1, "Operand Addressing".
5726          */
5727         int  scaling = vmx_instruction_info & 3;
5728         int  addr_size = (vmx_instruction_info >> 7) & 7;
5729         bool is_reg = vmx_instruction_info & (1u << 10);
5730         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5731         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5732         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5733         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5734         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
5735
5736         if (is_reg) {
5737                 kvm_queue_exception(vcpu, UD_VECTOR);
5738                 return 1;
5739         }
5740
5741         /* Addr = segment_base + offset */
5742         /* offset = base + [index * scale] + displacement */
5743         *ret = vmx_get_segment_base(vcpu, seg_reg);
5744         if (base_is_valid)
5745                 *ret += kvm_register_read(vcpu, base_reg);
5746         if (index_is_valid)
5747                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5748         *ret += exit_qualification; /* holds the displacement */
5749
5750         if (addr_size == 1) /* 32 bit */
5751                 *ret &= 0xffffffff;
5752
5753         /*
5754          * TODO: throw #GP (and return 1) in various cases that the VM*
5755          * instructions require it - e.g., offset beyond segment limit,
5756          * unusable or unreadable/unwritable segment, non-canonical 64-bit
5757          * address, and so on. Currently these are not checked.
5758          */
5759         return 0;
5760 }
5761
5762 /*
5763  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5764  * set the success or error code of an emulated VMX instruction, as specified
5765  * by Vol 2B, VMX Instruction Reference, "Conventions".
5766  */
5767 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5768 {
5769         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5770                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5771                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5772 }
5773
5774 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5775 {
5776         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5777                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5778                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5779                         | X86_EFLAGS_CF);
5780 }
5781
5782 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5783                                         u32 vm_instruction_error)
5784 {
5785         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5786                 /*
5787                  * failValid writes the error number to the current VMCS, which
5788                  * can't be done there isn't a current VMCS.
5789                  */
5790                 nested_vmx_failInvalid(vcpu);
5791                 return;
5792         }
5793         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5794                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5795                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5796                         | X86_EFLAGS_ZF);
5797         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5798         /*
5799          * We don't need to force a shadow sync because
5800          * VM_INSTRUCTION_ERROR is not shadowed
5801          */
5802 }
5803
5804 /* Emulate the VMCLEAR instruction */
5805 static int handle_vmclear(struct kvm_vcpu *vcpu)
5806 {
5807         struct vcpu_vmx *vmx = to_vmx(vcpu);
5808         gva_t gva;
5809         gpa_t vmptr;
5810         struct vmcs12 *vmcs12;
5811         struct page *page;
5812         struct x86_exception e;
5813
5814         if (!nested_vmx_check_permission(vcpu))
5815                 return 1;
5816
5817         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5818                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5819                 return 1;
5820
5821         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5822                                 sizeof(vmptr), &e)) {
5823                 kvm_inject_page_fault(vcpu, &e);
5824                 return 1;
5825         }
5826
5827         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5828                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5829                 skip_emulated_instruction(vcpu);
5830                 return 1;
5831         }
5832
5833         if (vmptr == vmx->nested.current_vmptr) {
5834                 nested_release_vmcs12(vmx);
5835                 vmx->nested.current_vmptr = -1ull;
5836                 vmx->nested.current_vmcs12 = NULL;
5837         }
5838
5839         page = nested_get_page(vcpu, vmptr);
5840         if (page == NULL) {
5841                 /*
5842                  * For accurate processor emulation, VMCLEAR beyond available
5843                  * physical memory should do nothing at all. However, it is
5844                  * possible that a nested vmx bug, not a guest hypervisor bug,
5845                  * resulted in this case, so let's shut down before doing any
5846                  * more damage:
5847                  */
5848                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5849                 return 1;
5850         }
5851         vmcs12 = kmap(page);
5852         vmcs12->launch_state = 0;
5853         kunmap(page);
5854         nested_release_page(page);
5855
5856         nested_free_vmcs02(vmx, vmptr);
5857
5858         skip_emulated_instruction(vcpu);
5859         nested_vmx_succeed(vcpu);
5860         return 1;
5861 }
5862
5863 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5864
5865 /* Emulate the VMLAUNCH instruction */
5866 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5867 {
5868         return nested_vmx_run(vcpu, true);
5869 }
5870
5871 /* Emulate the VMRESUME instruction */
5872 static int handle_vmresume(struct kvm_vcpu *vcpu)
5873 {
5874
5875         return nested_vmx_run(vcpu, false);
5876 }
5877
5878 enum vmcs_field_type {
5879         VMCS_FIELD_TYPE_U16 = 0,
5880         VMCS_FIELD_TYPE_U64 = 1,
5881         VMCS_FIELD_TYPE_U32 = 2,
5882         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5883 };
5884
5885 static inline int vmcs_field_type(unsigned long field)
5886 {
5887         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
5888                 return VMCS_FIELD_TYPE_U32;
5889         return (field >> 13) & 0x3 ;
5890 }
5891
5892 static inline int vmcs_field_readonly(unsigned long field)
5893 {
5894         return (((field >> 10) & 0x3) == 1);
5895 }
5896
5897 /*
5898  * Read a vmcs12 field. Since these can have varying lengths and we return
5899  * one type, we chose the biggest type (u64) and zero-extend the return value
5900  * to that size. Note that the caller, handle_vmread, might need to use only
5901  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5902  * 64-bit fields are to be returned).
5903  */
5904 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5905                                         unsigned long field, u64 *ret)
5906 {
5907         short offset = vmcs_field_to_offset(field);
5908         char *p;
5909
5910         if (offset < 0)
5911                 return 0;
5912
5913         p = ((char *)(get_vmcs12(vcpu))) + offset;
5914
5915         switch (vmcs_field_type(field)) {
5916         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5917                 *ret = *((natural_width *)p);
5918                 return 1;
5919         case VMCS_FIELD_TYPE_U16:
5920                 *ret = *((u16 *)p);
5921                 return 1;
5922         case VMCS_FIELD_TYPE_U32:
5923                 *ret = *((u32 *)p);
5924                 return 1;
5925         case VMCS_FIELD_TYPE_U64:
5926                 *ret = *((u64 *)p);
5927                 return 1;
5928         default:
5929                 return 0; /* can never happen. */
5930         }
5931 }
5932
5933
5934 static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
5935                                     unsigned long field, u64 field_value){
5936         short offset = vmcs_field_to_offset(field);
5937         char *p = ((char *) get_vmcs12(vcpu)) + offset;
5938         if (offset < 0)
5939                 return false;
5940
5941         switch (vmcs_field_type(field)) {
5942         case VMCS_FIELD_TYPE_U16:
5943                 *(u16 *)p = field_value;
5944                 return true;
5945         case VMCS_FIELD_TYPE_U32:
5946                 *(u32 *)p = field_value;
5947                 return true;
5948         case VMCS_FIELD_TYPE_U64:
5949                 *(u64 *)p = field_value;
5950                 return true;
5951         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5952                 *(natural_width *)p = field_value;
5953                 return true;
5954         default:
5955                 return false; /* can never happen. */
5956         }
5957
5958 }
5959
5960 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
5961 {
5962         int i;
5963         unsigned long field;
5964         u64 field_value;
5965         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
5966         unsigned long *fields = (unsigned long *)shadow_read_write_fields;
5967         int num_fields = max_shadow_read_write_fields;
5968
5969         vmcs_load(shadow_vmcs);
5970
5971         for (i = 0; i < num_fields; i++) {
5972                 field = fields[i];
5973                 switch (vmcs_field_type(field)) {
5974                 case VMCS_FIELD_TYPE_U16:
5975                         field_value = vmcs_read16(field);
5976                         break;
5977                 case VMCS_FIELD_TYPE_U32:
5978                         field_value = vmcs_read32(field);
5979                         break;
5980                 case VMCS_FIELD_TYPE_U64:
5981                         field_value = vmcs_read64(field);
5982                         break;
5983                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5984                         field_value = vmcs_readl(field);
5985                         break;
5986                 }
5987                 vmcs12_write_any(&vmx->vcpu, field, field_value);
5988         }
5989
5990         vmcs_clear(shadow_vmcs);
5991         vmcs_load(vmx->loaded_vmcs->vmcs);
5992 }
5993
5994 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
5995 {
5996         unsigned long *fields[] = {
5997                 (unsigned long *)shadow_read_write_fields,
5998                 (unsigned long *)shadow_read_only_fields
5999         };
6000         int num_lists =  ARRAY_SIZE(fields);
6001         int max_fields[] = {
6002                 max_shadow_read_write_fields,
6003                 max_shadow_read_only_fields
6004         };
6005         int i, q;
6006         unsigned long field;
6007         u64 field_value = 0;
6008         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6009
6010         vmcs_load(shadow_vmcs);
6011
6012         for (q = 0; q < num_lists; q++) {
6013                 for (i = 0; i < max_fields[q]; i++) {
6014                         field = fields[q][i];
6015                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
6016
6017                         switch (vmcs_field_type(field)) {
6018                         case VMCS_FIELD_TYPE_U16:
6019                                 vmcs_write16(field, (u16)field_value);
6020                                 break;
6021                         case VMCS_FIELD_TYPE_U32:
6022                                 vmcs_write32(field, (u32)field_value);
6023                                 break;
6024                         case VMCS_FIELD_TYPE_U64:
6025                                 vmcs_write64(field, (u64)field_value);
6026                                 break;
6027                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6028                                 vmcs_writel(field, (long)field_value);
6029                                 break;
6030                         }
6031                 }
6032         }
6033
6034         vmcs_clear(shadow_vmcs);
6035         vmcs_load(vmx->loaded_vmcs->vmcs);
6036 }
6037
6038 /*
6039  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6040  * used before) all generate the same failure when it is missing.
6041  */
6042 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6043 {
6044         struct vcpu_vmx *vmx = to_vmx(vcpu);
6045         if (vmx->nested.current_vmptr == -1ull) {
6046                 nested_vmx_failInvalid(vcpu);
6047                 skip_emulated_instruction(vcpu);
6048                 return 0;
6049         }
6050         return 1;
6051 }
6052
6053 static int handle_vmread(struct kvm_vcpu *vcpu)
6054 {
6055         unsigned long field;
6056         u64 field_value;
6057         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6058         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6059         gva_t gva = 0;
6060
6061         if (!nested_vmx_check_permission(vcpu) ||
6062             !nested_vmx_check_vmcs12(vcpu))
6063                 return 1;
6064
6065         /* Decode instruction info and find the field to read */
6066         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6067         /* Read the field, zero-extended to a u64 field_value */
6068         if (!vmcs12_read_any(vcpu, field, &field_value)) {
6069                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6070                 skip_emulated_instruction(vcpu);
6071                 return 1;
6072         }
6073         /*
6074          * Now copy part of this value to register or memory, as requested.
6075          * Note that the number of bits actually copied is 32 or 64 depending
6076          * on the guest's mode (32 or 64 bit), not on the given field's length.
6077          */
6078         if (vmx_instruction_info & (1u << 10)) {
6079                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6080                         field_value);
6081         } else {
6082                 if (get_vmx_mem_address(vcpu, exit_qualification,
6083                                 vmx_instruction_info, &gva))
6084                         return 1;
6085                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6086                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6087                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6088         }
6089
6090         nested_vmx_succeed(vcpu);
6091         skip_emulated_instruction(vcpu);
6092         return 1;
6093 }
6094
6095
6096 static int handle_vmwrite(struct kvm_vcpu *vcpu)
6097 {
6098         unsigned long field;
6099         gva_t gva;
6100         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6101         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6102         /* The value to write might be 32 or 64 bits, depending on L1's long
6103          * mode, and eventually we need to write that into a field of several
6104          * possible lengths. The code below first zero-extends the value to 64
6105          * bit (field_value), and then copies only the approriate number of
6106          * bits into the vmcs12 field.
6107          */
6108         u64 field_value = 0;
6109         struct x86_exception e;
6110
6111         if (!nested_vmx_check_permission(vcpu) ||
6112             !nested_vmx_check_vmcs12(vcpu))
6113                 return 1;
6114
6115         if (vmx_instruction_info & (1u << 10))
6116                 field_value = kvm_register_read(vcpu,
6117                         (((vmx_instruction_info) >> 3) & 0xf));
6118         else {
6119                 if (get_vmx_mem_address(vcpu, exit_qualification,
6120                                 vmx_instruction_info, &gva))
6121                         return 1;
6122                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6123                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6124                         kvm_inject_page_fault(vcpu, &e);
6125                         return 1;
6126                 }
6127         }
6128
6129
6130         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6131         if (vmcs_field_readonly(field)) {
6132                 nested_vmx_failValid(vcpu,
6133                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6134                 skip_emulated_instruction(vcpu);
6135                 return 1;
6136         }
6137
6138         if (!vmcs12_write_any(vcpu, field, field_value)) {
6139                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6140                 skip_emulated_instruction(vcpu);
6141                 return 1;
6142         }
6143
6144         nested_vmx_succeed(vcpu);
6145         skip_emulated_instruction(vcpu);
6146         return 1;
6147 }
6148
6149 /* Emulate the VMPTRLD instruction */
6150 static int handle_vmptrld(struct kvm_vcpu *vcpu)
6151 {
6152         struct vcpu_vmx *vmx = to_vmx(vcpu);
6153         gva_t gva;
6154         gpa_t vmptr;
6155         struct x86_exception e;
6156         u32 exec_control;
6157
6158         if (!nested_vmx_check_permission(vcpu))
6159                 return 1;
6160
6161         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6162                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6163                 return 1;
6164
6165         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6166                                 sizeof(vmptr), &e)) {
6167                 kvm_inject_page_fault(vcpu, &e);
6168                 return 1;
6169         }
6170
6171         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6172                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6173                 skip_emulated_instruction(vcpu);
6174                 return 1;
6175         }
6176
6177         if (vmx->nested.current_vmptr != vmptr) {
6178                 struct vmcs12 *new_vmcs12;
6179                 struct page *page;
6180                 page = nested_get_page(vcpu, vmptr);
6181                 if (page == NULL) {
6182                         nested_vmx_failInvalid(vcpu);
6183                         skip_emulated_instruction(vcpu);
6184                         return 1;
6185                 }
6186                 new_vmcs12 = kmap(page);
6187                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6188                         kunmap(page);
6189                         nested_release_page_clean(page);
6190                         nested_vmx_failValid(vcpu,
6191                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6192                         skip_emulated_instruction(vcpu);
6193                         return 1;
6194                 }
6195                 if (vmx->nested.current_vmptr != -1ull)
6196                         nested_release_vmcs12(vmx);
6197
6198                 vmx->nested.current_vmptr = vmptr;
6199                 vmx->nested.current_vmcs12 = new_vmcs12;
6200                 vmx->nested.current_vmcs12_page = page;
6201                 if (enable_shadow_vmcs) {
6202                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6203                         exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6204                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6205                         vmcs_write64(VMCS_LINK_POINTER,
6206                                      __pa(vmx->nested.current_shadow_vmcs));
6207                         vmx->nested.sync_shadow_vmcs = true;
6208                 }
6209         }
6210
6211         nested_vmx_succeed(vcpu);
6212         skip_emulated_instruction(vcpu);
6213         return 1;
6214 }
6215
6216 /* Emulate the VMPTRST instruction */
6217 static int handle_vmptrst(struct kvm_vcpu *vcpu)
6218 {
6219         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6220         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6221         gva_t vmcs_gva;
6222         struct x86_exception e;
6223
6224         if (!nested_vmx_check_permission(vcpu))
6225                 return 1;
6226
6227         if (get_vmx_mem_address(vcpu, exit_qualification,
6228                         vmx_instruction_info, &vmcs_gva))
6229                 return 1;
6230         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6231         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6232                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
6233                                  sizeof(u64), &e)) {
6234                 kvm_inject_page_fault(vcpu, &e);
6235                 return 1;
6236         }
6237         nested_vmx_succeed(vcpu);
6238         skip_emulated_instruction(vcpu);
6239         return 1;
6240 }
6241
6242 /*
6243  * The exit handlers return 1 if the exit was handled fully and guest execution
6244  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
6245  * to be done to userspace and return 0.
6246  */
6247 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6248         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
6249         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
6250         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
6251         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
6252         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
6253         [EXIT_REASON_CR_ACCESS]               = handle_cr,
6254         [EXIT_REASON_DR_ACCESS]               = handle_dr,
6255         [EXIT_REASON_CPUID]                   = handle_cpuid,
6256         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
6257         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
6258         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
6259         [EXIT_REASON_HLT]                     = handle_halt,
6260         [EXIT_REASON_INVD]                    = handle_invd,
6261         [EXIT_REASON_INVLPG]                  = handle_invlpg,
6262         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
6263         [EXIT_REASON_VMCALL]                  = handle_vmcall,
6264         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
6265         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
6266         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
6267         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
6268         [EXIT_REASON_VMREAD]                  = handle_vmread,
6269         [EXIT_REASON_VMRESUME]                = handle_vmresume,
6270         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
6271         [EXIT_REASON_VMOFF]                   = handle_vmoff,
6272         [EXIT_REASON_VMON]                    = handle_vmon,
6273         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
6274         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
6275         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
6276         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
6277         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
6278         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
6279         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
6280         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
6281         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
6282         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
6283         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
6284         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
6285         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
6286 };
6287
6288 static const int kvm_vmx_max_exit_handlers =
6289         ARRAY_SIZE(kvm_vmx_exit_handlers);
6290
6291 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6292                                        struct vmcs12 *vmcs12)
6293 {
6294         unsigned long exit_qualification;
6295         gpa_t bitmap, last_bitmap;
6296         unsigned int port;
6297         int size;
6298         u8 b;
6299
6300         if (nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING))
6301                 return 1;
6302
6303         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6304                 return 0;
6305
6306         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6307
6308         port = exit_qualification >> 16;
6309         size = (exit_qualification & 7) + 1;
6310
6311         last_bitmap = (gpa_t)-1;
6312         b = -1;
6313
6314         while (size > 0) {
6315                 if (port < 0x8000)
6316                         bitmap = vmcs12->io_bitmap_a;
6317                 else if (port < 0x10000)
6318                         bitmap = vmcs12->io_bitmap_b;
6319                 else
6320                         return 1;
6321                 bitmap += (port & 0x7fff) / 8;
6322
6323                 if (last_bitmap != bitmap)
6324                         if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6325                                 return 1;
6326                 if (b & (1 << (port & 7)))
6327                         return 1;
6328
6329                 port++;
6330                 size--;
6331                 last_bitmap = bitmap;
6332         }
6333
6334         return 0;
6335 }
6336
6337 /*
6338  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6339  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6340  * disinterest in the current event (read or write a specific MSR) by using an
6341  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6342  */
6343 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6344         struct vmcs12 *vmcs12, u32 exit_reason)
6345 {
6346         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6347         gpa_t bitmap;
6348
6349         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
6350                 return 1;
6351
6352         /*
6353          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6354          * for the four combinations of read/write and low/high MSR numbers.
6355          * First we need to figure out which of the four to use:
6356          */
6357         bitmap = vmcs12->msr_bitmap;
6358         if (exit_reason == EXIT_REASON_MSR_WRITE)
6359                 bitmap += 2048;
6360         if (msr_index >= 0xc0000000) {
6361                 msr_index -= 0xc0000000;
6362                 bitmap += 1024;
6363         }
6364
6365         /* Then read the msr_index'th bit from this bitmap: */
6366         if (msr_index < 1024*8) {
6367                 unsigned char b;
6368                 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6369                         return 1;
6370                 return 1 & (b >> (msr_index & 7));
6371         } else
6372                 return 1; /* let L1 handle the wrong parameter */
6373 }
6374
6375 /*
6376  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6377  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6378  * intercept (via guest_host_mask etc.) the current event.
6379  */
6380 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6381         struct vmcs12 *vmcs12)
6382 {
6383         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6384         int cr = exit_qualification & 15;
6385         int reg = (exit_qualification >> 8) & 15;
6386         unsigned long val = kvm_register_read(vcpu, reg);
6387
6388         switch ((exit_qualification >> 4) & 3) {
6389         case 0: /* mov to cr */
6390                 switch (cr) {
6391                 case 0:
6392                         if (vmcs12->cr0_guest_host_mask &
6393                             (val ^ vmcs12->cr0_read_shadow))
6394                                 return 1;
6395                         break;
6396                 case 3:
6397                         if ((vmcs12->cr3_target_count >= 1 &&
6398                                         vmcs12->cr3_target_value0 == val) ||
6399                                 (vmcs12->cr3_target_count >= 2 &&
6400