4e49caf9224dcc51f8bb15bdedd86527447c4d35
[linux-3.10.git] / arch / x86 / kvm / vmx.c
1 /*
2  * Kernel-based Virtual Machine driver for Linux
3  *
4  * This module enables machines with Intel VT-x extensions to run virtual
5  * machines without emulation or binary translation.
6  *
7  * Copyright (C) 2006 Qumranet, Inc.
8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
9  *
10  * Authors:
11  *   Avi Kivity   <avi@qumranet.com>
12  *   Yaniv Kamay  <yaniv@qumranet.com>
13  *
14  * This work is licensed under the terms of the GNU GPL, version 2.  See
15  * the COPYING file in the top-level directory.
16  *
17  */
18
19 #include "irq.h"
20 #include "mmu.h"
21 #include "cpuid.h"
22
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/mm.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include "kvm_cache_regs.h"
35 #include "x86.h"
36
37 #include <asm/io.h>
38 #include <asm/desc.h>
39 #include <asm/vmx.h>
40 #include <asm/virtext.h>
41 #include <asm/mce.h>
42 #include <asm/i387.h>
43 #include <asm/xcr.h>
44 #include <asm/perf_event.h>
45
46 #include "trace.h"
47
48 #define __ex(x) __kvm_handle_fault_on_reboot(x)
49 #define __ex_clear(x, reg) \
50         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
51
52 MODULE_AUTHOR("Qumranet");
53 MODULE_LICENSE("GPL");
54
55 static const struct x86_cpu_id vmx_cpu_id[] = {
56         X86_FEATURE_MATCH(X86_FEATURE_VMX),
57         {}
58 };
59 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
60
61 static bool __read_mostly enable_vpid = 1;
62 module_param_named(vpid, enable_vpid, bool, 0444);
63
64 static bool __read_mostly flexpriority_enabled = 1;
65 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
66
67 static bool __read_mostly enable_ept = 1;
68 module_param_named(ept, enable_ept, bool, S_IRUGO);
69
70 static bool __read_mostly enable_unrestricted_guest = 1;
71 module_param_named(unrestricted_guest,
72                         enable_unrestricted_guest, bool, S_IRUGO);
73
74 static bool __read_mostly enable_ept_ad_bits = 1;
75 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
76
77 static bool __read_mostly emulate_invalid_guest_state = true;
78 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
79
80 static bool __read_mostly vmm_exclusive = 1;
81 module_param(vmm_exclusive, bool, S_IRUGO);
82
83 static bool __read_mostly fasteoi = 1;
84 module_param(fasteoi, bool, S_IRUGO);
85
86 /*
87  * If nested=1, nested virtualization is supported, i.e., guests may use
88  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
89  * use VMX instructions.
90  */
91 static bool __read_mostly nested = 0;
92 module_param(nested, bool, S_IRUGO);
93
94 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
95         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
96 #define KVM_GUEST_CR0_MASK                                              \
97         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
98 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
99         (X86_CR0_WP | X86_CR0_NE)
100 #define KVM_VM_CR0_ALWAYS_ON                                            \
101         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
102 #define KVM_CR4_GUEST_OWNED_BITS                                      \
103         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
104          | X86_CR4_OSXMMEXCPT)
105
106 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
107 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
108
109 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
110
111 /*
112  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
113  * ple_gap:    upper bound on the amount of time between two successive
114  *             executions of PAUSE in a loop. Also indicate if ple enabled.
115  *             According to test, this time is usually smaller than 128 cycles.
116  * ple_window: upper bound on the amount of time a guest is allowed to execute
117  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
118  *             less than 2^12 cycles
119  * Time is measured based on a counter that runs at the same rate as the TSC,
120  * refer SDM volume 3b section 21.6.13 & 22.1.3.
121  */
122 #define KVM_VMX_DEFAULT_PLE_GAP    128
123 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
124 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
125 module_param(ple_gap, int, S_IRUGO);
126
127 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
128 module_param(ple_window, int, S_IRUGO);
129
130 #define NR_AUTOLOAD_MSRS 8
131 #define VMCS02_POOL_SIZE 1
132
133 struct vmcs {
134         u32 revision_id;
135         u32 abort;
136         char data[0];
137 };
138
139 /*
140  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
141  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
142  * loaded on this CPU (so we can clear them if the CPU goes down).
143  */
144 struct loaded_vmcs {
145         struct vmcs *vmcs;
146         int cpu;
147         int launched;
148         struct list_head loaded_vmcss_on_cpu_link;
149 };
150
151 struct shared_msr_entry {
152         unsigned index;
153         u64 data;
154         u64 mask;
155 };
156
157 /*
158  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
159  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
160  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
161  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
162  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
163  * More than one of these structures may exist, if L1 runs multiple L2 guests.
164  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
165  * underlying hardware which will be used to run L2.
166  * This structure is packed to ensure that its layout is identical across
167  * machines (necessary for live migration).
168  * If there are changes in this struct, VMCS12_REVISION must be changed.
169  */
170 typedef u64 natural_width;
171 struct __packed vmcs12 {
172         /* According to the Intel spec, a VMCS region must start with the
173          * following two fields. Then follow implementation-specific data.
174          */
175         u32 revision_id;
176         u32 abort;
177
178         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
179         u32 padding[7]; /* room for future expansion */
180
181         u64 io_bitmap_a;
182         u64 io_bitmap_b;
183         u64 msr_bitmap;
184         u64 vm_exit_msr_store_addr;
185         u64 vm_exit_msr_load_addr;
186         u64 vm_entry_msr_load_addr;
187         u64 tsc_offset;
188         u64 virtual_apic_page_addr;
189         u64 apic_access_addr;
190         u64 ept_pointer;
191         u64 guest_physical_address;
192         u64 vmcs_link_pointer;
193         u64 guest_ia32_debugctl;
194         u64 guest_ia32_pat;
195         u64 guest_ia32_efer;
196         u64 guest_ia32_perf_global_ctrl;
197         u64 guest_pdptr0;
198         u64 guest_pdptr1;
199         u64 guest_pdptr2;
200         u64 guest_pdptr3;
201         u64 host_ia32_pat;
202         u64 host_ia32_efer;
203         u64 host_ia32_perf_global_ctrl;
204         u64 padding64[8]; /* room for future expansion */
205         /*
206          * To allow migration of L1 (complete with its L2 guests) between
207          * machines of different natural widths (32 or 64 bit), we cannot have
208          * unsigned long fields with no explict size. We use u64 (aliased
209          * natural_width) instead. Luckily, x86 is little-endian.
210          */
211         natural_width cr0_guest_host_mask;
212         natural_width cr4_guest_host_mask;
213         natural_width cr0_read_shadow;
214         natural_width cr4_read_shadow;
215         natural_width cr3_target_value0;
216         natural_width cr3_target_value1;
217         natural_width cr3_target_value2;
218         natural_width cr3_target_value3;
219         natural_width exit_qualification;
220         natural_width guest_linear_address;
221         natural_width guest_cr0;
222         natural_width guest_cr3;
223         natural_width guest_cr4;
224         natural_width guest_es_base;
225         natural_width guest_cs_base;
226         natural_width guest_ss_base;
227         natural_width guest_ds_base;
228         natural_width guest_fs_base;
229         natural_width guest_gs_base;
230         natural_width guest_ldtr_base;
231         natural_width guest_tr_base;
232         natural_width guest_gdtr_base;
233         natural_width guest_idtr_base;
234         natural_width guest_dr7;
235         natural_width guest_rsp;
236         natural_width guest_rip;
237         natural_width guest_rflags;
238         natural_width guest_pending_dbg_exceptions;
239         natural_width guest_sysenter_esp;
240         natural_width guest_sysenter_eip;
241         natural_width host_cr0;
242         natural_width host_cr3;
243         natural_width host_cr4;
244         natural_width host_fs_base;
245         natural_width host_gs_base;
246         natural_width host_tr_base;
247         natural_width host_gdtr_base;
248         natural_width host_idtr_base;
249         natural_width host_ia32_sysenter_esp;
250         natural_width host_ia32_sysenter_eip;
251         natural_width host_rsp;
252         natural_width host_rip;
253         natural_width paddingl[8]; /* room for future expansion */
254         u32 pin_based_vm_exec_control;
255         u32 cpu_based_vm_exec_control;
256         u32 exception_bitmap;
257         u32 page_fault_error_code_mask;
258         u32 page_fault_error_code_match;
259         u32 cr3_target_count;
260         u32 vm_exit_controls;
261         u32 vm_exit_msr_store_count;
262         u32 vm_exit_msr_load_count;
263         u32 vm_entry_controls;
264         u32 vm_entry_msr_load_count;
265         u32 vm_entry_intr_info_field;
266         u32 vm_entry_exception_error_code;
267         u32 vm_entry_instruction_len;
268         u32 tpr_threshold;
269         u32 secondary_vm_exec_control;
270         u32 vm_instruction_error;
271         u32 vm_exit_reason;
272         u32 vm_exit_intr_info;
273         u32 vm_exit_intr_error_code;
274         u32 idt_vectoring_info_field;
275         u32 idt_vectoring_error_code;
276         u32 vm_exit_instruction_len;
277         u32 vmx_instruction_info;
278         u32 guest_es_limit;
279         u32 guest_cs_limit;
280         u32 guest_ss_limit;
281         u32 guest_ds_limit;
282         u32 guest_fs_limit;
283         u32 guest_gs_limit;
284         u32 guest_ldtr_limit;
285         u32 guest_tr_limit;
286         u32 guest_gdtr_limit;
287         u32 guest_idtr_limit;
288         u32 guest_es_ar_bytes;
289         u32 guest_cs_ar_bytes;
290         u32 guest_ss_ar_bytes;
291         u32 guest_ds_ar_bytes;
292         u32 guest_fs_ar_bytes;
293         u32 guest_gs_ar_bytes;
294         u32 guest_ldtr_ar_bytes;
295         u32 guest_tr_ar_bytes;
296         u32 guest_interruptibility_info;
297         u32 guest_activity_state;
298         u32 guest_sysenter_cs;
299         u32 host_ia32_sysenter_cs;
300         u32 padding32[8]; /* room for future expansion */
301         u16 virtual_processor_id;
302         u16 guest_es_selector;
303         u16 guest_cs_selector;
304         u16 guest_ss_selector;
305         u16 guest_ds_selector;
306         u16 guest_fs_selector;
307         u16 guest_gs_selector;
308         u16 guest_ldtr_selector;
309         u16 guest_tr_selector;
310         u16 host_es_selector;
311         u16 host_cs_selector;
312         u16 host_ss_selector;
313         u16 host_ds_selector;
314         u16 host_fs_selector;
315         u16 host_gs_selector;
316         u16 host_tr_selector;
317 };
318
319 /*
320  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
321  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
322  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
323  */
324 #define VMCS12_REVISION 0x11e57ed0
325
326 /*
327  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
328  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
329  * current implementation, 4K are reserved to avoid future complications.
330  */
331 #define VMCS12_SIZE 0x1000
332
333 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
334 struct vmcs02_list {
335         struct list_head list;
336         gpa_t vmptr;
337         struct loaded_vmcs vmcs02;
338 };
339
340 /*
341  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
342  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
343  */
344 struct nested_vmx {
345         /* Has the level1 guest done vmxon? */
346         bool vmxon;
347
348         /* The guest-physical address of the current VMCS L1 keeps for L2 */
349         gpa_t current_vmptr;
350         /* The host-usable pointer to the above */
351         struct page *current_vmcs12_page;
352         struct vmcs12 *current_vmcs12;
353
354         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
355         struct list_head vmcs02_pool;
356         int vmcs02_num;
357         u64 vmcs01_tsc_offset;
358         /* L2 must run next, and mustn't decide to exit to L1. */
359         bool nested_run_pending;
360         /*
361          * Guest pages referred to in vmcs02 with host-physical pointers, so
362          * we must keep them pinned while L2 runs.
363          */
364         struct page *apic_access_page;
365 };
366
367 struct vcpu_vmx {
368         struct kvm_vcpu       vcpu;
369         unsigned long         host_rsp;
370         u8                    fail;
371         u8                    cpl;
372         bool                  nmi_known_unmasked;
373         u32                   exit_intr_info;
374         u32                   idt_vectoring_info;
375         ulong                 rflags;
376         struct shared_msr_entry *guest_msrs;
377         int                   nmsrs;
378         int                   save_nmsrs;
379 #ifdef CONFIG_X86_64
380         u64                   msr_host_kernel_gs_base;
381         u64                   msr_guest_kernel_gs_base;
382 #endif
383         /*
384          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
385          * non-nested (L1) guest, it always points to vmcs01. For a nested
386          * guest (L2), it points to a different VMCS.
387          */
388         struct loaded_vmcs    vmcs01;
389         struct loaded_vmcs   *loaded_vmcs;
390         bool                  __launched; /* temporary, used in vmx_vcpu_run */
391         struct msr_autoload {
392                 unsigned nr;
393                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
394                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
395         } msr_autoload;
396         struct {
397                 int           loaded;
398                 u16           fs_sel, gs_sel, ldt_sel;
399 #ifdef CONFIG_X86_64
400                 u16           ds_sel, es_sel;
401 #endif
402                 int           gs_ldt_reload_needed;
403                 int           fs_reload_needed;
404         } host_state;
405         struct {
406                 int vm86_active;
407                 ulong save_rflags;
408                 struct kvm_save_segment {
409                         u16 selector;
410                         unsigned long base;
411                         u32 limit;
412                         u32 ar;
413                 } tr, es, ds, fs, gs;
414         } rmode;
415         struct {
416                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
417                 struct kvm_save_segment seg[8];
418         } segment_cache;
419         int vpid;
420         bool emulation_required;
421
422         /* Support for vnmi-less CPUs */
423         int soft_vnmi_blocked;
424         ktime_t entry_time;
425         s64 vnmi_blocked_time;
426         u32 exit_reason;
427
428         bool rdtscp_enabled;
429
430         /* Support for a guest hypervisor (nested VMX) */
431         struct nested_vmx nested;
432 };
433
434 enum segment_cache_field {
435         SEG_FIELD_SEL = 0,
436         SEG_FIELD_BASE = 1,
437         SEG_FIELD_LIMIT = 2,
438         SEG_FIELD_AR = 3,
439
440         SEG_FIELD_NR = 4
441 };
442
443 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
444 {
445         return container_of(vcpu, struct vcpu_vmx, vcpu);
446 }
447
448 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
449 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
450 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
451                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
452
453 static unsigned short vmcs_field_to_offset_table[] = {
454         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
455         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
456         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
457         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
458         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
459         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
460         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
461         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
462         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
463         FIELD(HOST_ES_SELECTOR, host_es_selector),
464         FIELD(HOST_CS_SELECTOR, host_cs_selector),
465         FIELD(HOST_SS_SELECTOR, host_ss_selector),
466         FIELD(HOST_DS_SELECTOR, host_ds_selector),
467         FIELD(HOST_FS_SELECTOR, host_fs_selector),
468         FIELD(HOST_GS_SELECTOR, host_gs_selector),
469         FIELD(HOST_TR_SELECTOR, host_tr_selector),
470         FIELD64(IO_BITMAP_A, io_bitmap_a),
471         FIELD64(IO_BITMAP_B, io_bitmap_b),
472         FIELD64(MSR_BITMAP, msr_bitmap),
473         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
474         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
475         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
476         FIELD64(TSC_OFFSET, tsc_offset),
477         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
478         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
479         FIELD64(EPT_POINTER, ept_pointer),
480         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
481         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
482         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
483         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
484         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
485         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
486         FIELD64(GUEST_PDPTR0, guest_pdptr0),
487         FIELD64(GUEST_PDPTR1, guest_pdptr1),
488         FIELD64(GUEST_PDPTR2, guest_pdptr2),
489         FIELD64(GUEST_PDPTR3, guest_pdptr3),
490         FIELD64(HOST_IA32_PAT, host_ia32_pat),
491         FIELD64(HOST_IA32_EFER, host_ia32_efer),
492         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
493         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
494         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
495         FIELD(EXCEPTION_BITMAP, exception_bitmap),
496         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
497         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
498         FIELD(CR3_TARGET_COUNT, cr3_target_count),
499         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
500         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
501         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
502         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
503         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
504         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
505         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
506         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
507         FIELD(TPR_THRESHOLD, tpr_threshold),
508         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
509         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
510         FIELD(VM_EXIT_REASON, vm_exit_reason),
511         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
512         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
513         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
514         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
515         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
516         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
517         FIELD(GUEST_ES_LIMIT, guest_es_limit),
518         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
519         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
520         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
521         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
522         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
523         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
524         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
525         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
526         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
527         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
528         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
529         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
530         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
531         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
532         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
533         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
534         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
535         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
536         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
537         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
538         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
539         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
540         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
541         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
542         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
543         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
544         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
545         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
546         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
547         FIELD(EXIT_QUALIFICATION, exit_qualification),
548         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
549         FIELD(GUEST_CR0, guest_cr0),
550         FIELD(GUEST_CR3, guest_cr3),
551         FIELD(GUEST_CR4, guest_cr4),
552         FIELD(GUEST_ES_BASE, guest_es_base),
553         FIELD(GUEST_CS_BASE, guest_cs_base),
554         FIELD(GUEST_SS_BASE, guest_ss_base),
555         FIELD(GUEST_DS_BASE, guest_ds_base),
556         FIELD(GUEST_FS_BASE, guest_fs_base),
557         FIELD(GUEST_GS_BASE, guest_gs_base),
558         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
559         FIELD(GUEST_TR_BASE, guest_tr_base),
560         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
561         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
562         FIELD(GUEST_DR7, guest_dr7),
563         FIELD(GUEST_RSP, guest_rsp),
564         FIELD(GUEST_RIP, guest_rip),
565         FIELD(GUEST_RFLAGS, guest_rflags),
566         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
567         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
568         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
569         FIELD(HOST_CR0, host_cr0),
570         FIELD(HOST_CR3, host_cr3),
571         FIELD(HOST_CR4, host_cr4),
572         FIELD(HOST_FS_BASE, host_fs_base),
573         FIELD(HOST_GS_BASE, host_gs_base),
574         FIELD(HOST_TR_BASE, host_tr_base),
575         FIELD(HOST_GDTR_BASE, host_gdtr_base),
576         FIELD(HOST_IDTR_BASE, host_idtr_base),
577         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
578         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
579         FIELD(HOST_RSP, host_rsp),
580         FIELD(HOST_RIP, host_rip),
581 };
582 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
583
584 static inline short vmcs_field_to_offset(unsigned long field)
585 {
586         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
587                 return -1;
588         return vmcs_field_to_offset_table[field];
589 }
590
591 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
592 {
593         return to_vmx(vcpu)->nested.current_vmcs12;
594 }
595
596 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
597 {
598         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
599         if (is_error_page(page))
600                 return NULL;
601
602         return page;
603 }
604
605 static void nested_release_page(struct page *page)
606 {
607         kvm_release_page_dirty(page);
608 }
609
610 static void nested_release_page_clean(struct page *page)
611 {
612         kvm_release_page_clean(page);
613 }
614
615 static u64 construct_eptp(unsigned long root_hpa);
616 static void kvm_cpu_vmxon(u64 addr);
617 static void kvm_cpu_vmxoff(void);
618 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
619 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
620 static void vmx_set_segment(struct kvm_vcpu *vcpu,
621                             struct kvm_segment *var, int seg);
622 static void vmx_get_segment(struct kvm_vcpu *vcpu,
623                             struct kvm_segment *var, int seg);
624
625 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
626 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
627 /*
628  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
629  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
630  */
631 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
632 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
633
634 static unsigned long *vmx_io_bitmap_a;
635 static unsigned long *vmx_io_bitmap_b;
636 static unsigned long *vmx_msr_bitmap_legacy;
637 static unsigned long *vmx_msr_bitmap_longmode;
638
639 static bool cpu_has_load_ia32_efer;
640 static bool cpu_has_load_perf_global_ctrl;
641
642 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
643 static DEFINE_SPINLOCK(vmx_vpid_lock);
644
645 static struct vmcs_config {
646         int size;
647         int order;
648         u32 revision_id;
649         u32 pin_based_exec_ctrl;
650         u32 cpu_based_exec_ctrl;
651         u32 cpu_based_2nd_exec_ctrl;
652         u32 vmexit_ctrl;
653         u32 vmentry_ctrl;
654 } vmcs_config;
655
656 static struct vmx_capability {
657         u32 ept;
658         u32 vpid;
659 } vmx_capability;
660
661 #define VMX_SEGMENT_FIELD(seg)                                  \
662         [VCPU_SREG_##seg] = {                                   \
663                 .selector = GUEST_##seg##_SELECTOR,             \
664                 .base = GUEST_##seg##_BASE,                     \
665                 .limit = GUEST_##seg##_LIMIT,                   \
666                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
667         }
668
669 static struct kvm_vmx_segment_field {
670         unsigned selector;
671         unsigned base;
672         unsigned limit;
673         unsigned ar_bytes;
674 } kvm_vmx_segment_fields[] = {
675         VMX_SEGMENT_FIELD(CS),
676         VMX_SEGMENT_FIELD(DS),
677         VMX_SEGMENT_FIELD(ES),
678         VMX_SEGMENT_FIELD(FS),
679         VMX_SEGMENT_FIELD(GS),
680         VMX_SEGMENT_FIELD(SS),
681         VMX_SEGMENT_FIELD(TR),
682         VMX_SEGMENT_FIELD(LDTR),
683 };
684
685 static u64 host_efer;
686
687 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
688
689 /*
690  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
691  * away by decrementing the array size.
692  */
693 static const u32 vmx_msr_index[] = {
694 #ifdef CONFIG_X86_64
695         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
696 #endif
697         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
698 };
699 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
700
701 static inline bool is_page_fault(u32 intr_info)
702 {
703         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
704                              INTR_INFO_VALID_MASK)) ==
705                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
706 }
707
708 static inline bool is_no_device(u32 intr_info)
709 {
710         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
711                              INTR_INFO_VALID_MASK)) ==
712                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
713 }
714
715 static inline bool is_invalid_opcode(u32 intr_info)
716 {
717         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
718                              INTR_INFO_VALID_MASK)) ==
719                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
720 }
721
722 static inline bool is_external_interrupt(u32 intr_info)
723 {
724         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
725                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
726 }
727
728 static inline bool is_machine_check(u32 intr_info)
729 {
730         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
731                              INTR_INFO_VALID_MASK)) ==
732                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
733 }
734
735 static inline bool cpu_has_vmx_msr_bitmap(void)
736 {
737         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
738 }
739
740 static inline bool cpu_has_vmx_tpr_shadow(void)
741 {
742         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
743 }
744
745 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
746 {
747         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
748 }
749
750 static inline bool cpu_has_secondary_exec_ctrls(void)
751 {
752         return vmcs_config.cpu_based_exec_ctrl &
753                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
754 }
755
756 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
757 {
758         return vmcs_config.cpu_based_2nd_exec_ctrl &
759                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
760 }
761
762 static inline bool cpu_has_vmx_flexpriority(void)
763 {
764         return cpu_has_vmx_tpr_shadow() &&
765                 cpu_has_vmx_virtualize_apic_accesses();
766 }
767
768 static inline bool cpu_has_vmx_ept_execute_only(void)
769 {
770         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
771 }
772
773 static inline bool cpu_has_vmx_eptp_uncacheable(void)
774 {
775         return vmx_capability.ept & VMX_EPTP_UC_BIT;
776 }
777
778 static inline bool cpu_has_vmx_eptp_writeback(void)
779 {
780         return vmx_capability.ept & VMX_EPTP_WB_BIT;
781 }
782
783 static inline bool cpu_has_vmx_ept_2m_page(void)
784 {
785         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
786 }
787
788 static inline bool cpu_has_vmx_ept_1g_page(void)
789 {
790         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
791 }
792
793 static inline bool cpu_has_vmx_ept_4levels(void)
794 {
795         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
796 }
797
798 static inline bool cpu_has_vmx_ept_ad_bits(void)
799 {
800         return vmx_capability.ept & VMX_EPT_AD_BIT;
801 }
802
803 static inline bool cpu_has_vmx_invept_individual_addr(void)
804 {
805         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
806 }
807
808 static inline bool cpu_has_vmx_invept_context(void)
809 {
810         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
811 }
812
813 static inline bool cpu_has_vmx_invept_global(void)
814 {
815         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
816 }
817
818 static inline bool cpu_has_vmx_invvpid_single(void)
819 {
820         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
821 }
822
823 static inline bool cpu_has_vmx_invvpid_global(void)
824 {
825         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
826 }
827
828 static inline bool cpu_has_vmx_ept(void)
829 {
830         return vmcs_config.cpu_based_2nd_exec_ctrl &
831                 SECONDARY_EXEC_ENABLE_EPT;
832 }
833
834 static inline bool cpu_has_vmx_unrestricted_guest(void)
835 {
836         return vmcs_config.cpu_based_2nd_exec_ctrl &
837                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
838 }
839
840 static inline bool cpu_has_vmx_ple(void)
841 {
842         return vmcs_config.cpu_based_2nd_exec_ctrl &
843                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
844 }
845
846 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
847 {
848         return flexpriority_enabled && irqchip_in_kernel(kvm);
849 }
850
851 static inline bool cpu_has_vmx_vpid(void)
852 {
853         return vmcs_config.cpu_based_2nd_exec_ctrl &
854                 SECONDARY_EXEC_ENABLE_VPID;
855 }
856
857 static inline bool cpu_has_vmx_rdtscp(void)
858 {
859         return vmcs_config.cpu_based_2nd_exec_ctrl &
860                 SECONDARY_EXEC_RDTSCP;
861 }
862
863 static inline bool cpu_has_vmx_invpcid(void)
864 {
865         return vmcs_config.cpu_based_2nd_exec_ctrl &
866                 SECONDARY_EXEC_ENABLE_INVPCID;
867 }
868
869 static inline bool cpu_has_virtual_nmis(void)
870 {
871         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
872 }
873
874 static inline bool cpu_has_vmx_wbinvd_exit(void)
875 {
876         return vmcs_config.cpu_based_2nd_exec_ctrl &
877                 SECONDARY_EXEC_WBINVD_EXITING;
878 }
879
880 static inline bool report_flexpriority(void)
881 {
882         return flexpriority_enabled;
883 }
884
885 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
886 {
887         return vmcs12->cpu_based_vm_exec_control & bit;
888 }
889
890 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
891 {
892         return (vmcs12->cpu_based_vm_exec_control &
893                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
894                 (vmcs12->secondary_vm_exec_control & bit);
895 }
896
897 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
898         struct kvm_vcpu *vcpu)
899 {
900         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
901 }
902
903 static inline bool is_exception(u32 intr_info)
904 {
905         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
906                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
907 }
908
909 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
910 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
911                         struct vmcs12 *vmcs12,
912                         u32 reason, unsigned long qualification);
913
914 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
915 {
916         int i;
917
918         for (i = 0; i < vmx->nmsrs; ++i)
919                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
920                         return i;
921         return -1;
922 }
923
924 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
925 {
926     struct {
927         u64 vpid : 16;
928         u64 rsvd : 48;
929         u64 gva;
930     } operand = { vpid, 0, gva };
931
932     asm volatile (__ex(ASM_VMX_INVVPID)
933                   /* CF==1 or ZF==1 --> rc = -1 */
934                   "; ja 1f ; ud2 ; 1:"
935                   : : "a"(&operand), "c"(ext) : "cc", "memory");
936 }
937
938 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
939 {
940         struct {
941                 u64 eptp, gpa;
942         } operand = {eptp, gpa};
943
944         asm volatile (__ex(ASM_VMX_INVEPT)
945                         /* CF==1 or ZF==1 --> rc = -1 */
946                         "; ja 1f ; ud2 ; 1:\n"
947                         : : "a" (&operand), "c" (ext) : "cc", "memory");
948 }
949
950 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
951 {
952         int i;
953
954         i = __find_msr_index(vmx, msr);
955         if (i >= 0)
956                 return &vmx->guest_msrs[i];
957         return NULL;
958 }
959
960 static void vmcs_clear(struct vmcs *vmcs)
961 {
962         u64 phys_addr = __pa(vmcs);
963         u8 error;
964
965         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
966                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
967                       : "cc", "memory");
968         if (error)
969                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
970                        vmcs, phys_addr);
971 }
972
973 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
974 {
975         vmcs_clear(loaded_vmcs->vmcs);
976         loaded_vmcs->cpu = -1;
977         loaded_vmcs->launched = 0;
978 }
979
980 static void vmcs_load(struct vmcs *vmcs)
981 {
982         u64 phys_addr = __pa(vmcs);
983         u8 error;
984
985         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
986                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
987                         : "cc", "memory");
988         if (error)
989                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
990                        vmcs, phys_addr);
991 }
992
993 static void __loaded_vmcs_clear(void *arg)
994 {
995         struct loaded_vmcs *loaded_vmcs = arg;
996         int cpu = raw_smp_processor_id();
997
998         if (loaded_vmcs->cpu != cpu)
999                 return; /* vcpu migration can race with cpu offline */
1000         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1001                 per_cpu(current_vmcs, cpu) = NULL;
1002         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1003         loaded_vmcs_init(loaded_vmcs);
1004 }
1005
1006 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1007 {
1008         if (loaded_vmcs->cpu != -1)
1009                 smp_call_function_single(
1010                         loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
1011 }
1012
1013 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1014 {
1015         if (vmx->vpid == 0)
1016                 return;
1017
1018         if (cpu_has_vmx_invvpid_single())
1019                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1020 }
1021
1022 static inline void vpid_sync_vcpu_global(void)
1023 {
1024         if (cpu_has_vmx_invvpid_global())
1025                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1026 }
1027
1028 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1029 {
1030         if (cpu_has_vmx_invvpid_single())
1031                 vpid_sync_vcpu_single(vmx);
1032         else
1033                 vpid_sync_vcpu_global();
1034 }
1035
1036 static inline void ept_sync_global(void)
1037 {
1038         if (cpu_has_vmx_invept_global())
1039                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1040 }
1041
1042 static inline void ept_sync_context(u64 eptp)
1043 {
1044         if (enable_ept) {
1045                 if (cpu_has_vmx_invept_context())
1046                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1047                 else
1048                         ept_sync_global();
1049         }
1050 }
1051
1052 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1053 {
1054         if (enable_ept) {
1055                 if (cpu_has_vmx_invept_individual_addr())
1056                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1057                                         eptp, gpa);
1058                 else
1059                         ept_sync_context(eptp);
1060         }
1061 }
1062
1063 static __always_inline unsigned long vmcs_readl(unsigned long field)
1064 {
1065         unsigned long value;
1066
1067         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1068                       : "=a"(value) : "d"(field) : "cc");
1069         return value;
1070 }
1071
1072 static __always_inline u16 vmcs_read16(unsigned long field)
1073 {
1074         return vmcs_readl(field);
1075 }
1076
1077 static __always_inline u32 vmcs_read32(unsigned long field)
1078 {
1079         return vmcs_readl(field);
1080 }
1081
1082 static __always_inline u64 vmcs_read64(unsigned long field)
1083 {
1084 #ifdef CONFIG_X86_64
1085         return vmcs_readl(field);
1086 #else
1087         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1088 #endif
1089 }
1090
1091 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1092 {
1093         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1094                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1095         dump_stack();
1096 }
1097
1098 static void vmcs_writel(unsigned long field, unsigned long value)
1099 {
1100         u8 error;
1101
1102         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1103                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1104         if (unlikely(error))
1105                 vmwrite_error(field, value);
1106 }
1107
1108 static void vmcs_write16(unsigned long field, u16 value)
1109 {
1110         vmcs_writel(field, value);
1111 }
1112
1113 static void vmcs_write32(unsigned long field, u32 value)
1114 {
1115         vmcs_writel(field, value);
1116 }
1117
1118 static void vmcs_write64(unsigned long field, u64 value)
1119 {
1120         vmcs_writel(field, value);
1121 #ifndef CONFIG_X86_64
1122         asm volatile ("");
1123         vmcs_writel(field+1, value >> 32);
1124 #endif
1125 }
1126
1127 static void vmcs_clear_bits(unsigned long field, u32 mask)
1128 {
1129         vmcs_writel(field, vmcs_readl(field) & ~mask);
1130 }
1131
1132 static void vmcs_set_bits(unsigned long field, u32 mask)
1133 {
1134         vmcs_writel(field, vmcs_readl(field) | mask);
1135 }
1136
1137 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1138 {
1139         vmx->segment_cache.bitmask = 0;
1140 }
1141
1142 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1143                                        unsigned field)
1144 {
1145         bool ret;
1146         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1147
1148         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1149                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1150                 vmx->segment_cache.bitmask = 0;
1151         }
1152         ret = vmx->segment_cache.bitmask & mask;
1153         vmx->segment_cache.bitmask |= mask;
1154         return ret;
1155 }
1156
1157 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1158 {
1159         u16 *p = &vmx->segment_cache.seg[seg].selector;
1160
1161         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1162                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1163         return *p;
1164 }
1165
1166 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1167 {
1168         ulong *p = &vmx->segment_cache.seg[seg].base;
1169
1170         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1171                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1172         return *p;
1173 }
1174
1175 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1176 {
1177         u32 *p = &vmx->segment_cache.seg[seg].limit;
1178
1179         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1180                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1181         return *p;
1182 }
1183
1184 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1185 {
1186         u32 *p = &vmx->segment_cache.seg[seg].ar;
1187
1188         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1189                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1190         return *p;
1191 }
1192
1193 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1194 {
1195         u32 eb;
1196
1197         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1198              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1199         if ((vcpu->guest_debug &
1200              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1201             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1202                 eb |= 1u << BP_VECTOR;
1203         if (to_vmx(vcpu)->rmode.vm86_active)
1204                 eb = ~0;
1205         if (enable_ept)
1206                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1207         if (vcpu->fpu_active)
1208                 eb &= ~(1u << NM_VECTOR);
1209
1210         /* When we are running a nested L2 guest and L1 specified for it a
1211          * certain exception bitmap, we must trap the same exceptions and pass
1212          * them to L1. When running L2, we will only handle the exceptions
1213          * specified above if L1 did not want them.
1214          */
1215         if (is_guest_mode(vcpu))
1216                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1217
1218         vmcs_write32(EXCEPTION_BITMAP, eb);
1219 }
1220
1221 static void clear_atomic_switch_msr_special(unsigned long entry,
1222                 unsigned long exit)
1223 {
1224         vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1225         vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1226 }
1227
1228 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1229 {
1230         unsigned i;
1231         struct msr_autoload *m = &vmx->msr_autoload;
1232
1233         switch (msr) {
1234         case MSR_EFER:
1235                 if (cpu_has_load_ia32_efer) {
1236                         clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1237                                         VM_EXIT_LOAD_IA32_EFER);
1238                         return;
1239                 }
1240                 break;
1241         case MSR_CORE_PERF_GLOBAL_CTRL:
1242                 if (cpu_has_load_perf_global_ctrl) {
1243                         clear_atomic_switch_msr_special(
1244                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1245                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1246                         return;
1247                 }
1248                 break;
1249         }
1250
1251         for (i = 0; i < m->nr; ++i)
1252                 if (m->guest[i].index == msr)
1253                         break;
1254
1255         if (i == m->nr)
1256                 return;
1257         --m->nr;
1258         m->guest[i] = m->guest[m->nr];
1259         m->host[i] = m->host[m->nr];
1260         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1261         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1262 }
1263
1264 static void add_atomic_switch_msr_special(unsigned long entry,
1265                 unsigned long exit, unsigned long guest_val_vmcs,
1266                 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1267 {
1268         vmcs_write64(guest_val_vmcs, guest_val);
1269         vmcs_write64(host_val_vmcs, host_val);
1270         vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1271         vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1272 }
1273
1274 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1275                                   u64 guest_val, u64 host_val)
1276 {
1277         unsigned i;
1278         struct msr_autoload *m = &vmx->msr_autoload;
1279
1280         switch (msr) {
1281         case MSR_EFER:
1282                 if (cpu_has_load_ia32_efer) {
1283                         add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1284                                         VM_EXIT_LOAD_IA32_EFER,
1285                                         GUEST_IA32_EFER,
1286                                         HOST_IA32_EFER,
1287                                         guest_val, host_val);
1288                         return;
1289                 }
1290                 break;
1291         case MSR_CORE_PERF_GLOBAL_CTRL:
1292                 if (cpu_has_load_perf_global_ctrl) {
1293                         add_atomic_switch_msr_special(
1294                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1295                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1296                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1297                                         HOST_IA32_PERF_GLOBAL_CTRL,
1298                                         guest_val, host_val);
1299                         return;
1300                 }
1301                 break;
1302         }
1303
1304         for (i = 0; i < m->nr; ++i)
1305                 if (m->guest[i].index == msr)
1306                         break;
1307
1308         if (i == NR_AUTOLOAD_MSRS) {
1309                 printk_once(KERN_WARNING"Not enough mst switch entries. "
1310                                 "Can't add msr %x\n", msr);
1311                 return;
1312         } else if (i == m->nr) {
1313                 ++m->nr;
1314                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1315                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1316         }
1317
1318         m->guest[i].index = msr;
1319         m->guest[i].value = guest_val;
1320         m->host[i].index = msr;
1321         m->host[i].value = host_val;
1322 }
1323
1324 static void reload_tss(void)
1325 {
1326         /*
1327          * VT restores TR but not its size.  Useless.
1328          */
1329         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1330         struct desc_struct *descs;
1331
1332         descs = (void *)gdt->address;
1333         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1334         load_TR_desc();
1335 }
1336
1337 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1338 {
1339         u64 guest_efer;
1340         u64 ignore_bits;
1341
1342         guest_efer = vmx->vcpu.arch.efer;
1343
1344         /*
1345          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1346          * outside long mode
1347          */
1348         ignore_bits = EFER_NX | EFER_SCE;
1349 #ifdef CONFIG_X86_64
1350         ignore_bits |= EFER_LMA | EFER_LME;
1351         /* SCE is meaningful only in long mode on Intel */
1352         if (guest_efer & EFER_LMA)
1353                 ignore_bits &= ~(u64)EFER_SCE;
1354 #endif
1355         guest_efer &= ~ignore_bits;
1356         guest_efer |= host_efer & ignore_bits;
1357         vmx->guest_msrs[efer_offset].data = guest_efer;
1358         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1359
1360         clear_atomic_switch_msr(vmx, MSR_EFER);
1361         /* On ept, can't emulate nx, and must switch nx atomically */
1362         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1363                 guest_efer = vmx->vcpu.arch.efer;
1364                 if (!(guest_efer & EFER_LMA))
1365                         guest_efer &= ~EFER_LME;
1366                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1367                 return false;
1368         }
1369
1370         return true;
1371 }
1372
1373 static unsigned long segment_base(u16 selector)
1374 {
1375         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1376         struct desc_struct *d;
1377         unsigned long table_base;
1378         unsigned long v;
1379
1380         if (!(selector & ~3))
1381                 return 0;
1382
1383         table_base = gdt->address;
1384
1385         if (selector & 4) {           /* from ldt */
1386                 u16 ldt_selector = kvm_read_ldt();
1387
1388                 if (!(ldt_selector & ~3))
1389                         return 0;
1390
1391                 table_base = segment_base(ldt_selector);
1392         }
1393         d = (struct desc_struct *)(table_base + (selector & ~7));
1394         v = get_desc_base(d);
1395 #ifdef CONFIG_X86_64
1396        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1397                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1398 #endif
1399         return v;
1400 }
1401
1402 static inline unsigned long kvm_read_tr_base(void)
1403 {
1404         u16 tr;
1405         asm("str %0" : "=g"(tr));
1406         return segment_base(tr);
1407 }
1408
1409 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1410 {
1411         struct vcpu_vmx *vmx = to_vmx(vcpu);
1412         int i;
1413
1414         if (vmx->host_state.loaded)
1415                 return;
1416
1417         vmx->host_state.loaded = 1;
1418         /*
1419          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1420          * allow segment selectors with cpl > 0 or ti == 1.
1421          */
1422         vmx->host_state.ldt_sel = kvm_read_ldt();
1423         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1424         savesegment(fs, vmx->host_state.fs_sel);
1425         if (!(vmx->host_state.fs_sel & 7)) {
1426                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1427                 vmx->host_state.fs_reload_needed = 0;
1428         } else {
1429                 vmcs_write16(HOST_FS_SELECTOR, 0);
1430                 vmx->host_state.fs_reload_needed = 1;
1431         }
1432         savesegment(gs, vmx->host_state.gs_sel);
1433         if (!(vmx->host_state.gs_sel & 7))
1434                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1435         else {
1436                 vmcs_write16(HOST_GS_SELECTOR, 0);
1437                 vmx->host_state.gs_ldt_reload_needed = 1;
1438         }
1439
1440 #ifdef CONFIG_X86_64
1441         savesegment(ds, vmx->host_state.ds_sel);
1442         savesegment(es, vmx->host_state.es_sel);
1443 #endif
1444
1445 #ifdef CONFIG_X86_64
1446         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1447         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1448 #else
1449         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1450         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1451 #endif
1452
1453 #ifdef CONFIG_X86_64
1454         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1455         if (is_long_mode(&vmx->vcpu))
1456                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1457 #endif
1458         for (i = 0; i < vmx->save_nmsrs; ++i)
1459                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1460                                    vmx->guest_msrs[i].data,
1461                                    vmx->guest_msrs[i].mask);
1462 }
1463
1464 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1465 {
1466         if (!vmx->host_state.loaded)
1467                 return;
1468
1469         ++vmx->vcpu.stat.host_state_reload;
1470         vmx->host_state.loaded = 0;
1471 #ifdef CONFIG_X86_64
1472         if (is_long_mode(&vmx->vcpu))
1473                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1474 #endif
1475         if (vmx->host_state.gs_ldt_reload_needed) {
1476                 kvm_load_ldt(vmx->host_state.ldt_sel);
1477 #ifdef CONFIG_X86_64
1478                 load_gs_index(vmx->host_state.gs_sel);
1479 #else
1480                 loadsegment(gs, vmx->host_state.gs_sel);
1481 #endif
1482         }
1483         if (vmx->host_state.fs_reload_needed)
1484                 loadsegment(fs, vmx->host_state.fs_sel);
1485 #ifdef CONFIG_X86_64
1486         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1487                 loadsegment(ds, vmx->host_state.ds_sel);
1488                 loadsegment(es, vmx->host_state.es_sel);
1489         }
1490 #endif
1491         reload_tss();
1492 #ifdef CONFIG_X86_64
1493         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1494 #endif
1495         if (user_has_fpu())
1496                 clts();
1497         load_gdt(&__get_cpu_var(host_gdt));
1498 }
1499
1500 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1501 {
1502         preempt_disable();
1503         __vmx_load_host_state(vmx);
1504         preempt_enable();
1505 }
1506
1507 /*
1508  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1509  * vcpu mutex is already taken.
1510  */
1511 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1512 {
1513         struct vcpu_vmx *vmx = to_vmx(vcpu);
1514         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1515
1516         if (!vmm_exclusive)
1517                 kvm_cpu_vmxon(phys_addr);
1518         else if (vmx->loaded_vmcs->cpu != cpu)
1519                 loaded_vmcs_clear(vmx->loaded_vmcs);
1520
1521         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1522                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1523                 vmcs_load(vmx->loaded_vmcs->vmcs);
1524         }
1525
1526         if (vmx->loaded_vmcs->cpu != cpu) {
1527                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1528                 unsigned long sysenter_esp;
1529
1530                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1531                 local_irq_disable();
1532                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1533                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1534                 local_irq_enable();
1535
1536                 /*
1537                  * Linux uses per-cpu TSS and GDT, so set these when switching
1538                  * processors.
1539                  */
1540                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1541                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1542
1543                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1544                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1545                 vmx->loaded_vmcs->cpu = cpu;
1546         }
1547 }
1548
1549 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1550 {
1551         __vmx_load_host_state(to_vmx(vcpu));
1552         if (!vmm_exclusive) {
1553                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1554                 vcpu->cpu = -1;
1555                 kvm_cpu_vmxoff();
1556         }
1557 }
1558
1559 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1560 {
1561         ulong cr0;
1562
1563         if (vcpu->fpu_active)
1564                 return;
1565         vcpu->fpu_active = 1;
1566         cr0 = vmcs_readl(GUEST_CR0);
1567         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1568         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1569         vmcs_writel(GUEST_CR0, cr0);
1570         update_exception_bitmap(vcpu);
1571         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1572         if (is_guest_mode(vcpu))
1573                 vcpu->arch.cr0_guest_owned_bits &=
1574                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1575         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1576 }
1577
1578 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1579
1580 /*
1581  * Return the cr0 value that a nested guest would read. This is a combination
1582  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1583  * its hypervisor (cr0_read_shadow).
1584  */
1585 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1586 {
1587         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1588                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1589 }
1590 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1591 {
1592         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1593                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1594 }
1595
1596 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1597 {
1598         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1599          * set this *before* calling this function.
1600          */
1601         vmx_decache_cr0_guest_bits(vcpu);
1602         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1603         update_exception_bitmap(vcpu);
1604         vcpu->arch.cr0_guest_owned_bits = 0;
1605         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1606         if (is_guest_mode(vcpu)) {
1607                 /*
1608                  * L1's specified read shadow might not contain the TS bit,
1609                  * so now that we turned on shadowing of this bit, we need to
1610                  * set this bit of the shadow. Like in nested_vmx_run we need
1611                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1612                  * up-to-date here because we just decached cr0.TS (and we'll
1613                  * only update vmcs12->guest_cr0 on nested exit).
1614                  */
1615                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1616                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1617                         (vcpu->arch.cr0 & X86_CR0_TS);
1618                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1619         } else
1620                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1621 }
1622
1623 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1624 {
1625         unsigned long rflags, save_rflags;
1626
1627         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1628                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1629                 rflags = vmcs_readl(GUEST_RFLAGS);
1630                 if (to_vmx(vcpu)->rmode.vm86_active) {
1631                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1632                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1633                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1634                 }
1635                 to_vmx(vcpu)->rflags = rflags;
1636         }
1637         return to_vmx(vcpu)->rflags;
1638 }
1639
1640 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1641 {
1642         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1643         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
1644         to_vmx(vcpu)->rflags = rflags;
1645         if (to_vmx(vcpu)->rmode.vm86_active) {
1646                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1647                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1648         }
1649         vmcs_writel(GUEST_RFLAGS, rflags);
1650 }
1651
1652 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1653 {
1654         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1655         int ret = 0;
1656
1657         if (interruptibility & GUEST_INTR_STATE_STI)
1658                 ret |= KVM_X86_SHADOW_INT_STI;
1659         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1660                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1661
1662         return ret & mask;
1663 }
1664
1665 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1666 {
1667         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1668         u32 interruptibility = interruptibility_old;
1669
1670         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1671
1672         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1673                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1674         else if (mask & KVM_X86_SHADOW_INT_STI)
1675                 interruptibility |= GUEST_INTR_STATE_STI;
1676
1677         if ((interruptibility != interruptibility_old))
1678                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1679 }
1680
1681 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1682 {
1683         unsigned long rip;
1684
1685         rip = kvm_rip_read(vcpu);
1686         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1687         kvm_rip_write(vcpu, rip);
1688
1689         /* skipping an emulated instruction also counts */
1690         vmx_set_interrupt_shadow(vcpu, 0);
1691 }
1692
1693 /*
1694  * KVM wants to inject page-faults which it got to the guest. This function
1695  * checks whether in a nested guest, we need to inject them to L1 or L2.
1696  * This function assumes it is called with the exit reason in vmcs02 being
1697  * a #PF exception (this is the only case in which KVM injects a #PF when L2
1698  * is running).
1699  */
1700 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1701 {
1702         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1703
1704         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1705         if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
1706                 return 0;
1707
1708         nested_vmx_vmexit(vcpu);
1709         return 1;
1710 }
1711
1712 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1713                                 bool has_error_code, u32 error_code,
1714                                 bool reinject)
1715 {
1716         struct vcpu_vmx *vmx = to_vmx(vcpu);
1717         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1718
1719         if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1720                 nested_pf_handled(vcpu))
1721                 return;
1722
1723         if (has_error_code) {
1724                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1725                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1726         }
1727
1728         if (vmx->rmode.vm86_active) {
1729                 int inc_eip = 0;
1730                 if (kvm_exception_is_soft(nr))
1731                         inc_eip = vcpu->arch.event_exit_inst_len;
1732                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1733                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1734                 return;
1735         }
1736
1737         if (kvm_exception_is_soft(nr)) {
1738                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1739                              vmx->vcpu.arch.event_exit_inst_len);
1740                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1741         } else
1742                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1743
1744         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1745 }
1746
1747 static bool vmx_rdtscp_supported(void)
1748 {
1749         return cpu_has_vmx_rdtscp();
1750 }
1751
1752 static bool vmx_invpcid_supported(void)
1753 {
1754         return cpu_has_vmx_invpcid() && enable_ept;
1755 }
1756
1757 /*
1758  * Swap MSR entry in host/guest MSR entry array.
1759  */
1760 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1761 {
1762         struct shared_msr_entry tmp;
1763
1764         tmp = vmx->guest_msrs[to];
1765         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1766         vmx->guest_msrs[from] = tmp;
1767 }
1768
1769 /*
1770  * Set up the vmcs to automatically save and restore system
1771  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1772  * mode, as fiddling with msrs is very expensive.
1773  */
1774 static void setup_msrs(struct vcpu_vmx *vmx)
1775 {
1776         int save_nmsrs, index;
1777         unsigned long *msr_bitmap;
1778
1779         save_nmsrs = 0;
1780 #ifdef CONFIG_X86_64
1781         if (is_long_mode(&vmx->vcpu)) {
1782                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1783                 if (index >= 0)
1784                         move_msr_up(vmx, index, save_nmsrs++);
1785                 index = __find_msr_index(vmx, MSR_LSTAR);
1786                 if (index >= 0)
1787                         move_msr_up(vmx, index, save_nmsrs++);
1788                 index = __find_msr_index(vmx, MSR_CSTAR);
1789                 if (index >= 0)
1790                         move_msr_up(vmx, index, save_nmsrs++);
1791                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1792                 if (index >= 0 && vmx->rdtscp_enabled)
1793                         move_msr_up(vmx, index, save_nmsrs++);
1794                 /*
1795                  * MSR_STAR is only needed on long mode guests, and only
1796                  * if efer.sce is enabled.
1797                  */
1798                 index = __find_msr_index(vmx, MSR_STAR);
1799                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1800                         move_msr_up(vmx, index, save_nmsrs++);
1801         }
1802 #endif
1803         index = __find_msr_index(vmx, MSR_EFER);
1804         if (index >= 0 && update_transition_efer(vmx, index))
1805                 move_msr_up(vmx, index, save_nmsrs++);
1806
1807         vmx->save_nmsrs = save_nmsrs;
1808
1809         if (cpu_has_vmx_msr_bitmap()) {
1810                 if (is_long_mode(&vmx->vcpu))
1811                         msr_bitmap = vmx_msr_bitmap_longmode;
1812                 else
1813                         msr_bitmap = vmx_msr_bitmap_legacy;
1814
1815                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1816         }
1817 }
1818
1819 /*
1820  * reads and returns guest's timestamp counter "register"
1821  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1822  */
1823 static u64 guest_read_tsc(void)
1824 {
1825         u64 host_tsc, tsc_offset;
1826
1827         rdtscll(host_tsc);
1828         tsc_offset = vmcs_read64(TSC_OFFSET);
1829         return host_tsc + tsc_offset;
1830 }
1831
1832 /*
1833  * Like guest_read_tsc, but always returns L1's notion of the timestamp
1834  * counter, even if a nested guest (L2) is currently running.
1835  */
1836 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu)
1837 {
1838         u64 host_tsc, tsc_offset;
1839
1840         rdtscll(host_tsc);
1841         tsc_offset = is_guest_mode(vcpu) ?
1842                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1843                 vmcs_read64(TSC_OFFSET);
1844         return host_tsc + tsc_offset;
1845 }
1846
1847 /*
1848  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
1849  * software catchup for faster rates on slower CPUs.
1850  */
1851 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1852 {
1853         if (!scale)
1854                 return;
1855
1856         if (user_tsc_khz > tsc_khz) {
1857                 vcpu->arch.tsc_catchup = 1;
1858                 vcpu->arch.tsc_always_catchup = 1;
1859         } else
1860                 WARN(1, "user requested TSC rate below hardware speed\n");
1861 }
1862
1863 /*
1864  * writes 'offset' into guest's timestamp counter offset register
1865  */
1866 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1867 {
1868         if (is_guest_mode(vcpu)) {
1869                 /*
1870                  * We're here if L1 chose not to trap WRMSR to TSC. According
1871                  * to the spec, this should set L1's TSC; The offset that L1
1872                  * set for L2 remains unchanged, and still needs to be added
1873                  * to the newly set TSC to get L2's TSC.
1874                  */
1875                 struct vmcs12 *vmcs12;
1876                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1877                 /* recalculate vmcs02.TSC_OFFSET: */
1878                 vmcs12 = get_vmcs12(vcpu);
1879                 vmcs_write64(TSC_OFFSET, offset +
1880                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1881                          vmcs12->tsc_offset : 0));
1882         } else {
1883                 vmcs_write64(TSC_OFFSET, offset);
1884         }
1885 }
1886
1887 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1888 {
1889         u64 offset = vmcs_read64(TSC_OFFSET);
1890         vmcs_write64(TSC_OFFSET, offset + adjustment);
1891         if (is_guest_mode(vcpu)) {
1892                 /* Even when running L2, the adjustment needs to apply to L1 */
1893                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1894         }
1895 }
1896
1897 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1898 {
1899         return target_tsc - native_read_tsc();
1900 }
1901
1902 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1903 {
1904         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1905         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1906 }
1907
1908 /*
1909  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1910  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1911  * all guests if the "nested" module option is off, and can also be disabled
1912  * for a single guest by disabling its VMX cpuid bit.
1913  */
1914 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1915 {
1916         return nested && guest_cpuid_has_vmx(vcpu);
1917 }
1918
1919 /*
1920  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1921  * returned for the various VMX controls MSRs when nested VMX is enabled.
1922  * The same values should also be used to verify that vmcs12 control fields are
1923  * valid during nested entry from L1 to L2.
1924  * Each of these control msrs has a low and high 32-bit half: A low bit is on
1925  * if the corresponding bit in the (32-bit) control field *must* be on, and a
1926  * bit in the high half is on if the corresponding bit in the control field
1927  * may be on. See also vmx_control_verify().
1928  * TODO: allow these variables to be modified (downgraded) by module options
1929  * or other means.
1930  */
1931 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1932 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1933 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1934 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1935 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1936 static __init void nested_vmx_setup_ctls_msrs(void)
1937 {
1938         /*
1939          * Note that as a general rule, the high half of the MSRs (bits in
1940          * the control fields which may be 1) should be initialized by the
1941          * intersection of the underlying hardware's MSR (i.e., features which
1942          * can be supported) and the list of features we want to expose -
1943          * because they are known to be properly supported in our code.
1944          * Also, usually, the low half of the MSRs (bits which must be 1) can
1945          * be set to 0, meaning that L1 may turn off any of these bits. The
1946          * reason is that if one of these bits is necessary, it will appear
1947          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1948          * fields of vmcs01 and vmcs02, will turn these bits off - and
1949          * nested_vmx_exit_handled() will not pass related exits to L1.
1950          * These rules have exceptions below.
1951          */
1952
1953         /* pin-based controls */
1954         /*
1955          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1956          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1957          */
1958         nested_vmx_pinbased_ctls_low = 0x16 ;
1959         nested_vmx_pinbased_ctls_high = 0x16 |
1960                 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1961                 PIN_BASED_VIRTUAL_NMIS;
1962
1963         /* exit controls */
1964         nested_vmx_exit_ctls_low = 0;
1965         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
1966 #ifdef CONFIG_X86_64
1967         nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1968 #else
1969         nested_vmx_exit_ctls_high = 0;
1970 #endif
1971
1972         /* entry controls */
1973         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1974                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1975         nested_vmx_entry_ctls_low = 0;
1976         nested_vmx_entry_ctls_high &=
1977                 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1978
1979         /* cpu-based controls */
1980         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1981                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1982         nested_vmx_procbased_ctls_low = 0;
1983         nested_vmx_procbased_ctls_high &=
1984                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1985                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1986                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1987                 CPU_BASED_CR3_STORE_EXITING |
1988 #ifdef CONFIG_X86_64
1989                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1990 #endif
1991                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1992                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1993                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
1994                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1995         /*
1996          * We can allow some features even when not supported by the
1997          * hardware. For example, L1 can specify an MSR bitmap - and we
1998          * can use it to avoid exits to L1 - even when L0 runs L2
1999          * without MSR bitmaps.
2000          */
2001         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2002
2003         /* secondary cpu-based controls */
2004         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2005                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2006         nested_vmx_secondary_ctls_low = 0;
2007         nested_vmx_secondary_ctls_high &=
2008                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2009 }
2010
2011 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2012 {
2013         /*
2014          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2015          */
2016         return ((control & high) | low) == control;
2017 }
2018
2019 static inline u64 vmx_control_msr(u32 low, u32 high)
2020 {
2021         return low | ((u64)high << 32);
2022 }
2023
2024 /*
2025  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2026  * also let it use VMX-specific MSRs.
2027  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2028  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2029  * like all other MSRs).
2030  */
2031 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2032 {
2033         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2034                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2035                 /*
2036                  * According to the spec, processors which do not support VMX
2037                  * should throw a #GP(0) when VMX capability MSRs are read.
2038                  */
2039                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2040                 return 1;
2041         }
2042
2043         switch (msr_index) {
2044         case MSR_IA32_FEATURE_CONTROL:
2045                 *pdata = 0;
2046                 break;
2047         case MSR_IA32_VMX_BASIC:
2048                 /*
2049                  * This MSR reports some information about VMX support. We
2050                  * should return information about the VMX we emulate for the
2051                  * guest, and the VMCS structure we give it - not about the
2052                  * VMX support of the underlying hardware.
2053                  */
2054                 *pdata = VMCS12_REVISION |
2055                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2056                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2057                 break;
2058         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2059         case MSR_IA32_VMX_PINBASED_CTLS:
2060                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2061                                         nested_vmx_pinbased_ctls_high);
2062                 break;
2063         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2064         case MSR_IA32_VMX_PROCBASED_CTLS:
2065                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2066                                         nested_vmx_procbased_ctls_high);
2067                 break;
2068         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2069         case MSR_IA32_VMX_EXIT_CTLS:
2070                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2071                                         nested_vmx_exit_ctls_high);
2072                 break;
2073         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2074         case MSR_IA32_VMX_ENTRY_CTLS:
2075                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2076                                         nested_vmx_entry_ctls_high);
2077                 break;
2078         case MSR_IA32_VMX_MISC:
2079                 *pdata = 0;
2080                 break;
2081         /*
2082          * These MSRs specify bits which the guest must keep fixed (on or off)
2083          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2084          * We picked the standard core2 setting.
2085          */
2086 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2087 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2088         case MSR_IA32_VMX_CR0_FIXED0:
2089                 *pdata = VMXON_CR0_ALWAYSON;
2090                 break;
2091         case MSR_IA32_VMX_CR0_FIXED1:
2092                 *pdata = -1ULL;
2093                 break;
2094         case MSR_IA32_VMX_CR4_FIXED0:
2095                 *pdata = VMXON_CR4_ALWAYSON;
2096                 break;
2097         case MSR_IA32_VMX_CR4_FIXED1:
2098                 *pdata = -1ULL;
2099                 break;
2100         case MSR_IA32_VMX_VMCS_ENUM:
2101                 *pdata = 0x1f;
2102                 break;
2103         case MSR_IA32_VMX_PROCBASED_CTLS2:
2104                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2105                                         nested_vmx_secondary_ctls_high);
2106                 break;
2107         case MSR_IA32_VMX_EPT_VPID_CAP:
2108                 /* Currently, no nested ept or nested vpid */
2109                 *pdata = 0;
2110                 break;
2111         default:
2112                 return 0;
2113         }
2114
2115         return 1;
2116 }
2117
2118 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2119 {
2120         if (!nested_vmx_allowed(vcpu))
2121                 return 0;
2122
2123         if (msr_index == MSR_IA32_FEATURE_CONTROL)
2124                 /* TODO: the right thing. */
2125                 return 1;
2126         /*
2127          * No need to treat VMX capability MSRs specially: If we don't handle
2128          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2129          */
2130         return 0;
2131 }
2132
2133 /*
2134  * Reads an msr value (of 'msr_index') into 'pdata'.
2135  * Returns 0 on success, non-0 otherwise.
2136  * Assumes vcpu_load() was already called.
2137  */
2138 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2139 {
2140         u64 data;
2141         struct shared_msr_entry *msr;
2142
2143         if (!pdata) {
2144                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2145                 return -EINVAL;
2146         }
2147
2148         switch (msr_index) {
2149 #ifdef CONFIG_X86_64
2150         case MSR_FS_BASE:
2151                 data = vmcs_readl(GUEST_FS_BASE);
2152                 break;
2153         case MSR_GS_BASE:
2154                 data = vmcs_readl(GUEST_GS_BASE);
2155                 break;
2156         case MSR_KERNEL_GS_BASE:
2157                 vmx_load_host_state(to_vmx(vcpu));
2158                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2159                 break;
2160 #endif
2161         case MSR_EFER:
2162                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2163         case MSR_IA32_TSC:
2164                 data = guest_read_tsc();
2165                 break;
2166         case MSR_IA32_SYSENTER_CS:
2167                 data = vmcs_read32(GUEST_SYSENTER_CS);
2168                 break;
2169         case MSR_IA32_SYSENTER_EIP:
2170                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2171                 break;
2172         case MSR_IA32_SYSENTER_ESP:
2173                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2174                 break;
2175         case MSR_TSC_AUX:
2176                 if (!to_vmx(vcpu)->rdtscp_enabled)
2177                         return 1;
2178                 /* Otherwise falls through */
2179         default:
2180                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2181                         return 0;
2182                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2183                 if (msr) {
2184                         data = msr->data;
2185                         break;
2186                 }
2187                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2188         }
2189
2190         *pdata = data;
2191         return 0;
2192 }
2193
2194 /*
2195  * Writes msr value into into the appropriate "register".
2196  * Returns 0 on success, non-0 otherwise.
2197  * Assumes vcpu_load() was already called.
2198  */
2199 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2200 {
2201         struct vcpu_vmx *vmx = to_vmx(vcpu);
2202         struct shared_msr_entry *msr;
2203         int ret = 0;
2204
2205         switch (msr_index) {
2206         case MSR_EFER:
2207                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2208                 break;
2209 #ifdef CONFIG_X86_64
2210         case MSR_FS_BASE:
2211                 vmx_segment_cache_clear(vmx);
2212                 vmcs_writel(GUEST_FS_BASE, data);
2213                 break;
2214         case MSR_GS_BASE:
2215                 vmx_segment_cache_clear(vmx);
2216                 vmcs_writel(GUEST_GS_BASE, data);
2217                 break;
2218         case MSR_KERNEL_GS_BASE:
2219                 vmx_load_host_state(vmx);
2220                 vmx->msr_guest_kernel_gs_base = data;
2221                 break;
2222 #endif
2223         case MSR_IA32_SYSENTER_CS:
2224                 vmcs_write32(GUEST_SYSENTER_CS, data);
2225                 break;
2226         case MSR_IA32_SYSENTER_EIP:
2227                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2228                 break;
2229         case MSR_IA32_SYSENTER_ESP:
2230                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2231                 break;
2232         case MSR_IA32_TSC:
2233                 kvm_write_tsc(vcpu, data);
2234                 break;
2235         case MSR_IA32_CR_PAT:
2236                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2237                         vmcs_write64(GUEST_IA32_PAT, data);
2238                         vcpu->arch.pat = data;
2239                         break;
2240                 }
2241                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2242                 break;
2243         case MSR_TSC_AUX:
2244                 if (!vmx->rdtscp_enabled)
2245                         return 1;
2246                 /* Check reserved bit, higher 32 bits should be zero */
2247                 if ((data >> 32) != 0)
2248                         return 1;
2249                 /* Otherwise falls through */
2250         default:
2251                 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2252                         break;
2253                 msr = find_msr_entry(vmx, msr_index);
2254                 if (msr) {
2255                         msr->data = data;
2256                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2257                                 preempt_disable();
2258                                 kvm_set_shared_msr(msr->index, msr->data,
2259                                                    msr->mask);
2260                                 preempt_enable();
2261                         }
2262                         break;
2263                 }
2264                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2265         }
2266
2267         return ret;
2268 }
2269
2270 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2271 {
2272         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2273         switch (reg) {
2274         case VCPU_REGS_RSP:
2275                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2276                 break;
2277         case VCPU_REGS_RIP:
2278                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2279                 break;
2280         case VCPU_EXREG_PDPTR:
2281                 if (enable_ept)
2282                         ept_save_pdptrs(vcpu);
2283                 break;
2284         default:
2285                 break;
2286         }
2287 }
2288
2289 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
2290 {
2291         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2292                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2293         else
2294                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2295
2296         update_exception_bitmap(vcpu);
2297 }
2298
2299 static __init int cpu_has_kvm_support(void)
2300 {
2301         return cpu_has_vmx();
2302 }
2303
2304 static __init int vmx_disabled_by_bios(void)
2305 {
2306         u64 msr;
2307
2308         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2309         if (msr & FEATURE_CONTROL_LOCKED) {
2310                 /* launched w/ TXT and VMX disabled */
2311                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2312                         && tboot_enabled())
2313                         return 1;
2314                 /* launched w/o TXT and VMX only enabled w/ TXT */
2315                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2316                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2317                         && !tboot_enabled()) {
2318                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2319                                 "activate TXT before enabling KVM\n");
2320                         return 1;
2321                 }
2322                 /* launched w/o TXT and VMX disabled */
2323                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2324                         && !tboot_enabled())
2325                         return 1;
2326         }
2327
2328         return 0;
2329 }
2330
2331 static void kvm_cpu_vmxon(u64 addr)
2332 {
2333         asm volatile (ASM_VMX_VMXON_RAX
2334                         : : "a"(&addr), "m"(addr)
2335                         : "memory", "cc");
2336 }
2337
2338 static int hardware_enable(void *garbage)
2339 {
2340         int cpu = raw_smp_processor_id();
2341         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2342         u64 old, test_bits;
2343
2344         if (read_cr4() & X86_CR4_VMXE)
2345                 return -EBUSY;
2346
2347         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2348         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2349
2350         test_bits = FEATURE_CONTROL_LOCKED;
2351         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2352         if (tboot_enabled())
2353                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2354
2355         if ((old & test_bits) != test_bits) {
2356                 /* enable and lock */
2357                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2358         }
2359         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2360
2361         if (vmm_exclusive) {
2362                 kvm_cpu_vmxon(phys_addr);
2363                 ept_sync_global();
2364         }
2365
2366         store_gdt(&__get_cpu_var(host_gdt));
2367
2368         return 0;
2369 }
2370
2371 static void vmclear_local_loaded_vmcss(void)
2372 {
2373         int cpu = raw_smp_processor_id();
2374         struct loaded_vmcs *v, *n;
2375
2376         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2377                                  loaded_vmcss_on_cpu_link)
2378                 __loaded_vmcs_clear(v);
2379 }
2380
2381
2382 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2383  * tricks.
2384  */
2385 static void kvm_cpu_vmxoff(void)
2386 {
2387         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2388 }
2389
2390 static void hardware_disable(void *garbage)
2391 {
2392         if (vmm_exclusive) {
2393                 vmclear_local_loaded_vmcss();
2394                 kvm_cpu_vmxoff();
2395         }
2396         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2397 }
2398
2399 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2400                                       u32 msr, u32 *result)
2401 {
2402         u32 vmx_msr_low, vmx_msr_high;
2403         u32 ctl = ctl_min | ctl_opt;
2404
2405         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2406
2407         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2408         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2409
2410         /* Ensure minimum (required) set of control bits are supported. */
2411         if (ctl_min & ~ctl)
2412                 return -EIO;
2413
2414         *result = ctl;
2415         return 0;
2416 }
2417
2418 static __init bool allow_1_setting(u32 msr, u32 ctl)
2419 {
2420         u32 vmx_msr_low, vmx_msr_high;
2421
2422         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2423         return vmx_msr_high & ctl;
2424 }
2425
2426 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2427 {
2428         u32 vmx_msr_low, vmx_msr_high;
2429         u32 min, opt, min2, opt2;
2430         u32 _pin_based_exec_control = 0;
2431         u32 _cpu_based_exec_control = 0;
2432         u32 _cpu_based_2nd_exec_control = 0;
2433         u32 _vmexit_control = 0;
2434         u32 _vmentry_control = 0;
2435
2436         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2437         opt = PIN_BASED_VIRTUAL_NMIS;
2438         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2439                                 &_pin_based_exec_control) < 0)
2440                 return -EIO;
2441
2442         min = CPU_BASED_HLT_EXITING |
2443 #ifdef CONFIG_X86_64
2444               CPU_BASED_CR8_LOAD_EXITING |
2445               CPU_BASED_CR8_STORE_EXITING |
2446 #endif
2447               CPU_BASED_CR3_LOAD_EXITING |
2448               CPU_BASED_CR3_STORE_EXITING |
2449               CPU_BASED_USE_IO_BITMAPS |
2450               CPU_BASED_MOV_DR_EXITING |
2451               CPU_BASED_USE_TSC_OFFSETING |
2452               CPU_BASED_MWAIT_EXITING |
2453               CPU_BASED_MONITOR_EXITING |
2454               CPU_BASED_INVLPG_EXITING |
2455               CPU_BASED_RDPMC_EXITING;
2456
2457         opt = CPU_BASED_TPR_SHADOW |
2458               CPU_BASED_USE_MSR_BITMAPS |
2459               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2460         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2461                                 &_cpu_based_exec_control) < 0)
2462                 return -EIO;
2463 #ifdef CONFIG_X86_64
2464         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2465                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2466                                            ~CPU_BASED_CR8_STORE_EXITING;
2467 #endif
2468         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2469                 min2 = 0;
2470                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2471                         SECONDARY_EXEC_WBINVD_EXITING |
2472                         SECONDARY_EXEC_ENABLE_VPID |
2473                         SECONDARY_EXEC_ENABLE_EPT |
2474                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2475                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2476                         SECONDARY_EXEC_RDTSCP |
2477                         SECONDARY_EXEC_ENABLE_INVPCID;
2478                 if (adjust_vmx_controls(min2, opt2,
2479                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2480                                         &_cpu_based_2nd_exec_control) < 0)
2481                         return -EIO;
2482         }
2483 #ifndef CONFIG_X86_64
2484         if (!(_cpu_based_2nd_exec_control &
2485                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2486                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2487 #endif
2488         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2489                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2490                    enabled */
2491                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2492                                              CPU_BASED_CR3_STORE_EXITING |
2493                                              CPU_BASED_INVLPG_EXITING);
2494                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2495                       vmx_capability.ept, vmx_capability.vpid);
2496         }
2497
2498         min = 0;
2499 #ifdef CONFIG_X86_64
2500         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2501 #endif
2502         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2503         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2504                                 &_vmexit_control) < 0)
2505                 return -EIO;
2506
2507         min = 0;
2508         opt = VM_ENTRY_LOAD_IA32_PAT;
2509         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2510                                 &_vmentry_control) < 0)
2511                 return -EIO;
2512
2513         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2514
2515         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2516         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2517                 return -EIO;
2518
2519 #ifdef CONFIG_X86_64
2520         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2521         if (vmx_msr_high & (1u<<16))
2522                 return -EIO;
2523 #endif
2524
2525         /* Require Write-Back (WB) memory type for VMCS accesses. */
2526         if (((vmx_msr_high >> 18) & 15) != 6)
2527                 return -EIO;
2528
2529         vmcs_conf->size = vmx_msr_high & 0x1fff;
2530         vmcs_conf->order = get_order(vmcs_config.size);
2531         vmcs_conf->revision_id = vmx_msr_low;
2532
2533         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2534         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2535         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2536         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2537         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2538
2539         cpu_has_load_ia32_efer =
2540                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2541                                 VM_ENTRY_LOAD_IA32_EFER)
2542                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2543                                    VM_EXIT_LOAD_IA32_EFER);
2544
2545         cpu_has_load_perf_global_ctrl =
2546                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2547                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2548                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2549                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2550
2551         /*
2552          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2553          * but due to arrata below it can't be used. Workaround is to use
2554          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2555          *
2556          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2557          *
2558          * AAK155             (model 26)
2559          * AAP115             (model 30)
2560          * AAT100             (model 37)
2561          * BC86,AAY89,BD102   (model 44)
2562          * BA97               (model 46)
2563          *
2564          */
2565         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2566                 switch (boot_cpu_data.x86_model) {
2567                 case 26:
2568                 case 30:
2569                 case 37:
2570                 case 44:
2571                 case 46:
2572                         cpu_has_load_perf_global_ctrl = false;
2573                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2574                                         "does not work properly. Using workaround\n");
2575                         break;
2576                 default:
2577                         break;
2578                 }
2579         }
2580
2581         return 0;
2582 }
2583
2584 static struct vmcs *alloc_vmcs_cpu(int cpu)
2585 {
2586         int node = cpu_to_node(cpu);
2587         struct page *pages;
2588         struct vmcs *vmcs;
2589
2590         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2591         if (!pages)
2592                 return NULL;
2593         vmcs = page_address(pages);
2594         memset(vmcs, 0, vmcs_config.size);
2595         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2596         return vmcs;
2597 }
2598
2599 static struct vmcs *alloc_vmcs(void)
2600 {
2601         return alloc_vmcs_cpu(raw_smp_processor_id());
2602 }
2603
2604 static void free_vmcs(struct vmcs *vmcs)
2605 {
2606         free_pages((unsigned long)vmcs, vmcs_config.order);
2607 }
2608
2609 /*
2610  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2611  */
2612 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2613 {
2614         if (!loaded_vmcs->vmcs)
2615                 return;
2616         loaded_vmcs_clear(loaded_vmcs);
2617         free_vmcs(loaded_vmcs->vmcs);
2618         loaded_vmcs->vmcs = NULL;
2619 }
2620
2621 static void free_kvm_area(void)
2622 {
2623         int cpu;
2624
2625         for_each_possible_cpu(cpu) {
2626                 free_vmcs(per_cpu(vmxarea, cpu));
2627                 per_cpu(vmxarea, cpu) = NULL;
2628         }
2629 }
2630
2631 static __init int alloc_kvm_area(void)
2632 {
2633         int cpu;
2634
2635         for_each_possible_cpu(cpu) {
2636                 struct vmcs *vmcs;
2637
2638                 vmcs = alloc_vmcs_cpu(cpu);
2639                 if (!vmcs) {
2640                         free_kvm_area();
2641                         return -ENOMEM;
2642                 }
2643
2644                 per_cpu(vmxarea, cpu) = vmcs;
2645         }
2646         return 0;
2647 }
2648
2649 static __init int hardware_setup(void)
2650 {
2651         if (setup_vmcs_config(&vmcs_config) < 0)
2652                 return -EIO;
2653
2654         if (boot_cpu_has(X86_FEATURE_NX))
2655                 kvm_enable_efer_bits(EFER_NX);
2656
2657         if (!cpu_has_vmx_vpid())
2658                 enable_vpid = 0;
2659
2660         if (!cpu_has_vmx_ept() ||
2661             !cpu_has_vmx_ept_4levels()) {
2662                 enable_ept = 0;
2663                 enable_unrestricted_guest = 0;
2664                 enable_ept_ad_bits = 0;
2665         }
2666
2667         if (!cpu_has_vmx_ept_ad_bits())
2668                 enable_ept_ad_bits = 0;
2669
2670         if (!cpu_has_vmx_unrestricted_guest())
2671                 enable_unrestricted_guest = 0;
2672
2673         if (!cpu_has_vmx_flexpriority())
2674                 flexpriority_enabled = 0;
2675
2676         if (!cpu_has_vmx_tpr_shadow())
2677                 kvm_x86_ops->update_cr8_intercept = NULL;
2678
2679         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2680                 kvm_disable_largepages();
2681
2682         if (!cpu_has_vmx_ple())
2683                 ple_gap = 0;
2684
2685         if (nested)
2686                 nested_vmx_setup_ctls_msrs();
2687
2688         return alloc_kvm_area();
2689 }
2690
2691 static __exit void hardware_unsetup(void)
2692 {
2693         free_kvm_area();
2694 }
2695
2696 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2697 {
2698         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2699
2700         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
2701                 vmcs_write16(sf->selector, save->selector);
2702                 vmcs_writel(sf->base, save->base);
2703                 vmcs_write32(sf->limit, save->limit);
2704                 vmcs_write32(sf->ar_bytes, save->ar);
2705         } else {
2706                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2707                         << AR_DPL_SHIFT;
2708                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2709         }
2710 }
2711
2712 static void enter_pmode(struct kvm_vcpu *vcpu)
2713 {
2714         unsigned long flags;
2715         struct vcpu_vmx *vmx = to_vmx(vcpu);
2716
2717         vmx->emulation_required = 1;
2718         vmx->rmode.vm86_active = 0;
2719
2720         vmx_segment_cache_clear(vmx);
2721
2722         vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
2723         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2724         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2725         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
2726
2727         flags = vmcs_readl(GUEST_RFLAGS);
2728         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2729         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2730         vmcs_writel(GUEST_RFLAGS, flags);
2731
2732         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2733                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2734
2735         update_exception_bitmap(vcpu);
2736
2737         if (emulate_invalid_guest_state)
2738                 return;
2739
2740         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2741         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2742         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2743         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
2744
2745         vmx_segment_cache_clear(vmx);
2746
2747         vmcs_write16(GUEST_SS_SELECTOR, 0);
2748         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2749
2750         vmcs_write16(GUEST_CS_SELECTOR,
2751                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2752         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2753 }
2754
2755 static gva_t rmode_tss_base(struct kvm *kvm)
2756 {
2757         if (!kvm->arch.tss_addr) {
2758                 struct kvm_memslots *slots;
2759                 struct kvm_memory_slot *slot;
2760                 gfn_t base_gfn;
2761
2762                 slots = kvm_memslots(kvm);
2763                 slot = id_to_memslot(slots, 0);
2764                 base_gfn = slot->base_gfn + slot->npages - 3;
2765
2766                 return base_gfn << PAGE_SHIFT;
2767         }
2768         return kvm->arch.tss_addr;
2769 }
2770
2771 static void save_rmode_seg(int seg, struct kvm_save_segment *save)
2772 {
2773         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2774
2775         save->selector = vmcs_read16(sf->selector);
2776         save->base = vmcs_readl(sf->base);
2777         save->limit = vmcs_read32(sf->limit);
2778         save->ar = vmcs_read32(sf->ar_bytes);
2779 }
2780
2781 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2782 {
2783         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2784
2785         vmcs_write16(sf->selector, save->base >> 4);
2786         vmcs_write32(sf->base, save->base & 0xffff0);
2787         vmcs_write32(sf->limit, 0xffff);
2788         vmcs_write32(sf->ar_bytes, 0xf3);
2789         if (save->base & 0xf)
2790                 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2791                             " aligned when entering protected mode (seg=%d)",
2792                             seg);
2793 }
2794
2795 static void enter_rmode(struct kvm_vcpu *vcpu)
2796 {
2797         unsigned long flags;
2798         struct vcpu_vmx *vmx = to_vmx(vcpu);
2799         struct kvm_segment var;
2800
2801         if (enable_unrestricted_guest)
2802                 return;
2803
2804         vmx->emulation_required = 1;
2805         vmx->rmode.vm86_active = 1;
2806
2807         save_rmode_seg(VCPU_SREG_TR, &vmx->rmode.tr);
2808         save_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
2809         save_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
2810         save_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
2811         save_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
2812
2813         /*
2814          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2815          * vcpu. Call it here with phys address pointing 16M below 4G.
2816          */
2817         if (!vcpu->kvm->arch.tss_addr) {
2818                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2819                              "called before entering vcpu\n");
2820                 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2821                 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2822                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2823         }
2824
2825         vmx_segment_cache_clear(vmx);
2826
2827         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2828         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2829         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2830
2831         flags = vmcs_readl(GUEST_RFLAGS);
2832         vmx->rmode.save_rflags = flags;
2833
2834         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2835
2836         vmcs_writel(GUEST_RFLAGS, flags);
2837         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2838         update_exception_bitmap(vcpu);
2839
2840         if (emulate_invalid_guest_state)
2841                 goto continue_rmode;
2842
2843         vmx_get_segment(vcpu, &var, VCPU_SREG_SS);
2844         vmx_set_segment(vcpu, &var, VCPU_SREG_SS);
2845
2846         vmx_get_segment(vcpu, &var, VCPU_SREG_CS);
2847         vmx_set_segment(vcpu, &var, VCPU_SREG_CS);
2848
2849         vmx_get_segment(vcpu, &var, VCPU_SREG_ES);
2850         vmx_set_segment(vcpu, &var, VCPU_SREG_ES);
2851
2852         vmx_get_segment(vcpu, &var, VCPU_SREG_DS);
2853         vmx_set_segment(vcpu, &var, VCPU_SREG_DS);
2854
2855         vmx_get_segment(vcpu, &var, VCPU_SREG_GS);
2856         vmx_set_segment(vcpu, &var, VCPU_SREG_GS);
2857
2858         vmx_get_segment(vcpu, &var, VCPU_SREG_FS);
2859         vmx_set_segment(vcpu, &var, VCPU_SREG_FS);
2860
2861 continue_rmode:
2862         kvm_mmu_reset_context(vcpu);
2863 }
2864
2865 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2866 {
2867         struct vcpu_vmx *vmx = to_vmx(vcpu);
2868         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2869
2870         if (!msr)
2871                 return;
2872
2873         /*
2874          * Force kernel_gs_base reloading before EFER changes, as control
2875          * of this msr depends on is_long_mode().
2876          */
2877         vmx_load_host_state(to_vmx(vcpu));
2878         vcpu->arch.efer = efer;
2879         if (efer & EFER_LMA) {
2880                 vmcs_write32(VM_ENTRY_CONTROLS,
2881                              vmcs_read32(VM_ENTRY_CONTROLS) |
2882                              VM_ENTRY_IA32E_MODE);
2883                 msr->data = efer;
2884         } else {
2885                 vmcs_write32(VM_ENTRY_CONTROLS,
2886                              vmcs_read32(VM_ENTRY_CONTROLS) &
2887                              ~VM_ENTRY_IA32E_MODE);
2888
2889                 msr->data = efer & ~EFER_LME;
2890         }
2891         setup_msrs(vmx);
2892 }
2893
2894 #ifdef CONFIG_X86_64
2895
2896 static void enter_lmode(struct kvm_vcpu *vcpu)
2897 {
2898         u32 guest_tr_ar;
2899
2900         vmx_segment_cache_clear(to_vmx(vcpu));
2901
2902         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2903         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2904                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2905                                      __func__);
2906                 vmcs_write32(GUEST_TR_AR_BYTES,
2907                              (guest_tr_ar & ~AR_TYPE_MASK)
2908                              | AR_TYPE_BUSY_64_TSS);
2909         }
2910         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2911 }
2912
2913 static void exit_lmode(struct kvm_vcpu *vcpu)
2914 {
2915         vmcs_write32(VM_ENTRY_CONTROLS,
2916                      vmcs_read32(VM_ENTRY_CONTROLS)
2917                      & ~VM_ENTRY_IA32E_MODE);
2918         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2919 }
2920
2921 #endif
2922
2923 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2924 {
2925         vpid_sync_context(to_vmx(vcpu));
2926         if (enable_ept) {
2927                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2928                         return;
2929                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2930         }
2931 }
2932
2933 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2934 {
2935         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2936
2937         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2938         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2939 }
2940
2941 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2942 {
2943         if (enable_ept && is_paging(vcpu))
2944                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2945         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2946 }
2947
2948 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2949 {
2950         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2951
2952         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2953         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2954 }
2955
2956 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2957 {
2958         if (!test_bit(VCPU_EXREG_PDPTR,
2959                       (unsigned long *)&vcpu->arch.regs_dirty))
2960                 return;
2961
2962         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2963                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2964                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2965                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2966                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
2967         }
2968 }
2969
2970 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2971 {
2972         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2973                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2974                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2975                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2976                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2977         }
2978
2979         __set_bit(VCPU_EXREG_PDPTR,
2980                   (unsigned long *)&vcpu->arch.regs_avail);
2981         __set_bit(VCPU_EXREG_PDPTR,
2982                   (unsigned long *)&vcpu->arch.regs_dirty);
2983 }
2984
2985 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2986
2987 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2988                                         unsigned long cr0,
2989                                         struct kvm_vcpu *vcpu)
2990 {
2991         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2992                 vmx_decache_cr3(vcpu);
2993         if (!(cr0 & X86_CR0_PG)) {
2994                 /* From paging/starting to nonpaging */
2995                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2996                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
2997                              (CPU_BASED_CR3_LOAD_EXITING |
2998                               CPU_BASED_CR3_STORE_EXITING));
2999                 vcpu->arch.cr0 = cr0;
3000                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3001         } else if (!is_paging(vcpu)) {
3002                 /* From nonpaging to paging */
3003                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3004                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3005                              ~(CPU_BASED_CR3_LOAD_EXITING |
3006                                CPU_BASED_CR3_STORE_EXITING));
3007                 vcpu->arch.cr0 = cr0;
3008                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3009         }
3010
3011         if (!(cr0 & X86_CR0_WP))
3012                 *hw_cr0 &= ~X86_CR0_WP;
3013 }
3014
3015 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3016 {
3017         struct vcpu_vmx *vmx = to_vmx(vcpu);
3018         unsigned long hw_cr0;
3019
3020         if (enable_unrestricted_guest)
3021                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
3022                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3023         else
3024                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
3025
3026         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3027                 enter_pmode(vcpu);
3028
3029         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3030                 enter_rmode(vcpu);
3031
3032 #ifdef CONFIG_X86_64
3033         if (vcpu->arch.efer & EFER_LME) {
3034                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3035                         enter_lmode(vcpu);
3036                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3037                         exit_lmode(vcpu);
3038         }
3039 #endif
3040
3041         if (enable_ept)
3042                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3043
3044         if (!vcpu->fpu_active)
3045                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3046
3047         vmcs_writel(CR0_READ_SHADOW, cr0);
3048         vmcs_writel(GUEST_CR0, hw_cr0);
3049         vcpu->arch.cr0 = cr0;
3050         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3051 }
3052
3053 static u64 construct_eptp(unsigned long root_hpa)
3054 {
3055         u64 eptp;
3056
3057         /* TODO write the value reading from MSR */
3058         eptp = VMX_EPT_DEFAULT_MT |
3059                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3060         if (enable_ept_ad_bits)
3061                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3062         eptp |= (root_hpa & PAGE_MASK);
3063
3064         return eptp;
3065 }
3066
3067 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3068 {
3069         unsigned long guest_cr3;
3070         u64 eptp;
3071
3072         guest_cr3 = cr3;
3073         if (enable_ept) {
3074                 eptp = construct_eptp(cr3);
3075                 vmcs_write64(EPT_POINTER, eptp);
3076                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3077                         vcpu->kvm->arch.ept_identity_map_addr;
3078                 ept_load_pdptrs(vcpu);
3079         }
3080
3081         vmx_flush_tlb(vcpu);
3082         vmcs_writel(GUEST_CR3, guest_cr3);
3083 }
3084
3085 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3086 {
3087         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3088                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3089
3090         if (cr4 & X86_CR4_VMXE) {
3091                 /*
3092                  * To use VMXON (and later other VMX instructions), a guest
3093                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3094                  * So basically the check on whether to allow nested VMX
3095                  * is here.
3096                  */
3097                 if (!nested_vmx_allowed(vcpu))
3098                         return 1;
3099         } else if (to_vmx(vcpu)->nested.vmxon)
3100                 return 1;
3101
3102         vcpu->arch.cr4 = cr4;
3103         if (enable_ept) {
3104                 if (!is_paging(vcpu)) {
3105                         hw_cr4 &= ~X86_CR4_PAE;
3106                         hw_cr4 |= X86_CR4_PSE;
3107                 } else if (!(cr4 & X86_CR4_PAE)) {
3108                         hw_cr4 &= ~X86_CR4_PAE;
3109                 }
3110         }
3111
3112         vmcs_writel(CR4_READ_SHADOW, cr4);
3113         vmcs_writel(GUEST_CR4, hw_cr4);
3114         return 0;
3115 }
3116
3117 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3118                             struct kvm_segment *var, int seg)
3119 {
3120         struct vcpu_vmx *vmx = to_vmx(vcpu);
3121         struct kvm_save_segment *save;
3122         u32 ar;
3123
3124         if (vmx->rmode.vm86_active
3125             && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
3126                 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
3127                 || seg == VCPU_SREG_GS)
3128             && !emulate_invalid_guest_state) {
3129                 switch (seg) {
3130                 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
3131                 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
3132                 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
3133                 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
3134                 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
3135                 default: BUG();
3136                 }
3137                 var->selector = save->selector;
3138                 var->base = save->base;
3139                 var->limit = save->limit;
3140                 ar = save->ar;
3141                 if (seg == VCPU_SREG_TR
3142                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3143                         goto use_saved_rmode_seg;
3144         }
3145         var->base = vmx_read_guest_seg_base(vmx, seg);
3146         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3147         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3148         ar = vmx_read_guest_seg_ar(vmx, seg);
3149 use_saved_rmode_seg:
3150         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
3151                 ar = 0;
3152         var->type = ar & 15;
3153         var->s = (ar >> 4) & 1;
3154         var->dpl = (ar >> 5) & 3;
3155         var->present = (ar >> 7) & 1;
3156         var->avl = (ar >> 12) & 1;
3157         var->l = (ar >> 13) & 1;
3158         var->db = (ar >> 14) & 1;
3159         var->g = (ar >> 15) & 1;
3160         var->unusable = (ar >> 16) & 1;
3161 }
3162
3163 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3164 {
3165         struct kvm_segment s;
3166
3167         if (to_vmx(vcpu)->rmode.vm86_active) {
3168                 vmx_get_segment(vcpu, &s, seg);
3169                 return s.base;
3170         }
3171         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3172 }
3173
3174 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
3175 {
3176         if (!is_protmode(vcpu))
3177                 return 0;
3178
3179         if (!is_long_mode(vcpu)
3180             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3181                 return 3;
3182
3183         return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
3184 }
3185
3186 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3187 {
3188         struct vcpu_vmx *vmx = to_vmx(vcpu);
3189
3190         /*
3191          * If we enter real mode with cs.sel & 3 != 0, the normal CPL calculations
3192          * fail; use the cache instead.
3193          */
3194         if (unlikely(vmx->emulation_required && emulate_invalid_guest_state)) {
3195                 return vmx->cpl;
3196         }
3197
3198         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3199                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3200                 vmx->cpl = __vmx_get_cpl(vcpu);
3201         }
3202
3203         return vmx->cpl;
3204 }
3205
3206
3207 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3208 {
3209         u32 ar;
3210
3211         if (var->unusable || !var->present)
3212                 ar = 1 << 16;
3213         else {
3214                 ar = var->type & 15;
3215                 ar |= (var->s & 1) << 4;
3216                 ar |= (var->dpl & 3) << 5;
3217                 ar |= (var->present & 1) << 7;
3218                 ar |= (var->avl & 1) << 12;
3219                 ar |= (var->l & 1) << 13;
3220                 ar |= (var->db & 1) << 14;
3221                 ar |= (var->g & 1) << 15;
3222         }
3223
3224         return ar;
3225 }
3226
3227 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3228                             struct kvm_segment *var, int seg)
3229 {
3230         struct vcpu_vmx *vmx = to_vmx(vcpu);
3231         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3232         u32 ar;
3233
3234         vmx_segment_cache_clear(vmx);
3235
3236         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
3237                 vmcs_write16(sf->selector, var->selector);
3238                 vmx->rmode.tr.selector = var->selector;
3239                 vmx->rmode.tr.base = var->base;
3240                 vmx->rmode.tr.limit = var->limit;
3241                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
3242                 return;
3243         }
3244         vmcs_writel(sf->base, var->base);
3245         vmcs_write32(sf->limit, var->limit);
3246         vmcs_write16(sf->selector, var->selector);
3247         if (vmx->rmode.vm86_active && var->s) {
3248                 /*
3249                  * Hack real-mode segments into vm86 compatibility.
3250                  */
3251                 if (var->base == 0xffff0000 && var->selector == 0xf000)
3252                         vmcs_writel(sf->base, 0xf0000);
3253                 ar = 0xf3;
3254         } else
3255                 ar = vmx_segment_access_rights(var);
3256
3257         /*
3258          *   Fix the "Accessed" bit in AR field of segment registers for older
3259          * qemu binaries.
3260          *   IA32 arch specifies that at the time of processor reset the
3261          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3262          * is setting it to 0 in the userland code. This causes invalid guest
3263          * state vmexit when "unrestricted guest" mode is turned on.
3264          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3265          * tree. Newer qemu binaries with that qemu fix would not need this
3266          * kvm hack.
3267          */
3268         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3269                 ar |= 0x1; /* Accessed */
3270
3271         vmcs_write32(sf->ar_bytes, ar);
3272         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3273
3274         /*
3275          * Fix segments for real mode guest in hosts that don't have
3276          * "unrestricted_mode" or it was disabled.
3277          * This is done to allow migration of the guests from hosts with
3278          * unrestricted guest like Westmere to older host that don't have
3279          * unrestricted guest like Nehelem.
3280          */
3281         if (!enable_unrestricted_guest && vmx->rmode.vm86_active) {
3282                 switch (seg) {
3283                 case VCPU_SREG_CS:
3284                         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
3285                         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
3286                         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
3287                                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
3288                         vmcs_write16(GUEST_CS_SELECTOR,
3289                                      vmcs_readl(GUEST_CS_BASE) >> 4);
3290                         break;
3291                 case VCPU_SREG_ES:
3292                         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
3293                         break;
3294                 case VCPU_SREG_DS:
3295                         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
3296                         break;
3297                 case VCPU_SREG_GS:
3298                         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
3299                         break;
3300                 case VCPU_SREG_FS:
3301                         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
3302                         break;
3303                 case VCPU_SREG_SS:
3304                         vmcs_write16(GUEST_SS_SELECTOR,
3305                                      vmcs_readl(GUEST_SS_BASE) >> 4);
3306                         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
3307                         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
3308                         break;
3309                 }
3310         }
3311 }
3312
3313 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3314 {
3315         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3316
3317         *db = (ar >> 14) & 1;
3318         *l = (ar >> 13) & 1;
3319 }
3320
3321 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3322 {
3323         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3324         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3325 }
3326
3327 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3328 {
3329         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3330         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3331 }
3332
3333 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3334 {
3335         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3336         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3337 }
3338
3339 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3340 {
3341         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3342         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3343 }
3344
3345 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3346 {
3347         struct kvm_segment var;
3348         u32 ar;
3349
3350         vmx_get_segment(vcpu, &var, seg);
3351         ar = vmx_segment_access_rights(&var);
3352
3353         if (var.base != (var.selector << 4))
3354                 return false;
3355         if (var.limit != 0xffff)
3356                 return false;
3357         if (ar != 0xf3)
3358                 return false;
3359
3360         return true;
3361 }
3362
3363 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3364 {
3365         struct kvm_segment cs;
3366         unsigned int cs_rpl;
3367
3368         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3369         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3370
3371         if (cs.unusable)
3372                 return false;
3373         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3374                 return false;
3375         if (!cs.s)
3376                 return false;
3377         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3378                 if (cs.dpl > cs_rpl)
3379                         return false;
3380         } else {
3381                 if (cs.dpl != cs_rpl)
3382                         return false;
3383         }
3384         if (!cs.present)
3385                 return false;
3386
3387         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3388         return true;
3389 }
3390
3391 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3392 {
3393         struct kvm_segment ss;
3394         unsigned int ss_rpl;
3395
3396         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3397         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3398
3399         if (ss.unusable)
3400                 return true;
3401         if (ss.type != 3 && ss.type != 7)
3402                 return false;
3403         if (!ss.s)
3404                 return false;
3405         if (ss.dpl != ss_rpl) /* DPL != RPL */
3406                 return false;
3407         if (!ss.present)
3408                 return false;
3409
3410         return true;
3411 }
3412
3413 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3414 {
3415         struct kvm_segment var;
3416         unsigned int rpl;
3417
3418         vmx_get_segment(vcpu, &var, seg);
3419         rpl = var.selector & SELECTOR_RPL_MASK;
3420
3421         if (var.unusable)
3422                 return true;
3423         if (!var.s)
3424                 return false;
3425         if (!var.present)
3426                 return false;
3427         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3428                 if (var.dpl < rpl) /* DPL < RPL */
3429                         return false;
3430         }
3431
3432         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3433          * rights flags
3434          */
3435         return true;
3436 }
3437
3438 static bool tr_valid(struct kvm_vcpu *vcpu)
3439 {
3440         struct kvm_segment tr;
3441
3442         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3443
3444         if (tr.unusable)
3445                 return false;
3446         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3447                 return false;
3448         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3449                 return false;
3450         if (!tr.present)
3451                 return false;
3452
3453         return true;
3454 }
3455
3456 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3457 {
3458         struct kvm_segment ldtr;
3459
3460         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3461
3462         if (ldtr.unusable)
3463                 return true;
3464         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3465                 return false;
3466         if (ldtr.type != 2)
3467                 return false;
3468         if (!ldtr.present)
3469                 return false;
3470
3471         return true;
3472 }
3473
3474 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3475 {
3476         struct kvm_segment cs, ss;
3477
3478         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3479         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3480
3481         return ((cs.selector & SELECTOR_RPL_MASK) ==
3482                  (ss.selector & SELECTOR_RPL_MASK));
3483 }
3484
3485 /*
3486  * Check if guest state is valid. Returns true if valid, false if
3487  * not.
3488  * We assume that registers are always usable
3489  */
3490 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3491 {
3492         /* real mode guest state checks */
3493         if (!is_protmode(vcpu)) {
3494                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3495                         return false;
3496                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3497                         return false;
3498                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3499                         return false;
3500                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3501                         return false;
3502                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3503                         return false;
3504                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3505                         return false;
3506         } else {
3507         /* protected mode guest state checks */
3508                 if (!cs_ss_rpl_check(vcpu))
3509                         return false;
3510                 if (!code_segment_valid(vcpu))
3511                         return false;
3512                 if (!stack_segment_valid(vcpu))
3513                         return false;
3514                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3515                         return false;
3516                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3517                         return false;
3518                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3519                         return false;
3520                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3521                         return false;
3522                 if (!tr_valid(vcpu))
3523                         return false;
3524                 if (!ldtr_valid(vcpu))
3525                         return false;
3526         }
3527         /* TODO:
3528          * - Add checks on RIP
3529          * - Add checks on RFLAGS
3530          */
3531
3532         return true;
3533 }
3534
3535 static int init_rmode_tss(struct kvm *kvm)
3536 {
3537         gfn_t fn;
3538         u16 data = 0;
3539         int r, idx, ret = 0;
3540
3541         idx = srcu_read_lock(&kvm->srcu);
3542         fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3543         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3544         if (r < 0)
3545                 goto out;
3546         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3547         r = kvm_write_guest_page(kvm, fn++, &data,
3548                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3549         if (r < 0)
3550                 goto out;
3551         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3552         if (r < 0)
3553                 goto out;
3554         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3555         if (r < 0)
3556                 goto out;
3557         data = ~0;
3558         r = kvm_write_guest_page(kvm, fn, &data,
3559                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3560                                  sizeof(u8));
3561         if (r < 0)
3562                 goto out;
3563
3564         ret = 1;
3565 out:
3566         srcu_read_unlock(&kvm->srcu, idx);
3567         return ret;
3568 }
3569
3570 static int init_rmode_identity_map(struct kvm *kvm)
3571 {
3572         int i, idx, r, ret;
3573         pfn_t identity_map_pfn;
3574         u32 tmp;
3575
3576         if (!enable_ept)
3577                 return 1;
3578         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3579                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3580                         "haven't been allocated!\n");
3581                 return 0;
3582         }
3583         if (likely(kvm->arch.ept_identity_pagetable_done))
3584                 return 1;
3585         ret = 0;
3586         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3587         idx = srcu_read_lock(&kvm->srcu);
3588         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3589         if (r < 0)
3590                 goto out;
3591         /* Set up identity-mapping pagetable for EPT in real mode */
3592         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3593                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3594                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3595                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3596                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3597                 if (r < 0)
3598                         goto out;
3599         }
3600         kvm->arch.ept_identity_pagetable_done = true;
3601         ret = 1;
3602 out:
3603         srcu_read_unlock(&kvm->srcu, idx);
3604         return ret;
3605 }
3606
3607 static void seg_setup(int seg)
3608 {
3609         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3610         unsigned int ar;
3611
3612         vmcs_write16(sf->selector, 0);
3613         vmcs_writel(sf->base, 0);
3614         vmcs_write32(sf->limit, 0xffff);
3615         if (enable_unrestricted_guest) {
3616                 ar = 0x93;
3617                 if (seg == VCPU_SREG_CS)
3618                         ar |= 0x08; /* code segment */
3619         } else
3620                 ar = 0xf3;
3621
3622         vmcs_write32(sf->ar_bytes, ar);
3623 }
3624
3625 static int alloc_apic_access_page(struct kvm *kvm)
3626 {
3627         struct kvm_userspace_memory_region kvm_userspace_mem;
3628         int r = 0;
3629
3630         mutex_lock(&kvm->slots_lock);
3631         if (kvm->arch.apic_access_page)
3632                 goto out;
3633         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3634         kvm_userspace_mem.flags = 0;
3635         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3636         kvm_userspace_mem.memory_size = PAGE_SIZE;
3637         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3638         if (r)
3639                 goto out;
3640
3641         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
3642 out:
3643         mutex_unlock(&kvm->slots_lock);
3644         return r;
3645 }
3646
3647 static int alloc_identity_pagetable(struct kvm *kvm)
3648 {
3649         struct kvm_userspace_memory_region kvm_userspace_mem;
3650         int r = 0;
3651
3652         mutex_lock(&kvm->slots_lock);
3653         if (kvm->arch.ept_identity_pagetable)
3654                 goto out;
3655         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3656         kvm_userspace_mem.flags = 0;
3657         kvm_userspace_mem.guest_phys_addr =
3658                 kvm->arch.ept_identity_map_addr;
3659         kvm_userspace_mem.memory_size = PAGE_SIZE;
3660         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3661         if (r)
3662                 goto out;
3663
3664         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
3665                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3666 out:
3667         mutex_unlock(&kvm->slots_lock);
3668         return r;
3669 }
3670
3671 static void allocate_vpid(struct vcpu_vmx *vmx)
3672 {
3673         int vpid;
3674
3675         vmx->vpid = 0;
3676         if (!enable_vpid)
3677                 return;
3678         spin_lock(&vmx_vpid_lock);
3679         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3680         if (vpid < VMX_NR_VPIDS) {
3681                 vmx->vpid = vpid;
3682                 __set_bit(vpid, vmx_vpid_bitmap);
3683         }
3684         spin_unlock(&vmx_vpid_lock);
3685 }
3686
3687 static void free_vpid(struct vcpu_vmx *vmx)
3688 {
3689         if (!enable_vpid)
3690                 return;
3691         spin_lock(&vmx_vpid_lock);
3692         if (vmx->vpid != 0)
3693                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3694         spin_unlock(&vmx_vpid_lock);
3695 }
3696
3697 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
3698 {
3699         int f = sizeof(unsigned long);
3700
3701         if (!cpu_has_vmx_msr_bitmap())
3702                 return;
3703
3704         /*
3705          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3706          * have the write-low and read-high bitmap offsets the wrong way round.
3707          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3708          */
3709         if (msr <= 0x1fff) {
3710                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3711                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
3712         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3713                 msr &= 0x1fff;
3714                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3715                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
3716         }
3717 }
3718
3719 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3720 {
3721         if (!longmode_only)
3722                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3723         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3724 }
3725
3726 /*
3727  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3728  * will not change in the lifetime of the guest.
3729  * Note that host-state that does change is set elsewhere. E.g., host-state
3730  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3731  */
3732 static void vmx_set_constant_host_state(void)
3733 {
3734         u32 low32, high32;
3735         unsigned long tmpl;
3736         struct desc_ptr dt;
3737
3738         vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS);  /* 22.2.3 */
3739         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
3740         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
3741
3742         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
3743 #ifdef CONFIG_X86_64
3744         /*
3745          * Load null selectors, so we can avoid reloading them in
3746          * __vmx_load_host_state(), in case userspace uses the null selectors
3747          * too (the expected case).
3748          */
3749         vmcs_write16(HOST_DS_SELECTOR, 0);
3750         vmcs_write16(HOST_ES_SELECTOR, 0);
3751 #else
3752         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3753         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3754 #endif
3755         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3756         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
3757
3758         native_store_idt(&dt);
3759         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
3760
3761         asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3762         vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3763
3764         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3765         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3766         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3767         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
3768
3769         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3770                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3771                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3772         }
3773 }
3774
3775 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3776 {
3777         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3778         if (enable_ept)
3779                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3780         if (is_guest_mode(&vmx->vcpu))
3781                 vmx->vcpu.arch.cr4_guest_owned_bits &=
3782                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3783         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3784 }
3785
3786 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3787 {
3788         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3789         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3790                 exec_control &= ~CPU_BASED_TPR_SHADOW;
3791 #ifdef CONFIG_X86_64
3792                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3793                                 CPU_BASED_CR8_LOAD_EXITING;
3794 #endif
3795         }
3796         if (!enable_ept)
3797                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3798                                 CPU_BASED_CR3_LOAD_EXITING  |
3799                                 CPU_BASED_INVLPG_EXITING;
3800         return exec_control;
3801 }
3802
3803 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3804 {
3805         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3806         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3807                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3808         if (vmx->vpid == 0)
3809                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3810         if (!enable_ept) {
3811                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3812                 enable_unrestricted_guest = 0;
3813                 /* Enable INVPCID for non-ept guests may cause performance regression. */
3814                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
3815         }
3816         if (!enable_unrestricted_guest)
3817                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3818         if (!ple_gap)
3819                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3820         return exec_control;
3821 }
3822
3823 static void ept_set_mmio_spte_mask(void)
3824 {
3825         /*
3826          * EPT Misconfigurations can be generated if the value of bits 2:0
3827          * of an EPT paging-structure entry is 110b (write/execute).
3828          * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3829          * spte.
3830          */
3831         kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3832 }
3833
3834 /*
3835  * Sets up the vmcs for emulated real mode.
3836  */
3837 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
3838 {
3839 #ifdef CONFIG_X86_64
3840         unsigned long a;
3841 #endif
3842         int i;
3843
3844         /* I/O */
3845         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3846         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
3847
3848         if (cpu_has_vmx_msr_bitmap())
3849                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
3850
3851         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3852
3853         /* Control */
3854         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3855                 vmcs_config.pin_based_exec_ctrl);
3856
3857         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
3858
3859         if (cpu_has_secondary_exec_ctrls()) {
3860                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3861                                 vmx_secondary_exec_control(vmx));
3862         }
3863
3864         if (ple_gap) {
3865                 vmcs_write32(PLE_GAP, ple_gap);
3866                 vmcs_write32(PLE_WINDOW, ple_window);
3867         }
3868
3869         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3870         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
3871         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
3872
3873         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
3874         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
3875         vmx_set_constant_host_state();
3876 #ifdef CONFIG_X86_64
3877         rdmsrl(MSR_FS_BASE, a);
3878         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3879         rdmsrl(MSR_GS_BASE, a);
3880         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3881 #else
3882         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3883         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3884 #endif
3885
3886         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3887         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
3888         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
3889         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
3890         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
3891
3892         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3893                 u32 msr_low, msr_high;
3894                 u64 host_pat;
3895                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3896                 host_pat = msr_low | ((u64) msr_high << 32);
3897                 /* Write the default value follow host pat */
3898                 vmcs_write64(GUEST_IA32_PAT, host_pat);
3899                 /* Keep arch.pat sync with GUEST_IA32_PAT */
3900                 vmx->vcpu.arch.pat = host_pat;
3901         }
3902
3903         for (i = 0; i < NR_VMX_MSR; ++i) {
3904                 u32 index = vmx_msr_index[i];
3905                 u32 data_low, data_high;
3906                 int j = vmx->nmsrs;
3907
3908                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3909                         continue;
3910                 if (wrmsr_safe(index, data_low, data_high) < 0)
3911                         continue;
3912                 vmx->guest_msrs[j].index = i;
3913                 vmx->guest_msrs[j].data = 0;
3914                 vmx->guest_msrs[j].mask = -1ull;
3915                 ++vmx->nmsrs;
3916         }
3917
3918         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
3919
3920         /* 22.2.1, 20.8.1 */
3921         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3922
3923         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
3924         set_cr4_guest_host_mask(vmx);
3925
3926         kvm_write_tsc(&vmx->vcpu, 0);
3927
3928         return 0;
3929 }
3930
3931 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3932 {
3933         struct vcpu_vmx *vmx = to_vmx(vcpu);
3934         u64 msr;
3935         int ret;
3936
3937         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3938
3939         vmx->rmode.vm86_active = 0;
3940
3941         vmx->soft_vnmi_blocked = 0;
3942
3943         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
3944         kvm_set_cr8(&vmx->vcpu, 0);
3945         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
3946         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3947                 msr |= MSR_IA32_APICBASE_BSP;
3948         kvm_set_apic_base(&vmx->vcpu, msr);
3949
3950         ret = fx_init(&vmx->vcpu);
3951         if (ret != 0)
3952                 goto out;
3953
3954         vmx_segment_cache_clear(vmx);
3955
3956         seg_setup(VCPU_SREG_CS);
3957         /*
3958          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3959          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
3960          */
3961         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
3962                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3963                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3964         } else {
3965                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3966                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
3967         }
3968
3969         seg_setup(VCPU_SREG_DS);
3970         seg_setup(VCPU_SREG_ES);
3971         seg_setup(VCPU_SREG_FS);
3972         seg_setup(VCPU_SREG_GS);
3973         seg_setup(VCPU_SREG_SS);
3974
3975         vmcs_write16(GUEST_TR_SELECTOR, 0);
3976         vmcs_writel(GUEST_TR_BASE, 0);
3977         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3978         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3979
3980         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3981         vmcs_writel(GUEST_LDTR_BASE, 0);
3982         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3983         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3984
3985         vmcs_write32(GUEST_SYSENTER_CS, 0);
3986         vmcs_writel(GUEST_SYSENTER_ESP, 0);
3987         vmcs_writel(GUEST_SYSENTER_EIP, 0);
3988
3989         vmcs_writel(GUEST_RFLAGS, 0x02);
3990         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3991                 kvm_rip_write(vcpu, 0xfff0);
3992         else
3993                 kvm_rip_write(vcpu, 0);
3994         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
3995
3996         vmcs_writel(GUEST_DR7, 0x400);
3997
3998         vmcs_writel(GUEST_GDTR_BASE, 0);
3999         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4000
4001         vmcs_writel(GUEST_IDTR_BASE, 0);
4002         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4003
4004         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4005         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4006         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4007
4008         /* Special registers */
4009         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4010
4011         setup_msrs(vmx);
4012
4013         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4014
4015         if (cpu_has_vmx_tpr_shadow()) {
4016                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4017                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4018                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4019                                      __pa(vmx->vcpu.arch.apic->regs));
4020                 vmcs_write32(TPR_THRESHOLD, 0);
4021         }
4022
4023         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4024                 vmcs_write64(APIC_ACCESS_ADDR,
4025                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
4026
4027         if (vmx->vpid != 0)
4028                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4029
4030         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4031         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
4032         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4033         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
4034         vmx_set_cr4(&vmx->vcpu, 0);
4035         vmx_set_efer(&vmx->vcpu, 0);
4036         vmx_fpu_activate(&vmx->vcpu);
4037         update_exception_bitmap(&vmx->vcpu);
4038
4039         vpid_sync_context(vmx);
4040
4041         ret = 0;
4042
4043         /* HACK: Don't enable emulation on guest boot/reset */
4044         vmx->emulation_required = 0;
4045
4046 out:
4047         return ret;
4048 }
4049
4050 /*
4051  * In nested virtualization, check if L1 asked to exit on external interrupts.
4052  * For most existing hypervisors, this will always return true.
4053  */
4054 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4055 {
4056         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4057                 PIN_BASED_EXT_INTR_MASK;
4058 }
4059
4060 static void enable_irq_window(struct kvm_vcpu *vcpu)
4061 {
4062         u32 cpu_based_vm_exec_control;
4063         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4064                 /*
4065                  * We get here if vmx_interrupt_allowed() said we can't
4066                  * inject to L1 now because L2 must run. Ask L2 to exit
4067                  * right after entry, so we can inject to L1 more promptly.
4068                  */
4069                 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
4070                 return;
4071         }
4072
4073         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4074         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4075         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4076 }
4077
4078 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4079 {
4080         u32 cpu_based_vm_exec_control;
4081
4082         if (!cpu_has_virtual_nmis()) {
4083                 enable_irq_window(vcpu);
4084                 return;
4085         }
4086
4087         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4088                 enable_irq_window(vcpu);
4089                 return;
4090         }
4091         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4092         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4093         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4094 }
4095
4096 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4097 {
4098         struct vcpu_vmx *vmx = to_vmx(vcpu);
4099         uint32_t intr;
4100         int irq = vcpu->arch.interrupt.nr;
4101
4102         trace_kvm_inj_virq(irq);
4103
4104         ++vcpu->stat.irq_injections;
4105         if (vmx->rmode.vm86_active) {
4106                 int inc_eip = 0;
4107                 if (vcpu->arch.interrupt.soft)
4108                         inc_eip = vcpu->arch.event_exit_inst_len;
4109                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4110                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4111                 return;
4112         }
4113         intr = irq | INTR_INFO_VALID_MASK;
4114         if (vcpu->arch.interrupt.soft) {
4115                 intr |= INTR_TYPE_SOFT_INTR;
4116                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4117                              vmx->vcpu.arch.event_exit_inst_len);
4118         } else
4119                 intr |= INTR_TYPE_EXT_INTR;
4120         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4121 }
4122
4123 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4124 {
4125         struct vcpu_vmx *vmx = to_vmx(vcpu);
4126
4127         if (is_guest_mode(vcpu))
4128                 return;
4129
4130         if (!cpu_has_virtual_nmis()) {
4131                 /*
4132                  * Tracking the NMI-blocked state in software is built upon
4133                  * finding the next open IRQ window. This, in turn, depends on
4134                  * well-behaving guests: They have to keep IRQs disabled at
4135                  * least as long as the NMI handler runs. Otherwise we may
4136                  * cause NMI nesting, maybe breaking the guest. But as this is
4137                  * highly unlikely, we can live with the residual risk.
4138                  */
4139                 vmx->soft_vnmi_blocked = 1;
4140                 vmx->vnmi_blocked_time = 0;
4141         }
4142
4143         ++vcpu->stat.nmi_injections;
4144         vmx->nmi_known_unmasked = false;
4145         if (vmx->rmode.vm86_active) {
4146                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4147                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4148                 return;
4149         }
4150         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4151                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4152 }
4153
4154 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4155 {
4156         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4157                 return 0;
4158
4159         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4160                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4161                    | GUEST_INTR_STATE_NMI));
4162 }
4163
4164 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4165 {
4166         if (!cpu_has_virtual_nmis())
4167                 return to_vmx(vcpu)->soft_vnmi_blocked;
4168         if (to_vmx(vcpu)->nmi_known_unmasked)
4169                 return false;
4170         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4171 }
4172
4173 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4174 {
4175         struct vcpu_vmx *vmx = to_vmx(vcpu);
4176
4177         if (!cpu_has_virtual_nmis()) {
4178                 if (vmx->soft_vnmi_blocked != masked) {
4179                         vmx->soft_vnmi_blocked = masked;
4180                         vmx->vnmi_blocked_time = 0;
4181                 }
4182         } else {
4183                 vmx->nmi_known_unmasked = !masked;
4184                 if (masked)
4185                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4186                                       GUEST_INTR_STATE_NMI);
4187                 else
4188                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4189                                         GUEST_INTR_STATE_NMI);
4190         }
4191 }
4192
4193 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4194 {
4195         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4196                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4197                 if (to_vmx(vcpu)->nested.nested_run_pending ||
4198                     (vmcs12->idt_vectoring_info_field &
4199                      VECTORING_INFO_VALID_MASK))
4200                         return 0;
4201                 nested_vmx_vmexit(vcpu);
4202                 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4203                 vmcs12->vm_exit_intr_info = 0;
4204                 /* fall through to normal code, but now in L1, not L2 */
4205         }
4206
4207         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4208                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4209                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4210 }
4211
4212 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4213 {
4214         int ret;
4215         struct kvm_userspace_memory_region tss_mem = {
4216                 .slot = TSS_PRIVATE_MEMSLOT,
4217                 .guest_phys_addr = addr,
4218                 .memory_size = PAGE_SIZE * 3,
4219                 .flags = 0,
4220         };
4221
4222         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
4223         if (ret)
4224                 return ret;
4225         kvm->arch.tss_addr = addr;
4226         if (!init_rmode_tss(kvm))
4227                 return  -ENOMEM;
4228
4229         return 0;
4230 }
4231
4232 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4233                                   int vec, u32 err_code)
4234 {
4235         /*
4236          * Instruction with address size override prefix opcode 0x67
4237          * Cause the #SS fault with 0 error code in VM86 mode.
4238          */
4239         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
4240                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
4241                         return 1;
4242         /*
4243          * Forward all other exceptions that are valid in real mode.
4244          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4245          *        the required debugging infrastructure rework.
4246          */
4247         switch (vec) {
4248         case DB_VECTOR:
4249                 if (vcpu->guest_debug &
4250                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4251                         return 0;
4252                 kvm_queue_exception(vcpu, vec);
4253                 return 1;
4254         case BP_VECTOR:
4255                 /*
4256                  * Update instruction length as we may reinject the exception
4257                  * from user space while in guest debugging mode.
4258                  */
4259                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4260                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4261                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4262                         return 0;
4263                 /* fall through */
4264         case DE_VECTOR:
4265         case OF_VECTOR:
4266         case BR_VECTOR:
4267         case UD_VECTOR:
4268         case DF_VECTOR:
4269         case SS_VECTOR:
4270         case GP_VECTOR:
4271         case MF_VECTOR:
4272                 kvm_queue_exception(vcpu, vec);
4273                 return 1;
4274         }
4275         return 0;
4276 }
4277
4278 /*
4279  * Trigger machine check on the host. We assume all the MSRs are already set up
4280  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4281  * We pass a fake environment to the machine check handler because we want
4282  * the guest to be always treated like user space, no matter what context
4283  * it used internally.
4284  */
4285 static void kvm_machine_check(void)
4286 {
4287 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4288         struct pt_regs regs = {
4289                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4290                 .flags = X86_EFLAGS_IF,
4291         };
4292
4293         do_machine_check(&regs, 0);
4294 #endif
4295 }
4296
4297 static int handle_machine_check(struct kvm_vcpu *vcpu)
4298 {
4299         /* already handled by vcpu_run */
4300         return 1;
4301 }
4302
4303 static int handle_exception(struct kvm_vcpu *vcpu)
4304 {
4305         struct vcpu_vmx *vmx = to_vmx(vcpu);
4306         struct kvm_run *kvm_run = vcpu->run;
4307         u32 intr_info, ex_no, error_code;
4308         unsigned long cr2, rip, dr6;
4309         u32 vect_info;
4310         enum emulation_result er;
4311
4312         vect_info = vmx->idt_vectoring_info;
4313         intr_info = vmx->exit_intr_info;
4314
4315         if (is_machine_check(intr_info))
4316                 return handle_machine_check(vcpu);
4317
4318         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4319             !is_page_fault(intr_info)) {
4320                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4321                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4322                 vcpu->run->internal.ndata = 2;
4323                 vcpu->run->internal.data[0] = vect_info;
4324                 vcpu->run->internal.data[1] = intr_info;
4325                 return 0;
4326         }
4327
4328         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4329                 return 1;  /* already handled by vmx_vcpu_run() */
4330
4331         if (is_no_device(intr_info)) {
4332                 vmx_fpu_activate(vcpu);
4333                 return 1;
4334         }
4335
4336         if (is_invalid_opcode(intr_info)) {
4337                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4338                 if (er != EMULATE_DONE)
4339                         kvm_queue_exception(vcpu, UD_VECTOR);
4340                 return 1;
4341         }
4342
4343         error_code = 0;
4344         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4345                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4346         if (is_page_fault(intr_info)) {
4347                 /* EPT won't cause page fault directly */
4348                 BUG_ON(enable_ept);
4349                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4350                 trace_kvm_page_fault(cr2, error_code);
4351
4352                 if (kvm_event_needs_reinjection(vcpu))
4353                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4354                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4355         }
4356
4357         if (vmx->rmode.vm86_active &&
4358             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
4359                                                                 error_code)) {
4360                 if (vcpu->arch.halt_request) {
4361                         vcpu->arch.halt_request = 0;
4362                         return kvm_emulate_halt(vcpu);
4363                 }
4364                 return 1;
4365         }
4366
4367         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4368         switch (ex_no) {
4369         case DB_VECTOR:
4370                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4371                 if (!(vcpu->guest_debug &
4372                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4373                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4374                         kvm_queue_exception(vcpu, DB_VECTOR);
4375                         return 1;
4376                 }
4377                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4378                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4379                 /* fall through */
4380         case BP_VECTOR:
4381                 /*
4382                  * Update instruction length as we may reinject #BP from
4383                  * user space while in guest debugging mode. Reading it for
4384                  * #DB as well causes no harm, it is not used in that case.
4385                  */
4386                 vmx->vcpu.arch.event_exit_inst_len =
4387                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4388                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4389                 rip = kvm_rip_read(vcpu);
4390                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4391                 kvm_run->debug.arch.exception = ex_no;
4392                 break;
4393         default:
4394                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4395                 kvm_run->ex.exception = ex_no;
4396                 kvm_run->ex.error_code = error_code;
4397                 break;
4398         }
4399         return 0;
4400 }
4401
4402 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4403 {
4404         ++vcpu->stat.irq_exits;
4405         return 1;
4406 }
4407
4408 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4409 {
4410         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4411         return 0;
4412 }
4413
4414 static int handle_io(struct kvm_vcpu *vcpu)
4415 {
4416         unsigned long exit_qualification;
4417         int size, in, string;
4418         unsigned port;
4419
4420         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4421         string = (exit_qualification & 16) != 0;
4422         in = (exit_qualification & 8) != 0;
4423
4424         ++vcpu->stat.io_exits;
4425
4426         if (string || in)
4427                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4428
4429         port = exit_qualification >> 16;
4430         size = (exit_qualification & 7) + 1;
4431         skip_emulated_instruction(vcpu);
4432
4433         return kvm_fast_pio_out(vcpu, size, port);
4434 }
4435
4436 static void
4437 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4438 {
4439         /*
4440          * Patch in the VMCALL instruction:
4441          */
4442         hypercall[0] = 0x0f;
4443         hypercall[1] = 0x01;
4444         hypercall[2] = 0xc1;
4445 }
4446
4447 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4448 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4449 {
4450         if (to_vmx(vcpu)->nested.vmxon &&
4451             ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4452                 return 1;
4453
4454         if (is_guest_mode(vcpu)) {
4455                 /*
4456                  * We get here when L2 changed cr0 in a way that did not change
4457                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4458                  * but did change L0 shadowed bits. This can currently happen
4459                  * with the TS bit: L0 may want to leave TS on (for lazy fpu
4460                  * loading) while pretending to allow the guest to change it.
4461                  */
4462                 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4463                          (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4464                         return 1;
4465                 vmcs_writel(CR0_READ_SHADOW, val);
4466                 return 0;
4467         } else
4468                 return kvm_set_cr0(vcpu, val);
4469 }
4470
4471 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4472 {
4473         if (is_guest_mode(vcpu)) {
4474                 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4475                          (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4476                         return 1;
4477                 vmcs_writel(CR4_READ_SHADOW, val);
4478                 return 0;
4479         } else
4480                 return kvm_set_cr4(vcpu, val);
4481 }
4482
4483 /* called to set cr0 as approriate for clts instruction exit. */
4484 static void handle_clts(struct kvm_vcpu *vcpu)
4485 {
4486         if (is_guest_mode(vcpu)) {
4487                 /*
4488                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4489                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4490                  * just pretend it's off (also in arch.cr0 for fpu_activate).
4491                  */
4492                 vmcs_writel(CR0_READ_SHADOW,
4493                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4494                 vcpu->arch.cr0 &= ~X86_CR0_TS;
4495         } else
4496                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4497 }
4498
4499 static int handle_cr(struct kvm_vcpu *vcpu)
4500 {
4501         unsigned long exit_qualification, val;
4502         int cr;
4503         int reg;
4504         int err;
4505
4506         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4507         cr = exit_qualification & 15;
4508         reg = (exit_qualification >> 8) & 15;
4509         switch ((exit_qualification >> 4) & 3) {
4510         case 0: /* mov to cr */
4511                 val = kvm_register_read(vcpu, reg);
4512                 trace_kvm_cr_write(cr, val);
4513                 switch (cr) {
4514                 case 0:
4515                         err = handle_set_cr0(vcpu, val);
4516                         kvm_complete_insn_gp(vcpu, err);
4517                         return 1;
4518                 case 3:
4519                         err = kvm_set_cr3(vcpu, val);
4520                         kvm_complete_insn_gp(vcpu, err);
4521                         return 1;
4522                 case 4:
4523                         err = handle_set_cr4(vcpu, val);
4524                         kvm_complete_insn_gp(vcpu, err);
4525                         return 1;
4526                 case 8: {
4527                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4528                                 u8 cr8 = kvm_register_read(vcpu, reg);
4529                                 err = kvm_set_cr8(vcpu, cr8);
4530                                 kvm_complete_insn_gp(vcpu, err);
4531                                 if (irqchip_in_kernel(vcpu->kvm))
4532                                         return 1;
4533                                 if (cr8_prev <= cr8)
4534                                         return 1;
4535                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4536                                 return 0;
4537                         }
4538                 };
4539                 break;
4540         case 2: /* clts */
4541                 handle_clts(vcpu);
4542                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4543                 skip_emulated_instruction(vcpu);
4544                 vmx_fpu_activate(vcpu);
4545                 return 1;
4546         case 1: /*mov from cr*/
4547                 switch (cr) {
4548                 case 3:
4549                         val = kvm_read_cr3(vcpu);
4550                         kvm_register_write(vcpu, reg, val);
4551                         trace_kvm_cr_read(cr, val);
4552                         skip_emulated_instruction(vcpu);
4553                         return 1;
4554                 case 8:
4555                         val = kvm_get_cr8(vcpu);
4556                         kvm_register_write(vcpu, reg, val);
4557                         trace_kvm_cr_read(cr, val);
4558                         skip_emulated_instruction(vcpu);
4559                         return 1;
4560                 }
4561                 break;
4562         case 3: /* lmsw */
4563                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4564                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4565                 kvm_lmsw(vcpu, val);
4566
4567                 skip_emulated_instruction(vcpu);
4568                 return 1;
4569         default:
4570                 break;
4571         }
4572         vcpu->run->exit_reason = 0;
4573         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4574                (int)(exit_qualification >> 4) & 3, cr);
4575         return 0;
4576 }
4577
4578 static int handle_dr(struct kvm_vcpu *vcpu)
4579 {
4580         unsigned long exit_qualification;
4581         int dr, reg;
4582
4583         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4584         if (!kvm_require_cpl(vcpu, 0))
4585                 return 1;
4586         dr = vmcs_readl(GUEST_DR7);
4587         if (dr & DR7_GD) {
4588                 /*
4589                  * As the vm-exit takes precedence over the debug trap, we
4590                  * need to emulate the latter, either for the host or the
4591                  * guest debugging itself.
4592                  */
4593                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4594                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4595                         vcpu->run->debug.arch.dr7 = dr;
4596                         vcpu->run->debug.arch.pc =
4597                                 vmcs_readl(GUEST_CS_BASE) +
4598                                 vmcs_readl(GUEST_RIP);
4599                         vcpu->run->debug.arch.exception = DB_VECTOR;
4600                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4601                         return 0;
4602                 } else {
4603                         vcpu->arch.dr7 &= ~DR7_GD;
4604                         vcpu->arch.dr6 |= DR6_BD;
4605                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4606                         kvm_queue_exception(vcpu, DB_VECTOR);
4607                         return 1;
4608                 }
4609         }
4610
4611         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4612         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4613         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4614         if (exit_qualification & TYPE_MOV_FROM_DR) {
4615                 unsigned long val;
4616                 if (!kvm_get_dr(vcpu, dr, &val))
4617                         kvm_register_write(vcpu, reg, val);
4618         } else
4619                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
4620         skip_emulated_instruction(vcpu);
4621         return 1;
4622 }
4623
4624 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4625 {
4626         vmcs_writel(GUEST_DR7, val);
4627 }
4628
4629 static int handle_cpuid(struct kvm_vcpu *vcpu)
4630 {
4631         kvm_emulate_cpuid(vcpu);
4632         return 1;
4633 }
4634
4635 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4636 {
4637         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4638         u64 data;
4639
4640         if (vmx_get_msr(vcpu, ecx, &data)) {
4641                 trace_kvm_msr_read_ex(ecx);
4642                 kvm_inject_gp(vcpu, 0);
4643                 return 1;
4644         }
4645
4646         trace_kvm_msr_read(ecx, data);
4647
4648         /* FIXME: handling of bits 32:63 of rax, rdx */
4649         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4650         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
4651         skip_emulated_instruction(vcpu);
4652         return 1;
4653 }
4654
4655 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4656 {
4657         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4658         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4659                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4660
4661         if (vmx_set_msr(vcpu, ecx, data) != 0) {
4662                 trace_kvm_msr_write_ex(ecx, data);
4663                 kvm_inject_gp(vcpu, 0);
4664                 return 1;
4665         }
4666
4667         trace_kvm_msr_write(ecx, data);
4668         skip_emulated_instruction(vcpu);
4669         return 1;
4670 }
4671
4672 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4673 {
4674         kvm_make_request(KVM_REQ_EVENT, vcpu);
4675         return 1;
4676 }
4677
4678 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4679 {
4680         u32 cpu_based_vm_exec_control;
4681
4682         /* clear pending irq */
4683         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4684         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4685         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4686
4687         kvm_make_request(KVM_REQ_EVENT, vcpu);
4688
4689         ++vcpu->stat.irq_window_exits;
4690
4691         /*
4692          * If the user space waits to inject interrupts, exit as soon as
4693          * possible
4694          */
4695         if (!irqchip_in_kernel(vcpu->kvm) &&
4696             vcpu->run->request_interrupt_window &&
4697             !kvm_cpu_has_interrupt(vcpu)) {
4698                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
4699                 return 0;
4700         }
4701         return 1;
4702 }
4703
4704 static int handle_halt(struct kvm_vcpu *vcpu)
4705 {
4706         skip_emulated_instruction(vcpu);
4707         return kvm_emulate_halt(vcpu);
4708 }
4709
4710 static int handle_vmcall(struct kvm_vcpu *vcpu)
4711 {
4712         skip_emulated_instruction(vcpu);
4713         kvm_emulate_hypercall(vcpu);
4714         return 1;
4715 }
4716
4717 static int handle_invd(struct kvm_vcpu *vcpu)
4718 {
4719         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4720 }
4721
4722 static int handle_invlpg(struct kvm_vcpu *vcpu)
4723 {
4724         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4725
4726         kvm_mmu_invlpg(vcpu, exit_qualification);
4727         skip_emulated_instruction(vcpu);
4728         return 1;
4729 }
4730
4731 static int handle_rdpmc(struct kvm_vcpu *vcpu)
4732 {
4733         int err;
4734
4735         err = kvm_rdpmc(vcpu);
4736         kvm_complete_insn_gp(vcpu, err);
4737
4738         return 1;
4739 }
4740
4741 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4742 {
4743         skip_emulated_instruction(vcpu);
4744         kvm_emulate_wbinvd(vcpu);
4745         return 1;
4746 }
4747
4748 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4749 {
4750         u64 new_bv = kvm_read_edx_eax(vcpu);
4751         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4752
4753         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4754                 skip_emulated_instruction(vcpu);
4755         return 1;
4756 }
4757
4758 static int handle_apic_access(struct kvm_vcpu *vcpu)
4759 {
4760         if (likely(fasteoi)) {
4761                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4762                 int access_type, offset;
4763
4764                 access_type = exit_qualification & APIC_ACCESS_TYPE;
4765                 offset = exit_qualification & APIC_ACCESS_OFFSET;
4766                 /*
4767                  * Sane guest uses MOV to write EOI, with written value
4768                  * not cared. So make a short-circuit here by avoiding
4769                  * heavy instruction emulation.
4770                  */
4771                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4772                     (offset == APIC_EOI)) {
4773                         kvm_lapic_set_eoi(vcpu);
4774                         skip_emulated_instruction(vcpu);
4775                         return 1;
4776                 }
4777         }
4778         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4779 }
4780
4781 static int handle_task_switch(struct kvm_vcpu *vcpu)
4782 {
4783         struct vcpu_vmx *vmx = to_vmx(vcpu);
4784         unsigned long exit_qualification;
4785         bool has_error_code = false;
4786         u32 error_code = 0;
4787         u16 tss_selector;
4788         int reason, type, idt_v, idt_index;
4789
4790         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4791         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
4792         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
4793
4794         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4795
4796         reason = (u32)exit_qualification >> 30;
4797         if (reason == TASK_SWITCH_GATE && idt_v) {
4798                 switch (type) {
4799                 case INTR_TYPE_NMI_INTR:
4800                         vcpu->arch.nmi_injected = false;
4801                         vmx_set_nmi_mask(vcpu, true);
4802                         break;
4803                 case INTR_TYPE_EXT_INTR:
4804                 case INTR_TYPE_SOFT_INTR:
4805                         kvm_clear_interrupt_queue(vcpu);
4806                         break;
4807                 case INTR_TYPE_HARD_EXCEPTION:
4808                         if (vmx->idt_vectoring_info &
4809                             VECTORING_INFO_DELIVER_CODE_MASK) {
4810                                 has_error_code = true;
4811                                 error_code =
4812                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
4813                         }
4814                         /* fall through */
4815                 case INTR_TYPE_SOFT_EXCEPTION:
4816                         kvm_clear_exception_queue(vcpu);
4817                         break;
4818                 default:
4819                         break;
4820                 }
4821         }
4822         tss_selector = exit_qualification;
4823
4824         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4825                        type != INTR_TYPE_EXT_INTR &&
4826                        type != INTR_TYPE_NMI_INTR))
4827                 skip_emulated_instruction(vcpu);
4828
4829         if (kvm_task_switch(vcpu, tss_selector,
4830                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
4831                             has_error_code, error_code) == EMULATE_FAIL) {
4832                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4833                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4834                 vcpu->run->internal.ndata = 0;
4835                 return 0;
4836         }
4837
4838         /* clear all local breakpoint enable flags */
4839         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4840
4841         /*
4842          * TODO: What about debug traps on tss switch?
4843          *       Are we supposed to inject them and update dr6?
4844          */
4845
4846         return 1;
4847 }
4848
4849 static int handle_ept_violation(struct kvm_vcpu *vcpu)
4850 {
4851         unsigned long exit_qualification;
4852         gpa_t gpa;
4853         u32 error_code;
4854         int gla_validity;
4855
4856         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4857
4858         if (exit_qualification & (1 << 6)) {
4859                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
4860                 return -EINVAL;
4861         }
4862
4863         gla_validity = (exit_qualification >> 7) & 0x3;
4864         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4865                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4866                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4867                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
4868                         vmcs_readl(GUEST_LINEAR_ADDRESS));
4869                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4870                         (long unsigned int)exit_qualification);
4871                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4872                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
4873                 return 0;
4874         }
4875
4876         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4877         trace_kvm_page_fault(gpa, exit_qualification);
4878
4879         /* It is a write fault? */
4880         error_code = exit_qualification & (1U << 1);
4881         /* ept page table is present? */
4882         error_code |= (exit_qualification >> 3) & 0x1;
4883
4884         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
4885 }
4886
4887 static u64 ept_rsvd_mask(u64 spte, int level)
4888 {
4889         int i;
4890         u64 mask = 0;
4891
4892         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4893                 mask |= (1ULL << i);
4894
4895         if (level > 2)
4896                 /* bits 7:3 reserved */
4897                 mask |= 0xf8;
4898         else if (level == 2) {
4899                 if (spte & (1ULL << 7))
4900                         /* 2MB ref, bits 20:12 reserved */
4901                         mask |= 0x1ff000;
4902                 else
4903                         /* bits 6:3 reserved */
4904                         mask |= 0x78;
4905         }
4906
4907         return mask;
4908 }
4909
4910 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4911                                        int level)
4912 {
4913         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4914
4915         /* 010b (write-only) */
4916         WARN_ON((spte & 0x7) == 0x2);
4917
4918         /* 110b (write/execute) */
4919         WARN_ON((spte & 0x7) == 0x6);
4920
4921         /* 100b (execute-only) and value not supported by logical processor */
4922         if (!cpu_has_vmx_ept_execute_only())
4923                 WARN_ON((spte & 0x7) == 0x4);
4924
4925         /* not 000b */
4926         if ((spte & 0x7)) {
4927                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4928
4929                 if (rsvd_bits != 0) {
4930                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4931                                          __func__, rsvd_bits);
4932                         WARN_ON(1);
4933                 }
4934
4935                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4936                         u64 ept_mem_type = (spte & 0x38) >> 3;
4937
4938                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
4939                             ept_mem_type == 7) {
4940                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4941                                                 __func__, ept_mem_type);
4942                                 WARN_ON(1);
4943                         }
4944                 }
4945         }
4946 }
4947
4948 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
4949 {
4950         u64 sptes[4];
4951         int nr_sptes, i, ret;
4952         gpa_t gpa;
4953
4954         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4955
4956         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4957         if (likely(ret == 1))
4958                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4959                                               EMULATE_DONE;
4960         if (unlikely(!ret))
4961                 return 1;
4962
4963         /* It is the real ept misconfig */
4964         printk(KERN_ERR "EPT: Misconfiguration.\n");
4965         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4966
4967         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4968
4969         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4970                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4971
4972         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4973         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
4974
4975         return 0;
4976 }
4977
4978 static int handle_nmi_window(struct kvm_vcpu *vcpu)
4979 {
4980         u32 cpu_based_vm_exec_control;
4981
4982         /* clear pending NMI */
4983         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4984         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4985         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4986         ++vcpu->stat.nmi_window_exits;
4987         kvm_make_request(KVM_REQ_EVENT, vcpu);
4988
4989         return 1;
4990 }
4991
4992 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
4993 {
4994         struct vcpu_vmx *vmx = to_vmx(vcpu);
4995         enum emulation_result err = EMULATE_DONE;
4996         int ret = 1;
4997         u32 cpu_exec_ctrl;
4998         bool intr_window_requested;
4999         unsigned count = 130;
5000
5001         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5002         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5003
5004         while (!guest_state_valid(vcpu) && count-- != 0) {
5005                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5006                         return handle_interrupt_window(&vmx->vcpu);
5007
5008                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5009                         return 1;
5010
5011                 err = emulate_instruction(vcpu, 0);
5012
5013                 if (err == EMULATE_DO_MMIO) {
5014                         ret = 0;
5015                         goto out;
5016                 }
5017
5018                 if (err != EMULATE_DONE) {
5019                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5020                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5021                         vcpu->run->internal.ndata = 0;
5022                         return 0;
5023                 }
5024
5025                 if (signal_pending(current))
5026                         goto out;
5027                 if (need_resched())
5028                         schedule();
5029         }
5030
5031         vmx->emulation_required = !guest_state_valid(vcpu);
5032 out:
5033         return ret;
5034 }
5035
5036 /*
5037  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5038  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5039  */
5040 static int handle_pause(struct kvm_vcpu *vcpu)
5041 {
5042         skip_emulated_instruction(vcpu);
5043         kvm_vcpu_on_spin(vcpu);
5044
5045         return 1;
5046 }
5047
5048 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5049 {
5050         kvm_queue_exception(vcpu, UD_VECTOR);
5051         return 1;
5052 }
5053
5054 /*
5055  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5056  * We could reuse a single VMCS for all the L2 guests, but we also want the
5057  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5058  * allows keeping them loaded on the processor, and in the future will allow
5059  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5060  * every entry if they never change.
5061  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5062  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5063  *
5064  * The following functions allocate and free a vmcs02 in this pool.
5065  */
5066
5067 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5068 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5069 {
5070         struct vmcs02_list *item;
5071         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5072                 if (item->vmptr == vmx->nested.current_vmptr) {
5073                         list_move(&item->list, &vmx->nested.vmcs02_pool);
5074                         return &item->vmcs02;
5075                 }
5076
5077         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5078                 /* Recycle the least recently used VMCS. */
5079                 item = list_entry(vmx->nested.vmcs02_pool.prev,
5080                         struct vmcs02_list, list);
5081                 item->vmptr = vmx->nested.current_vmptr;
5082                 list_move(&item->list, &vmx->nested.vmcs02_pool);
5083                 return &item->vmcs02;
5084         }
5085
5086         /* Create a new VMCS */
5087         item = (struct vmcs02_list *)
5088                 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5089         if (!item)
5090                 return NULL;
5091         item->vmcs02.vmcs = alloc_vmcs();
5092         if (!item->vmcs02.vmcs) {
5093                 kfree(item);
5094                 return NULL;
5095         }
5096         loaded_vmcs_init(&item->vmcs02);
5097         item->vmptr = vmx->nested.current_vmptr;
5098         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5099         vmx->nested.vmcs02_num++;
5100         return &item->vmcs02;
5101 }
5102
5103 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5104 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5105 {
5106         struct vmcs02_list *item;
5107         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5108                 if (item->vmptr == vmptr) {
5109                         free_loaded_vmcs(&item->vmcs02);
5110                         list_del(&item->list);
5111                         kfree(item);
5112                         vmx->nested.vmcs02_num--;
5113                         return;
5114                 }
5115 }
5116
5117 /*
5118  * Free all VMCSs saved for this vcpu, except the one pointed by
5119  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5120  * currently used, if running L2), and vmcs01 when running L2.
5121  */
5122 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5123 {
5124         struct vmcs02_list *item, *n;
5125         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5126                 if (vmx->loaded_vmcs != &item->vmcs02)
5127                         free_loaded_vmcs(&item->vmcs02);
5128                 list_del(&item->list);
5129                 kfree(item);
5130         }
5131         vmx->nested.vmcs02_num = 0;
5132
5133         if (vmx->loaded_vmcs != &vmx->vmcs01)
5134                 free_loaded_vmcs(&vmx->vmcs01);
5135 }
5136
5137 /*
5138  * Emulate the VMXON instruction.
5139  * Currently, we just remember that VMX is active, and do not save or even
5140  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5141  * do not currently need to store anything in that guest-allocated memory
5142  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5143  * argument is different from the VMXON pointer (which the spec says they do).
5144  */
5145 static int handle_vmon(struct kvm_vcpu *vcpu)
5146 {
5147         struct kvm_segment cs;
5148         struct vcpu_vmx *vmx = to_vmx(vcpu);
5149
5150         /* The Intel VMX Instruction Reference lists a bunch of bits that
5151          * are prerequisite to running VMXON, most notably cr4.VMXE must be
5152          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5153          * Otherwise, we should fail with #UD. We test these now:
5154          */
5155         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5156             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5157             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5158                 kvm_queue_exception(vcpu, UD_VECTOR);
5159                 return 1;
5160         }
5161
5162         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5163         if (is_long_mode(vcpu) && !cs.l) {
5164                 kvm_queue_exception(vcpu, UD_VECTOR);
5165                 return 1;
5166         }
5167
5168         if (vmx_get_cpl(vcpu)) {
5169                 kvm_inject_gp(vcpu, 0);
5170                 return 1;
5171         }
5172
5173         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5174         vmx->nested.vmcs02_num = 0;
5175
5176         vmx->nested.vmxon = true;
5177
5178         skip_emulated_instruction(vcpu);
5179         return 1;
5180 }
5181
5182 /*
5183  * Intel's VMX Instruction Reference specifies a common set of prerequisites
5184  * for running VMX instructions (except VMXON, whose prerequisites are
5185  * slightly different). It also specifies what exception to inject otherwise.
5186  */
5187 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5188 {
5189         struct kvm_segment cs;
5190         struct vcpu_vmx *vmx = to_vmx(vcpu);
5191
5192         if (!vmx->nested.vmxon) {
5193                 kvm_queue_exception(vcpu, UD_VECTOR);
5194                 return 0;
5195         }
5196
5197         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5198         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5199             (is_long_mode(vcpu) && !cs.l)) {
5200                 kvm_queue_exception(vcpu, UD_VECTOR);
5201                 return 0;
5202         }
5203
5204         if (vmx_get_cpl(vcpu)) {
5205                 kvm_inject_gp(vcpu, 0);
5206                 return 0;
5207         }
5208
5209         return 1;
5210 }
5211
5212 /*
5213  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5214  * just stops using VMX.
5215  */
5216 static void free_nested(struct vcpu_vmx *vmx)
5217 {
5218         if (!vmx->nested.vmxon)
5219                 return;
5220         vmx->nested.vmxon = false;
5221         if (vmx->nested.current_vmptr != -1ull) {
5222                 kunmap(vmx->nested.current_vmcs12_page);
5223                 nested_release_page(vmx->nested.current_vmcs12_page);
5224                 vmx->nested.current_vmptr = -1ull;
5225                 vmx->nested.current_vmcs12 = NULL;
5226         }
5227         /* Unpin physical memory we referred to in current vmcs02 */
5228         if (vmx->nested.apic_access_page) {
5229                 nested_release_page(vmx->nested.apic_access_page);
5230                 vmx->nested.apic_access_page = 0;
5231         }
5232
5233         nested_free_all_saved_vmcss(vmx);
5234 }
5235
5236 /* Emulate the VMXOFF instruction */
5237 static int handle_vmoff(struct kvm_vcpu *vcpu)
5238 {
5239         if (!nested_vmx_check_permission(vcpu))
5240                 return 1;
5241         free_nested(to_vmx(vcpu));
5242         skip_emulated_instruction(vcpu);
5243         return 1;
5244 }
5245
5246 /*
5247  * Decode the memory-address operand of a vmx instruction, as recorded on an
5248  * exit caused by such an instruction (run by a guest hypervisor).
5249  * On success, returns 0. When the operand is invalid, returns 1 and throws
5250  * #UD or #GP.
5251  */
5252 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5253                                  unsigned long exit_qualification,
5254                                  u32 vmx_instruction_info, gva_t *ret)
5255 {
5256         /*
5257          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5258          * Execution", on an exit, vmx_instruction_info holds most of the
5259          * addressing components of the operand. Only the displacement part
5260          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5261          * For how an actual address is calculated from all these components,
5262          * refer to Vol. 1, "Operand Addressing".
5263          */
5264         int  scaling = vmx_instruction_info & 3;
5265         int  addr_size = (vmx_instruction_info >> 7) & 7;
5266         bool is_reg = vmx_instruction_info & (1u << 10);
5267         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5268         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5269         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5270         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5271         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
5272
5273         if (is_reg) {
5274                 kvm_queue_exception(vcpu, UD_VECTOR);
5275                 return 1;
5276         }
5277
5278         /* Addr = segment_base + offset */
5279         /* offset = base + [index * scale] + displacement */
5280         *ret = vmx_get_segment_base(vcpu, seg_reg);
5281         if (base_is_valid)
5282                 *ret += kvm_register_read(vcpu, base_reg);
5283         if (index_is_valid)
5284                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5285         *ret += exit_qualification; /* holds the displacement */
5286
5287         if (addr_size == 1) /* 32 bit */
5288                 *ret &= 0xffffffff;
5289
5290         /*
5291          * TODO: throw #GP (and return 1) in various cases that the VM*
5292          * instructions require it - e.g., offset beyond segment limit,
5293          * unusable or unreadable/unwritable segment, non-canonical 64-bit
5294          * address, and so on. Currently these are not checked.
5295          */
5296         return 0;
5297 }
5298
5299 /*
5300  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5301  * set the success or error code of an emulated VMX instruction, as specified
5302  * by Vol 2B, VMX Instruction Reference, "Conventions".
5303  */
5304 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5305 {
5306         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5307                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5308                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5309 }
5310
5311 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5312 {
5313         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5314                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5315                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5316                         | X86_EFLAGS_CF);
5317 }
5318
5319 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5320                                         u32 vm_instruction_error)
5321 {
5322         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5323                 /*
5324                  * failValid writes the error number to the current VMCS, which
5325                  * can't be done there isn't a current VMCS.
5326                  */
5327                 nested_vmx_failInvalid(vcpu);
5328                 return;
5329         }
5330         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5331                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5332                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5333                         | X86_EFLAGS_ZF);
5334         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5335 }
5336
5337 /* Emulate the VMCLEAR instruction */
5338 static int handle_vmclear(struct kvm_vcpu *vcpu)
5339 {
5340         struct vcpu_vmx *vmx = to_vmx(vcpu);
5341         gva_t gva;
5342         gpa_t vmptr;
5343         struct vmcs12 *vmcs12;
5344         struct page *page;
5345         struct x86_exception e;
5346
5347         if (!nested_vmx_check_permission(vcpu))
5348                 return 1;
5349
5350         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5351                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5352                 return 1;
5353
5354         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5355                                 sizeof(vmptr), &e)) {
5356                 kvm_inject_page_fault(vcpu, &e);
5357                 return 1;
5358         }
5359
5360         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5361                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5362                 skip_emulated_instruction(vcpu);
5363                 return 1;
5364         }
5365
5366         if (vmptr == vmx->nested.current_vmptr) {
5367                 kunmap(vmx->nested.current_vmcs12_page);
5368                 nested_release_page(vmx->nested.current_vmcs12_page);
5369                 vmx->nested.current_vmptr = -1ull;
5370                 vmx->nested.current_vmcs12 = NULL;
5371         }
5372
5373         page = nested_get_page(vcpu, vmptr);
5374         if (page == NULL) {
5375                 /*
5376                  * For accurate processor emulation, VMCLEAR beyond available
5377                  * physical memory should do nothing at all. However, it is
5378                  * possible that a nested vmx bug, not a guest hypervisor bug,
5379                  * resulted in this case, so let's shut down before doing any
5380                  * more damage:
5381                  */
5382                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5383                 return 1;
5384         }
5385         vmcs12 = kmap(page);
5386         vmcs12->launch_state = 0;
5387         kunmap(page);
5388         nested_release_page(page);
5389
5390         nested_free_vmcs02(vmx, vmptr);
5391
5392         skip_emulated_instruction(vcpu);
5393         nested_vmx_succeed(vcpu);
5394         return 1;
5395 }
5396
5397 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5398
5399 /* Emulate the VMLAUNCH instruction */
5400 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5401 {
5402         return nested_vmx_run(vcpu, true);
5403 }
5404
5405 /* Emulate the VMRESUME instruction */
5406 static int handle_vmresume(struct kvm_vcpu *vcpu)
5407 {
5408
5409         return nested_vmx_run(vcpu, false);
5410 }
5411
5412 enum vmcs_field_type {
5413         VMCS_FIELD_TYPE_U16 = 0,
5414         VMCS_FIELD_TYPE_U64 = 1,
5415         VMCS_FIELD_TYPE_U32 = 2,
5416         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5417 };
5418
5419 static inline int vmcs_field_type(unsigned long field)
5420 {
5421         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
5422                 return VMCS_FIELD_TYPE_U32;
5423         return (field >> 13) & 0x3 ;
5424 }
5425
5426 static inline int vmcs_field_readonly(unsigned long field)
5427 {
5428         return (((field >> 10) & 0x3) == 1);
5429 }
5430
5431 /*
5432  * Read a vmcs12 field. Since these can have varying lengths and we return
5433  * one type, we chose the biggest type (u64) and zero-extend the return value
5434  * to that size. Note that the caller, handle_vmread, might need to use only
5435  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5436  * 64-bit fields are to be returned).
5437  */
5438 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5439                                         unsigned long field, u64 *ret)
5440 {
5441         short offset = vmcs_field_to_offset(field);
5442         char *p;
5443
5444         if (offset < 0)
5445                 return 0;
5446
5447         p = ((char *)(get_vmcs12(vcpu))) + offset;
5448
5449         switch (vmcs_field_type(field)) {
5450         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5451                 *ret = *((natural_width *)p);
5452                 return 1;
5453         case VMCS_FIELD_TYPE_U16:
5454                 *ret = *((u16 *)p);
5455                 return 1;
5456         case VMCS_FIELD_TYPE_U32:
5457                 *ret = *((u32 *)p);
5458                 return 1;
5459         case VMCS_FIELD_TYPE_U64:
5460                 *ret = *((u64 *)p);
5461                 return 1;
5462         default:
5463                 return 0; /* can never happen. */
5464         }
5465 }
5466
5467 /*
5468  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5469  * used before) all generate the same failure when it is missing.
5470  */
5471 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5472 {
5473         struct vcpu_vmx *vmx = to_vmx(vcpu);
5474         if (vmx->nested.current_vmptr == -1ull) {
5475                 nested_vmx_failInvalid(vcpu);
5476                 skip_emulated_instruction(vcpu);
5477                 return 0;
5478         }
5479         return 1;
5480 }
5481
5482 static int handle_vmread(struct kvm_vcpu *vcpu)
5483 {
5484         unsigned long field;
5485         u64 field_value;
5486         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5487         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5488         gva_t gva = 0;
5489
5490         if (!nested_vmx_check_permission(vcpu) ||
5491             !nested_vmx_check_vmcs12(vcpu))
5492                 return 1;
5493
5494         /* Decode instruction info and find the field to read */
5495         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5496         /* Read the field, zero-extended to a u64 field_value */
5497         if (!vmcs12_read_any(vcpu, field, &field_value)) {
5498                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5499                 skip_emulated_instruction(vcpu);
5500                 return 1;
5501         }
5502         /*
5503          * Now copy part of this value to register or memory, as requested.
5504          * Note that the number of bits actually copied is 32 or 64 depending
5505          * on the guest's mode (32 or 64 bit), not on the given field's length.
5506          */
5507         if (vmx_instruction_info & (1u << 10)) {
5508                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5509                         field_value);
5510         } else {
5511                 if (get_vmx_mem_address(vcpu, exit_qualification,
5512                                 vmx_instruction_info, &gva))
5513                         return 1;
5514                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5515                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5516                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5517         }
5518
5519         nested_vmx_succeed(vcpu);
5520         skip_emulated_instruction(vcpu);
5521         return 1;
5522 }
5523
5524
5525 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5526 {
5527         unsigned long field;
5528         gva_t gva;
5529         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5530         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5531         char *p;
5532         short offset;
5533         /* The value to write might be 32 or 64 bits, depending on L1's long
5534          * mode, and eventually we need to write that into a field of several
5535          * possible lengths. The code below first zero-extends the value to 64
5536          * bit (field_value), and then copies only the approriate number of
5537          * bits into the vmcs12 field.
5538          */
5539         u64 field_value = 0;
5540         struct x86_exception e;
5541
5542         if (!nested_vmx_check_permission(vcpu) ||
5543             !nested_vmx_check_vmcs12(vcpu))
5544                 return 1;
5545
5546         if (vmx_instruction_info & (1u << 10))
5547                 field_value = kvm_register_read(vcpu,
5548                         (((vmx_instruction_info) >> 3) & 0xf));
5549         else {
5550                 if (get_vmx_mem_address(vcpu, exit_qualification,
5551                                 vmx_instruction_info, &gva))
5552                         return 1;
5553                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5554                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5555                         kvm_inject_page_fault(vcpu, &e);
5556                         return 1;
5557                 }
5558         }
5559
5560
5561         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5562         if (vmcs_field_readonly(field)) {
5563                 nested_vmx_failValid(vcpu,
5564                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5565                 skip_emulated_instruction(vcpu);
5566                 return 1;
5567         }
5568
5569         offset = vmcs_field_to_offset(field);
5570         if (offset < 0) {
5571                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5572                 skip_emulated_instruction(vcpu);
5573                 return 1;
5574         }
5575         p = ((char *) get_vmcs12(vcpu)) + offset;
5576
5577         switch (vmcs_field_type(field)) {
5578         case VMCS_FIELD_TYPE_U16:
5579                 *(u16 *)p = field_value;
5580                 break;
5581         case VMCS_FIELD_TYPE_U32:
5582                 *(u32 *)p = field_value;
5583                 break;
5584         case VMCS_FIELD_TYPE_U64:
5585                 *(u64 *)p = field_value;
5586                 break;
5587         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5588                 *(natural_width *)p = field_value;
5589                 break;
5590         default:
5591                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5592                 skip_emulated_instruction(vcpu);
5593                 return 1;
5594         }
5595
5596         nested_vmx_succeed(vcpu);
5597         skip_emulated_instruction(vcpu);
5598         return 1;
5599 }
5600
5601 /* Emulate the VMPTRLD instruction */
5602 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5603 {
5604         struct vcpu_vmx *vmx = to_vmx(vcpu);
5605         gva_t gva;
5606         gpa_t vmptr;
5607         struct x86_exception e;
5608
5609         if (!nested_vmx_check_permission(vcpu))
5610                 return 1;
5611
5612         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5613                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5614                 return 1;
5615
5616         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5617                                 sizeof(vmptr), &e)) {
5618                 kvm_inject_page_fault(vcpu, &e);
5619                 return 1;
5620         }
5621
5622         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5623                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5624                 skip_emulated_instruction(vcpu);
5625                 return 1;
5626         }
5627
5628         if (vmx->nested.current_vmptr != vmptr) {
5629                 struct vmcs12 *new_vmcs12;
5630                 struct page *page;
5631                 page = nested_get_page(vcpu, vmptr);
5632                 if (page == NULL) {
5633                         nested_vmx_failInvalid(vcpu);
5634                         skip_emulated_instruction(vcpu);
5635                         return 1;
5636                 }
5637                 new_vmcs12 = kmap(page);
5638                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5639                         kunmap(page);
5640                         nested_release_page_clean(page);
5641                         nested_vmx_failValid(vcpu,
5642                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5643                         skip_emulated_instruction(vcpu);
5644                         return 1;
5645                 }
5646                 if (vmx->nested.current_vmptr != -1ull) {
5647                         kunmap(vmx->nested.current_vmcs12_page);
5648                         nested_release_page(vmx->nested.current_vmcs12_page);
5649                 }
5650
5651                 vmx->nested.current_vmptr = vmptr;
5652                 vmx->nested.current_vmcs12 = new_vmcs12;
5653                 vmx->nested.current_vmcs12_page = page;
5654         }
5655
5656         nested_vmx_succeed(vcpu);
5657         skip_emulated_instruction(vcpu);
5658         return 1;
5659 }
5660
5661 /* Emulate the VMPTRST instruction */
5662 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5663 {
5664         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5665         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5666         gva_t vmcs_gva;
5667         struct x86_exception e;
5668
5669         if (!nested_vmx_check_permission(vcpu))
5670                 return 1;
5671
5672         if (get_vmx_mem_address(vcpu, exit_qualification,
5673                         vmx_instruction_info, &vmcs_gva))
5674                 return 1;
5675         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5676         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5677                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
5678                                  sizeof(u64), &e)) {
5679                 kvm_inject_page_fault(vcpu, &e);
5680                 return 1;
5681         }
5682         nested_vmx_succeed(vcpu);
5683         skip_emulated_instruction(vcpu);
5684         return 1;
5685 }
5686
5687 /*
5688  * The exit handlers return 1 if the exit was handled fully and guest execution
5689  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5690  * to be done to userspace and return 0.
5691  */
5692 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5693         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
5694         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5695         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5696         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5697         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5698         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5699         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5700         [EXIT_REASON_CPUID]                   = handle_cpuid,
5701         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
5702         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
5703         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
5704         [EXIT_REASON_HLT]                     = handle_halt,
5705         [EXIT_REASON_INVD]                    = handle_invd,
5706         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5707         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
5708         [EXIT_REASON_VMCALL]                  = handle_vmcall,
5709         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
5710         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
5711         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
5712         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
5713         [EXIT_REASON_VMREAD]                  = handle_vmread,
5714         [EXIT_REASON_VMRESUME]                = handle_vmresume,
5715         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
5716         [EXIT_REASON_VMOFF]                   = handle_vmoff,
5717         [EXIT_REASON_VMON]                    = handle_vmon,
5718         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5719         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5720         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
5721         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
5722         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5723         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5724         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5725         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5726         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5727         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
5728         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
5729 };
5730
5731 static const int kvm_vmx_max_exit_handlers =
5732         ARRAY_SIZE(kvm_vmx_exit_handlers);
5733
5734 /*
5735  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5736  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5737  * disinterest in the current event (read or write a specific MSR) by using an
5738  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5739  */
5740 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5741         struct vmcs12 *vmcs12, u32 exit_reason)
5742 {
5743         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5744         gpa_t bitmap;
5745
5746         if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5747                 return 1;
5748
5749         /*
5750          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5751          * for the four combinations of read/write and low/high MSR numbers.
5752          * First we need to figure out which of the four to use:
5753          */
5754         bitmap = vmcs12->msr_bitmap;
5755         if (exit_reason == EXIT_REASON_MSR_WRITE)
5756                 bitmap += 2048;
5757         if (msr_index >= 0xc0000000) {
5758                 msr_index -= 0xc0000000;
5759                 bitmap += 1024;
5760         }
5761
5762         /* Then read the msr_index'th bit from this bitmap: */
5763         if (msr_index < 1024*8) {
5764                 unsigned char b;
5765                 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5766                 return 1 & (b >> (msr_index & 7));
5767         } else
5768                 return 1; /* let L1 handle the wrong parameter */
5769 }
5770
5771 /*
5772  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5773  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5774  * intercept (via guest_host_mask etc.) the current event.
5775  */
5776 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5777         struct vmcs12 *vmcs12)
5778 {
5779         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5780         int cr = exit_qualification & 15;
5781         int reg = (exit_qualification >> 8) & 15;
5782         unsigned long val = kvm_register_read(vcpu, reg);
5783
5784         switch ((exit_qualification >> 4) & 3) {
5785         case 0: /* mov to cr */
5786                 switch (cr) {
5787                 case 0:
5788                         if (vmcs12->cr0_guest_host_mask &
5789                             (val ^ vmcs12->cr0_read_shadow))
5790                                 return 1;
5791                         break;
5792                 case 3:
5793                         if ((vmcs12->cr3_target_count >= 1 &&
5794                                         vmcs12->cr3_target_value0 == val) ||
5795                                 (vmcs12->cr3_target_count >= 2 &&
5796                                         vmcs12->cr3_target_value1 == val) ||
5797                                 (vmcs12->cr3_target_count >= 3 &&
5798                                         vmcs12->cr3_target_value2 == val) ||
5799                                 (vmcs12->cr3_target_count >= 4 &&
5800                                         vmcs12->cr3_target_value3 == val))
5801                                 return 0;
5802                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5803                                 return 1;
5804                         break;
5805                 case 4:
5806                         if (vmcs12->cr4_guest_host_mask &
5807                             (vmcs12->cr4_read_shadow ^ val))
5808                                 return 1;
5809                         break;
5810                 case 8:
5811                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5812                                 return 1;
5813                         break;
5814                 }
5815                 break;
5816         case 2: /* clts */
5817                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5818                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
5819                         return 1;
5820                 break;
5821         case 1: /* mov from cr */
5822                 switch (cr) {
5823                 case 3:
5824                         if (vmcs12->cpu_based_vm_exec_control &
5825                             CPU_BASED_CR3_STORE_EXITING)
5826                                 return 1;
5827                         break;
5828                 case 8:
5829                         if (vmcs12->cpu_based_vm_exec_control &
5830                             CPU_BASED_CR8_STORE_EXITING)
5831                                 return 1;
5832                         break;
5833                 }
5834                 break;
5835         case 3: /* lmsw */
5836                 /*
5837                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5838                  * cr0. Other attempted changes are ignored, with no exit.
5839                  */
5840                 if (vmcs12->cr0_guest_host_mask & 0xe &
5841                     (val ^ vmcs12->cr0_read_shadow))
5842                         return 1;
5843                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5844                     !(vmcs12->cr0_read_shadow & 0x1) &&
5845                     (val & 0x1))
5846                         return 1;
5847                 break;
5848         }
5849         return 0;
5850 }
5851
5852 /*
5853  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5854  * should handle it ourselves in L0 (and then continue L2). Only call this
5855  * when in is_guest_mode (L2).
5856  */
5857 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5858 {
5859         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5860         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5861         struct vcpu_vmx *vmx = to_vmx(vcpu);
5862         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5863
5864         if (vmx->nested.nested_run_pending)
5865                 return 0;
5866
5867         if (unlikely(vmx->fail)) {
5868                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5869                                     vmcs_read32(VM_INSTRUCTION_ERROR));
5870                 return 1;
5871         }
5872
5873         switch (exit_reason) {
5874         case EXIT_REASON_EXCEPTION_NMI:
5875                 if (!is_exception(intr_info))
5876                         return 0;
5877                 else if (is_page_fault(intr_info))
5878                         return enable_ept;
5879                 return vmcs12->exception_bitmap &
5880                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5881         case EXIT_REASON_EXTERNAL_INTERRUPT:
5882                 return 0;
5883         case EXIT_REASON_TRIPLE_FAULT:
5884                 return 1;
5885         case EXIT_REASON_PENDING_INTERRUPT:
5886         case EXIT_REASON_NMI_WINDOW:
5887                 /*
5888                  * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5889                  * (aka Interrupt Window Exiting) only when L1 turned it on,
5890                  * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5891                  * Same for NMI Window Exiting.
5892                  */
5893                 return 1;
5894         case EXIT_REASON_TASK_SWITCH:
5895                 return 1;
5896         case EXIT_REASON_CPUID:
5897                 return 1;
5898         case EXIT_REASON_HLT:
5899                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5900         case EXIT_REASON_INVD:
5901                 return 1;
5902         case EXIT_REASON_INVLPG:
5903                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5904         case EXIT_REASON_RDPMC:
5905                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5906         case EXIT_REASON_RDTSC:
5907                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5908         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5909         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5910         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5911         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5912         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5913                 /*
5914                  * VMX instructions trap unconditionally. This allows L1 to
5915                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
5916                  */
5917                 return 1;
5918         case EXIT_REASON_CR_ACCESS:
5919                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5920         case EXIT_REASON_DR_ACCESS:
5921                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5922         case EXIT_REASON_IO_INSTRUCTION:
5923                 /* TODO: support IO bitmaps */
5924                 return 1;
5925         case EXIT_REASON_MSR_READ:
5926         case EXIT_REASON_MSR_WRITE:
5927                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5928         case EXIT_REASON_INVALID_STATE:
5929                 return 1;
5930         case EXIT_REASON_MWAIT_INSTRUCTION:
5931                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5932         case EXIT_REASON_MONITOR_INSTRUCTION:
5933                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5934         case EXIT_REASON_PAUSE_INSTRUCTION:
5935                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5936                         nested_cpu_has2(vmcs12,
5937                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5938         case EXIT_REASON_MCE_DURING_VMENTRY:
5939                 return 0;
5940         case EXIT_REASON_TPR_BELOW_THRESHOLD:
5941                 return 1;
5942         case EXIT_REASON_APIC_ACCESS:
5943                 return nested_cpu_has2(vmcs12,
5944                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5945         case EXIT_REASON_EPT_VIOLATION:
5946         case EXIT_REASON_EPT_MISCONFIG:
5947                 return 0;
5948         case EXIT_REASON_WBINVD:
5949                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5950         case EXIT_REASON_XSETBV:
5951                 return 1;
5952         default:
5953                 return 1;
5954         }
5955 }
5956
5957 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5958 {
5959         *info1 = vmcs_readl(EXIT_QUALIFICATION);
5960         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5961 }
5962
5963 /*
5964  * The guest has exited.  See if we can fix it or if we need userspace
5965  * assistance.
5966  */
5967 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5968 {
5969         struct vcpu_vmx *vmx = to_vmx(vcpu);
5970         u32 exit_reason = vmx->exit_reason;
5971         u32 vectoring_info = vmx->idt_vectoring_info;
5972
5973         /* If guest state is invalid, start emulating */
5974         if (vmx->emulation_required && emulate_invalid_guest_state)
5975                 return handle_invalid_guest_state(vcpu);
5976
5977         /*
5978          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5979          * we did not inject a still-pending event to L1 now because of
5980          * nested_run_pending, we need to re-enable this bit.
5981          */
5982         if (vmx->nested.nested_run_pending)
5983                 kvm_make_request(KVM_REQ_EVENT, vcpu);
5984
5985         if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5986             exit_reason == EXIT_REASON_VMRESUME))
5987                 vmx->nested.nested_run_pending = 1;
5988         else
5989                 vmx->nested.nested_run_pending = 0;
5990
5991         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5992                 nested_vmx_vmexit(vcpu);
5993                 return 1;
5994         }
5995
5996         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5997                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5998                 vcpu->run->fail_entry.hardware_entry_failure_reason
5999                         = exit_reason;
6000                 return 0;
6001         }
6002
6003         if (unlikely(vmx->fail)) {
6004                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6005                 vcpu->run->fail_entry.hardware_entry_failure_reason
6006                         = vmcs_read32(VM_INSTRUCTION_ERROR);
6007                 return 0;
6008         }
6009
6010         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
6011                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
6012                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
6013                         exit_reason != EXIT_REASON_TASK_SWITCH))
6014                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
6015                        "(0x%x) and exit reason is 0x%x\n",
6016                        __func__, vectoring_info, exit_reason);
6017
6018         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6019             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6020                                         get_vmcs12(vcpu), vcpu)))) {
6021                 if (vmx_interrupt_allowed(vcpu)) {
6022                         vmx->soft_vnmi_blocked = 0;
6023                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
6024                            vcpu->arch.nmi_pending) {
6025                         /*
6026                          * This CPU don't support us in finding the end of an
6027                          * NMI-blocked window if the guest runs with IRQs
6028                          * disabled. So we pull the trigger after 1 s of
6029                          * futile waiting, but inform the user about this.
6030                          */
6031                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6032                                "state on VCPU %d after 1 s timeout\n",
6033                                __func__, vcpu->vcpu_id);
6034                         vmx->soft_vnmi_blocked = 0;
6035                 }
6036         }
6037
6038         if (exit_reason < kvm_vmx_max_exit_handlers
6039             && kvm_vmx_exit_handlers[exit_reason])
6040                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6041         else {
6042                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6043                 vcpu->run->hw.hardware_exit_reason = exit_reason;
6044         }
6045         return 0;
6046 }
6047
6048 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6049 {
6050         if (irr == -1 || tpr < irr) {
6051                 vmcs_write32(TPR_THRESHOLD, 0);
6052                 return;
6053         }
6054
6055         vmcs_write32(TPR_THRESHOLD, irr);
6056 }
6057
6058 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
6059 {
6060         u32 exit_intr_info;
6061
6062         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6063               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6064                 return;
6065
6066         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6067         exit_intr_info = vmx->exit_intr_info;
6068
6069         /* Handle machine checks before interrupts are enabled */
6070         if (is_machine_check(exit_intr_info))
6071                 kvm_machine_check();
6072
6073         /* We need to handle NMIs before interrupts are enabled */
6074         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
6075             (exit_intr_info & INTR_INFO_VALID_MASK)) {
6076                 kvm_before_handle_nmi(&vmx->vcpu);
6077                 asm("int $2");
6078                 kvm_after_handle_nmi(&vmx->vcpu);
6079         }
6080 }
6081
6082 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6083 {
6084         u32 exit_intr_info;
6085         bool unblock_nmi;
6086         u8 vector;
6087         bool idtv_info_valid;
6088
6089         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6090
6091         if (cpu_has_virtual_nmis()) {
6092                 if (vmx->nmi_known_unmasked)
6093                         return;
6094                 /*
6095                  * Can't use vmx->exit_intr_info since we're not sure what
6096                  * the exit reason is.
6097                  */
6098                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6099                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6100                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6101                 /*
6102                  * SDM 3: 27.7.1.2 (September 2008)
6103                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
6104                  * a guest IRET fault.
6105                  * SDM 3: 23.2.2 (September 2008)
6106                  * Bit 12 is undefined in any of the following cases:
6107                  *  If the VM exit sets the valid bit in the IDT-vectoring
6108                  *   information field.
6109                  *  If the VM exit is due to a double fault.
6110                  */
6111                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6112                     vector != DF_VECTOR && !idtv_info_valid)
6113                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6114                                       GUEST_INTR_STATE_NMI);
6115                 else
6116                         vmx->nmi_known_unmasked =
6117                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6118                                   & GUEST_INTR_STATE_NMI);
6119         } else if (unlikely(vmx->soft_vnmi_blocked))
6120                 vmx->vnmi_blocked_time +=
6121                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
6122 }
6123
6124 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
6125                                       u32 idt_vectoring_info,
6126                                       int instr_len_field,
6127                                       int error_code_field)
6128 {
6129         u8 vector;
6130         int type;
6131         bool idtv_info_valid;
6132
6133         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6134
6135         vmx->vcpu.arch.nmi_injected = false;
6136         kvm_clear_exception_queue(&vmx->vcpu);
6137         kvm_clear_interrupt_queue(&vmx->vcpu);
6138
6139         if (!idtv_info_valid)
6140                 return;
6141
6142         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6143
6144         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6145         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6146
6147         switch (type) {
6148         case INTR_TYPE_NMI_INTR:
6149                 vmx->vcpu.arch.nmi_injected = true;
6150                 /*
6151                  * SDM 3: 27.7.1.2 (September 2008)
6152                  * Clear bit "block by NMI" before VM entry if a NMI
6153                  * delivery faulted.
6154                  */
6155                 vmx_set_nmi_mask(&vmx->vcpu, false);
6156                 break;
6157         case INTR_TYPE_SOFT_EXCEPTION:
6158                 vmx->vcpu.arch.event_exit_inst_len =
6159                         vmcs_read32(instr_len_field);
6160                 /* fall through */
6161         case INTR_TYPE_HARD_EXCEPTION:
6162                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6163                         u32 err = vmcs_read32(error_code_field);
6164                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
6165                 } else
6166                         kvm_queue_exception(&vmx->vcpu, vector);
6167                 break;
6168         case INTR_TYPE_SOFT_INTR:
6169                 vmx->vcpu.arch.event_exit_inst_len =
6170                         vmcs_read32(instr_len_field);
6171                 /* fall through */
6172         case INTR_TYPE_EXT_INTR:
6173                 kvm_queue_interrupt(&vmx->vcpu, vector,
6174                         type == INTR_TYPE_SOFT_INTR);
6175                 break;
6176         default:
6177                 break;
6178         }
6179 }
6180
6181 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6182 {
6183         if (is_guest_mode(&vmx->vcpu))
6184                 return;
6185         __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6186                                   VM_EXIT_INSTRUCTION_LEN,
6187                                   IDT_VECTORING_ERROR_CODE);
6188 }
6189
6190 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6191 {
6192         if (is_guest_mode(vcpu))
6193                 return;
6194         __vmx_complete_interrupts(to_vmx(vcpu),
6195                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6196                                   VM_ENTRY_INSTRUCTION_LEN,
6197                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6198
6199         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6200 }
6201
6202 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6203 {
6204         int i, nr_msrs;
6205         struct perf_guest_switch_msr *msrs;
6206
6207         msrs = perf_guest_get_msrs(&nr_msrs);
6208
6209         if (!msrs)
6210                 return;
6211
6212         for (i = 0; i < nr_msrs; i++)
6213                 if (msrs[i].host == msrs[i].guest)
6214                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6215                 else
6216                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6217                                         msrs[i].host);
6218 }
6219
6220 #ifdef CONFIG_X86_64
6221 #define R "r"
6222 #define Q "q"
6223 #else
6224 #define R "e"
6225 #define Q "l"
6226 #endif
6227
6228 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6229 {
6230         struct vcpu_vmx *vmx = to_vmx(vcpu);
6231         unsigned long debugctlmsr;
6232
6233         if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6234                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6235                 if (vmcs12->idt_vectoring_info_field &
6236                                 VECTORING_INFO_VALID_MASK) {
6237                         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6238                                 vmcs12->idt_vectoring_info_field);
6239                         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6240                                 vmcs12->vm_exit_instruction_len);
6241                         if (vmcs12->idt_vectoring_info_field &
6242                                         VECTORING_INFO_DELIVER_CODE_MASK)
6243                                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6244                                         vmcs12->idt_vectoring_error_code);
6245                 }
6246         }
6247
6248         /* Record the guest's net vcpu time for enforced NMI injections. */
6249         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6250                 vmx->entry_time = ktime_get();
6251
6252         /* Don't enter VMX if guest state is invalid, let the exit handler
6253            start emulation until we arrive back to a valid state */
6254         if (vmx->emulation_required && emulate_invalid_guest_state)
6255                 return;
6256
6257         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6258                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6259         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6260                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6261
6262         /* When single-stepping over STI and MOV SS, we must clear the
6263          * corresponding interruptibility bits in the guest state. Otherwise
6264          * vmentry fails as it then expects bit 14 (BS) in pending debug
6265          * exceptions being set, but that's not correct for the guest debugging
6266          * case. */
6267         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6268                 vmx_set_interrupt_shadow(vcpu, 0);
6269
6270         atomic_switch_perf_msrs(vmx);
6271         debugctlmsr = get_debugctlmsr();
6272
6273         vmx->__launched = vmx->loaded_vmcs->launched;
6274         asm(
6275                 /* Store host registers */
6276                 "push %%"R"dx; push %%"R"bp;"
6277                 "push %%"R"cx \n\t" /* placeholder for guest rcx */
6278                 "push %%"R"cx \n\t"
6279                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
6280                 "je 1f \n\t"
6281                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
6282                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
6283                 "1: \n\t"
6284                 /* Reload cr2 if changed */
6285                 "mov %c[cr2](%0), %%"R"ax \n\t"
6286                 "mov %%cr2, %%"R"dx \n\t"
6287                 "cmp %%"R"ax, %%"R"dx \n\t"
6288                 "je 2f \n\t"
6289                 "mov %%"R"ax, %%cr2 \n\t"
6290                 "2: \n\t"
6291                 /* Check if vmlaunch of vmresume is needed */
6292                 "cmpl $0, %c[launched](%0) \n\t"
6293                 /* Load guest registers.  Don't clobber flags. */
6294                 "mov %c[rax](%0), %%"R"ax \n\t"
6295                 "mov %c[rbx](%0), %%"R"bx \n\t"
6296                 "mov %c[rdx](%0), %%"R"dx \n\t"
6297                 "mov %c[rsi](%0), %%"R"si \n\t"
6298                 "mov %c[rdi](%0), %%"R"di \n\t"
6299                 "mov %c[rbp](%0), %%"R"bp \n\t"
6300 #ifdef CONFIG_X86_64
6301                 "mov %c[r8](%0),  %%r8  \n\t"
6302                 "mov %c[r9](%0),  %%r9  \n\t"
6303                 "mov %c[r10](%0), %%r10 \n\t"
6304                 "mov %c[r11](%0), %%r11 \n\t"
6305                 "mov %c[r12](%0), %%r12 \n\t"
6306                 "mov %c[r13](%0), %%r13 \n\t"
6307                 "mov %c[r14](%0), %%r14 \n\t"
6308                 "mov %c[r15](%0), %%r15 \n\t"
6309 #endif
6310                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
6311
6312                 /* Enter guest mode */
6313                 "jne .Llaunched \n\t"
6314                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
6315                 "jmp .Lkvm_vmx_return \n\t"
6316                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
6317                 ".Lkvm_vmx_return: "
6318                 /* Save guest registers, load host registers, keep flags */
6319                 "mov %0, %c[wordsize](%%"R"sp) \n\t"
6320                 "pop %0 \n\t"
6321                 "mov %%"R"ax, %c[rax](%0) \n\t"
6322                 "mov %%"R&qu