KVM: nVMX: Implement VMXON and VMXOFF
[linux-3.10.git] / arch / x86 / kvm / vmx.c
1 /*
2  * Kernel-based Virtual Machine driver for Linux
3  *
4  * This module enables machines with Intel VT-x extensions to run virtual
5  * machines without emulation or binary translation.
6  *
7  * Copyright (C) 2006 Qumranet, Inc.
8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
9  *
10  * Authors:
11  *   Avi Kivity   <avi@qumranet.com>
12  *   Yaniv Kamay  <yaniv@qumranet.com>
13  *
14  * This work is licensed under the terms of the GNU GPL, version 2.  See
15  * the COPYING file in the top-level directory.
16  *
17  */
18
19 #include "irq.h"
20 #include "mmu.h"
21
22 #include <linux/kvm_host.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/mm.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/moduleparam.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31 #include <linux/tboot.h>
32 #include "kvm_cache_regs.h"
33 #include "x86.h"
34
35 #include <asm/io.h>
36 #include <asm/desc.h>
37 #include <asm/vmx.h>
38 #include <asm/virtext.h>
39 #include <asm/mce.h>
40 #include <asm/i387.h>
41 #include <asm/xcr.h>
42
43 #include "trace.h"
44
45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
46 #define __ex_clear(x, reg) \
47         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
48
49 MODULE_AUTHOR("Qumranet");
50 MODULE_LICENSE("GPL");
51
52 static int __read_mostly bypass_guest_pf = 1;
53 module_param(bypass_guest_pf, bool, S_IRUGO);
54
55 static int __read_mostly enable_vpid = 1;
56 module_param_named(vpid, enable_vpid, bool, 0444);
57
58 static int __read_mostly flexpriority_enabled = 1;
59 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
60
61 static int __read_mostly enable_ept = 1;
62 module_param_named(ept, enable_ept, bool, S_IRUGO);
63
64 static int __read_mostly enable_unrestricted_guest = 1;
65 module_param_named(unrestricted_guest,
66                         enable_unrestricted_guest, bool, S_IRUGO);
67
68 static int __read_mostly emulate_invalid_guest_state = 0;
69 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
70
71 static int __read_mostly vmm_exclusive = 1;
72 module_param(vmm_exclusive, bool, S_IRUGO);
73
74 static int __read_mostly yield_on_hlt = 1;
75 module_param(yield_on_hlt, bool, S_IRUGO);
76
77 /*
78  * If nested=1, nested virtualization is supported, i.e., guests may use
79  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
80  * use VMX instructions.
81  */
82 static int __read_mostly nested = 0;
83 module_param(nested, bool, S_IRUGO);
84
85 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
86         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
87 #define KVM_GUEST_CR0_MASK                                              \
88         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
89 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
90         (X86_CR0_WP | X86_CR0_NE)
91 #define KVM_VM_CR0_ALWAYS_ON                                            \
92         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
93 #define KVM_CR4_GUEST_OWNED_BITS                                      \
94         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
95          | X86_CR4_OSXMMEXCPT)
96
97 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
98 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
99
100 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
101
102 /*
103  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
104  * ple_gap:    upper bound on the amount of time between two successive
105  *             executions of PAUSE in a loop. Also indicate if ple enabled.
106  *             According to test, this time is usually smaller than 128 cycles.
107  * ple_window: upper bound on the amount of time a guest is allowed to execute
108  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
109  *             less than 2^12 cycles
110  * Time is measured based on a counter that runs at the same rate as the TSC,
111  * refer SDM volume 3b section 21.6.13 & 22.1.3.
112  */
113 #define KVM_VMX_DEFAULT_PLE_GAP    128
114 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
115 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
116 module_param(ple_gap, int, S_IRUGO);
117
118 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
119 module_param(ple_window, int, S_IRUGO);
120
121 #define NR_AUTOLOAD_MSRS 1
122
123 struct vmcs {
124         u32 revision_id;
125         u32 abort;
126         char data[0];
127 };
128
129 /*
130  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
131  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
132  * loaded on this CPU (so we can clear them if the CPU goes down).
133  */
134 struct loaded_vmcs {
135         struct vmcs *vmcs;
136         int cpu;
137         int launched;
138         struct list_head loaded_vmcss_on_cpu_link;
139 };
140
141 struct shared_msr_entry {
142         unsigned index;
143         u64 data;
144         u64 mask;
145 };
146
147 /*
148  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
149  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
150  */
151 struct nested_vmx {
152         /* Has the level1 guest done vmxon? */
153         bool vmxon;
154 };
155
156 struct vcpu_vmx {
157         struct kvm_vcpu       vcpu;
158         unsigned long         host_rsp;
159         u8                    fail;
160         u8                    cpl;
161         bool                  nmi_known_unmasked;
162         u32                   exit_intr_info;
163         u32                   idt_vectoring_info;
164         ulong                 rflags;
165         struct shared_msr_entry *guest_msrs;
166         int                   nmsrs;
167         int                   save_nmsrs;
168 #ifdef CONFIG_X86_64
169         u64                   msr_host_kernel_gs_base;
170         u64                   msr_guest_kernel_gs_base;
171 #endif
172         /*
173          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
174          * non-nested (L1) guest, it always points to vmcs01. For a nested
175          * guest (L2), it points to a different VMCS.
176          */
177         struct loaded_vmcs    vmcs01;
178         struct loaded_vmcs   *loaded_vmcs;
179         bool                  __launched; /* temporary, used in vmx_vcpu_run */
180         struct msr_autoload {
181                 unsigned nr;
182                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
183                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
184         } msr_autoload;
185         struct {
186                 int           loaded;
187                 u16           fs_sel, gs_sel, ldt_sel;
188                 int           gs_ldt_reload_needed;
189                 int           fs_reload_needed;
190         } host_state;
191         struct {
192                 int vm86_active;
193                 ulong save_rflags;
194                 struct kvm_save_segment {
195                         u16 selector;
196                         unsigned long base;
197                         u32 limit;
198                         u32 ar;
199                 } tr, es, ds, fs, gs;
200         } rmode;
201         struct {
202                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
203                 struct kvm_save_segment seg[8];
204         } segment_cache;
205         int vpid;
206         bool emulation_required;
207
208         /* Support for vnmi-less CPUs */
209         int soft_vnmi_blocked;
210         ktime_t entry_time;
211         s64 vnmi_blocked_time;
212         u32 exit_reason;
213
214         bool rdtscp_enabled;
215
216         /* Support for a guest hypervisor (nested VMX) */
217         struct nested_vmx nested;
218 };
219
220 enum segment_cache_field {
221         SEG_FIELD_SEL = 0,
222         SEG_FIELD_BASE = 1,
223         SEG_FIELD_LIMIT = 2,
224         SEG_FIELD_AR = 3,
225
226         SEG_FIELD_NR = 4
227 };
228
229 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
230 {
231         return container_of(vcpu, struct vcpu_vmx, vcpu);
232 }
233
234 static u64 construct_eptp(unsigned long root_hpa);
235 static void kvm_cpu_vmxon(u64 addr);
236 static void kvm_cpu_vmxoff(void);
237 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
238 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
239
240 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
241 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
242 /*
243  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
244  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
245  */
246 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
247 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
248
249 static unsigned long *vmx_io_bitmap_a;
250 static unsigned long *vmx_io_bitmap_b;
251 static unsigned long *vmx_msr_bitmap_legacy;
252 static unsigned long *vmx_msr_bitmap_longmode;
253
254 static bool cpu_has_load_ia32_efer;
255
256 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
257 static DEFINE_SPINLOCK(vmx_vpid_lock);
258
259 static struct vmcs_config {
260         int size;
261         int order;
262         u32 revision_id;
263         u32 pin_based_exec_ctrl;
264         u32 cpu_based_exec_ctrl;
265         u32 cpu_based_2nd_exec_ctrl;
266         u32 vmexit_ctrl;
267         u32 vmentry_ctrl;
268 } vmcs_config;
269
270 static struct vmx_capability {
271         u32 ept;
272         u32 vpid;
273 } vmx_capability;
274
275 #define VMX_SEGMENT_FIELD(seg)                                  \
276         [VCPU_SREG_##seg] = {                                   \
277                 .selector = GUEST_##seg##_SELECTOR,             \
278                 .base = GUEST_##seg##_BASE,                     \
279                 .limit = GUEST_##seg##_LIMIT,                   \
280                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
281         }
282
283 static struct kvm_vmx_segment_field {
284         unsigned selector;
285         unsigned base;
286         unsigned limit;
287         unsigned ar_bytes;
288 } kvm_vmx_segment_fields[] = {
289         VMX_SEGMENT_FIELD(CS),
290         VMX_SEGMENT_FIELD(DS),
291         VMX_SEGMENT_FIELD(ES),
292         VMX_SEGMENT_FIELD(FS),
293         VMX_SEGMENT_FIELD(GS),
294         VMX_SEGMENT_FIELD(SS),
295         VMX_SEGMENT_FIELD(TR),
296         VMX_SEGMENT_FIELD(LDTR),
297 };
298
299 static u64 host_efer;
300
301 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
302
303 /*
304  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
305  * away by decrementing the array size.
306  */
307 static const u32 vmx_msr_index[] = {
308 #ifdef CONFIG_X86_64
309         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
310 #endif
311         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
312 };
313 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
314
315 static inline bool is_page_fault(u32 intr_info)
316 {
317         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
318                              INTR_INFO_VALID_MASK)) ==
319                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
320 }
321
322 static inline bool is_no_device(u32 intr_info)
323 {
324         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
325                              INTR_INFO_VALID_MASK)) ==
326                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
327 }
328
329 static inline bool is_invalid_opcode(u32 intr_info)
330 {
331         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
332                              INTR_INFO_VALID_MASK)) ==
333                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
334 }
335
336 static inline bool is_external_interrupt(u32 intr_info)
337 {
338         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
339                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
340 }
341
342 static inline bool is_machine_check(u32 intr_info)
343 {
344         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
345                              INTR_INFO_VALID_MASK)) ==
346                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
347 }
348
349 static inline bool cpu_has_vmx_msr_bitmap(void)
350 {
351         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
352 }
353
354 static inline bool cpu_has_vmx_tpr_shadow(void)
355 {
356         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
357 }
358
359 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
360 {
361         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
362 }
363
364 static inline bool cpu_has_secondary_exec_ctrls(void)
365 {
366         return vmcs_config.cpu_based_exec_ctrl &
367                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
368 }
369
370 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
371 {
372         return vmcs_config.cpu_based_2nd_exec_ctrl &
373                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
374 }
375
376 static inline bool cpu_has_vmx_flexpriority(void)
377 {
378         return cpu_has_vmx_tpr_shadow() &&
379                 cpu_has_vmx_virtualize_apic_accesses();
380 }
381
382 static inline bool cpu_has_vmx_ept_execute_only(void)
383 {
384         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
385 }
386
387 static inline bool cpu_has_vmx_eptp_uncacheable(void)
388 {
389         return vmx_capability.ept & VMX_EPTP_UC_BIT;
390 }
391
392 static inline bool cpu_has_vmx_eptp_writeback(void)
393 {
394         return vmx_capability.ept & VMX_EPTP_WB_BIT;
395 }
396
397 static inline bool cpu_has_vmx_ept_2m_page(void)
398 {
399         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
400 }
401
402 static inline bool cpu_has_vmx_ept_1g_page(void)
403 {
404         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
405 }
406
407 static inline bool cpu_has_vmx_ept_4levels(void)
408 {
409         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
410 }
411
412 static inline bool cpu_has_vmx_invept_individual_addr(void)
413 {
414         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
415 }
416
417 static inline bool cpu_has_vmx_invept_context(void)
418 {
419         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
420 }
421
422 static inline bool cpu_has_vmx_invept_global(void)
423 {
424         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
425 }
426
427 static inline bool cpu_has_vmx_invvpid_single(void)
428 {
429         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
430 }
431
432 static inline bool cpu_has_vmx_invvpid_global(void)
433 {
434         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
435 }
436
437 static inline bool cpu_has_vmx_ept(void)
438 {
439         return vmcs_config.cpu_based_2nd_exec_ctrl &
440                 SECONDARY_EXEC_ENABLE_EPT;
441 }
442
443 static inline bool cpu_has_vmx_unrestricted_guest(void)
444 {
445         return vmcs_config.cpu_based_2nd_exec_ctrl &
446                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
447 }
448
449 static inline bool cpu_has_vmx_ple(void)
450 {
451         return vmcs_config.cpu_based_2nd_exec_ctrl &
452                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
453 }
454
455 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
456 {
457         return flexpriority_enabled && irqchip_in_kernel(kvm);
458 }
459
460 static inline bool cpu_has_vmx_vpid(void)
461 {
462         return vmcs_config.cpu_based_2nd_exec_ctrl &
463                 SECONDARY_EXEC_ENABLE_VPID;
464 }
465
466 static inline bool cpu_has_vmx_rdtscp(void)
467 {
468         return vmcs_config.cpu_based_2nd_exec_ctrl &
469                 SECONDARY_EXEC_RDTSCP;
470 }
471
472 static inline bool cpu_has_virtual_nmis(void)
473 {
474         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
475 }
476
477 static inline bool cpu_has_vmx_wbinvd_exit(void)
478 {
479         return vmcs_config.cpu_based_2nd_exec_ctrl &
480                 SECONDARY_EXEC_WBINVD_EXITING;
481 }
482
483 static inline bool report_flexpriority(void)
484 {
485         return flexpriority_enabled;
486 }
487
488 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
489 {
490         int i;
491
492         for (i = 0; i < vmx->nmsrs; ++i)
493                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
494                         return i;
495         return -1;
496 }
497
498 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
499 {
500     struct {
501         u64 vpid : 16;
502         u64 rsvd : 48;
503         u64 gva;
504     } operand = { vpid, 0, gva };
505
506     asm volatile (__ex(ASM_VMX_INVVPID)
507                   /* CF==1 or ZF==1 --> rc = -1 */
508                   "; ja 1f ; ud2 ; 1:"
509                   : : "a"(&operand), "c"(ext) : "cc", "memory");
510 }
511
512 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
513 {
514         struct {
515                 u64 eptp, gpa;
516         } operand = {eptp, gpa};
517
518         asm volatile (__ex(ASM_VMX_INVEPT)
519                         /* CF==1 or ZF==1 --> rc = -1 */
520                         "; ja 1f ; ud2 ; 1:\n"
521                         : : "a" (&operand), "c" (ext) : "cc", "memory");
522 }
523
524 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
525 {
526         int i;
527
528         i = __find_msr_index(vmx, msr);
529         if (i >= 0)
530                 return &vmx->guest_msrs[i];
531         return NULL;
532 }
533
534 static void vmcs_clear(struct vmcs *vmcs)
535 {
536         u64 phys_addr = __pa(vmcs);
537         u8 error;
538
539         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
540                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
541                       : "cc", "memory");
542         if (error)
543                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
544                        vmcs, phys_addr);
545 }
546
547 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
548 {
549         vmcs_clear(loaded_vmcs->vmcs);
550         loaded_vmcs->cpu = -1;
551         loaded_vmcs->launched = 0;
552 }
553
554 static void vmcs_load(struct vmcs *vmcs)
555 {
556         u64 phys_addr = __pa(vmcs);
557         u8 error;
558
559         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
560                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
561                         : "cc", "memory");
562         if (error)
563                 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
564                        vmcs, phys_addr);
565 }
566
567 static void __loaded_vmcs_clear(void *arg)
568 {
569         struct loaded_vmcs *loaded_vmcs = arg;
570         int cpu = raw_smp_processor_id();
571
572         if (loaded_vmcs->cpu != cpu)
573                 return; /* vcpu migration can race with cpu offline */
574         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
575                 per_cpu(current_vmcs, cpu) = NULL;
576         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
577         loaded_vmcs_init(loaded_vmcs);
578 }
579
580 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
581 {
582         if (loaded_vmcs->cpu != -1)
583                 smp_call_function_single(
584                         loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
585 }
586
587 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
588 {
589         if (vmx->vpid == 0)
590                 return;
591
592         if (cpu_has_vmx_invvpid_single())
593                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
594 }
595
596 static inline void vpid_sync_vcpu_global(void)
597 {
598         if (cpu_has_vmx_invvpid_global())
599                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
600 }
601
602 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
603 {
604         if (cpu_has_vmx_invvpid_single())
605                 vpid_sync_vcpu_single(vmx);
606         else
607                 vpid_sync_vcpu_global();
608 }
609
610 static inline void ept_sync_global(void)
611 {
612         if (cpu_has_vmx_invept_global())
613                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
614 }
615
616 static inline void ept_sync_context(u64 eptp)
617 {
618         if (enable_ept) {
619                 if (cpu_has_vmx_invept_context())
620                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
621                 else
622                         ept_sync_global();
623         }
624 }
625
626 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
627 {
628         if (enable_ept) {
629                 if (cpu_has_vmx_invept_individual_addr())
630                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
631                                         eptp, gpa);
632                 else
633                         ept_sync_context(eptp);
634         }
635 }
636
637 static __always_inline unsigned long vmcs_readl(unsigned long field)
638 {
639         unsigned long value;
640
641         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
642                       : "=a"(value) : "d"(field) : "cc");
643         return value;
644 }
645
646 static __always_inline u16 vmcs_read16(unsigned long field)
647 {
648         return vmcs_readl(field);
649 }
650
651 static __always_inline u32 vmcs_read32(unsigned long field)
652 {
653         return vmcs_readl(field);
654 }
655
656 static __always_inline u64 vmcs_read64(unsigned long field)
657 {
658 #ifdef CONFIG_X86_64
659         return vmcs_readl(field);
660 #else
661         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
662 #endif
663 }
664
665 static noinline void vmwrite_error(unsigned long field, unsigned long value)
666 {
667         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
668                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
669         dump_stack();
670 }
671
672 static void vmcs_writel(unsigned long field, unsigned long value)
673 {
674         u8 error;
675
676         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
677                        : "=q"(error) : "a"(value), "d"(field) : "cc");
678         if (unlikely(error))
679                 vmwrite_error(field, value);
680 }
681
682 static void vmcs_write16(unsigned long field, u16 value)
683 {
684         vmcs_writel(field, value);
685 }
686
687 static void vmcs_write32(unsigned long field, u32 value)
688 {
689         vmcs_writel(field, value);
690 }
691
692 static void vmcs_write64(unsigned long field, u64 value)
693 {
694         vmcs_writel(field, value);
695 #ifndef CONFIG_X86_64
696         asm volatile ("");
697         vmcs_writel(field+1, value >> 32);
698 #endif
699 }
700
701 static void vmcs_clear_bits(unsigned long field, u32 mask)
702 {
703         vmcs_writel(field, vmcs_readl(field) & ~mask);
704 }
705
706 static void vmcs_set_bits(unsigned long field, u32 mask)
707 {
708         vmcs_writel(field, vmcs_readl(field) | mask);
709 }
710
711 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
712 {
713         vmx->segment_cache.bitmask = 0;
714 }
715
716 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
717                                        unsigned field)
718 {
719         bool ret;
720         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
721
722         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
723                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
724                 vmx->segment_cache.bitmask = 0;
725         }
726         ret = vmx->segment_cache.bitmask & mask;
727         vmx->segment_cache.bitmask |= mask;
728         return ret;
729 }
730
731 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
732 {
733         u16 *p = &vmx->segment_cache.seg[seg].selector;
734
735         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
736                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
737         return *p;
738 }
739
740 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
741 {
742         ulong *p = &vmx->segment_cache.seg[seg].base;
743
744         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
745                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
746         return *p;
747 }
748
749 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
750 {
751         u32 *p = &vmx->segment_cache.seg[seg].limit;
752
753         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
754                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
755         return *p;
756 }
757
758 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
759 {
760         u32 *p = &vmx->segment_cache.seg[seg].ar;
761
762         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
763                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
764         return *p;
765 }
766
767 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
768 {
769         u32 eb;
770
771         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
772              (1u << NM_VECTOR) | (1u << DB_VECTOR);
773         if ((vcpu->guest_debug &
774              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
775             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
776                 eb |= 1u << BP_VECTOR;
777         if (to_vmx(vcpu)->rmode.vm86_active)
778                 eb = ~0;
779         if (enable_ept)
780                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
781         if (vcpu->fpu_active)
782                 eb &= ~(1u << NM_VECTOR);
783         vmcs_write32(EXCEPTION_BITMAP, eb);
784 }
785
786 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
787 {
788         unsigned i;
789         struct msr_autoload *m = &vmx->msr_autoload;
790
791         if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
792                 vmcs_clear_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
793                 vmcs_clear_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
794                 return;
795         }
796
797         for (i = 0; i < m->nr; ++i)
798                 if (m->guest[i].index == msr)
799                         break;
800
801         if (i == m->nr)
802                 return;
803         --m->nr;
804         m->guest[i] = m->guest[m->nr];
805         m->host[i] = m->host[m->nr];
806         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
807         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
808 }
809
810 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
811                                   u64 guest_val, u64 host_val)
812 {
813         unsigned i;
814         struct msr_autoload *m = &vmx->msr_autoload;
815
816         if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
817                 vmcs_write64(GUEST_IA32_EFER, guest_val);
818                 vmcs_write64(HOST_IA32_EFER, host_val);
819                 vmcs_set_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
820                 vmcs_set_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
821                 return;
822         }
823
824         for (i = 0; i < m->nr; ++i)
825                 if (m->guest[i].index == msr)
826                         break;
827
828         if (i == m->nr) {
829                 ++m->nr;
830                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
831                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
832         }
833
834         m->guest[i].index = msr;
835         m->guest[i].value = guest_val;
836         m->host[i].index = msr;
837         m->host[i].value = host_val;
838 }
839
840 static void reload_tss(void)
841 {
842         /*
843          * VT restores TR but not its size.  Useless.
844          */
845         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
846         struct desc_struct *descs;
847
848         descs = (void *)gdt->address;
849         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
850         load_TR_desc();
851 }
852
853 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
854 {
855         u64 guest_efer;
856         u64 ignore_bits;
857
858         guest_efer = vmx->vcpu.arch.efer;
859
860         /*
861          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
862          * outside long mode
863          */
864         ignore_bits = EFER_NX | EFER_SCE;
865 #ifdef CONFIG_X86_64
866         ignore_bits |= EFER_LMA | EFER_LME;
867         /* SCE is meaningful only in long mode on Intel */
868         if (guest_efer & EFER_LMA)
869                 ignore_bits &= ~(u64)EFER_SCE;
870 #endif
871         guest_efer &= ~ignore_bits;
872         guest_efer |= host_efer & ignore_bits;
873         vmx->guest_msrs[efer_offset].data = guest_efer;
874         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
875
876         clear_atomic_switch_msr(vmx, MSR_EFER);
877         /* On ept, can't emulate nx, and must switch nx atomically */
878         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
879                 guest_efer = vmx->vcpu.arch.efer;
880                 if (!(guest_efer & EFER_LMA))
881                         guest_efer &= ~EFER_LME;
882                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
883                 return false;
884         }
885
886         return true;
887 }
888
889 static unsigned long segment_base(u16 selector)
890 {
891         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
892         struct desc_struct *d;
893         unsigned long table_base;
894         unsigned long v;
895
896         if (!(selector & ~3))
897                 return 0;
898
899         table_base = gdt->address;
900
901         if (selector & 4) {           /* from ldt */
902                 u16 ldt_selector = kvm_read_ldt();
903
904                 if (!(ldt_selector & ~3))
905                         return 0;
906
907                 table_base = segment_base(ldt_selector);
908         }
909         d = (struct desc_struct *)(table_base + (selector & ~7));
910         v = get_desc_base(d);
911 #ifdef CONFIG_X86_64
912        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
913                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
914 #endif
915         return v;
916 }
917
918 static inline unsigned long kvm_read_tr_base(void)
919 {
920         u16 tr;
921         asm("str %0" : "=g"(tr));
922         return segment_base(tr);
923 }
924
925 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
926 {
927         struct vcpu_vmx *vmx = to_vmx(vcpu);
928         int i;
929
930         if (vmx->host_state.loaded)
931                 return;
932
933         vmx->host_state.loaded = 1;
934         /*
935          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
936          * allow segment selectors with cpl > 0 or ti == 1.
937          */
938         vmx->host_state.ldt_sel = kvm_read_ldt();
939         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
940         savesegment(fs, vmx->host_state.fs_sel);
941         if (!(vmx->host_state.fs_sel & 7)) {
942                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
943                 vmx->host_state.fs_reload_needed = 0;
944         } else {
945                 vmcs_write16(HOST_FS_SELECTOR, 0);
946                 vmx->host_state.fs_reload_needed = 1;
947         }
948         savesegment(gs, vmx->host_state.gs_sel);
949         if (!(vmx->host_state.gs_sel & 7))
950                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
951         else {
952                 vmcs_write16(HOST_GS_SELECTOR, 0);
953                 vmx->host_state.gs_ldt_reload_needed = 1;
954         }
955
956 #ifdef CONFIG_X86_64
957         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
958         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
959 #else
960         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
961         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
962 #endif
963
964 #ifdef CONFIG_X86_64
965         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
966         if (is_long_mode(&vmx->vcpu))
967                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
968 #endif
969         for (i = 0; i < vmx->save_nmsrs; ++i)
970                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
971                                    vmx->guest_msrs[i].data,
972                                    vmx->guest_msrs[i].mask);
973 }
974
975 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
976 {
977         if (!vmx->host_state.loaded)
978                 return;
979
980         ++vmx->vcpu.stat.host_state_reload;
981         vmx->host_state.loaded = 0;
982 #ifdef CONFIG_X86_64
983         if (is_long_mode(&vmx->vcpu))
984                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
985 #endif
986         if (vmx->host_state.gs_ldt_reload_needed) {
987                 kvm_load_ldt(vmx->host_state.ldt_sel);
988 #ifdef CONFIG_X86_64
989                 load_gs_index(vmx->host_state.gs_sel);
990 #else
991                 loadsegment(gs, vmx->host_state.gs_sel);
992 #endif
993         }
994         if (vmx->host_state.fs_reload_needed)
995                 loadsegment(fs, vmx->host_state.fs_sel);
996         reload_tss();
997 #ifdef CONFIG_X86_64
998         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
999 #endif
1000         if (current_thread_info()->status & TS_USEDFPU)
1001                 clts();
1002         load_gdt(&__get_cpu_var(host_gdt));
1003 }
1004
1005 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1006 {
1007         preempt_disable();
1008         __vmx_load_host_state(vmx);
1009         preempt_enable();
1010 }
1011
1012 /*
1013  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1014  * vcpu mutex is already taken.
1015  */
1016 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1017 {
1018         struct vcpu_vmx *vmx = to_vmx(vcpu);
1019         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1020
1021         if (!vmm_exclusive)
1022                 kvm_cpu_vmxon(phys_addr);
1023         else if (vmx->loaded_vmcs->cpu != cpu)
1024                 loaded_vmcs_clear(vmx->loaded_vmcs);
1025
1026         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1027                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1028                 vmcs_load(vmx->loaded_vmcs->vmcs);
1029         }
1030
1031         if (vmx->loaded_vmcs->cpu != cpu) {
1032                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1033                 unsigned long sysenter_esp;
1034
1035                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1036                 local_irq_disable();
1037                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1038                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1039                 local_irq_enable();
1040
1041                 /*
1042                  * Linux uses per-cpu TSS and GDT, so set these when switching
1043                  * processors.
1044                  */
1045                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1046                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1047
1048                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1049                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1050                 vmx->loaded_vmcs->cpu = cpu;
1051         }
1052 }
1053
1054 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1055 {
1056         __vmx_load_host_state(to_vmx(vcpu));
1057         if (!vmm_exclusive) {
1058                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1059                 vcpu->cpu = -1;
1060                 kvm_cpu_vmxoff();
1061         }
1062 }
1063
1064 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1065 {
1066         ulong cr0;
1067
1068         if (vcpu->fpu_active)
1069                 return;
1070         vcpu->fpu_active = 1;
1071         cr0 = vmcs_readl(GUEST_CR0);
1072         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1073         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1074         vmcs_writel(GUEST_CR0, cr0);
1075         update_exception_bitmap(vcpu);
1076         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1077         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1078 }
1079
1080 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1081
1082 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1083 {
1084         vmx_decache_cr0_guest_bits(vcpu);
1085         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1086         update_exception_bitmap(vcpu);
1087         vcpu->arch.cr0_guest_owned_bits = 0;
1088         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1089         vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1090 }
1091
1092 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1093 {
1094         unsigned long rflags, save_rflags;
1095
1096         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1097                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1098                 rflags = vmcs_readl(GUEST_RFLAGS);
1099                 if (to_vmx(vcpu)->rmode.vm86_active) {
1100                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1101                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1102                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1103                 }
1104                 to_vmx(vcpu)->rflags = rflags;
1105         }
1106         return to_vmx(vcpu)->rflags;
1107 }
1108
1109 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1110 {
1111         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1112         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
1113         to_vmx(vcpu)->rflags = rflags;
1114         if (to_vmx(vcpu)->rmode.vm86_active) {
1115                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1116                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1117         }
1118         vmcs_writel(GUEST_RFLAGS, rflags);
1119 }
1120
1121 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1122 {
1123         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1124         int ret = 0;
1125
1126         if (interruptibility & GUEST_INTR_STATE_STI)
1127                 ret |= KVM_X86_SHADOW_INT_STI;
1128         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1129                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1130
1131         return ret & mask;
1132 }
1133
1134 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1135 {
1136         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1137         u32 interruptibility = interruptibility_old;
1138
1139         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1140
1141         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1142                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1143         else if (mask & KVM_X86_SHADOW_INT_STI)
1144                 interruptibility |= GUEST_INTR_STATE_STI;
1145
1146         if ((interruptibility != interruptibility_old))
1147                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1148 }
1149
1150 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1151 {
1152         unsigned long rip;
1153
1154         rip = kvm_rip_read(vcpu);
1155         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1156         kvm_rip_write(vcpu, rip);
1157
1158         /* skipping an emulated instruction also counts */
1159         vmx_set_interrupt_shadow(vcpu, 0);
1160 }
1161
1162 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1163 {
1164         /* Ensure that we clear the HLT state in the VMCS.  We don't need to
1165          * explicitly skip the instruction because if the HLT state is set, then
1166          * the instruction is already executing and RIP has already been
1167          * advanced. */
1168         if (!yield_on_hlt &&
1169             vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1170                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1171 }
1172
1173 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1174                                 bool has_error_code, u32 error_code,
1175                                 bool reinject)
1176 {
1177         struct vcpu_vmx *vmx = to_vmx(vcpu);
1178         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1179
1180         if (has_error_code) {
1181                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1182                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1183         }
1184
1185         if (vmx->rmode.vm86_active) {
1186                 int inc_eip = 0;
1187                 if (kvm_exception_is_soft(nr))
1188                         inc_eip = vcpu->arch.event_exit_inst_len;
1189                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1190                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1191                 return;
1192         }
1193
1194         if (kvm_exception_is_soft(nr)) {
1195                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1196                              vmx->vcpu.arch.event_exit_inst_len);
1197                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1198         } else
1199                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1200
1201         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1202         vmx_clear_hlt(vcpu);
1203 }
1204
1205 static bool vmx_rdtscp_supported(void)
1206 {
1207         return cpu_has_vmx_rdtscp();
1208 }
1209
1210 /*
1211  * Swap MSR entry in host/guest MSR entry array.
1212  */
1213 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1214 {
1215         struct shared_msr_entry tmp;
1216
1217         tmp = vmx->guest_msrs[to];
1218         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1219         vmx->guest_msrs[from] = tmp;
1220 }
1221
1222 /*
1223  * Set up the vmcs to automatically save and restore system
1224  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1225  * mode, as fiddling with msrs is very expensive.
1226  */
1227 static void setup_msrs(struct vcpu_vmx *vmx)
1228 {
1229         int save_nmsrs, index;
1230         unsigned long *msr_bitmap;
1231
1232         vmx_load_host_state(vmx);
1233         save_nmsrs = 0;
1234 #ifdef CONFIG_X86_64
1235         if (is_long_mode(&vmx->vcpu)) {
1236                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1237                 if (index >= 0)
1238                         move_msr_up(vmx, index, save_nmsrs++);
1239                 index = __find_msr_index(vmx, MSR_LSTAR);
1240                 if (index >= 0)
1241                         move_msr_up(vmx, index, save_nmsrs++);
1242                 index = __find_msr_index(vmx, MSR_CSTAR);
1243                 if (index >= 0)
1244                         move_msr_up(vmx, index, save_nmsrs++);
1245                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1246                 if (index >= 0 && vmx->rdtscp_enabled)
1247                         move_msr_up(vmx, index, save_nmsrs++);
1248                 /*
1249                  * MSR_STAR is only needed on long mode guests, and only
1250                  * if efer.sce is enabled.
1251                  */
1252                 index = __find_msr_index(vmx, MSR_STAR);
1253                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1254                         move_msr_up(vmx, index, save_nmsrs++);
1255         }
1256 #endif
1257         index = __find_msr_index(vmx, MSR_EFER);
1258         if (index >= 0 && update_transition_efer(vmx, index))
1259                 move_msr_up(vmx, index, save_nmsrs++);
1260
1261         vmx->save_nmsrs = save_nmsrs;
1262
1263         if (cpu_has_vmx_msr_bitmap()) {
1264                 if (is_long_mode(&vmx->vcpu))
1265                         msr_bitmap = vmx_msr_bitmap_longmode;
1266                 else
1267                         msr_bitmap = vmx_msr_bitmap_legacy;
1268
1269                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1270         }
1271 }
1272
1273 /*
1274  * reads and returns guest's timestamp counter "register"
1275  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1276  */
1277 static u64 guest_read_tsc(void)
1278 {
1279         u64 host_tsc, tsc_offset;
1280
1281         rdtscll(host_tsc);
1282         tsc_offset = vmcs_read64(TSC_OFFSET);
1283         return host_tsc + tsc_offset;
1284 }
1285
1286 /*
1287  * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ
1288  * ioctl. In this case the call-back should update internal vmx state to make
1289  * the changes effective.
1290  */
1291 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1292 {
1293         /* Nothing to do here */
1294 }
1295
1296 /*
1297  * writes 'offset' into guest's timestamp counter offset register
1298  */
1299 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1300 {
1301         vmcs_write64(TSC_OFFSET, offset);
1302 }
1303
1304 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1305 {
1306         u64 offset = vmcs_read64(TSC_OFFSET);
1307         vmcs_write64(TSC_OFFSET, offset + adjustment);
1308 }
1309
1310 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1311 {
1312         return target_tsc - native_read_tsc();
1313 }
1314
1315 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1316 {
1317         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1318         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1319 }
1320
1321 /*
1322  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1323  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1324  * all guests if the "nested" module option is off, and can also be disabled
1325  * for a single guest by disabling its VMX cpuid bit.
1326  */
1327 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1328 {
1329         return nested && guest_cpuid_has_vmx(vcpu);
1330 }
1331
1332 /*
1333  * Reads an msr value (of 'msr_index') into 'pdata'.
1334  * Returns 0 on success, non-0 otherwise.
1335  * Assumes vcpu_load() was already called.
1336  */
1337 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1338 {
1339         u64 data;
1340         struct shared_msr_entry *msr;
1341
1342         if (!pdata) {
1343                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1344                 return -EINVAL;
1345         }
1346
1347         switch (msr_index) {
1348 #ifdef CONFIG_X86_64
1349         case MSR_FS_BASE:
1350                 data = vmcs_readl(GUEST_FS_BASE);
1351                 break;
1352         case MSR_GS_BASE:
1353                 data = vmcs_readl(GUEST_GS_BASE);
1354                 break;
1355         case MSR_KERNEL_GS_BASE:
1356                 vmx_load_host_state(to_vmx(vcpu));
1357                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1358                 break;
1359 #endif
1360         case MSR_EFER:
1361                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1362         case MSR_IA32_TSC:
1363                 data = guest_read_tsc();
1364                 break;
1365         case MSR_IA32_SYSENTER_CS:
1366                 data = vmcs_read32(GUEST_SYSENTER_CS);
1367                 break;
1368         case MSR_IA32_SYSENTER_EIP:
1369                 data = vmcs_readl(GUEST_SYSENTER_EIP);
1370                 break;
1371         case MSR_IA32_SYSENTER_ESP:
1372                 data = vmcs_readl(GUEST_SYSENTER_ESP);
1373                 break;
1374         case MSR_TSC_AUX:
1375                 if (!to_vmx(vcpu)->rdtscp_enabled)
1376                         return 1;
1377                 /* Otherwise falls through */
1378         default:
1379                 vmx_load_host_state(to_vmx(vcpu));
1380                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1381                 if (msr) {
1382                         vmx_load_host_state(to_vmx(vcpu));
1383                         data = msr->data;
1384                         break;
1385                 }
1386                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1387         }
1388
1389         *pdata = data;
1390         return 0;
1391 }
1392
1393 /*
1394  * Writes msr value into into the appropriate "register".
1395  * Returns 0 on success, non-0 otherwise.
1396  * Assumes vcpu_load() was already called.
1397  */
1398 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1399 {
1400         struct vcpu_vmx *vmx = to_vmx(vcpu);
1401         struct shared_msr_entry *msr;
1402         int ret = 0;
1403
1404         switch (msr_index) {
1405         case MSR_EFER:
1406                 vmx_load_host_state(vmx);
1407                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1408                 break;
1409 #ifdef CONFIG_X86_64
1410         case MSR_FS_BASE:
1411                 vmx_segment_cache_clear(vmx);
1412                 vmcs_writel(GUEST_FS_BASE, data);
1413                 break;
1414         case MSR_GS_BASE:
1415                 vmx_segment_cache_clear(vmx);
1416                 vmcs_writel(GUEST_GS_BASE, data);
1417                 break;
1418         case MSR_KERNEL_GS_BASE:
1419                 vmx_load_host_state(vmx);
1420                 vmx->msr_guest_kernel_gs_base = data;
1421                 break;
1422 #endif
1423         case MSR_IA32_SYSENTER_CS:
1424                 vmcs_write32(GUEST_SYSENTER_CS, data);
1425                 break;
1426         case MSR_IA32_SYSENTER_EIP:
1427                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1428                 break;
1429         case MSR_IA32_SYSENTER_ESP:
1430                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1431                 break;
1432         case MSR_IA32_TSC:
1433                 kvm_write_tsc(vcpu, data);
1434                 break;
1435         case MSR_IA32_CR_PAT:
1436                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1437                         vmcs_write64(GUEST_IA32_PAT, data);
1438                         vcpu->arch.pat = data;
1439                         break;
1440                 }
1441                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1442                 break;
1443         case MSR_TSC_AUX:
1444                 if (!vmx->rdtscp_enabled)
1445                         return 1;
1446                 /* Check reserved bit, higher 32 bits should be zero */
1447                 if ((data >> 32) != 0)
1448                         return 1;
1449                 /* Otherwise falls through */
1450         default:
1451                 msr = find_msr_entry(vmx, msr_index);
1452                 if (msr) {
1453                         vmx_load_host_state(vmx);
1454                         msr->data = data;
1455                         break;
1456                 }
1457                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1458         }
1459
1460         return ret;
1461 }
1462
1463 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1464 {
1465         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1466         switch (reg) {
1467         case VCPU_REGS_RSP:
1468                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1469                 break;
1470         case VCPU_REGS_RIP:
1471                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1472                 break;
1473         case VCPU_EXREG_PDPTR:
1474                 if (enable_ept)
1475                         ept_save_pdptrs(vcpu);
1476                 break;
1477         default:
1478                 break;
1479         }
1480 }
1481
1482 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1483 {
1484         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1485                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1486         else
1487                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1488
1489         update_exception_bitmap(vcpu);
1490 }
1491
1492 static __init int cpu_has_kvm_support(void)
1493 {
1494         return cpu_has_vmx();
1495 }
1496
1497 static __init int vmx_disabled_by_bios(void)
1498 {
1499         u64 msr;
1500
1501         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1502         if (msr & FEATURE_CONTROL_LOCKED) {
1503                 /* launched w/ TXT and VMX disabled */
1504                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1505                         && tboot_enabled())
1506                         return 1;
1507                 /* launched w/o TXT and VMX only enabled w/ TXT */
1508                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1509                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1510                         && !tboot_enabled()) {
1511                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
1512                                 "activate TXT before enabling KVM\n");
1513                         return 1;
1514                 }
1515                 /* launched w/o TXT and VMX disabled */
1516                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1517                         && !tboot_enabled())
1518                         return 1;
1519         }
1520
1521         return 0;
1522 }
1523
1524 static void kvm_cpu_vmxon(u64 addr)
1525 {
1526         asm volatile (ASM_VMX_VMXON_RAX
1527                         : : "a"(&addr), "m"(addr)
1528                         : "memory", "cc");
1529 }
1530
1531 static int hardware_enable(void *garbage)
1532 {
1533         int cpu = raw_smp_processor_id();
1534         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1535         u64 old, test_bits;
1536
1537         if (read_cr4() & X86_CR4_VMXE)
1538                 return -EBUSY;
1539
1540         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
1541         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1542
1543         test_bits = FEATURE_CONTROL_LOCKED;
1544         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1545         if (tboot_enabled())
1546                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1547
1548         if ((old & test_bits) != test_bits) {
1549                 /* enable and lock */
1550                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1551         }
1552         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1553
1554         if (vmm_exclusive) {
1555                 kvm_cpu_vmxon(phys_addr);
1556                 ept_sync_global();
1557         }
1558
1559         store_gdt(&__get_cpu_var(host_gdt));
1560
1561         return 0;
1562 }
1563
1564 static void vmclear_local_loaded_vmcss(void)
1565 {
1566         int cpu = raw_smp_processor_id();
1567         struct loaded_vmcs *v, *n;
1568
1569         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
1570                                  loaded_vmcss_on_cpu_link)
1571                 __loaded_vmcs_clear(v);
1572 }
1573
1574
1575 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1576  * tricks.
1577  */
1578 static void kvm_cpu_vmxoff(void)
1579 {
1580         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1581 }
1582
1583 static void hardware_disable(void *garbage)
1584 {
1585         if (vmm_exclusive) {
1586                 vmclear_local_loaded_vmcss();
1587                 kvm_cpu_vmxoff();
1588         }
1589         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1590 }
1591
1592 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1593                                       u32 msr, u32 *result)
1594 {
1595         u32 vmx_msr_low, vmx_msr_high;
1596         u32 ctl = ctl_min | ctl_opt;
1597
1598         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1599
1600         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1601         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1602
1603         /* Ensure minimum (required) set of control bits are supported. */
1604         if (ctl_min & ~ctl)
1605                 return -EIO;
1606
1607         *result = ctl;
1608         return 0;
1609 }
1610
1611 static __init bool allow_1_setting(u32 msr, u32 ctl)
1612 {
1613         u32 vmx_msr_low, vmx_msr_high;
1614
1615         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1616         return vmx_msr_high & ctl;
1617 }
1618
1619 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1620 {
1621         u32 vmx_msr_low, vmx_msr_high;
1622         u32 min, opt, min2, opt2;
1623         u32 _pin_based_exec_control = 0;
1624         u32 _cpu_based_exec_control = 0;
1625         u32 _cpu_based_2nd_exec_control = 0;
1626         u32 _vmexit_control = 0;
1627         u32 _vmentry_control = 0;
1628
1629         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1630         opt = PIN_BASED_VIRTUAL_NMIS;
1631         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1632                                 &_pin_based_exec_control) < 0)
1633                 return -EIO;
1634
1635         min =
1636 #ifdef CONFIG_X86_64
1637               CPU_BASED_CR8_LOAD_EXITING |
1638               CPU_BASED_CR8_STORE_EXITING |
1639 #endif
1640               CPU_BASED_CR3_LOAD_EXITING |
1641               CPU_BASED_CR3_STORE_EXITING |
1642               CPU_BASED_USE_IO_BITMAPS |
1643               CPU_BASED_MOV_DR_EXITING |
1644               CPU_BASED_USE_TSC_OFFSETING |
1645               CPU_BASED_MWAIT_EXITING |
1646               CPU_BASED_MONITOR_EXITING |
1647               CPU_BASED_INVLPG_EXITING;
1648
1649         if (yield_on_hlt)
1650                 min |= CPU_BASED_HLT_EXITING;
1651
1652         opt = CPU_BASED_TPR_SHADOW |
1653               CPU_BASED_USE_MSR_BITMAPS |
1654               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1655         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1656                                 &_cpu_based_exec_control) < 0)
1657                 return -EIO;
1658 #ifdef CONFIG_X86_64
1659         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1660                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1661                                            ~CPU_BASED_CR8_STORE_EXITING;
1662 #endif
1663         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1664                 min2 = 0;
1665                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1666                         SECONDARY_EXEC_WBINVD_EXITING |
1667                         SECONDARY_EXEC_ENABLE_VPID |
1668                         SECONDARY_EXEC_ENABLE_EPT |
1669                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
1670                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1671                         SECONDARY_EXEC_RDTSCP;
1672                 if (adjust_vmx_controls(min2, opt2,
1673                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1674                                         &_cpu_based_2nd_exec_control) < 0)
1675                         return -EIO;
1676         }
1677 #ifndef CONFIG_X86_64
1678         if (!(_cpu_based_2nd_exec_control &
1679                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1680                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1681 #endif
1682         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1683                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1684                    enabled */
1685                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1686                                              CPU_BASED_CR3_STORE_EXITING |
1687                                              CPU_BASED_INVLPG_EXITING);
1688                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1689                       vmx_capability.ept, vmx_capability.vpid);
1690         }
1691
1692         min = 0;
1693 #ifdef CONFIG_X86_64
1694         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1695 #endif
1696         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1697         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1698                                 &_vmexit_control) < 0)
1699                 return -EIO;
1700
1701         min = 0;
1702         opt = VM_ENTRY_LOAD_IA32_PAT;
1703         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1704                                 &_vmentry_control) < 0)
1705                 return -EIO;
1706
1707         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1708
1709         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1710         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1711                 return -EIO;
1712
1713 #ifdef CONFIG_X86_64
1714         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1715         if (vmx_msr_high & (1u<<16))
1716                 return -EIO;
1717 #endif
1718
1719         /* Require Write-Back (WB) memory type for VMCS accesses. */
1720         if (((vmx_msr_high >> 18) & 15) != 6)
1721                 return -EIO;
1722
1723         vmcs_conf->size = vmx_msr_high & 0x1fff;
1724         vmcs_conf->order = get_order(vmcs_config.size);
1725         vmcs_conf->revision_id = vmx_msr_low;
1726
1727         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1728         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1729         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1730         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1731         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1732
1733         cpu_has_load_ia32_efer =
1734                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
1735                                 VM_ENTRY_LOAD_IA32_EFER)
1736                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
1737                                    VM_EXIT_LOAD_IA32_EFER);
1738
1739         return 0;
1740 }
1741
1742 static struct vmcs *alloc_vmcs_cpu(int cpu)
1743 {
1744         int node = cpu_to_node(cpu);
1745         struct page *pages;
1746         struct vmcs *vmcs;
1747
1748         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1749         if (!pages)
1750                 return NULL;
1751         vmcs = page_address(pages);
1752         memset(vmcs, 0, vmcs_config.size);
1753         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1754         return vmcs;
1755 }
1756
1757 static struct vmcs *alloc_vmcs(void)
1758 {
1759         return alloc_vmcs_cpu(raw_smp_processor_id());
1760 }
1761
1762 static void free_vmcs(struct vmcs *vmcs)
1763 {
1764         free_pages((unsigned long)vmcs, vmcs_config.order);
1765 }
1766
1767 /*
1768  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
1769  */
1770 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
1771 {
1772         if (!loaded_vmcs->vmcs)
1773                 return;
1774         loaded_vmcs_clear(loaded_vmcs);
1775         free_vmcs(loaded_vmcs->vmcs);
1776         loaded_vmcs->vmcs = NULL;
1777 }
1778
1779 static void free_kvm_area(void)
1780 {
1781         int cpu;
1782
1783         for_each_possible_cpu(cpu) {
1784                 free_vmcs(per_cpu(vmxarea, cpu));
1785                 per_cpu(vmxarea, cpu) = NULL;
1786         }
1787 }
1788
1789 static __init int alloc_kvm_area(void)
1790 {
1791         int cpu;
1792
1793         for_each_possible_cpu(cpu) {
1794                 struct vmcs *vmcs;
1795
1796                 vmcs = alloc_vmcs_cpu(cpu);
1797                 if (!vmcs) {
1798                         free_kvm_area();
1799                         return -ENOMEM;
1800                 }
1801
1802                 per_cpu(vmxarea, cpu) = vmcs;
1803         }
1804         return 0;
1805 }
1806
1807 static __init int hardware_setup(void)
1808 {
1809         if (setup_vmcs_config(&vmcs_config) < 0)
1810                 return -EIO;
1811
1812         if (boot_cpu_has(X86_FEATURE_NX))
1813                 kvm_enable_efer_bits(EFER_NX);
1814
1815         if (!cpu_has_vmx_vpid())
1816                 enable_vpid = 0;
1817
1818         if (!cpu_has_vmx_ept() ||
1819             !cpu_has_vmx_ept_4levels()) {
1820                 enable_ept = 0;
1821                 enable_unrestricted_guest = 0;
1822         }
1823
1824         if (!cpu_has_vmx_unrestricted_guest())
1825                 enable_unrestricted_guest = 0;
1826
1827         if (!cpu_has_vmx_flexpriority())
1828                 flexpriority_enabled = 0;
1829
1830         if (!cpu_has_vmx_tpr_shadow())
1831                 kvm_x86_ops->update_cr8_intercept = NULL;
1832
1833         if (enable_ept && !cpu_has_vmx_ept_2m_page())
1834                 kvm_disable_largepages();
1835
1836         if (!cpu_has_vmx_ple())
1837                 ple_gap = 0;
1838
1839         return alloc_kvm_area();
1840 }
1841
1842 static __exit void hardware_unsetup(void)
1843 {
1844         free_kvm_area();
1845 }
1846
1847 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1848 {
1849         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1850
1851         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1852                 vmcs_write16(sf->selector, save->selector);
1853                 vmcs_writel(sf->base, save->base);
1854                 vmcs_write32(sf->limit, save->limit);
1855                 vmcs_write32(sf->ar_bytes, save->ar);
1856         } else {
1857                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1858                         << AR_DPL_SHIFT;
1859                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1860         }
1861 }
1862
1863 static void enter_pmode(struct kvm_vcpu *vcpu)
1864 {
1865         unsigned long flags;
1866         struct vcpu_vmx *vmx = to_vmx(vcpu);
1867
1868         vmx->emulation_required = 1;
1869         vmx->rmode.vm86_active = 0;
1870
1871         vmx_segment_cache_clear(vmx);
1872
1873         vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
1874         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1875         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1876         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1877
1878         flags = vmcs_readl(GUEST_RFLAGS);
1879         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1880         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1881         vmcs_writel(GUEST_RFLAGS, flags);
1882
1883         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1884                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1885
1886         update_exception_bitmap(vcpu);
1887
1888         if (emulate_invalid_guest_state)
1889                 return;
1890
1891         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1892         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1893         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1894         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1895
1896         vmx_segment_cache_clear(vmx);
1897
1898         vmcs_write16(GUEST_SS_SELECTOR, 0);
1899         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1900
1901         vmcs_write16(GUEST_CS_SELECTOR,
1902                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1903         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1904 }
1905
1906 static gva_t rmode_tss_base(struct kvm *kvm)
1907 {
1908         if (!kvm->arch.tss_addr) {
1909                 struct kvm_memslots *slots;
1910                 gfn_t base_gfn;
1911
1912                 slots = kvm_memslots(kvm);
1913                 base_gfn = slots->memslots[0].base_gfn +
1914                                  kvm->memslots->memslots[0].npages - 3;
1915                 return base_gfn << PAGE_SHIFT;
1916         }
1917         return kvm->arch.tss_addr;
1918 }
1919
1920 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1921 {
1922         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1923
1924         save->selector = vmcs_read16(sf->selector);
1925         save->base = vmcs_readl(sf->base);
1926         save->limit = vmcs_read32(sf->limit);
1927         save->ar = vmcs_read32(sf->ar_bytes);
1928         vmcs_write16(sf->selector, save->base >> 4);
1929         vmcs_write32(sf->base, save->base & 0xffff0);
1930         vmcs_write32(sf->limit, 0xffff);
1931         vmcs_write32(sf->ar_bytes, 0xf3);
1932         if (save->base & 0xf)
1933                 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
1934                             " aligned when entering protected mode (seg=%d)",
1935                             seg);
1936 }
1937
1938 static void enter_rmode(struct kvm_vcpu *vcpu)
1939 {
1940         unsigned long flags;
1941         struct vcpu_vmx *vmx = to_vmx(vcpu);
1942
1943         if (enable_unrestricted_guest)
1944                 return;
1945
1946         vmx->emulation_required = 1;
1947         vmx->rmode.vm86_active = 1;
1948
1949         /*
1950          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
1951          * vcpu. Call it here with phys address pointing 16M below 4G.
1952          */
1953         if (!vcpu->kvm->arch.tss_addr) {
1954                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
1955                              "called before entering vcpu\n");
1956                 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
1957                 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
1958                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
1959         }
1960
1961         vmx_segment_cache_clear(vmx);
1962
1963         vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
1964         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1965         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1966
1967         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1968         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1969
1970         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1971         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1972
1973         flags = vmcs_readl(GUEST_RFLAGS);
1974         vmx->rmode.save_rflags = flags;
1975
1976         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1977
1978         vmcs_writel(GUEST_RFLAGS, flags);
1979         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1980         update_exception_bitmap(vcpu);
1981
1982         if (emulate_invalid_guest_state)
1983                 goto continue_rmode;
1984
1985         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1986         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1987         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1988
1989         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1990         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1991         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1992                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1993         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1994
1995         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1996         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1997         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1998         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1999
2000 continue_rmode:
2001         kvm_mmu_reset_context(vcpu);
2002 }
2003
2004 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2005 {
2006         struct vcpu_vmx *vmx = to_vmx(vcpu);
2007         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2008
2009         if (!msr)
2010                 return;
2011
2012         /*
2013          * Force kernel_gs_base reloading before EFER changes, as control
2014          * of this msr depends on is_long_mode().
2015          */
2016         vmx_load_host_state(to_vmx(vcpu));
2017         vcpu->arch.efer = efer;
2018         if (efer & EFER_LMA) {
2019                 vmcs_write32(VM_ENTRY_CONTROLS,
2020                              vmcs_read32(VM_ENTRY_CONTROLS) |
2021                              VM_ENTRY_IA32E_MODE);
2022                 msr->data = efer;
2023         } else {
2024                 vmcs_write32(VM_ENTRY_CONTROLS,
2025                              vmcs_read32(VM_ENTRY_CONTROLS) &
2026                              ~VM_ENTRY_IA32E_MODE);
2027
2028                 msr->data = efer & ~EFER_LME;
2029         }
2030         setup_msrs(vmx);
2031 }
2032
2033 #ifdef CONFIG_X86_64
2034
2035 static void enter_lmode(struct kvm_vcpu *vcpu)
2036 {
2037         u32 guest_tr_ar;
2038
2039         vmx_segment_cache_clear(to_vmx(vcpu));
2040
2041         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2042         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2043                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
2044                        __func__);
2045                 vmcs_write32(GUEST_TR_AR_BYTES,
2046                              (guest_tr_ar & ~AR_TYPE_MASK)
2047                              | AR_TYPE_BUSY_64_TSS);
2048         }
2049         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2050 }
2051
2052 static void exit_lmode(struct kvm_vcpu *vcpu)
2053 {
2054         vmcs_write32(VM_ENTRY_CONTROLS,
2055                      vmcs_read32(VM_ENTRY_CONTROLS)
2056                      & ~VM_ENTRY_IA32E_MODE);
2057         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2058 }
2059
2060 #endif
2061
2062 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2063 {
2064         vpid_sync_context(to_vmx(vcpu));
2065         if (enable_ept) {
2066                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2067                         return;
2068                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2069         }
2070 }
2071
2072 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2073 {
2074         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2075
2076         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2077         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2078 }
2079
2080 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2081 {
2082         if (enable_ept && is_paging(vcpu))
2083                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2084         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2085 }
2086
2087 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2088 {
2089         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2090
2091         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2092         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2093 }
2094
2095 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2096 {
2097         if (!test_bit(VCPU_EXREG_PDPTR,
2098                       (unsigned long *)&vcpu->arch.regs_dirty))
2099                 return;
2100
2101         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2102                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2103                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2104                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2105                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
2106         }
2107 }
2108
2109 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2110 {
2111         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2112                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2113                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2114                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2115                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2116         }
2117
2118         __set_bit(VCPU_EXREG_PDPTR,
2119                   (unsigned long *)&vcpu->arch.regs_avail);
2120         __set_bit(VCPU_EXREG_PDPTR,
2121                   (unsigned long *)&vcpu->arch.regs_dirty);
2122 }
2123
2124 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2125
2126 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2127                                         unsigned long cr0,
2128                                         struct kvm_vcpu *vcpu)
2129 {
2130         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2131                 vmx_decache_cr3(vcpu);
2132         if (!(cr0 & X86_CR0_PG)) {
2133                 /* From paging/starting to nonpaging */
2134                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2135                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
2136                              (CPU_BASED_CR3_LOAD_EXITING |
2137                               CPU_BASED_CR3_STORE_EXITING));
2138                 vcpu->arch.cr0 = cr0;
2139                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2140         } else if (!is_paging(vcpu)) {
2141                 /* From nonpaging to paging */
2142                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2143                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
2144                              ~(CPU_BASED_CR3_LOAD_EXITING |
2145                                CPU_BASED_CR3_STORE_EXITING));
2146                 vcpu->arch.cr0 = cr0;
2147                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2148         }
2149
2150         if (!(cr0 & X86_CR0_WP))
2151                 *hw_cr0 &= ~X86_CR0_WP;
2152 }
2153
2154 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2155 {
2156         struct vcpu_vmx *vmx = to_vmx(vcpu);
2157         unsigned long hw_cr0;
2158
2159         if (enable_unrestricted_guest)
2160                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2161                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2162         else
2163                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
2164
2165         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2166                 enter_pmode(vcpu);
2167
2168         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2169                 enter_rmode(vcpu);
2170
2171 #ifdef CONFIG_X86_64
2172         if (vcpu->arch.efer & EFER_LME) {
2173                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2174                         enter_lmode(vcpu);
2175                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2176                         exit_lmode(vcpu);
2177         }
2178 #endif
2179
2180         if (enable_ept)
2181                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2182
2183         if (!vcpu->fpu_active)
2184                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
2185
2186         vmcs_writel(CR0_READ_SHADOW, cr0);
2187         vmcs_writel(GUEST_CR0, hw_cr0);
2188         vcpu->arch.cr0 = cr0;
2189         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2190 }
2191
2192 static u64 construct_eptp(unsigned long root_hpa)
2193 {
2194         u64 eptp;
2195
2196         /* TODO write the value reading from MSR */
2197         eptp = VMX_EPT_DEFAULT_MT |
2198                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
2199         eptp |= (root_hpa & PAGE_MASK);
2200
2201         return eptp;
2202 }
2203
2204 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2205 {
2206         unsigned long guest_cr3;
2207         u64 eptp;
2208
2209         guest_cr3 = cr3;
2210         if (enable_ept) {
2211                 eptp = construct_eptp(cr3);
2212                 vmcs_write64(EPT_POINTER, eptp);
2213                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
2214                         vcpu->kvm->arch.ept_identity_map_addr;
2215                 ept_load_pdptrs(vcpu);
2216         }
2217
2218         vmx_flush_tlb(vcpu);
2219         vmcs_writel(GUEST_CR3, guest_cr3);
2220 }
2221
2222 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2223 {
2224         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
2225                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
2226
2227         vcpu->arch.cr4 = cr4;
2228         if (enable_ept) {
2229                 if (!is_paging(vcpu)) {
2230                         hw_cr4 &= ~X86_CR4_PAE;
2231                         hw_cr4 |= X86_CR4_PSE;
2232                 } else if (!(cr4 & X86_CR4_PAE)) {
2233                         hw_cr4 &= ~X86_CR4_PAE;
2234                 }
2235         }
2236
2237         vmcs_writel(CR4_READ_SHADOW, cr4);
2238         vmcs_writel(GUEST_CR4, hw_cr4);
2239 }
2240
2241 static void vmx_get_segment(struct kvm_vcpu *vcpu,
2242                             struct kvm_segment *var, int seg)
2243 {
2244         struct vcpu_vmx *vmx = to_vmx(vcpu);
2245         struct kvm_save_segment *save;
2246         u32 ar;
2247
2248         if (vmx->rmode.vm86_active
2249             && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
2250                 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
2251                 || seg == VCPU_SREG_GS)
2252             && !emulate_invalid_guest_state) {
2253                 switch (seg) {
2254                 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
2255                 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
2256                 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
2257                 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
2258                 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
2259                 default: BUG();
2260                 }
2261                 var->selector = save->selector;
2262                 var->base = save->base;
2263                 var->limit = save->limit;
2264                 ar = save->ar;
2265                 if (seg == VCPU_SREG_TR
2266                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
2267                         goto use_saved_rmode_seg;
2268         }
2269         var->base = vmx_read_guest_seg_base(vmx, seg);
2270         var->limit = vmx_read_guest_seg_limit(vmx, seg);
2271         var->selector = vmx_read_guest_seg_selector(vmx, seg);
2272         ar = vmx_read_guest_seg_ar(vmx, seg);
2273 use_saved_rmode_seg:
2274         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
2275                 ar = 0;
2276         var->type = ar & 15;
2277         var->s = (ar >> 4) & 1;
2278         var->dpl = (ar >> 5) & 3;
2279         var->present = (ar >> 7) & 1;
2280         var->avl = (ar >> 12) & 1;
2281         var->l = (ar >> 13) & 1;
2282         var->db = (ar >> 14) & 1;
2283         var->g = (ar >> 15) & 1;
2284         var->unusable = (ar >> 16) & 1;
2285 }
2286
2287 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2288 {
2289         struct kvm_segment s;
2290
2291         if (to_vmx(vcpu)->rmode.vm86_active) {
2292                 vmx_get_segment(vcpu, &s, seg);
2293                 return s.base;
2294         }
2295         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
2296 }
2297
2298 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
2299 {
2300         if (!is_protmode(vcpu))
2301                 return 0;
2302
2303         if (!is_long_mode(vcpu)
2304             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2305                 return 3;
2306
2307         return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
2308 }
2309
2310 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2311 {
2312         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
2313                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2314                 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
2315         }
2316         return to_vmx(vcpu)->cpl;
2317 }
2318
2319
2320 static u32 vmx_segment_access_rights(struct kvm_segment *var)
2321 {
2322         u32 ar;
2323
2324         if (var->unusable)
2325                 ar = 1 << 16;
2326         else {
2327                 ar = var->type & 15;
2328                 ar |= (var->s & 1) << 4;
2329                 ar |= (var->dpl & 3) << 5;
2330                 ar |= (var->present & 1) << 7;
2331                 ar |= (var->avl & 1) << 12;
2332                 ar |= (var->l & 1) << 13;
2333                 ar |= (var->db & 1) << 14;
2334                 ar |= (var->g & 1) << 15;
2335         }
2336         if (ar == 0) /* a 0 value means unusable */
2337                 ar = AR_UNUSABLE_MASK;
2338
2339         return ar;
2340 }
2341
2342 static void vmx_set_segment(struct kvm_vcpu *vcpu,
2343                             struct kvm_segment *var, int seg)
2344 {
2345         struct vcpu_vmx *vmx = to_vmx(vcpu);
2346         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2347         u32 ar;
2348
2349         vmx_segment_cache_clear(vmx);
2350
2351         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2352                 vmcs_write16(sf->selector, var->selector);
2353                 vmx->rmode.tr.selector = var->selector;
2354                 vmx->rmode.tr.base = var->base;
2355                 vmx->rmode.tr.limit = var->limit;
2356                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
2357                 return;
2358         }
2359         vmcs_writel(sf->base, var->base);
2360         vmcs_write32(sf->limit, var->limit);
2361         vmcs_write16(sf->selector, var->selector);
2362         if (vmx->rmode.vm86_active && var->s) {
2363                 /*
2364                  * Hack real-mode segments into vm86 compatibility.
2365                  */
2366                 if (var->base == 0xffff0000 && var->selector == 0xf000)
2367                         vmcs_writel(sf->base, 0xf0000);
2368                 ar = 0xf3;
2369         } else
2370                 ar = vmx_segment_access_rights(var);
2371
2372         /*
2373          *   Fix the "Accessed" bit in AR field of segment registers for older
2374          * qemu binaries.
2375          *   IA32 arch specifies that at the time of processor reset the
2376          * "Accessed" bit in the AR field of segment registers is 1. And qemu
2377          * is setting it to 0 in the usedland code. This causes invalid guest
2378          * state vmexit when "unrestricted guest" mode is turned on.
2379          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
2380          * tree. Newer qemu binaries with that qemu fix would not need this
2381          * kvm hack.
2382          */
2383         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2384                 ar |= 0x1; /* Accessed */
2385
2386         vmcs_write32(sf->ar_bytes, ar);
2387         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2388 }
2389
2390 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2391 {
2392         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
2393
2394         *db = (ar >> 14) & 1;
2395         *l = (ar >> 13) & 1;
2396 }
2397
2398 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2399 {
2400         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2401         dt->address = vmcs_readl(GUEST_IDTR_BASE);
2402 }
2403
2404 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2405 {
2406         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2407         vmcs_writel(GUEST_IDTR_BASE, dt->address);
2408 }
2409
2410 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2411 {
2412         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2413         dt->address = vmcs_readl(GUEST_GDTR_BASE);
2414 }
2415
2416 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2417 {
2418         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2419         vmcs_writel(GUEST_GDTR_BASE, dt->address);
2420 }
2421
2422 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2423 {
2424         struct kvm_segment var;
2425         u32 ar;
2426
2427         vmx_get_segment(vcpu, &var, seg);
2428         ar = vmx_segment_access_rights(&var);
2429
2430         if (var.base != (var.selector << 4))
2431                 return false;
2432         if (var.limit != 0xffff)
2433                 return false;
2434         if (ar != 0xf3)
2435                 return false;
2436
2437         return true;
2438 }
2439
2440 static bool code_segment_valid(struct kvm_vcpu *vcpu)
2441 {
2442         struct kvm_segment cs;
2443         unsigned int cs_rpl;
2444
2445         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2446         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2447
2448         if (cs.unusable)
2449                 return false;
2450         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2451                 return false;
2452         if (!cs.s)
2453                 return false;
2454         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
2455                 if (cs.dpl > cs_rpl)
2456                         return false;
2457         } else {
2458                 if (cs.dpl != cs_rpl)
2459                         return false;
2460         }
2461         if (!cs.present)
2462                 return false;
2463
2464         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2465         return true;
2466 }
2467
2468 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2469 {
2470         struct kvm_segment ss;
2471         unsigned int ss_rpl;
2472
2473         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2474         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2475
2476         if (ss.unusable)
2477                 return true;
2478         if (ss.type != 3 && ss.type != 7)
2479                 return false;
2480         if (!ss.s)
2481                 return false;
2482         if (ss.dpl != ss_rpl) /* DPL != RPL */
2483                 return false;
2484         if (!ss.present)
2485                 return false;
2486
2487         return true;
2488 }
2489
2490 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2491 {
2492         struct kvm_segment var;
2493         unsigned int rpl;
2494
2495         vmx_get_segment(vcpu, &var, seg);
2496         rpl = var.selector & SELECTOR_RPL_MASK;
2497
2498         if (var.unusable)
2499                 return true;
2500         if (!var.s)
2501                 return false;
2502         if (!var.present)
2503                 return false;
2504         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2505                 if (var.dpl < rpl) /* DPL < RPL */
2506                         return false;
2507         }
2508
2509         /* TODO: Add other members to kvm_segment_field to allow checking for other access
2510          * rights flags
2511          */
2512         return true;
2513 }
2514
2515 static bool tr_valid(struct kvm_vcpu *vcpu)
2516 {
2517         struct kvm_segment tr;
2518
2519         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2520
2521         if (tr.unusable)
2522                 return false;
2523         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
2524                 return false;
2525         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2526                 return false;
2527         if (!tr.present)
2528                 return false;
2529
2530         return true;
2531 }
2532
2533 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2534 {
2535         struct kvm_segment ldtr;
2536
2537         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2538
2539         if (ldtr.unusable)
2540                 return true;
2541         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
2542                 return false;
2543         if (ldtr.type != 2)
2544                 return false;
2545         if (!ldtr.present)
2546                 return false;
2547
2548         return true;
2549 }
2550
2551 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2552 {
2553         struct kvm_segment cs, ss;
2554
2555         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2556         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2557
2558         return ((cs.selector & SELECTOR_RPL_MASK) ==
2559                  (ss.selector & SELECTOR_RPL_MASK));
2560 }
2561
2562 /*
2563  * Check if guest state is valid. Returns true if valid, false if
2564  * not.
2565  * We assume that registers are always usable
2566  */
2567 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2568 {
2569         /* real mode guest state checks */
2570         if (!is_protmode(vcpu)) {
2571                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2572                         return false;
2573                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2574                         return false;
2575                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2576                         return false;
2577                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2578                         return false;
2579                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2580                         return false;
2581                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2582                         return false;
2583         } else {
2584         /* protected mode guest state checks */
2585                 if (!cs_ss_rpl_check(vcpu))
2586                         return false;
2587                 if (!code_segment_valid(vcpu))
2588                         return false;
2589                 if (!stack_segment_valid(vcpu))
2590                         return false;
2591                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2592                         return false;
2593                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2594                         return false;
2595                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2596                         return false;
2597                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2598                         return false;
2599                 if (!tr_valid(vcpu))
2600                         return false;
2601                 if (!ldtr_valid(vcpu))
2602                         return false;
2603         }
2604         /* TODO:
2605          * - Add checks on RIP
2606          * - Add checks on RFLAGS
2607          */
2608
2609         return true;
2610 }
2611
2612 static int init_rmode_tss(struct kvm *kvm)
2613 {
2614         gfn_t fn;
2615         u16 data = 0;
2616         int r, idx, ret = 0;
2617
2618         idx = srcu_read_lock(&kvm->srcu);
2619         fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2620         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2621         if (r < 0)
2622                 goto out;
2623         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2624         r = kvm_write_guest_page(kvm, fn++, &data,
2625                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
2626         if (r < 0)
2627                 goto out;
2628         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2629         if (r < 0)
2630                 goto out;
2631         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2632         if (r < 0)
2633                 goto out;
2634         data = ~0;
2635         r = kvm_write_guest_page(kvm, fn, &data,
2636                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2637                                  sizeof(u8));
2638         if (r < 0)
2639                 goto out;
2640
2641         ret = 1;
2642 out:
2643         srcu_read_unlock(&kvm->srcu, idx);
2644         return ret;
2645 }
2646
2647 static int init_rmode_identity_map(struct kvm *kvm)
2648 {
2649         int i, idx, r, ret;
2650         pfn_t identity_map_pfn;
2651         u32 tmp;
2652
2653         if (!enable_ept)
2654                 return 1;
2655         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2656                 printk(KERN_ERR "EPT: identity-mapping pagetable "
2657                         "haven't been allocated!\n");
2658                 return 0;
2659         }
2660         if (likely(kvm->arch.ept_identity_pagetable_done))
2661                 return 1;
2662         ret = 0;
2663         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2664         idx = srcu_read_lock(&kvm->srcu);
2665         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2666         if (r < 0)
2667                 goto out;
2668         /* Set up identity-mapping pagetable for EPT in real mode */
2669         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2670                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2671                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2672                 r = kvm_write_guest_page(kvm, identity_map_pfn,
2673                                 &tmp, i * sizeof(tmp), sizeof(tmp));
2674                 if (r < 0)
2675                         goto out;
2676         }
2677         kvm->arch.ept_identity_pagetable_done = true;
2678         ret = 1;
2679 out:
2680         srcu_read_unlock(&kvm->srcu, idx);
2681         return ret;
2682 }
2683
2684 static void seg_setup(int seg)
2685 {
2686         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2687         unsigned int ar;
2688
2689         vmcs_write16(sf->selector, 0);
2690         vmcs_writel(sf->base, 0);
2691         vmcs_write32(sf->limit, 0xffff);
2692         if (enable_unrestricted_guest) {
2693                 ar = 0x93;
2694                 if (seg == VCPU_SREG_CS)
2695                         ar |= 0x08; /* code segment */
2696         } else
2697                 ar = 0xf3;
2698
2699         vmcs_write32(sf->ar_bytes, ar);
2700 }
2701
2702 static int alloc_apic_access_page(struct kvm *kvm)
2703 {
2704         struct kvm_userspace_memory_region kvm_userspace_mem;
2705         int r = 0;
2706
2707         mutex_lock(&kvm->slots_lock);
2708         if (kvm->arch.apic_access_page)
2709                 goto out;
2710         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2711         kvm_userspace_mem.flags = 0;
2712         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2713         kvm_userspace_mem.memory_size = PAGE_SIZE;
2714         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2715         if (r)
2716                 goto out;
2717
2718         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2719 out:
2720         mutex_unlock(&kvm->slots_lock);
2721         return r;
2722 }
2723
2724 static int alloc_identity_pagetable(struct kvm *kvm)
2725 {
2726         struct kvm_userspace_memory_region kvm_userspace_mem;
2727         int r = 0;
2728
2729         mutex_lock(&kvm->slots_lock);
2730         if (kvm->arch.ept_identity_pagetable)
2731                 goto out;
2732         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2733         kvm_userspace_mem.flags = 0;
2734         kvm_userspace_mem.guest_phys_addr =
2735                 kvm->arch.ept_identity_map_addr;
2736         kvm_userspace_mem.memory_size = PAGE_SIZE;
2737         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2738         if (r)
2739                 goto out;
2740
2741         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2742                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2743 out:
2744         mutex_unlock(&kvm->slots_lock);
2745         return r;
2746 }
2747
2748 static void allocate_vpid(struct vcpu_vmx *vmx)
2749 {
2750         int vpid;
2751
2752         vmx->vpid = 0;
2753         if (!enable_vpid)
2754                 return;
2755         spin_lock(&vmx_vpid_lock);
2756         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2757         if (vpid < VMX_NR_VPIDS) {
2758                 vmx->vpid = vpid;
2759                 __set_bit(vpid, vmx_vpid_bitmap);
2760         }
2761         spin_unlock(&vmx_vpid_lock);
2762 }
2763
2764 static void free_vpid(struct vcpu_vmx *vmx)
2765 {
2766         if (!enable_vpid)
2767                 return;
2768         spin_lock(&vmx_vpid_lock);
2769         if (vmx->vpid != 0)
2770                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2771         spin_unlock(&vmx_vpid_lock);
2772 }
2773
2774 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2775 {
2776         int f = sizeof(unsigned long);
2777
2778         if (!cpu_has_vmx_msr_bitmap())
2779                 return;
2780
2781         /*
2782          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2783          * have the write-low and read-high bitmap offsets the wrong way round.
2784          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2785          */
2786         if (msr <= 0x1fff) {
2787                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2788                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2789         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2790                 msr &= 0x1fff;
2791                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2792                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2793         }
2794 }
2795
2796 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2797 {
2798         if (!longmode_only)
2799                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2800         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2801 }
2802
2803 /*
2804  * Sets up the vmcs for emulated real mode.
2805  */
2806 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2807 {
2808         u32 host_sysenter_cs, msr_low, msr_high;
2809         u32 junk;
2810         u64 host_pat;
2811         unsigned long a;
2812         struct desc_ptr dt;
2813         int i;
2814         unsigned long kvm_vmx_return;
2815         u32 exec_control;
2816
2817         /* I/O */
2818         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2819         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2820
2821         if (cpu_has_vmx_msr_bitmap())
2822                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2823
2824         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2825
2826         /* Control */
2827         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2828                 vmcs_config.pin_based_exec_ctrl);
2829
2830         exec_control = vmcs_config.cpu_based_exec_ctrl;
2831         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2832                 exec_control &= ~CPU_BASED_TPR_SHADOW;
2833 #ifdef CONFIG_X86_64
2834                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2835                                 CPU_BASED_CR8_LOAD_EXITING;
2836 #endif
2837         }
2838         if (!enable_ept)
2839                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2840                                 CPU_BASED_CR3_LOAD_EXITING  |
2841                                 CPU_BASED_INVLPG_EXITING;
2842         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2843
2844         if (cpu_has_secondary_exec_ctrls()) {
2845                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2846                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2847                         exec_control &=
2848                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2849                 if (vmx->vpid == 0)
2850                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2851                 if (!enable_ept) {
2852                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2853                         enable_unrestricted_guest = 0;
2854                 }
2855                 if (!enable_unrestricted_guest)
2856                         exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2857                 if (!ple_gap)
2858                         exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2859                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2860         }
2861
2862         if (ple_gap) {
2863                 vmcs_write32(PLE_GAP, ple_gap);
2864                 vmcs_write32(PLE_WINDOW, ple_window);
2865         }
2866
2867         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2868         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2869         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
2870
2871         vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS);  /* 22.2.3 */
2872         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
2873         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
2874
2875         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
2876         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2877         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2878         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
2879         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
2880         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2881 #ifdef CONFIG_X86_64
2882         rdmsrl(MSR_FS_BASE, a);
2883         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2884         rdmsrl(MSR_GS_BASE, a);
2885         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2886 #else
2887         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2888         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2889 #endif
2890
2891         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
2892
2893         native_store_idt(&dt);
2894         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
2895
2896         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2897         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2898         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2899         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2900         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2901         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2902         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
2903
2904         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2905         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2906         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2907         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
2908         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2909         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
2910
2911         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2912                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2913                 host_pat = msr_low | ((u64) msr_high << 32);
2914                 vmcs_write64(HOST_IA32_PAT, host_pat);
2915         }
2916         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2917                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2918                 host_pat = msr_low | ((u64) msr_high << 32);
2919                 /* Write the default value follow host pat */
2920                 vmcs_write64(GUEST_IA32_PAT, host_pat);
2921                 /* Keep arch.pat sync with GUEST_IA32_PAT */
2922                 vmx->vcpu.arch.pat = host_pat;
2923         }
2924
2925         for (i = 0; i < NR_VMX_MSR; ++i) {
2926                 u32 index = vmx_msr_index[i];
2927                 u32 data_low, data_high;
2928                 int j = vmx->nmsrs;
2929
2930                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2931                         continue;
2932                 if (wrmsr_safe(index, data_low, data_high) < 0)
2933                         continue;
2934                 vmx->guest_msrs[j].index = i;
2935                 vmx->guest_msrs[j].data = 0;
2936                 vmx->guest_msrs[j].mask = -1ull;
2937                 ++vmx->nmsrs;
2938         }
2939
2940         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2941
2942         /* 22.2.1, 20.8.1 */
2943         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2944
2945         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2946         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
2947         if (enable_ept)
2948                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
2949         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
2950
2951         kvm_write_tsc(&vmx->vcpu, 0);
2952
2953         return 0;
2954 }
2955
2956 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2957 {
2958         struct vcpu_vmx *vmx = to_vmx(vcpu);
2959         u64 msr;
2960         int ret;
2961
2962         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2963
2964         vmx->rmode.vm86_active = 0;
2965
2966         vmx->soft_vnmi_blocked = 0;
2967
2968         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2969         kvm_set_cr8(&vmx->vcpu, 0);
2970         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2971         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2972                 msr |= MSR_IA32_APICBASE_BSP;
2973         kvm_set_apic_base(&vmx->vcpu, msr);
2974
2975         ret = fx_init(&vmx->vcpu);
2976         if (ret != 0)
2977                 goto out;
2978
2979         vmx_segment_cache_clear(vmx);
2980
2981         seg_setup(VCPU_SREG_CS);
2982         /*
2983          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2984          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2985          */
2986         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2987                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2988                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2989         } else {
2990                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2991                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2992         }
2993
2994         seg_setup(VCPU_SREG_DS);
2995         seg_setup(VCPU_SREG_ES);
2996         seg_setup(VCPU_SREG_FS);
2997         seg_setup(VCPU_SREG_GS);
2998         seg_setup(VCPU_SREG_SS);
2999
3000         vmcs_write16(GUEST_TR_SELECTOR, 0);
3001         vmcs_writel(GUEST_TR_BASE, 0);
3002         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3003         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3004
3005         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3006         vmcs_writel(GUEST_LDTR_BASE, 0);
3007         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3008         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3009
3010         vmcs_write32(GUEST_SYSENTER_CS, 0);
3011         vmcs_writel(GUEST_SYSENTER_ESP, 0);
3012         vmcs_writel(GUEST_SYSENTER_EIP, 0);
3013
3014         vmcs_writel(GUEST_RFLAGS, 0x02);
3015         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3016                 kvm_rip_write(vcpu, 0xfff0);
3017         else
3018                 kvm_rip_write(vcpu, 0);
3019         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
3020
3021         vmcs_writel(GUEST_DR7, 0x400);
3022
3023         vmcs_writel(GUEST_GDTR_BASE, 0);
3024         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3025
3026         vmcs_writel(GUEST_IDTR_BASE, 0);
3027         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3028
3029         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3030         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3031         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3032
3033         /* Special registers */
3034         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3035
3036         setup_msrs(vmx);
3037
3038         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
3039
3040         if (cpu_has_vmx_tpr_shadow()) {
3041                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3042                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3043                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
3044                                      __pa(vmx->vcpu.arch.apic->regs));
3045                 vmcs_write32(TPR_THRESHOLD, 0);
3046         }
3047
3048         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3049                 vmcs_write64(APIC_ACCESS_ADDR,
3050                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
3051
3052         if (vmx->vpid != 0)
3053                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3054
3055         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
3056         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
3057         vmx_set_cr4(&vmx->vcpu, 0);
3058         vmx_set_efer(&vmx->vcpu, 0);
3059         vmx_fpu_activate(&vmx->vcpu);
3060         update_exception_bitmap(&vmx->vcpu);
3061
3062         vpid_sync_context(vmx);
3063
3064         ret = 0;
3065
3066         /* HACK: Don't enable emulation on guest boot/reset */
3067         vmx->emulation_required = 0;
3068
3069 out:
3070         return ret;
3071 }
3072
3073 static void enable_irq_window(struct kvm_vcpu *vcpu)
3074 {
3075         u32 cpu_based_vm_exec_control;
3076
3077         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3078         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
3079         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3080 }
3081
3082 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3083 {
3084         u32 cpu_based_vm_exec_control;
3085
3086         if (!cpu_has_virtual_nmis()) {
3087                 enable_irq_window(vcpu);
3088                 return;
3089         }
3090
3091         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
3092                 enable_irq_window(vcpu);
3093                 return;
3094         }
3095         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3096         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
3097         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3098 }
3099
3100 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
3101 {
3102         struct vcpu_vmx *vmx = to_vmx(vcpu);
3103         uint32_t intr;
3104         int irq = vcpu->arch.interrupt.nr;
3105
3106         trace_kvm_inj_virq(irq);
3107
3108         ++vcpu->stat.irq_injections;
3109         if (vmx->rmode.vm86_active) {
3110                 int inc_eip = 0;
3111                 if (vcpu->arch.interrupt.soft)
3112                         inc_eip = vcpu->arch.event_exit_inst_len;
3113                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
3114                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3115                 return;
3116         }
3117         intr = irq | INTR_INFO_VALID_MASK;
3118         if (vcpu->arch.interrupt.soft) {
3119                 intr |= INTR_TYPE_SOFT_INTR;
3120                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3121                              vmx->vcpu.arch.event_exit_inst_len);
3122         } else
3123                 intr |= INTR_TYPE_EXT_INTR;
3124         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
3125         vmx_clear_hlt(vcpu);
3126 }
3127
3128 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
3129 {
3130         struct vcpu_vmx *vmx = to_vmx(vcpu);
3131
3132         if (!cpu_has_virtual_nmis()) {
3133                 /*
3134                  * Tracking the NMI-blocked state in software is built upon
3135                  * finding the next open IRQ window. This, in turn, depends on
3136                  * well-behaving guests: They have to keep IRQs disabled at
3137                  * least as long as the NMI handler runs. Otherwise we may
3138                  * cause NMI nesting, maybe breaking the guest. But as this is
3139                  * highly unlikely, we can live with the residual risk.
3140                  */
3141                 vmx->soft_vnmi_blocked = 1;
3142                 vmx->vnmi_blocked_time = 0;
3143         }
3144
3145         ++vcpu->stat.nmi_injections;
3146         vmx->nmi_known_unmasked = false;
3147         if (vmx->rmode.vm86_active) {
3148                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
3149                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3150                 return;
3151         }
3152         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
3153                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
3154         vmx_clear_hlt(vcpu);
3155 }
3156
3157 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
3158 {
3159         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
3160                 return 0;
3161
3162         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3163                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
3164                    | GUEST_INTR_STATE_NMI));
3165 }
3166
3167 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
3168 {
3169         if (!cpu_has_virtual_nmis())
3170                 return to_vmx(vcpu)->soft_vnmi_blocked;
3171         if (to_vmx(vcpu)->nmi_known_unmasked)
3172                 return false;
3173         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3174 }
3175
3176 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3177 {
3178         struct vcpu_vmx *vmx = to_vmx(vcpu);
3179
3180         if (!cpu_has_virtual_nmis()) {
3181                 if (vmx->soft_vnmi_blocked != masked) {
3182                         vmx->soft_vnmi_blocked = masked;
3183                         vmx->vnmi_blocked_time = 0;
3184                 }
3185         } else {
3186                 vmx->nmi_known_unmasked = !masked;
3187                 if (masked)
3188                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3189                                       GUEST_INTR_STATE_NMI);
3190                 else
3191                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3192                                         GUEST_INTR_STATE_NMI);
3193         }
3194 }
3195
3196 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
3197 {
3198         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
3199                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3200                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
3201 }
3202
3203 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
3204 {
3205         int ret;
3206         struct kvm_userspace_memory_region tss_mem = {
3207                 .slot = TSS_PRIVATE_MEMSLOT,
3208                 .guest_phys_addr = addr,
3209                 .memory_size = PAGE_SIZE * 3,
3210                 .flags = 0,
3211         };
3212
3213         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
3214         if (ret)
3215                 return ret;
3216         kvm->arch.tss_addr = addr;
3217         if (!init_rmode_tss(kvm))
3218                 return  -ENOMEM;
3219
3220         return 0;
3221 }
3222
3223 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
3224                                   int vec, u32 err_code)
3225 {
3226         /*
3227          * Instruction with address size override prefix opcode 0x67
3228          * Cause the #SS fault with 0 error code in VM86 mode.
3229          */
3230         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
3231                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
3232                         return 1;
3233         /*
3234          * Forward all other exceptions that are valid in real mode.
3235          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
3236          *        the required debugging infrastructure rework.
3237          */
3238         switch (vec) {
3239         case DB_VECTOR:
3240                 if (vcpu->guest_debug &
3241                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
3242                         return 0;
3243                 kvm_queue_exception(vcpu, vec);
3244                 return 1;
3245         case BP_VECTOR:
3246                 /*
3247                  * Update instruction length as we may reinject the exception
3248                  * from user space while in guest debugging mode.
3249                  */
3250                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
3251                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3252                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
3253                         return 0;
3254                 /* fall through */
3255         case DE_VECTOR:
3256         case OF_VECTOR:
3257         case BR_VECTOR:
3258         case UD_VECTOR:
3259         case DF_VECTOR:
3260         case SS_VECTOR:
3261         case GP_VECTOR:
3262         case MF_VECTOR:
3263                 kvm_queue_exception(vcpu, vec);
3264                 return 1;
3265         }
3266         return 0;
3267 }
3268
3269 /*
3270  * Trigger machine check on the host. We assume all the MSRs are already set up
3271  * by the CPU and that we still run on the same CPU as the MCE occurred on.
3272  * We pass a fake environment to the machine check handler because we want
3273  * the guest to be always treated like user space, no matter what context
3274  * it used internally.
3275  */
3276 static void kvm_machine_check(void)
3277 {
3278 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
3279         struct pt_regs regs = {
3280                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
3281                 .flags = X86_EFLAGS_IF,
3282         };
3283
3284         do_machine_check(&regs, 0);
3285 #endif
3286 }
3287
3288 static int handle_machine_check(struct kvm_vcpu *vcpu)
3289 {
3290         /* already handled by vcpu_run */
3291         return 1;
3292 }
3293
3294 static int handle_exception(struct kvm_vcpu *vcpu)
3295 {
3296         struct vcpu_vmx *vmx = to_vmx(vcpu);
3297         struct kvm_run *kvm_run = vcpu->run;
3298         u32 intr_info, ex_no, error_code;
3299         unsigned long cr2, rip, dr6;
3300         u32 vect_info;
3301         enum emulation_result er;
3302
3303         vect_info = vmx->idt_vectoring_info;
3304         intr_info = vmx->exit_intr_info;
3305
3306         if (is_machine_check(intr_info))
3307                 return handle_machine_check(vcpu);
3308
3309         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
3310             !is_page_fault(intr_info)) {
3311                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3312                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3313                 vcpu->run->internal.ndata = 2;
3314                 vcpu->run->internal.data[0] = vect_info;
3315                 vcpu->run->internal.data[1] = intr_info;
3316                 return 0;
3317         }
3318
3319         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
3320                 return 1;  /* already handled by vmx_vcpu_run() */
3321
3322         if (is_no_device(intr_info)) {
3323                 vmx_fpu_activate(vcpu);
3324                 return 1;
3325         }
3326
3327         if (is_invalid_opcode(intr_info)) {
3328                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
3329                 if (er != EMULATE_DONE)
3330                         kvm_queue_exception(vcpu, UD_VECTOR);
3331                 return 1;
3332         }
3333
3334         error_code = 0;
3335         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
3336                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3337         if (is_page_fault(intr_info)) {
3338                 /* EPT won't cause page fault directly */
3339                 if (enable_ept)
3340                         BUG();
3341                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
3342                 trace_kvm_page_fault(cr2, error_code);
3343
3344                 if (kvm_event_needs_reinjection(vcpu))
3345                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
3346                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
3347         }
3348
3349         if (vmx->rmode.vm86_active &&
3350             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
3351                                                                 error_code)) {
3352                 if (vcpu->arch.halt_request) {
3353                         vcpu->arch.halt_request = 0;
3354                         return kvm_emulate_halt(vcpu);
3355                 }
3356                 return 1;
3357         }
3358
3359         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
3360         switch (ex_no) {
3361         case DB_VECTOR:
3362                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3363                 if (!(vcpu->guest_debug &
3364                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3365                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3366                         kvm_queue_exception(vcpu, DB_VECTOR);
3367                         return 1;
3368                 }
3369                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3370                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3371                 /* fall through */
3372         case BP_VECTOR:
3373                 /*
3374                  * Update instruction length as we may reinject #BP from
3375                  * user space while in guest debugging mode. Reading it for
3376                  * #DB as well causes no harm, it is not used in that case.
3377                  */
3378                 vmx->vcpu.arch.event_exit_inst_len =
3379                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3380                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
3381                 rip = kvm_rip_read(vcpu);
3382                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3383                 kvm_run->debug.arch.exception = ex_no;
3384                 break;
3385         default:
3386                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3387                 kvm_run->ex.exception = ex_no;
3388                 kvm_run->ex.error_code = error_code;
3389                 break;
3390         }
3391         return 0;
3392 }
3393
3394 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
3395 {
3396         ++vcpu->stat.irq_exits;
3397         return 1;
3398 }
3399
3400 static int handle_triple_fault(struct kvm_vcpu *vcpu)
3401 {
3402         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
3403         return 0;
3404 }
3405
3406 static int handle_io(struct kvm_vcpu *vcpu)
3407 {
3408         unsigned long exit_qualification;
3409         int size, in, string;
3410         unsigned port;
3411
3412         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3413         string = (exit_qualification & 16) != 0;
3414         in = (exit_qualification & 8) != 0;
3415
3416         ++vcpu->stat.io_exits;
3417
3418         if (string || in)
3419                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
3420
3421         port = exit_qualification >> 16;
3422         size = (exit_qualification & 7) + 1;
3423         skip_emulated_instruction(vcpu);
3424
3425         return kvm_fast_pio_out(vcpu, size, port);
3426 }
3427
3428 static void
3429 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3430 {
3431         /*
3432          * Patch in the VMCALL instruction:
3433          */
3434         hypercall[0] = 0x0f;
3435         hypercall[1] = 0x01;
3436         hypercall[2] = 0xc1;
3437 }
3438
3439 static int handle_cr(struct kvm_vcpu *vcpu)
3440 {
3441         unsigned long exit_qualification, val;
3442         int cr;
3443         int reg;
3444         int err;
3445
3446         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3447         cr = exit_qualification & 15;
3448         reg = (exit_qualification >> 8) & 15;
3449         switch ((exit_qualification >> 4) & 3) {
3450         case 0: /* mov to cr */
3451                 val = kvm_register_read(vcpu, reg);
3452                 trace_kvm_cr_write(cr, val);
3453                 switch (cr) {
3454                 case 0:
3455                         err = kvm_set_cr0(vcpu, val);
3456                         kvm_complete_insn_gp(vcpu, err);
3457                         return 1;
3458                 case 3:
3459                         err = kvm_set_cr3(vcpu, val);
3460                         kvm_complete_insn_gp(vcpu, err);
3461                         return 1;
3462                 case 4:
3463                         err = kvm_set_cr4(vcpu, val);
3464                         kvm_complete_insn_gp(vcpu, err);
3465                         return 1;
3466                 case 8: {
3467                                 u8 cr8_prev = kvm_get_cr8(vcpu);
3468                                 u8 cr8 = kvm_register_read(vcpu, reg);
3469                                 err = kvm_set_cr8(vcpu, cr8);
3470                                 kvm_complete_insn_gp(vcpu, err);
3471                                 if (irqchip_in_kernel(vcpu->kvm))
3472                                         return 1;
3473                                 if (cr8_prev <= cr8)
3474                                         return 1;
3475                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
3476                                 return 0;
3477                         }
3478                 };
3479                 break;
3480         case 2: /* clts */
3481                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
3482                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
3483                 skip_emulated_instruction(vcpu);
3484                 vmx_fpu_activate(vcpu);
3485                 return 1;
3486         case 1: /*mov from cr*/
3487                 switch (cr) {
3488                 case 3:
3489                         val = kvm_read_cr3(vcpu);
3490                         kvm_register_write(vcpu, reg, val);
3491                         trace_kvm_cr_read(cr, val);
3492                         skip_emulated_instruction(vcpu);
3493                         return 1;
3494                 case 8:
3495                         val = kvm_get_cr8(vcpu);
3496                         kvm_register_write(vcpu, reg, val);
3497                         trace_kvm_cr_read(cr, val);
3498                         skip_emulated_instruction(vcpu);
3499                         return 1;
3500                 }
3501                 break;
3502         case 3: /* lmsw */
3503                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
3504                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
3505                 kvm_lmsw(vcpu, val);
3506
3507                 skip_emulated_instruction(vcpu);
3508                 return 1;
3509         default:
3510                 break;
3511         }
3512         vcpu->run->exit_reason = 0;
3513         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
3514                (int)(exit_qualification >> 4) & 3, cr);
3515         return 0;
3516 }
3517
3518 static int handle_dr(struct kvm_vcpu *vcpu)
3519 {
3520         unsigned long exit_qualification;
3521         int dr, reg;
3522
3523         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3524         if (!kvm_require_cpl(vcpu, 0))
3525                 return 1;
3526         dr = vmcs_readl(GUEST_DR7);
3527         if (dr & DR7_GD) {
3528                 /*
3529                  * As the vm-exit takes precedence over the debug trap, we
3530                  * need to emulate the latter, either for the host or the
3531                  * guest debugging itself.
3532                  */
3533                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3534                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3535                         vcpu->run->debug.arch.dr7 = dr;
3536                         vcpu->run->debug.arch.pc =
3537                                 vmcs_readl(GUEST_CS_BASE) +
3538                                 vmcs_readl(GUEST_RIP);
3539                         vcpu->run->debug.arch.exception = DB_VECTOR;
3540                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3541                         return 0;
3542                 } else {
3543                         vcpu->arch.dr7 &= ~DR7_GD;
3544                         vcpu->arch.dr6 |= DR6_BD;
3545                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3546                         kvm_queue_exception(vcpu, DB_VECTOR);
3547                         return 1;
3548                 }
3549         }
3550
3551         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3552         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3553         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3554         if (exit_qualification & TYPE_MOV_FROM_DR) {
3555                 unsigned long val;
3556                 if (!kvm_get_dr(vcpu, dr, &val))
3557                         kvm_register_write(vcpu, reg, val);
3558         } else
3559                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
3560         skip_emulated_instruction(vcpu);
3561         return 1;
3562 }
3563
3564 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3565 {
3566         vmcs_writel(GUEST_DR7, val);
3567 }
3568
3569 static int handle_cpuid(struct kvm_vcpu *vcpu)
3570 {
3571         kvm_emulate_cpuid(vcpu);
3572         return 1;
3573 }
3574
3575 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3576 {
3577         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3578         u64 data;
3579
3580         if (vmx_get_msr(vcpu, ecx, &data)) {
3581                 trace_kvm_msr_read_ex(ecx);
3582                 kvm_inject_gp(vcpu, 0);
3583                 return 1;
3584         }
3585
3586         trace_kvm_msr_read(ecx, data);
3587
3588         /* FIXME: handling of bits 32:63 of rax, rdx */
3589         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3590         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3591         skip_emulated_instruction(vcpu);
3592         return 1;
3593 }
3594
3595 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3596 {
3597         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3598         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3599                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3600
3601         if (vmx_set_msr(vcpu, ecx, data) != 0) {
3602                 trace_kvm_msr_write_ex(ecx, data);
3603                 kvm_inject_gp(vcpu, 0);
3604                 return 1;
3605         }
3606
3607         trace_kvm_msr_write(ecx, data);
3608         skip_emulated_instruction(vcpu);
3609         return 1;
3610 }
3611
3612 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3613 {
3614         kvm_make_request(KVM_REQ_EVENT, vcpu);
3615         return 1;
3616 }
3617
3618 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3619 {
3620         u32 cpu_based_vm_exec_control;
3621
3622         /* clear pending irq */
3623         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3624         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3625         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3626
3627         kvm_make_request(KVM_REQ_EVENT, vcpu);
3628
3629         ++vcpu->stat.irq_window_exits;
3630
3631         /*
3632          * If the user space waits to inject interrupts, exit as soon as
3633          * possible
3634          */
3635         if (!irqchip_in_kernel(vcpu->kvm) &&
3636             vcpu->run->request_interrupt_window &&
3637             !kvm_cpu_has_interrupt(vcpu)) {
3638                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3639                 return 0;
3640         }
3641         return 1;
3642 }
3643
3644 static int handle_halt(struct kvm_vcpu *vcpu)
3645 {
3646         skip_emulated_instruction(vcpu);
3647         return kvm_emulate_halt(vcpu);
3648 }
3649
3650 static int handle_vmcall(struct kvm_vcpu *vcpu)
3651 {
3652         skip_emulated_instruction(vcpu);
3653         kvm_emulate_hypercall(vcpu);
3654         return 1;
3655 }
3656
3657 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3658 {
3659         kvm_queue_exception(vcpu, UD_VECTOR);
3660         return 1;
3661 }
3662
3663 static int handle_invd(struct kvm_vcpu *vcpu)
3664 {
3665         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
3666 }
3667
3668 static int handle_invlpg(struct kvm_vcpu *vcpu)
3669 {
3670         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3671
3672         kvm_mmu_invlpg(vcpu, exit_qualification);
3673         skip_emulated_instruction(vcpu);
3674         return 1;
3675 }
3676
3677 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3678 {
3679         skip_emulated_instruction(vcpu);
3680         kvm_emulate_wbinvd(vcpu);
3681         return 1;
3682 }
3683
3684 static int handle_xsetbv(struct kvm_vcpu *vcpu)
3685 {
3686         u64 new_bv = kvm_read_edx_eax(vcpu);
3687         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3688
3689         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
3690                 skip_emulated_instruction(vcpu);
3691         return 1;
3692 }
3693
3694 static int handle_apic_access(struct kvm_vcpu *vcpu)
3695 {
3696         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
3697 }
3698
3699 static int handle_task_switch(struct kvm_vcpu *vcpu)
3700 {
3701         struct vcpu_vmx *vmx = to_vmx(vcpu);
3702         unsigned long exit_qualification;
3703         bool has_error_code = false;
3704         u32 error_code = 0;
3705         u16 tss_selector;
3706         int reason, type, idt_v;
3707
3708         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3709         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3710
3711         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3712
3713         reason = (u32)exit_qualification >> 30;
3714         if (reason == TASK_SWITCH_GATE && idt_v) {
3715                 switch (type) {
3716                 case INTR_TYPE_NMI_INTR:
3717                         vcpu->arch.nmi_injected = false;
3718                         vmx_set_nmi_mask(vcpu, true);
3719                         break;
3720                 case INTR_TYPE_EXT_INTR:
3721                 case INTR_TYPE_SOFT_INTR:
3722                         kvm_clear_interrupt_queue(vcpu);
3723                         break;
3724                 case INTR_TYPE_HARD_EXCEPTION:
3725                         if (vmx->idt_vectoring_info &
3726                             VECTORING_INFO_DELIVER_CODE_MASK) {
3727                                 has_error_code = true;
3728                                 error_code =
3729                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
3730                         }
3731                         /* fall through */
3732                 case INTR_TYPE_SOFT_EXCEPTION:
3733                         kvm_clear_exception_queue(vcpu);
3734                         break;
3735                 default:
3736                         break;
3737                 }
3738         }
3739         tss_selector = exit_qualification;
3740
3741         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3742                        type != INTR_TYPE_EXT_INTR &&
3743                        type != INTR_TYPE_NMI_INTR))
3744                 skip_emulated_instruction(vcpu);
3745
3746         if (kvm_task_switch(vcpu, tss_selector, reason,
3747                                 has_error_code, error_code) == EMULATE_FAIL) {
3748                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3749                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3750                 vcpu->run->internal.ndata = 0;
3751                 return 0;
3752         }
3753
3754         /* clear all local breakpoint enable flags */
3755         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3756
3757         /*
3758          * TODO: What about debug traps on tss switch?
3759          *       Are we supposed to inject them and update dr6?
3760          */
3761
3762         return 1;
3763 }
3764
3765 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3766 {
3767         unsigned long exit_qualification;
3768         gpa_t gpa;
3769         int gla_validity;
3770
3771         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3772
3773         if (exit_qualification & (1 << 6)) {
3774                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3775                 return -EINVAL;
3776         }
3777
3778         gla_validity = (exit_qualification >> 7) & 0x3;
3779         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3780                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3781                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3782                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3783                         vmcs_readl(GUEST_LINEAR_ADDRESS));
3784                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3785                         (long unsigned int)exit_qualification);
3786                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3787                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3788                 return 0;
3789         }
3790
3791         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3792         trace_kvm_page_fault(gpa, exit_qualification);
3793         return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
3794 }
3795
3796 static u64 ept_rsvd_mask(u64 spte, int level)
3797 {
3798         int i;
3799         u64 mask = 0;
3800
3801         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3802                 mask |= (1ULL << i);
3803
3804         if (level > 2)
3805                 /* bits 7:3 reserved */
3806                 mask |= 0xf8;
3807         else if (level == 2) {
3808                 if (spte & (1ULL << 7))
3809                         /* 2MB ref, bits 20:12 reserved */
3810                         mask |= 0x1ff000;
3811                 else
3812                         /* bits 6:3 reserved */
3813                         mask |= 0x78;
3814         }
3815
3816         return mask;
3817 }
3818
3819 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3820                                        int level)
3821 {
3822         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3823
3824         /* 010b (write-only) */
3825         WARN_ON((spte & 0x7) == 0x2);
3826
3827         /* 110b (write/execute) */
3828         WARN_ON((spte & 0x7) == 0x6);
3829
3830         /* 100b (execute-only) and value not supported by logical processor */
3831         if (!cpu_has_vmx_ept_execute_only())
3832                 WARN_ON((spte & 0x7) == 0x4);
3833
3834         /* not 000b */
3835         if ((spte & 0x7)) {
3836                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3837
3838                 if (rsvd_bits != 0) {
3839                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3840                                          __func__, rsvd_bits);
3841                         WARN_ON(1);
3842                 }
3843
3844                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3845                         u64 ept_mem_type = (spte & 0x38) >> 3;
3846
3847                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
3848                             ept_mem_type == 7) {
3849                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3850                                                 __func__, ept_mem_type);
3851                                 WARN_ON(1);
3852                         }
3853                 }
3854         }
3855 }
3856
3857 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3858 {
3859         u64 sptes[4];
3860         int nr_sptes, i;
3861         gpa_t gpa;
3862
3863         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3864
3865         printk(KERN_ERR "EPT: Misconfiguration.\n");
3866         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3867
3868         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3869
3870         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3871                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3872
3873         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3874         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3875
3876         return 0;
3877 }
3878
3879 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3880 {
3881         u32 cpu_based_vm_exec_control;
3882
3883         /* clear pending NMI */
3884         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3885         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3886         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3887         ++vcpu->stat.nmi_window_exits;
3888         kvm_make_request(KVM_REQ_EVENT, vcpu);
3889
3890         return 1;
3891 }
3892
3893 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3894 {
3895         struct vcpu_vmx *vmx = to_vmx(vcpu);
3896         enum emulation_result err = EMULATE_DONE;
3897         int ret = 1;
3898         u32 cpu_exec_ctrl;
3899         bool intr_window_requested;
3900
3901         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3902         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
3903
3904         while (!guest_state_valid(vcpu)) {
3905                 if (intr_window_requested
3906                     && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
3907                         return handle_interrupt_window(&vmx->vcpu);
3908
3909                 err = emulate_instruction(vcpu, 0);
3910
3911                 if (err == EMULATE_DO_MMIO) {
3912                         ret = 0;
3913                         goto out;
3914                 }
3915
3916                 if (err != EMULATE_DONE)
3917                         return 0;
3918
3919                 if (signal_pending(current))
3920                         goto out;
3921                 if (need_resched())
3922                         schedule();
3923         }
3924
3925         vmx->emulation_required = 0;
3926 out:
3927         return ret;
3928 }
3929
3930 /*
3931  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3932  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3933  */
3934 static int handle_pause(struct kvm_vcpu *vcpu)
3935 {
3936         skip_emulated_instruction(vcpu);
3937         kvm_vcpu_on_spin(vcpu);
3938
3939         return 1;
3940 }
3941
3942 static int handle_invalid_op(struct kvm_vcpu *vcpu)
3943 {
3944         kvm_queue_exception(vcpu, UD_VECTOR);
3945         return 1;
3946 }
3947
3948 /*
3949  * Emulate the VMXON instruction.
3950  * Currently, we just remember that VMX is active, and do not save or even
3951  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
3952  * do not currently need to store anything in that guest-allocated memory
3953  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
3954  * argument is different from the VMXON pointer (which the spec says they do).
3955  */
3956 static int handle_vmon(struct kvm_vcpu *vcpu)
3957 {
3958         struct kvm_segment cs;
3959         struct vcpu_vmx *vmx = to_vmx(vcpu);
3960
3961         /* The Intel VMX Instruction Reference lists a bunch of bits that
3962          * are prerequisite to running VMXON, most notably cr4.VMXE must be
3963          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
3964          * Otherwise, we should fail with #UD. We test these now:
3965          */
3966         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
3967             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
3968             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3969                 kvm_queue_exception(vcpu, UD_VECTOR);
3970                 return 1;
3971         }
3972
3973         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3974         if (is_long_mode(vcpu) && !cs.l) {
3975                 kvm_queue_exception(vcpu, UD_VECTOR);
3976                 return 1;
3977         }
3978
3979         if (vmx_get_cpl(vcpu)) {
3980                 kvm_inject_gp(vcpu, 0);
3981                 return 1;
3982         }
3983
3984         vmx->nested.vmxon = true;
3985
3986         skip_emulated_instruction(vcpu);
3987         return 1;
3988 }
3989
3990 /*
3991  * Intel's VMX Instruction Reference specifies a common set of prerequisites
3992  * for running VMX instructions (except VMXON, whose prerequisites are
3993  * slightly different). It also specifies what exception to inject otherwise.
3994  */
3995 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
3996 {
3997         struct kvm_segment cs;
3998         struct vcpu_vmx *vmx = to_vmx(vcpu);
3999
4000         if (!vmx->nested.vmxon) {
4001                 kvm_queue_exception(vcpu, UD_VECTOR);
4002                 return 0;
4003         }
4004
4005         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4006         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
4007             (is_long_mode(vcpu) && !cs.l)) {
4008                 kvm_queue_exception(vcpu, UD_VECTOR);
4009                 return 0;
4010         }
4011
4012         if (vmx_get_cpl(vcpu)) {
4013                 kvm_inject_gp(vcpu, 0);
4014                 return 0;
4015         }
4016
4017         return 1;
4018 }
4019
4020 /*
4021  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
4022  * just stops using VMX.
4023  */
4024 static void free_nested(struct vcpu_vmx *vmx)
4025 {
4026         if (!vmx->nested.vmxon)
4027                 return;
4028         vmx->nested.vmxon = false;
4029 }
4030
4031 /* Emulate the VMXOFF instruction */
4032 static int handle_vmoff(struct kvm_vcpu *vcpu)
4033 {
4034         if (!nested_vmx_check_permission(vcpu))
4035                 return 1;
4036         free_nested(to_vmx(vcpu));
4037         skip_emulated_instruction(vcpu);
4038         return 1;
4039 }
4040
4041 /*
4042  * The exit handlers return 1 if the exit was handled fully and guest execution
4043  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
4044  * to be done to userspace and return 0.
4045  */
4046 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
4047         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
4048         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
4049         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
4050         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
4051         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
4052         [EXIT_REASON_CR_ACCESS]               = handle_cr,
4053         [EXIT_REASON_DR_ACCESS]               = handle_dr,
4054         [EXIT_REASON_CPUID]                   = handle_cpuid,
4055         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
4056         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
4057         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
4058         [EXIT_REASON_HLT]                     = handle_halt,
4059         [EXIT_REASON_INVD]                    = handle_invd,
4060         [EXIT_REASON_INVLPG]                  = handle_invlpg,
4061         [EXIT_REASON_VMCALL]                  = handle_vmcall,
4062         [EXIT_REASON_VMCLEAR]                 = handle_vmx_insn,
4063         [EXIT_REASON_VMLAUNCH]                = handle_vmx_insn,
4064         [EXIT_REASON_VMPTRLD]                 = handle_vmx_insn,
4065         [EXIT_REASON_VMPTRST]                 = handle_vmx_insn,
4066         [EXIT_REASON_VMREAD]                  = handle_vmx_insn,
4067         [EXIT_REASON_VMRESUME]                = handle_vmx_insn,
4068         [EXIT_REASON_VMWRITE]                 = handle_vmx_insn,
4069         [EXIT_REASON_VMOFF]                   = handle_vmoff,
4070         [EXIT_REASON_VMON]                    = handle_vmon,
4071         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
4072         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
4073         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
4074         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
4075         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
4076         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
4077         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
4078         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
4079         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
4080         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
4081         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
4082 };
4083
4084 static const int kvm_vmx_max_exit_handlers =
4085         ARRAY_SIZE(kvm_vmx_exit_handlers);
4086
4087 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4088 {
4089         *info1 = vmcs_readl(EXIT_QUALIFICATION);
4090         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
4091 }
4092
4093 /*
4094  * The guest has exited.  See if we can fix it or if we need userspace
4095  * assistance.
4096  */
4097 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
4098 {
4099         struct vcpu_vmx *vmx = to_vmx(vcpu);
4100         u32 exit_reason = vmx->exit_reason;
4101         u32 vectoring_info = vmx->idt_vectoring_info;
4102
4103         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
4104
4105         /* If guest state is invalid, start emulating */
4106         if (vmx->emulation_required && emulate_invalid_guest_state)
4107                 return handle_invalid_guest_state(vcpu);
4108
4109         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
4110                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4111                 vcpu->run->fail_entry.hardware_entry_failure_reason
4112                         = exit_reason;
4113                 return 0;
4114         }
4115
4116         if (unlikely(vmx->fail)) {
4117                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4118                 vcpu->run->fail_entry.hardware_entry_failure_reason
4119                         = vmcs_read32(VM_INSTRUCTION_ERROR);
4120                 return 0;
4121         }
4122
4123         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
4124                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
4125                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
4126                         exit_reason != EXIT_REASON_TASK_SWITCH))
4127                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
4128                        "(0x%x) and exit reason is 0x%x\n",
4129                        __func__, vectoring_info, exit_reason);
4130
4131         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
4132                 if (vmx_interrupt_allowed(vcpu)) {
4133                         vmx->soft_vnmi_blocked = 0;
4134                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4135                            vcpu->arch.nmi_pending) {
4136                         /*
4137                          * This CPU don't support us in finding the end of an
4138                          * NMI-blocked window if the guest runs with IRQs
4139                          * disabled. So we pull the trigger after 1 s of
4140                          * futile waiting, but inform the user about this.
4141                          */
4142                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
4143                                "state on VCPU %d after 1 s timeout\n",
4144                                __func__, vcpu->vcpu_id);
4145                         vmx->soft_vnmi_blocked = 0;
4146                 }
4147         }
4148
4149         if (exit_reason < kvm_vmx_max_exit_handlers
4150             && kvm_vmx_exit_handlers[exit_reason])
4151                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
4152         else {
4153                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4154                 vcpu->run->hw.hardware_exit_reason = exit_reason;
4155         }
4156         return 0;
4157 }
4158
4159 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
4160 {
4161         if (irr == -1 || tpr < irr) {
4162                 vmcs_write32(TPR_THRESHOLD, 0);
4163                 return;
4164         }
4165
4166         vmcs_write32(TPR_THRESHOLD, irr);
4167 }
4168
4169 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
4170 {
4171         u32 exit_intr_info;
4172
4173         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
4174               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
4175                 return;
4176
4177         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
4178         exit_intr_info = vmx->exit_intr_info;
4179
4180         /* Handle machine checks before interrupts are enabled */
4181         if (is_machine_check(exit_intr_info))
4182                 kvm_machine_check();
4183
4184         /* We need to handle NMIs before interrupts are enabled */
4185         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
4186             (exit_intr_info & INTR_INFO_VALID_MASK)) {
4187                 kvm_before_handle_nmi(&vmx->vcpu);
4188                 asm("int $2");
4189                 kvm_after_handle_nmi(&vmx->vcpu);
4190         }
4191 }
4192
4193 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
4194 {
4195         u32 exit_intr_info;
4196         bool unblock_nmi;
4197         u8 vector;
4198         bool idtv_info_valid;
4199
4200         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
4201
4202         if (cpu_has_virtual_nmis()) {
4203                 if (vmx->nmi_known_unmasked)
4204                         return;
4205                 /*
4206                  * Can't use vmx->exit_intr_info since we're not sure what
4207                  * the exit reason is.
4208                  */
4209                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
4210                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
4211                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
4212                 /*
4213                  * SDM 3: 27.7.1.2 (September 2008)
4214                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
4215                  * a guest IRET fault.
4216                  * SDM 3: 23.2.2 (September 2008)
4217                  * Bit 12 is undefined in any of the following cases:
4218                  *  If the VM exit sets the valid bit in the IDT-vectoring
4219                  *   information field.
4220                  *  If the VM exit is due to a double fault.
4221                  */
4222                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
4223                     vector != DF_VECTOR && !idtv_info_valid)
4224                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4225                                       GUEST_INTR_STATE_NMI);
4226                 else
4227                         vmx->nmi_known_unmasked =
4228                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
4229                                   & GUEST_INTR_STATE_NMI);
4230         } else if (unlikely(vmx->soft_vnmi_blocked))
4231                 vmx->vnmi_blocked_time +=
4232                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
4233 }
4234
4235 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
4236                                       u32 idt_vectoring_info,
4237                                       int instr_len_field,
4238                                       int error_code_field)
4239 {
4240         u8 vector;
4241         int type;
4242         bool idtv_info_valid;
4243
4244         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
4245
4246         vmx->vcpu.arch.nmi_injected = false;
4247         kvm_clear_exception_queue(&vmx->vcpu);
4248         kvm_clear_interrupt_queue(&vmx->vcpu);
4249
4250         if (!idtv_info_valid)
4251                 return;
4252
4253         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
4254
4255         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
4256         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
4257
4258         switch (type) {
4259         case INTR_TYPE_NMI_INTR:
4260                 vmx->vcpu.arch.nmi_injected = true;
4261                 /*
4262                  * SDM 3: 27.7.1.2 (September 2008)
4263                  * Clear bit "block by NMI" before VM entry if a NMI
4264                  * delivery faulted.
4265                  */
4266                 vmx_set_nmi_mask(&vmx->vcpu, false);
4267                 break;
4268         case INTR_TYPE_SOFT_EXCEPTION:
4269                 vmx->vcpu.arch.event_exit_inst_len =
4270                         vmcs_read32(instr_len_field);
4271                 /* fall through */
4272         case INTR_TYPE_HARD_EXCEPTION:
4273                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
4274                         u32 err = vmcs_read32(error_code_field);
4275                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
4276                 } else
4277                         kvm_queue_exception(&vmx->vcpu, vector);
4278                 break;
4279         case INTR_TYPE_SOFT_INTR:
4280                 vmx->vcpu.arch.event_exit_inst_len =
4281                         vmcs_read32(instr_len_field);
4282                 /* fall through */
4283         case INTR_TYPE_EXT_INTR:
4284                 kvm_queue_interrupt(&vmx->vcpu, vector,
4285                         type == INTR_TYPE_SOFT_INTR);
4286                 break;
4287         default:
4288                 break;
4289         }
4290 }
4291
4292 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
4293 {
4294         __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
4295                                   VM_EXIT_INSTRUCTION_LEN,
4296                                   IDT_VECTORING_ERROR_CODE);
4297 }
4298
4299 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
4300 {
4301         __vmx_complete_interrupts(to_vmx(vcpu),
4302                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
4303                                   VM_ENTRY_INSTRUCTION_LEN,
4304                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
4305
4306         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
4307 }
4308
4309 #ifdef CONFIG_X86_64
4310 #define R "r"
4311 #define Q "q"
4312 #else
4313 #define R "e"
4314 #define Q "l"
4315 #endif
4316
4317 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
4318 {
4319         struct vcpu_vmx *vmx = to_vmx(vcpu);
4320
4321         /* Record the guest's net vcpu time for enforced NMI injections. */
4322         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
4323                 vmx->entry_time = ktime_get();
4324
4325         /* Don't enter VMX if guest state is invalid, let the exit handler
4326            start emulation until we arrive back to a valid state */
4327         if (vmx->emulation_required && emulate_invalid_guest_state)
4328                 return;
4329
4330         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
4331                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
4332         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
4333                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
4334
4335         /* When single-stepping over STI and MOV SS, we must clear the
4336          * corresponding interruptibility bits in the guest state. Otherwise
4337          * vmentry fails as it then expects bit 14 (BS) in pending debug
4338          * exceptions being set, but that's not correct for the guest debugging
4339          * case. */
4340         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
4341                 vmx_set_interrupt_shadow(vcpu, 0);
4342
4343         vmx->__launched = vmx->loaded_vmcs->launched;
4344         asm(
4345                 /* Store host registers */
4346                 "push %%"R"dx; push %%"R"bp;"
4347                 "push %%"R"cx \n\t" /* placeholder for guest rcx */
4348                 "push %%"R"cx \n\t"
4349                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
4350                 "je 1f \n\t"
4351                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4352                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
4353                 "1: \n\t"
4354                 /* Reload cr2 if changed */
4355                 "mov %c[cr2](%0), %%"R"ax \n\t"
4356                 "mov %%cr2, %%"R"dx \n\t"
4357                 "cmp %%"R"ax, %%"R"dx \n\t"
4358                 "je 2f \n\t"
4359                 "mov %%"R"ax, %%cr2 \n\t"
4360                 "2: \n\t"
4361                 /* Check if vmlaunch of vmresume is needed */
4362                 "cmpl $0, %c[launched](%0) \n\t"
4363                 /* Load guest registers.  Don't clobber flags. */
4364                 "mov %c[rax](%0), %%"R"ax \n\t"
4365                 "mov %c[rbx](%0), %%"R"bx \n\t"
4366                 "mov %c[rdx](%0), %%"R"dx \n\t"
4367                 "mov %c[rsi](%0), %%"R"si \n\t"
4368                 "mov %c[rdi](%0), %%"R"di \n\t"
4369                 "mov %c[rbp](%0), %%"R"bp \n\t"
4370 #ifdef CONFIG_X86_64
4371                 "mov %c[r8](%0),  %%r8  \n\t"
4372                 "mov %c[r9](%0),  %%r9  \n\t"
4373                 "mov %c[r10](%0), %%r10 \n\t"
4374                 "mov %c[r11](%0), %%r11 \n\t"
4375                 "mov %c[r12](%0), %%r12 \n\t"
4376                 "mov %c[r13](%0), %%r13 \n\t"
4377                 "mov %c[r14](%0), %%r14 \n\t"
4378                 "mov %c[r15](%0), %%r15 \n\t"
4379 #endif
4380                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
4381
4382                 /* Enter guest mode */
4383                 "jne .Llaunched \n\t"
4384                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
4385                 "jmp .Lkvm_vmx_return \n\t"
4386                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
4387                 ".Lkvm_vmx_return: "
4388                 /* Save guest registers, load host registers, keep flags */
4389                 "mov %0, %c[wordsize](%%"R"sp) \n\t"
4390                 "pop %0 \n\t"
4391                 "mov %%"R"ax, %c[rax](%0) \n\t"
4392                 "mov %%"R"bx, %c[rbx](%0) \n\t"
4393                 "pop"Q" %c[rcx](%0) \n\t"
4394                 "mov %%"R"dx, %c[rdx](%0) \n\t"
4395                 "mov %%"R"si, %c[rsi](%0) \n\t"
4396                 "mov %%"R"di, %c[rdi](%0) \n\t"
4397                 "mov %%"R"bp, %c[rbp](%0) \n\t"
4398 #ifdef CONFIG_X86_64
4399                 "mov %%r8,  %c[r8](%0) \n\t"
4400                 "mov %%r9,  %c[r9](%0) \n\t"
4401                 "mov %%r10, %c[r10](%0) \n\t"
4402                 "mov %%r11, %c[r11](%0) \n\t"
4403                 "mov %%r12, %c[r12](%0) \n\t"
4404                 "mov %%r13, %c[r13](%0) \n\t"
4405                 "mov %%r14, %c[r14](%0) \n\t"
4406                 "mov %%r15, %c[r15](%0) \n\t"
4407 #endif
4408                 "mov %%cr2, %%"R"ax   \n\t"
4409                 "mov %%"R"ax, %c[cr2](%0) \n\t"
4410
4411                 "pop  %%"R"bp; pop  %%"R"dx \n\t"
4412                 "setbe %c[fail](%0) \n\t"
4413               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
4414                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
4415                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
4416                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
4417                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
4418                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
4419                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
4420                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
4421                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
4422                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
4423                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
4424 #ifdef CONFIG_X86_64
4425                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
4426                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
4427                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
4428                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
4429                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4430                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4431                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4432                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
4433 #endif
4434                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
4435                 [wordsize]"i"(sizeof(ulong))
4436               : "cc", "memory"
4437                 , R"ax", R"bx", R"di", R"si"
4438 #ifdef CONFIG_X86_64
4439                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4440 #endif
4441               );
4442
4443         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
4444                                   | (1 << VCPU_EXREG_RFLAGS)
4445                                   | (1 << VCPU_EXREG_CPL)
4446                                   | (1 << VCPU_EXREG_PDPTR)
4447                                   | (1 << VCPU_EXREG_SEGMENTS)
4448                                   | (1 << VCPU_EXREG_CR3));
4449         vcpu->arch.regs_dirty = 0;
4450
4451         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
4452
4453         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
4454         vmx->loaded_vmcs->launched = 1;
4455
4456         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
4457
4458         vmx_complete_atomic_exit(vmx);
4459         vmx_recover_nmi_blocking(vmx);
4460         vmx_complete_interrupts(vmx);
4461 }
4462
4463 #undef R
4464 #undef Q
4465
4466 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4467 {
4468         struct vcpu_vmx *vmx = to_vmx(vcpu);
4469
4470         free_vpid(vmx);
4471         free_nested(vmx);
4472         free_loaded_vmcs(vmx->loaded_vmcs);
4473         kfree(vmx->guest_msrs);
4474         kvm_vcpu_uninit(vcpu);
4475         kmem_cache_free(kvm_vcpu_cache, vmx);
4476 }
4477
4478 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
4479 {
4480         int err;
4481         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
4482         int cpu;
4483
4484         if (!vmx)
4485                 return ERR_PTR(-ENOMEM);
4486
4487         allocate_vpid(vmx);
4488
4489         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4490         if (err)
4491                 goto free_vcpu;
4492
4493         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
4494         err = -ENOMEM;
4495         if (!vmx->guest_msrs) {
4496                 goto uninit_vcpu;
4497         }
4498
4499         vmx->loaded_vmcs = &vmx->vmcs01;
4500         vmx->loaded_vmcs->vmcs = alloc_vmcs();
4501         if (!vmx->loaded_vmcs->vmcs)
4502                 goto free_msrs;
4503         if (!vmm_exclusive)
4504                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
4505         loaded_vmcs_init(vmx->loaded_vmcs);
4506         if (!vmm_exclusive)
4507                 kvm_cpu_vmxoff();
4508
4509         cpu = get_cpu();
4510         vmx_vcpu_load(&vmx->vcpu, cpu);
4511         vmx->vcpu.cpu = cpu;
4512         err = vmx_vcpu_setup(vmx);
4513         vmx_vcpu_put(&vmx->vcpu);
4514         put_cpu();
4515         if (err)
4516                 goto free_vmcs;
4517         if (vm_need_virtualize_apic_accesses(kvm))
4518                 err = alloc_apic_access_page(kvm);
4519                 if (err)
4520                         goto free_vmcs;
4521
4522         if (enable_ept) {
4523                 if (!kvm->arch.ept_identity_map_addr)
4524                         kvm->arch.ept_identity_map_addr =
4525                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
4526                 err = -ENOMEM;
4527                 if (alloc_identity_pagetable(kvm) != 0)
4528                         goto free_vmcs;
4529                 if (!init_rmode_identity_map(kvm))
4530                         goto free_vmcs;
4531         }
4532
4533         return &vmx->vcpu;
4534
4535 free_vmcs:
4536         free_vmcs(vmx->loaded_vmcs->vmcs);
4537 free_msrs:
4538         kfree(vmx->guest_msrs);
4539 uninit_vcpu:
4540         kvm_vcpu_uninit(&vmx->vcpu);
4541 free_vcpu:
4542         free_vpid(vmx);
4543         kmem_cache_free(kvm_vcpu_cache, vmx);
4544         return ERR_PTR(err);
4545 }
4546
4547 static void __init vmx_check_processor_compat(void *rtn)
4548 {
4549         struct vmcs_config vmcs_conf;
4550
4551         *(int *)rtn = 0;
4552         if (setup_vmcs_config(&vmcs_conf) < 0)
4553                 *(int *)rtn = -EIO;
4554         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4555                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4556                                 smp_processor_id());
4557                 *(int *)rtn = -EIO;
4558         }
4559 }
4560
4561 static int get_ept_level(void)
4562 {
4563         return VMX_EPT_DEFAULT_GAW + 1;
4564 }
4565
4566 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4567 {
4568         u64 ret;
4569
4570         /* For VT-d and EPT combination
4571          * 1. MMIO: always map as UC
4572          * 2. EPT with VT-d:
4573          *   a. VT-d without snooping control feature: can't guarantee the
4574          *      result, try to trust guest.
4575          *   b. VT-d with snooping control feature: snooping control feature of
4576          *      VT-d engine can guarantee the cache correctness. Just set it
4577          *      to WB to keep consistent with host. So the same as item 3.
4578          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
4579          *    consistent with host MTRR
4580          */
4581         if (is_mmio)
4582                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
4583         else if (vcpu->kvm->arch.iommu_domain &&
4584                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4585                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4586                       VMX_EPT_MT_EPTE_SHIFT;
4587         else
4588                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
4589                         | VMX_EPT_IPAT_BIT;
4590
4591         return ret;
4592 }
4593
4594 #define _ER(x) { EXIT_REASON_##x, #x }
4595
4596 static const struct trace_print_flags vmx_exit_reasons_str[] = {
4597         _ER(EXCEPTION_NMI),
4598         _ER(EXTERNAL_INTERRUPT),
4599         _ER(TRIPLE_FAULT),
4600         _ER(PENDING_INTERRUPT),
4601         _ER(NMI_WINDOW),
4602         _ER(TASK_SWITCH),
4603         _ER(CPUID),
4604         _ER(HLT),
4605         _ER(INVLPG),
4606         _ER(RDPMC),
4607         _ER(RDTSC),
4608         _ER(VMCALL),
4609         _ER(VMCLEAR),
4610         _ER(VMLAUNCH),
4611         _ER(VMPTRLD),
4612         _ER(VMPTRST),
4613         _ER(VMREAD),
4614         _ER(VMRESUME),
4615         _ER(VMWRITE),
4616         _ER(VMOFF),
4617         _ER(VMON),
4618         _ER(CR_ACCESS),
4619         _ER(DR_ACCESS),
4620         _ER(IO_INSTRUCTION),
4621         _ER(MSR_READ),
4622         _ER(MSR_WRITE),
4623         _ER(MWAIT_INSTRUCTION),
4624         _ER(MONITOR_INSTRUCTION),
4625         _ER(PAUSE_INSTRUCTION),
4626         _ER(MCE_DURING_VMENTRY),
4627         _ER(TPR_BELOW_THRESHOLD),
4628         _ER(APIC_ACCESS),
4629         _ER(EPT_VIOLATION),
4630         _ER(EPT_MISCONFIG),
4631         _ER(WBINVD),
4632         { -1, NULL }
4633 };
4634
4635 #undef _ER
4636
4637 static int vmx_get_lpage_level(void)
4638 {
4639         if (enable_ept && !cpu_has_vmx_ept_1g_page())
4640                 return PT_DIRECTORY_LEVEL;
4641         else
4642                 /* For shadow and EPT supported 1GB page */
4643                 return PT_PDPE_LEVEL;
4644 }
4645
4646 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4647 {
4648         struct kvm_cpuid_entry2 *best;
4649         struct vcpu_vmx *vmx = to_vmx(vcpu);
4650         u32 exec_control;
4651
4652         vmx->rdtscp_enabled = false;
4653         if (vmx_rdtscp_supported()) {
4654                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4655                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4656                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4657                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4658                                 vmx->rdtscp_enabled = true;
4659                         else {
4660                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4661                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4662                                                 exec_control);
4663                         }
4664                 }
4665         }
4666 }
4667
4668 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4669 {
4670 }
4671
4672 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
4673                                struct x86_instruction_info *info,
4674                                enum x86_intercept_stage stage)
4675 {
4676         return X86EMUL_CONTINUE;
4677 }
4678
4679 static struct kvm_x86_ops vmx_x86_ops = {
4680         .cpu_has_kvm_support = cpu_has_kvm_support,
4681         .disabled_by_bios = vmx_disabled_by_bios,
4682         .hardware_setup = hardware_setup,
4683         .hardware_unsetup = hardware_unsetup,
4684         .check_processor_compatibility = vmx_check_processor_compat,
4685         .hardware_enable = hardware_enable,
4686         .hardware_disable = hardware_disable,
4687         .cpu_has_accelerated_tpr = report_flexpriority,
4688
4689         .vcpu_create = vmx_create_vcpu,
4690         .vcpu_free = vmx_free_vcpu,
4691         .vcpu_reset = vmx_vcpu_reset,
4692
4693         .prepare_guest_switch = vmx_save_host_state,
4694         .vcpu_load = vmx_vcpu_load,
4695         .vcpu_put = vmx_vcpu_put,
4696
4697         .set_guest_debug = set_guest_debug,
4698         .get_msr = vmx_get_msr,
4699         .set_msr = vmx_set_msr,
4700         .get_segment_base = vmx_get_segment_base,
4701         .get_segment = vmx_get_segment,
4702         .set_segment = vmx_set_segment,
4703         .get_cpl = vmx_get_cpl,
4704         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4705         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
4706         .decache_cr3 = vmx_decache_cr3,
4707         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4708         .set_cr0 = vmx_set_cr0,
4709         .set_cr3 = vmx_set_cr3,
4710         .set_cr4 = vmx_set_cr4,
4711         .set_efer = vmx_set_efer,
4712         .get_idt = vmx_get_idt,
4713         .set_idt = vmx_set_idt,
4714         .get_gdt = vmx_get_gdt,
4715         .set_gdt = vmx_set_gdt,
4716         .set_dr7 = vmx_set_dr7,
4717         .cache_reg = vmx_cache_reg,
4718         .get_rflags = vmx_get_rflags,
4719         .set_rflags = vmx_set_rflags,
4720         .fpu_activate = vmx_fpu_activate,
4721         .fpu_deactivate = vmx_fpu_deactivate,
4722
4723         .tlb_flush = vmx_flush_tlb,
4724
4725         .run = vmx_vcpu_run,
4726         .handle_exit = vmx_handle_exit,
4727         .skip_emulated_instruction = skip_emulated_instruction,
4728         .set_interrupt_shadow = vmx_set_interrupt_shadow,
4729         .get_interrupt_shadow = vmx_get_interrupt_shadow,
4730         .patch_hypercall = vmx_patch_hypercall,
4731         .set_irq = vmx_inject_irq,
4732         .set_nmi = vmx_inject_nmi,
4733         .queue_exception = vmx_queue_exception,
4734         .cancel_injection = vmx_cancel_injection,
4735         .interrupt_allowed = vmx_interrupt_allowed,
4736         .nmi_allowed = vmx_nmi_allowed,
4737         .get_nmi_mask = vmx_get_nmi_mask,
4738         .set_nmi_mask = vmx_set_nmi_mask,
4739         .enable_nmi_window = enable_nmi_window,
4740         .enable_irq_window = enable_irq_window,
4741         .update_cr8_intercept = update_cr8_intercept,
4742
4743         .set_tss_addr = vmx_set_tss_addr,
4744         .get_tdp_level = get_ept_level,
4745         .get_mt_mask = vmx_get_mt_mask,
4746
4747         .get_exit_info = vmx_get_exit_info,
4748         .exit_reasons_str = vmx_exit_reasons_str,
4749
4750         .get_lpage_level = vmx_get_lpage_level,
4751
4752         .cpuid_update = vmx_cpuid_update,
4753
4754         .rdtscp_supported = vmx_rdtscp_supported,
4755
4756         .set_supported_cpuid = vmx_set_supported_cpuid,
4757
4758         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
4759
4760         .set_tsc_khz = vmx_set_tsc_khz,
4761         .write_tsc_offset = vmx_write_tsc_offset,
4762         .adjust_tsc_offset = vmx_adjust_tsc_offset,
4763         .compute_tsc_offset = vmx_compute_tsc_offset,
4764
4765         .set_tdp_cr3 = vmx_set_cr3,
4766
4767         .check_intercept = vmx_check_intercept,
4768 };
4769
4770 static int __init vmx_init(void)
4771 {
4772         int r, i;
4773
4774         rdmsrl_safe(MSR_EFER, &host_efer);
4775
4776         for (i = 0; i < NR_VMX_MSR; ++i)
4777                 kvm_define_shared_msr(i, vmx_msr_index[i]);
4778
4779         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4780         if (!vmx_io_bitmap_a)
4781                 return -ENOMEM;
4782
4783         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4784         if (!vmx_io_bitmap_b) {
4785                 r = -ENOMEM;
4786                 goto out;
4787         }
4788
4789         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4790         if (!vmx_msr_bitmap_legacy) {
4791                 r = -ENOMEM;
4792                 goto out1;
4793         }
4794
4795         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4796         if (!vmx_msr_bitmap_longmode) {
4797                 r = -ENOMEM;
4798                 goto out2;
4799         }
4800
4801         /*
4802          * Allow direct access to the PC debug port (it is often used for I/O
4803          * delays, but the vmexits simply slow things down).
4804          */
4805         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4806         clear_bit(0x80, vmx_io_bitmap_a);
4807
4808         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4809
4810         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4811         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4812
4813         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4814
4815         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4816                      __alignof__(struct vcpu_vmx), THIS_MODULE);
4817         if (r)
4818                 goto out3;
4819
4820         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4821         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4822         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4823         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4824         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4825         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4826
4827         if (enable_ept) {
4828                 bypass_guest_pf = 0;
4829                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4830                                 VMX_EPT_EXECUTABLE_MASK);
4831                 kvm_enable_tdp();
4832         } else
4833                 kvm_disable_tdp();
4834
4835         if (bypass_guest_pf)
4836                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4837
4838         return 0;
4839
4840 out3:
4841         free_page((unsigned long)vmx_msr_bitmap_longmode);
4842 out2:
4843         free_page((unsigned long)vmx_msr_bitmap_legacy);
4844 out1:
4845         free_page((unsigned long)vmx_io_bitmap_b);
4846 out:
4847         free_page((unsigned long)vmx_io_bitmap_a);
4848         return r;
4849 }
4850
4851 static void __exit vmx_exit(void)
4852 {
4853         free_page((unsigned long)vmx_msr_bitmap_legacy);
4854         free_page((unsigned long)vmx_msr_bitmap_longmode);
4855         free_page((unsigned long)vmx_io_bitmap_b);
4856         free_page((unsigned long)vmx_io_bitmap_a);
4857
4858         kvm_exit();
4859 }
4860
4861 module_init(vmx_init)
4862 module_exit(vmx_exit)