263be2debde89eff09206e081c2b2eda6c28aa64
[linux-3.10.git] / arch / x86 / kvm / vmx.c
1 /*
2  * Kernel-based Virtual Machine driver for Linux
3  *
4  * This module enables machines with Intel VT-x extensions to run virtual
5  * machines without emulation or binary translation.
6  *
7  * Copyright (C) 2006 Qumranet, Inc.
8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
9  *
10  * Authors:
11  *   Avi Kivity   <avi@qumranet.com>
12  *   Yaniv Kamay  <yaniv@qumranet.com>
13  *
14  * This work is licensed under the terms of the GNU GPL, version 2.  See
15  * the COPYING file in the top-level directory.
16  *
17  */
18
19 #include "irq.h"
20 #include "mmu.h"
21
22 #include <linux/kvm_host.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/mm.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/moduleparam.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31 #include <linux/tboot.h>
32 #include "kvm_cache_regs.h"
33 #include "x86.h"
34
35 #include <asm/io.h>
36 #include <asm/desc.h>
37 #include <asm/vmx.h>
38 #include <asm/virtext.h>
39 #include <asm/mce.h>
40 #include <asm/i387.h>
41 #include <asm/xcr.h>
42
43 #include "trace.h"
44
45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
46 #define __ex_clear(x, reg) \
47         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
48
49 MODULE_AUTHOR("Qumranet");
50 MODULE_LICENSE("GPL");
51
52 static int __read_mostly bypass_guest_pf = 1;
53 module_param(bypass_guest_pf, bool, S_IRUGO);
54
55 static int __read_mostly enable_vpid = 1;
56 module_param_named(vpid, enable_vpid, bool, 0444);
57
58 static int __read_mostly flexpriority_enabled = 1;
59 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
60
61 static int __read_mostly enable_ept = 1;
62 module_param_named(ept, enable_ept, bool, S_IRUGO);
63
64 static int __read_mostly enable_unrestricted_guest = 1;
65 module_param_named(unrestricted_guest,
66                         enable_unrestricted_guest, bool, S_IRUGO);
67
68 static int __read_mostly emulate_invalid_guest_state = 0;
69 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
70
71 static int __read_mostly vmm_exclusive = 1;
72 module_param(vmm_exclusive, bool, S_IRUGO);
73
74 static int __read_mostly yield_on_hlt = 1;
75 module_param(yield_on_hlt, bool, S_IRUGO);
76
77 /*
78  * If nested=1, nested virtualization is supported, i.e., guests may use
79  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
80  * use VMX instructions.
81  */
82 static int __read_mostly nested = 0;
83 module_param(nested, bool, S_IRUGO);
84
85 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
86         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
87 #define KVM_GUEST_CR0_MASK                                              \
88         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
89 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
90         (X86_CR0_WP | X86_CR0_NE)
91 #define KVM_VM_CR0_ALWAYS_ON                                            \
92         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
93 #define KVM_CR4_GUEST_OWNED_BITS                                      \
94         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
95          | X86_CR4_OSXMMEXCPT)
96
97 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
98 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
99
100 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
101
102 /*
103  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
104  * ple_gap:    upper bound on the amount of time between two successive
105  *             executions of PAUSE in a loop. Also indicate if ple enabled.
106  *             According to test, this time is usually smaller than 128 cycles.
107  * ple_window: upper bound on the amount of time a guest is allowed to execute
108  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
109  *             less than 2^12 cycles
110  * Time is measured based on a counter that runs at the same rate as the TSC,
111  * refer SDM volume 3b section 21.6.13 & 22.1.3.
112  */
113 #define KVM_VMX_DEFAULT_PLE_GAP    128
114 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
115 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
116 module_param(ple_gap, int, S_IRUGO);
117
118 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
119 module_param(ple_window, int, S_IRUGO);
120
121 #define NR_AUTOLOAD_MSRS 1
122
123 struct vmcs {
124         u32 revision_id;
125         u32 abort;
126         char data[0];
127 };
128
129 /*
130  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
131  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
132  * loaded on this CPU (so we can clear them if the CPU goes down).
133  */
134 struct loaded_vmcs {
135         struct vmcs *vmcs;
136         int cpu;
137         int launched;
138         struct list_head loaded_vmcss_on_cpu_link;
139 };
140
141 struct shared_msr_entry {
142         unsigned index;
143         u64 data;
144         u64 mask;
145 };
146
147 struct vcpu_vmx {
148         struct kvm_vcpu       vcpu;
149         unsigned long         host_rsp;
150         u8                    fail;
151         u8                    cpl;
152         bool                  nmi_known_unmasked;
153         u32                   exit_intr_info;
154         u32                   idt_vectoring_info;
155         ulong                 rflags;
156         struct shared_msr_entry *guest_msrs;
157         int                   nmsrs;
158         int                   save_nmsrs;
159 #ifdef CONFIG_X86_64
160         u64                   msr_host_kernel_gs_base;
161         u64                   msr_guest_kernel_gs_base;
162 #endif
163         /*
164          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
165          * non-nested (L1) guest, it always points to vmcs01. For a nested
166          * guest (L2), it points to a different VMCS.
167          */
168         struct loaded_vmcs    vmcs01;
169         struct loaded_vmcs   *loaded_vmcs;
170         bool                  __launched; /* temporary, used in vmx_vcpu_run */
171         struct msr_autoload {
172                 unsigned nr;
173                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
174                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
175         } msr_autoload;
176         struct {
177                 int           loaded;
178                 u16           fs_sel, gs_sel, ldt_sel;
179                 int           gs_ldt_reload_needed;
180                 int           fs_reload_needed;
181         } host_state;
182         struct {
183                 int vm86_active;
184                 ulong save_rflags;
185                 struct kvm_save_segment {
186                         u16 selector;
187                         unsigned long base;
188                         u32 limit;
189                         u32 ar;
190                 } tr, es, ds, fs, gs;
191         } rmode;
192         struct {
193                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
194                 struct kvm_save_segment seg[8];
195         } segment_cache;
196         int vpid;
197         bool emulation_required;
198
199         /* Support for vnmi-less CPUs */
200         int soft_vnmi_blocked;
201         ktime_t entry_time;
202         s64 vnmi_blocked_time;
203         u32 exit_reason;
204
205         bool rdtscp_enabled;
206 };
207
208 enum segment_cache_field {
209         SEG_FIELD_SEL = 0,
210         SEG_FIELD_BASE = 1,
211         SEG_FIELD_LIMIT = 2,
212         SEG_FIELD_AR = 3,
213
214         SEG_FIELD_NR = 4
215 };
216
217 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
218 {
219         return container_of(vcpu, struct vcpu_vmx, vcpu);
220 }
221
222 static u64 construct_eptp(unsigned long root_hpa);
223 static void kvm_cpu_vmxon(u64 addr);
224 static void kvm_cpu_vmxoff(void);
225 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
226 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
227
228 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
229 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
230 /*
231  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
232  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
233  */
234 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
235 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
236
237 static unsigned long *vmx_io_bitmap_a;
238 static unsigned long *vmx_io_bitmap_b;
239 static unsigned long *vmx_msr_bitmap_legacy;
240 static unsigned long *vmx_msr_bitmap_longmode;
241
242 static bool cpu_has_load_ia32_efer;
243
244 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
245 static DEFINE_SPINLOCK(vmx_vpid_lock);
246
247 static struct vmcs_config {
248         int size;
249         int order;
250         u32 revision_id;
251         u32 pin_based_exec_ctrl;
252         u32 cpu_based_exec_ctrl;
253         u32 cpu_based_2nd_exec_ctrl;
254         u32 vmexit_ctrl;
255         u32 vmentry_ctrl;
256 } vmcs_config;
257
258 static struct vmx_capability {
259         u32 ept;
260         u32 vpid;
261 } vmx_capability;
262
263 #define VMX_SEGMENT_FIELD(seg)                                  \
264         [VCPU_SREG_##seg] = {                                   \
265                 .selector = GUEST_##seg##_SELECTOR,             \
266                 .base = GUEST_##seg##_BASE,                     \
267                 .limit = GUEST_##seg##_LIMIT,                   \
268                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
269         }
270
271 static struct kvm_vmx_segment_field {
272         unsigned selector;
273         unsigned base;
274         unsigned limit;
275         unsigned ar_bytes;
276 } kvm_vmx_segment_fields[] = {
277         VMX_SEGMENT_FIELD(CS),
278         VMX_SEGMENT_FIELD(DS),
279         VMX_SEGMENT_FIELD(ES),
280         VMX_SEGMENT_FIELD(FS),
281         VMX_SEGMENT_FIELD(GS),
282         VMX_SEGMENT_FIELD(SS),
283         VMX_SEGMENT_FIELD(TR),
284         VMX_SEGMENT_FIELD(LDTR),
285 };
286
287 static u64 host_efer;
288
289 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
290
291 /*
292  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
293  * away by decrementing the array size.
294  */
295 static const u32 vmx_msr_index[] = {
296 #ifdef CONFIG_X86_64
297         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
298 #endif
299         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
300 };
301 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
302
303 static inline bool is_page_fault(u32 intr_info)
304 {
305         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
306                              INTR_INFO_VALID_MASK)) ==
307                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
308 }
309
310 static inline bool is_no_device(u32 intr_info)
311 {
312         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
313                              INTR_INFO_VALID_MASK)) ==
314                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
315 }
316
317 static inline bool is_invalid_opcode(u32 intr_info)
318 {
319         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
320                              INTR_INFO_VALID_MASK)) ==
321                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
322 }
323
324 static inline bool is_external_interrupt(u32 intr_info)
325 {
326         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
327                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
328 }
329
330 static inline bool is_machine_check(u32 intr_info)
331 {
332         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
333                              INTR_INFO_VALID_MASK)) ==
334                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
335 }
336
337 static inline bool cpu_has_vmx_msr_bitmap(void)
338 {
339         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
340 }
341
342 static inline bool cpu_has_vmx_tpr_shadow(void)
343 {
344         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
345 }
346
347 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
348 {
349         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
350 }
351
352 static inline bool cpu_has_secondary_exec_ctrls(void)
353 {
354         return vmcs_config.cpu_based_exec_ctrl &
355                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
356 }
357
358 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
359 {
360         return vmcs_config.cpu_based_2nd_exec_ctrl &
361                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
362 }
363
364 static inline bool cpu_has_vmx_flexpriority(void)
365 {
366         return cpu_has_vmx_tpr_shadow() &&
367                 cpu_has_vmx_virtualize_apic_accesses();
368 }
369
370 static inline bool cpu_has_vmx_ept_execute_only(void)
371 {
372         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
373 }
374
375 static inline bool cpu_has_vmx_eptp_uncacheable(void)
376 {
377         return vmx_capability.ept & VMX_EPTP_UC_BIT;
378 }
379
380 static inline bool cpu_has_vmx_eptp_writeback(void)
381 {
382         return vmx_capability.ept & VMX_EPTP_WB_BIT;
383 }
384
385 static inline bool cpu_has_vmx_ept_2m_page(void)
386 {
387         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
388 }
389
390 static inline bool cpu_has_vmx_ept_1g_page(void)
391 {
392         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
393 }
394
395 static inline bool cpu_has_vmx_ept_4levels(void)
396 {
397         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
398 }
399
400 static inline bool cpu_has_vmx_invept_individual_addr(void)
401 {
402         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
403 }
404
405 static inline bool cpu_has_vmx_invept_context(void)
406 {
407         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
408 }
409
410 static inline bool cpu_has_vmx_invept_global(void)
411 {
412         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
413 }
414
415 static inline bool cpu_has_vmx_invvpid_single(void)
416 {
417         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
418 }
419
420 static inline bool cpu_has_vmx_invvpid_global(void)
421 {
422         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
423 }
424
425 static inline bool cpu_has_vmx_ept(void)
426 {
427         return vmcs_config.cpu_based_2nd_exec_ctrl &
428                 SECONDARY_EXEC_ENABLE_EPT;
429 }
430
431 static inline bool cpu_has_vmx_unrestricted_guest(void)
432 {
433         return vmcs_config.cpu_based_2nd_exec_ctrl &
434                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
435 }
436
437 static inline bool cpu_has_vmx_ple(void)
438 {
439         return vmcs_config.cpu_based_2nd_exec_ctrl &
440                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
441 }
442
443 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
444 {
445         return flexpriority_enabled && irqchip_in_kernel(kvm);
446 }
447
448 static inline bool cpu_has_vmx_vpid(void)
449 {
450         return vmcs_config.cpu_based_2nd_exec_ctrl &
451                 SECONDARY_EXEC_ENABLE_VPID;
452 }
453
454 static inline bool cpu_has_vmx_rdtscp(void)
455 {
456         return vmcs_config.cpu_based_2nd_exec_ctrl &
457                 SECONDARY_EXEC_RDTSCP;
458 }
459
460 static inline bool cpu_has_virtual_nmis(void)
461 {
462         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
463 }
464
465 static inline bool cpu_has_vmx_wbinvd_exit(void)
466 {
467         return vmcs_config.cpu_based_2nd_exec_ctrl &
468                 SECONDARY_EXEC_WBINVD_EXITING;
469 }
470
471 static inline bool report_flexpriority(void)
472 {
473         return flexpriority_enabled;
474 }
475
476 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
477 {
478         int i;
479
480         for (i = 0; i < vmx->nmsrs; ++i)
481                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
482                         return i;
483         return -1;
484 }
485
486 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
487 {
488     struct {
489         u64 vpid : 16;
490         u64 rsvd : 48;
491         u64 gva;
492     } operand = { vpid, 0, gva };
493
494     asm volatile (__ex(ASM_VMX_INVVPID)
495                   /* CF==1 or ZF==1 --> rc = -1 */
496                   "; ja 1f ; ud2 ; 1:"
497                   : : "a"(&operand), "c"(ext) : "cc", "memory");
498 }
499
500 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
501 {
502         struct {
503                 u64 eptp, gpa;
504         } operand = {eptp, gpa};
505
506         asm volatile (__ex(ASM_VMX_INVEPT)
507                         /* CF==1 or ZF==1 --> rc = -1 */
508                         "; ja 1f ; ud2 ; 1:\n"
509                         : : "a" (&operand), "c" (ext) : "cc", "memory");
510 }
511
512 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
513 {
514         int i;
515
516         i = __find_msr_index(vmx, msr);
517         if (i >= 0)
518                 return &vmx->guest_msrs[i];
519         return NULL;
520 }
521
522 static void vmcs_clear(struct vmcs *vmcs)
523 {
524         u64 phys_addr = __pa(vmcs);
525         u8 error;
526
527         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
528                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
529                       : "cc", "memory");
530         if (error)
531                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
532                        vmcs, phys_addr);
533 }
534
535 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
536 {
537         vmcs_clear(loaded_vmcs->vmcs);
538         loaded_vmcs->cpu = -1;
539         loaded_vmcs->launched = 0;
540 }
541
542 static void vmcs_load(struct vmcs *vmcs)
543 {
544         u64 phys_addr = __pa(vmcs);
545         u8 error;
546
547         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
548                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
549                         : "cc", "memory");
550         if (error)
551                 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
552                        vmcs, phys_addr);
553 }
554
555 static void __loaded_vmcs_clear(void *arg)
556 {
557         struct loaded_vmcs *loaded_vmcs = arg;
558         int cpu = raw_smp_processor_id();
559
560         if (loaded_vmcs->cpu != cpu)
561                 return; /* vcpu migration can race with cpu offline */
562         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
563                 per_cpu(current_vmcs, cpu) = NULL;
564         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
565         loaded_vmcs_init(loaded_vmcs);
566 }
567
568 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
569 {
570         if (loaded_vmcs->cpu != -1)
571                 smp_call_function_single(
572                         loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
573 }
574
575 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
576 {
577         if (vmx->vpid == 0)
578                 return;
579
580         if (cpu_has_vmx_invvpid_single())
581                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
582 }
583
584 static inline void vpid_sync_vcpu_global(void)
585 {
586         if (cpu_has_vmx_invvpid_global())
587                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
588 }
589
590 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
591 {
592         if (cpu_has_vmx_invvpid_single())
593                 vpid_sync_vcpu_single(vmx);
594         else
595                 vpid_sync_vcpu_global();
596 }
597
598 static inline void ept_sync_global(void)
599 {
600         if (cpu_has_vmx_invept_global())
601                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
602 }
603
604 static inline void ept_sync_context(u64 eptp)
605 {
606         if (enable_ept) {
607                 if (cpu_has_vmx_invept_context())
608                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
609                 else
610                         ept_sync_global();
611         }
612 }
613
614 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
615 {
616         if (enable_ept) {
617                 if (cpu_has_vmx_invept_individual_addr())
618                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
619                                         eptp, gpa);
620                 else
621                         ept_sync_context(eptp);
622         }
623 }
624
625 static __always_inline unsigned long vmcs_readl(unsigned long field)
626 {
627         unsigned long value;
628
629         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
630                       : "=a"(value) : "d"(field) : "cc");
631         return value;
632 }
633
634 static __always_inline u16 vmcs_read16(unsigned long field)
635 {
636         return vmcs_readl(field);
637 }
638
639 static __always_inline u32 vmcs_read32(unsigned long field)
640 {
641         return vmcs_readl(field);
642 }
643
644 static __always_inline u64 vmcs_read64(unsigned long field)
645 {
646 #ifdef CONFIG_X86_64
647         return vmcs_readl(field);
648 #else
649         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
650 #endif
651 }
652
653 static noinline void vmwrite_error(unsigned long field, unsigned long value)
654 {
655         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
656                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
657         dump_stack();
658 }
659
660 static void vmcs_writel(unsigned long field, unsigned long value)
661 {
662         u8 error;
663
664         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
665                        : "=q"(error) : "a"(value), "d"(field) : "cc");
666         if (unlikely(error))
667                 vmwrite_error(field, value);
668 }
669
670 static void vmcs_write16(unsigned long field, u16 value)
671 {
672         vmcs_writel(field, value);
673 }
674
675 static void vmcs_write32(unsigned long field, u32 value)
676 {
677         vmcs_writel(field, value);
678 }
679
680 static void vmcs_write64(unsigned long field, u64 value)
681 {
682         vmcs_writel(field, value);
683 #ifndef CONFIG_X86_64
684         asm volatile ("");
685         vmcs_writel(field+1, value >> 32);
686 #endif
687 }
688
689 static void vmcs_clear_bits(unsigned long field, u32 mask)
690 {
691         vmcs_writel(field, vmcs_readl(field) & ~mask);
692 }
693
694 static void vmcs_set_bits(unsigned long field, u32 mask)
695 {
696         vmcs_writel(field, vmcs_readl(field) | mask);
697 }
698
699 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
700 {
701         vmx->segment_cache.bitmask = 0;
702 }
703
704 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
705                                        unsigned field)
706 {
707         bool ret;
708         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
709
710         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
711                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
712                 vmx->segment_cache.bitmask = 0;
713         }
714         ret = vmx->segment_cache.bitmask & mask;
715         vmx->segment_cache.bitmask |= mask;
716         return ret;
717 }
718
719 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
720 {
721         u16 *p = &vmx->segment_cache.seg[seg].selector;
722
723         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
724                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
725         return *p;
726 }
727
728 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
729 {
730         ulong *p = &vmx->segment_cache.seg[seg].base;
731
732         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
733                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
734         return *p;
735 }
736
737 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
738 {
739         u32 *p = &vmx->segment_cache.seg[seg].limit;
740
741         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
742                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
743         return *p;
744 }
745
746 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
747 {
748         u32 *p = &vmx->segment_cache.seg[seg].ar;
749
750         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
751                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
752         return *p;
753 }
754
755 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
756 {
757         u32 eb;
758
759         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
760              (1u << NM_VECTOR) | (1u << DB_VECTOR);
761         if ((vcpu->guest_debug &
762              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
763             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
764                 eb |= 1u << BP_VECTOR;
765         if (to_vmx(vcpu)->rmode.vm86_active)
766                 eb = ~0;
767         if (enable_ept)
768                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
769         if (vcpu->fpu_active)
770                 eb &= ~(1u << NM_VECTOR);
771         vmcs_write32(EXCEPTION_BITMAP, eb);
772 }
773
774 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
775 {
776         unsigned i;
777         struct msr_autoload *m = &vmx->msr_autoload;
778
779         if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
780                 vmcs_clear_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
781                 vmcs_clear_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
782                 return;
783         }
784
785         for (i = 0; i < m->nr; ++i)
786                 if (m->guest[i].index == msr)
787                         break;
788
789         if (i == m->nr)
790                 return;
791         --m->nr;
792         m->guest[i] = m->guest[m->nr];
793         m->host[i] = m->host[m->nr];
794         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
795         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
796 }
797
798 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
799                                   u64 guest_val, u64 host_val)
800 {
801         unsigned i;
802         struct msr_autoload *m = &vmx->msr_autoload;
803
804         if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
805                 vmcs_write64(GUEST_IA32_EFER, guest_val);
806                 vmcs_write64(HOST_IA32_EFER, host_val);
807                 vmcs_set_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
808                 vmcs_set_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
809                 return;
810         }
811
812         for (i = 0; i < m->nr; ++i)
813                 if (m->guest[i].index == msr)
814                         break;
815
816         if (i == m->nr) {
817                 ++m->nr;
818                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
819                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
820         }
821
822         m->guest[i].index = msr;
823         m->guest[i].value = guest_val;
824         m->host[i].index = msr;
825         m->host[i].value = host_val;
826 }
827
828 static void reload_tss(void)
829 {
830         /*
831          * VT restores TR but not its size.  Useless.
832          */
833         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
834         struct desc_struct *descs;
835
836         descs = (void *)gdt->address;
837         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
838         load_TR_desc();
839 }
840
841 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
842 {
843         u64 guest_efer;
844         u64 ignore_bits;
845
846         guest_efer = vmx->vcpu.arch.efer;
847
848         /*
849          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
850          * outside long mode
851          */
852         ignore_bits = EFER_NX | EFER_SCE;
853 #ifdef CONFIG_X86_64
854         ignore_bits |= EFER_LMA | EFER_LME;
855         /* SCE is meaningful only in long mode on Intel */
856         if (guest_efer & EFER_LMA)
857                 ignore_bits &= ~(u64)EFER_SCE;
858 #endif
859         guest_efer &= ~ignore_bits;
860         guest_efer |= host_efer & ignore_bits;
861         vmx->guest_msrs[efer_offset].data = guest_efer;
862         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
863
864         clear_atomic_switch_msr(vmx, MSR_EFER);
865         /* On ept, can't emulate nx, and must switch nx atomically */
866         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
867                 guest_efer = vmx->vcpu.arch.efer;
868                 if (!(guest_efer & EFER_LMA))
869                         guest_efer &= ~EFER_LME;
870                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
871                 return false;
872         }
873
874         return true;
875 }
876
877 static unsigned long segment_base(u16 selector)
878 {
879         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
880         struct desc_struct *d;
881         unsigned long table_base;
882         unsigned long v;
883
884         if (!(selector & ~3))
885                 return 0;
886
887         table_base = gdt->address;
888
889         if (selector & 4) {           /* from ldt */
890                 u16 ldt_selector = kvm_read_ldt();
891
892                 if (!(ldt_selector & ~3))
893                         return 0;
894
895                 table_base = segment_base(ldt_selector);
896         }
897         d = (struct desc_struct *)(table_base + (selector & ~7));
898         v = get_desc_base(d);
899 #ifdef CONFIG_X86_64
900        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
901                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
902 #endif
903         return v;
904 }
905
906 static inline unsigned long kvm_read_tr_base(void)
907 {
908         u16 tr;
909         asm("str %0" : "=g"(tr));
910         return segment_base(tr);
911 }
912
913 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
914 {
915         struct vcpu_vmx *vmx = to_vmx(vcpu);
916         int i;
917
918         if (vmx->host_state.loaded)
919                 return;
920
921         vmx->host_state.loaded = 1;
922         /*
923          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
924          * allow segment selectors with cpl > 0 or ti == 1.
925          */
926         vmx->host_state.ldt_sel = kvm_read_ldt();
927         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
928         savesegment(fs, vmx->host_state.fs_sel);
929         if (!(vmx->host_state.fs_sel & 7)) {
930                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
931                 vmx->host_state.fs_reload_needed = 0;
932         } else {
933                 vmcs_write16(HOST_FS_SELECTOR, 0);
934                 vmx->host_state.fs_reload_needed = 1;
935         }
936         savesegment(gs, vmx->host_state.gs_sel);
937         if (!(vmx->host_state.gs_sel & 7))
938                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
939         else {
940                 vmcs_write16(HOST_GS_SELECTOR, 0);
941                 vmx->host_state.gs_ldt_reload_needed = 1;
942         }
943
944 #ifdef CONFIG_X86_64
945         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
946         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
947 #else
948         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
949         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
950 #endif
951
952 #ifdef CONFIG_X86_64
953         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
954         if (is_long_mode(&vmx->vcpu))
955                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
956 #endif
957         for (i = 0; i < vmx->save_nmsrs; ++i)
958                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
959                                    vmx->guest_msrs[i].data,
960                                    vmx->guest_msrs[i].mask);
961 }
962
963 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
964 {
965         if (!vmx->host_state.loaded)
966                 return;
967
968         ++vmx->vcpu.stat.host_state_reload;
969         vmx->host_state.loaded = 0;
970 #ifdef CONFIG_X86_64
971         if (is_long_mode(&vmx->vcpu))
972                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
973 #endif
974         if (vmx->host_state.gs_ldt_reload_needed) {
975                 kvm_load_ldt(vmx->host_state.ldt_sel);
976 #ifdef CONFIG_X86_64
977                 load_gs_index(vmx->host_state.gs_sel);
978 #else
979                 loadsegment(gs, vmx->host_state.gs_sel);
980 #endif
981         }
982         if (vmx->host_state.fs_reload_needed)
983                 loadsegment(fs, vmx->host_state.fs_sel);
984         reload_tss();
985 #ifdef CONFIG_X86_64
986         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
987 #endif
988         if (current_thread_info()->status & TS_USEDFPU)
989                 clts();
990         load_gdt(&__get_cpu_var(host_gdt));
991 }
992
993 static void vmx_load_host_state(struct vcpu_vmx *vmx)
994 {
995         preempt_disable();
996         __vmx_load_host_state(vmx);
997         preempt_enable();
998 }
999
1000 /*
1001  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1002  * vcpu mutex is already taken.
1003  */
1004 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1005 {
1006         struct vcpu_vmx *vmx = to_vmx(vcpu);
1007         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1008
1009         if (!vmm_exclusive)
1010                 kvm_cpu_vmxon(phys_addr);
1011         else if (vmx->loaded_vmcs->cpu != cpu)
1012                 loaded_vmcs_clear(vmx->loaded_vmcs);
1013
1014         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1015                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1016                 vmcs_load(vmx->loaded_vmcs->vmcs);
1017         }
1018
1019         if (vmx->loaded_vmcs->cpu != cpu) {
1020                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1021                 unsigned long sysenter_esp;
1022
1023                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1024                 local_irq_disable();
1025                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1026                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1027                 local_irq_enable();
1028
1029                 /*
1030                  * Linux uses per-cpu TSS and GDT, so set these when switching
1031                  * processors.
1032                  */
1033                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1034                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1035
1036                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1037                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1038                 vmx->loaded_vmcs->cpu = cpu;
1039         }
1040 }
1041
1042 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1043 {
1044         __vmx_load_host_state(to_vmx(vcpu));
1045         if (!vmm_exclusive) {
1046                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1047                 vcpu->cpu = -1;
1048                 kvm_cpu_vmxoff();
1049         }
1050 }
1051
1052 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1053 {
1054         ulong cr0;
1055
1056         if (vcpu->fpu_active)
1057                 return;
1058         vcpu->fpu_active = 1;
1059         cr0 = vmcs_readl(GUEST_CR0);
1060         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1061         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1062         vmcs_writel(GUEST_CR0, cr0);
1063         update_exception_bitmap(vcpu);
1064         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1065         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1066 }
1067
1068 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1069
1070 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1071 {
1072         vmx_decache_cr0_guest_bits(vcpu);
1073         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1074         update_exception_bitmap(vcpu);
1075         vcpu->arch.cr0_guest_owned_bits = 0;
1076         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1077         vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1078 }
1079
1080 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1081 {
1082         unsigned long rflags, save_rflags;
1083
1084         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1085                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1086                 rflags = vmcs_readl(GUEST_RFLAGS);
1087                 if (to_vmx(vcpu)->rmode.vm86_active) {
1088                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1089                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1090                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1091                 }
1092                 to_vmx(vcpu)->rflags = rflags;
1093         }
1094         return to_vmx(vcpu)->rflags;
1095 }
1096
1097 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1098 {
1099         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1100         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
1101         to_vmx(vcpu)->rflags = rflags;
1102         if (to_vmx(vcpu)->rmode.vm86_active) {
1103                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1104                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1105         }
1106         vmcs_writel(GUEST_RFLAGS, rflags);
1107 }
1108
1109 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1110 {
1111         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1112         int ret = 0;
1113
1114         if (interruptibility & GUEST_INTR_STATE_STI)
1115                 ret |= KVM_X86_SHADOW_INT_STI;
1116         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1117                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1118
1119         return ret & mask;
1120 }
1121
1122 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1123 {
1124         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1125         u32 interruptibility = interruptibility_old;
1126
1127         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1128
1129         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1130                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1131         else if (mask & KVM_X86_SHADOW_INT_STI)
1132                 interruptibility |= GUEST_INTR_STATE_STI;
1133
1134         if ((interruptibility != interruptibility_old))
1135                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1136 }
1137
1138 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1139 {
1140         unsigned long rip;
1141
1142         rip = kvm_rip_read(vcpu);
1143         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1144         kvm_rip_write(vcpu, rip);
1145
1146         /* skipping an emulated instruction also counts */
1147         vmx_set_interrupt_shadow(vcpu, 0);
1148 }
1149
1150 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1151 {
1152         /* Ensure that we clear the HLT state in the VMCS.  We don't need to
1153          * explicitly skip the instruction because if the HLT state is set, then
1154          * the instruction is already executing and RIP has already been
1155          * advanced. */
1156         if (!yield_on_hlt &&
1157             vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1158                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1159 }
1160
1161 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1162                                 bool has_error_code, u32 error_code,
1163                                 bool reinject)
1164 {
1165         struct vcpu_vmx *vmx = to_vmx(vcpu);
1166         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1167
1168         if (has_error_code) {
1169                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1170                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1171         }
1172
1173         if (vmx->rmode.vm86_active) {
1174                 int inc_eip = 0;
1175                 if (kvm_exception_is_soft(nr))
1176                         inc_eip = vcpu->arch.event_exit_inst_len;
1177                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1178                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1179                 return;
1180         }
1181
1182         if (kvm_exception_is_soft(nr)) {
1183                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1184                              vmx->vcpu.arch.event_exit_inst_len);
1185                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1186         } else
1187                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1188
1189         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1190         vmx_clear_hlt(vcpu);
1191 }
1192
1193 static bool vmx_rdtscp_supported(void)
1194 {
1195         return cpu_has_vmx_rdtscp();
1196 }
1197
1198 /*
1199  * Swap MSR entry in host/guest MSR entry array.
1200  */
1201 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1202 {
1203         struct shared_msr_entry tmp;
1204
1205         tmp = vmx->guest_msrs[to];
1206         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1207         vmx->guest_msrs[from] = tmp;
1208 }
1209
1210 /*
1211  * Set up the vmcs to automatically save and restore system
1212  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1213  * mode, as fiddling with msrs is very expensive.
1214  */
1215 static void setup_msrs(struct vcpu_vmx *vmx)
1216 {
1217         int save_nmsrs, index;
1218         unsigned long *msr_bitmap;
1219
1220         vmx_load_host_state(vmx);
1221         save_nmsrs = 0;
1222 #ifdef CONFIG_X86_64
1223         if (is_long_mode(&vmx->vcpu)) {
1224                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1225                 if (index >= 0)
1226                         move_msr_up(vmx, index, save_nmsrs++);
1227                 index = __find_msr_index(vmx, MSR_LSTAR);
1228                 if (index >= 0)
1229                         move_msr_up(vmx, index, save_nmsrs++);
1230                 index = __find_msr_index(vmx, MSR_CSTAR);
1231                 if (index >= 0)
1232                         move_msr_up(vmx, index, save_nmsrs++);
1233                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1234                 if (index >= 0 && vmx->rdtscp_enabled)
1235                         move_msr_up(vmx, index, save_nmsrs++);
1236                 /*
1237                  * MSR_STAR is only needed on long mode guests, and only
1238                  * if efer.sce is enabled.
1239                  */
1240                 index = __find_msr_index(vmx, MSR_STAR);
1241                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1242                         move_msr_up(vmx, index, save_nmsrs++);
1243         }
1244 #endif
1245         index = __find_msr_index(vmx, MSR_EFER);
1246         if (index >= 0 && update_transition_efer(vmx, index))
1247                 move_msr_up(vmx, index, save_nmsrs++);
1248
1249         vmx->save_nmsrs = save_nmsrs;
1250
1251         if (cpu_has_vmx_msr_bitmap()) {
1252                 if (is_long_mode(&vmx->vcpu))
1253                         msr_bitmap = vmx_msr_bitmap_longmode;
1254                 else
1255                         msr_bitmap = vmx_msr_bitmap_legacy;
1256
1257                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1258         }
1259 }
1260
1261 /*
1262  * reads and returns guest's timestamp counter "register"
1263  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1264  */
1265 static u64 guest_read_tsc(void)
1266 {
1267         u64 host_tsc, tsc_offset;
1268
1269         rdtscll(host_tsc);
1270         tsc_offset = vmcs_read64(TSC_OFFSET);
1271         return host_tsc + tsc_offset;
1272 }
1273
1274 /*
1275  * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ
1276  * ioctl. In this case the call-back should update internal vmx state to make
1277  * the changes effective.
1278  */
1279 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1280 {
1281         /* Nothing to do here */
1282 }
1283
1284 /*
1285  * writes 'offset' into guest's timestamp counter offset register
1286  */
1287 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1288 {
1289         vmcs_write64(TSC_OFFSET, offset);
1290 }
1291
1292 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1293 {
1294         u64 offset = vmcs_read64(TSC_OFFSET);
1295         vmcs_write64(TSC_OFFSET, offset + adjustment);
1296 }
1297
1298 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1299 {
1300         return target_tsc - native_read_tsc();
1301 }
1302
1303 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1304 {
1305         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1306         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1307 }
1308
1309 /*
1310  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1311  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1312  * all guests if the "nested" module option is off, and can also be disabled
1313  * for a single guest by disabling its VMX cpuid bit.
1314  */
1315 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1316 {
1317         return nested && guest_cpuid_has_vmx(vcpu);
1318 }
1319
1320 /*
1321  * Reads an msr value (of 'msr_index') into 'pdata'.
1322  * Returns 0 on success, non-0 otherwise.
1323  * Assumes vcpu_load() was already called.
1324  */
1325 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1326 {
1327         u64 data;
1328         struct shared_msr_entry *msr;
1329
1330         if (!pdata) {
1331                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1332                 return -EINVAL;
1333         }
1334
1335         switch (msr_index) {
1336 #ifdef CONFIG_X86_64
1337         case MSR_FS_BASE:
1338                 data = vmcs_readl(GUEST_FS_BASE);
1339                 break;
1340         case MSR_GS_BASE:
1341                 data = vmcs_readl(GUEST_GS_BASE);
1342                 break;
1343         case MSR_KERNEL_GS_BASE:
1344                 vmx_load_host_state(to_vmx(vcpu));
1345                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1346                 break;
1347 #endif
1348         case MSR_EFER:
1349                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1350         case MSR_IA32_TSC:
1351                 data = guest_read_tsc();
1352                 break;
1353         case MSR_IA32_SYSENTER_CS:
1354                 data = vmcs_read32(GUEST_SYSENTER_CS);
1355                 break;
1356         case MSR_IA32_SYSENTER_EIP:
1357                 data = vmcs_readl(GUEST_SYSENTER_EIP);
1358                 break;
1359         case MSR_IA32_SYSENTER_ESP:
1360                 data = vmcs_readl(GUEST_SYSENTER_ESP);
1361                 break;
1362         case MSR_TSC_AUX:
1363                 if (!to_vmx(vcpu)->rdtscp_enabled)
1364                         return 1;
1365                 /* Otherwise falls through */
1366         default:
1367                 vmx_load_host_state(to_vmx(vcpu));
1368                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1369                 if (msr) {
1370                         vmx_load_host_state(to_vmx(vcpu));
1371                         data = msr->data;
1372                         break;
1373                 }
1374                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1375         }
1376
1377         *pdata = data;
1378         return 0;
1379 }
1380
1381 /*
1382  * Writes msr value into into the appropriate "register".
1383  * Returns 0 on success, non-0 otherwise.
1384  * Assumes vcpu_load() was already called.
1385  */
1386 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1387 {
1388         struct vcpu_vmx *vmx = to_vmx(vcpu);
1389         struct shared_msr_entry *msr;
1390         int ret = 0;
1391
1392         switch (msr_index) {
1393         case MSR_EFER:
1394                 vmx_load_host_state(vmx);
1395                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1396                 break;
1397 #ifdef CONFIG_X86_64
1398         case MSR_FS_BASE:
1399                 vmx_segment_cache_clear(vmx);
1400                 vmcs_writel(GUEST_FS_BASE, data);
1401                 break;
1402         case MSR_GS_BASE:
1403                 vmx_segment_cache_clear(vmx);
1404                 vmcs_writel(GUEST_GS_BASE, data);
1405                 break;
1406         case MSR_KERNEL_GS_BASE:
1407                 vmx_load_host_state(vmx);
1408                 vmx->msr_guest_kernel_gs_base = data;
1409                 break;
1410 #endif
1411         case MSR_IA32_SYSENTER_CS:
1412                 vmcs_write32(GUEST_SYSENTER_CS, data);
1413                 break;
1414         case MSR_IA32_SYSENTER_EIP:
1415                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1416                 break;
1417         case MSR_IA32_SYSENTER_ESP:
1418                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1419                 break;
1420         case MSR_IA32_TSC:
1421                 kvm_write_tsc(vcpu, data);
1422                 break;
1423         case MSR_IA32_CR_PAT:
1424                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1425                         vmcs_write64(GUEST_IA32_PAT, data);
1426                         vcpu->arch.pat = data;
1427                         break;
1428                 }
1429                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1430                 break;
1431         case MSR_TSC_AUX:
1432                 if (!vmx->rdtscp_enabled)
1433                         return 1;
1434                 /* Check reserved bit, higher 32 bits should be zero */
1435                 if ((data >> 32) != 0)
1436                         return 1;
1437                 /* Otherwise falls through */
1438         default:
1439                 msr = find_msr_entry(vmx, msr_index);
1440                 if (msr) {
1441                         vmx_load_host_state(vmx);
1442                         msr->data = data;
1443                         break;
1444                 }
1445                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1446         }
1447
1448         return ret;
1449 }
1450
1451 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1452 {
1453         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1454         switch (reg) {
1455         case VCPU_REGS_RSP:
1456                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1457                 break;
1458         case VCPU_REGS_RIP:
1459                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1460                 break;
1461         case VCPU_EXREG_PDPTR:
1462                 if (enable_ept)
1463                         ept_save_pdptrs(vcpu);
1464                 break;
1465         default:
1466                 break;
1467         }
1468 }
1469
1470 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1471 {
1472         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1473                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1474         else
1475                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1476
1477         update_exception_bitmap(vcpu);
1478 }
1479
1480 static __init int cpu_has_kvm_support(void)
1481 {
1482         return cpu_has_vmx();
1483 }
1484
1485 static __init int vmx_disabled_by_bios(void)
1486 {
1487         u64 msr;
1488
1489         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1490         if (msr & FEATURE_CONTROL_LOCKED) {
1491                 /* launched w/ TXT and VMX disabled */
1492                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1493                         && tboot_enabled())
1494                         return 1;
1495                 /* launched w/o TXT and VMX only enabled w/ TXT */
1496                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1497                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1498                         && !tboot_enabled()) {
1499                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
1500                                 "activate TXT before enabling KVM\n");
1501                         return 1;
1502                 }
1503                 /* launched w/o TXT and VMX disabled */
1504                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1505                         && !tboot_enabled())
1506                         return 1;
1507         }
1508
1509         return 0;
1510 }
1511
1512 static void kvm_cpu_vmxon(u64 addr)
1513 {
1514         asm volatile (ASM_VMX_VMXON_RAX
1515                         : : "a"(&addr), "m"(addr)
1516                         : "memory", "cc");
1517 }
1518
1519 static int hardware_enable(void *garbage)
1520 {
1521         int cpu = raw_smp_processor_id();
1522         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1523         u64 old, test_bits;
1524
1525         if (read_cr4() & X86_CR4_VMXE)
1526                 return -EBUSY;
1527
1528         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
1529         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1530
1531         test_bits = FEATURE_CONTROL_LOCKED;
1532         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1533         if (tboot_enabled())
1534                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1535
1536         if ((old & test_bits) != test_bits) {
1537                 /* enable and lock */
1538                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1539         }
1540         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1541
1542         if (vmm_exclusive) {
1543                 kvm_cpu_vmxon(phys_addr);
1544                 ept_sync_global();
1545         }
1546
1547         store_gdt(&__get_cpu_var(host_gdt));
1548
1549         return 0;
1550 }
1551
1552 static void vmclear_local_loaded_vmcss(void)
1553 {
1554         int cpu = raw_smp_processor_id();
1555         struct loaded_vmcs *v, *n;
1556
1557         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
1558                                  loaded_vmcss_on_cpu_link)
1559                 __loaded_vmcs_clear(v);
1560 }
1561
1562
1563 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1564  * tricks.
1565  */
1566 static void kvm_cpu_vmxoff(void)
1567 {
1568         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1569 }
1570
1571 static void hardware_disable(void *garbage)
1572 {
1573         if (vmm_exclusive) {
1574                 vmclear_local_loaded_vmcss();
1575                 kvm_cpu_vmxoff();
1576         }
1577         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1578 }
1579
1580 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1581                                       u32 msr, u32 *result)
1582 {
1583         u32 vmx_msr_low, vmx_msr_high;
1584         u32 ctl = ctl_min | ctl_opt;
1585
1586         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1587
1588         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1589         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1590
1591         /* Ensure minimum (required) set of control bits are supported. */
1592         if (ctl_min & ~ctl)
1593                 return -EIO;
1594
1595         *result = ctl;
1596         return 0;
1597 }
1598
1599 static __init bool allow_1_setting(u32 msr, u32 ctl)
1600 {
1601         u32 vmx_msr_low, vmx_msr_high;
1602
1603         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1604         return vmx_msr_high & ctl;
1605 }
1606
1607 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1608 {
1609         u32 vmx_msr_low, vmx_msr_high;
1610         u32 min, opt, min2, opt2;
1611         u32 _pin_based_exec_control = 0;
1612         u32 _cpu_based_exec_control = 0;
1613         u32 _cpu_based_2nd_exec_control = 0;
1614         u32 _vmexit_control = 0;
1615         u32 _vmentry_control = 0;
1616
1617         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1618         opt = PIN_BASED_VIRTUAL_NMIS;
1619         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1620                                 &_pin_based_exec_control) < 0)
1621                 return -EIO;
1622
1623         min =
1624 #ifdef CONFIG_X86_64
1625               CPU_BASED_CR8_LOAD_EXITING |
1626               CPU_BASED_CR8_STORE_EXITING |
1627 #endif
1628               CPU_BASED_CR3_LOAD_EXITING |
1629               CPU_BASED_CR3_STORE_EXITING |
1630               CPU_BASED_USE_IO_BITMAPS |
1631               CPU_BASED_MOV_DR_EXITING |
1632               CPU_BASED_USE_TSC_OFFSETING |
1633               CPU_BASED_MWAIT_EXITING |
1634               CPU_BASED_MONITOR_EXITING |
1635               CPU_BASED_INVLPG_EXITING;
1636
1637         if (yield_on_hlt)
1638                 min |= CPU_BASED_HLT_EXITING;
1639
1640         opt = CPU_BASED_TPR_SHADOW |
1641               CPU_BASED_USE_MSR_BITMAPS |
1642               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1643         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1644                                 &_cpu_based_exec_control) < 0)
1645                 return -EIO;
1646 #ifdef CONFIG_X86_64
1647         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1648                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1649                                            ~CPU_BASED_CR8_STORE_EXITING;
1650 #endif
1651         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1652                 min2 = 0;
1653                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1654                         SECONDARY_EXEC_WBINVD_EXITING |
1655                         SECONDARY_EXEC_ENABLE_VPID |
1656                         SECONDARY_EXEC_ENABLE_EPT |
1657                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
1658                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1659                         SECONDARY_EXEC_RDTSCP;
1660                 if (adjust_vmx_controls(min2, opt2,
1661                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1662                                         &_cpu_based_2nd_exec_control) < 0)
1663                         return -EIO;
1664         }
1665 #ifndef CONFIG_X86_64
1666         if (!(_cpu_based_2nd_exec_control &
1667                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1668                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1669 #endif
1670         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1671                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1672                    enabled */
1673                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1674                                              CPU_BASED_CR3_STORE_EXITING |
1675                                              CPU_BASED_INVLPG_EXITING);
1676                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1677                       vmx_capability.ept, vmx_capability.vpid);
1678         }
1679
1680         min = 0;
1681 #ifdef CONFIG_X86_64
1682         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1683 #endif
1684         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1685         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1686                                 &_vmexit_control) < 0)
1687                 return -EIO;
1688
1689         min = 0;
1690         opt = VM_ENTRY_LOAD_IA32_PAT;
1691         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1692                                 &_vmentry_control) < 0)
1693                 return -EIO;
1694
1695         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1696
1697         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1698         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1699                 return -EIO;
1700
1701 #ifdef CONFIG_X86_64
1702         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1703         if (vmx_msr_high & (1u<<16))
1704                 return -EIO;
1705 #endif
1706
1707         /* Require Write-Back (WB) memory type for VMCS accesses. */
1708         if (((vmx_msr_high >> 18) & 15) != 6)
1709                 return -EIO;
1710
1711         vmcs_conf->size = vmx_msr_high & 0x1fff;
1712         vmcs_conf->order = get_order(vmcs_config.size);
1713         vmcs_conf->revision_id = vmx_msr_low;
1714
1715         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1716         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1717         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1718         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1719         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1720
1721         cpu_has_load_ia32_efer =
1722                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
1723                                 VM_ENTRY_LOAD_IA32_EFER)
1724                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
1725                                    VM_EXIT_LOAD_IA32_EFER);
1726
1727         return 0;
1728 }
1729
1730 static struct vmcs *alloc_vmcs_cpu(int cpu)
1731 {
1732         int node = cpu_to_node(cpu);
1733         struct page *pages;
1734         struct vmcs *vmcs;
1735
1736         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1737         if (!pages)
1738                 return NULL;
1739         vmcs = page_address(pages);
1740         memset(vmcs, 0, vmcs_config.size);
1741         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1742         return vmcs;
1743 }
1744
1745 static struct vmcs *alloc_vmcs(void)
1746 {
1747         return alloc_vmcs_cpu(raw_smp_processor_id());
1748 }
1749
1750 static void free_vmcs(struct vmcs *vmcs)
1751 {
1752         free_pages((unsigned long)vmcs, vmcs_config.order);
1753 }
1754
1755 /*
1756  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
1757  */
1758 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
1759 {
1760         if (!loaded_vmcs->vmcs)
1761                 return;
1762         loaded_vmcs_clear(loaded_vmcs);
1763         free_vmcs(loaded_vmcs->vmcs);
1764         loaded_vmcs->vmcs = NULL;
1765 }
1766
1767 static void free_kvm_area(void)
1768 {
1769         int cpu;
1770
1771         for_each_possible_cpu(cpu) {
1772                 free_vmcs(per_cpu(vmxarea, cpu));
1773                 per_cpu(vmxarea, cpu) = NULL;
1774         }
1775 }
1776
1777 static __init int alloc_kvm_area(void)
1778 {
1779         int cpu;
1780
1781         for_each_possible_cpu(cpu) {
1782                 struct vmcs *vmcs;
1783
1784                 vmcs = alloc_vmcs_cpu(cpu);
1785                 if (!vmcs) {
1786                         free_kvm_area();
1787                         return -ENOMEM;
1788                 }
1789
1790                 per_cpu(vmxarea, cpu) = vmcs;
1791         }
1792         return 0;
1793 }
1794
1795 static __init int hardware_setup(void)
1796 {
1797         if (setup_vmcs_config(&vmcs_config) < 0)
1798                 return -EIO;
1799
1800         if (boot_cpu_has(X86_FEATURE_NX))
1801                 kvm_enable_efer_bits(EFER_NX);
1802
1803         if (!cpu_has_vmx_vpid())
1804                 enable_vpid = 0;
1805
1806         if (!cpu_has_vmx_ept() ||
1807             !cpu_has_vmx_ept_4levels()) {
1808                 enable_ept = 0;
1809                 enable_unrestricted_guest = 0;
1810         }
1811
1812         if (!cpu_has_vmx_unrestricted_guest())
1813                 enable_unrestricted_guest = 0;
1814
1815         if (!cpu_has_vmx_flexpriority())
1816                 flexpriority_enabled = 0;
1817
1818         if (!cpu_has_vmx_tpr_shadow())
1819                 kvm_x86_ops->update_cr8_intercept = NULL;
1820
1821         if (enable_ept && !cpu_has_vmx_ept_2m_page())
1822                 kvm_disable_largepages();
1823
1824         if (!cpu_has_vmx_ple())
1825                 ple_gap = 0;
1826
1827         return alloc_kvm_area();
1828 }
1829
1830 static __exit void hardware_unsetup(void)
1831 {
1832         free_kvm_area();
1833 }
1834
1835 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1836 {
1837         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1838
1839         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1840                 vmcs_write16(sf->selector, save->selector);
1841                 vmcs_writel(sf->base, save->base);
1842                 vmcs_write32(sf->limit, save->limit);
1843                 vmcs_write32(sf->ar_bytes, save->ar);
1844         } else {
1845                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1846                         << AR_DPL_SHIFT;
1847                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1848         }
1849 }
1850
1851 static void enter_pmode(struct kvm_vcpu *vcpu)
1852 {
1853         unsigned long flags;
1854         struct vcpu_vmx *vmx = to_vmx(vcpu);
1855
1856         vmx->emulation_required = 1;
1857         vmx->rmode.vm86_active = 0;
1858
1859         vmx_segment_cache_clear(vmx);
1860
1861         vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
1862         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1863         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1864         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1865
1866         flags = vmcs_readl(GUEST_RFLAGS);
1867         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1868         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1869         vmcs_writel(GUEST_RFLAGS, flags);
1870
1871         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1872                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1873
1874         update_exception_bitmap(vcpu);
1875
1876         if (emulate_invalid_guest_state)
1877                 return;
1878
1879         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1880         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1881         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1882         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1883
1884         vmx_segment_cache_clear(vmx);
1885
1886         vmcs_write16(GUEST_SS_SELECTOR, 0);
1887         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1888
1889         vmcs_write16(GUEST_CS_SELECTOR,
1890                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1891         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1892 }
1893
1894 static gva_t rmode_tss_base(struct kvm *kvm)
1895 {
1896         if (!kvm->arch.tss_addr) {
1897                 struct kvm_memslots *slots;
1898                 gfn_t base_gfn;
1899
1900                 slots = kvm_memslots(kvm);
1901                 base_gfn = slots->memslots[0].base_gfn +
1902                                  kvm->memslots->memslots[0].npages - 3;
1903                 return base_gfn << PAGE_SHIFT;
1904         }
1905         return kvm->arch.tss_addr;
1906 }
1907
1908 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1909 {
1910         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1911
1912         save->selector = vmcs_read16(sf->selector);
1913         save->base = vmcs_readl(sf->base);
1914         save->limit = vmcs_read32(sf->limit);
1915         save->ar = vmcs_read32(sf->ar_bytes);
1916         vmcs_write16(sf->selector, save->base >> 4);
1917         vmcs_write32(sf->base, save->base & 0xffff0);
1918         vmcs_write32(sf->limit, 0xffff);
1919         vmcs_write32(sf->ar_bytes, 0xf3);
1920         if (save->base & 0xf)
1921                 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
1922                             " aligned when entering protected mode (seg=%d)",
1923                             seg);
1924 }
1925
1926 static void enter_rmode(struct kvm_vcpu *vcpu)
1927 {
1928         unsigned long flags;
1929         struct vcpu_vmx *vmx = to_vmx(vcpu);
1930
1931         if (enable_unrestricted_guest)
1932                 return;
1933
1934         vmx->emulation_required = 1;
1935         vmx->rmode.vm86_active = 1;
1936
1937         /*
1938          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
1939          * vcpu. Call it here with phys address pointing 16M below 4G.
1940          */
1941         if (!vcpu->kvm->arch.tss_addr) {
1942                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
1943                              "called before entering vcpu\n");
1944                 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
1945                 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
1946                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
1947         }
1948
1949         vmx_segment_cache_clear(vmx);
1950
1951         vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
1952         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1953         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1954
1955         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1956         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1957
1958         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1959         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1960
1961         flags = vmcs_readl(GUEST_RFLAGS);
1962         vmx->rmode.save_rflags = flags;
1963
1964         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1965
1966         vmcs_writel(GUEST_RFLAGS, flags);
1967         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1968         update_exception_bitmap(vcpu);
1969
1970         if (emulate_invalid_guest_state)
1971                 goto continue_rmode;
1972
1973         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1974         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1975         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1976
1977         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1978         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1979         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1980                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1981         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1982
1983         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1984         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1985         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1986         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1987
1988 continue_rmode:
1989         kvm_mmu_reset_context(vcpu);
1990 }
1991
1992 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1993 {
1994         struct vcpu_vmx *vmx = to_vmx(vcpu);
1995         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1996
1997         if (!msr)
1998                 return;
1999
2000         /*
2001          * Force kernel_gs_base reloading before EFER changes, as control
2002          * of this msr depends on is_long_mode().
2003          */
2004         vmx_load_host_state(to_vmx(vcpu));
2005         vcpu->arch.efer = efer;
2006         if (efer & EFER_LMA) {
2007                 vmcs_write32(VM_ENTRY_CONTROLS,
2008                              vmcs_read32(VM_ENTRY_CONTROLS) |
2009                              VM_ENTRY_IA32E_MODE);
2010                 msr->data = efer;
2011         } else {
2012                 vmcs_write32(VM_ENTRY_CONTROLS,
2013                              vmcs_read32(VM_ENTRY_CONTROLS) &
2014                              ~VM_ENTRY_IA32E_MODE);
2015
2016                 msr->data = efer & ~EFER_LME;
2017         }
2018         setup_msrs(vmx);
2019 }
2020
2021 #ifdef CONFIG_X86_64
2022
2023 static void enter_lmode(struct kvm_vcpu *vcpu)
2024 {
2025         u32 guest_tr_ar;
2026
2027         vmx_segment_cache_clear(to_vmx(vcpu));
2028
2029         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2030         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2031                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
2032                        __func__);
2033                 vmcs_write32(GUEST_TR_AR_BYTES,
2034                              (guest_tr_ar & ~AR_TYPE_MASK)
2035                              | AR_TYPE_BUSY_64_TSS);
2036         }
2037         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2038 }
2039
2040 static void exit_lmode(struct kvm_vcpu *vcpu)
2041 {
2042         vmcs_write32(VM_ENTRY_CONTROLS,
2043                      vmcs_read32(VM_ENTRY_CONTROLS)
2044                      & ~VM_ENTRY_IA32E_MODE);
2045         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2046 }
2047
2048 #endif
2049
2050 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2051 {
2052         vpid_sync_context(to_vmx(vcpu));
2053         if (enable_ept) {
2054                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2055                         return;
2056                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2057         }
2058 }
2059
2060 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2061 {
2062         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2063
2064         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2065         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2066 }
2067
2068 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2069 {
2070         if (enable_ept && is_paging(vcpu))
2071                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2072         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2073 }
2074
2075 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2076 {
2077         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2078
2079         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2080         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2081 }
2082
2083 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2084 {
2085         if (!test_bit(VCPU_EXREG_PDPTR,
2086                       (unsigned long *)&vcpu->arch.regs_dirty))
2087                 return;
2088
2089         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2090                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2091                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2092                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2093                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
2094         }
2095 }
2096
2097 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2098 {
2099         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2100                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2101                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2102                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2103                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2104         }
2105
2106         __set_bit(VCPU_EXREG_PDPTR,
2107                   (unsigned long *)&vcpu->arch.regs_avail);
2108         __set_bit(VCPU_EXREG_PDPTR,
2109                   (unsigned long *)&vcpu->arch.regs_dirty);
2110 }
2111
2112 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2113
2114 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2115                                         unsigned long cr0,
2116                                         struct kvm_vcpu *vcpu)
2117 {
2118         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2119                 vmx_decache_cr3(vcpu);
2120         if (!(cr0 & X86_CR0_PG)) {
2121                 /* From paging/starting to nonpaging */
2122                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2123                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
2124                              (CPU_BASED_CR3_LOAD_EXITING |
2125                               CPU_BASED_CR3_STORE_EXITING));
2126                 vcpu->arch.cr0 = cr0;
2127                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2128         } else if (!is_paging(vcpu)) {
2129                 /* From nonpaging to paging */
2130                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2131                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
2132                              ~(CPU_BASED_CR3_LOAD_EXITING |
2133                                CPU_BASED_CR3_STORE_EXITING));
2134                 vcpu->arch.cr0 = cr0;
2135                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2136         }
2137
2138         if (!(cr0 & X86_CR0_WP))
2139                 *hw_cr0 &= ~X86_CR0_WP;
2140 }
2141
2142 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2143 {
2144         struct vcpu_vmx *vmx = to_vmx(vcpu);
2145         unsigned long hw_cr0;
2146
2147         if (enable_unrestricted_guest)
2148                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2149                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2150         else
2151                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
2152
2153         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2154                 enter_pmode(vcpu);
2155
2156         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2157                 enter_rmode(vcpu);
2158
2159 #ifdef CONFIG_X86_64
2160         if (vcpu->arch.efer & EFER_LME) {
2161                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2162                         enter_lmode(vcpu);
2163                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2164                         exit_lmode(vcpu);
2165         }
2166 #endif
2167
2168         if (enable_ept)
2169                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2170
2171         if (!vcpu->fpu_active)
2172                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
2173
2174         vmcs_writel(CR0_READ_SHADOW, cr0);
2175         vmcs_writel(GUEST_CR0, hw_cr0);
2176         vcpu->arch.cr0 = cr0;
2177         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2178 }
2179
2180 static u64 construct_eptp(unsigned long root_hpa)
2181 {
2182         u64 eptp;
2183
2184         /* TODO write the value reading from MSR */
2185         eptp = VMX_EPT_DEFAULT_MT |
2186                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
2187         eptp |= (root_hpa & PAGE_MASK);
2188
2189         return eptp;
2190 }
2191
2192 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2193 {
2194         unsigned long guest_cr3;
2195         u64 eptp;
2196
2197         guest_cr3 = cr3;
2198         if (enable_ept) {
2199                 eptp = construct_eptp(cr3);
2200                 vmcs_write64(EPT_POINTER, eptp);
2201                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
2202                         vcpu->kvm->arch.ept_identity_map_addr;
2203                 ept_load_pdptrs(vcpu);
2204         }
2205
2206         vmx_flush_tlb(vcpu);
2207         vmcs_writel(GUEST_CR3, guest_cr3);
2208 }
2209
2210 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2211 {
2212         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
2213                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
2214
2215         vcpu->arch.cr4 = cr4;
2216         if (enable_ept) {
2217                 if (!is_paging(vcpu)) {
2218                         hw_cr4 &= ~X86_CR4_PAE;
2219                         hw_cr4 |= X86_CR4_PSE;
2220                 } else if (!(cr4 & X86_CR4_PAE)) {
2221                         hw_cr4 &= ~X86_CR4_PAE;
2222                 }
2223         }
2224
2225         vmcs_writel(CR4_READ_SHADOW, cr4);
2226         vmcs_writel(GUEST_CR4, hw_cr4);
2227 }
2228
2229 static void vmx_get_segment(struct kvm_vcpu *vcpu,
2230                             struct kvm_segment *var, int seg)
2231 {
2232         struct vcpu_vmx *vmx = to_vmx(vcpu);
2233         struct kvm_save_segment *save;
2234         u32 ar;
2235
2236         if (vmx->rmode.vm86_active
2237             && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
2238                 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
2239                 || seg == VCPU_SREG_GS)
2240             && !emulate_invalid_guest_state) {
2241                 switch (seg) {
2242                 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
2243                 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
2244                 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
2245                 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
2246                 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
2247                 default: BUG();
2248                 }
2249                 var->selector = save->selector;
2250                 var->base = save->base;
2251                 var->limit = save->limit;
2252                 ar = save->ar;
2253                 if (seg == VCPU_SREG_TR
2254                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
2255                         goto use_saved_rmode_seg;
2256         }
2257         var->base = vmx_read_guest_seg_base(vmx, seg);
2258         var->limit = vmx_read_guest_seg_limit(vmx, seg);
2259         var->selector = vmx_read_guest_seg_selector(vmx, seg);
2260         ar = vmx_read_guest_seg_ar(vmx, seg);
2261 use_saved_rmode_seg:
2262         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
2263                 ar = 0;
2264         var->type = ar & 15;
2265         var->s = (ar >> 4) & 1;
2266         var->dpl = (ar >> 5) & 3;
2267         var->present = (ar >> 7) & 1;
2268         var->avl = (ar >> 12) & 1;
2269         var->l = (ar >> 13) & 1;
2270         var->db = (ar >> 14) & 1;
2271         var->g = (ar >> 15) & 1;
2272         var->unusable = (ar >> 16) & 1;
2273 }
2274
2275 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2276 {
2277         struct kvm_segment s;
2278
2279         if (to_vmx(vcpu)->rmode.vm86_active) {
2280                 vmx_get_segment(vcpu, &s, seg);
2281                 return s.base;
2282         }
2283         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
2284 }
2285
2286 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
2287 {
2288         if (!is_protmode(vcpu))
2289                 return 0;
2290
2291         if (!is_long_mode(vcpu)
2292             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2293                 return 3;
2294
2295         return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
2296 }
2297
2298 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2299 {
2300         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
2301                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2302                 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
2303         }
2304         return to_vmx(vcpu)->cpl;
2305 }
2306
2307
2308 static u32 vmx_segment_access_rights(struct kvm_segment *var)
2309 {
2310         u32 ar;
2311
2312         if (var->unusable)
2313                 ar = 1 << 16;
2314         else {
2315                 ar = var->type & 15;
2316                 ar |= (var->s & 1) << 4;
2317                 ar |= (var->dpl & 3) << 5;
2318                 ar |= (var->present & 1) << 7;
2319                 ar |= (var->avl & 1) << 12;
2320                 ar |= (var->l & 1) << 13;
2321                 ar |= (var->db & 1) << 14;
2322                 ar |= (var->g & 1) << 15;
2323         }
2324         if (ar == 0) /* a 0 value means unusable */
2325                 ar = AR_UNUSABLE_MASK;
2326
2327         return ar;
2328 }
2329
2330 static void vmx_set_segment(struct kvm_vcpu *vcpu,
2331                             struct kvm_segment *var, int seg)
2332 {
2333         struct vcpu_vmx *vmx = to_vmx(vcpu);
2334         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2335         u32 ar;
2336
2337         vmx_segment_cache_clear(vmx);
2338
2339         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2340                 vmcs_write16(sf->selector, var->selector);
2341                 vmx->rmode.tr.selector = var->selector;
2342                 vmx->rmode.tr.base = var->base;
2343                 vmx->rmode.tr.limit = var->limit;
2344                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
2345                 return;
2346         }
2347         vmcs_writel(sf->base, var->base);
2348         vmcs_write32(sf->limit, var->limit);
2349         vmcs_write16(sf->selector, var->selector);
2350         if (vmx->rmode.vm86_active && var->s) {
2351                 /*
2352                  * Hack real-mode segments into vm86 compatibility.
2353                  */
2354                 if (var->base == 0xffff0000 && var->selector == 0xf000)
2355                         vmcs_writel(sf->base, 0xf0000);
2356                 ar = 0xf3;
2357         } else
2358                 ar = vmx_segment_access_rights(var);
2359
2360         /*
2361          *   Fix the "Accessed" bit in AR field of segment registers for older
2362          * qemu binaries.
2363          *   IA32 arch specifies that at the time of processor reset the
2364          * "Accessed" bit in the AR field of segment registers is 1. And qemu
2365          * is setting it to 0 in the usedland code. This causes invalid guest
2366          * state vmexit when "unrestricted guest" mode is turned on.
2367          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
2368          * tree. Newer qemu binaries with that qemu fix would not need this
2369          * kvm hack.
2370          */
2371         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2372                 ar |= 0x1; /* Accessed */
2373
2374         vmcs_write32(sf->ar_bytes, ar);
2375         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2376 }
2377
2378 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2379 {
2380         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
2381
2382         *db = (ar >> 14) & 1;
2383         *l = (ar >> 13) & 1;
2384 }
2385
2386 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2387 {
2388         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2389         dt->address = vmcs_readl(GUEST_IDTR_BASE);
2390 }
2391
2392 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2393 {
2394         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2395         vmcs_writel(GUEST_IDTR_BASE, dt->address);
2396 }
2397
2398 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2399 {
2400         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2401         dt->address = vmcs_readl(GUEST_GDTR_BASE);
2402 }
2403
2404 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2405 {
2406         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2407         vmcs_writel(GUEST_GDTR_BASE, dt->address);
2408 }
2409
2410 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2411 {
2412         struct kvm_segment var;
2413         u32 ar;
2414
2415         vmx_get_segment(vcpu, &var, seg);
2416         ar = vmx_segment_access_rights(&var);
2417
2418         if (var.base != (var.selector << 4))
2419                 return false;
2420         if (var.limit != 0xffff)
2421                 return false;
2422         if (ar != 0xf3)
2423                 return false;
2424
2425         return true;
2426 }
2427
2428 static bool code_segment_valid(struct kvm_vcpu *vcpu)
2429 {
2430         struct kvm_segment cs;
2431         unsigned int cs_rpl;
2432
2433         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2434         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2435
2436         if (cs.unusable)
2437                 return false;
2438         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2439                 return false;
2440         if (!cs.s)
2441                 return false;
2442         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
2443                 if (cs.dpl > cs_rpl)
2444                         return false;
2445         } else {
2446                 if (cs.dpl != cs_rpl)
2447                         return false;
2448         }
2449         if (!cs.present)
2450                 return false;
2451
2452         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2453         return true;
2454 }
2455
2456 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2457 {
2458         struct kvm_segment ss;
2459         unsigned int ss_rpl;
2460
2461         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2462         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2463
2464         if (ss.unusable)
2465                 return true;
2466         if (ss.type != 3 && ss.type != 7)
2467                 return false;
2468         if (!ss.s)
2469                 return false;
2470         if (ss.dpl != ss_rpl) /* DPL != RPL */
2471                 return false;
2472         if (!ss.present)
2473                 return false;
2474
2475         return true;
2476 }
2477
2478 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2479 {
2480         struct kvm_segment var;
2481         unsigned int rpl;
2482
2483         vmx_get_segment(vcpu, &var, seg);
2484         rpl = var.selector & SELECTOR_RPL_MASK;
2485
2486         if (var.unusable)
2487                 return true;
2488         if (!var.s)
2489                 return false;
2490         if (!var.present)
2491                 return false;
2492         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2493                 if (var.dpl < rpl) /* DPL < RPL */
2494                         return false;
2495         }
2496
2497         /* TODO: Add other members to kvm_segment_field to allow checking for other access
2498          * rights flags
2499          */
2500         return true;
2501 }
2502
2503 static bool tr_valid(struct kvm_vcpu *vcpu)
2504 {
2505         struct kvm_segment tr;
2506
2507         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2508
2509         if (tr.unusable)
2510                 return false;
2511         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
2512                 return false;
2513         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2514                 return false;
2515         if (!tr.present)
2516                 return false;
2517
2518         return true;
2519 }
2520
2521 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2522 {
2523         struct kvm_segment ldtr;
2524
2525         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2526
2527         if (ldtr.unusable)
2528                 return true;
2529         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
2530                 return false;
2531         if (ldtr.type != 2)
2532                 return false;
2533         if (!ldtr.present)
2534                 return false;
2535
2536         return true;
2537 }
2538
2539 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2540 {
2541         struct kvm_segment cs, ss;
2542
2543         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2544         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2545
2546         return ((cs.selector & SELECTOR_RPL_MASK) ==
2547                  (ss.selector & SELECTOR_RPL_MASK));
2548 }
2549
2550 /*
2551  * Check if guest state is valid. Returns true if valid, false if
2552  * not.
2553  * We assume that registers are always usable
2554  */
2555 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2556 {
2557         /* real mode guest state checks */
2558         if (!is_protmode(vcpu)) {
2559                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2560                         return false;
2561                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2562                         return false;
2563                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2564                         return false;
2565                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2566                         return false;
2567                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2568                         return false;
2569                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2570                         return false;
2571         } else {
2572         /* protected mode guest state checks */
2573                 if (!cs_ss_rpl_check(vcpu))
2574                         return false;
2575                 if (!code_segment_valid(vcpu))
2576                         return false;
2577                 if (!stack_segment_valid(vcpu))
2578                         return false;
2579                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2580                         return false;
2581                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2582                         return false;
2583                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2584                         return false;
2585                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2586                         return false;
2587                 if (!tr_valid(vcpu))
2588                         return false;
2589                 if (!ldtr_valid(vcpu))
2590                         return false;
2591         }
2592         /* TODO:
2593          * - Add checks on RIP
2594          * - Add checks on RFLAGS
2595          */
2596
2597         return true;
2598 }
2599
2600 static int init_rmode_tss(struct kvm *kvm)
2601 {
2602         gfn_t fn;
2603         u16 data = 0;
2604         int r, idx, ret = 0;
2605
2606         idx = srcu_read_lock(&kvm->srcu);
2607         fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2608         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2609         if (r < 0)
2610                 goto out;
2611         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2612         r = kvm_write_guest_page(kvm, fn++, &data,
2613                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
2614         if (r < 0)
2615                 goto out;
2616         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2617         if (r < 0)
2618                 goto out;
2619         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2620         if (r < 0)
2621                 goto out;
2622         data = ~0;
2623         r = kvm_write_guest_page(kvm, fn, &data,
2624                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2625                                  sizeof(u8));
2626         if (r < 0)
2627                 goto out;
2628
2629         ret = 1;
2630 out:
2631         srcu_read_unlock(&kvm->srcu, idx);
2632         return ret;
2633 }
2634
2635 static int init_rmode_identity_map(struct kvm *kvm)
2636 {
2637         int i, idx, r, ret;
2638         pfn_t identity_map_pfn;
2639         u32 tmp;
2640
2641         if (!enable_ept)
2642                 return 1;
2643         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2644                 printk(KERN_ERR "EPT: identity-mapping pagetable "
2645                         "haven't been allocated!\n");
2646                 return 0;
2647         }
2648         if (likely(kvm->arch.ept_identity_pagetable_done))
2649                 return 1;
2650         ret = 0;
2651         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2652         idx = srcu_read_lock(&kvm->srcu);
2653         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2654         if (r < 0)
2655                 goto out;
2656         /* Set up identity-mapping pagetable for EPT in real mode */
2657         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2658                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2659                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2660                 r = kvm_write_guest_page(kvm, identity_map_pfn,
2661                                 &tmp, i * sizeof(tmp), sizeof(tmp));
2662                 if (r < 0)
2663                         goto out;
2664         }
2665         kvm->arch.ept_identity_pagetable_done = true;
2666         ret = 1;
2667 out:
2668         srcu_read_unlock(&kvm->srcu, idx);
2669         return ret;
2670 }
2671
2672 static void seg_setup(int seg)
2673 {
2674         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2675         unsigned int ar;
2676
2677         vmcs_write16(sf->selector, 0);
2678         vmcs_writel(sf->base, 0);
2679         vmcs_write32(sf->limit, 0xffff);
2680         if (enable_unrestricted_guest) {
2681                 ar = 0x93;
2682                 if (seg == VCPU_SREG_CS)
2683                         ar |= 0x08; /* code segment */
2684         } else
2685                 ar = 0xf3;
2686
2687         vmcs_write32(sf->ar_bytes, ar);
2688 }
2689
2690 static int alloc_apic_access_page(struct kvm *kvm)
2691 {
2692         struct kvm_userspace_memory_region kvm_userspace_mem;
2693         int r = 0;
2694
2695         mutex_lock(&kvm->slots_lock);
2696         if (kvm->arch.apic_access_page)
2697                 goto out;
2698         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2699         kvm_userspace_mem.flags = 0;
2700         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2701         kvm_userspace_mem.memory_size = PAGE_SIZE;
2702         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2703         if (r)
2704                 goto out;
2705
2706         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2707 out:
2708         mutex_unlock(&kvm->slots_lock);
2709         return r;
2710 }
2711
2712 static int alloc_identity_pagetable(struct kvm *kvm)
2713 {
2714         struct kvm_userspace_memory_region kvm_userspace_mem;
2715         int r = 0;
2716
2717         mutex_lock(&kvm->slots_lock);
2718         if (kvm->arch.ept_identity_pagetable)
2719                 goto out;
2720         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2721         kvm_userspace_mem.flags = 0;
2722         kvm_userspace_mem.guest_phys_addr =
2723                 kvm->arch.ept_identity_map_addr;
2724         kvm_userspace_mem.memory_size = PAGE_SIZE;
2725         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2726         if (r)
2727                 goto out;
2728
2729         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2730                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2731 out:
2732         mutex_unlock(&kvm->slots_lock);
2733         return r;
2734 }
2735
2736 static void allocate_vpid(struct vcpu_vmx *vmx)
2737 {
2738         int vpid;
2739
2740         vmx->vpid = 0;
2741         if (!enable_vpid)
2742                 return;
2743         spin_lock(&vmx_vpid_lock);
2744         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2745         if (vpid < VMX_NR_VPIDS) {
2746                 vmx->vpid = vpid;
2747                 __set_bit(vpid, vmx_vpid_bitmap);
2748         }
2749         spin_unlock(&vmx_vpid_lock);
2750 }
2751
2752 static void free_vpid(struct vcpu_vmx *vmx)
2753 {
2754         if (!enable_vpid)
2755                 return;
2756         spin_lock(&vmx_vpid_lock);
2757         if (vmx->vpid != 0)
2758                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2759         spin_unlock(&vmx_vpid_lock);
2760 }
2761
2762 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2763 {
2764         int f = sizeof(unsigned long);
2765
2766         if (!cpu_has_vmx_msr_bitmap())
2767                 return;
2768
2769         /*
2770          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2771          * have the write-low and read-high bitmap offsets the wrong way round.
2772          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2773          */
2774         if (msr <= 0x1fff) {
2775                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2776                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2777         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2778                 msr &= 0x1fff;
2779                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2780                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2781         }
2782 }
2783
2784 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2785 {
2786         if (!longmode_only)
2787                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2788         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2789 }
2790
2791 /*
2792  * Sets up the vmcs for emulated real mode.
2793  */
2794 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2795 {
2796         u32 host_sysenter_cs, msr_low, msr_high;
2797         u32 junk;
2798         u64 host_pat;
2799         unsigned long a;
2800         struct desc_ptr dt;
2801         int i;
2802         unsigned long kvm_vmx_return;
2803         u32 exec_control;
2804
2805         /* I/O */
2806         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2807         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2808
2809         if (cpu_has_vmx_msr_bitmap())
2810                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2811
2812         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2813
2814         /* Control */
2815         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2816                 vmcs_config.pin_based_exec_ctrl);
2817
2818         exec_control = vmcs_config.cpu_based_exec_ctrl;
2819         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2820                 exec_control &= ~CPU_BASED_TPR_SHADOW;
2821 #ifdef CONFIG_X86_64
2822                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2823                                 CPU_BASED_CR8_LOAD_EXITING;
2824 #endif
2825         }
2826         if (!enable_ept)
2827                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2828                                 CPU_BASED_CR3_LOAD_EXITING  |
2829                                 CPU_BASED_INVLPG_EXITING;
2830         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2831
2832         if (cpu_has_secondary_exec_ctrls()) {
2833                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2834                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2835                         exec_control &=
2836                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2837                 if (vmx->vpid == 0)
2838                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2839                 if (!enable_ept) {
2840                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2841                         enable_unrestricted_guest = 0;
2842                 }
2843                 if (!enable_unrestricted_guest)
2844                         exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2845                 if (!ple_gap)
2846                         exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2847                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2848         }
2849
2850         if (ple_gap) {
2851                 vmcs_write32(PLE_GAP, ple_gap);
2852                 vmcs_write32(PLE_WINDOW, ple_window);
2853         }
2854
2855         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2856         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2857         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
2858
2859         vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS);  /* 22.2.3 */
2860         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
2861         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
2862
2863         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
2864         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2865         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2866         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
2867         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
2868         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2869 #ifdef CONFIG_X86_64
2870         rdmsrl(MSR_FS_BASE, a);
2871         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2872         rdmsrl(MSR_GS_BASE, a);
2873         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2874 #else
2875         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2876         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2877 #endif
2878
2879         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
2880
2881         native_store_idt(&dt);
2882         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
2883
2884         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2885         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2886         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2887         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2888         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2889         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2890         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
2891
2892         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2893         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2894         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2895         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
2896         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2897         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
2898
2899         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2900                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2901                 host_pat = msr_low | ((u64) msr_high << 32);
2902                 vmcs_write64(HOST_IA32_PAT, host_pat);
2903         }
2904         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2905                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2906                 host_pat = msr_low | ((u64) msr_high << 32);
2907                 /* Write the default value follow host pat */
2908                 vmcs_write64(GUEST_IA32_PAT, host_pat);
2909                 /* Keep arch.pat sync with GUEST_IA32_PAT */
2910                 vmx->vcpu.arch.pat = host_pat;
2911         }
2912
2913         for (i = 0; i < NR_VMX_MSR; ++i) {
2914                 u32 index = vmx_msr_index[i];
2915                 u32 data_low, data_high;
2916                 int j = vmx->nmsrs;
2917
2918                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2919                         continue;
2920                 if (wrmsr_safe(index, data_low, data_high) < 0)
2921                         continue;
2922                 vmx->guest_msrs[j].index = i;
2923                 vmx->guest_msrs[j].data = 0;
2924                 vmx->guest_msrs[j].mask = -1ull;
2925                 ++vmx->nmsrs;
2926         }
2927
2928         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2929
2930         /* 22.2.1, 20.8.1 */
2931         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2932
2933         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2934         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
2935         if (enable_ept)
2936                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
2937         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
2938
2939         kvm_write_tsc(&vmx->vcpu, 0);
2940
2941         return 0;
2942 }
2943
2944 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2945 {
2946         struct vcpu_vmx *vmx = to_vmx(vcpu);
2947         u64 msr;
2948         int ret;
2949
2950         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2951
2952         vmx->rmode.vm86_active = 0;
2953
2954         vmx->soft_vnmi_blocked = 0;
2955
2956         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2957         kvm_set_cr8(&vmx->vcpu, 0);
2958         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2959         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2960                 msr |= MSR_IA32_APICBASE_BSP;
2961         kvm_set_apic_base(&vmx->vcpu, msr);
2962
2963         ret = fx_init(&vmx->vcpu);
2964         if (ret != 0)
2965                 goto out;
2966
2967         vmx_segment_cache_clear(vmx);
2968
2969         seg_setup(VCPU_SREG_CS);
2970         /*
2971          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2972          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2973          */
2974         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2975                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2976                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2977         } else {
2978                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2979                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2980         }
2981
2982         seg_setup(VCPU_SREG_DS);
2983         seg_setup(VCPU_SREG_ES);
2984         seg_setup(VCPU_SREG_FS);
2985         seg_setup(VCPU_SREG_GS);
2986         seg_setup(VCPU_SREG_SS);
2987
2988         vmcs_write16(GUEST_TR_SELECTOR, 0);
2989         vmcs_writel(GUEST_TR_BASE, 0);
2990         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2991         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2992
2993         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2994         vmcs_writel(GUEST_LDTR_BASE, 0);
2995         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2996         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2997
2998         vmcs_write32(GUEST_SYSENTER_CS, 0);
2999         vmcs_writel(GUEST_SYSENTER_ESP, 0);
3000         vmcs_writel(GUEST_SYSENTER_EIP, 0);
3001
3002         vmcs_writel(GUEST_RFLAGS, 0x02);
3003         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3004                 kvm_rip_write(vcpu, 0xfff0);
3005         else
3006                 kvm_rip_write(vcpu, 0);
3007         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
3008
3009         vmcs_writel(GUEST_DR7, 0x400);
3010
3011         vmcs_writel(GUEST_GDTR_BASE, 0);
3012         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3013
3014         vmcs_writel(GUEST_IDTR_BASE, 0);
3015         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3016
3017         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3018         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3019         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3020
3021         /* Special registers */
3022         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3023
3024         setup_msrs(vmx);
3025
3026         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
3027
3028         if (cpu_has_vmx_tpr_shadow()) {
3029                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3030                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3031                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
3032                                      __pa(vmx->vcpu.arch.apic->regs));
3033                 vmcs_write32(TPR_THRESHOLD, 0);
3034         }
3035
3036         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3037                 vmcs_write64(APIC_ACCESS_ADDR,
3038                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
3039
3040         if (vmx->vpid != 0)
3041                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3042
3043         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
3044         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
3045         vmx_set_cr4(&vmx->vcpu, 0);
3046         vmx_set_efer(&vmx->vcpu, 0);
3047         vmx_fpu_activate(&vmx->vcpu);
3048         update_exception_bitmap(&vmx->vcpu);
3049
3050         vpid_sync_context(vmx);
3051
3052         ret = 0;
3053
3054         /* HACK: Don't enable emulation on guest boot/reset */
3055         vmx->emulation_required = 0;
3056
3057 out:
3058         return ret;
3059 }
3060
3061 static void enable_irq_window(struct kvm_vcpu *vcpu)
3062 {
3063         u32 cpu_based_vm_exec_control;
3064
3065         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3066         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
3067         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3068 }
3069
3070 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3071 {
3072         u32 cpu_based_vm_exec_control;
3073
3074         if (!cpu_has_virtual_nmis()) {
3075                 enable_irq_window(vcpu);
3076                 return;
3077         }
3078
3079         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
3080                 enable_irq_window(vcpu);
3081                 return;
3082         }
3083         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3084         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
3085         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3086 }
3087
3088 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
3089 {
3090         struct vcpu_vmx *vmx = to_vmx(vcpu);
3091         uint32_t intr;
3092         int irq = vcpu->arch.interrupt.nr;
3093
3094         trace_kvm_inj_virq(irq);
3095
3096         ++vcpu->stat.irq_injections;
3097         if (vmx->rmode.vm86_active) {
3098                 int inc_eip = 0;
3099                 if (vcpu->arch.interrupt.soft)
3100                         inc_eip = vcpu->arch.event_exit_inst_len;
3101                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
3102                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3103                 return;
3104         }
3105         intr = irq | INTR_INFO_VALID_MASK;
3106         if (vcpu->arch.interrupt.soft) {
3107                 intr |= INTR_TYPE_SOFT_INTR;
3108                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3109                              vmx->vcpu.arch.event_exit_inst_len);
3110         } else
3111                 intr |= INTR_TYPE_EXT_INTR;
3112         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
3113         vmx_clear_hlt(vcpu);
3114 }
3115
3116 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
3117 {
3118         struct vcpu_vmx *vmx = to_vmx(vcpu);
3119
3120         if (!cpu_has_virtual_nmis()) {
3121                 /*
3122                  * Tracking the NMI-blocked state in software is built upon
3123                  * finding the next open IRQ window. This, in turn, depends on
3124                  * well-behaving guests: They have to keep IRQs disabled at
3125                  * least as long as the NMI handler runs. Otherwise we may
3126                  * cause NMI nesting, maybe breaking the guest. But as this is
3127                  * highly unlikely, we can live with the residual risk.
3128                  */
3129                 vmx->soft_vnmi_blocked = 1;
3130                 vmx->vnmi_blocked_time = 0;
3131         }
3132
3133         ++vcpu->stat.nmi_injections;
3134         vmx->nmi_known_unmasked = false;
3135         if (vmx->rmode.vm86_active) {
3136                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
3137                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3138                 return;
3139         }
3140         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
3141                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
3142         vmx_clear_hlt(vcpu);
3143 }
3144
3145 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
3146 {
3147         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
3148                 return 0;
3149
3150         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3151                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
3152                    | GUEST_INTR_STATE_NMI));
3153 }
3154
3155 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
3156 {
3157         if (!cpu_has_virtual_nmis())
3158                 return to_vmx(vcpu)->soft_vnmi_blocked;
3159         if (to_vmx(vcpu)->nmi_known_unmasked)
3160                 return false;
3161         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3162 }
3163
3164 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3165 {
3166         struct vcpu_vmx *vmx = to_vmx(vcpu);
3167
3168         if (!cpu_has_virtual_nmis()) {
3169                 if (vmx->soft_vnmi_blocked != masked) {
3170                         vmx->soft_vnmi_blocked = masked;
3171                         vmx->vnmi_blocked_time = 0;
3172                 }
3173         } else {
3174                 vmx->nmi_known_unmasked = !masked;
3175                 if (masked)
3176                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3177                                       GUEST_INTR_STATE_NMI);
3178                 else
3179                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3180                                         GUEST_INTR_STATE_NMI);
3181         }
3182 }
3183
3184 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
3185 {
3186         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
3187                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3188                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
3189 }
3190
3191 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
3192 {
3193         int ret;
3194         struct kvm_userspace_memory_region tss_mem = {
3195                 .slot = TSS_PRIVATE_MEMSLOT,
3196                 .guest_phys_addr = addr,
3197                 .memory_size = PAGE_SIZE * 3,
3198                 .flags = 0,
3199         };
3200
3201         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
3202         if (ret)
3203                 return ret;
3204         kvm->arch.tss_addr = addr;
3205         if (!init_rmode_tss(kvm))
3206                 return  -ENOMEM;
3207
3208         return 0;
3209 }
3210
3211 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
3212                                   int vec, u32 err_code)
3213 {
3214         /*
3215          * Instruction with address size override prefix opcode 0x67
3216          * Cause the #SS fault with 0 error code in VM86 mode.
3217          */
3218         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
3219                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
3220                         return 1;
3221         /*
3222          * Forward all other exceptions that are valid in real mode.
3223          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
3224          *        the required debugging infrastructure rework.
3225          */
3226         switch (vec) {
3227         case DB_VECTOR:
3228                 if (vcpu->guest_debug &
3229                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
3230                         return 0;
3231                 kvm_queue_exception(vcpu, vec);
3232                 return 1;
3233         case BP_VECTOR:
3234                 /*
3235                  * Update instruction length as we may reinject the exception
3236                  * from user space while in guest debugging mode.
3237                  */
3238                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
3239                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3240                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
3241                         return 0;
3242                 /* fall through */
3243         case DE_VECTOR:
3244         case OF_VECTOR:
3245         case BR_VECTOR:
3246         case UD_VECTOR:
3247         case DF_VECTOR:
3248         case SS_VECTOR:
3249         case GP_VECTOR:
3250         case MF_VECTOR:
3251                 kvm_queue_exception(vcpu, vec);
3252                 return 1;
3253         }
3254         return 0;
3255 }
3256
3257 /*
3258  * Trigger machine check on the host. We assume all the MSRs are already set up
3259  * by the CPU and that we still run on the same CPU as the MCE occurred on.
3260  * We pass a fake environment to the machine check handler because we want
3261  * the guest to be always treated like user space, no matter what context
3262  * it used internally.
3263  */
3264 static void kvm_machine_check(void)
3265 {
3266 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
3267         struct pt_regs regs = {
3268                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
3269                 .flags = X86_EFLAGS_IF,
3270         };
3271
3272         do_machine_check(&regs, 0);
3273 #endif
3274 }
3275
3276 static int handle_machine_check(struct kvm_vcpu *vcpu)
3277 {
3278         /* already handled by vcpu_run */
3279         return 1;
3280 }
3281
3282 static int handle_exception(struct kvm_vcpu *vcpu)
3283 {
3284         struct vcpu_vmx *vmx = to_vmx(vcpu);
3285         struct kvm_run *kvm_run = vcpu->run;
3286         u32 intr_info, ex_no, error_code;
3287         unsigned long cr2, rip, dr6;
3288         u32 vect_info;
3289         enum emulation_result er;
3290
3291         vect_info = vmx->idt_vectoring_info;
3292         intr_info = vmx->exit_intr_info;
3293
3294         if (is_machine_check(intr_info))
3295                 return handle_machine_check(vcpu);
3296
3297         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
3298             !is_page_fault(intr_info)) {
3299                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3300                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3301                 vcpu->run->internal.ndata = 2;
3302                 vcpu->run->internal.data[0] = vect_info;
3303                 vcpu->run->internal.data[1] = intr_info;
3304                 return 0;
3305         }
3306
3307         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
3308                 return 1;  /* already handled by vmx_vcpu_run() */
3309
3310         if (is_no_device(intr_info)) {
3311                 vmx_fpu_activate(vcpu);
3312                 return 1;
3313         }
3314
3315         if (is_invalid_opcode(intr_info)) {
3316                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
3317                 if (er != EMULATE_DONE)
3318                         kvm_queue_exception(vcpu, UD_VECTOR);
3319                 return 1;
3320         }
3321
3322         error_code = 0;
3323         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
3324                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3325         if (is_page_fault(intr_info)) {
3326                 /* EPT won't cause page fault directly */
3327                 if (enable_ept)
3328                         BUG();
3329                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
3330                 trace_kvm_page_fault(cr2, error_code);
3331
3332                 if (kvm_event_needs_reinjection(vcpu))
3333                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
3334                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
3335         }
3336
3337         if (vmx->rmode.vm86_active &&
3338             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
3339                                                                 error_code)) {
3340                 if (vcpu->arch.halt_request) {
3341                         vcpu->arch.halt_request = 0;
3342                         return kvm_emulate_halt(vcpu);
3343                 }
3344                 return 1;
3345         }
3346
3347         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
3348         switch (ex_no) {
3349         case DB_VECTOR:
3350                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3351                 if (!(vcpu->guest_debug &
3352                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3353                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3354                         kvm_queue_exception(vcpu, DB_VECTOR);
3355                         return 1;
3356                 }
3357                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3358                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3359                 /* fall through */
3360         case BP_VECTOR:
3361                 /*
3362                  * Update instruction length as we may reinject #BP from
3363                  * user space while in guest debugging mode. Reading it for
3364                  * #DB as well causes no harm, it is not used in that case.
3365                  */
3366                 vmx->vcpu.arch.event_exit_inst_len =
3367                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3368                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
3369                 rip = kvm_rip_read(vcpu);
3370                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3371                 kvm_run->debug.arch.exception = ex_no;
3372                 break;
3373         default:
3374                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3375                 kvm_run->ex.exception = ex_no;
3376                 kvm_run->ex.error_code = error_code;
3377                 break;
3378         }
3379         return 0;
3380 }
3381
3382 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
3383 {
3384         ++vcpu->stat.irq_exits;
3385         return 1;
3386 }
3387
3388 static int handle_triple_fault(struct kvm_vcpu *vcpu)
3389 {
3390         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
3391         return 0;
3392 }
3393
3394 static int handle_io(struct kvm_vcpu *vcpu)
3395 {
3396         unsigned long exit_qualification;
3397         int size, in, string;
3398         unsigned port;
3399
3400         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3401         string = (exit_qualification & 16) != 0;
3402         in = (exit_qualification & 8) != 0;
3403
3404         ++vcpu->stat.io_exits;
3405
3406         if (string || in)
3407                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
3408
3409         port = exit_qualification >> 16;
3410         size = (exit_qualification & 7) + 1;
3411         skip_emulated_instruction(vcpu);
3412
3413         return kvm_fast_pio_out(vcpu, size, port);
3414 }
3415
3416 static void
3417 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3418 {
3419         /*
3420          * Patch in the VMCALL instruction:
3421          */
3422         hypercall[0] = 0x0f;
3423         hypercall[1] = 0x01;
3424         hypercall[2] = 0xc1;
3425 }
3426
3427 static int handle_cr(struct kvm_vcpu *vcpu)
3428 {
3429         unsigned long exit_qualification, val;
3430         int cr;
3431         int reg;
3432         int err;
3433
3434         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3435         cr = exit_qualification & 15;
3436         reg = (exit_qualification >> 8) & 15;
3437         switch ((exit_qualification >> 4) & 3) {
3438         case 0: /* mov to cr */
3439                 val = kvm_register_read(vcpu, reg);
3440                 trace_kvm_cr_write(cr, val);
3441                 switch (cr) {
3442                 case 0:
3443                         err = kvm_set_cr0(vcpu, val);
3444                         kvm_complete_insn_gp(vcpu, err);
3445                         return 1;
3446                 case 3:
3447                         err = kvm_set_cr3(vcpu, val);
3448                         kvm_complete_insn_gp(vcpu, err);
3449                         return 1;
3450                 case 4:
3451                         err = kvm_set_cr4(vcpu, val);
3452                         kvm_complete_insn_gp(vcpu, err);
3453                         return 1;
3454                 case 8: {
3455                                 u8 cr8_prev = kvm_get_cr8(vcpu);
3456                                 u8 cr8 = kvm_register_read(vcpu, reg);
3457                                 err = kvm_set_cr8(vcpu, cr8);
3458                                 kvm_complete_insn_gp(vcpu, err);
3459                                 if (irqchip_in_kernel(vcpu->kvm))
3460                                         return 1;
3461                                 if (cr8_prev <= cr8)
3462                                         return 1;
3463                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
3464                                 return 0;
3465                         }
3466                 };
3467                 break;
3468         case 2: /* clts */
3469                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
3470                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
3471                 skip_emulated_instruction(vcpu);
3472                 vmx_fpu_activate(vcpu);
3473                 return 1;
3474         case 1: /*mov from cr*/
3475                 switch (cr) {
3476                 case 3:
3477                         val = kvm_read_cr3(vcpu);
3478                         kvm_register_write(vcpu, reg, val);
3479                         trace_kvm_cr_read(cr, val);
3480                         skip_emulated_instruction(vcpu);
3481                         return 1;
3482                 case 8:
3483                         val = kvm_get_cr8(vcpu);
3484                         kvm_register_write(vcpu, reg, val);
3485                         trace_kvm_cr_read(cr, val);
3486                         skip_emulated_instruction(vcpu);
3487                         return 1;
3488                 }
3489                 break;
3490         case 3: /* lmsw */
3491                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
3492                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
3493                 kvm_lmsw(vcpu, val);
3494
3495                 skip_emulated_instruction(vcpu);
3496                 return 1;
3497         default:
3498                 break;
3499         }
3500         vcpu->run->exit_reason = 0;
3501         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
3502                (int)(exit_qualification >> 4) & 3, cr);
3503         return 0;
3504 }
3505
3506 static int handle_dr(struct kvm_vcpu *vcpu)
3507 {
3508         unsigned long exit_qualification;
3509         int dr, reg;
3510
3511         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3512         if (!kvm_require_cpl(vcpu, 0))
3513                 return 1;
3514         dr = vmcs_readl(GUEST_DR7);
3515         if (dr & DR7_GD) {
3516                 /*
3517                  * As the vm-exit takes precedence over the debug trap, we
3518                  * need to emulate the latter, either for the host or the
3519                  * guest debugging itself.
3520                  */
3521                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3522                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3523                         vcpu->run->debug.arch.dr7 = dr;
3524                         vcpu->run->debug.arch.pc =
3525                                 vmcs_readl(GUEST_CS_BASE) +
3526                                 vmcs_readl(GUEST_RIP);
3527                         vcpu->run->debug.arch.exception = DB_VECTOR;
3528                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3529                         return 0;
3530                 } else {
3531                         vcpu->arch.dr7 &= ~DR7_GD;
3532                         vcpu->arch.dr6 |= DR6_BD;
3533                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3534                         kvm_queue_exception(vcpu, DB_VECTOR);
3535                         return 1;
3536                 }
3537         }
3538
3539         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3540         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3541         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3542         if (exit_qualification & TYPE_MOV_FROM_DR) {
3543                 unsigned long val;
3544                 if (!kvm_get_dr(vcpu, dr, &val))
3545                         kvm_register_write(vcpu, reg, val);
3546         } else
3547                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
3548         skip_emulated_instruction(vcpu);
3549         return 1;
3550 }
3551
3552 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3553 {
3554         vmcs_writel(GUEST_DR7, val);
3555 }
3556
3557 static int handle_cpuid(struct kvm_vcpu *vcpu)
3558 {
3559         kvm_emulate_cpuid(vcpu);
3560         return 1;
3561 }
3562
3563 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3564 {
3565         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3566         u64 data;
3567
3568         if (vmx_get_msr(vcpu, ecx, &data)) {
3569                 trace_kvm_msr_read_ex(ecx);
3570                 kvm_inject_gp(vcpu, 0);
3571                 return 1;
3572         }
3573
3574         trace_kvm_msr_read(ecx, data);
3575
3576         /* FIXME: handling of bits 32:63 of rax, rdx */
3577         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3578         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3579         skip_emulated_instruction(vcpu);
3580         return 1;
3581 }
3582
3583 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3584 {
3585         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3586         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3587                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3588
3589         if (vmx_set_msr(vcpu, ecx, data) != 0) {
3590                 trace_kvm_msr_write_ex(ecx, data);
3591                 kvm_inject_gp(vcpu, 0);
3592                 return 1;
3593         }
3594
3595         trace_kvm_msr_write(ecx, data);
3596         skip_emulated_instruction(vcpu);
3597         return 1;
3598 }
3599
3600 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3601 {
3602         kvm_make_request(KVM_REQ_EVENT, vcpu);
3603         return 1;
3604 }
3605
3606 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3607 {
3608         u32 cpu_based_vm_exec_control;
3609
3610         /* clear pending irq */
3611         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3612         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3613         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3614
3615         kvm_make_request(KVM_REQ_EVENT, vcpu);
3616
3617         ++vcpu->stat.irq_window_exits;
3618
3619         /*
3620          * If the user space waits to inject interrupts, exit as soon as
3621          * possible
3622          */
3623         if (!irqchip_in_kernel(vcpu->kvm) &&
3624             vcpu->run->request_interrupt_window &&
3625             !kvm_cpu_has_interrupt(vcpu)) {
3626                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3627                 return 0;
3628         }
3629         return 1;
3630 }
3631
3632 static int handle_halt(struct kvm_vcpu *vcpu)
3633 {
3634         skip_emulated_instruction(vcpu);
3635         return kvm_emulate_halt(vcpu);
3636 }
3637
3638 static int handle_vmcall(struct kvm_vcpu *vcpu)
3639 {
3640         skip_emulated_instruction(vcpu);
3641         kvm_emulate_hypercall(vcpu);
3642         return 1;
3643 }
3644
3645 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3646 {
3647         kvm_queue_exception(vcpu, UD_VECTOR);
3648         return 1;
3649 }
3650
3651 static int handle_invd(struct kvm_vcpu *vcpu)
3652 {
3653         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
3654 }
3655
3656 static int handle_invlpg(struct kvm_vcpu *vcpu)
3657 {
3658         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3659
3660         kvm_mmu_invlpg(vcpu, exit_qualification);
3661         skip_emulated_instruction(vcpu);
3662         return 1;
3663 }
3664
3665 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3666 {
3667         skip_emulated_instruction(vcpu);
3668         kvm_emulate_wbinvd(vcpu);
3669         return 1;
3670 }
3671
3672 static int handle_xsetbv(struct kvm_vcpu *vcpu)
3673 {
3674         u64 new_bv = kvm_read_edx_eax(vcpu);
3675         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3676
3677         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
3678                 skip_emulated_instruction(vcpu);
3679         return 1;
3680 }
3681
3682 static int handle_apic_access(struct kvm_vcpu *vcpu)
3683 {
3684         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
3685 }
3686
3687 static int handle_task_switch(struct kvm_vcpu *vcpu)
3688 {
3689         struct vcpu_vmx *vmx = to_vmx(vcpu);
3690         unsigned long exit_qualification;
3691         bool has_error_code = false;
3692         u32 error_code = 0;
3693         u16 tss_selector;
3694         int reason, type, idt_v;
3695
3696         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3697         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3698
3699         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3700
3701         reason = (u32)exit_qualification >> 30;
3702         if (reason == TASK_SWITCH_GATE && idt_v) {
3703                 switch (type) {
3704                 case INTR_TYPE_NMI_INTR:
3705                         vcpu->arch.nmi_injected = false;
3706                         vmx_set_nmi_mask(vcpu, true);
3707                         break;
3708                 case INTR_TYPE_EXT_INTR:
3709                 case INTR_TYPE_SOFT_INTR:
3710                         kvm_clear_interrupt_queue(vcpu);
3711                         break;
3712                 case INTR_TYPE_HARD_EXCEPTION:
3713                         if (vmx->idt_vectoring_info &
3714                             VECTORING_INFO_DELIVER_CODE_MASK) {
3715                                 has_error_code = true;
3716                                 error_code =
3717                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
3718                         }
3719                         /* fall through */
3720                 case INTR_TYPE_SOFT_EXCEPTION:
3721                         kvm_clear_exception_queue(vcpu);
3722                         break;
3723                 default:
3724                         break;
3725                 }
3726         }
3727         tss_selector = exit_qualification;
3728
3729         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3730                        type != INTR_TYPE_EXT_INTR &&
3731                        type != INTR_TYPE_NMI_INTR))
3732                 skip_emulated_instruction(vcpu);
3733
3734         if (kvm_task_switch(vcpu, tss_selector, reason,
3735                                 has_error_code, error_code) == EMULATE_FAIL) {
3736                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3737                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3738                 vcpu->run->internal.ndata = 0;
3739                 return 0;
3740         }
3741
3742         /* clear all local breakpoint enable flags */
3743         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3744
3745         /*
3746          * TODO: What about debug traps on tss switch?
3747          *       Are we supposed to inject them and update dr6?
3748          */
3749
3750         return 1;
3751 }
3752
3753 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3754 {
3755         unsigned long exit_qualification;
3756         gpa_t gpa;
3757         int gla_validity;
3758
3759         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3760
3761         if (exit_qualification & (1 << 6)) {
3762                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3763                 return -EINVAL;
3764         }
3765
3766         gla_validity = (exit_qualification >> 7) & 0x3;
3767         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3768                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3769                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3770                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3771                         vmcs_readl(GUEST_LINEAR_ADDRESS));
3772                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3773                         (long unsigned int)exit_qualification);
3774                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3775                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3776                 return 0;
3777         }
3778
3779         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3780         trace_kvm_page_fault(gpa, exit_qualification);
3781         return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
3782 }
3783
3784 static u64 ept_rsvd_mask(u64 spte, int level)
3785 {
3786         int i;
3787         u64 mask = 0;
3788
3789         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3790                 mask |= (1ULL << i);
3791
3792         if (level > 2)
3793                 /* bits 7:3 reserved */
3794                 mask |= 0xf8;
3795         else if (level == 2) {
3796                 if (spte & (1ULL << 7))
3797                         /* 2MB ref, bits 20:12 reserved */
3798                         mask |= 0x1ff000;
3799                 else
3800                         /* bits 6:3 reserved */
3801                         mask |= 0x78;
3802         }
3803
3804         return mask;
3805 }
3806
3807 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3808                                        int level)
3809 {
3810         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3811
3812         /* 010b (write-only) */
3813         WARN_ON((spte & 0x7) == 0x2);
3814
3815         /* 110b (write/execute) */
3816         WARN_ON((spte & 0x7) == 0x6);
3817
3818         /* 100b (execute-only) and value not supported by logical processor */
3819         if (!cpu_has_vmx_ept_execute_only())
3820                 WARN_ON((spte & 0x7) == 0x4);
3821
3822         /* not 000b */
3823         if ((spte & 0x7)) {
3824                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3825
3826                 if (rsvd_bits != 0) {
3827                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3828                                          __func__, rsvd_bits);
3829                         WARN_ON(1);
3830                 }
3831
3832                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3833                         u64 ept_mem_type = (spte & 0x38) >> 3;
3834
3835                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
3836                             ept_mem_type == 7) {
3837                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3838                                                 __func__, ept_mem_type);
3839                                 WARN_ON(1);
3840                         }
3841                 }
3842         }
3843 }
3844
3845 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3846 {
3847         u64 sptes[4];
3848         int nr_sptes, i;
3849         gpa_t gpa;
3850
3851         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3852
3853         printk(KERN_ERR "EPT: Misconfiguration.\n");
3854         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3855
3856         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3857
3858         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3859                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3860
3861         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3862         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3863
3864         return 0;
3865 }
3866
3867 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3868 {
3869         u32 cpu_based_vm_exec_control;
3870
3871         /* clear pending NMI */
3872         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3873         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3874         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3875         ++vcpu->stat.nmi_window_exits;
3876         kvm_make_request(KVM_REQ_EVENT, vcpu);
3877
3878         return 1;
3879 }
3880
3881 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3882 {
3883         struct vcpu_vmx *vmx = to_vmx(vcpu);
3884         enum emulation_result err = EMULATE_DONE;
3885         int ret = 1;
3886         u32 cpu_exec_ctrl;
3887         bool intr_window_requested;
3888
3889         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3890         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
3891
3892         while (!guest_state_valid(vcpu)) {
3893                 if (intr_window_requested
3894                     && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
3895                         return handle_interrupt_window(&vmx->vcpu);
3896
3897                 err = emulate_instruction(vcpu, 0);
3898
3899                 if (err == EMULATE_DO_MMIO) {
3900                         ret = 0;
3901                         goto out;
3902                 }
3903
3904                 if (err != EMULATE_DONE)
3905                         return 0;
3906
3907                 if (signal_pending(current))
3908                         goto out;
3909                 if (need_resched())
3910                         schedule();
3911         }
3912
3913         vmx->emulation_required = 0;
3914 out:
3915         return ret;
3916 }
3917
3918 /*
3919  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3920  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3921  */
3922 static int handle_pause(struct kvm_vcpu *vcpu)
3923 {
3924         skip_emulated_instruction(vcpu);
3925         kvm_vcpu_on_spin(vcpu);
3926
3927         return 1;
3928 }
3929
3930 static int handle_invalid_op(struct kvm_vcpu *vcpu)
3931 {
3932         kvm_queue_exception(vcpu, UD_VECTOR);
3933         return 1;
3934 }
3935
3936 /*
3937  * The exit handlers return 1 if the exit was handled fully and guest execution
3938  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
3939  * to be done to userspace and return 0.
3940  */
3941 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3942         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
3943         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
3944         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
3945         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
3946         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
3947         [EXIT_REASON_CR_ACCESS]               = handle_cr,
3948         [EXIT_REASON_DR_ACCESS]               = handle_dr,
3949         [EXIT_REASON_CPUID]                   = handle_cpuid,
3950         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
3951         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
3952         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
3953         [EXIT_REASON_HLT]                     = handle_halt,
3954         [EXIT_REASON_INVD]                    = handle_invd,
3955         [EXIT_REASON_INVLPG]                  = handle_invlpg,
3956         [EXIT_REASON_VMCALL]                  = handle_vmcall,
3957         [EXIT_REASON_VMCLEAR]                 = handle_vmx_insn,
3958         [EXIT_REASON_VMLAUNCH]                = handle_vmx_insn,
3959         [EXIT_REASON_VMPTRLD]                 = handle_vmx_insn,
3960         [EXIT_REASON_VMPTRST]                 = handle_vmx_insn,
3961         [EXIT_REASON_VMREAD]                  = handle_vmx_insn,
3962         [EXIT_REASON_VMRESUME]                = handle_vmx_insn,
3963         [EXIT_REASON_VMWRITE]                 = handle_vmx_insn,
3964         [EXIT_REASON_VMOFF]                   = handle_vmx_insn,
3965         [EXIT_REASON_VMON]                    = handle_vmx_insn,
3966         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
3967         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
3968         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
3969         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
3970         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
3971         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
3972         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
3973         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
3974         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
3975         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
3976         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
3977 };
3978
3979 static const int kvm_vmx_max_exit_handlers =
3980         ARRAY_SIZE(kvm_vmx_exit_handlers);
3981
3982 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3983 {
3984         *info1 = vmcs_readl(EXIT_QUALIFICATION);
3985         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
3986 }
3987
3988 /*
3989  * The guest has exited.  See if we can fix it or if we need userspace
3990  * assistance.
3991  */
3992 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3993 {
3994         struct vcpu_vmx *vmx = to_vmx(vcpu);
3995         u32 exit_reason = vmx->exit_reason;
3996         u32 vectoring_info = vmx->idt_vectoring_info;
3997
3998         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
3999
4000         /* If guest state is invalid, start emulating */
4001         if (vmx->emulation_required && emulate_invalid_guest_state)
4002                 return handle_invalid_guest_state(vcpu);
4003
4004         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
4005                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4006                 vcpu->run->fail_entry.hardware_entry_failure_reason
4007                         = exit_reason;
4008                 return 0;
4009         }
4010
4011         if (unlikely(vmx->fail)) {
4012                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4013                 vcpu->run->fail_entry.hardware_entry_failure_reason
4014                         = vmcs_read32(VM_INSTRUCTION_ERROR);
4015                 return 0;
4016         }
4017
4018         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
4019                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
4020                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
4021                         exit_reason != EXIT_REASON_TASK_SWITCH))
4022                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
4023                        "(0x%x) and exit reason is 0x%x\n",
4024                        __func__, vectoring_info, exit_reason);
4025
4026         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
4027                 if (vmx_interrupt_allowed(vcpu)) {
4028                         vmx->soft_vnmi_blocked = 0;
4029                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4030                            vcpu->arch.nmi_pending) {
4031                         /*
4032                          * This CPU don't support us in finding the end of an
4033                          * NMI-blocked window if the guest runs with IRQs
4034                          * disabled. So we pull the trigger after 1 s of
4035                          * futile waiting, but inform the user about this.
4036                          */
4037                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
4038                                "state on VCPU %d after 1 s timeout\n",
4039                                __func__, vcpu->vcpu_id);
4040                         vmx->soft_vnmi_blocked = 0;
4041                 }
4042         }
4043
4044         if (exit_reason < kvm_vmx_max_exit_handlers
4045             && kvm_vmx_exit_handlers[exit_reason])
4046                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
4047         else {
4048                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4049                 vcpu->run->hw.hardware_exit_reason = exit_reason;
4050         }
4051         return 0;
4052 }
4053
4054 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
4055 {
4056         if (irr == -1 || tpr < irr) {
4057                 vmcs_write32(TPR_THRESHOLD, 0);
4058                 return;
4059         }
4060
4061         vmcs_write32(TPR_THRESHOLD, irr);
4062 }
4063
4064 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
4065 {
4066         u32 exit_intr_info;
4067
4068         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
4069               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
4070                 return;
4071
4072         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
4073         exit_intr_info = vmx->exit_intr_info;
4074
4075         /* Handle machine checks before interrupts are enabled */
4076         if (is_machine_check(exit_intr_info))
4077                 kvm_machine_check();
4078
4079         /* We need to handle NMIs before interrupts are enabled */
4080         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
4081             (exit_intr_info & INTR_INFO_VALID_MASK)) {
4082                 kvm_before_handle_nmi(&vmx->vcpu);
4083                 asm("int $2");
4084                 kvm_after_handle_nmi(&vmx->vcpu);
4085         }
4086 }
4087
4088 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
4089 {
4090         u32 exit_intr_info;
4091         bool unblock_nmi;
4092         u8 vector;
4093         bool idtv_info_valid;
4094
4095         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
4096
4097         if (cpu_has_virtual_nmis()) {
4098                 if (vmx->nmi_known_unmasked)
4099                         return;
4100                 /*
4101                  * Can't use vmx->exit_intr_info since we're not sure what
4102                  * the exit reason is.
4103                  */
4104                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
4105                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
4106                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
4107                 /*
4108                  * SDM 3: 27.7.1.2 (September 2008)
4109                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
4110                  * a guest IRET fault.
4111                  * SDM 3: 23.2.2 (September 2008)
4112                  * Bit 12 is undefined in any of the following cases:
4113                  *  If the VM exit sets the valid bit in the IDT-vectoring
4114                  *   information field.
4115                  *  If the VM exit is due to a double fault.
4116                  */
4117                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
4118                     vector != DF_VECTOR && !idtv_info_valid)
4119                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4120                                       GUEST_INTR_STATE_NMI);
4121                 else
4122                         vmx->nmi_known_unmasked =
4123                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
4124                                   & GUEST_INTR_STATE_NMI);
4125         } else if (unlikely(vmx->soft_vnmi_blocked))
4126                 vmx->vnmi_blocked_time +=
4127                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
4128 }
4129
4130 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
4131                                       u32 idt_vectoring_info,
4132                                       int instr_len_field,
4133                                       int error_code_field)
4134 {
4135         u8 vector;
4136         int type;
4137         bool idtv_info_valid;
4138
4139         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
4140
4141         vmx->vcpu.arch.nmi_injected = false;
4142         kvm_clear_exception_queue(&vmx->vcpu);
4143         kvm_clear_interrupt_queue(&vmx->vcpu);
4144
4145         if (!idtv_info_valid)
4146                 return;
4147
4148         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
4149
4150         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
4151         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
4152
4153         switch (type) {
4154         case INTR_TYPE_NMI_INTR:
4155                 vmx->vcpu.arch.nmi_injected = true;
4156                 /*
4157                  * SDM 3: 27.7.1.2 (September 2008)
4158                  * Clear bit "block by NMI" before VM entry if a NMI
4159                  * delivery faulted.
4160                  */
4161                 vmx_set_nmi_mask(&vmx->vcpu, false);
4162                 break;
4163         case INTR_TYPE_SOFT_EXCEPTION:
4164                 vmx->vcpu.arch.event_exit_inst_len =
4165                         vmcs_read32(instr_len_field);
4166                 /* fall through */
4167         case INTR_TYPE_HARD_EXCEPTION:
4168                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
4169                         u32 err = vmcs_read32(error_code_field);
4170                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
4171                 } else
4172                         kvm_queue_exception(&vmx->vcpu, vector);
4173                 break;
4174         case INTR_TYPE_SOFT_INTR:
4175                 vmx->vcpu.arch.event_exit_inst_len =
4176                         vmcs_read32(instr_len_field);
4177                 /* fall through */
4178         case INTR_TYPE_EXT_INTR:
4179                 kvm_queue_interrupt(&vmx->vcpu, vector,
4180                         type == INTR_TYPE_SOFT_INTR);
4181                 break;
4182         default:
4183                 break;
4184         }
4185 }
4186
4187 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
4188 {
4189         __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
4190                                   VM_EXIT_INSTRUCTION_LEN,
4191                                   IDT_VECTORING_ERROR_CODE);
4192 }
4193
4194 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
4195 {
4196         __vmx_complete_interrupts(to_vmx(vcpu),
4197                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
4198                                   VM_ENTRY_INSTRUCTION_LEN,
4199                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
4200
4201         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
4202 }
4203
4204 #ifdef CONFIG_X86_64
4205 #define R "r"
4206 #define Q "q"
4207 #else
4208 #define R "e"
4209 #define Q "l"
4210 #endif
4211
4212 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
4213 {
4214         struct vcpu_vmx *vmx = to_vmx(vcpu);
4215
4216         /* Record the guest's net vcpu time for enforced NMI injections. */
4217         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
4218                 vmx->entry_time = ktime_get();
4219
4220         /* Don't enter VMX if guest state is invalid, let the exit handler
4221            start emulation until we arrive back to a valid state */
4222         if (vmx->emulation_required && emulate_invalid_guest_state)
4223                 return;
4224
4225         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
4226                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
4227         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
4228                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
4229
4230         /* When single-stepping over STI and MOV SS, we must clear the
4231          * corresponding interruptibility bits in the guest state. Otherwise
4232          * vmentry fails as it then expects bit 14 (BS) in pending debug
4233          * exceptions being set, but that's not correct for the guest debugging
4234          * case. */
4235         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
4236                 vmx_set_interrupt_shadow(vcpu, 0);
4237
4238         vmx->__launched = vmx->loaded_vmcs->launched;
4239         asm(
4240                 /* Store host registers */
4241                 "push %%"R"dx; push %%"R"bp;"
4242                 "push %%"R"cx \n\t" /* placeholder for guest rcx */
4243                 "push %%"R"cx \n\t"
4244                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
4245                 "je 1f \n\t"
4246                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4247                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
4248                 "1: \n\t"
4249                 /* Reload cr2 if changed */
4250                 "mov %c[cr2](%0), %%"R"ax \n\t"
4251                 "mov %%cr2, %%"R"dx \n\t"
4252                 "cmp %%"R"ax, %%"R"dx \n\t"
4253                 "je 2f \n\t"
4254                 "mov %%"R"ax, %%cr2 \n\t"
4255                 "2: \n\t"
4256                 /* Check if vmlaunch of vmresume is needed */
4257                 "cmpl $0, %c[launched](%0) \n\t"
4258                 /* Load guest registers.  Don't clobber flags. */
4259                 "mov %c[rax](%0), %%"R"ax \n\t"
4260                 "mov %c[rbx](%0), %%"R"bx \n\t"
4261                 "mov %c[rdx](%0), %%"R"dx \n\t"
4262                 "mov %c[rsi](%0), %%"R"si \n\t"
4263                 "mov %c[rdi](%0), %%"R"di \n\t"
4264                 "mov %c[rbp](%0), %%"R"bp \n\t"
4265 #ifdef CONFIG_X86_64
4266                 "mov %c[r8](%0),  %%r8  \n\t"
4267                 "mov %c[r9](%0),  %%r9  \n\t"
4268                 "mov %c[r10](%0), %%r10 \n\t"
4269                 "mov %c[r11](%0), %%r11 \n\t"
4270                 "mov %c[r12](%0), %%r12 \n\t"
4271                 "mov %c[r13](%0), %%r13 \n\t"
4272                 "mov %c[r14](%0), %%r14 \n\t"
4273                 "mov %c[r15](%0), %%r15 \n\t"
4274 #endif
4275                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
4276
4277                 /* Enter guest mode */
4278                 "jne .Llaunched \n\t"
4279                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
4280                 "jmp .Lkvm_vmx_return \n\t"
4281                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
4282                 ".Lkvm_vmx_return: "
4283                 /* Save guest registers, load host registers, keep flags */
4284                 "mov %0, %c[wordsize](%%"R"sp) \n\t"
4285                 "pop %0 \n\t"
4286                 "mov %%"R"ax, %c[rax](%0) \n\t"
4287                 "mov %%"R"bx, %c[rbx](%0) \n\t"
4288                 "pop"Q" %c[rcx](%0) \n\t"
4289                 "mov %%"R"dx, %c[rdx](%0) \n\t"
4290                 "mov %%"R"si, %c[rsi](%0) \n\t"
4291                 "mov %%"R"di, %c[rdi](%0) \n\t"
4292                 "mov %%"R"bp, %c[rbp](%0) \n\t"
4293 #ifdef CONFIG_X86_64
4294                 "mov %%r8,  %c[r8](%0) \n\t"
4295                 "mov %%r9,  %c[r9](%0) \n\t"
4296                 "mov %%r10, %c[r10](%0) \n\t"
4297                 "mov %%r11, %c[r11](%0) \n\t"
4298                 "mov %%r12, %c[r12](%0) \n\t"
4299                 "mov %%r13, %c[r13](%0) \n\t"
4300                 "mov %%r14, %c[r14](%0) \n\t"
4301                 "mov %%r15, %c[r15](%0) \n\t"
4302 #endif
4303                 "mov %%cr2, %%"R"ax   \n\t"
4304                 "mov %%"R"ax, %c[cr2](%0) \n\t"
4305
4306                 "pop  %%"R"bp; pop  %%"R"dx \n\t"
4307                 "setbe %c[fail](%0) \n\t"
4308               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
4309                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
4310                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
4311                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
4312                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
4313                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
4314                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
4315                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
4316                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
4317                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
4318                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
4319 #ifdef CONFIG_X86_64
4320                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
4321                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
4322                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
4323                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
4324                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4325                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4326                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4327                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
4328 #endif
4329                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
4330                 [wordsize]"i"(sizeof(ulong))
4331               : "cc", "memory"
4332                 , R"ax", R"bx", R"di", R"si"
4333 #ifdef CONFIG_X86_64
4334                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4335 #endif
4336               );
4337
4338         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
4339                                   | (1 << VCPU_EXREG_RFLAGS)
4340                                   | (1 << VCPU_EXREG_CPL)
4341                                   | (1 << VCPU_EXREG_PDPTR)
4342                                   | (1 << VCPU_EXREG_SEGMENTS)
4343                                   | (1 << VCPU_EXREG_CR3));
4344         vcpu->arch.regs_dirty = 0;
4345
4346         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
4347
4348         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
4349         vmx->loaded_vmcs->launched = 1;
4350
4351         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
4352
4353         vmx_complete_atomic_exit(vmx);
4354         vmx_recover_nmi_blocking(vmx);
4355         vmx_complete_interrupts(vmx);
4356 }
4357
4358 #undef R
4359 #undef Q
4360
4361 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4362 {
4363         struct vcpu_vmx *vmx = to_vmx(vcpu);
4364
4365         free_vpid(vmx);
4366         free_loaded_vmcs(vmx->loaded_vmcs);
4367         kfree(vmx->guest_msrs);
4368         kvm_vcpu_uninit(vcpu);
4369         kmem_cache_free(kvm_vcpu_cache, vmx);
4370 }
4371
4372 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
4373 {
4374         int err;
4375         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
4376         int cpu;
4377
4378         if (!vmx)
4379                 return ERR_PTR(-ENOMEM);
4380
4381         allocate_vpid(vmx);
4382
4383         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4384         if (err)
4385                 goto free_vcpu;
4386
4387         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
4388         err = -ENOMEM;
4389         if (!vmx->guest_msrs) {
4390                 goto uninit_vcpu;
4391         }
4392
4393         vmx->loaded_vmcs = &vmx->vmcs01;
4394         vmx->loaded_vmcs->vmcs = alloc_vmcs();
4395         if (!vmx->loaded_vmcs->vmcs)
4396                 goto free_msrs;
4397         if (!vmm_exclusive)
4398                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
4399         loaded_vmcs_init(vmx->loaded_vmcs);
4400         if (!vmm_exclusive)
4401                 kvm_cpu_vmxoff();
4402
4403         cpu = get_cpu();
4404         vmx_vcpu_load(&vmx->vcpu, cpu);
4405         vmx->vcpu.cpu = cpu;
4406         err = vmx_vcpu_setup(vmx);
4407         vmx_vcpu_put(&vmx->vcpu);
4408         put_cpu();
4409         if (err)
4410                 goto free_vmcs;
4411         if (vm_need_virtualize_apic_accesses(kvm))
4412                 err = alloc_apic_access_page(kvm);
4413                 if (err)
4414                         goto free_vmcs;
4415
4416         if (enable_ept) {
4417                 if (!kvm->arch.ept_identity_map_addr)
4418                         kvm->arch.ept_identity_map_addr =
4419                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
4420                 err = -ENOMEM;
4421                 if (alloc_identity_pagetable(kvm) != 0)
4422                         goto free_vmcs;
4423                 if (!init_rmode_identity_map(kvm))
4424                         goto free_vmcs;
4425         }
4426
4427         return &vmx->vcpu;
4428
4429 free_vmcs:
4430         free_vmcs(vmx->loaded_vmcs->vmcs);
4431 free_msrs:
4432         kfree(vmx->guest_msrs);
4433 uninit_vcpu:
4434         kvm_vcpu_uninit(&vmx->vcpu);
4435 free_vcpu:
4436         free_vpid(vmx);
4437         kmem_cache_free(kvm_vcpu_cache, vmx);
4438         return ERR_PTR(err);
4439 }
4440
4441 static void __init vmx_check_processor_compat(void *rtn)
4442 {
4443         struct vmcs_config vmcs_conf;
4444
4445         *(int *)rtn = 0;
4446         if (setup_vmcs_config(&vmcs_conf) < 0)
4447                 *(int *)rtn = -EIO;
4448         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4449                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4450                                 smp_processor_id());
4451                 *(int *)rtn = -EIO;
4452         }
4453 }
4454
4455 static int get_ept_level(void)
4456 {
4457         return VMX_EPT_DEFAULT_GAW + 1;
4458 }
4459
4460 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4461 {
4462         u64 ret;
4463
4464         /* For VT-d and EPT combination
4465          * 1. MMIO: always map as UC
4466          * 2. EPT with VT-d:
4467          *   a. VT-d without snooping control feature: can't guarantee the
4468          *      result, try to trust guest.
4469          *   b. VT-d with snooping control feature: snooping control feature of
4470          *      VT-d engine can guarantee the cache correctness. Just set it
4471          *      to WB to keep consistent with host. So the same as item 3.
4472          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
4473          *    consistent with host MTRR
4474          */
4475         if (is_mmio)
4476                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
4477         else if (vcpu->kvm->arch.iommu_domain &&
4478                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4479                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4480                       VMX_EPT_MT_EPTE_SHIFT;
4481         else
4482                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
4483                         | VMX_EPT_IPAT_BIT;
4484
4485         return ret;
4486 }
4487
4488 #define _ER(x) { EXIT_REASON_##x, #x }
4489
4490 static const struct trace_print_flags vmx_exit_reasons_str[] = {
4491         _ER(EXCEPTION_NMI),
4492         _ER(EXTERNAL_INTERRUPT),
4493         _ER(TRIPLE_FAULT),
4494         _ER(PENDING_INTERRUPT),
4495         _ER(NMI_WINDOW),
4496         _ER(TASK_SWITCH),
4497         _ER(CPUID),
4498         _ER(HLT),
4499         _ER(INVLPG),
4500         _ER(RDPMC),
4501         _ER(RDTSC),
4502         _ER(VMCALL),
4503         _ER(VMCLEAR),
4504         _ER(VMLAUNCH),
4505         _ER(VMPTRLD),
4506         _ER(VMPTRST),
4507         _ER(VMREAD),
4508         _ER(VMRESUME),
4509         _ER(VMWRITE),
4510         _ER(VMOFF),
4511         _ER(VMON),
4512         _ER(CR_ACCESS),
4513         _ER(DR_ACCESS),
4514         _ER(IO_INSTRUCTION),
4515         _ER(MSR_READ),
4516         _ER(MSR_WRITE),
4517         _ER(MWAIT_INSTRUCTION),
4518         _ER(MONITOR_INSTRUCTION),
4519         _ER(PAUSE_INSTRUCTION),
4520         _ER(MCE_DURING_VMENTRY),
4521         _ER(TPR_BELOW_THRESHOLD),
4522         _ER(APIC_ACCESS),
4523         _ER(EPT_VIOLATION),
4524         _ER(EPT_MISCONFIG),
4525         _ER(WBINVD),
4526         { -1, NULL }
4527 };
4528
4529 #undef _ER
4530
4531 static int vmx_get_lpage_level(void)
4532 {
4533         if (enable_ept && !cpu_has_vmx_ept_1g_page())
4534                 return PT_DIRECTORY_LEVEL;
4535         else
4536                 /* For shadow and EPT supported 1GB page */
4537                 return PT_PDPE_LEVEL;
4538 }
4539
4540 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4541 {
4542         struct kvm_cpuid_entry2 *best;
4543         struct vcpu_vmx *vmx = to_vmx(vcpu);
4544         u32 exec_control;
4545
4546         vmx->rdtscp_enabled = false;
4547         if (vmx_rdtscp_supported()) {
4548                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4549                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4550                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4551                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4552                                 vmx->rdtscp_enabled = true;
4553                         else {
4554                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4555                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4556                                                 exec_control);
4557                         }
4558                 }
4559         }
4560 }
4561
4562 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4563 {
4564 }
4565
4566 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
4567                                struct x86_instruction_info *info,
4568                                enum x86_intercept_stage stage)
4569 {
4570         return X86EMUL_CONTINUE;
4571 }
4572
4573 static struct kvm_x86_ops vmx_x86_ops = {
4574         .cpu_has_kvm_support = cpu_has_kvm_support,
4575         .disabled_by_bios = vmx_disabled_by_bios,
4576         .hardware_setup = hardware_setup,
4577         .hardware_unsetup = hardware_unsetup,
4578         .check_processor_compatibility = vmx_check_processor_compat,
4579         .hardware_enable = hardware_enable,
4580         .hardware_disable = hardware_disable,
4581         .cpu_has_accelerated_tpr = report_flexpriority,
4582
4583         .vcpu_create = vmx_create_vcpu,
4584         .vcpu_free = vmx_free_vcpu,
4585         .vcpu_reset = vmx_vcpu_reset,
4586
4587         .prepare_guest_switch = vmx_save_host_state,
4588         .vcpu_load = vmx_vcpu_load,
4589         .vcpu_put = vmx_vcpu_put,
4590
4591         .set_guest_debug = set_guest_debug,
4592         .get_msr = vmx_get_msr,
4593         .set_msr = vmx_set_msr,
4594         .get_segment_base = vmx_get_segment_base,
4595         .get_segment = vmx_get_segment,
4596         .set_segment = vmx_set_segment,
4597         .get_cpl = vmx_get_cpl,
4598         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4599         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
4600         .decache_cr3 = vmx_decache_cr3,
4601         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4602         .set_cr0 = vmx_set_cr0,
4603         .set_cr3 = vmx_set_cr3,
4604         .set_cr4 = vmx_set_cr4,
4605         .set_efer = vmx_set_efer,
4606         .get_idt = vmx_get_idt,
4607         .set_idt = vmx_set_idt,
4608         .get_gdt = vmx_get_gdt,
4609         .set_gdt = vmx_set_gdt,
4610         .set_dr7 = vmx_set_dr7,
4611         .cache_reg = vmx_cache_reg,
4612         .get_rflags = vmx_get_rflags,
4613         .set_rflags = vmx_set_rflags,
4614         .fpu_activate = vmx_fpu_activate,
4615         .fpu_deactivate = vmx_fpu_deactivate,
4616
4617         .tlb_flush = vmx_flush_tlb,
4618
4619         .run = vmx_vcpu_run,
4620         .handle_exit = vmx_handle_exit,
4621         .skip_emulated_instruction = skip_emulated_instruction,
4622         .set_interrupt_shadow = vmx_set_interrupt_shadow,
4623         .get_interrupt_shadow = vmx_get_interrupt_shadow,
4624         .patch_hypercall = vmx_patch_hypercall,
4625         .set_irq = vmx_inject_irq,
4626         .set_nmi = vmx_inject_nmi,
4627         .queue_exception = vmx_queue_exception,
4628         .cancel_injection = vmx_cancel_injection,
4629         .interrupt_allowed = vmx_interrupt_allowed,
4630         .nmi_allowed = vmx_nmi_allowed,
4631         .get_nmi_mask = vmx_get_nmi_mask,
4632         .set_nmi_mask = vmx_set_nmi_mask,
4633         .enable_nmi_window = enable_nmi_window,
4634         .enable_irq_window = enable_irq_window,
4635         .update_cr8_intercept = update_cr8_intercept,
4636
4637         .set_tss_addr = vmx_set_tss_addr,
4638         .get_tdp_level = get_ept_level,
4639         .get_mt_mask = vmx_get_mt_mask,
4640
4641         .get_exit_info = vmx_get_exit_info,
4642         .exit_reasons_str = vmx_exit_reasons_str,
4643
4644         .get_lpage_level = vmx_get_lpage_level,
4645
4646         .cpuid_update = vmx_cpuid_update,
4647
4648         .rdtscp_supported = vmx_rdtscp_supported,
4649
4650         .set_supported_cpuid = vmx_set_supported_cpuid,
4651
4652         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
4653
4654         .set_tsc_khz = vmx_set_tsc_khz,
4655         .write_tsc_offset = vmx_write_tsc_offset,
4656         .adjust_tsc_offset = vmx_adjust_tsc_offset,
4657         .compute_tsc_offset = vmx_compute_tsc_offset,
4658
4659         .set_tdp_cr3 = vmx_set_cr3,
4660
4661         .check_intercept = vmx_check_intercept,
4662 };
4663
4664 static int __init vmx_init(void)
4665 {
4666         int r, i;
4667
4668         rdmsrl_safe(MSR_EFER, &host_efer);
4669
4670         for (i = 0; i < NR_VMX_MSR; ++i)
4671                 kvm_define_shared_msr(i, vmx_msr_index[i]);
4672
4673         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4674         if (!vmx_io_bitmap_a)
4675                 return -ENOMEM;
4676
4677         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4678         if (!vmx_io_bitmap_b) {
4679                 r = -ENOMEM;
4680                 goto out;
4681         }
4682
4683         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4684         if (!vmx_msr_bitmap_legacy) {
4685                 r = -ENOMEM;
4686                 goto out1;
4687         }
4688
4689         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4690         if (!vmx_msr_bitmap_longmode) {
4691                 r = -ENOMEM;
4692                 goto out2;
4693         }
4694
4695         /*
4696          * Allow direct access to the PC debug port (it is often used for I/O
4697          * delays, but the vmexits simply slow things down).
4698          */
4699         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4700         clear_bit(0x80, vmx_io_bitmap_a);
4701
4702         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4703
4704         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4705         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4706
4707         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4708
4709         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4710                      __alignof__(struct vcpu_vmx), THIS_MODULE);
4711         if (r)
4712                 goto out3;
4713
4714         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4715         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4716         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4717         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4718         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4719         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4720
4721         if (enable_ept) {
4722                 bypass_guest_pf = 0;
4723                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4724                                 VMX_EPT_EXECUTABLE_MASK);
4725                 kvm_enable_tdp();
4726         } else
4727                 kvm_disable_tdp();
4728
4729         if (bypass_guest_pf)
4730                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4731
4732         return 0;
4733
4734 out3:
4735         free_page((unsigned long)vmx_msr_bitmap_longmode);
4736 out2:
4737         free_page((unsigned long)vmx_msr_bitmap_legacy);
4738 out1:
4739         free_page((unsigned long)vmx_io_bitmap_b);
4740 out:
4741         free_page((unsigned long)vmx_io_bitmap_a);
4742         return r;
4743 }
4744
4745 static void __exit vmx_exit(void)
4746 {
4747         free_page((unsigned long)vmx_msr_bitmap_legacy);
4748         free_page((unsigned long)vmx_msr_bitmap_longmode);
4749         free_page((unsigned long)vmx_io_bitmap_b);
4750         free_page((unsigned long)vmx_io_bitmap_a);
4751
4752         kvm_exit();
4753 }
4754
4755 module_init(vmx_init)
4756 module_exit(vmx_exit)