x86: remove the second argument of k[un]map_atomic()
[linux-3.10.git] / arch / x86 / kvm / lapic.c
1
2 /*
3  * Local APIC virtualization
4  *
5  * Copyright (C) 2006 Qumranet, Inc.
6  * Copyright (C) 2007 Novell
7  * Copyright (C) 2007 Intel
8  * Copyright 2009 Red Hat, Inc. and/or its affiliates.
9  *
10  * Authors:
11  *   Dor Laor <dor.laor@qumranet.com>
12  *   Gregory Haskins <ghaskins@novell.com>
13  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
14  *
15  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
16  *
17  * This work is licensed under the terms of the GNU GPL, version 2.  See
18  * the COPYING file in the top-level directory.
19  */
20
21 #include <linux/kvm_host.h>
22 #include <linux/kvm.h>
23 #include <linux/mm.h>
24 #include <linux/highmem.h>
25 #include <linux/smp.h>
26 #include <linux/hrtimer.h>
27 #include <linux/io.h>
28 #include <linux/module.h>
29 #include <linux/math64.h>
30 #include <linux/slab.h>
31 #include <asm/processor.h>
32 #include <asm/msr.h>
33 #include <asm/page.h>
34 #include <asm/current.h>
35 #include <asm/apicdef.h>
36 #include <linux/atomic.h>
37 #include "kvm_cache_regs.h"
38 #include "irq.h"
39 #include "trace.h"
40 #include "x86.h"
41 #include "cpuid.h"
42
43 #ifndef CONFIG_X86_64
44 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
45 #else
46 #define mod_64(x, y) ((x) % (y))
47 #endif
48
49 #define PRId64 "d"
50 #define PRIx64 "llx"
51 #define PRIu64 "u"
52 #define PRIo64 "o"
53
54 #define APIC_BUS_CYCLE_NS 1
55
56 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
57 #define apic_debug(fmt, arg...)
58
59 #define APIC_LVT_NUM                    6
60 /* 14 is the version for Xeon and Pentium 8.4.8*/
61 #define APIC_VERSION                    (0x14UL | ((APIC_LVT_NUM - 1) << 16))
62 #define LAPIC_MMIO_LENGTH               (1 << 12)
63 /* followed define is not in apicdef.h */
64 #define APIC_SHORT_MASK                 0xc0000
65 #define APIC_DEST_NOSHORT               0x0
66 #define APIC_DEST_MASK                  0x800
67 #define MAX_APIC_VECTOR                 256
68
69 #define VEC_POS(v) ((v) & (32 - 1))
70 #define REG_POS(v) (((v) >> 5) << 4)
71
72 static unsigned int min_timer_period_us = 500;
73 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
74
75 static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
76 {
77         return *((u32 *) (apic->regs + reg_off));
78 }
79
80 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
81 {
82         *((u32 *) (apic->regs + reg_off)) = val;
83 }
84
85 static inline int apic_test_and_set_vector(int vec, void *bitmap)
86 {
87         return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
88 }
89
90 static inline int apic_test_and_clear_vector(int vec, void *bitmap)
91 {
92         return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
93 }
94
95 static inline void apic_set_vector(int vec, void *bitmap)
96 {
97         set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
98 }
99
100 static inline void apic_clear_vector(int vec, void *bitmap)
101 {
102         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
103 }
104
105 static inline int apic_hw_enabled(struct kvm_lapic *apic)
106 {
107         return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
108 }
109
110 static inline int  apic_sw_enabled(struct kvm_lapic *apic)
111 {
112         return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
113 }
114
115 static inline int apic_enabled(struct kvm_lapic *apic)
116 {
117         return apic_sw_enabled(apic) && apic_hw_enabled(apic);
118 }
119
120 #define LVT_MASK        \
121         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
122
123 #define LINT_MASK       \
124         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
125          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
126
127 static inline int kvm_apic_id(struct kvm_lapic *apic)
128 {
129         return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
130 }
131
132 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
133 {
134         return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
135 }
136
137 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
138 {
139         return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
140 }
141
142 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
143 {
144         return ((apic_get_reg(apic, APIC_LVTT) &
145                 apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_ONESHOT);
146 }
147
148 static inline int apic_lvtt_period(struct kvm_lapic *apic)
149 {
150         return ((apic_get_reg(apic, APIC_LVTT) &
151                 apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_PERIODIC);
152 }
153
154 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
155 {
156         return ((apic_get_reg(apic, APIC_LVTT) &
157                 apic->lapic_timer.timer_mode_mask) ==
158                         APIC_LVT_TIMER_TSCDEADLINE);
159 }
160
161 static inline int apic_lvt_nmi_mode(u32 lvt_val)
162 {
163         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
164 }
165
166 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
167 {
168         struct kvm_lapic *apic = vcpu->arch.apic;
169         struct kvm_cpuid_entry2 *feat;
170         u32 v = APIC_VERSION;
171
172         if (!irqchip_in_kernel(vcpu->kvm))
173                 return;
174
175         feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
176         if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
177                 v |= APIC_LVR_DIRECTED_EOI;
178         apic_set_reg(apic, APIC_LVR, v);
179 }
180
181 static inline int apic_x2apic_mode(struct kvm_lapic *apic)
182 {
183         return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
184 }
185
186 static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
187         LVT_MASK ,      /* part LVTT mask, timer mode mask added at runtime */
188         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
189         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
190         LINT_MASK, LINT_MASK,   /* LVT0-1 */
191         LVT_MASK                /* LVTERR */
192 };
193
194 static int find_highest_vector(void *bitmap)
195 {
196         u32 *word = bitmap;
197         int word_offset = MAX_APIC_VECTOR >> 5;
198
199         while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
200                 continue;
201
202         if (likely(!word_offset && !word[0]))
203                 return -1;
204         else
205                 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
206 }
207
208 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
209 {
210         apic->irr_pending = true;
211         return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
212 }
213
214 static inline int apic_search_irr(struct kvm_lapic *apic)
215 {
216         return find_highest_vector(apic->regs + APIC_IRR);
217 }
218
219 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
220 {
221         int result;
222
223         if (!apic->irr_pending)
224                 return -1;
225
226         result = apic_search_irr(apic);
227         ASSERT(result == -1 || result >= 16);
228
229         return result;
230 }
231
232 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
233 {
234         apic->irr_pending = false;
235         apic_clear_vector(vec, apic->regs + APIC_IRR);
236         if (apic_search_irr(apic) != -1)
237                 apic->irr_pending = true;
238 }
239
240 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
241 {
242         struct kvm_lapic *apic = vcpu->arch.apic;
243         int highest_irr;
244
245         /* This may race with setting of irr in __apic_accept_irq() and
246          * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
247          * will cause vmexit immediately and the value will be recalculated
248          * on the next vmentry.
249          */
250         if (!apic)
251                 return 0;
252         highest_irr = apic_find_highest_irr(apic);
253
254         return highest_irr;
255 }
256
257 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
258                              int vector, int level, int trig_mode);
259
260 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq)
261 {
262         struct kvm_lapic *apic = vcpu->arch.apic;
263
264         return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
265                         irq->level, irq->trig_mode);
266 }
267
268 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
269 {
270         int result;
271
272         result = find_highest_vector(apic->regs + APIC_ISR);
273         ASSERT(result == -1 || result >= 16);
274
275         return result;
276 }
277
278 static void apic_update_ppr(struct kvm_lapic *apic)
279 {
280         u32 tpr, isrv, ppr, old_ppr;
281         int isr;
282
283         old_ppr = apic_get_reg(apic, APIC_PROCPRI);
284         tpr = apic_get_reg(apic, APIC_TASKPRI);
285         isr = apic_find_highest_isr(apic);
286         isrv = (isr != -1) ? isr : 0;
287
288         if ((tpr & 0xf0) >= (isrv & 0xf0))
289                 ppr = tpr & 0xff;
290         else
291                 ppr = isrv & 0xf0;
292
293         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
294                    apic, ppr, isr, isrv);
295
296         if (old_ppr != ppr) {
297                 apic_set_reg(apic, APIC_PROCPRI, ppr);
298                 if (ppr < old_ppr)
299                         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
300         }
301 }
302
303 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
304 {
305         apic_set_reg(apic, APIC_TASKPRI, tpr);
306         apic_update_ppr(apic);
307 }
308
309 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
310 {
311         return dest == 0xff || kvm_apic_id(apic) == dest;
312 }
313
314 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
315 {
316         int result = 0;
317         u32 logical_id;
318
319         if (apic_x2apic_mode(apic)) {
320                 logical_id = apic_get_reg(apic, APIC_LDR);
321                 return logical_id & mda;
322         }
323
324         logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
325
326         switch (apic_get_reg(apic, APIC_DFR)) {
327         case APIC_DFR_FLAT:
328                 if (logical_id & mda)
329                         result = 1;
330                 break;
331         case APIC_DFR_CLUSTER:
332                 if (((logical_id >> 4) == (mda >> 0x4))
333                     && (logical_id & mda & 0xf))
334                         result = 1;
335                 break;
336         default:
337                 apic_debug("Bad DFR vcpu %d: %08x\n",
338                            apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
339                 break;
340         }
341
342         return result;
343 }
344
345 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
346                            int short_hand, int dest, int dest_mode)
347 {
348         int result = 0;
349         struct kvm_lapic *target = vcpu->arch.apic;
350
351         apic_debug("target %p, source %p, dest 0x%x, "
352                    "dest_mode 0x%x, short_hand 0x%x\n",
353                    target, source, dest, dest_mode, short_hand);
354
355         ASSERT(target);
356         switch (short_hand) {
357         case APIC_DEST_NOSHORT:
358                 if (dest_mode == 0)
359                         /* Physical mode. */
360                         result = kvm_apic_match_physical_addr(target, dest);
361                 else
362                         /* Logical mode. */
363                         result = kvm_apic_match_logical_addr(target, dest);
364                 break;
365         case APIC_DEST_SELF:
366                 result = (target == source);
367                 break;
368         case APIC_DEST_ALLINC:
369                 result = 1;
370                 break;
371         case APIC_DEST_ALLBUT:
372                 result = (target != source);
373                 break;
374         default:
375                 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
376                            short_hand);
377                 break;
378         }
379
380         return result;
381 }
382
383 /*
384  * Add a pending IRQ into lapic.
385  * Return 1 if successfully added and 0 if discarded.
386  */
387 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
388                              int vector, int level, int trig_mode)
389 {
390         int result = 0;
391         struct kvm_vcpu *vcpu = apic->vcpu;
392
393         switch (delivery_mode) {
394         case APIC_DM_LOWEST:
395                 vcpu->arch.apic_arb_prio++;
396         case APIC_DM_FIXED:
397                 /* FIXME add logic for vcpu on reset */
398                 if (unlikely(!apic_enabled(apic)))
399                         break;
400
401                 if (trig_mode) {
402                         apic_debug("level trig mode for vector %d", vector);
403                         apic_set_vector(vector, apic->regs + APIC_TMR);
404                 } else
405                         apic_clear_vector(vector, apic->regs + APIC_TMR);
406
407                 result = !apic_test_and_set_irr(vector, apic);
408                 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
409                                           trig_mode, vector, !result);
410                 if (!result) {
411                         if (trig_mode)
412                                 apic_debug("level trig mode repeatedly for "
413                                                 "vector %d", vector);
414                         break;
415                 }
416
417                 kvm_make_request(KVM_REQ_EVENT, vcpu);
418                 kvm_vcpu_kick(vcpu);
419                 break;
420
421         case APIC_DM_REMRD:
422                 apic_debug("Ignoring delivery mode 3\n");
423                 break;
424
425         case APIC_DM_SMI:
426                 apic_debug("Ignoring guest SMI\n");
427                 break;
428
429         case APIC_DM_NMI:
430                 result = 1;
431                 kvm_inject_nmi(vcpu);
432                 kvm_vcpu_kick(vcpu);
433                 break;
434
435         case APIC_DM_INIT:
436                 if (level) {
437                         result = 1;
438                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
439                         kvm_make_request(KVM_REQ_EVENT, vcpu);
440                         kvm_vcpu_kick(vcpu);
441                 } else {
442                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
443                                    vcpu->vcpu_id);
444                 }
445                 break;
446
447         case APIC_DM_STARTUP:
448                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
449                            vcpu->vcpu_id, vector);
450                 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
451                         result = 1;
452                         vcpu->arch.sipi_vector = vector;
453                         vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
454                         kvm_make_request(KVM_REQ_EVENT, vcpu);
455                         kvm_vcpu_kick(vcpu);
456                 }
457                 break;
458
459         case APIC_DM_EXTINT:
460                 /*
461                  * Should only be called by kvm_apic_local_deliver() with LVT0,
462                  * before NMI watchdog was enabled. Already handled by
463                  * kvm_apic_accept_pic_intr().
464                  */
465                 break;
466
467         default:
468                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
469                        delivery_mode);
470                 break;
471         }
472         return result;
473 }
474
475 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
476 {
477         return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
478 }
479
480 static void apic_set_eoi(struct kvm_lapic *apic)
481 {
482         int vector = apic_find_highest_isr(apic);
483         int trigger_mode;
484         /*
485          * Not every write EOI will has corresponding ISR,
486          * one example is when Kernel check timer on setup_IO_APIC
487          */
488         if (vector == -1)
489                 return;
490
491         apic_clear_vector(vector, apic->regs + APIC_ISR);
492         apic_update_ppr(apic);
493
494         if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
495                 trigger_mode = IOAPIC_LEVEL_TRIG;
496         else
497                 trigger_mode = IOAPIC_EDGE_TRIG;
498         if (!(apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI))
499                 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
500         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
501 }
502
503 static void apic_send_ipi(struct kvm_lapic *apic)
504 {
505         u32 icr_low = apic_get_reg(apic, APIC_ICR);
506         u32 icr_high = apic_get_reg(apic, APIC_ICR2);
507         struct kvm_lapic_irq irq;
508
509         irq.vector = icr_low & APIC_VECTOR_MASK;
510         irq.delivery_mode = icr_low & APIC_MODE_MASK;
511         irq.dest_mode = icr_low & APIC_DEST_MASK;
512         irq.level = icr_low & APIC_INT_ASSERT;
513         irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
514         irq.shorthand = icr_low & APIC_SHORT_MASK;
515         if (apic_x2apic_mode(apic))
516                 irq.dest_id = icr_high;
517         else
518                 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
519
520         trace_kvm_apic_ipi(icr_low, irq.dest_id);
521
522         apic_debug("icr_high 0x%x, icr_low 0x%x, "
523                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
524                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
525                    icr_high, icr_low, irq.shorthand, irq.dest_id,
526                    irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
527                    irq.vector);
528
529         kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq);
530 }
531
532 static u32 apic_get_tmcct(struct kvm_lapic *apic)
533 {
534         ktime_t remaining;
535         s64 ns;
536         u32 tmcct;
537
538         ASSERT(apic != NULL);
539
540         /* if initial count is 0, current count should also be 0 */
541         if (apic_get_reg(apic, APIC_TMICT) == 0)
542                 return 0;
543
544         remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
545         if (ktime_to_ns(remaining) < 0)
546                 remaining = ktime_set(0, 0);
547
548         ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
549         tmcct = div64_u64(ns,
550                          (APIC_BUS_CYCLE_NS * apic->divide_count));
551
552         return tmcct;
553 }
554
555 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
556 {
557         struct kvm_vcpu *vcpu = apic->vcpu;
558         struct kvm_run *run = vcpu->run;
559
560         kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
561         run->tpr_access.rip = kvm_rip_read(vcpu);
562         run->tpr_access.is_write = write;
563 }
564
565 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
566 {
567         if (apic->vcpu->arch.tpr_access_reporting)
568                 __report_tpr_access(apic, write);
569 }
570
571 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
572 {
573         u32 val = 0;
574
575         if (offset >= LAPIC_MMIO_LENGTH)
576                 return 0;
577
578         switch (offset) {
579         case APIC_ID:
580                 if (apic_x2apic_mode(apic))
581                         val = kvm_apic_id(apic);
582                 else
583                         val = kvm_apic_id(apic) << 24;
584                 break;
585         case APIC_ARBPRI:
586                 apic_debug("Access APIC ARBPRI register which is for P6\n");
587                 break;
588
589         case APIC_TMCCT:        /* Timer CCR */
590                 if (apic_lvtt_tscdeadline(apic))
591                         return 0;
592
593                 val = apic_get_tmcct(apic);
594                 break;
595
596         case APIC_TASKPRI:
597                 report_tpr_access(apic, false);
598                 /* fall thru */
599         default:
600                 apic_update_ppr(apic);
601                 val = apic_get_reg(apic, offset);
602                 break;
603         }
604
605         return val;
606 }
607
608 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
609 {
610         return container_of(dev, struct kvm_lapic, dev);
611 }
612
613 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
614                 void *data)
615 {
616         unsigned char alignment = offset & 0xf;
617         u32 result;
618         /* this bitmask has a bit cleared for each reserver register */
619         static const u64 rmask = 0x43ff01ffffffe70cULL;
620
621         if ((alignment + len) > 4) {
622                 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
623                            offset, len);
624                 return 1;
625         }
626
627         if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
628                 apic_debug("KVM_APIC_READ: read reserved register %x\n",
629                            offset);
630                 return 1;
631         }
632
633         result = __apic_read(apic, offset & ~0xf);
634
635         trace_kvm_apic_read(offset, result);
636
637         switch (len) {
638         case 1:
639         case 2:
640         case 4:
641                 memcpy(data, (char *)&result + alignment, len);
642                 break;
643         default:
644                 printk(KERN_ERR "Local APIC read with len = %x, "
645                        "should be 1,2, or 4 instead\n", len);
646                 break;
647         }
648         return 0;
649 }
650
651 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
652 {
653         return apic_hw_enabled(apic) &&
654             addr >= apic->base_address &&
655             addr < apic->base_address + LAPIC_MMIO_LENGTH;
656 }
657
658 static int apic_mmio_read(struct kvm_io_device *this,
659                            gpa_t address, int len, void *data)
660 {
661         struct kvm_lapic *apic = to_lapic(this);
662         u32 offset = address - apic->base_address;
663
664         if (!apic_mmio_in_range(apic, address))
665                 return -EOPNOTSUPP;
666
667         apic_reg_read(apic, offset, len, data);
668
669         return 0;
670 }
671
672 static void update_divide_count(struct kvm_lapic *apic)
673 {
674         u32 tmp1, tmp2, tdcr;
675
676         tdcr = apic_get_reg(apic, APIC_TDCR);
677         tmp1 = tdcr & 0xf;
678         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
679         apic->divide_count = 0x1 << (tmp2 & 0x7);
680
681         apic_debug("timer divide count is 0x%x\n",
682                                    apic->divide_count);
683 }
684
685 static void start_apic_timer(struct kvm_lapic *apic)
686 {
687         ktime_t now;
688         atomic_set(&apic->lapic_timer.pending, 0);
689
690         if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
691                 /* lapic timer in oneshot or peroidic mode */
692                 now = apic->lapic_timer.timer.base->get_time();
693                 apic->lapic_timer.period = (u64)apic_get_reg(apic, APIC_TMICT)
694                             * APIC_BUS_CYCLE_NS * apic->divide_count;
695
696                 if (!apic->lapic_timer.period)
697                         return;
698                 /*
699                  * Do not allow the guest to program periodic timers with small
700                  * interval, since the hrtimers are not throttled by the host
701                  * scheduler.
702                  */
703                 if (apic_lvtt_period(apic)) {
704                         s64 min_period = min_timer_period_us * 1000LL;
705
706                         if (apic->lapic_timer.period < min_period) {
707                                 pr_info_ratelimited(
708                                     "kvm: vcpu %i: requested %lld ns "
709                                     "lapic timer period limited to %lld ns\n",
710                                     apic->vcpu->vcpu_id,
711                                     apic->lapic_timer.period, min_period);
712                                 apic->lapic_timer.period = min_period;
713                         }
714                 }
715
716                 hrtimer_start(&apic->lapic_timer.timer,
717                               ktime_add_ns(now, apic->lapic_timer.period),
718                               HRTIMER_MODE_ABS);
719
720                 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
721                            PRIx64 ", "
722                            "timer initial count 0x%x, period %lldns, "
723                            "expire @ 0x%016" PRIx64 ".\n", __func__,
724                            APIC_BUS_CYCLE_NS, ktime_to_ns(now),
725                            apic_get_reg(apic, APIC_TMICT),
726                            apic->lapic_timer.period,
727                            ktime_to_ns(ktime_add_ns(now,
728                                         apic->lapic_timer.period)));
729         } else if (apic_lvtt_tscdeadline(apic)) {
730                 /* lapic timer in tsc deadline mode */
731                 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
732                 u64 ns = 0;
733                 struct kvm_vcpu *vcpu = apic->vcpu;
734                 unsigned long this_tsc_khz = vcpu_tsc_khz(vcpu);
735                 unsigned long flags;
736
737                 if (unlikely(!tscdeadline || !this_tsc_khz))
738                         return;
739
740                 local_irq_save(flags);
741
742                 now = apic->lapic_timer.timer.base->get_time();
743                 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
744                 if (likely(tscdeadline > guest_tsc)) {
745                         ns = (tscdeadline - guest_tsc) * 1000000ULL;
746                         do_div(ns, this_tsc_khz);
747                 }
748                 hrtimer_start(&apic->lapic_timer.timer,
749                         ktime_add_ns(now, ns), HRTIMER_MODE_ABS);
750
751                 local_irq_restore(flags);
752         }
753 }
754
755 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
756 {
757         int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0));
758
759         if (apic_lvt_nmi_mode(lvt0_val)) {
760                 if (!nmi_wd_enabled) {
761                         apic_debug("Receive NMI setting on APIC_LVT0 "
762                                    "for cpu %d\n", apic->vcpu->vcpu_id);
763                         apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
764                 }
765         } else if (nmi_wd_enabled)
766                 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
767 }
768
769 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
770 {
771         int ret = 0;
772
773         trace_kvm_apic_write(reg, val);
774
775         switch (reg) {
776         case APIC_ID:           /* Local APIC ID */
777                 if (!apic_x2apic_mode(apic))
778                         apic_set_reg(apic, APIC_ID, val);
779                 else
780                         ret = 1;
781                 break;
782
783         case APIC_TASKPRI:
784                 report_tpr_access(apic, true);
785                 apic_set_tpr(apic, val & 0xff);
786                 break;
787
788         case APIC_EOI:
789                 apic_set_eoi(apic);
790                 break;
791
792         case APIC_LDR:
793                 if (!apic_x2apic_mode(apic))
794                         apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
795                 else
796                         ret = 1;
797                 break;
798
799         case APIC_DFR:
800                 if (!apic_x2apic_mode(apic))
801                         apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
802                 else
803                         ret = 1;
804                 break;
805
806         case APIC_SPIV: {
807                 u32 mask = 0x3ff;
808                 if (apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
809                         mask |= APIC_SPIV_DIRECTED_EOI;
810                 apic_set_reg(apic, APIC_SPIV, val & mask);
811                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
812                         int i;
813                         u32 lvt_val;
814
815                         for (i = 0; i < APIC_LVT_NUM; i++) {
816                                 lvt_val = apic_get_reg(apic,
817                                                        APIC_LVTT + 0x10 * i);
818                                 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
819                                              lvt_val | APIC_LVT_MASKED);
820                         }
821                         atomic_set(&apic->lapic_timer.pending, 0);
822
823                 }
824                 break;
825         }
826         case APIC_ICR:
827                 /* No delay here, so we always clear the pending bit */
828                 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
829                 apic_send_ipi(apic);
830                 break;
831
832         case APIC_ICR2:
833                 if (!apic_x2apic_mode(apic))
834                         val &= 0xff000000;
835                 apic_set_reg(apic, APIC_ICR2, val);
836                 break;
837
838         case APIC_LVT0:
839                 apic_manage_nmi_watchdog(apic, val);
840         case APIC_LVTTHMR:
841         case APIC_LVTPC:
842         case APIC_LVT1:
843         case APIC_LVTERR:
844                 /* TODO: Check vector */
845                 if (!apic_sw_enabled(apic))
846                         val |= APIC_LVT_MASKED;
847
848                 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
849                 apic_set_reg(apic, reg, val);
850
851                 break;
852
853         case APIC_LVTT:
854                 if ((apic_get_reg(apic, APIC_LVTT) &
855                     apic->lapic_timer.timer_mode_mask) !=
856                    (val & apic->lapic_timer.timer_mode_mask))
857                         hrtimer_cancel(&apic->lapic_timer.timer);
858
859                 if (!apic_sw_enabled(apic))
860                         val |= APIC_LVT_MASKED;
861                 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
862                 apic_set_reg(apic, APIC_LVTT, val);
863                 break;
864
865         case APIC_TMICT:
866                 if (apic_lvtt_tscdeadline(apic))
867                         break;
868
869                 hrtimer_cancel(&apic->lapic_timer.timer);
870                 apic_set_reg(apic, APIC_TMICT, val);
871                 start_apic_timer(apic);
872                 break;
873
874         case APIC_TDCR:
875                 if (val & 4)
876                         apic_debug("KVM_WRITE:TDCR %x\n", val);
877                 apic_set_reg(apic, APIC_TDCR, val);
878                 update_divide_count(apic);
879                 break;
880
881         case APIC_ESR:
882                 if (apic_x2apic_mode(apic) && val != 0) {
883                         apic_debug("KVM_WRITE:ESR not zero %x\n", val);
884                         ret = 1;
885                 }
886                 break;
887
888         case APIC_SELF_IPI:
889                 if (apic_x2apic_mode(apic)) {
890                         apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
891                 } else
892                         ret = 1;
893                 break;
894         default:
895                 ret = 1;
896                 break;
897         }
898         if (ret)
899                 apic_debug("Local APIC Write to read-only register %x\n", reg);
900         return ret;
901 }
902
903 static int apic_mmio_write(struct kvm_io_device *this,
904                             gpa_t address, int len, const void *data)
905 {
906         struct kvm_lapic *apic = to_lapic(this);
907         unsigned int offset = address - apic->base_address;
908         u32 val;
909
910         if (!apic_mmio_in_range(apic, address))
911                 return -EOPNOTSUPP;
912
913         /*
914          * APIC register must be aligned on 128-bits boundary.
915          * 32/64/128 bits registers must be accessed thru 32 bits.
916          * Refer SDM 8.4.1
917          */
918         if (len != 4 || (offset & 0xf)) {
919                 /* Don't shout loud, $infamous_os would cause only noise. */
920                 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
921                 return 0;
922         }
923
924         val = *(u32*)data;
925
926         /* too common printing */
927         if (offset != APIC_EOI)
928                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
929                            "0x%x\n", __func__, offset, len, val);
930
931         apic_reg_write(apic, offset & 0xff0, val);
932
933         return 0;
934 }
935
936 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
937 {
938         struct kvm_lapic *apic = vcpu->arch.apic;
939
940         if (apic)
941                 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
942 }
943 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
944
945 void kvm_free_lapic(struct kvm_vcpu *vcpu)
946 {
947         if (!vcpu->arch.apic)
948                 return;
949
950         hrtimer_cancel(&vcpu->arch.apic->lapic_timer.timer);
951
952         if (vcpu->arch.apic->regs)
953                 free_page((unsigned long)vcpu->arch.apic->regs);
954
955         kfree(vcpu->arch.apic);
956 }
957
958 /*
959  *----------------------------------------------------------------------
960  * LAPIC interface
961  *----------------------------------------------------------------------
962  */
963
964 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
965 {
966         struct kvm_lapic *apic = vcpu->arch.apic;
967         if (!apic)
968                 return 0;
969
970         if (apic_lvtt_oneshot(apic) || apic_lvtt_period(apic))
971                 return 0;
972
973         return apic->lapic_timer.tscdeadline;
974 }
975
976 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
977 {
978         struct kvm_lapic *apic = vcpu->arch.apic;
979         if (!apic)
980                 return;
981
982         if (apic_lvtt_oneshot(apic) || apic_lvtt_period(apic))
983                 return;
984
985         hrtimer_cancel(&apic->lapic_timer.timer);
986         apic->lapic_timer.tscdeadline = data;
987         start_apic_timer(apic);
988 }
989
990 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
991 {
992         struct kvm_lapic *apic = vcpu->arch.apic;
993
994         if (!apic)
995                 return;
996         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
997                      | (apic_get_reg(apic, APIC_TASKPRI) & 4));
998 }
999
1000 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1001 {
1002         struct kvm_lapic *apic = vcpu->arch.apic;
1003         u64 tpr;
1004
1005         if (!apic)
1006                 return 0;
1007         tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
1008
1009         return (tpr & 0xf0) >> 4;
1010 }
1011
1012 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1013 {
1014         struct kvm_lapic *apic = vcpu->arch.apic;
1015
1016         if (!apic) {
1017                 value |= MSR_IA32_APICBASE_BSP;
1018                 vcpu->arch.apic_base = value;
1019                 return;
1020         }
1021
1022         if (!kvm_vcpu_is_bsp(apic->vcpu))
1023                 value &= ~MSR_IA32_APICBASE_BSP;
1024
1025         vcpu->arch.apic_base = value;
1026         if (apic_x2apic_mode(apic)) {
1027                 u32 id = kvm_apic_id(apic);
1028                 u32 ldr = ((id & ~0xf) << 16) | (1 << (id & 0xf));
1029                 apic_set_reg(apic, APIC_LDR, ldr);
1030         }
1031         apic->base_address = apic->vcpu->arch.apic_base &
1032                              MSR_IA32_APICBASE_BASE;
1033
1034         /* with FSB delivery interrupt, we can restart APIC functionality */
1035         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1036                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1037
1038 }
1039
1040 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
1041 {
1042         struct kvm_lapic *apic;
1043         int i;
1044
1045         apic_debug("%s\n", __func__);
1046
1047         ASSERT(vcpu);
1048         apic = vcpu->arch.apic;
1049         ASSERT(apic != NULL);
1050
1051         /* Stop the timer in case it's a reset to an active apic */
1052         hrtimer_cancel(&apic->lapic_timer.timer);
1053
1054         apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
1055         kvm_apic_set_version(apic->vcpu);
1056
1057         for (i = 0; i < APIC_LVT_NUM; i++)
1058                 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1059         apic_set_reg(apic, APIC_LVT0,
1060                      SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1061
1062         apic_set_reg(apic, APIC_DFR, 0xffffffffU);
1063         apic_set_reg(apic, APIC_SPIV, 0xff);
1064         apic_set_reg(apic, APIC_TASKPRI, 0);
1065         apic_set_reg(apic, APIC_LDR, 0);
1066         apic_set_reg(apic, APIC_ESR, 0);
1067         apic_set_reg(apic, APIC_ICR, 0);
1068         apic_set_reg(apic, APIC_ICR2, 0);
1069         apic_set_reg(apic, APIC_TDCR, 0);
1070         apic_set_reg(apic, APIC_TMICT, 0);
1071         for (i = 0; i < 8; i++) {
1072                 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1073                 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1074                 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1075         }
1076         apic->irr_pending = false;
1077         update_divide_count(apic);
1078         atomic_set(&apic->lapic_timer.pending, 0);
1079         if (kvm_vcpu_is_bsp(vcpu))
1080                 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
1081         apic_update_ppr(apic);
1082
1083         vcpu->arch.apic_arb_prio = 0;
1084
1085         apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
1086                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1087                    vcpu, kvm_apic_id(apic),
1088                    vcpu->arch.apic_base, apic->base_address);
1089 }
1090
1091 bool kvm_apic_present(struct kvm_vcpu *vcpu)
1092 {
1093         return vcpu->arch.apic && apic_hw_enabled(vcpu->arch.apic);
1094 }
1095
1096 int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
1097 {
1098         return kvm_apic_present(vcpu) && apic_sw_enabled(vcpu->arch.apic);
1099 }
1100
1101 /*
1102  *----------------------------------------------------------------------
1103  * timer interface
1104  *----------------------------------------------------------------------
1105  */
1106
1107 static bool lapic_is_periodic(struct kvm_timer *ktimer)
1108 {
1109         struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic,
1110                                               lapic_timer);
1111         return apic_lvtt_period(apic);
1112 }
1113
1114 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1115 {
1116         struct kvm_lapic *lapic = vcpu->arch.apic;
1117
1118         if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT))
1119                 return atomic_read(&lapic->lapic_timer.pending);
1120
1121         return 0;
1122 }
1123
1124 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1125 {
1126         u32 reg = apic_get_reg(apic, lvt_type);
1127         int vector, mode, trig_mode;
1128
1129         if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1130                 vector = reg & APIC_VECTOR_MASK;
1131                 mode = reg & APIC_MODE_MASK;
1132                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1133                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode);
1134         }
1135         return 0;
1136 }
1137
1138 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1139 {
1140         struct kvm_lapic *apic = vcpu->arch.apic;
1141
1142         if (apic)
1143                 kvm_apic_local_deliver(apic, APIC_LVT0);
1144 }
1145
1146 static struct kvm_timer_ops lapic_timer_ops = {
1147         .is_periodic = lapic_is_periodic,
1148 };
1149
1150 static const struct kvm_io_device_ops apic_mmio_ops = {
1151         .read     = apic_mmio_read,
1152         .write    = apic_mmio_write,
1153 };
1154
1155 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1156 {
1157         struct kvm_lapic *apic;
1158
1159         ASSERT(vcpu != NULL);
1160         apic_debug("apic_init %d\n", vcpu->vcpu_id);
1161
1162         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1163         if (!apic)
1164                 goto nomem;
1165
1166         vcpu->arch.apic = apic;
1167
1168         apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1169         if (!apic->regs) {
1170                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1171                        vcpu->vcpu_id);
1172                 goto nomem_free_apic;
1173         }
1174         apic->vcpu = vcpu;
1175
1176         hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1177                      HRTIMER_MODE_ABS);
1178         apic->lapic_timer.timer.function = kvm_timer_fn;
1179         apic->lapic_timer.t_ops = &lapic_timer_ops;
1180         apic->lapic_timer.kvm = vcpu->kvm;
1181         apic->lapic_timer.vcpu = vcpu;
1182
1183         apic->base_address = APIC_DEFAULT_PHYS_BASE;
1184         vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
1185
1186         kvm_lapic_reset(vcpu);
1187         kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1188
1189         return 0;
1190 nomem_free_apic:
1191         kfree(apic);
1192 nomem:
1193         return -ENOMEM;
1194 }
1195
1196 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1197 {
1198         struct kvm_lapic *apic = vcpu->arch.apic;
1199         int highest_irr;
1200
1201         if (!apic || !apic_enabled(apic))
1202                 return -1;
1203
1204         apic_update_ppr(apic);
1205         highest_irr = apic_find_highest_irr(apic);
1206         if ((highest_irr == -1) ||
1207             ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
1208                 return -1;
1209         return highest_irr;
1210 }
1211
1212 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1213 {
1214         u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1215         int r = 0;
1216
1217         if (!apic_hw_enabled(vcpu->arch.apic))
1218                 r = 1;
1219         if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1220             GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1221                 r = 1;
1222         return r;
1223 }
1224
1225 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1226 {
1227         struct kvm_lapic *apic = vcpu->arch.apic;
1228
1229         if (apic && atomic_read(&apic->lapic_timer.pending) > 0) {
1230                 if (kvm_apic_local_deliver(apic, APIC_LVTT))
1231                         atomic_dec(&apic->lapic_timer.pending);
1232         }
1233 }
1234
1235 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1236 {
1237         int vector = kvm_apic_has_interrupt(vcpu);
1238         struct kvm_lapic *apic = vcpu->arch.apic;
1239
1240         if (vector == -1)
1241                 return -1;
1242
1243         apic_set_vector(vector, apic->regs + APIC_ISR);
1244         apic_update_ppr(apic);
1245         apic_clear_irr(vector, apic);
1246         return vector;
1247 }
1248
1249 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1250 {
1251         struct kvm_lapic *apic = vcpu->arch.apic;
1252
1253         apic->base_address = vcpu->arch.apic_base &
1254                              MSR_IA32_APICBASE_BASE;
1255         kvm_apic_set_version(vcpu);
1256
1257         apic_update_ppr(apic);
1258         hrtimer_cancel(&apic->lapic_timer.timer);
1259         update_divide_count(apic);
1260         start_apic_timer(apic);
1261         apic->irr_pending = true;
1262         kvm_make_request(KVM_REQ_EVENT, vcpu);
1263 }
1264
1265 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1266 {
1267         struct kvm_lapic *apic = vcpu->arch.apic;
1268         struct hrtimer *timer;
1269
1270         if (!apic)
1271                 return;
1272
1273         timer = &apic->lapic_timer.timer;
1274         if (hrtimer_cancel(timer))
1275                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1276 }
1277
1278 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1279 {
1280         u32 data;
1281         void *vapic;
1282
1283         if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1284                 return;
1285
1286         vapic = kmap_atomic(vcpu->arch.apic->vapic_page);
1287         data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
1288         kunmap_atomic(vapic);
1289
1290         apic_set_tpr(vcpu->arch.apic, data & 0xff);
1291 }
1292
1293 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1294 {
1295         u32 data, tpr;
1296         int max_irr, max_isr;
1297         struct kvm_lapic *apic;
1298         void *vapic;
1299
1300         if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1301                 return;
1302
1303         apic = vcpu->arch.apic;
1304         tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1305         max_irr = apic_find_highest_irr(apic);
1306         if (max_irr < 0)
1307                 max_irr = 0;
1308         max_isr = apic_find_highest_isr(apic);
1309         if (max_isr < 0)
1310                 max_isr = 0;
1311         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1312
1313         vapic = kmap_atomic(vcpu->arch.apic->vapic_page);
1314         *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1315         kunmap_atomic(vapic);
1316 }
1317
1318 void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1319 {
1320         if (!irqchip_in_kernel(vcpu->kvm))
1321                 return;
1322
1323         vcpu->arch.apic->vapic_addr = vapic_addr;
1324 }
1325
1326 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1327 {
1328         struct kvm_lapic *apic = vcpu->arch.apic;
1329         u32 reg = (msr - APIC_BASE_MSR) << 4;
1330
1331         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1332                 return 1;
1333
1334         /* if this is ICR write vector before command */
1335         if (msr == 0x830)
1336                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1337         return apic_reg_write(apic, reg, (u32)data);
1338 }
1339
1340 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1341 {
1342         struct kvm_lapic *apic = vcpu->arch.apic;
1343         u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1344
1345         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1346                 return 1;
1347
1348         if (apic_reg_read(apic, reg, 4, &low))
1349                 return 1;
1350         if (msr == 0x830)
1351                 apic_reg_read(apic, APIC_ICR2, 4, &high);
1352
1353         *data = (((u64)high) << 32) | low;
1354
1355         return 0;
1356 }
1357
1358 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
1359 {
1360         struct kvm_lapic *apic = vcpu->arch.apic;
1361
1362         if (!irqchip_in_kernel(vcpu->kvm))
1363                 return 1;
1364
1365         /* if this is ICR write vector before command */
1366         if (reg == APIC_ICR)
1367                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1368         return apic_reg_write(apic, reg, (u32)data);
1369 }
1370
1371 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
1372 {
1373         struct kvm_lapic *apic = vcpu->arch.apic;
1374         u32 low, high = 0;
1375
1376         if (!irqchip_in_kernel(vcpu->kvm))
1377                 return 1;
1378
1379         if (apic_reg_read(apic, reg, 4, &low))
1380                 return 1;
1381         if (reg == APIC_ICR)
1382                 apic_reg_read(apic, APIC_ICR2, 4, &high);
1383
1384         *data = (((u64)high) << 32) | low;
1385
1386         return 0;
1387 }