KVM: irq ack notification
[linux-3.10.git] / arch / x86 / kvm / i8259.c
1 /*
2  * 8259 interrupt controller emulation
3  *
4  * Copyright (c) 2003-2004 Fabrice Bellard
5  * Copyright (c) 2007 Intel Corporation
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a copy
8  * of this software and associated documentation files (the "Software"), to deal
9  * in the Software without restriction, including without limitation the rights
10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11  * copies of the Software, and to permit persons to whom the Software is
12  * furnished to do so, subject to the following conditions:
13  *
14  * The above copyright notice and this permission notice shall be included in
15  * all copies or substantial portions of the Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23  * THE SOFTWARE.
24  * Authors:
25  *   Yaozu (Eddie) Dong <Eddie.dong@intel.com>
26  *   Port from Qemu.
27  */
28 #include <linux/mm.h>
29 #include "irq.h"
30
31 #include <linux/kvm_host.h>
32
33 static void pic_clear_isr(struct kvm_kpic_state *s, int irq)
34 {
35         s->isr &= ~(1 << irq);
36 }
37
38 /*
39  * set irq level. If an edge is detected, then the IRR is set to 1
40  */
41 static inline void pic_set_irq1(struct kvm_kpic_state *s, int irq, int level)
42 {
43         int mask;
44         mask = 1 << irq;
45         if (s->elcr & mask)     /* level triggered */
46                 if (level) {
47                         s->irr |= mask;
48                         s->last_irr |= mask;
49                 } else {
50                         s->irr &= ~mask;
51                         s->last_irr &= ~mask;
52                 }
53         else    /* edge triggered */
54                 if (level) {
55                         if ((s->last_irr & mask) == 0)
56                                 s->irr |= mask;
57                         s->last_irr |= mask;
58                 } else
59                         s->last_irr &= ~mask;
60 }
61
62 /*
63  * return the highest priority found in mask (highest = smallest
64  * number). Return 8 if no irq
65  */
66 static inline int get_priority(struct kvm_kpic_state *s, int mask)
67 {
68         int priority;
69         if (mask == 0)
70                 return 8;
71         priority = 0;
72         while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
73                 priority++;
74         return priority;
75 }
76
77 /*
78  * return the pic wanted interrupt. return -1 if none
79  */
80 static int pic_get_irq(struct kvm_kpic_state *s)
81 {
82         int mask, cur_priority, priority;
83
84         mask = s->irr & ~s->imr;
85         priority = get_priority(s, mask);
86         if (priority == 8)
87                 return -1;
88         /*
89          * compute current priority. If special fully nested mode on the
90          * master, the IRQ coming from the slave is not taken into account
91          * for the priority computation.
92          */
93         mask = s->isr;
94         if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
95                 mask &= ~(1 << 2);
96         cur_priority = get_priority(s, mask);
97         if (priority < cur_priority)
98                 /*
99                  * higher priority found: an irq should be generated
100                  */
101                 return (priority + s->priority_add) & 7;
102         else
103                 return -1;
104 }
105
106 /*
107  * raise irq to CPU if necessary. must be called every time the active
108  * irq may change
109  */
110 static void pic_update_irq(struct kvm_pic *s)
111 {
112         int irq2, irq;
113
114         irq2 = pic_get_irq(&s->pics[1]);
115         if (irq2 >= 0) {
116                 /*
117                  * if irq request by slave pic, signal master PIC
118                  */
119                 pic_set_irq1(&s->pics[0], 2, 1);
120                 pic_set_irq1(&s->pics[0], 2, 0);
121         }
122         irq = pic_get_irq(&s->pics[0]);
123         if (irq >= 0)
124                 s->irq_request(s->irq_request_opaque, 1);
125         else
126                 s->irq_request(s->irq_request_opaque, 0);
127 }
128
129 void kvm_pic_update_irq(struct kvm_pic *s)
130 {
131         pic_update_irq(s);
132 }
133
134 void kvm_pic_set_irq(void *opaque, int irq, int level)
135 {
136         struct kvm_pic *s = opaque;
137
138         if (irq >= 0 && irq < PIC_NUM_PINS) {
139                 pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
140                 pic_update_irq(s);
141         }
142 }
143
144 /*
145  * acknowledge interrupt 'irq'
146  */
147 static inline void pic_intack(struct kvm_kpic_state *s, int irq)
148 {
149         s->isr |= 1 << irq;
150         if (s->auto_eoi) {
151                 if (s->rotate_on_auto_eoi)
152                         s->priority_add = (irq + 1) & 7;
153                 pic_clear_isr(s, irq);
154         }
155         /*
156          * We don't clear a level sensitive interrupt here
157          */
158         if (!(s->elcr & (1 << irq)))
159                 s->irr &= ~(1 << irq);
160 }
161
162 int kvm_pic_read_irq(struct kvm *kvm)
163 {
164         int irq, irq2, intno;
165         struct kvm_pic *s = pic_irqchip(kvm);
166
167         irq = pic_get_irq(&s->pics[0]);
168         if (irq >= 0) {
169                 pic_intack(&s->pics[0], irq);
170                 if (irq == 2) {
171                         irq2 = pic_get_irq(&s->pics[1]);
172                         if (irq2 >= 0)
173                                 pic_intack(&s->pics[1], irq2);
174                         else
175                                 /*
176                                  * spurious IRQ on slave controller
177                                  */
178                                 irq2 = 7;
179                         intno = s->pics[1].irq_base + irq2;
180                         irq = irq2 + 8;
181                 } else
182                         intno = s->pics[0].irq_base + irq;
183         } else {
184                 /*
185                  * spurious IRQ on host controller
186                  */
187                 irq = 7;
188                 intno = s->pics[0].irq_base + irq;
189         }
190         pic_update_irq(s);
191         kvm_notify_acked_irq(kvm, irq);
192
193         return intno;
194 }
195
196 void kvm_pic_reset(struct kvm_kpic_state *s)
197 {
198         int irq;
199         struct kvm *kvm = s->pics_state->irq_request_opaque;
200
201         for (irq = 0; irq < PIC_NUM_PINS; irq++) {
202                 if (!(s->imr & (1 << irq)) && (s->irr & (1 << irq) ||
203                     s->isr & (1 << irq)))
204                         kvm_notify_acked_irq(kvm, irq);
205         }
206         s->last_irr = 0;
207         s->irr = 0;
208         s->imr = 0;
209         s->isr = 0;
210         s->priority_add = 0;
211         s->irq_base = 0;
212         s->read_reg_select = 0;
213         s->poll = 0;
214         s->special_mask = 0;
215         s->init_state = 0;
216         s->auto_eoi = 0;
217         s->rotate_on_auto_eoi = 0;
218         s->special_fully_nested_mode = 0;
219         s->init4 = 0;
220 }
221
222 static void pic_ioport_write(void *opaque, u32 addr, u32 val)
223 {
224         struct kvm_kpic_state *s = opaque;
225         int priority, cmd, irq;
226
227         addr &= 1;
228         if (addr == 0) {
229                 if (val & 0x10) {
230                         kvm_pic_reset(s);       /* init */
231                         /*
232                          * deassert a pending interrupt
233                          */
234                         s->pics_state->irq_request(s->pics_state->
235                                                    irq_request_opaque, 0);
236                         s->init_state = 1;
237                         s->init4 = val & 1;
238                         if (val & 0x02)
239                                 printk(KERN_ERR "single mode not supported");
240                         if (val & 0x08)
241                                 printk(KERN_ERR
242                                        "level sensitive irq not supported");
243                 } else if (val & 0x08) {
244                         if (val & 0x04)
245                                 s->poll = 1;
246                         if (val & 0x02)
247                                 s->read_reg_select = val & 1;
248                         if (val & 0x40)
249                                 s->special_mask = (val >> 5) & 1;
250                 } else {
251                         cmd = val >> 5;
252                         switch (cmd) {
253                         case 0:
254                         case 4:
255                                 s->rotate_on_auto_eoi = cmd >> 2;
256                                 break;
257                         case 1: /* end of interrupt */
258                         case 5:
259                                 priority = get_priority(s, s->isr);
260                                 if (priority != 8) {
261                                         irq = (priority + s->priority_add) & 7;
262                                         pic_clear_isr(s, irq);
263                                         if (cmd == 5)
264                                                 s->priority_add = (irq + 1) & 7;
265                                         pic_update_irq(s->pics_state);
266                                 }
267                                 break;
268                         case 3:
269                                 irq = val & 7;
270                                 pic_clear_isr(s, irq);
271                                 pic_update_irq(s->pics_state);
272                                 break;
273                         case 6:
274                                 s->priority_add = (val + 1) & 7;
275                                 pic_update_irq(s->pics_state);
276                                 break;
277                         case 7:
278                                 irq = val & 7;
279                                 s->priority_add = (irq + 1) & 7;
280                                 pic_clear_isr(s, irq);
281                                 pic_update_irq(s->pics_state);
282                                 break;
283                         default:
284                                 break;  /* no operation */
285                         }
286                 }
287         } else
288                 switch (s->init_state) {
289                 case 0:         /* normal mode */
290                         s->imr = val;
291                         pic_update_irq(s->pics_state);
292                         break;
293                 case 1:
294                         s->irq_base = val & 0xf8;
295                         s->init_state = 2;
296                         break;
297                 case 2:
298                         if (s->init4)
299                                 s->init_state = 3;
300                         else
301                                 s->init_state = 0;
302                         break;
303                 case 3:
304                         s->special_fully_nested_mode = (val >> 4) & 1;
305                         s->auto_eoi = (val >> 1) & 1;
306                         s->init_state = 0;
307                         break;
308                 }
309 }
310
311 static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1)
312 {
313         int ret;
314
315         ret = pic_get_irq(s);
316         if (ret >= 0) {
317                 if (addr1 >> 7) {
318                         s->pics_state->pics[0].isr &= ~(1 << 2);
319                         s->pics_state->pics[0].irr &= ~(1 << 2);
320                 }
321                 s->irr &= ~(1 << ret);
322                 pic_clear_isr(s, ret);
323                 if (addr1 >> 7 || ret != 2)
324                         pic_update_irq(s->pics_state);
325         } else {
326                 ret = 0x07;
327                 pic_update_irq(s->pics_state);
328         }
329
330         return ret;
331 }
332
333 static u32 pic_ioport_read(void *opaque, u32 addr1)
334 {
335         struct kvm_kpic_state *s = opaque;
336         unsigned int addr;
337         int ret;
338
339         addr = addr1;
340         addr &= 1;
341         if (s->poll) {
342                 ret = pic_poll_read(s, addr1);
343                 s->poll = 0;
344         } else
345                 if (addr == 0)
346                         if (s->read_reg_select)
347                                 ret = s->isr;
348                         else
349                                 ret = s->irr;
350                 else
351                         ret = s->imr;
352         return ret;
353 }
354
355 static void elcr_ioport_write(void *opaque, u32 addr, u32 val)
356 {
357         struct kvm_kpic_state *s = opaque;
358         s->elcr = val & s->elcr_mask;
359 }
360
361 static u32 elcr_ioport_read(void *opaque, u32 addr1)
362 {
363         struct kvm_kpic_state *s = opaque;
364         return s->elcr;
365 }
366
367 static int picdev_in_range(struct kvm_io_device *this, gpa_t addr,
368                            int len, int is_write)
369 {
370         switch (addr) {
371         case 0x20:
372         case 0x21:
373         case 0xa0:
374         case 0xa1:
375         case 0x4d0:
376         case 0x4d1:
377                 return 1;
378         default:
379                 return 0;
380         }
381 }
382
383 static void picdev_write(struct kvm_io_device *this,
384                          gpa_t addr, int len, const void *val)
385 {
386         struct kvm_pic *s = this->private;
387         unsigned char data = *(unsigned char *)val;
388
389         if (len != 1) {
390                 if (printk_ratelimit())
391                         printk(KERN_ERR "PIC: non byte write\n");
392                 return;
393         }
394         switch (addr) {
395         case 0x20:
396         case 0x21:
397         case 0xa0:
398         case 0xa1:
399                 pic_ioport_write(&s->pics[addr >> 7], addr, data);
400                 break;
401         case 0x4d0:
402         case 0x4d1:
403                 elcr_ioport_write(&s->pics[addr & 1], addr, data);
404                 break;
405         }
406 }
407
408 static void picdev_read(struct kvm_io_device *this,
409                         gpa_t addr, int len, void *val)
410 {
411         struct kvm_pic *s = this->private;
412         unsigned char data = 0;
413
414         if (len != 1) {
415                 if (printk_ratelimit())
416                         printk(KERN_ERR "PIC: non byte read\n");
417                 return;
418         }
419         switch (addr) {
420         case 0x20:
421         case 0x21:
422         case 0xa0:
423         case 0xa1:
424                 data = pic_ioport_read(&s->pics[addr >> 7], addr);
425                 break;
426         case 0x4d0:
427         case 0x4d1:
428                 data = elcr_ioport_read(&s->pics[addr & 1], addr);
429                 break;
430         }
431         *(unsigned char *)val = data;
432 }
433
434 /*
435  * callback when PIC0 irq status changed
436  */
437 static void pic_irq_request(void *opaque, int level)
438 {
439         struct kvm *kvm = opaque;
440         struct kvm_vcpu *vcpu = kvm->vcpus[0];
441
442         pic_irqchip(kvm)->output = level;
443         if (vcpu)
444                 kvm_vcpu_kick(vcpu);
445 }
446
447 struct kvm_pic *kvm_create_pic(struct kvm *kvm)
448 {
449         struct kvm_pic *s;
450         s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL);
451         if (!s)
452                 return NULL;
453         s->pics[0].elcr_mask = 0xf8;
454         s->pics[1].elcr_mask = 0xde;
455         s->irq_request = pic_irq_request;
456         s->irq_request_opaque = kvm;
457         s->pics[0].pics_state = s;
458         s->pics[1].pics_state = s;
459
460         /*
461          * Initialize PIO device
462          */
463         s->dev.read = picdev_read;
464         s->dev.write = picdev_write;
465         s->dev.in_range = picdev_in_range;
466         s->dev.private = s;
467         kvm_io_bus_register_dev(&kvm->pio_bus, &s->dev);
468         return s;
469 }